ARTICLES The River Runs Deep [The latter part] by Stillman Gates Gratitude to the author: In these pages, we run the original manuscript in English, then please understand that there are some differences from the contents of the magazine. This article is carried by authots' favor. Signal I/O Cell Variations Because PCI-X 2.0 defines three categories of I/O cells with different signal requirements, designers will likely need to review and modify their signal I/O cell designs. Category 1 I/O Cells Used for signals that operate in both synchronous data transfer mode and common CLK data transfer mode (AD, ECC and C/BE#). Two versions of a category 1 I/O receive section 1 cell are shown in Figures 1(a) and (b). Only one version could be developed but having two versions appears to have an advantage. Figure 2(a) depicts a category 1 I/O receive section 2 cell design. In Figure 2(a), S1-S8 comprise two circular shift registers which generate clocks for the associated Ln and Rn bit values. The upper block is clocked by STBF and the lower by STBS. H1 stores the received data back in common clock mode. The white and grey Rn bits operate in a ping-pong fashion. The gray blocks are not used when only DDR is supported. Figure 2(b) depicts the required timing for the category 1 I/O receive section 2 cell. Note that the specification allows an additional clock for the action provided by Figure 2 to enable variations of the receive section. [Figure 1] Category 1 I/O receive section 1 cell disign [Figure 2] Category 1 I/O receive section 2 cell design (a) Category 1 Receive Section 2 Design (3) (b)Category 1 Receive Section 2 Timing (3) To ARTICLE Top page Next>> To DESIGN WAVE MAGAZINE's Homepage (English) To CQ Publishing's Homepage (Japanese) Copyright(C) 1996-2002 CQ Publishing Co., Ltd.