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The River Runs Deep [The latter part] |
New power connection cells are also required to support category 1-3 cell designs for the new power requirements of the die power rings.
Some designs may need to provide a comparitor cell connected between VIO and 3.3V that indicates the voltage level of VIO to the I/O cells for the operation differences.
Category 1 Mode 2 data transfer signals now require termination at the receiver. Terminators can either be internal to the PCI device package or external. The driver cell design depends on your choice. Figure 5(a) illustrates a design with internal termination that should be implemented as a hard macro in close proximity to the pin. Figure 5(b) illustrates a design with external termination.
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(a) Category 1 Driver With Internal Termination (4)
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(b) Category 1 Driver With External Termination
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Figure 5(a) illustrates an internal terminator design. Category 1 I/O cells operate at the PCI CLK frequency and also at 2X or 4X the PCI CLK frequency. Four driver section "points" are provided in a category 1 I/O cell with internal VTERM generation from the die VIO power ring. It is expected that the three depicted resistors are tuned for driver operations.
The first (top) driver section is the same as the category 2 I/O cell and is used when the bus operates in PCI, PCI-X 1.0 or PCI-X 2.0 mode 1. In these modes the VIO value is 3.3V.
The second, third and fourth driver sections are used when the bus mode is PCI-X 2.0 mode 2. In this mode the VIO value is 1.5V.
Mode 2 I/O cells operate in the following I/O states:
- Low power state (driver disabled, terminator disabled, receiver disabled)
- Blind state (driver disabled, terminator enabled receiver disabled)
- Receive state (driver disabled, terminator enabled, receiver enabled)
- Drive state (driver enabled, terminator disabled, receiver disabled)
The receive and drive states may be selected for common CLK data transfers or synchronous data transfers. Synchronous data transfer is used for Memory Write Block, Split Completion and Device ID Message data transfers. The three registers with inputs M2IO_A,_B,_C control the cell I/O state selection.
For the blind and receive states, the second and third driver sections are enabled to provide internal receiver termination. When termination is enabled, the second driver is enabled to pull up and the third driver is enabled to pull down to represent a split terminator providing a VTERM value of VIO/2 for the receiver. The receiver section is discussed elsewhere. Connections C0, M2IO_RD and M2IO_CQ are used by receive sections 1 and 2.
For the drive state, the second, third and fourth driver sections are enabled to drive in parallel with the same data value. The output driver section impedances combine to represent the correct impedance for the category 1 mode 2 driver output.
The register with the M2IO_C input selects either common clock data or synchronous data transfers for output data when in the drive state. Synchronous data, SDO, is clocked with M2SCLK, which is 2X or 4X the rate of common clock depending on the bus mode (DDR or QDR). Common clock data CDO is clocked with the common clock CCLK.
Figure 5(b) illustrates a Category 1 driver with an external termination design. Again, category 1 I/O cells operate at the PCI CLK frequency and also at 2X or 4X the PCI CLK frequency.
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