# Static Timing Analysis

Project : | Switch_LED
Build Time : | 04/12/12 22:58:46
Device : | CY8C3866LTI-030
Temperature : | -40C - 85C
Vio0 : | 5.0
Vio1 : | 5.0
Vio2 : | 5.0
Vio3 : | 5.0
Voltage : | 5.0

Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Type | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
ClockBlock/clk_bus | Async | 24.000 MHz | 24.000 MHz | N/A |
CyBUS_CLK | Sync | 24.000 MHz | 24.000 MHz | N/A |
CyILO | Async | 1.000 kHz | 1.000 kHz | N/A |
CyIMO | Async | 3.000 MHz | 3.000 MHz | N/A |
CyMASTER_CLK | Sync | 24.000 MHz | 24.000 MHz | N/A |
CyPLL_OUT | Async | 24.000 MHz | 24.000 MHz | N/A |

+ Clock To Output Section
+ CyBUS_CLK

Source | Destination | Delay (ns)
--- | --- | ---
SWInput(0)/fb | LEDOut(0)_PAD | 25.019
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell_ireg | P2[0] | 1 | SWInput(0) | SWInput(0)/clock | SWInput(0)/fb | 6.160
Route |  | 1 | Net_38 | SWInput(0)/fb | LEDOut(0)/pin_input | 2.659
iocell | P2[7] | 1 | LEDOut(0) | LEDOut(0)/pin_input | LEDOut(0)/pad_out | 16.200
Route |  | 1 | LEDOut(0)_PAD | LEDOut(0)/pad_out | LEDOut(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000