/*******************************************************************************
* FILENAME: cydevice_trm.h
* 
* PSoC Creator 2.0 Component Pack 1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
*
********************************************************************************
* Copyright 2008-2011, Cypress Semiconductor Corporation.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#if !defined(CYDEVICE_TRM_H)
#define CYDEVICE_TRM_H
#include <cytypes.h>
#define CYDEV_SRAM_BASE 0x00000000u
#define CYDEV_SRAM_SIZE 0x00002000u
#define CYDEV_SRAM_MAP_BASE 0x00000000u
#define CYDEV_SRAM_MAP_SIZE 0x00003000u
#define CYDEV_SRAM_MAP_SYSMEM0_BASE 0x00000000u
#define CYDEV_SRAM_MAP_SYSMEM0_SIZE 0x00001000u
#define CYREG_SRAM_MAP_SYSMEM0_DATA_MBASE 0x00000000u
#define CYREG_SRAM_MAP_SYSMEM0_DATA_MSIZE 0x00001000u
#define CYDEV_SRAM_MAP_SYSMEM1_BASE 0x00001000u
#define CYDEV_SRAM_MAP_SYSMEM1_SIZE 0x00001000u
#define CYREG_SRAM_MAP_SYSMEM1_DATA_MBASE 0x00001000u
#define CYREG_SRAM_MAP_SYSMEM1_DATA_MSIZE 0x00001000u
#define CYDEV_SRAM_MAP_TRACEMEM_BASE 0x00002000u
#define CYDEV_SRAM_MAP_TRACEMEM_SIZE 0x00001000u
#define CYREG_SRAM_MAP_TRACEMEM_DATA_MBASE 0x00002000u
#define CYREG_SRAM_MAP_TRACEMEM_DATA_MSIZE 0x00001000u
#define CYDEV_CLKDIST_BASE 0x00004000u
#define CYDEV_CLKDIST_SIZE 0x00000110u
#define CYREG_CLKDIST_CR 0x00004000u
#define CYREG_CLKDIST_LD 0x00004001u
#define CYREG_CLKDIST_WRK0 0x00004002u
#define CYREG_CLKDIST_WRK1 0x00004003u
#define CYREG_CLKDIST_MSTR0 0x00004004u
#define CYREG_CLKDIST_MSTR1 0x00004005u
#define CYREG_CLKDIST_BCFG0 0x00004006u
#define CYREG_CLKDIST_BCFG1 0x00004007u
#define CYREG_CLKDIST_BCFG2 0x00004008u
#define CYREG_CLKDIST_UCFG 0x00004009u
#define CYREG_CLKDIST_DLY0 0x0000400au
#define CYREG_CLKDIST_DLY1 0x0000400bu
#define CYREG_CLKDIST_DMASK 0x00004010u
#define CYREG_CLKDIST_AMASK 0x00004014u
#define CYDEV_CLKDIST_DCFG0_BASE 0x00004080u
#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u
#define CYREG_CLKDIST_DCFG0_CFG0 0x00004080u
#define CYREG_CLKDIST_DCFG0_CFG1 0x00004081u
#define CYREG_CLKDIST_DCFG0_CFG2 0x00004082u
#define CYDEV_CLKDIST_DCFG1_BASE 0x00004084u
#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u
#define CYREG_CLKDIST_DCFG1_CFG0 0x00004084u
#define CYREG_CLKDIST_DCFG1_CFG1 0x00004085u
#define CYREG_CLKDIST_DCFG1_CFG2 0x00004086u
#define CYDEV_CLKDIST_DCFG2_BASE 0x00004088u
#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u
#define CYREG_CLKDIST_DCFG2_CFG0 0x00004088u
#define CYREG_CLKDIST_DCFG2_CFG1 0x00004089u
#define CYREG_CLKDIST_DCFG2_CFG2 0x0000408au
#define CYDEV_CLKDIST_DCFG3_BASE 0x0000408cu
#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u
#define CYREG_CLKDIST_DCFG3_CFG0 0x0000408cu
#define CYREG_CLKDIST_DCFG3_CFG1 0x0000408du
#define CYREG_CLKDIST_DCFG3_CFG2 0x0000408eu
#define CYDEV_CLKDIST_DCFG4_BASE 0x00004090u
#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u
#define CYREG_CLKDIST_DCFG4_CFG0 0x00004090u
#define CYREG_CLKDIST_DCFG4_CFG1 0x00004091u
#define CYREG_CLKDIST_DCFG4_CFG2 0x00004092u
#define CYDEV_CLKDIST_DCFG5_BASE 0x00004094u
#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u
#define CYREG_CLKDIST_DCFG5_CFG0 0x00004094u
#define CYREG_CLKDIST_DCFG5_CFG1 0x00004095u
#define CYREG_CLKDIST_DCFG5_CFG2 0x00004096u
#define CYDEV_CLKDIST_DCFG6_BASE 0x00004098u
#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u
#define CYREG_CLKDIST_DCFG6_CFG0 0x00004098u
#define CYREG_CLKDIST_DCFG6_CFG1 0x00004099u
#define CYREG_CLKDIST_DCFG6_CFG2 0x0000409au
#define CYDEV_CLKDIST_DCFG7_BASE 0x0000409cu
#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u
#define CYREG_CLKDIST_DCFG7_CFG0 0x0000409cu
#define CYREG_CLKDIST_DCFG7_CFG1 0x0000409du
#define CYREG_CLKDIST_DCFG7_CFG2 0x0000409eu
#define CYDEV_CLKDIST_ACFG0_BASE 0x00004100u
#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u
#define CYREG_CLKDIST_ACFG0_CFG0 0x00004100u
#define CYREG_CLKDIST_ACFG0_CFG1 0x00004101u
#define CYREG_CLKDIST_ACFG0_CFG2 0x00004102u
#define CYREG_CLKDIST_ACFG0_CFG3 0x00004103u
#define CYDEV_CLKDIST_ACFG1_BASE 0x00004104u
#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u
#define CYREG_CLKDIST_ACFG1_CFG0 0x00004104u
#define CYREG_CLKDIST_ACFG1_CFG1 0x00004105u
#define CYREG_CLKDIST_ACFG1_CFG2 0x00004106u
#define CYREG_CLKDIST_ACFG1_CFG3 0x00004107u
#define CYDEV_CLKDIST_ACFG2_BASE 0x00004108u
#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u
#define CYREG_CLKDIST_ACFG2_CFG0 0x00004108u
#define CYREG_CLKDIST_ACFG2_CFG1 0x00004109u
#define CYREG_CLKDIST_ACFG2_CFG2 0x0000410au
#define CYREG_CLKDIST_ACFG2_CFG3 0x0000410bu
#define CYDEV_CLKDIST_ACFG3_BASE 0x0000410cu
#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u
#define CYREG_CLKDIST_ACFG3_CFG0 0x0000410cu
#define CYREG_CLKDIST_ACFG3_CFG1 0x0000410du
#define CYREG_CLKDIST_ACFG3_CFG2 0x0000410eu
#define CYREG_CLKDIST_ACFG3_CFG3 0x0000410fu
#define CYDEV_FASTCLK_BASE 0x00004200u
#define CYDEV_FASTCLK_SIZE 0x00000026u
#define CYDEV_FASTCLK_IMO_BASE 0x00004200u
#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u
#define CYREG_FASTCLK_IMO_CR 0x00004200u
#define CYDEV_FASTCLK_XMHZ_BASE 0x00004210u
#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u
#define CYREG_FASTCLK_XMHZ_CSR 0x00004210u
#define CYREG_FASTCLK_XMHZ_TST 0x00004211u
#define CYREG_FASTCLK_XMHZ_CFG0 0x00004212u
#define CYREG_FASTCLK_XMHZ_CFG1 0x00004213u
#define CYDEV_FASTCLK_PLL_BASE 0x00004220u
#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u
#define CYREG_FASTCLK_PLL_CFG0 0x00004220u
#define CYREG_FASTCLK_PLL_CFG1 0x00004221u
#define CYREG_FASTCLK_PLL_P 0x00004222u
#define CYREG_FASTCLK_PLL_Q 0x00004223u
#define CYREG_FASTCLK_PLL_TST 0x00004224u
#define CYREG_FASTCLK_PLL_SR 0x00004225u
#define CYDEV_SLOWCLK_BASE 0x00004300u
#define CYDEV_SLOWCLK_SIZE 0x0000000bu
#define CYDEV_SLOWCLK_ILO_BASE 0x00004300u
#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u
#define CYREG_SLOWCLK_ILO_CR0 0x00004300u
#define CYREG_SLOWCLK_ILO_CR1 0x00004301u
#define CYDEV_SLOWCLK_X32_BASE 0x00004308u
#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u
#define CYREG_SLOWCLK_X32_CR 0x00004308u
#define CYREG_SLOWCLK_X32_CFG 0x00004309u
#define CYREG_SLOWCLK_X32_TST 0x0000430au
#define CYDEV_BOOST_BASE 0x00004320u
#define CYDEV_BOOST_SIZE 0x00000007u
#define CYREG_BOOST_CR0 0x00004320u
#define CYREG_BOOST_CR1 0x00004321u
#define CYREG_BOOST_CR2 0x00004322u
#define CYREG_BOOST_CR3 0x00004323u
#define CYREG_BOOST_SR 0x00004324u
#define CYREG_BOOST_CR4 0x00004325u
#define CYREG_BOOST_SR2 0x00004326u
#define CYDEV_PWRSYS_BASE 0x00004330u
#define CYDEV_PWRSYS_SIZE 0x00000002u
#define CYREG_PWRSYS_CR0 0x00004330u
#define CYREG_PWRSYS_CR1 0x00004331u
#define CYDEV_PM_BASE 0x00004380u
#define CYDEV_PM_SIZE 0x00000057u
#define CYREG_PM_TW_CFG0 0x00004380u
#define CYREG_PM_TW_CFG1 0x00004381u
#define CYREG_PM_TW_CFG2 0x00004382u
#define CYREG_PM_WDT_CFG 0x00004383u
#define CYREG_PM_WDT_CR 0x00004384u
#define CYREG_PM_INT_SR 0x00004390u
#define CYREG_PM_MODE_CFG0 0x00004391u
#define CYREG_PM_MODE_CFG1 0x00004392u
#define CYREG_PM_MODE_CSR 0x00004393u
#define CYREG_PM_USB_CR0 0x00004394u
#define CYREG_PM_WAKEUP_CFG0 0x00004398u
#define CYREG_PM_WAKEUP_CFG1 0x00004399u
#define CYREG_PM_WAKEUP_CFG2 0x0000439au
#define CYDEV_PM_ACT_BASE 0x000043a0u
#define CYDEV_PM_ACT_SIZE 0x0000000eu
#define CYREG_PM_ACT_CFG0 0x000043a0u
#define CYREG_PM_ACT_CFG1 0x000043a1u
#define CYREG_PM_ACT_CFG2 0x000043a2u
#define CYREG_PM_ACT_CFG3 0x000043a3u
#define CYREG_PM_ACT_CFG4 0x000043a4u
#define CYREG_PM_ACT_CFG5 0x000043a5u
#define CYREG_PM_ACT_CFG6 0x000043a6u
#define CYREG_PM_ACT_CFG7 0x000043a7u
#define CYREG_PM_ACT_CFG8 0x000043a8u
#define CYREG_PM_ACT_CFG9 0x000043a9u
#define CYREG_PM_ACT_CFG10 0x000043aau
#define CYREG_PM_ACT_CFG11 0x000043abu
#define CYREG_PM_ACT_CFG12 0x000043acu
#define CYREG_PM_ACT_CFG13 0x000043adu
#define CYDEV_PM_STBY_BASE 0x000043b0u
#define CYDEV_PM_STBY_SIZE 0x0000000eu
#define CYREG_PM_STBY_CFG0 0x000043b0u
#define CYREG_PM_STBY_CFG1 0x000043b1u
#define CYREG_PM_STBY_CFG2 0x000043b2u
#define CYREG_PM_STBY_CFG3 0x000043b3u
#define CYREG_PM_STBY_CFG4 0x000043b4u
#define CYREG_PM_STBY_CFG5 0x000043b5u
#define CYREG_PM_STBY_CFG6 0x000043b6u
#define CYREG_PM_STBY_CFG7 0x000043b7u
#define CYREG_PM_STBY_CFG8 0x000043b8u
#define CYREG_PM_STBY_CFG9 0x000043b9u
#define CYREG_PM_STBY_CFG10 0x000043bau
#define CYREG_PM_STBY_CFG11 0x000043bbu
#define CYREG_PM_STBY_CFG12 0x000043bcu
#define CYREG_PM_STBY_CFG13 0x000043bdu
#define CYDEV_PM_AVAIL_BASE 0x000043c0u
#define CYDEV_PM_AVAIL_SIZE 0x00000017u
#define CYREG_PM_AVAIL_CR0 0x000043c0u
#define CYREG_PM_AVAIL_CR1 0x000043c1u
#define CYREG_PM_AVAIL_CR2 0x000043c2u
#define CYREG_PM_AVAIL_CR3 0x000043c3u
#define CYREG_PM_AVAIL_CR4 0x000043c4u
#define CYREG_PM_AVAIL_CR5 0x000043c5u
#define CYREG_PM_AVAIL_CR6 0x000043c6u
#define CYREG_PM_AVAIL_SR0 0x000043d0u
#define CYREG_PM_AVAIL_SR1 0x000043d1u
#define CYREG_PM_AVAIL_SR2 0x000043d2u
#define CYREG_PM_AVAIL_SR3 0x000043d3u
#define CYREG_PM_AVAIL_SR4 0x000043d4u
#define CYREG_PM_AVAIL_SR5 0x000043d5u
#define CYREG_PM_AVAIL_SR6 0x000043d6u
#define CYDEV_INTC_BASE 0x00004400u
#define CYDEV_INTC_SIZE 0x000000f6u
#define CYREG_INTC_VECT_MBASE 0x00004400u
#define CYREG_INTC_VECT_MSIZE 0x00000040u
#define CYREG_INTC_PRIOR0 0x00004480u
#define CYREG_INTC_PRIOR1 0x00004481u
#define CYREG_INTC_PRIOR2 0x00004482u
#define CYREG_INTC_PRIOR3 0x00004483u
#define CYREG_INTC_PRIOR4 0x00004484u
#define CYREG_INTC_PRIOR5 0x00004485u
#define CYREG_INTC_PRIOR6 0x00004486u
#define CYREG_INTC_PRIOR7 0x00004487u
#define CYREG_INTC_PRIOR8 0x00004488u
#define CYREG_INTC_PRIOR9 0x00004489u
#define CYREG_INTC_PRIOR10 0x0000448au
#define CYREG_INTC_PRIOR11 0x0000448bu
#define CYREG_INTC_PRIOR12 0x0000448cu
#define CYREG_INTC_PRIOR13 0x0000448du
#define CYREG_INTC_PRIOR14 0x0000448eu
#define CYREG_INTC_PRIOR15 0x0000448fu
#define CYREG_INTC_PRIOR16 0x00004490u
#define CYREG_INTC_PRIOR17 0x00004491u
#define CYREG_INTC_PRIOR18 0x00004492u
#define CYREG_INTC_PRIOR19 0x00004493u
#define CYREG_INTC_PRIOR20 0x00004494u
#define CYREG_INTC_PRIOR21 0x00004495u
#define CYREG_INTC_PRIOR22 0x00004496u
#define CYREG_INTC_PRIOR23 0x00004497u
#define CYREG_INTC_PRIOR24 0x00004498u
#define CYREG_INTC_PRIOR25 0x00004499u
#define CYREG_INTC_PRIOR26 0x0000449au
#define CYREG_INTC_PRIOR27 0x0000449bu
#define CYREG_INTC_PRIOR28 0x0000449cu
#define CYREG_INTC_PRIOR29 0x0000449du
#define CYREG_INTC_PRIOR30 0x0000449eu
#define CYREG_INTC_PRIOR31 0x0000449fu
#define CYREG_INTC_SET_EN0 0x000044c0u
#define CYREG_INTC_SET_EN1 0x000044c1u
#define CYREG_INTC_SET_EN2 0x000044c2u
#define CYREG_INTC_SET_EN3 0x000044c3u
#define CYREG_INTC_CLR_EN0 0x000044c8u
#define CYREG_INTC_CLR_EN1 0x000044c9u
#define CYREG_INTC_CLR_EN2 0x000044cau
#define CYREG_INTC_CLR_EN3 0x000044cbu
#define CYREG_INTC_SET_PD0 0x000044d0u
#define CYREG_INTC_SET_PD1 0x000044d1u
#define CYREG_INTC_SET_PD2 0x000044d2u
#define CYREG_INTC_SET_PD3 0x000044d3u
#define CYREG_INTC_CLR_PD0 0x000044d8u
#define CYREG_INTC_CLR_PD1 0x000044d9u
#define CYREG_INTC_CLR_PD2 0x000044dau
#define CYREG_INTC_CLR_PD3 0x000044dbu
#define CYREG_INTC_STK_TOP 0x000044e0u
#define CYREG_INTC_STK1 0x000044e1u
#define CYREG_INTC_STK2 0x000044e2u
#define CYREG_INTC_STK3 0x000044e3u
#define CYREG_INTC_STK4 0x000044e4u
#define CYREG_INTC_STK5 0x000044e5u
#define CYREG_INTC_STK6 0x000044e6u
#define CYREG_INTC_STK7 0x000044e7u
#define CYREG_INTC_STK_INT_NUM0 0x000044e8u
#define CYREG_INTC_STK_INT_NUM1 0x000044e9u
#define CYREG_INTC_STK_INT_NUM2 0x000044eau
#define CYREG_INTC_STK_INT_NUM3 0x000044ebu
#define CYREG_INTC_STK_INT_NUM4 0x000044ecu
#define CYREG_INTC_STK_INT_NUM5 0x000044edu
#define CYREG_INTC_STK_INT_NUM6 0x000044eeu
#define CYREG_INTC_STK_INT_NUM7 0x000044efu
#define CYREG_INTC_NUM_LINES 0x000044f0u
#define CYREG_INTC_ACT_INT_NUM 0x000044f1u
#define CYREG_INTC_ACT_VECT 0x000044f2u
#define CYREG_INTC_CSR_EN 0x000044f4u
#define CYDEV_PICU_BASE 0x00004500u
#define CYDEV_PICU_SIZE 0x000000b0u
#define CYDEV_PICU_INTTYPE_BASE 0x00004500u
#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u
#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x00004500u
#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u
#define CYREG_PICU0_INTTYPE0 0x00004500u
#define CYREG_PICU0_INTTYPE1 0x00004501u
#define CYREG_PICU0_INTTYPE2 0x00004502u
#define CYREG_PICU0_INTTYPE3 0x00004503u
#define CYREG_PICU0_INTTYPE4 0x00004504u
#define CYREG_PICU0_INTTYPE5 0x00004505u
#define CYREG_PICU0_INTTYPE6 0x00004506u
#define CYREG_PICU0_INTTYPE7 0x00004507u
#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x00004508u
#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u
#define CYREG_PICU1_INTTYPE0 0x00004508u
#define CYREG_PICU1_INTTYPE1 0x00004509u
#define CYREG_PICU1_INTTYPE2 0x0000450au
#define CYREG_PICU1_INTTYPE3 0x0000450bu
#define CYREG_PICU1_INTTYPE4 0x0000450cu
#define CYREG_PICU1_INTTYPE5 0x0000450du
#define CYREG_PICU1_INTTYPE6 0x0000450eu
#define CYREG_PICU1_INTTYPE7 0x0000450fu
#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x00004510u
#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u
#define CYREG_PICU2_INTTYPE0 0x00004510u
#define CYREG_PICU2_INTTYPE1 0x00004511u
#define CYREG_PICU2_INTTYPE2 0x00004512u
#define CYREG_PICU2_INTTYPE3 0x00004513u
#define CYREG_PICU2_INTTYPE4 0x00004514u
#define CYREG_PICU2_INTTYPE5 0x00004515u
#define CYREG_PICU2_INTTYPE6 0x00004516u
#define CYREG_PICU2_INTTYPE7 0x00004517u
#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x00004518u
#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u
#define CYREG_PICU3_INTTYPE0 0x00004518u
#define CYREG_PICU3_INTTYPE1 0x00004519u
#define CYREG_PICU3_INTTYPE2 0x0000451au
#define CYREG_PICU3_INTTYPE3 0x0000451bu
#define CYREG_PICU3_INTTYPE4 0x0000451cu
#define CYREG_PICU3_INTTYPE5 0x0000451du
#define CYREG_PICU3_INTTYPE6 0x0000451eu
#define CYREG_PICU3_INTTYPE7 0x0000451fu
#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x00004520u
#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u
#define CYREG_PICU4_INTTYPE0 0x00004520u
#define CYREG_PICU4_INTTYPE1 0x00004521u
#define CYREG_PICU4_INTTYPE2 0x00004522u
#define CYREG_PICU4_INTTYPE3 0x00004523u
#define CYREG_PICU4_INTTYPE4 0x00004524u
#define CYREG_PICU4_INTTYPE5 0x00004525u
#define CYREG_PICU4_INTTYPE6 0x00004526u
#define CYREG_PICU4_INTTYPE7 0x00004527u
#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x00004528u
#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u
#define CYREG_PICU5_INTTYPE0 0x00004528u
#define CYREG_PICU5_INTTYPE1 0x00004529u
#define CYREG_PICU5_INTTYPE2 0x0000452au
#define CYREG_PICU5_INTTYPE3 0x0000452bu
#define CYREG_PICU5_INTTYPE4 0x0000452cu
#define CYREG_PICU5_INTTYPE5 0x0000452du
#define CYREG_PICU5_INTTYPE6 0x0000452eu
#define CYREG_PICU5_INTTYPE7 0x0000452fu
#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x00004530u
#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u
#define CYREG_PICU6_INTTYPE0 0x00004530u
#define CYREG_PICU6_INTTYPE1 0x00004531u
#define CYREG_PICU6_INTTYPE2 0x00004532u
#define CYREG_PICU6_INTTYPE3 0x00004533u
#define CYREG_PICU6_INTTYPE4 0x00004534u
#define CYREG_PICU6_INTTYPE5 0x00004535u
#define CYREG_PICU6_INTTYPE6 0x00004536u
#define CYREG_PICU6_INTTYPE7 0x00004537u
#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x00004560u
#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u
#define CYREG_PICU12_INTTYPE0 0x00004560u
#define CYREG_PICU12_INTTYPE1 0x00004561u
#define CYREG_PICU12_INTTYPE2 0x00004562u
#define CYREG_PICU12_INTTYPE3 0x00004563u
#define CYREG_PICU12_INTTYPE4 0x00004564u
#define CYREG_PICU12_INTTYPE5 0x00004565u
#define CYREG_PICU12_INTTYPE6 0x00004566u
#define CYREG_PICU12_INTTYPE7 0x00004567u
#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x00004578u
#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u
#define CYREG_PICU15_INTTYPE0 0x00004578u
#define CYREG_PICU15_INTTYPE1 0x00004579u
#define CYREG_PICU15_INTTYPE2 0x0000457au
#define CYREG_PICU15_INTTYPE3 0x0000457bu
#define CYREG_PICU15_INTTYPE4 0x0000457cu
#define CYREG_PICU15_INTTYPE5 0x0000457du
#define CYREG_PICU15_INTTYPE6 0x0000457eu
#define CYREG_PICU15_INTTYPE7 0x0000457fu
#define CYDEV_PICU_STAT_BASE 0x00004580u
#define CYDEV_PICU_STAT_SIZE 0x00000010u
#define CYDEV_PICU_STAT_PICU0_BASE 0x00004580u
#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u
#define CYREG_PICU0_INTSTAT 0x00004580u
#define CYDEV_PICU_STAT_PICU1_BASE 0x00004581u
#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u
#define CYREG_PICU1_INTSTAT 0x00004581u
#define CYDEV_PICU_STAT_PICU2_BASE 0x00004582u
#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u
#define CYREG_PICU2_INTSTAT 0x00004582u
#define CYDEV_PICU_STAT_PICU3_BASE 0x00004583u
#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u
#define CYREG_PICU3_INTSTAT 0x00004583u
#define CYDEV_PICU_STAT_PICU4_BASE 0x00004584u
#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u
#define CYREG_PICU4_INTSTAT 0x00004584u
#define CYDEV_PICU_STAT_PICU5_BASE 0x00004585u
#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u
#define CYREG_PICU5_INTSTAT 0x00004585u
#define CYDEV_PICU_STAT_PICU6_BASE 0x00004586u
#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u
#define CYREG_PICU6_INTSTAT 0x00004586u
#define CYDEV_PICU_STAT_PICU12_BASE 0x0000458cu
#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u
#define CYREG_PICU12_INTSTAT 0x0000458cu
#define CYDEV_PICU_STAT_PICU15_BASE 0x0000458fu
#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u
#define CYREG_PICU15_INTSTAT 0x0000458fu
#define CYDEV_PICU_SNAP_BASE 0x00004590u
#define CYDEV_PICU_SNAP_SIZE 0x00000010u
#define CYDEV_PICU_SNAP_PICU0_BASE 0x00004590u
#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u
#define CYREG_PICU0_SNAP 0x00004590u
#define CYDEV_PICU_SNAP_PICU1_BASE 0x00004591u
#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u
#define CYREG_PICU1_SNAP 0x00004591u
#define CYDEV_PICU_SNAP_PICU2_BASE 0x00004592u
#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u
#define CYREG_PICU2_SNAP 0x00004592u
#define CYDEV_PICU_SNAP_PICU3_BASE 0x00004593u
#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u
#define CYREG_PICU3_SNAP 0x00004593u
#define CYDEV_PICU_SNAP_PICU4_BASE 0x00004594u
#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u
#define CYREG_PICU4_SNAP 0x00004594u
#define CYDEV_PICU_SNAP_PICU5_BASE 0x00004595u
#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u
#define CYREG_PICU5_SNAP 0x00004595u
#define CYDEV_PICU_SNAP_PICU6_BASE 0x00004596u
#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u
#define CYREG_PICU6_SNAP 0x00004596u
#define CYDEV_PICU_SNAP_PICU12_BASE 0x0000459cu
#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u
#define CYREG_PICU12_SNAP 0x0000459cu
#define CYDEV_PICU_SNAP_PICU15_BASE 0x0000459fu
#define CYDEV_PICU_SNAP_PICU15_SIZE 0x00000001u
#define CYREG_PICU15_SNAP 0x0000459fu
#define CYDEV_PICU_DISABLE_COR_BASE 0x000045a0u
#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u
#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x000045a0u
#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u
#define CYREG_PICU0_DISABLE_COR 0x000045a0u
#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x000045a1u
#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u
#define CYREG_PICU1_DISABLE_COR 0x000045a1u
#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x000045a2u
#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u
#define CYREG_PICU2_DISABLE_COR 0x000045a2u
#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x000045a3u
#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u
#define CYREG_PICU3_DISABLE_COR 0x000045a3u
#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x000045a4u
#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u
#define CYREG_PICU4_DISABLE_COR 0x000045a4u
#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x000045a5u
#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u
#define CYREG_PICU5_DISABLE_COR 0x000045a5u
#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x000045a6u
#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u
#define CYREG_PICU6_DISABLE_COR 0x000045a6u
#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x000045acu
#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u
#define CYREG_PICU12_DISABLE_COR 0x000045acu
#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x000045afu
#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u
#define CYREG_PICU15_DISABLE_COR 0x000045afu
#define CYDEV_MFGCFG_BASE 0x00004600u
#define CYDEV_MFGCFG_SIZE 0x000000edu
#define CYDEV_MFGCFG_ANAIF_BASE 0x00004600u
#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u
#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x00004608u
#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u
#define CYREG_DAC0_TR 0x00004608u
#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x00004609u
#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u
#define CYREG_DAC1_TR 0x00004609u
#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x0000460au
#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u
#define CYREG_DAC2_TR 0x0000460au
#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x0000460bu
#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u
#define CYREG_DAC3_TR 0x0000460bu
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x00004610u
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u
#define CYREG_NPUMP_DSM_TR0 0x00004610u
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x00004611u
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u
#define CYREG_NPUMP_SC_TR0 0x00004611u
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x00004612u
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u
#define CYREG_NPUMP_OPAMP_TR0 0x00004612u
#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x00004620u
#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u
#define CYREG_OPAMP0_TR0 0x00004620u
#define CYREG_OPAMP0_TR1 0x00004621u
#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x00004622u
#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u
#define CYREG_OPAMP1_TR0 0x00004622u
#define CYREG_OPAMP1_TR1 0x00004623u
#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x00004624u
#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u
#define CYREG_OPAMP2_TR0 0x00004624u
#define CYREG_OPAMP2_TR1 0x00004625u
#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x00004626u
#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u
#define CYREG_OPAMP3_TR0 0x00004626u
#define CYREG_OPAMP3_TR1 0x00004627u
#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x00004630u
#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u
#define CYREG_CMP0_TR0 0x00004630u
#define CYREG_CMP0_TR1 0x00004631u
#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x00004632u
#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u
#define CYREG_CMP1_TR0 0x00004632u
#define CYREG_CMP1_TR1 0x00004633u
#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x00004634u
#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u
#define CYREG_CMP2_TR0 0x00004634u
#define CYREG_CMP2_TR1 0x00004635u
#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x00004636u
#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u
#define CYREG_CMP3_TR0 0x00004636u
#define CYREG_CMP3_TR1 0x00004637u
#define CYDEV_MFGCFG_PWRSYS_BASE 0x00004680u
#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu
#define CYREG_PWRSYS_HIB_TR0 0x00004680u
#define CYREG_PWRSYS_HIB_TR1 0x00004681u
#define CYREG_PWRSYS_I2C_TR 0x00004682u
#define CYREG_PWRSYS_SLP_TR 0x00004683u
#define CYREG_PWRSYS_BUZZ_TR 0x00004684u
#define CYREG_PWRSYS_WAKE_TR0 0x00004685u
#define CYREG_PWRSYS_WAKE_TR1 0x00004686u
#define CYREG_PWRSYS_BREF_TR 0x00004687u
#define CYREG_PWRSYS_BG_TR 0x00004688u
#define CYREG_PWRSYS_WAKE_TR2 0x00004689u
#define CYREG_PWRSYS_WAKE_TR3 0x0000468au
#define CYDEV_MFGCFG_ILO_BASE 0x00004690u
#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u
#define CYREG_ILO_TR0 0x00004690u
#define CYREG_ILO_TR1 0x00004691u
#define CYDEV_MFGCFG_X32_BASE 0x00004698u
#define CYDEV_MFGCFG_X32_SIZE 0x00000001u
#define CYREG_X32_TR 0x00004698u
#define CYDEV_MFGCFG_IMO_BASE 0x000046a0u
#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u
#define CYREG_IMO_TR0 0x000046a0u
#define CYREG_IMO_TR1 0x000046a1u
#define CYREG_IMO_GAIN 0x000046a2u
#define CYREG_IMO_C36M 0x000046a3u
#define CYREG_IMO_TR2 0x000046a4u
#define CYDEV_MFGCFG_XMHZ_BASE 0x000046a8u
#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u
#define CYREG_XMHZ_TR 0x000046a8u
#define CYREG_MFGCFG_DLY 0x000046c0u
#define CYDEV_MFGCFG_MLOGIC_BASE 0x000046e0u
#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du
#define CYREG_MLOGIC_DMPSTR 0x000046e2u
#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x000046e4u
#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u
#define CYREG_MLOGIC_SEG_CR 0x000046e4u
#define CYREG_MLOGIC_SEG_CFG0 0x000046e5u
#define CYREG_MLOGIC_DEBUG 0x000046e8u
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x000046eau
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u
#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x000046eau
#define CYREG_MLOGIC_REV_ID 0x000046ecu
#define CYDEV_RESET_BASE 0x000046f0u
#define CYDEV_RESET_SIZE 0x0000000fu
#define CYREG_RESET_IPOR_CR0 0x000046f0u
#define CYREG_RESET_IPOR_CR1 0x000046f1u
#define CYREG_RESET_IPOR_CR2 0x000046f2u
#define CYREG_RESET_IPOR_CR3 0x000046f3u
#define CYREG_RESET_CR0 0x000046f4u
#define CYREG_RESET_CR1 0x000046f5u
#define CYREG_RESET_CR2 0x000046f6u
#define CYREG_RESET_CR3 0x000046f7u
#define CYREG_RESET_CR4 0x000046f8u
#define CYREG_RESET_CR5 0x000046f9u
#define CYREG_RESET_SR0 0x000046fau
#define CYREG_RESET_SR1 0x000046fbu
#define CYREG_RESET_SR2 0x000046fcu
#define CYREG_RESET_SR3 0x000046fdu
#define CYREG_RESET_TR 0x000046feu
#define CYDEV_SPC_BASE 0x00004700u
#define CYDEV_SPC_SIZE 0x00000100u
#define CYREG_SPC_FM_EE_CR 0x00004700u
#define CYREG_SPC_FM_EE_WAKE_CNT 0x00004701u
#define CYREG_SPC_EE_SCR 0x00004702u
#define CYREG_SPC_EE_ERR 0x00004703u
#define CYREG_SPC_CPU_DATA 0x00004720u
#define CYREG_SPC_DMA_DATA 0x00004721u
#define CYREG_SPC_SR 0x00004722u
#define CYREG_SPC_CR 0x00004723u
#define CYDEV_SPC_DMM_MAP_BASE 0x00004780u
#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u
#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x00004780u
#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u
#define CYDEV_CACHE_BASE 0x00004800u
#define CYDEV_CACHE_SIZE 0x00000092u
#define CYREG_CACHE_CR 0x00004800u
#define CYREG_CACHE_LP_MODE 0x00004801u
#define CYREG_CACHE_SR 0x00004808u
#define CYREG_CACHE_TAG_SR 0x00004810u
#define CYREG_CACHE_TAG0 0x00004818u
#define CYREG_CACHE_TAG1 0x00004820u
#define CYREG_CACHE_TAG2 0x00004828u
#define CYREG_CACHE_TAG3 0x00004830u
#define CYREG_CACHE_TAG4 0x00004838u
#define CYREG_CACHE_TAG5 0x00004840u
#define CYREG_CACHE_TAG6 0x00004848u
#define CYREG_CACHE_TAG7 0x00004850u
#define CYREG_CACHE_INT_MSK 0x00004858u
#define CYREG_CACHE_INT_SR 0x00004860u
#define CYREG_CACHE_INT_LOG0 0x00004868u
#define CYREG_CACHE_INT_LOG1 0x00004870u
#define CYREG_CACHE_INT_LOG2 0x00004878u
#define CYREG_CACHE_INT_LOG3 0x00004880u
#define CYREG_CACHE_INT_LOG4 0x00004888u
#define CYREG_CACHE_INT_LOG5 0x00004890u
#define CYDEV_I2C_BASE 0x00004900u
#define CYDEV_I2C_SIZE 0x000000ddu
#define CYREG_I2C_XCFG 0x000049c8u
#define CYREG_I2C_ADR 0x000049cau
#define CYREG_I2C_CFG 0x000049d6u
#define CYREG_I2C_CSR 0x000049d7u
#define CYREG_I2C_D 0x000049d8u
#define CYREG_I2C_MCSR 0x000049d9u
#define CYREG_I2C_CLK_DIV1 0x000049dbu
#define CYREG_I2C_CLK_DIV2 0x000049dcu
#define CYDEV_DEC_BASE 0x00004e00u
#define CYDEV_DEC_SIZE 0x00000015u
#define CYREG_DEC_CR 0x00004e00u
#define CYREG_DEC_SR 0x00004e01u
#define CYREG_DEC_SHIFT1 0x00004e02u
#define CYREG_DEC_SHIFT2 0x00004e03u
#define CYREG_DEC_DR2 0x00004e04u
#define CYREG_DEC_DR2H 0x00004e05u
#define CYREG_DEC_DR1 0x00004e06u
#define CYREG_DEC_OCOR 0x00004e08u
#define CYREG_DEC_OCORM 0x00004e09u
#define CYREG_DEC_OCORH 0x00004e0au
#define CYREG_DEC_GCOR 0x00004e0cu
#define CYREG_DEC_GCORH 0x00004e0du
#define CYREG_DEC_GVAL 0x00004e0eu
#define CYREG_DEC_OUTSAMP 0x00004e10u
#define CYREG_DEC_OUTSAMPM 0x00004e11u
#define CYREG_DEC_OUTSAMPH 0x00004e12u
#define CYREG_DEC_OUTSAMPS 0x00004e13u
#define CYREG_DEC_COHER 0x00004e14u
#define CYDEV_TMR0_BASE 0x00004f00u
#define CYDEV_TMR0_SIZE 0x0000000cu
#define CYREG_TMR0_CFG0 0x00004f00u
#define CYREG_TMR0_CFG1 0x00004f01u
#define CYREG_TMR0_CFG2 0x00004f02u
#define CYREG_TMR0_SR0 0x00004f03u
#define CYREG_TMR0_PER0 0x00004f04u
#define CYREG_TMR0_PER1 0x00004f05u
#define CYREG_TMR0_CNT_CMP0 0x00004f06u
#define CYREG_TMR0_CNT_CMP1 0x00004f07u
#define CYREG_TMR0_CAP0 0x00004f08u
#define CYREG_TMR0_CAP1 0x00004f09u
#define CYREG_TMR0_RT0 0x00004f0au
#define CYREG_TMR0_RT1 0x00004f0bu
#define CYDEV_TMR1_BASE 0x00004f0cu
#define CYDEV_TMR1_SIZE 0x0000000cu
#define CYREG_TMR1_CFG0 0x00004f0cu
#define CYREG_TMR1_CFG1 0x00004f0du
#define CYREG_TMR1_CFG2 0x00004f0eu
#define CYREG_TMR1_SR0 0x00004f0fu
#define CYREG_TMR1_PER0 0x00004f10u
#define CYREG_TMR1_PER1 0x00004f11u
#define CYREG_TMR1_CNT_CMP0 0x00004f12u
#define CYREG_TMR1_CNT_CMP1 0x00004f13u
#define CYREG_TMR1_CAP0 0x00004f14u
#define CYREG_TMR1_CAP1 0x00004f15u
#define CYREG_TMR1_RT0 0x00004f16u
#define CYREG_TMR1_RT1 0x00004f17u
#define CYDEV_TMR2_BASE 0x00004f18u
#define CYDEV_TMR2_SIZE 0x0000000cu
#define CYREG_TMR2_CFG0 0x00004f18u
#define CYREG_TMR2_CFG1 0x00004f19u
#define CYREG_TMR2_CFG2 0x00004f1au
#define CYREG_TMR2_SR0 0x00004f1bu
#define CYREG_TMR2_PER0 0x00004f1cu
#define CYREG_TMR2_PER1 0x00004f1du
#define CYREG_TMR2_CNT_CMP0 0x00004f1eu
#define CYREG_TMR2_CNT_CMP1 0x00004f1fu
#define CYREG_TMR2_CAP0 0x00004f20u
#define CYREG_TMR2_CAP1 0x00004f21u
#define CYREG_TMR2_RT0 0x00004f22u
#define CYREG_TMR2_RT1 0x00004f23u
#define CYDEV_TMR3_BASE 0x00004f24u
#define CYDEV_TMR3_SIZE 0x0000000cu
#define CYREG_TMR3_CFG0 0x00004f24u
#define CYREG_TMR3_CFG1 0x00004f25u
#define CYREG_TMR3_CFG2 0x00004f26u
#define CYREG_TMR3_SR0 0x00004f27u
#define CYREG_TMR3_PER0 0x00004f28u
#define CYREG_TMR3_PER1 0x00004f29u
#define CYREG_TMR3_CNT_CMP0 0x00004f2au
#define CYREG_TMR3_CNT_CMP1 0x00004f2bu
#define CYREG_TMR3_CAP0 0x00004f2cu
#define CYREG_TMR3_CAP1 0x00004f2du
#define CYREG_TMR3_RT0 0x00004f2eu
#define CYREG_TMR3_RT1 0x00004f2fu
#define CYDEV_IO_BASE 0x00005000u
#define CYDEV_IO_SIZE 0x00000200u
#define CYDEV_IO_PC_BASE 0x00005000u
#define CYDEV_IO_PC_SIZE 0x00000080u
#define CYDEV_IO_PC_PRT0_BASE 0x00005000u
#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u
#define CYREG_PRT0_PC0 0x00005000u
#define CYREG_PRT0_PC1 0x00005001u
#define CYREG_PRT0_PC2 0x00005002u
#define CYREG_PRT0_PC3 0x00005003u
#define CYREG_PRT0_PC4 0x00005004u
#define CYREG_PRT0_PC5 0x00005005u
#define CYREG_PRT0_PC6 0x00005006u
#define CYREG_PRT0_PC7 0x00005007u
#define CYDEV_IO_PC_PRT1_BASE 0x00005008u
#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u
#define CYREG_PRT1_PC0 0x00005008u
#define CYREG_PRT1_PC1 0x00005009u
#define CYREG_PRT1_PC2 0x0000500au
#define CYREG_PRT1_PC3 0x0000500bu
#define CYREG_PRT1_PC4 0x0000500cu
#define CYREG_PRT1_PC5 0x0000500du
#define CYREG_PRT1_PC6 0x0000500eu
#define CYREG_PRT1_PC7 0x0000500fu
#define CYDEV_IO_PC_PRT2_BASE 0x00005010u
#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u
#define CYREG_PRT2_PC0 0x00005010u
#define CYREG_PRT2_PC1 0x00005011u
#define CYREG_PRT2_PC2 0x00005012u
#define CYREG_PRT2_PC3 0x00005013u
#define CYREG_PRT2_PC4 0x00005014u
#define CYREG_PRT2_PC5 0x00005015u
#define CYREG_PRT2_PC6 0x00005016u
#define CYREG_PRT2_PC7 0x00005017u
#define CYDEV_IO_PC_PRT3_BASE 0x00005018u
#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u
#define CYREG_PRT3_PC0 0x00005018u
#define CYREG_PRT3_PC1 0x00005019u
#define CYREG_PRT3_PC2 0x0000501au
#define CYREG_PRT3_PC3 0x0000501bu
#define CYREG_PRT3_PC4 0x0000501cu
#define CYREG_PRT3_PC5 0x0000501du
#define CYREG_PRT3_PC6 0x0000501eu
#define CYREG_PRT3_PC7 0x0000501fu
#define CYDEV_IO_PC_PRT4_BASE 0x00005020u
#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u
#define CYREG_PRT4_PC0 0x00005020u
#define CYREG_PRT4_PC1 0x00005021u
#define CYREG_PRT4_PC2 0x00005022u
#define CYREG_PRT4_PC3 0x00005023u
#define CYREG_PRT4_PC4 0x00005024u
#define CYREG_PRT4_PC5 0x00005025u
#define CYREG_PRT4_PC6 0x00005026u
#define CYREG_PRT4_PC7 0x00005027u
#define CYDEV_IO_PC_PRT5_BASE 0x00005028u
#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u
#define CYREG_PRT5_PC0 0x00005028u
#define CYREG_PRT5_PC1 0x00005029u
#define CYREG_PRT5_PC2 0x0000502au
#define CYREG_PRT5_PC3 0x0000502bu
#define CYREG_PRT5_PC4 0x0000502cu
#define CYREG_PRT5_PC5 0x0000502du
#define CYREG_PRT5_PC6 0x0000502eu
#define CYREG_PRT5_PC7 0x0000502fu
#define CYDEV_IO_PC_PRT6_BASE 0x00005030u
#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u
#define CYREG_PRT6_PC0 0x00005030u
#define CYREG_PRT6_PC1 0x00005031u
#define CYREG_PRT6_PC2 0x00005032u
#define CYREG_PRT6_PC3 0x00005033u
#define CYREG_PRT6_PC4 0x00005034u
#define CYREG_PRT6_PC5 0x00005035u
#define CYREG_PRT6_PC6 0x00005036u
#define CYREG_PRT6_PC7 0x00005037u
#define CYDEV_IO_PC_PRT12_BASE 0x00005060u
#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u
#define CYREG_PRT12_PC0 0x00005060u
#define CYREG_PRT12_PC1 0x00005061u
#define CYREG_PRT12_PC2 0x00005062u
#define CYREG_PRT12_PC3 0x00005063u
#define CYREG_PRT12_PC4 0x00005064u
#define CYREG_PRT12_PC5 0x00005065u
#define CYREG_PRT12_PC6 0x00005066u
#define CYREG_PRT12_PC7 0x00005067u
#define CYDEV_IO_PC_PRT15_BASE 0x00005078u
#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u
#define CYREG_IO_PC_PRT15_PC0 0x00005078u
#define CYREG_IO_PC_PRT15_PC1 0x00005079u
#define CYREG_IO_PC_PRT15_PC2 0x0000507au
#define CYREG_IO_PC_PRT15_PC3 0x0000507bu
#define CYREG_IO_PC_PRT15_PC4 0x0000507cu
#define CYREG_IO_PC_PRT15_PC5 0x0000507du
#define CYDEV_IO_PC_PRT15_7_6_BASE 0x0000507eu
#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u
#define CYREG_IO_PC_PRT15_7_6_PC0 0x0000507eu
#define CYREG_IO_PC_PRT15_7_6_PC1 0x0000507fu
#define CYDEV_IO_DR_BASE 0x00005080u
#define CYDEV_IO_DR_SIZE 0x00000010u
#define CYDEV_IO_DR_PRT0_BASE 0x00005080u
#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u
#define CYREG_PRT0_DR_ALIAS 0x00005080u
#define CYDEV_IO_DR_PRT1_BASE 0x00005081u
#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u
#define CYREG_PRT1_DR_ALIAS 0x00005081u
#define CYDEV_IO_DR_PRT2_BASE 0x00005082u
#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u
#define CYREG_PRT2_DR_ALIAS 0x00005082u
#define CYDEV_IO_DR_PRT3_BASE 0x00005083u
#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u
#define CYREG_PRT3_DR_ALIAS 0x00005083u
#define CYDEV_IO_DR_PRT4_BASE 0x00005084u
#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u
#define CYREG_PRT4_DR_ALIAS 0x00005084u
#define CYDEV_IO_DR_PRT5_BASE 0x00005085u
#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u
#define CYREG_PRT5_DR_ALIAS 0x00005085u
#define CYDEV_IO_DR_PRT6_BASE 0x00005086u
#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u
#define CYREG_PRT6_DR_ALIAS 0x00005086u
#define CYDEV_IO_DR_PRT12_BASE 0x0000508cu
#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u
#define CYREG_PRT12_DR_ALIAS 0x0000508cu
#define CYDEV_IO_DR_PRT15_BASE 0x0000508fu
#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u
#define CYREG_PRT15_DR_15_ALIAS 0x0000508fu
#define CYDEV_IO_PS_BASE 0x00005090u
#define CYDEV_IO_PS_SIZE 0x00000010u
#define CYDEV_IO_PS_PRT0_BASE 0x00005090u
#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u
#define CYREG_PRT0_PS_ALIAS 0x00005090u
#define CYDEV_IO_PS_PRT1_BASE 0x00005091u
#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u
#define CYREG_PRT1_PS_ALIAS 0x00005091u
#define CYDEV_IO_PS_PRT2_BASE 0x00005092u
#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u
#define CYREG_PRT2_PS_ALIAS 0x00005092u
#define CYDEV_IO_PS_PRT3_BASE 0x00005093u
#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u
#define CYREG_PRT3_PS_ALIAS 0x00005093u
#define CYDEV_IO_PS_PRT4_BASE 0x00005094u
#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u
#define CYREG_PRT4_PS_ALIAS 0x00005094u
#define CYDEV_IO_PS_PRT5_BASE 0x00005095u
#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u
#define CYREG_PRT5_PS_ALIAS 0x00005095u
#define CYDEV_IO_PS_PRT6_BASE 0x00005096u
#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u
#define CYREG_PRT6_PS_ALIAS 0x00005096u
#define CYDEV_IO_PS_PRT12_BASE 0x0000509cu
#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u
#define CYREG_PRT12_PS_ALIAS 0x0000509cu
#define CYDEV_IO_PS_PRT15_BASE 0x0000509fu
#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u
#define CYREG_PRT15_PS15_ALIAS 0x0000509fu
#define CYDEV_IO_PRT_BASE 0x00005100u
#define CYDEV_IO_PRT_SIZE 0x00000100u
#define CYDEV_IO_PRT_PRT0_BASE 0x00005100u
#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u
#define CYREG_PRT0_DR 0x00005100u
#define CYREG_PRT0_PS 0x00005101u
#define CYREG_PRT0_DM0 0x00005102u
#define CYREG_PRT0_DM1 0x00005103u
#define CYREG_PRT0_DM2 0x00005104u
#define CYREG_PRT0_SLW 0x00005105u
#define CYREG_PRT0_BYP 0x00005106u
#define CYREG_PRT0_BIE 0x00005107u
#define CYREG_PRT0_INP_DIS 0x00005108u
#define CYREG_PRT0_CTL 0x00005109u
#define CYREG_PRT0_PRT 0x0000510au
#define CYREG_PRT0_BIT_MASK 0x0000510bu
#define CYREG_PRT0_AMUX 0x0000510cu
#define CYREG_PRT0_AG 0x0000510du
#define CYREG_PRT0_LCD_COM_SEG 0x0000510eu
#define CYREG_PRT0_LCD_EN 0x0000510fu
#define CYDEV_IO_PRT_PRT1_BASE 0x00005110u
#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u
#define CYREG_PRT1_DR 0x00005110u
#define CYREG_PRT1_PS 0x00005111u
#define CYREG_PRT1_DM0 0x00005112u
#define CYREG_PRT1_DM1 0x00005113u
#define CYREG_PRT1_DM2 0x00005114u
#define CYREG_PRT1_SLW 0x00005115u
#define CYREG_PRT1_BYP 0x00005116u
#define CYREG_PRT1_BIE 0x00005117u
#define CYREG_PRT1_INP_DIS 0x00005118u
#define CYREG_PRT1_CTL 0x00005119u
#define CYREG_PRT1_PRT 0x0000511au
#define CYREG_PRT1_BIT_MASK 0x0000511bu
#define CYREG_PRT1_AMUX 0x0000511cu
#define CYREG_PRT1_AG 0x0000511du
#define CYREG_PRT1_LCD_COM_SEG 0x0000511eu
#define CYREG_PRT1_LCD_EN 0x0000511fu
#define CYDEV_IO_PRT_PRT2_BASE 0x00005120u
#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u
#define CYREG_PRT2_DR 0x00005120u
#define CYREG_PRT2_PS 0x00005121u
#define CYREG_PRT2_DM0 0x00005122u
#define CYREG_PRT2_DM1 0x00005123u
#define CYREG_PRT2_DM2 0x00005124u
#define CYREG_PRT2_SLW 0x00005125u
#define CYREG_PRT2_BYP 0x00005126u
#define CYREG_PRT2_BIE 0x00005127u
#define CYREG_PRT2_INP_DIS 0x00005128u
#define CYREG_PRT2_CTL 0x00005129u
#define CYREG_PRT2_PRT 0x0000512au
#define CYREG_PRT2_BIT_MASK 0x0000512bu
#define CYREG_PRT2_AMUX 0x0000512cu
#define CYREG_PRT2_AG 0x0000512du
#define CYREG_PRT2_LCD_COM_SEG 0x0000512eu
#define CYREG_PRT2_LCD_EN 0x0000512fu
#define CYDEV_IO_PRT_PRT3_BASE 0x00005130u
#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u
#define CYREG_PRT3_DR 0x00005130u
#define CYREG_PRT3_PS 0x00005131u
#define CYREG_PRT3_DM0 0x00005132u
#define CYREG_PRT3_DM1 0x00005133u
#define CYREG_PRT3_DM2 0x00005134u
#define CYREG_PRT3_SLW 0x00005135u
#define CYREG_PRT3_BYP 0x00005136u
#define CYREG_PRT3_BIE 0x00005137u
#define CYREG_PRT3_INP_DIS 0x00005138u
#define CYREG_PRT3_CTL 0x00005139u
#define CYREG_PRT3_PRT 0x0000513au
#define CYREG_PRT3_BIT_MASK 0x0000513bu
#define CYREG_PRT3_AMUX 0x0000513cu
#define CYREG_PRT3_AG 0x0000513du
#define CYREG_PRT3_LCD_COM_SEG 0x0000513eu
#define CYREG_PRT3_LCD_EN 0x0000513fu
#define CYDEV_IO_PRT_PRT4_BASE 0x00005140u
#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u
#define CYREG_PRT4_DR 0x00005140u
#define CYREG_PRT4_PS 0x00005141u
#define CYREG_PRT4_DM0 0x00005142u
#define CYREG_PRT4_DM1 0x00005143u
#define CYREG_PRT4_DM2 0x00005144u
#define CYREG_PRT4_SLW 0x00005145u
#define CYREG_PRT4_BYP 0x00005146u
#define CYREG_PRT4_BIE 0x00005147u
#define CYREG_PRT4_INP_DIS 0x00005148u
#define CYREG_PRT4_CTL 0x00005149u
#define CYREG_PRT4_PRT 0x0000514au
#define CYREG_PRT4_BIT_MASK 0x0000514bu
#define CYREG_PRT4_AMUX 0x0000514cu
#define CYREG_PRT4_AG 0x0000514du
#define CYREG_PRT4_LCD_COM_SEG 0x0000514eu
#define CYREG_PRT4_LCD_EN 0x0000514fu
#define CYDEV_IO_PRT_PRT5_BASE 0x00005150u
#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u
#define CYREG_PRT5_DR 0x00005150u
#define CYREG_PRT5_PS 0x00005151u
#define CYREG_PRT5_DM0 0x00005152u
#define CYREG_PRT5_DM1 0x00005153u
#define CYREG_PRT5_DM2 0x00005154u
#define CYREG_PRT5_SLW 0x00005155u
#define CYREG_PRT5_BYP 0x00005156u
#define CYREG_PRT5_BIE 0x00005157u
#define CYREG_PRT5_INP_DIS 0x00005158u
#define CYREG_PRT5_CTL 0x00005159u
#define CYREG_PRT5_PRT 0x0000515au
#define CYREG_PRT5_BIT_MASK 0x0000515bu
#define CYREG_PRT5_AMUX 0x0000515cu
#define CYREG_PRT5_AG 0x0000515du
#define CYREG_PRT5_LCD_COM_SEG 0x0000515eu
#define CYREG_PRT5_LCD_EN 0x0000515fu
#define CYDEV_IO_PRT_PRT6_BASE 0x00005160u
#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u
#define CYREG_PRT6_DR 0x00005160u
#define CYREG_PRT6_PS 0x00005161u
#define CYREG_PRT6_DM0 0x00005162u
#define CYREG_PRT6_DM1 0x00005163u
#define CYREG_PRT6_DM2 0x00005164u
#define CYREG_PRT6_SLW 0x00005165u
#define CYREG_PRT6_BYP 0x00005166u
#define CYREG_PRT6_BIE 0x00005167u
#define CYREG_PRT6_INP_DIS 0x00005168u
#define CYREG_PRT6_CTL 0x00005169u
#define CYREG_PRT6_PRT 0x0000516au
#define CYREG_PRT6_BIT_MASK 0x0000516bu
#define CYREG_PRT6_AMUX 0x0000516cu
#define CYREG_PRT6_AG 0x0000516du
#define CYREG_PRT6_LCD_COM_SEG 0x0000516eu
#define CYREG_PRT6_LCD_EN 0x0000516fu
#define CYDEV_IO_PRT_PRT12_BASE 0x000051c0u
#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u
#define CYREG_PRT12_DR 0x000051c0u
#define CYREG_PRT12_PS 0x000051c1u
#define CYREG_PRT12_DM0 0x000051c2u
#define CYREG_PRT12_DM1 0x000051c3u
#define CYREG_PRT12_DM2 0x000051c4u
#define CYREG_PRT12_SLW 0x000051c5u
#define CYREG_PRT12_BYP 0x000051c6u
#define CYREG_PRT12_BIE 0x000051c7u
#define CYREG_PRT12_INP_DIS 0x000051c8u
#define CYREG_PRT12_SIO_HYST_EN 0x000051c9u
#define CYREG_PRT12_PRT 0x000051cau
#define CYREG_PRT12_BIT_MASK 0x000051cbu
#define CYREG_PRT12_SIO_REG_HIFREQ 0x000051ccu
#define CYREG_PRT12_AG 0x000051cdu
#define CYREG_PRT12_SIO_CFG 0x000051ceu
#define CYREG_PRT12_SIO_DIFF 0x000051cfu
#define CYDEV_IO_PRT_PRT15_BASE 0x000051f0u
#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u
#define CYREG_PRT15_DR 0x000051f0u
#define CYREG_PRT15_PS 0x000051f1u
#define CYREG_PRT15_DM0 0x000051f2u
#define CYREG_PRT15_DM1 0x000051f3u
#define CYREG_PRT15_DM2 0x000051f4u
#define CYREG_PRT15_SLW 0x000051f5u
#define CYREG_PRT15_BYP 0x000051f6u
#define CYREG_PRT15_BIE 0x000051f7u
#define CYREG_PRT15_INP_DIS 0x000051f8u
#define CYREG_PRT15_CTL 0x000051f9u
#define CYREG_PRT15_PRT 0x000051fau
#define CYREG_PRT15_BIT_MASK 0x000051fbu
#define CYREG_PRT15_AMUX 0x000051fcu
#define CYREG_PRT15_AG 0x000051fdu
#define CYREG_PRT15_LCD_COM_SEG 0x000051feu
#define CYREG_PRT15_LCD_EN 0x000051ffu
#define CYDEV_PRTDSI_BASE 0x00005200u
#define CYDEV_PRTDSI_SIZE 0x0000007fu
#define CYDEV_PRTDSI_PRT0_BASE 0x00005200u
#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u
#define CYREG_PRT0_OUT_SEL0 0x00005200u
#define CYREG_PRT0_OUT_SEL1 0x00005201u
#define CYREG_PRT0_OE_SEL0 0x00005202u
#define CYREG_PRT0_OE_SEL1 0x00005203u
#define CYREG_PRT0_DBL_SYNC_IN 0x00005204u
#define CYREG_PRT0_SYNC_OUT 0x00005205u
#define CYREG_PRT0_CAPS_SEL 0x00005206u
#define CYDEV_PRTDSI_PRT1_BASE 0x00005208u
#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u
#define CYREG_PRT1_OUT_SEL0 0x00005208u
#define CYREG_PRT1_OUT_SEL1 0x00005209u
#define CYREG_PRT1_OE_SEL0 0x0000520au
#define CYREG_PRT1_OE_SEL1 0x0000520bu
#define CYREG_PRT1_DBL_SYNC_IN 0x0000520cu
#define CYREG_PRT1_SYNC_OUT 0x0000520du
#define CYREG_PRT1_CAPS_SEL 0x0000520eu
#define CYDEV_PRTDSI_PRT2_BASE 0x00005210u
#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u
#define CYREG_PRT2_OUT_SEL0 0x00005210u
#define CYREG_PRT2_OUT_SEL1 0x00005211u
#define CYREG_PRT2_OE_SEL0 0x00005212u
#define CYREG_PRT2_OE_SEL1 0x00005213u
#define CYREG_PRT2_DBL_SYNC_IN 0x00005214u
#define CYREG_PRT2_SYNC_OUT 0x00005215u
#define CYREG_PRT2_CAPS_SEL 0x00005216u
#define CYDEV_PRTDSI_PRT3_BASE 0x00005218u
#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u
#define CYREG_PRT3_OUT_SEL0 0x00005218u
#define CYREG_PRT3_OUT_SEL1 0x00005219u
#define CYREG_PRT3_OE_SEL0 0x0000521au
#define CYREG_PRT3_OE_SEL1 0x0000521bu
#define CYREG_PRT3_DBL_SYNC_IN 0x0000521cu
#define CYREG_PRT3_SYNC_OUT 0x0000521du
#define CYREG_PRT3_CAPS_SEL 0x0000521eu
#define CYDEV_PRTDSI_PRT4_BASE 0x00005220u
#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u
#define CYREG_PRT4_OUT_SEL0 0x00005220u
#define CYREG_PRT4_OUT_SEL1 0x00005221u
#define CYREG_PRT4_OE_SEL0 0x00005222u
#define CYREG_PRT4_OE_SEL1 0x00005223u
#define CYREG_PRT4_DBL_SYNC_IN 0x00005224u
#define CYREG_PRT4_SYNC_OUT 0x00005225u
#define CYREG_PRT4_CAPS_SEL 0x00005226u
#define CYDEV_PRTDSI_PRT5_BASE 0x00005228u
#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u
#define CYREG_PRT5_OUT_SEL0 0x00005228u
#define CYREG_PRT5_OUT_SEL1 0x00005229u
#define CYREG_PRT5_OE_SEL0 0x0000522au
#define CYREG_PRT5_OE_SEL1 0x0000522bu
#define CYREG_PRT5_DBL_SYNC_IN 0x0000522cu
#define CYREG_PRT5_SYNC_OUT 0x0000522du
#define CYREG_PRT5_CAPS_SEL 0x0000522eu
#define CYDEV_PRTDSI_PRT6_BASE 0x00005230u
#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u
#define CYREG_PRT6_OUT_SEL0 0x00005230u
#define CYREG_PRT6_OUT_SEL1 0x00005231u
#define CYREG_PRT6_OE_SEL0 0x00005232u
#define CYREG_PRT6_OE_SEL1 0x00005233u
#define CYREG_PRT6_DBL_SYNC_IN 0x00005234u
#define CYREG_PRT6_SYNC_OUT 0x00005235u
#define CYREG_PRT6_CAPS_SEL 0x00005236u
#define CYDEV_PRTDSI_PRT12_BASE 0x00005260u
#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u
#define CYREG_PRT12_OUT_SEL0 0x00005260u
#define CYREG_PRT12_OUT_SEL1 0x00005261u
#define CYREG_PRT12_OE_SEL0 0x00005262u
#define CYREG_PRT12_OE_SEL1 0x00005263u
#define CYREG_PRT12_DBL_SYNC_IN 0x00005264u
#define CYREG_PRT12_SYNC_OUT 0x00005265u
#define CYDEV_PRTDSI_PRT15_BASE 0x00005278u
#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u
#define CYREG_PRT15_OUT_SEL0 0x00005278u
#define CYREG_PRT15_OUT_SEL1 0x00005279u
#define CYREG_PRT15_OE_SEL0 0x0000527au
#define CYREG_PRT15_OE_SEL1 0x0000527bu
#define CYREG_PRT15_DBL_SYNC_IN 0x0000527cu
#define CYREG_PRT15_SYNC_OUT 0x0000527du
#define CYREG_PRT15_CAPS_SEL 0x0000527eu
#define CYDEV_EMIF_BASE 0x00005400u
#define CYDEV_EMIF_SIZE 0x00000007u
#define CYREG_EMIF_NO_UDB 0x00005400u
#define CYREG_EMIF_RP_WAIT_STATES 0x00005401u
#define CYREG_EMIF_MEM_DWN 0x00005402u
#define CYREG_EMIF_MEMCLK_DIV 0x00005403u
#define CYREG_EMIF_CLOCK_EN 0x00005404u
#define CYREG_EMIF_EM_TYPE 0x00005405u
#define CYREG_EMIF_WP_WAIT_STATES 0x00005406u
#define CYDEV_ANAIF_BASE 0x00005800u
#define CYDEV_ANAIF_SIZE 0x0000039du
#define CYDEV_ANAIF_CFG_BASE 0x00005800u
#define CYDEV_ANAIF_CFG_SIZE 0x000000a0u
#define CYDEV_ANAIF_CFG_SC0_BASE 0x00005800u
#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u
#define CYREG_SC0_CR0 0x00005800u
#define CYREG_SC0_CR1 0x00005801u
#define CYREG_SC0_CR2 0x00005802u
#define CYDEV_ANAIF_CFG_SC1_BASE 0x00005804u
#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u
#define CYREG_SC1_CR0 0x00005804u
#define CYREG_SC1_CR1 0x00005805u
#define CYREG_SC1_CR2 0x00005806u
#define CYDEV_ANAIF_CFG_SC2_BASE 0x00005808u
#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u
#define CYREG_SC2_CR0 0x00005808u
#define CYREG_SC2_CR1 0x00005809u
#define CYREG_SC2_CR2 0x0000580au
#define CYDEV_ANAIF_CFG_SC3_BASE 0x0000580cu
#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u
#define CYREG_SC3_CR0 0x0000580cu
#define CYREG_SC3_CR1 0x0000580du
#define CYREG_SC3_CR2 0x0000580eu
#define CYDEV_ANAIF_CFG_DAC0_BASE 0x00005820u
#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u
#define CYREG_DAC0_CR0 0x00005820u
#define CYREG_DAC0_CR1 0x00005821u
#define CYREG_DAC0_TST 0x00005822u
#define CYDEV_ANAIF_CFG_DAC1_BASE 0x00005824u
#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u
#define CYREG_DAC1_CR0 0x00005824u
#define CYREG_DAC1_CR1 0x00005825u
#define CYREG_DAC1_TST 0x00005826u
#define CYDEV_ANAIF_CFG_DAC2_BASE 0x00005828u
#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u
#define CYREG_DAC2_CR0 0x00005828u
#define CYREG_DAC2_CR1 0x00005829u
#define CYREG_DAC2_TST 0x0000582au
#define CYDEV_ANAIF_CFG_DAC3_BASE 0x0000582cu
#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u
#define CYREG_DAC3_CR0 0x0000582cu
#define CYREG_DAC3_CR1 0x0000582du
#define CYREG_DAC3_TST 0x0000582eu
#define CYDEV_ANAIF_CFG_CMP0_BASE 0x00005840u
#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u
#define CYREG_CMP0_CR 0x00005840u
#define CYDEV_ANAIF_CFG_CMP1_BASE 0x00005841u
#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u
#define CYREG_CMP1_CR 0x00005841u
#define CYDEV_ANAIF_CFG_CMP2_BASE 0x00005842u
#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u
#define CYREG_CMP2_CR 0x00005842u
#define CYDEV_ANAIF_CFG_CMP3_BASE 0x00005843u
#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u
#define CYREG_CMP3_CR 0x00005843u
#define CYDEV_ANAIF_CFG_LUT0_BASE 0x00005848u
#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u
#define CYREG_LUT0_CR 0x00005848u
#define CYREG_LUT0_MX 0x00005849u
#define CYDEV_ANAIF_CFG_LUT1_BASE 0x0000584au
#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u
#define CYREG_LUT1_CR 0x0000584au
#define CYREG_LUT1_MX 0x0000584bu
#define CYDEV_ANAIF_CFG_LUT2_BASE 0x0000584cu
#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u
#define CYREG_LUT2_CR 0x0000584cu
#define CYREG_LUT2_MX 0x0000584du
#define CYDEV_ANAIF_CFG_LUT3_BASE 0x0000584eu
#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u
#define CYREG_LUT3_CR 0x0000584eu
#define CYREG_LUT3_MX 0x0000584fu
#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x00005858u
#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u
#define CYREG_OPAMP0_CR 0x00005858u
#define CYREG_OPAMP0_RSVD 0x00005859u
#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x0000585au
#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u
#define CYREG_OPAMP1_CR 0x0000585au
#define CYREG_OPAMP1_RSVD 0x0000585bu
#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x0000585cu
#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u
#define CYREG_OPAMP2_CR 0x0000585cu
#define CYREG_OPAMP2_RSVD 0x0000585du
#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x0000585eu
#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u
#define CYREG_OPAMP3_CR 0x0000585eu
#define CYREG_OPAMP3_RSVD 0x0000585fu
#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x00005868u
#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u
#define CYREG_LCDDAC_CR0 0x00005868u
#define CYREG_LCDDAC_CR1 0x00005869u
#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x0000586au
#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u
#define CYREG_LCDDRV_CR 0x0000586au
#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x0000586bu
#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u
#define CYREG_LCDTMR_CFG 0x0000586bu
#define CYDEV_ANAIF_CFG_BG_BASE 0x0000586cu
#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u
#define CYREG_BG_CR0 0x0000586cu
#define CYREG_BG_RSVD 0x0000586du
#define CYREG_BG_DFT0 0x0000586eu
#define CYREG_BG_DFT1 0x0000586fu
#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x00005870u
#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u
#define CYREG_CAPSL_CFG0 0x00005870u
#define CYREG_CAPSL_CFG1 0x00005871u
#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x00005872u
#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u
#define CYREG_CAPSR_CFG0 0x00005872u
#define CYREG_CAPSR_CFG1 0x00005873u
#define CYDEV_ANAIF_CFG_PUMP_BASE 0x00005876u
#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u
#define CYREG_PUMP_CR0 0x00005876u
#define CYREG_PUMP_CR1 0x00005877u
#define CYDEV_ANAIF_CFG_LPF0_BASE 0x00005878u
#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u
#define CYREG_LPF0_CR0 0x00005878u
#define CYREG_LPF0_RSVD 0x00005879u
#define CYDEV_ANAIF_CFG_LPF1_BASE 0x0000587au
#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u
#define CYREG_LPF1_CR0 0x0000587au
#define CYREG_LPF1_RSVD 0x0000587bu
#define CYDEV_ANAIF_CFG_MISC_BASE 0x0000587cu
#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u
#define CYREG_ANAIF_CFG_MISC_CR0 0x0000587cu
#define CYDEV_ANAIF_CFG_DSM0_BASE 0x00005880u
#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u
#define CYREG_DSM0_CR0 0x00005880u
#define CYREG_DSM0_CR1 0x00005881u
#define CYREG_DSM0_CR2 0x00005882u
#define CYREG_DSM0_CR3 0x00005883u
#define CYREG_DSM0_CR4 0x00005884u
#define CYREG_DSM0_CR5 0x00005885u
#define CYREG_DSM0_CR6 0x00005886u
#define CYREG_DSM0_CR7 0x00005887u
#define CYREG_DSM0_CR8 0x00005888u
#define CYREG_DSM0_CR9 0x00005889u
#define CYREG_DSM0_CR10 0x0000588au
#define CYREG_DSM0_CR11 0x0000588bu
#define CYREG_DSM0_CR12 0x0000588cu
#define CYREG_DSM0_CR13 0x0000588du
#define CYREG_DSM0_CR14 0x0000588eu
#define CYREG_DSM0_CR15 0x0000588fu
#define CYREG_DSM0_CR16 0x00005890u
#define CYREG_DSM0_CR17 0x00005891u
#define CYREG_DSM0_REF0 0x00005892u
#define CYREG_DSM0_REF1 0x00005893u
#define CYREG_DSM0_REF2 0x00005894u
#define CYREG_DSM0_REF3 0x00005895u
#define CYREG_DSM0_DEM0 0x00005896u
#define CYREG_DSM0_DEM1 0x00005897u
#define CYREG_DSM0_TST0 0x00005898u
#define CYREG_DSM0_TST1 0x00005899u
#define CYREG_DSM0_BUF0 0x0000589au
#define CYREG_DSM0_BUF1 0x0000589bu
#define CYREG_DSM0_BUF2 0x0000589cu
#define CYREG_DSM0_BUF3 0x0000589du
#define CYREG_DSM0_MISC 0x0000589eu
#define CYREG_DSM0_RSVD1 0x0000589fu
#define CYDEV_ANAIF_RT_BASE 0x00005a00u
#define CYDEV_ANAIF_RT_SIZE 0x00000162u
#define CYDEV_ANAIF_RT_SC0_BASE 0x00005a00u
#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du
#define CYREG_SC0_SW0 0x00005a00u
#define CYREG_SC0_SW2 0x00005a02u
#define CYREG_SC0_SW3 0x00005a03u
#define CYREG_SC0_SW4 0x00005a04u
#define CYREG_SC0_SW6 0x00005a06u
#define CYREG_SC0_SW7 0x00005a07u
#define CYREG_SC0_SW8 0x00005a08u
#define CYREG_SC0_SW10 0x00005a0au
#define CYREG_SC0_CLK 0x00005a0bu
#define CYREG_SC0_BST 0x00005a0cu
#define CYDEV_ANAIF_RT_SC1_BASE 0x00005a10u
#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du
#define CYREG_SC1_SW0 0x00005a10u
#define CYREG_SC1_SW2 0x00005a12u
#define CYREG_SC1_SW3 0x00005a13u
#define CYREG_SC1_SW4 0x00005a14u
#define CYREG_SC1_SW6 0x00005a16u
#define CYREG_SC1_SW7 0x00005a17u
#define CYREG_SC1_SW8 0x00005a18u
#define CYREG_SC1_SW10 0x00005a1au
#define CYREG_SC1_CLK 0x00005a1bu
#define CYREG_SC1_BST 0x00005a1cu
#define CYDEV_ANAIF_RT_SC2_BASE 0x00005a20u
#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du
#define CYREG_SC2_SW0 0x00005a20u
#define CYREG_SC2_SW2 0x00005a22u
#define CYREG_SC2_SW3 0x00005a23u
#define CYREG_SC2_SW4 0x00005a24u
#define CYREG_SC2_SW6 0x00005a26u
#define CYREG_SC2_SW7 0x00005a27u
#define CYREG_SC2_SW8 0x00005a28u
#define CYREG_SC2_SW10 0x00005a2au
#define CYREG_SC2_CLK 0x00005a2bu
#define CYREG_SC2_BST 0x00005a2cu
#define CYDEV_ANAIF_RT_SC3_BASE 0x00005a30u
#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du
#define CYREG_SC3_SW0 0x00005a30u
#define CYREG_SC3_SW2 0x00005a32u
#define CYREG_SC3_SW3 0x00005a33u
#define CYREG_SC3_SW4 0x00005a34u
#define CYREG_SC3_SW6 0x00005a36u
#define CYREG_SC3_SW7 0x00005a37u
#define CYREG_SC3_SW8 0x00005a38u
#define CYREG_SC3_SW10 0x00005a3au
#define CYREG_SC3_CLK 0x00005a3bu
#define CYREG_SC3_BST 0x00005a3cu
#define CYDEV_ANAIF_RT_DAC0_BASE 0x00005a80u
#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u
#define CYREG_DAC0_SW0 0x00005a80u
#define CYREG_DAC0_SW2 0x00005a82u
#define CYREG_DAC0_SW3 0x00005a83u
#define CYREG_DAC0_SW4 0x00005a84u
#define CYREG_DAC0_STROBE 0x00005a87u
#define CYDEV_ANAIF_RT_DAC1_BASE 0x00005a88u
#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u
#define CYREG_DAC1_SW0 0x00005a88u
#define CYREG_DAC1_SW2 0x00005a8au
#define CYREG_DAC1_SW3 0x00005a8bu
#define CYREG_DAC1_SW4 0x00005a8cu
#define CYREG_DAC1_STROBE 0x00005a8fu
#define CYDEV_ANAIF_RT_DAC2_BASE 0x00005a90u
#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u
#define CYREG_DAC2_SW0 0x00005a90u
#define CYREG_DAC2_SW2 0x00005a92u
#define CYREG_DAC2_SW3 0x00005a93u
#define CYREG_DAC2_SW4 0x00005a94u
#define CYREG_DAC2_STROBE 0x00005a97u
#define CYDEV_ANAIF_RT_DAC3_BASE 0x00005a98u
#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u
#define CYREG_DAC3_SW0 0x00005a98u
#define CYREG_DAC3_SW2 0x00005a9au
#define CYREG_DAC3_SW3 0x00005a9bu
#define CYREG_DAC3_SW4 0x00005a9cu
#define CYREG_DAC3_STROBE 0x00005a9fu
#define CYDEV_ANAIF_RT_CMP0_BASE 0x00005ac0u
#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u
#define CYREG_CMP0_SW0 0x00005ac0u
#define CYREG_CMP0_SW2 0x00005ac2u
#define CYREG_CMP0_SW3 0x00005ac3u
#define CYREG_CMP0_SW4 0x00005ac4u
#define CYREG_CMP0_SW6 0x00005ac6u
#define CYREG_CMP0_CLK 0x00005ac7u
#define CYDEV_ANAIF_RT_CMP1_BASE 0x00005ac8u
#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u
#define CYREG_CMP1_SW0 0x00005ac8u
#define CYREG_CMP1_SW2 0x00005acau
#define CYREG_CMP1_SW3 0x00005acbu
#define CYREG_CMP1_SW4 0x00005accu
#define CYREG_CMP1_SW6 0x00005aceu
#define CYREG_CMP1_CLK 0x00005acfu
#define CYDEV_ANAIF_RT_CMP2_BASE 0x00005ad0u
#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u
#define CYREG_CMP2_SW0 0x00005ad0u
#define CYREG_CMP2_SW2 0x00005ad2u
#define CYREG_CMP2_SW3 0x00005ad3u
#define CYREG_CMP2_SW4 0x00005ad4u
#define CYREG_CMP2_SW6 0x00005ad6u
#define CYREG_CMP2_CLK 0x00005ad7u
#define CYDEV_ANAIF_RT_CMP3_BASE 0x00005ad8u
#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u
#define CYREG_CMP3_SW0 0x00005ad8u
#define CYREG_CMP3_SW2 0x00005adau
#define CYREG_CMP3_SW3 0x00005adbu
#define CYREG_CMP3_SW4 0x00005adcu
#define CYREG_CMP3_SW6 0x00005adeu
#define CYREG_CMP3_CLK 0x00005adfu
#define CYDEV_ANAIF_RT_DSM0_BASE 0x00005b00u
#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u
#define CYREG_DSM0_SW0 0x00005b00u
#define CYREG_DSM0_SW2 0x00005b02u
#define CYREG_DSM0_SW3 0x00005b03u
#define CYREG_DSM0_SW4 0x00005b04u
#define CYREG_DSM0_SW6 0x00005b06u
#define CYREG_DSM0_CLK 0x00005b07u
#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x00005b40u
#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u
#define CYREG_OPAMP0_MX 0x00005b40u
#define CYREG_OPAMP0_SW 0x00005b41u
#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x00005b42u
#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u
#define CYREG_OPAMP1_MX 0x00005b42u
#define CYREG_OPAMP1_SW 0x00005b43u
#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x00005b44u
#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u
#define CYREG_OPAMP2_MX 0x00005b44u
#define CYREG_OPAMP2_SW 0x00005b45u
#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x00005b46u
#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u
#define CYREG_OPAMP3_MX 0x00005b46u
#define CYREG_OPAMP3_SW 0x00005b47u
#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x00005b50u
#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u
#define CYREG_LCDDAC_SW0 0x00005b50u
#define CYREG_LCDDAC_SW1 0x00005b51u
#define CYREG_LCDDAC_SW2 0x00005b52u
#define CYREG_LCDDAC_SW3 0x00005b53u
#define CYREG_LCDDAC_SW4 0x00005b54u
#define CYDEV_ANAIF_RT_SC_BASE 0x00005b56u
#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u
#define CYREG_SC_MISC 0x00005b56u
#define CYDEV_ANAIF_RT_BUS_BASE 0x00005b58u
#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u
#define CYREG_BUS_SW0 0x00005b58u
#define CYREG_BUS_SW2 0x00005b5au
#define CYREG_BUS_SW3 0x00005b5bu
#define CYDEV_ANAIF_RT_DFT_BASE 0x00005b5cu
#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u
#define CYREG_DFT_CR0 0x00005b5cu
#define CYREG_DFT_CR1 0x00005b5du
#define CYREG_DFT_CR2 0x00005b5eu
#define CYREG_DFT_CR3 0x00005b5fu
#define CYREG_DFT_CR4 0x00005b60u
#define CYREG_DFT_CR5 0x00005b61u
#define CYDEV_ANAIF_WRK_BASE 0x00005b80u
#define CYDEV_ANAIF_WRK_SIZE 0x0000001du
#define CYDEV_ANAIF_WRK_DAC0_BASE 0x00005b80u
#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u
#define CYREG_DAC0_D 0x00005b80u
#define CYDEV_ANAIF_WRK_DAC1_BASE 0x00005b81u
#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u
#define CYREG_DAC1_D 0x00005b81u
#define CYDEV_ANAIF_WRK_DAC2_BASE 0x00005b82u
#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u
#define CYREG_DAC2_D 0x00005b82u
#define CYDEV_ANAIF_WRK_DAC3_BASE 0x00005b83u
#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u
#define CYREG_DAC3_D 0x00005b83u
#define CYDEV_ANAIF_WRK_DSM0_BASE 0x00005b88u
#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u
#define CYREG_DSM0_OUT0 0x00005b88u
#define CYREG_DSM0_OUT1 0x00005b89u
#define CYDEV_ANAIF_WRK_LUT_BASE 0x00005b90u
#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u
#define CYREG_LUT_SR 0x00005b90u
#define CYREG_LUT_WRK1 0x00005b91u
#define CYREG_LUT_MSK 0x00005b92u
#define CYREG_LUT_CLK 0x00005b93u
#define CYREG_LUT_CPTR 0x00005b94u
#define CYDEV_ANAIF_WRK_CMP_BASE 0x00005b96u
#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u
#define CYREG_CMP_WRK 0x00005b96u
#define CYREG_CMP_TST 0x00005b97u
#define CYDEV_ANAIF_WRK_SC_BASE 0x00005b98u
#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u
#define CYREG_SC_SR 0x00005b98u
#define CYREG_SC_WRK1 0x00005b99u
#define CYREG_SC_MSK 0x00005b9au
#define CYREG_SC_CMPINV 0x00005b9bu
#define CYREG_SC_CPTR 0x00005b9cu
#define CYDEV_USB_BASE 0x00006000u
#define CYDEV_USB_SIZE 0x00000300u
#define CYREG_USB_EP0_DR0 0x00006000u
#define CYREG_USB_EP0_DR1 0x00006001u
#define CYREG_USB_EP0_DR2 0x00006002u
#define CYREG_USB_EP0_DR3 0x00006003u
#define CYREG_USB_EP0_DR4 0x00006004u
#define CYREG_USB_EP0_DR5 0x00006005u
#define CYREG_USB_EP0_DR6 0x00006006u
#define CYREG_USB_EP0_DR7 0x00006007u
#define CYREG_USB_CR0 0x00006008u
#define CYREG_USB_CR1 0x00006009u
#define CYREG_USB_SIE_EP_INT_EN 0x0000600au
#define CYREG_USB_SIE_EP_INT_SR 0x0000600bu
#define CYDEV_USB_SIE_EP1_BASE 0x0000600cu
#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u
#define CYREG_USB_SIE_EP1_CNT0 0x0000600cu
#define CYREG_USB_SIE_EP1_CNT1 0x0000600du
#define CYREG_USB_SIE_EP1_CR0 0x0000600eu
#define CYREG_USB_USBIO_CR0 0x00006010u
#define CYREG_USB_USBIO_CR2 0x00006011u
#define CYREG_USB_USBIO_CR1 0x00006012u
#define CYREG_USB_DYN_RECONFIG 0x00006014u
#define CYREG_USB_SOF0 0x00006018u
#define CYREG_USB_SOF1 0x00006019u
#define CYDEV_USB_SIE_EP2_BASE 0x0000601cu
#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u
#define CYREG_USB_SIE_EP2_CNT0 0x0000601cu
#define CYREG_USB_SIE_EP2_CNT1 0x0000601du
#define CYREG_USB_SIE_EP2_CR0 0x0000601eu
#define CYREG_USB_OSCLK_DR0 0x00006020u
#define CYREG_USB_OSCLK_DR1 0x00006021u
#define CYREG_USB_EP0_CR 0x00006028u
#define CYREG_USB_EP0_CNT 0x00006029u
#define CYDEV_USB_SIE_EP3_BASE 0x0000602cu
#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u
#define CYREG_USB_SIE_EP3_CNT0 0x0000602cu
#define CYREG_USB_SIE_EP3_CNT1 0x0000602du
#define CYREG_USB_SIE_EP3_CR0 0x0000602eu
#define CYDEV_USB_SIE_EP4_BASE 0x0000603cu
#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u
#define CYREG_USB_SIE_EP4_CNT0 0x0000603cu
#define CYREG_USB_SIE_EP4_CNT1 0x0000603du
#define CYREG_USB_SIE_EP4_CR0 0x0000603eu
#define CYDEV_USB_SIE_EP5_BASE 0x0000604cu
#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u
#define CYREG_USB_SIE_EP5_CNT0 0x0000604cu
#define CYREG_USB_SIE_EP5_CNT1 0x0000604du
#define CYREG_USB_SIE_EP5_CR0 0x0000604eu
#define CYDEV_USB_SIE_EP6_BASE 0x0000605cu
#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u
#define CYREG_USB_SIE_EP6_CNT0 0x0000605cu
#define CYREG_USB_SIE_EP6_CNT1 0x0000605du
#define CYREG_USB_SIE_EP6_CR0 0x0000605eu
#define CYDEV_USB_SIE_EP7_BASE 0x0000606cu
#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u
#define CYREG_USB_SIE_EP7_CNT0 0x0000606cu
#define CYREG_USB_SIE_EP7_CNT1 0x0000606du
#define CYREG_USB_SIE_EP7_CR0 0x0000606eu
#define CYDEV_USB_SIE_EP8_BASE 0x0000607cu
#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u
#define CYREG_USB_SIE_EP8_CNT0 0x0000607cu
#define CYREG_USB_SIE_EP8_CNT1 0x0000607du
#define CYREG_USB_SIE_EP8_CR0 0x0000607eu
#define CYDEV_USB_ARB_EP1_BASE 0x00006080u
#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u
#define CYREG_USB_ARB_EP1_CFG 0x00006080u
#define CYREG_USB_ARB_EP1_INT_EN 0x00006081u
#define CYREG_USB_ARB_EP1_SR 0x00006082u
#define CYDEV_USB_ARB_RW1_BASE 0x00006084u
#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u
#define CYREG_USB_ARB_RW1_WA 0x00006084u
#define CYREG_USB_ARB_RW1_WA_MSB 0x00006085u
#define CYREG_USB_ARB_RW1_RA 0x00006086u
#define CYREG_USB_ARB_RW1_RA_MSB 0x00006087u
#define CYREG_USB_ARB_RW1_DR 0x00006088u
#define CYREG_USB_BUF_SIZE 0x0000608cu
#define CYREG_USB_EP_ACTIVE 0x0000608eu
#define CYREG_USB_EP_TYPE 0x0000608fu
#define CYDEV_USB_ARB_EP2_BASE 0x00006090u
#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u
#define CYREG_USB_ARB_EP2_CFG 0x00006090u
#define CYREG_USB_ARB_EP2_INT_EN 0x00006091u
#define CYREG_USB_ARB_EP2_SR 0x00006092u
#define CYDEV_USB_ARB_RW2_BASE 0x00006094u
#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u
#define CYREG_USB_ARB_RW2_WA 0x00006094u
#define CYREG_USB_ARB_RW2_WA_MSB 0x00006095u
#define CYREG_USB_ARB_RW2_RA 0x00006096u
#define CYREG_USB_ARB_RW2_RA_MSB 0x00006097u
#define CYREG_USB_ARB_RW2_DR 0x00006098u
#define CYREG_USB_ARB_CFG 0x0000609cu
#define CYREG_USB_USB_CLK_EN 0x0000609du
#define CYREG_USB_ARB_INT_EN 0x0000609eu
#define CYREG_USB_ARB_INT_SR 0x0000609fu
#define CYDEV_USB_ARB_EP3_BASE 0x000060a0u
#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u
#define CYREG_USB_ARB_EP3_CFG 0x000060a0u
#define CYREG_USB_ARB_EP3_INT_EN 0x000060a1u
#define CYREG_USB_ARB_EP3_SR 0x000060a2u
#define CYDEV_USB_ARB_RW3_BASE 0x000060a4u
#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u
#define CYREG_USB_ARB_RW3_WA 0x000060a4u
#define CYREG_USB_ARB_RW3_WA_MSB 0x000060a5u
#define CYREG_USB_ARB_RW3_RA 0x000060a6u
#define CYREG_USB_ARB_RW3_RA_MSB 0x000060a7u
#define CYREG_USB_ARB_RW3_DR 0x000060a8u
#define CYREG_USB_CWA 0x000060acu
#define CYREG_USB_CWA_MSB 0x000060adu
#define CYDEV_USB_ARB_EP4_BASE 0x000060b0u
#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u
#define CYREG_USB_ARB_EP4_CFG 0x000060b0u
#define CYREG_USB_ARB_EP4_INT_EN 0x000060b1u
#define CYREG_USB_ARB_EP4_SR 0x000060b2u
#define CYDEV_USB_ARB_RW4_BASE 0x000060b4u
#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u
#define CYREG_USB_ARB_RW4_WA 0x000060b4u
#define CYREG_USB_ARB_RW4_WA_MSB 0x000060b5u
#define CYREG_USB_ARB_RW4_RA 0x000060b6u
#define CYREG_USB_ARB_RW4_RA_MSB 0x000060b7u
#define CYREG_USB_ARB_RW4_DR 0x000060b8u
#define CYREG_USB_DMA_THRES 0x000060bcu
#define CYREG_USB_DMA_THRES_MSB 0x000060bdu
#define CYDEV_USB_ARB_EP5_BASE 0x000060c0u
#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u
#define CYREG_USB_ARB_EP5_CFG 0x000060c0u
#define CYREG_USB_ARB_EP5_INT_EN 0x000060c1u
#define CYREG_USB_ARB_EP5_SR 0x000060c2u
#define CYDEV_USB_ARB_RW5_BASE 0x000060c4u
#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u
#define CYREG_USB_ARB_RW5_WA 0x000060c4u
#define CYREG_USB_ARB_RW5_WA_MSB 0x000060c5u
#define CYREG_USB_ARB_RW5_RA 0x000060c6u
#define CYREG_USB_ARB_RW5_RA_MSB 0x000060c7u
#define CYREG_USB_ARB_RW5_DR 0x000060c8u
#define CYREG_USB_BUS_RST_CNT 0x000060ccu
#define CYDEV_USB_ARB_EP6_BASE 0x000060d0u
#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u
#define CYREG_USB_ARB_EP6_CFG 0x000060d0u
#define CYREG_USB_ARB_EP6_INT_EN 0x000060d1u
#define CYREG_USB_ARB_EP6_SR 0x000060d2u
#define CYDEV_USB_ARB_RW6_BASE 0x000060d4u
#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u
#define CYREG_USB_ARB_RW6_WA 0x000060d4u
#define CYREG_USB_ARB_RW6_WA_MSB 0x000060d5u
#define CYREG_USB_ARB_RW6_RA 0x000060d6u
#define CYREG_USB_ARB_RW6_RA_MSB 0x000060d7u
#define CYREG_USB_ARB_RW6_DR 0x000060d8u
#define CYDEV_USB_ARB_EP7_BASE 0x000060e0u
#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u
#define CYREG_USB_ARB_EP7_CFG 0x000060e0u
#define CYREG_USB_ARB_EP7_INT_EN 0x000060e1u
#define CYREG_USB_ARB_EP7_SR 0x000060e2u
#define CYDEV_USB_ARB_RW7_BASE 0x000060e4u
#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u
#define CYREG_USB_ARB_RW7_WA 0x000060e4u
#define CYREG_USB_ARB_RW7_WA_MSB 0x000060e5u
#define CYREG_USB_ARB_RW7_RA 0x000060e6u
#define CYREG_USB_ARB_RW7_RA_MSB 0x000060e7u
#define CYREG_USB_ARB_RW7_DR 0x000060e8u
#define CYDEV_USB_ARB_EP8_BASE 0x000060f0u
#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u
#define CYREG_USB_ARB_EP8_CFG 0x000060f0u
#define CYREG_USB_ARB_EP8_INT_EN 0x000060f1u
#define CYREG_USB_ARB_EP8_SR 0x000060f2u
#define CYDEV_USB_ARB_RW8_BASE 0x000060f4u
#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u
#define CYREG_USB_ARB_RW8_WA 0x000060f4u
#define CYREG_USB_ARB_RW8_WA_MSB 0x000060f5u
#define CYREG_USB_ARB_RW8_RA 0x000060f6u
#define CYREG_USB_ARB_RW8_RA_MSB 0x000060f7u
#define CYREG_USB_ARB_RW8_DR 0x000060f8u
#define CYDEV_USB_MEM_BASE 0x00006100u
#define CYDEV_USB_MEM_SIZE 0x00000200u
#define CYREG_USB_MEM_DATA_MBASE 0x00006100u
#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u
#define CYDEV_UWRK_BASE 0x00006400u
#define CYDEV_UWRK_SIZE 0x00000b60u
#define CYDEV_UWRK_UWRK8_BASE 0x00006400u
#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u
#define CYDEV_UWRK_UWRK8_B0_BASE 0x00006400u
#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u
#define CYREG_B0_UDB00_A0 0x00006400u
#define CYREG_B0_UDB01_A0 0x00006401u
#define CYREG_B0_UDB02_A0 0x00006402u
#define CYREG_B0_UDB03_A0 0x00006403u
#define CYREG_B0_UDB04_A0 0x00006404u
#define CYREG_B0_UDB05_A0 0x00006405u
#define CYREG_B0_UDB06_A0 0x00006406u
#define CYREG_B0_UDB07_A0 0x00006407u
#define CYREG_B0_UDB08_A0 0x00006408u
#define CYREG_B0_UDB09_A0 0x00006409u
#define CYREG_B0_UDB10_A0 0x0000640au
#define CYREG_B0_UDB11_A0 0x0000640bu
#define CYREG_B0_UDB12_A0 0x0000640cu
#define CYREG_B0_UDB13_A0 0x0000640du
#define CYREG_B0_UDB14_A0 0x0000640eu
#define CYREG_B0_UDB15_A0 0x0000640fu
#define CYREG_B0_UDB00_A1 0x00006410u
#define CYREG_B0_UDB01_A1 0x00006411u
#define CYREG_B0_UDB02_A1 0x00006412u
#define CYREG_B0_UDB03_A1 0x00006413u
#define CYREG_B0_UDB04_A1 0x00006414u
#define CYREG_B0_UDB05_A1 0x00006415u
#define CYREG_B0_UDB06_A1 0x00006416u
#define CYREG_B0_UDB07_A1 0x00006417u
#define CYREG_B0_UDB08_A1 0x00006418u
#define CYREG_B0_UDB09_A1 0x00006419u
#define CYREG_B0_UDB10_A1 0x0000641au
#define CYREG_B0_UDB11_A1 0x0000641bu
#define CYREG_B0_UDB12_A1 0x0000641cu
#define CYREG_B0_UDB13_A1 0x0000641du
#define CYREG_B0_UDB14_A1 0x0000641eu
#define CYREG_B0_UDB15_A1 0x0000641fu
#define CYREG_B0_UDB00_D0 0x00006420u
#define CYREG_B0_UDB01_D0 0x00006421u
#define CYREG_B0_UDB02_D0 0x00006422u
#define CYREG_B0_UDB03_D0 0x00006423u
#define CYREG_B0_UDB04_D0 0x00006424u
#define CYREG_B0_UDB05_D0 0x00006425u
#define CYREG_B0_UDB06_D0 0x00006426u
#define CYREG_B0_UDB07_D0 0x00006427u
#define CYREG_B0_UDB08_D0 0x00006428u
#define CYREG_B0_UDB09_D0 0x00006429u
#define CYREG_B0_UDB10_D0 0x0000642au
#define CYREG_B0_UDB11_D0 0x0000642bu
#define CYREG_B0_UDB12_D0 0x0000642cu
#define CYREG_B0_UDB13_D0 0x0000642du
#define CYREG_B0_UDB14_D0 0x0000642eu
#define CYREG_B0_UDB15_D0 0x0000642fu
#define CYREG_B0_UDB00_D1 0x00006430u
#define CYREG_B0_UDB01_D1 0x00006431u
#define CYREG_B0_UDB02_D1 0x00006432u
#define CYREG_B0_UDB03_D1 0x00006433u
#define CYREG_B0_UDB04_D1 0x00006434u
#define CYREG_B0_UDB05_D1 0x00006435u
#define CYREG_B0_UDB06_D1 0x00006436u
#define CYREG_B0_UDB07_D1 0x00006437u
#define CYREG_B0_UDB08_D1 0x00006438u
#define CYREG_B0_UDB09_D1 0x00006439u
#define CYREG_B0_UDB10_D1 0x0000643au
#define CYREG_B0_UDB11_D1 0x0000643bu
#define CYREG_B0_UDB12_D1 0x0000643cu
#define CYREG_B0_UDB13_D1 0x0000643du
#define CYREG_B0_UDB14_D1 0x0000643eu
#define CYREG_B0_UDB15_D1 0x0000643fu
#define CYREG_B0_UDB00_F0 0x00006440u
#define CYREG_B0_UDB01_F0 0x00006441u
#define CYREG_B0_UDB02_F0 0x00006442u
#define CYREG_B0_UDB03_F0 0x00006443u
#define CYREG_B0_UDB04_F0 0x00006444u
#define CYREG_B0_UDB05_F0 0x00006445u
#define CYREG_B0_UDB06_F0 0x00006446u
#define CYREG_B0_UDB07_F0 0x00006447u
#define CYREG_B0_UDB08_F0 0x00006448u
#define CYREG_B0_UDB09_F0 0x00006449u
#define CYREG_B0_UDB10_F0 0x0000644au
#define CYREG_B0_UDB11_F0 0x0000644bu
#define CYREG_B0_UDB12_F0 0x0000644cu
#define CYREG_B0_UDB13_F0 0x0000644du
#define CYREG_B0_UDB14_F0 0x0000644eu
#define CYREG_B0_UDB15_F0 0x0000644fu
#define CYREG_B0_UDB00_F1 0x00006450u
#define CYREG_B0_UDB01_F1 0x00006451u
#define CYREG_B0_UDB02_F1 0x00006452u
#define CYREG_B0_UDB03_F1 0x00006453u
#define CYREG_B0_UDB04_F1 0x00006454u
#define CYREG_B0_UDB05_F1 0x00006455u
#define CYREG_B0_UDB06_F1 0x00006456u
#define CYREG_B0_UDB07_F1 0x00006457u
#define CYREG_B0_UDB08_F1 0x00006458u
#define CYREG_B0_UDB09_F1 0x00006459u
#define CYREG_B0_UDB10_F1 0x0000645au
#define CYREG_B0_UDB11_F1 0x0000645bu
#define CYREG_B0_UDB12_F1 0x0000645cu
#define CYREG_B0_UDB13_F1 0x0000645du
#define CYREG_B0_UDB14_F1 0x0000645eu
#define CYREG_B0_UDB15_F1 0x0000645fu
#define CYREG_B0_UDB00_ST 0x00006460u
#define CYREG_B0_UDB01_ST 0x00006461u
#define CYREG_B0_UDB02_ST 0x00006462u
#define CYREG_B0_UDB03_ST 0x00006463u
#define CYREG_B0_UDB04_ST 0x00006464u
#define CYREG_B0_UDB05_ST 0x00006465u
#define CYREG_B0_UDB06_ST 0x00006466u
#define CYREG_B0_UDB07_ST 0x00006467u
#define CYREG_B0_UDB08_ST 0x00006468u
#define CYREG_B0_UDB09_ST 0x00006469u
#define CYREG_B0_UDB10_ST 0x0000646au
#define CYREG_B0_UDB11_ST 0x0000646bu
#define CYREG_B0_UDB12_ST 0x0000646cu
#define CYREG_B0_UDB13_ST 0x0000646du
#define CYREG_B0_UDB14_ST 0x0000646eu
#define CYREG_B0_UDB15_ST 0x0000646fu
#define CYREG_B0_UDB00_CTL 0x00006470u
#define CYREG_B0_UDB01_CTL 0x00006471u
#define CYREG_B0_UDB02_CTL 0x00006472u
#define CYREG_B0_UDB03_CTL 0x00006473u
#define CYREG_B0_UDB04_CTL 0x00006474u
#define CYREG_B0_UDB05_CTL 0x00006475u
#define CYREG_B0_UDB06_CTL 0x00006476u
#define CYREG_B0_UDB07_CTL 0x00006477u
#define CYREG_B0_UDB08_CTL 0x00006478u
#define CYREG_B0_UDB09_CTL 0x00006479u
#define CYREG_B0_UDB10_CTL 0x0000647au
#define CYREG_B0_UDB11_CTL 0x0000647bu
#define CYREG_B0_UDB12_CTL 0x0000647cu
#define CYREG_B0_UDB13_CTL 0x0000647du
#define CYREG_B0_UDB14_CTL 0x0000647eu
#define CYREG_B0_UDB15_CTL 0x0000647fu
#define CYREG_B0_UDB00_MSK 0x00006480u
#define CYREG_B0_UDB01_MSK 0x00006481u
#define CYREG_B0_UDB02_MSK 0x00006482u
#define CYREG_B0_UDB03_MSK 0x00006483u
#define CYREG_B0_UDB04_MSK 0x00006484u
#define CYREG_B0_UDB05_MSK 0x00006485u
#define CYREG_B0_UDB06_MSK 0x00006486u
#define CYREG_B0_UDB07_MSK 0x00006487u
#define CYREG_B0_UDB08_MSK 0x00006488u
#define CYREG_B0_UDB09_MSK 0x00006489u
#define CYREG_B0_UDB10_MSK 0x0000648au
#define CYREG_B0_UDB11_MSK 0x0000648bu
#define CYREG_B0_UDB12_MSK 0x0000648cu
#define CYREG_B0_UDB13_MSK 0x0000648du
#define CYREG_B0_UDB14_MSK 0x0000648eu
#define CYREG_B0_UDB15_MSK 0x0000648fu
#define CYREG_B0_UDB00_ACTL 0x00006490u
#define CYREG_B0_UDB01_ACTL 0x00006491u
#define CYREG_B0_UDB02_ACTL 0x00006492u
#define CYREG_B0_UDB03_ACTL 0x00006493u
#define CYREG_B0_UDB04_ACTL 0x00006494u
#define CYREG_B0_UDB05_ACTL 0x00006495u
#define CYREG_B0_UDB06_ACTL 0x00006496u
#define CYREG_B0_UDB07_ACTL 0x00006497u
#define CYREG_B0_UDB08_ACTL 0x00006498u
#define CYREG_B0_UDB09_ACTL 0x00006499u
#define CYREG_B0_UDB10_ACTL 0x0000649au
#define CYREG_B0_UDB11_ACTL 0x0000649bu
#define CYREG_B0_UDB12_ACTL 0x0000649cu
#define CYREG_B0_UDB13_ACTL 0x0000649du
#define CYREG_B0_UDB14_ACTL 0x0000649eu
#define CYREG_B0_UDB15_ACTL 0x0000649fu
#define CYREG_B0_UDB00_MC 0x000064a0u
#define CYREG_B0_UDB01_MC 0x000064a1u
#define CYREG_B0_UDB02_MC 0x000064a2u
#define CYREG_B0_UDB03_MC 0x000064a3u
#define CYREG_B0_UDB04_MC 0x000064a4u
#define CYREG_B0_UDB05_MC 0x000064a5u
#define CYREG_B0_UDB06_MC 0x000064a6u
#define CYREG_B0_UDB07_MC 0x000064a7u
#define CYREG_B0_UDB08_MC 0x000064a8u
#define CYREG_B0_UDB09_MC 0x000064a9u
#define CYREG_B0_UDB10_MC 0x000064aau
#define CYREG_B0_UDB11_MC 0x000064abu
#define CYREG_B0_UDB12_MC 0x000064acu
#define CYREG_B0_UDB13_MC 0x000064adu
#define CYREG_B0_UDB14_MC 0x000064aeu
#define CYREG_B0_UDB15_MC 0x000064afu
#define CYDEV_UWRK_UWRK8_B1_BASE 0x00006500u
#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u
#define CYREG_B1_UDB04_A0 0x00006504u
#define CYREG_B1_UDB05_A0 0x00006505u
#define CYREG_B1_UDB06_A0 0x00006506u
#define CYREG_B1_UDB07_A0 0x00006507u
#define CYREG_B1_UDB08_A0 0x00006508u
#define CYREG_B1_UDB09_A0 0x00006509u
#define CYREG_B1_UDB10_A0 0x0000650au
#define CYREG_B1_UDB11_A0 0x0000650bu
#define CYREG_B1_UDB04_A1 0x00006514u
#define CYREG_B1_UDB05_A1 0x00006515u
#define CYREG_B1_UDB06_A1 0x00006516u
#define CYREG_B1_UDB07_A1 0x00006517u
#define CYREG_B1_UDB08_A1 0x00006518u
#define CYREG_B1_UDB09_A1 0x00006519u
#define CYREG_B1_UDB10_A1 0x0000651au
#define CYREG_B1_UDB11_A1 0x0000651bu
#define CYREG_B1_UDB04_D0 0x00006524u
#define CYREG_B1_UDB05_D0 0x00006525u
#define CYREG_B1_UDB06_D0 0x00006526u
#define CYREG_B1_UDB07_D0 0x00006527u
#define CYREG_B1_UDB08_D0 0x00006528u
#define CYREG_B1_UDB09_D0 0x00006529u
#define CYREG_B1_UDB10_D0 0x0000652au
#define CYREG_B1_UDB11_D0 0x0000652bu
#define CYREG_B1_UDB04_D1 0x00006534u
#define CYREG_B1_UDB05_D1 0x00006535u
#define CYREG_B1_UDB06_D1 0x00006536u
#define CYREG_B1_UDB07_D1 0x00006537u
#define CYREG_B1_UDB08_D1 0x00006538u
#define CYREG_B1_UDB09_D1 0x00006539u
#define CYREG_B1_UDB10_D1 0x0000653au
#define CYREG_B1_UDB11_D1 0x0000653bu
#define CYREG_B1_UDB04_F0 0x00006544u
#define CYREG_B1_UDB05_F0 0x00006545u
#define CYREG_B1_UDB06_F0 0x00006546u
#define CYREG_B1_UDB07_F0 0x00006547u
#define CYREG_B1_UDB08_F0 0x00006548u
#define CYREG_B1_UDB09_F0 0x00006549u
#define CYREG_B1_UDB10_F0 0x0000654au
#define CYREG_B1_UDB11_F0 0x0000654bu
#define CYREG_B1_UDB04_F1 0x00006554u
#define CYREG_B1_UDB05_F1 0x00006555u
#define CYREG_B1_UDB06_F1 0x00006556u
#define CYREG_B1_UDB07_F1 0x00006557u
#define CYREG_B1_UDB08_F1 0x00006558u
#define CYREG_B1_UDB09_F1 0x00006559u
#define CYREG_B1_UDB10_F1 0x0000655au
#define CYREG_B1_UDB11_F1 0x0000655bu
#define CYREG_B1_UDB04_ST 0x00006564u
#define CYREG_B1_UDB05_ST 0x00006565u
#define CYREG_B1_UDB06_ST 0x00006566u
#define CYREG_B1_UDB07_ST 0x00006567u
#define CYREG_B1_UDB08_ST 0x00006568u
#define CYREG_B1_UDB09_ST 0x00006569u
#define CYREG_B1_UDB10_ST 0x0000656au
#define CYREG_B1_UDB11_ST 0x0000656bu
#define CYREG_B1_UDB04_CTL 0x00006574u
#define CYREG_B1_UDB05_CTL 0x00006575u
#define CYREG_B1_UDB06_CTL 0x00006576u
#define CYREG_B1_UDB07_CTL 0x00006577u
#define CYREG_B1_UDB08_CTL 0x00006578u
#define CYREG_B1_UDB09_CTL 0x00006579u
#define CYREG_B1_UDB10_CTL 0x0000657au
#define CYREG_B1_UDB11_CTL 0x0000657bu
#define CYREG_B1_UDB04_MSK 0x00006584u
#define CYREG_B1_UDB05_MSK 0x00006585u
#define CYREG_B1_UDB06_MSK 0x00006586u
#define CYREG_B1_UDB07_MSK 0x00006587u
#define CYREG_B1_UDB08_MSK 0x00006588u
#define CYREG_B1_UDB09_MSK 0x00006589u
#define CYREG_B1_UDB10_MSK 0x0000658au
#define CYREG_B1_UDB11_MSK 0x0000658bu
#define CYREG_B1_UDB04_ACTL 0x00006594u
#define CYREG_B1_UDB05_ACTL 0x00006595u
#define CYREG_B1_UDB06_ACTL 0x00006596u
#define CYREG_B1_UDB07_ACTL 0x00006597u
#define CYREG_B1_UDB08_ACTL 0x00006598u
#define CYREG_B1_UDB09_ACTL 0x00006599u
#define CYREG_B1_UDB10_ACTL 0x0000659au
#define CYREG_B1_UDB11_ACTL 0x0000659bu
#define CYREG_B1_UDB04_MC 0x000065a4u
#define CYREG_B1_UDB05_MC 0x000065a5u
#define CYREG_B1_UDB06_MC 0x000065a6u
#define CYREG_B1_UDB07_MC 0x000065a7u
#define CYREG_B1_UDB08_MC 0x000065a8u
#define CYREG_B1_UDB09_MC 0x000065a9u
#define CYREG_B1_UDB10_MC 0x000065aau
#define CYREG_B1_UDB11_MC 0x000065abu
#define CYDEV_UWRK_UWRK16_BASE 0x00006800u
#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u
#define CYDEV_UWRK_UWRK16_CAT_BASE 0x00006800u
#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u
#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x00006800u
#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u
#define CYREG_B0_UDB00_A0_A1 0x00006800u
#define CYREG_B0_UDB01_A0_A1 0x00006802u
#define CYREG_B0_UDB02_A0_A1 0x00006804u
#define CYREG_B0_UDB03_A0_A1 0x00006806u
#define CYREG_B0_UDB04_A0_A1 0x00006808u
#define CYREG_B0_UDB05_A0_A1 0x0000680au
#define CYREG_B0_UDB06_A0_A1 0x0000680cu
#define CYREG_B0_UDB07_A0_A1 0x0000680eu
#define CYREG_B0_UDB08_A0_A1 0x00006810u
#define CYREG_B0_UDB09_A0_A1 0x00006812u
#define CYREG_B0_UDB10_A0_A1 0x00006814u
#define CYREG_B0_UDB11_A0_A1 0x00006816u
#define CYREG_B0_UDB12_A0_A1 0x00006818u
#define CYREG_B0_UDB13_A0_A1 0x0000681au
#define CYREG_B0_UDB14_A0_A1 0x0000681cu
#define CYREG_B0_UDB15_A0_A1 0x0000681eu
#define CYREG_B0_UDB00_D0_D1 0x00006840u
#define CYREG_B0_UDB01_D0_D1 0x00006842u
#define CYREG_B0_UDB02_D0_D1 0x00006844u
#define CYREG_B0_UDB03_D0_D1 0x00006846u
#define CYREG_B0_UDB04_D0_D1 0x00006848u
#define CYREG_B0_UDB05_D0_D1 0x0000684au
#define CYREG_B0_UDB06_D0_D1 0x0000684cu
#define CYREG_B0_UDB07_D0_D1 0x0000684eu
#define CYREG_B0_UDB08_D0_D1 0x00006850u
#define CYREG_B0_UDB09_D0_D1 0x00006852u
#define CYREG_B0_UDB10_D0_D1 0x00006854u
#define CYREG_B0_UDB11_D0_D1 0x00006856u
#define CYREG_B0_UDB12_D0_D1 0x00006858u
#define CYREG_B0_UDB13_D0_D1 0x0000685au
#define CYREG_B0_UDB14_D0_D1 0x0000685cu
#define CYREG_B0_UDB15_D0_D1 0x0000685eu
#define CYREG_B0_UDB00_F0_F1 0x00006880u
#define CYREG_B0_UDB01_F0_F1 0x00006882u
#define CYREG_B0_UDB02_F0_F1 0x00006884u
#define CYREG_B0_UDB03_F0_F1 0x00006886u
#define CYREG_B0_UDB04_F0_F1 0x00006888u
#define CYREG_B0_UDB05_F0_F1 0x0000688au
#define CYREG_B0_UDB06_F0_F1 0x0000688cu
#define CYREG_B0_UDB07_F0_F1 0x0000688eu
#define CYREG_B0_UDB08_F0_F1 0x00006890u
#define CYREG_B0_UDB09_F0_F1 0x00006892u
#define CYREG_B0_UDB10_F0_F1 0x00006894u
#define CYREG_B0_UDB11_F0_F1 0x00006896u
#define CYREG_B0_UDB12_F0_F1 0x00006898u
#define CYREG_B0_UDB13_F0_F1 0x0000689au
#define CYREG_B0_UDB14_F0_F1 0x0000689cu
#define CYREG_B0_UDB15_F0_F1 0x0000689eu
#define CYREG_B0_UDB00_ST_CTL 0x000068c0u
#define CYREG_B0_UDB01_ST_CTL 0x000068c2u
#define CYREG_B0_UDB02_ST_CTL 0x000068c4u
#define CYREG_B0_UDB03_ST_CTL 0x000068c6u
#define CYREG_B0_UDB04_ST_CTL 0x000068c8u
#define CYREG_B0_UDB05_ST_CTL 0x000068cau
#define CYREG_B0_UDB06_ST_CTL 0x000068ccu
#define CYREG_B0_UDB07_ST_CTL 0x000068ceu
#define CYREG_B0_UDB08_ST_CTL 0x000068d0u
#define CYREG_B0_UDB09_ST_CTL 0x000068d2u
#define CYREG_B0_UDB10_ST_CTL 0x000068d4u
#define CYREG_B0_UDB11_ST_CTL 0x000068d6u
#define CYREG_B0_UDB12_ST_CTL 0x000068d8u
#define CYREG_B0_UDB13_ST_CTL 0x000068dau
#define CYREG_B0_UDB14_ST_CTL 0x000068dcu
#define CYREG_B0_UDB15_ST_CTL 0x000068deu
#define CYREG_B0_UDB00_MSK_ACTL 0x00006900u
#define CYREG_B0_UDB01_MSK_ACTL 0x00006902u
#define CYREG_B0_UDB02_MSK_ACTL 0x00006904u
#define CYREG_B0_UDB03_MSK_ACTL 0x00006906u
#define CYREG_B0_UDB04_MSK_ACTL 0x00006908u
#define CYREG_B0_UDB05_MSK_ACTL 0x0000690au
#define CYREG_B0_UDB06_MSK_ACTL 0x0000690cu
#define CYREG_B0_UDB07_MSK_ACTL 0x0000690eu
#define CYREG_B0_UDB08_MSK_ACTL 0x00006910u
#define CYREG_B0_UDB09_MSK_ACTL 0x00006912u
#define CYREG_B0_UDB10_MSK_ACTL 0x00006914u
#define CYREG_B0_UDB11_MSK_ACTL 0x00006916u
#define CYREG_B0_UDB12_MSK_ACTL 0x00006918u
#define CYREG_B0_UDB13_MSK_ACTL 0x0000691au
#define CYREG_B0_UDB14_MSK_ACTL 0x0000691cu
#define CYREG_B0_UDB15_MSK_ACTL 0x0000691eu
#define CYREG_B0_UDB00_MC_00 0x00006940u
#define CYREG_B0_UDB01_MC_00 0x00006942u
#define CYREG_B0_UDB02_MC_00 0x00006944u
#define CYREG_B0_UDB03_MC_00 0x00006946u
#define CYREG_B0_UDB04_MC_00 0x00006948u
#define CYREG_B0_UDB05_MC_00 0x0000694au
#define CYREG_B0_UDB06_MC_00 0x0000694cu
#define CYREG_B0_UDB07_MC_00 0x0000694eu
#define CYREG_B0_UDB08_MC_00 0x00006950u
#define CYREG_B0_UDB09_MC_00 0x00006952u
#define CYREG_B0_UDB10_MC_00 0x00006954u
#define CYREG_B0_UDB11_MC_00 0x00006956u
#define CYREG_B0_UDB12_MC_00 0x00006958u
#define CYREG_B0_UDB13_MC_00 0x0000695au
#define CYREG_B0_UDB14_MC_00 0x0000695cu
#define CYREG_B0_UDB15_MC_00 0x0000695eu
#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x00006a00u
#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u
#define CYREG_B1_UDB04_A0_A1 0x00006a08u
#define CYREG_B1_UDB05_A0_A1 0x00006a0au
#define CYREG_B1_UDB06_A0_A1 0x00006a0cu
#define CYREG_B1_UDB07_A0_A1 0x00006a0eu
#define CYREG_B1_UDB08_A0_A1 0x00006a10u
#define CYREG_B1_UDB09_A0_A1 0x00006a12u
#define CYREG_B1_UDB10_A0_A1 0x00006a14u
#define CYREG_B1_UDB11_A0_A1 0x00006a16u
#define CYREG_B1_UDB04_D0_D1 0x00006a48u
#define CYREG_B1_UDB05_D0_D1 0x00006a4au
#define CYREG_B1_UDB06_D0_D1 0x00006a4cu
#define CYREG_B1_UDB07_D0_D1 0x00006a4eu
#define CYREG_B1_UDB08_D0_D1 0x00006a50u
#define CYREG_B1_UDB09_D0_D1 0x00006a52u
#define CYREG_B1_UDB10_D0_D1 0x00006a54u
#define CYREG_B1_UDB11_D0_D1 0x00006a56u
#define CYREG_B1_UDB04_F0_F1 0x00006a88u
#define CYREG_B1_UDB05_F0_F1 0x00006a8au
#define CYREG_B1_UDB06_F0_F1 0x00006a8cu
#define CYREG_B1_UDB07_F0_F1 0x00006a8eu
#define CYREG_B1_UDB08_F0_F1 0x00006a90u
#define CYREG_B1_UDB09_F0_F1 0x00006a92u
#define CYREG_B1_UDB10_F0_F1 0x00006a94u
#define CYREG_B1_UDB11_F0_F1 0x00006a96u
#define CYREG_B1_UDB04_ST_CTL 0x00006ac8u
#define CYREG_B1_UDB05_ST_CTL 0x00006acau
#define CYREG_B1_UDB06_ST_CTL 0x00006accu
#define CYREG_B1_UDB07_ST_CTL 0x00006aceu
#define CYREG_B1_UDB08_ST_CTL 0x00006ad0u
#define CYREG_B1_UDB09_ST_CTL 0x00006ad2u
#define CYREG_B1_UDB10_ST_CTL 0x00006ad4u
#define CYREG_B1_UDB11_ST_CTL 0x00006ad6u
#define CYREG_B1_UDB04_MSK_ACTL 0x00006b08u
#define CYREG_B1_UDB05_MSK_ACTL 0x00006b0au
#define CYREG_B1_UDB06_MSK_ACTL 0x00006b0cu
#define CYREG_B1_UDB07_MSK_ACTL 0x00006b0eu
#define CYREG_B1_UDB08_MSK_ACTL 0x00006b10u
#define CYREG_B1_UDB09_MSK_ACTL 0x00006b12u
#define CYREG_B1_UDB10_MSK_ACTL 0x00006b14u
#define CYREG_B1_UDB11_MSK_ACTL 0x00006b16u
#define CYREG_B1_UDB04_MC_00 0x00006b48u
#define CYREG_B1_UDB05_MC_00 0x00006b4au
#define CYREG_B1_UDB06_MC_00 0x00006b4cu
#define CYREG_B1_UDB07_MC_00 0x00006b4eu
#define CYREG_B1_UDB08_MC_00 0x00006b50u
#define CYREG_B1_UDB09_MC_00 0x00006b52u
#define CYREG_B1_UDB10_MC_00 0x00006b54u
#define CYREG_B1_UDB11_MC_00 0x00006b56u
#define CYDEV_UWRK_UWRK16_DEF_BASE 0x00006800u
#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu
#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x00006800u
#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu
#define CYREG_B0_UDB00_01_A0 0x00006800u
#define CYREG_B0_UDB01_02_A0 0x00006802u
#define CYREG_B0_UDB02_03_A0 0x00006804u
#define CYREG_B0_UDB03_04_A0 0x00006806u
#define CYREG_B0_UDB04_05_A0 0x00006808u
#define CYREG_B0_UDB05_06_A0 0x0000680au
#define CYREG_B0_UDB06_07_A0 0x0000680cu
#define CYREG_B0_UDB07_08_A0 0x0000680eu
#define CYREG_B0_UDB08_09_A0 0x00006810u
#define CYREG_B0_UDB09_10_A0 0x00006812u
#define CYREG_B0_UDB10_11_A0 0x00006814u
#define CYREG_B0_UDB11_12_A0 0x00006816u
#define CYREG_B0_UDB12_13_A0 0x00006818u
#define CYREG_B0_UDB13_14_A0 0x0000681au
#define CYREG_B0_UDB14_15_A0 0x0000681cu
#define CYREG_B0_UDB00_01_A1 0x00006820u
#define CYREG_B0_UDB01_02_A1 0x00006822u
#define CYREG_B0_UDB02_03_A1 0x00006824u
#define CYREG_B0_UDB03_04_A1 0x00006826u
#define CYREG_B0_UDB04_05_A1 0x00006828u
#define CYREG_B0_UDB05_06_A1 0x0000682au
#define CYREG_B0_UDB06_07_A1 0x0000682cu
#define CYREG_B0_UDB07_08_A1 0x0000682eu
#define CYREG_B0_UDB08_09_A1 0x00006830u
#define CYREG_B0_UDB09_10_A1 0x00006832u
#define CYREG_B0_UDB10_11_A1 0x00006834u
#define CYREG_B0_UDB11_12_A1 0x00006836u
#define CYREG_B0_UDB12_13_A1 0x00006838u
#define CYREG_B0_UDB13_14_A1 0x0000683au
#define CYREG_B0_UDB14_15_A1 0x0000683cu
#define CYREG_B0_UDB00_01_D0 0x00006840u
#define CYREG_B0_UDB01_02_D0 0x00006842u
#define CYREG_B0_UDB02_03_D0 0x00006844u
#define CYREG_B0_UDB03_04_D0 0x00006846u
#define CYREG_B0_UDB04_05_D0 0x00006848u
#define CYREG_B0_UDB05_06_D0 0x0000684au
#define CYREG_B0_UDB06_07_D0 0x0000684cu
#define CYREG_B0_UDB07_08_D0 0x0000684eu
#define CYREG_B0_UDB08_09_D0 0x00006850u
#define CYREG_B0_UDB09_10_D0 0x00006852u
#define CYREG_B0_UDB10_11_D0 0x00006854u
#define CYREG_B0_UDB11_12_D0 0x00006856u
#define CYREG_B0_UDB12_13_D0 0x00006858u
#define CYREG_B0_UDB13_14_D0 0x0000685au
#define CYREG_B0_UDB14_15_D0 0x0000685cu
#define CYREG_B0_UDB00_01_D1 0x00006860u
#define CYREG_B0_UDB01_02_D1 0x00006862u
#define CYREG_B0_UDB02_03_D1 0x00006864u
#define CYREG_B0_UDB03_04_D1 0x00006866u
#define CYREG_B0_UDB04_05_D1 0x00006868u
#define CYREG_B0_UDB05_06_D1 0x0000686au
#define CYREG_B0_UDB06_07_D1 0x0000686cu
#define CYREG_B0_UDB07_08_D1 0x0000686eu
#define CYREG_B0_UDB08_09_D1 0x00006870u
#define CYREG_B0_UDB09_10_D1 0x00006872u
#define CYREG_B0_UDB10_11_D1 0x00006874u
#define CYREG_B0_UDB11_12_D1 0x00006876u
#define CYREG_B0_UDB12_13_D1 0x00006878u
#define CYREG_B0_UDB13_14_D1 0x0000687au
#define CYREG_B0_UDB14_15_D1 0x0000687cu
#define CYREG_B0_UDB00_01_F0 0x00006880u
#define CYREG_B0_UDB01_02_F0 0x00006882u
#define CYREG_B0_UDB02_03_F0 0x00006884u
#define CYREG_B0_UDB03_04_F0 0x00006886u
#define CYREG_B0_UDB04_05_F0 0x00006888u
#define CYREG_B0_UDB05_06_F0 0x0000688au
#define CYREG_B0_UDB06_07_F0 0x0000688cu
#define CYREG_B0_UDB07_08_F0 0x0000688eu
#define CYREG_B0_UDB08_09_F0 0x00006890u
#define CYREG_B0_UDB09_10_F0 0x00006892u
#define CYREG_B0_UDB10_11_F0 0x00006894u
#define CYREG_B0_UDB11_12_F0 0x00006896u
#define CYREG_B0_UDB12_13_F0 0x00006898u
#define CYREG_B0_UDB13_14_F0 0x0000689au
#define CYREG_B0_UDB14_15_F0 0x0000689cu
#define CYREG_B0_UDB00_01_F1 0x000068a0u
#define CYREG_B0_UDB01_02_F1 0x000068a2u
#define CYREG_B0_UDB02_03_F1 0x000068a4u
#define CYREG_B0_UDB03_04_F1 0x000068a6u
#define CYREG_B0_UDB04_05_F1 0x000068a8u
#define CYREG_B0_UDB05_06_F1 0x000068aau
#define CYREG_B0_UDB06_07_F1 0x000068acu
#define CYREG_B0_UDB07_08_F1 0x000068aeu
#define CYREG_B0_UDB08_09_F1 0x000068b0u
#define CYREG_B0_UDB09_10_F1 0x000068b2u
#define CYREG_B0_UDB10_11_F1 0x000068b4u
#define CYREG_B0_UDB11_12_F1 0x000068b6u
#define CYREG_B0_UDB12_13_F1 0x000068b8u
#define CYREG_B0_UDB13_14_F1 0x000068bau
#define CYREG_B0_UDB14_15_F1 0x000068bcu
#define CYREG_B0_UDB00_01_ST 0x000068c0u
#define CYREG_B0_UDB01_02_ST 0x000068c2u
#define CYREG_B0_UDB02_03_ST 0x000068c4u
#define CYREG_B0_UDB03_04_ST 0x000068c6u
#define CYREG_B0_UDB04_05_ST 0x000068c8u
#define CYREG_B0_UDB05_06_ST 0x000068cau
#define CYREG_B0_UDB06_07_ST 0x000068ccu
#define CYREG_B0_UDB07_08_ST 0x000068ceu
#define CYREG_B0_UDB08_09_ST 0x000068d0u
#define CYREG_B0_UDB09_10_ST 0x000068d2u
#define CYREG_B0_UDB10_11_ST 0x000068d4u
#define CYREG_B0_UDB11_12_ST 0x000068d6u
#define CYREG_B0_UDB12_13_ST 0x000068d8u
#define CYREG_B0_UDB13_14_ST 0x000068dau
#define CYREG_B0_UDB14_15_ST 0x000068dcu
#define CYREG_B0_UDB00_01_CTL 0x000068e0u
#define CYREG_B0_UDB01_02_CTL 0x000068e2u
#define CYREG_B0_UDB02_03_CTL 0x000068e4u
#define CYREG_B0_UDB03_04_CTL 0x000068e6u
#define CYREG_B0_UDB04_05_CTL 0x000068e8u
#define CYREG_B0_UDB05_06_CTL 0x000068eau
#define CYREG_B0_UDB06_07_CTL 0x000068ecu
#define CYREG_B0_UDB07_08_CTL 0x000068eeu
#define CYREG_B0_UDB08_09_CTL 0x000068f0u
#define CYREG_B0_UDB09_10_CTL 0x000068f2u
#define CYREG_B0_UDB10_11_CTL 0x000068f4u
#define CYREG_B0_UDB11_12_CTL 0x000068f6u
#define CYREG_B0_UDB12_13_CTL 0x000068f8u
#define CYREG_B0_UDB13_14_CTL 0x000068fau
#define CYREG_B0_UDB14_15_CTL 0x000068fcu
#define CYREG_B0_UDB00_01_MSK 0x00006900u
#define CYREG_B0_UDB01_02_MSK 0x00006902u
#define CYREG_B0_UDB02_03_MSK 0x00006904u
#define CYREG_B0_UDB03_04_MSK 0x00006906u
#define CYREG_B0_UDB04_05_MSK 0x00006908u
#define CYREG_B0_UDB05_06_MSK 0x0000690au
#define CYREG_B0_UDB06_07_MSK 0x0000690cu
#define CYREG_B0_UDB07_08_MSK 0x0000690eu
#define CYREG_B0_UDB08_09_MSK 0x00006910u
#define CYREG_B0_UDB09_10_MSK 0x00006912u
#define CYREG_B0_UDB10_11_MSK 0x00006914u
#define CYREG_B0_UDB11_12_MSK 0x00006916u
#define CYREG_B0_UDB12_13_MSK 0x00006918u
#define CYREG_B0_UDB13_14_MSK 0x0000691au
#define CYREG_B0_UDB14_15_MSK 0x0000691cu
#define CYREG_B0_UDB00_01_ACTL 0x00006920u
#define CYREG_B0_UDB01_02_ACTL 0x00006922u
#define CYREG_B0_UDB02_03_ACTL 0x00006924u
#define CYREG_B0_UDB03_04_ACTL 0x00006926u
#define CYREG_B0_UDB04_05_ACTL 0x00006928u
#define CYREG_B0_UDB05_06_ACTL 0x0000692au
#define CYREG_B0_UDB06_07_ACTL 0x0000692cu
#define CYREG_B0_UDB07_08_ACTL 0x0000692eu
#define CYREG_B0_UDB08_09_ACTL 0x00006930u
#define CYREG_B0_UDB09_10_ACTL 0x00006932u
#define CYREG_B0_UDB10_11_ACTL 0x00006934u
#define CYREG_B0_UDB11_12_ACTL 0x00006936u
#define CYREG_B0_UDB12_13_ACTL 0x00006938u
#define CYREG_B0_UDB13_14_ACTL 0x0000693au
#define CYREG_B0_UDB14_15_ACTL 0x0000693cu
#define CYREG_B0_UDB00_01_MC 0x00006940u
#define CYREG_B0_UDB01_02_MC 0x00006942u
#define CYREG_B0_UDB02_03_MC 0x00006944u
#define CYREG_B0_UDB03_04_MC 0x00006946u
#define CYREG_B0_UDB04_05_MC 0x00006948u
#define CYREG_B0_UDB05_06_MC 0x0000694au
#define CYREG_B0_UDB06_07_MC 0x0000694cu
#define CYREG_B0_UDB07_08_MC 0x0000694eu
#define CYREG_B0_UDB08_09_MC 0x00006950u
#define CYREG_B0_UDB09_10_MC 0x00006952u
#define CYREG_B0_UDB10_11_MC 0x00006954u
#define CYREG_B0_UDB11_12_MC 0x00006956u
#define CYREG_B0_UDB12_13_MC 0x00006958u
#define CYREG_B0_UDB13_14_MC 0x0000695au
#define CYREG_B0_UDB14_15_MC 0x0000695cu
#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x00006a00u
#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu
#define CYREG_B1_UDB04_05_A0 0x00006a08u
#define CYREG_B1_UDB05_06_A0 0x00006a0au
#define CYREG_B1_UDB06_07_A0 0x00006a0cu
#define CYREG_B1_UDB07_08_A0 0x00006a0eu
#define CYREG_B1_UDB08_09_A0 0x00006a10u
#define CYREG_B1_UDB09_10_A0 0x00006a12u
#define CYREG_B1_UDB10_11_A0 0x00006a14u
#define CYREG_B1_UDB11_12_A0 0x00006a16u
#define CYREG_B1_UDB04_05_A1 0x00006a28u
#define CYREG_B1_UDB05_06_A1 0x00006a2au
#define CYREG_B1_UDB06_07_A1 0x00006a2cu
#define CYREG_B1_UDB07_08_A1 0x00006a2eu
#define CYREG_B1_UDB08_09_A1 0x00006a30u
#define CYREG_B1_UDB09_10_A1 0x00006a32u
#define CYREG_B1_UDB10_11_A1 0x00006a34u
#define CYREG_B1_UDB11_12_A1 0x00006a36u
#define CYREG_B1_UDB04_05_D0 0x00006a48u
#define CYREG_B1_UDB05_06_D0 0x00006a4au
#define CYREG_B1_UDB06_07_D0 0x00006a4cu
#define CYREG_B1_UDB07_08_D0 0x00006a4eu
#define CYREG_B1_UDB08_09_D0 0x00006a50u
#define CYREG_B1_UDB09_10_D0 0x00006a52u
#define CYREG_B1_UDB10_11_D0 0x00006a54u
#define CYREG_B1_UDB11_12_D0 0x00006a56u
#define CYREG_B1_UDB04_05_D1 0x00006a68u
#define CYREG_B1_UDB05_06_D1 0x00006a6au
#define CYREG_B1_UDB06_07_D1 0x00006a6cu
#define CYREG_B1_UDB07_08_D1 0x00006a6eu
#define CYREG_B1_UDB08_09_D1 0x00006a70u
#define CYREG_B1_UDB09_10_D1 0x00006a72u
#define CYREG_B1_UDB10_11_D1 0x00006a74u
#define CYREG_B1_UDB11_12_D1 0x00006a76u
#define CYREG_B1_UDB04_05_F0 0x00006a88u
#define CYREG_B1_UDB05_06_F0 0x00006a8au
#define CYREG_B1_UDB06_07_F0 0x00006a8cu
#define CYREG_B1_UDB07_08_F0 0x00006a8eu
#define CYREG_B1_UDB08_09_F0 0x00006a90u
#define CYREG_B1_UDB09_10_F0 0x00006a92u
#define CYREG_B1_UDB10_11_F0 0x00006a94u
#define CYREG_B1_UDB11_12_F0 0x00006a96u
#define CYREG_B1_UDB04_05_F1 0x00006aa8u
#define CYREG_B1_UDB05_06_F1 0x00006aaau
#define CYREG_B1_UDB06_07_F1 0x00006aacu
#define CYREG_B1_UDB07_08_F1 0x00006aaeu
#define CYREG_B1_UDB08_09_F1 0x00006ab0u
#define CYREG_B1_UDB09_10_F1 0x00006ab2u
#define CYREG_B1_UDB10_11_F1 0x00006ab4u
#define CYREG_B1_UDB11_12_F1 0x00006ab6u
#define CYREG_B1_UDB04_05_ST 0x00006ac8u
#define CYREG_B1_UDB05_06_ST 0x00006acau
#define CYREG_B1_UDB06_07_ST 0x00006accu
#define CYREG_B1_UDB07_08_ST 0x00006aceu
#define CYREG_B1_UDB08_09_ST 0x00006ad0u
#define CYREG_B1_UDB09_10_ST 0x00006ad2u
#define CYREG_B1_UDB10_11_ST 0x00006ad4u
#define CYREG_B1_UDB11_12_ST 0x00006ad6u
#define CYREG_B1_UDB04_05_CTL 0x00006ae8u
#define CYREG_B1_UDB05_06_CTL 0x00006aeau
#define CYREG_B1_UDB06_07_CTL 0x00006aecu
#define CYREG_B1_UDB07_08_CTL 0x00006aeeu
#define CYREG_B1_UDB08_09_CTL 0x00006af0u
#define CYREG_B1_UDB09_10_CTL 0x00006af2u
#define CYREG_B1_UDB10_11_CTL 0x00006af4u
#define CYREG_B1_UDB11_12_CTL 0x00006af6u
#define CYREG_B1_UDB04_05_MSK 0x00006b08u
#define CYREG_B1_UDB05_06_MSK 0x00006b0au
#define CYREG_B1_UDB06_07_MSK 0x00006b0cu
#define CYREG_B1_UDB07_08_MSK 0x00006b0eu
#define CYREG_B1_UDB08_09_MSK 0x00006b10u
#define CYREG_B1_UDB09_10_MSK 0x00006b12u
#define CYREG_B1_UDB10_11_MSK 0x00006b14u
#define CYREG_B1_UDB11_12_MSK 0x00006b16u
#define CYREG_B1_UDB04_05_ACTL 0x00006b28u
#define CYREG_B1_UDB05_06_ACTL 0x00006b2au
#define CYREG_B1_UDB06_07_ACTL 0x00006b2cu
#define CYREG_B1_UDB07_08_ACTL 0x00006b2eu
#define CYREG_B1_UDB08_09_ACTL 0x00006b30u
#define CYREG_B1_UDB09_10_ACTL 0x00006b32u
#define CYREG_B1_UDB10_11_ACTL 0x00006b34u
#define CYREG_B1_UDB11_12_ACTL 0x00006b36u
#define CYREG_B1_UDB04_05_MC 0x00006b48u
#define CYREG_B1_UDB05_06_MC 0x00006b4au
#define CYREG_B1_UDB06_07_MC 0x00006b4cu
#define CYREG_B1_UDB07_08_MC 0x00006b4eu
#define CYREG_B1_UDB08_09_MC 0x00006b50u
#define CYREG_B1_UDB09_10_MC 0x00006b52u
#define CYREG_B1_UDB10_11_MC 0x00006b54u
#define CYREG_B1_UDB11_12_MC 0x00006b56u
#define CYDEV_PHUB_BASE 0x00007000u
#define CYDEV_PHUB_SIZE 0x00000c00u
#define CYREG_PHUB_CFG 0x00007000u
#define CYREG_PHUB_ERR 0x00007004u
#define CYREG_PHUB_ERR_ADR 0x00007008u
#define CYDEV_PHUB_CH0_BASE 0x00007010u
#define CYDEV_PHUB_CH0_SIZE 0x0000000cu
#define CYREG_PHUB_CH0_BASIC_CFG 0x00007010u
#define CYREG_PHUB_CH0_ACTION 0x00007014u
#define CYREG_PHUB_CH0_BASIC_STATUS 0x00007018u
#define CYDEV_PHUB_CH1_BASE 0x00007020u
#define CYDEV_PHUB_CH1_SIZE 0x0000000cu
#define CYREG_PHUB_CH1_BASIC_CFG 0x00007020u
#define CYREG_PHUB_CH1_ACTION 0x00007024u
#define CYREG_PHUB_CH1_BASIC_STATUS 0x00007028u
#define CYDEV_PHUB_CH2_BASE 0x00007030u
#define CYDEV_PHUB_CH2_SIZE 0x0000000cu
#define CYREG_PHUB_CH2_BASIC_CFG 0x00007030u
#define CYREG_PHUB_CH2_ACTION 0x00007034u
#define CYREG_PHUB_CH2_BASIC_STATUS 0x00007038u
#define CYDEV_PHUB_CH3_BASE 0x00007040u
#define CYDEV_PHUB_CH3_SIZE 0x0000000cu
#define CYREG_PHUB_CH3_BASIC_CFG 0x00007040u
#define CYREG_PHUB_CH3_ACTION 0x00007044u
#define CYREG_PHUB_CH3_BASIC_STATUS 0x00007048u
#define CYDEV_PHUB_CH4_BASE 0x00007050u
#define CYDEV_PHUB_CH4_SIZE 0x0000000cu
#define CYREG_PHUB_CH4_BASIC_CFG 0x00007050u
#define CYREG_PHUB_CH4_ACTION 0x00007054u
#define CYREG_PHUB_CH4_BASIC_STATUS 0x00007058u
#define CYDEV_PHUB_CH5_BASE 0x00007060u
#define CYDEV_PHUB_CH5_SIZE 0x0000000cu
#define CYREG_PHUB_CH5_BASIC_CFG 0x00007060u
#define CYREG_PHUB_CH5_ACTION 0x00007064u
#define CYREG_PHUB_CH5_BASIC_STATUS 0x00007068u
#define CYDEV_PHUB_CH6_BASE 0x00007070u
#define CYDEV_PHUB_CH6_SIZE 0x0000000cu
#define CYREG_PHUB_CH6_BASIC_CFG 0x00007070u
#define CYREG_PHUB_CH6_ACTION 0x00007074u
#define CYREG_PHUB_CH6_BASIC_STATUS 0x00007078u
#define CYDEV_PHUB_CH7_BASE 0x00007080u
#define CYDEV_PHUB_CH7_SIZE 0x0000000cu
#define CYREG_PHUB_CH7_BASIC_CFG 0x00007080u
#define CYREG_PHUB_CH7_ACTION 0x00007084u
#define CYREG_PHUB_CH7_BASIC_STATUS 0x00007088u
#define CYDEV_PHUB_CH8_BASE 0x00007090u
#define CYDEV_PHUB_CH8_SIZE 0x0000000cu
#define CYREG_PHUB_CH8_BASIC_CFG 0x00007090u
#define CYREG_PHUB_CH8_ACTION 0x00007094u
#define CYREG_PHUB_CH8_BASIC_STATUS 0x00007098u
#define CYDEV_PHUB_CH9_BASE 0x000070a0u
#define CYDEV_PHUB_CH9_SIZE 0x0000000cu
#define CYREG_PHUB_CH9_BASIC_CFG 0x000070a0u
#define CYREG_PHUB_CH9_ACTION 0x000070a4u
#define CYREG_PHUB_CH9_BASIC_STATUS 0x000070a8u
#define CYDEV_PHUB_CH10_BASE 0x000070b0u
#define CYDEV_PHUB_CH10_SIZE 0x0000000cu
#define CYREG_PHUB_CH10_BASIC_CFG 0x000070b0u
#define CYREG_PHUB_CH10_ACTION 0x000070b4u
#define CYREG_PHUB_CH10_BASIC_STATUS 0x000070b8u
#define CYDEV_PHUB_CH11_BASE 0x000070c0u
#define CYDEV_PHUB_CH11_SIZE 0x0000000cu
#define CYREG_PHUB_CH11_BASIC_CFG 0x000070c0u
#define CYREG_PHUB_CH11_ACTION 0x000070c4u
#define CYREG_PHUB_CH11_BASIC_STATUS 0x000070c8u
#define CYDEV_PHUB_CH12_BASE 0x000070d0u
#define CYDEV_PHUB_CH12_SIZE 0x0000000cu
#define CYREG_PHUB_CH12_BASIC_CFG 0x000070d0u
#define CYREG_PHUB_CH12_ACTION 0x000070d4u
#define CYREG_PHUB_CH12_BASIC_STATUS 0x000070d8u
#define CYDEV_PHUB_CH13_BASE 0x000070e0u
#define CYDEV_PHUB_CH13_SIZE 0x0000000cu
#define CYREG_PHUB_CH13_BASIC_CFG 0x000070e0u
#define CYREG_PHUB_CH13_ACTION 0x000070e4u
#define CYREG_PHUB_CH13_BASIC_STATUS 0x000070e8u
#define CYDEV_PHUB_CH14_BASE 0x000070f0u
#define CYDEV_PHUB_CH14_SIZE 0x0000000cu
#define CYREG_PHUB_CH14_BASIC_CFG 0x000070f0u
#define CYREG_PHUB_CH14_ACTION 0x000070f4u
#define CYREG_PHUB_CH14_BASIC_STATUS 0x000070f8u
#define CYDEV_PHUB_CH15_BASE 0x00007100u
#define CYDEV_PHUB_CH15_SIZE 0x0000000cu
#define CYREG_PHUB_CH15_BASIC_CFG 0x00007100u
#define CYREG_PHUB_CH15_ACTION 0x00007104u
#define CYREG_PHUB_CH15_BASIC_STATUS 0x00007108u
#define CYDEV_PHUB_CH16_BASE 0x00007110u
#define CYDEV_PHUB_CH16_SIZE 0x0000000cu
#define CYREG_PHUB_CH16_BASIC_CFG 0x00007110u
#define CYREG_PHUB_CH16_ACTION 0x00007114u
#define CYREG_PHUB_CH16_BASIC_STATUS 0x00007118u
#define CYDEV_PHUB_CH17_BASE 0x00007120u
#define CYDEV_PHUB_CH17_SIZE 0x0000000cu
#define CYREG_PHUB_CH17_BASIC_CFG 0x00007120u
#define CYREG_PHUB_CH17_ACTION 0x00007124u
#define CYREG_PHUB_CH17_BASIC_STATUS 0x00007128u
#define CYDEV_PHUB_CH18_BASE 0x00007130u
#define CYDEV_PHUB_CH18_SIZE 0x0000000cu
#define CYREG_PHUB_CH18_BASIC_CFG 0x00007130u
#define CYREG_PHUB_CH18_ACTION 0x00007134u
#define CYREG_PHUB_CH18_BASIC_STATUS 0x00007138u
#define CYDEV_PHUB_CH19_BASE 0x00007140u
#define CYDEV_PHUB_CH19_SIZE 0x0000000cu
#define CYREG_PHUB_CH19_BASIC_CFG 0x00007140u
#define CYREG_PHUB_CH19_ACTION 0x00007144u
#define CYREG_PHUB_CH19_BASIC_STATUS 0x00007148u
#define CYDEV_PHUB_CH20_BASE 0x00007150u
#define CYDEV_PHUB_CH20_SIZE 0x0000000cu
#define CYREG_PHUB_CH20_BASIC_CFG 0x00007150u
#define CYREG_PHUB_CH20_ACTION 0x00007154u
#define CYREG_PHUB_CH20_BASIC_STATUS 0x00007158u
#define CYDEV_PHUB_CH21_BASE 0x00007160u
#define CYDEV_PHUB_CH21_SIZE 0x0000000cu
#define CYREG_PHUB_CH21_BASIC_CFG 0x00007160u
#define CYREG_PHUB_CH21_ACTION 0x00007164u
#define CYREG_PHUB_CH21_BASIC_STATUS 0x00007168u
#define CYDEV_PHUB_CH22_BASE 0x00007170u
#define CYDEV_PHUB_CH22_SIZE 0x0000000cu
#define CYREG_PHUB_CH22_BASIC_CFG 0x00007170u
#define CYREG_PHUB_CH22_ACTION 0x00007174u
#define CYREG_PHUB_CH22_BASIC_STATUS 0x00007178u
#define CYDEV_PHUB_CH23_BASE 0x00007180u
#define CYDEV_PHUB_CH23_SIZE 0x0000000cu
#define CYREG_PHUB_CH23_BASIC_CFG 0x00007180u
#define CYREG_PHUB_CH23_ACTION 0x00007184u
#define CYREG_PHUB_CH23_BASIC_STATUS 0x00007188u
#define CYDEV_PHUB_CFGMEM0_BASE 0x00007600u
#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM0_CFG0 0x00007600u
#define CYREG_PHUB_CFGMEM0_CFG1 0x00007604u
#define CYDEV_PHUB_CFGMEM1_BASE 0x00007608u
#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM1_CFG0 0x00007608u
#define CYREG_PHUB_CFGMEM1_CFG1 0x0000760cu
#define CYDEV_PHUB_CFGMEM2_BASE 0x00007610u
#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM2_CFG0 0x00007610u
#define CYREG_PHUB_CFGMEM2_CFG1 0x00007614u
#define CYDEV_PHUB_CFGMEM3_BASE 0x00007618u
#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM3_CFG0 0x00007618u
#define CYREG_PHUB_CFGMEM3_CFG1 0x0000761cu
#define CYDEV_PHUB_CFGMEM4_BASE 0x00007620u
#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM4_CFG0 0x00007620u
#define CYREG_PHUB_CFGMEM4_CFG1 0x00007624u
#define CYDEV_PHUB_CFGMEM5_BASE 0x00007628u
#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM5_CFG0 0x00007628u
#define CYREG_PHUB_CFGMEM5_CFG1 0x0000762cu
#define CYDEV_PHUB_CFGMEM6_BASE 0x00007630u
#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM6_CFG0 0x00007630u
#define CYREG_PHUB_CFGMEM6_CFG1 0x00007634u
#define CYDEV_PHUB_CFGMEM7_BASE 0x00007638u
#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM7_CFG0 0x00007638u
#define CYREG_PHUB_CFGMEM7_CFG1 0x0000763cu
#define CYDEV_PHUB_CFGMEM8_BASE 0x00007640u
#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM8_CFG0 0x00007640u
#define CYREG_PHUB_CFGMEM8_CFG1 0x00007644u
#define CYDEV_PHUB_CFGMEM9_BASE 0x00007648u
#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM9_CFG0 0x00007648u
#define CYREG_PHUB_CFGMEM9_CFG1 0x0000764cu
#define CYDEV_PHUB_CFGMEM10_BASE 0x00007650u
#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM10_CFG0 0x00007650u
#define CYREG_PHUB_CFGMEM10_CFG1 0x00007654u
#define CYDEV_PHUB_CFGMEM11_BASE 0x00007658u
#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM11_CFG0 0x00007658u
#define CYREG_PHUB_CFGMEM11_CFG1 0x0000765cu
#define CYDEV_PHUB_CFGMEM12_BASE 0x00007660u
#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM12_CFG0 0x00007660u
#define CYREG_PHUB_CFGMEM12_CFG1 0x00007664u
#define CYDEV_PHUB_CFGMEM13_BASE 0x00007668u
#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM13_CFG0 0x00007668u
#define CYREG_PHUB_CFGMEM13_CFG1 0x0000766cu
#define CYDEV_PHUB_CFGMEM14_BASE 0x00007670u
#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM14_CFG0 0x00007670u
#define CYREG_PHUB_CFGMEM14_CFG1 0x00007674u
#define CYDEV_PHUB_CFGMEM15_BASE 0x00007678u
#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM15_CFG0 0x00007678u
#define CYREG_PHUB_CFGMEM15_CFG1 0x0000767cu
#define CYDEV_PHUB_CFGMEM16_BASE 0x00007680u
#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM16_CFG0 0x00007680u
#define CYREG_PHUB_CFGMEM16_CFG1 0x00007684u
#define CYDEV_PHUB_CFGMEM17_BASE 0x00007688u
#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM17_CFG0 0x00007688u
#define CYREG_PHUB_CFGMEM17_CFG1 0x0000768cu
#define CYDEV_PHUB_CFGMEM18_BASE 0x00007690u
#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM18_CFG0 0x00007690u
#define CYREG_PHUB_CFGMEM18_CFG1 0x00007694u
#define CYDEV_PHUB_CFGMEM19_BASE 0x00007698u
#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM19_CFG0 0x00007698u
#define CYREG_PHUB_CFGMEM19_CFG1 0x0000769cu
#define CYDEV_PHUB_CFGMEM20_BASE 0x000076a0u
#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM20_CFG0 0x000076a0u
#define CYREG_PHUB_CFGMEM20_CFG1 0x000076a4u
#define CYDEV_PHUB_CFGMEM21_BASE 0x000076a8u
#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM21_CFG0 0x000076a8u
#define CYREG_PHUB_CFGMEM21_CFG1 0x000076acu
#define CYDEV_PHUB_CFGMEM22_BASE 0x000076b0u
#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM22_CFG0 0x000076b0u
#define CYREG_PHUB_CFGMEM22_CFG1 0x000076b4u
#define CYDEV_PHUB_CFGMEM23_BASE 0x000076b8u
#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u
#define CYREG_PHUB_CFGMEM23_CFG0 0x000076b8u
#define CYREG_PHUB_CFGMEM23_CFG1 0x000076bcu
#define CYDEV_PHUB_TDMEM0_BASE 0x00007800u
#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x00007800u
#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x00007804u
#define CYDEV_PHUB_TDMEM1_BASE 0x00007808u
#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x00007808u
#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x0000780cu
#define CYDEV_PHUB_TDMEM2_BASE 0x00007810u
#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x00007810u
#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x00007814u
#define CYDEV_PHUB_TDMEM3_BASE 0x00007818u
#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x00007818u
#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x0000781cu
#define CYDEV_PHUB_TDMEM4_BASE 0x00007820u
#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x00007820u
#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x00007824u
#define CYDEV_PHUB_TDMEM5_BASE 0x00007828u
#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x00007828u
#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x0000782cu
#define CYDEV_PHUB_TDMEM6_BASE 0x00007830u
#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x00007830u
#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x00007834u
#define CYDEV_PHUB_TDMEM7_BASE 0x00007838u
#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x00007838u
#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x0000783cu
#define CYDEV_PHUB_TDMEM8_BASE 0x00007840u
#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x00007840u
#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x00007844u
#define CYDEV_PHUB_TDMEM9_BASE 0x00007848u
#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x00007848u
#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x0000784cu
#define CYDEV_PHUB_TDMEM10_BASE 0x00007850u
#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x00007850u
#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x00007854u
#define CYDEV_PHUB_TDMEM11_BASE 0x00007858u
#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x00007858u
#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x0000785cu
#define CYDEV_PHUB_TDMEM12_BASE 0x00007860u
#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x00007860u
#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x00007864u
#define CYDEV_PHUB_TDMEM13_BASE 0x00007868u
#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x00007868u
#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x0000786cu
#define CYDEV_PHUB_TDMEM14_BASE 0x00007870u
#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x00007870u
#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x00007874u
#define CYDEV_PHUB_TDMEM15_BASE 0x00007878u
#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x00007878u
#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x0000787cu
#define CYDEV_PHUB_TDMEM16_BASE 0x00007880u
#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x00007880u
#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x00007884u
#define CYDEV_PHUB_TDMEM17_BASE 0x00007888u
#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x00007888u
#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x0000788cu
#define CYDEV_PHUB_TDMEM18_BASE 0x00007890u
#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x00007890u
#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x00007894u
#define CYDEV_PHUB_TDMEM19_BASE 0x00007898u
#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x00007898u
#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x0000789cu
#define CYDEV_PHUB_TDMEM20_BASE 0x000078a0u
#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x000078a0u
#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x000078a4u
#define CYDEV_PHUB_TDMEM21_BASE 0x000078a8u
#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x000078a8u
#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x000078acu
#define CYDEV_PHUB_TDMEM22_BASE 0x000078b0u
#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x000078b0u
#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x000078b4u
#define CYDEV_PHUB_TDMEM23_BASE 0x000078b8u
#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x000078b8u
#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x000078bcu
#define CYDEV_PHUB_TDMEM24_BASE 0x000078c0u
#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x000078c0u
#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x000078c4u
#define CYDEV_PHUB_TDMEM25_BASE 0x000078c8u
#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x000078c8u
#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x000078ccu
#define CYDEV_PHUB_TDMEM26_BASE 0x000078d0u
#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x000078d0u
#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x000078d4u
#define CYDEV_PHUB_TDMEM27_BASE 0x000078d8u
#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x000078d8u
#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x000078dcu
#define CYDEV_PHUB_TDMEM28_BASE 0x000078e0u
#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x000078e0u
#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x000078e4u
#define CYDEV_PHUB_TDMEM29_BASE 0x000078e8u
#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x000078e8u
#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x000078ecu
#define CYDEV_PHUB_TDMEM30_BASE 0x000078f0u
#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x000078f0u
#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x000078f4u
#define CYDEV_PHUB_TDMEM31_BASE 0x000078f8u
#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x000078f8u
#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x000078fcu
#define CYDEV_PHUB_TDMEM32_BASE 0x00007900u
#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x00007900u
#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x00007904u
#define CYDEV_PHUB_TDMEM33_BASE 0x00007908u
#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x00007908u
#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x0000790cu
#define CYDEV_PHUB_TDMEM34_BASE 0x00007910u
#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x00007910u
#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x00007914u
#define CYDEV_PHUB_TDMEM35_BASE 0x00007918u
#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x00007918u
#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x0000791cu
#define CYDEV_PHUB_TDMEM36_BASE 0x00007920u
#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x00007920u
#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x00007924u
#define CYDEV_PHUB_TDMEM37_BASE 0x00007928u
#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x00007928u
#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x0000792cu
#define CYDEV_PHUB_TDMEM38_BASE 0x00007930u
#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x00007930u
#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x00007934u
#define CYDEV_PHUB_TDMEM39_BASE 0x00007938u
#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x00007938u
#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x0000793cu
#define CYDEV_PHUB_TDMEM40_BASE 0x00007940u
#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x00007940u
#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x00007944u
#define CYDEV_PHUB_TDMEM41_BASE 0x00007948u
#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x00007948u
#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x0000794cu
#define CYDEV_PHUB_TDMEM42_BASE 0x00007950u
#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x00007950u
#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x00007954u
#define CYDEV_PHUB_TDMEM43_BASE 0x00007958u
#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x00007958u
#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x0000795cu
#define CYDEV_PHUB_TDMEM44_BASE 0x00007960u
#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x00007960u
#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x00007964u
#define CYDEV_PHUB_TDMEM45_BASE 0x00007968u
#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x00007968u
#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x0000796cu
#define CYDEV_PHUB_TDMEM46_BASE 0x00007970u
#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x00007970u
#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x00007974u
#define CYDEV_PHUB_TDMEM47_BASE 0x00007978u
#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x00007978u
#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x0000797cu
#define CYDEV_PHUB_TDMEM48_BASE 0x00007980u
#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x00007980u
#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x00007984u
#define CYDEV_PHUB_TDMEM49_BASE 0x00007988u
#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x00007988u
#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x0000798cu
#define CYDEV_PHUB_TDMEM50_BASE 0x00007990u
#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x00007990u
#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x00007994u
#define CYDEV_PHUB_TDMEM51_BASE 0x00007998u
#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x00007998u
#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x0000799cu
#define CYDEV_PHUB_TDMEM52_BASE 0x000079a0u
#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x000079a0u
#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x000079a4u
#define CYDEV_PHUB_TDMEM53_BASE 0x000079a8u
#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x000079a8u
#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x000079acu
#define CYDEV_PHUB_TDMEM54_BASE 0x000079b0u
#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x000079b0u
#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x000079b4u
#define CYDEV_PHUB_TDMEM55_BASE 0x000079b8u
#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x000079b8u
#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x000079bcu
#define CYDEV_PHUB_TDMEM56_BASE 0x000079c0u
#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x000079c0u
#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x000079c4u
#define CYDEV_PHUB_TDMEM57_BASE 0x000079c8u
#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x000079c8u
#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x000079ccu
#define CYDEV_PHUB_TDMEM58_BASE 0x000079d0u
#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x000079d0u
#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x000079d4u
#define CYDEV_PHUB_TDMEM59_BASE 0x000079d8u
#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x000079d8u
#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x000079dcu
#define CYDEV_PHUB_TDMEM60_BASE 0x000079e0u
#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x000079e0u
#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x000079e4u
#define CYDEV_PHUB_TDMEM61_BASE 0x000079e8u
#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x000079e8u
#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x000079ecu
#define CYDEV_PHUB_TDMEM62_BASE 0x000079f0u
#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x000079f0u
#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x000079f4u
#define CYDEV_PHUB_TDMEM63_BASE 0x000079f8u
#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x000079f8u
#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x000079fcu
#define CYDEV_PHUB_TDMEM64_BASE 0x00007a00u
#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x00007a00u
#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x00007a04u
#define CYDEV_PHUB_TDMEM65_BASE 0x00007a08u
#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x00007a08u
#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x00007a0cu
#define CYDEV_PHUB_TDMEM66_BASE 0x00007a10u
#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x00007a10u
#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x00007a14u
#define CYDEV_PHUB_TDMEM67_BASE 0x00007a18u
#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x00007a18u
#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x00007a1cu
#define CYDEV_PHUB_TDMEM68_BASE 0x00007a20u
#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x00007a20u
#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x00007a24u
#define CYDEV_PHUB_TDMEM69_BASE 0x00007a28u
#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x00007a28u
#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x00007a2cu
#define CYDEV_PHUB_TDMEM70_BASE 0x00007a30u
#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x00007a30u
#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x00007a34u
#define CYDEV_PHUB_TDMEM71_BASE 0x00007a38u
#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x00007a38u
#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x00007a3cu
#define CYDEV_PHUB_TDMEM72_BASE 0x00007a40u
#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x00007a40u
#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x00007a44u
#define CYDEV_PHUB_TDMEM73_BASE 0x00007a48u
#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x00007a48u
#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x00007a4cu
#define CYDEV_PHUB_TDMEM74_BASE 0x00007a50u
#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x00007a50u
#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x00007a54u
#define CYDEV_PHUB_TDMEM75_BASE 0x00007a58u
#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x00007a58u
#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x00007a5cu
#define CYDEV_PHUB_TDMEM76_BASE 0x00007a60u
#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x00007a60u
#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x00007a64u
#define CYDEV_PHUB_TDMEM77_BASE 0x00007a68u
#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x00007a68u
#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x00007a6cu
#define CYDEV_PHUB_TDMEM78_BASE 0x00007a70u
#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x00007a70u
#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x00007a74u
#define CYDEV_PHUB_TDMEM79_BASE 0x00007a78u
#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x00007a78u
#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x00007a7cu
#define CYDEV_PHUB_TDMEM80_BASE 0x00007a80u
#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x00007a80u
#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x00007a84u
#define CYDEV_PHUB_TDMEM81_BASE 0x00007a88u
#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x00007a88u
#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x00007a8cu
#define CYDEV_PHUB_TDMEM82_BASE 0x00007a90u
#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x00007a90u
#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x00007a94u
#define CYDEV_PHUB_TDMEM83_BASE 0x00007a98u
#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x00007a98u
#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x00007a9cu
#define CYDEV_PHUB_TDMEM84_BASE 0x00007aa0u
#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x00007aa0u
#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x00007aa4u
#define CYDEV_PHUB_TDMEM85_BASE 0x00007aa8u
#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x00007aa8u
#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x00007aacu
#define CYDEV_PHUB_TDMEM86_BASE 0x00007ab0u
#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x00007ab0u
#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x00007ab4u
#define CYDEV_PHUB_TDMEM87_BASE 0x00007ab8u
#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x00007ab8u
#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x00007abcu
#define CYDEV_PHUB_TDMEM88_BASE 0x00007ac0u
#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x00007ac0u
#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x00007ac4u
#define CYDEV_PHUB_TDMEM89_BASE 0x00007ac8u
#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x00007ac8u
#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x00007accu
#define CYDEV_PHUB_TDMEM90_BASE 0x00007ad0u
#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x00007ad0u
#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x00007ad4u
#define CYDEV_PHUB_TDMEM91_BASE 0x00007ad8u
#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x00007ad8u
#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x00007adcu
#define CYDEV_PHUB_TDMEM92_BASE 0x00007ae0u
#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x00007ae0u
#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x00007ae4u
#define CYDEV_PHUB_TDMEM93_BASE 0x00007ae8u
#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x00007ae8u
#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x00007aecu
#define CYDEV_PHUB_TDMEM94_BASE 0x00007af0u
#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x00007af0u
#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x00007af4u
#define CYDEV_PHUB_TDMEM95_BASE 0x00007af8u
#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x00007af8u
#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x00007afcu
#define CYDEV_PHUB_TDMEM96_BASE 0x00007b00u
#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x00007b00u
#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x00007b04u
#define CYDEV_PHUB_TDMEM97_BASE 0x00007b08u
#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x00007b08u
#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x00007b0cu
#define CYDEV_PHUB_TDMEM98_BASE 0x00007b10u
#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x00007b10u
#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x00007b14u
#define CYDEV_PHUB_TDMEM99_BASE 0x00007b18u
#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x00007b18u
#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x00007b1cu
#define CYDEV_PHUB_TDMEM100_BASE 0x00007b20u
#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x00007b20u
#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x00007b24u
#define CYDEV_PHUB_TDMEM101_BASE 0x00007b28u
#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x00007b28u
#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x00007b2cu
#define CYDEV_PHUB_TDMEM102_BASE 0x00007b30u
#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x00007b30u
#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x00007b34u
#define CYDEV_PHUB_TDMEM103_BASE 0x00007b38u
#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x00007b38u
#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x00007b3cu
#define CYDEV_PHUB_TDMEM104_BASE 0x00007b40u
#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x00007b40u
#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x00007b44u
#define CYDEV_PHUB_TDMEM105_BASE 0x00007b48u
#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x00007b48u
#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x00007b4cu
#define CYDEV_PHUB_TDMEM106_BASE 0x00007b50u
#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x00007b50u
#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x00007b54u
#define CYDEV_PHUB_TDMEM107_BASE 0x00007b58u
#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x00007b58u
#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x00007b5cu
#define CYDEV_PHUB_TDMEM108_BASE 0x00007b60u
#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x00007b60u
#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x00007b64u
#define CYDEV_PHUB_TDMEM109_BASE 0x00007b68u
#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x00007b68u
#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x00007b6cu
#define CYDEV_PHUB_TDMEM110_BASE 0x00007b70u
#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x00007b70u
#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x00007b74u
#define CYDEV_PHUB_TDMEM111_BASE 0x00007b78u
#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x00007b78u
#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x00007b7cu
#define CYDEV_PHUB_TDMEM112_BASE 0x00007b80u
#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x00007b80u
#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x00007b84u
#define CYDEV_PHUB_TDMEM113_BASE 0x00007b88u
#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x00007b88u
#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x00007b8cu
#define CYDEV_PHUB_TDMEM114_BASE 0x00007b90u
#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x00007b90u
#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x00007b94u
#define CYDEV_PHUB_TDMEM115_BASE 0x00007b98u
#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x00007b98u
#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x00007b9cu
#define CYDEV_PHUB_TDMEM116_BASE 0x00007ba0u
#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x00007ba0u
#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x00007ba4u
#define CYDEV_PHUB_TDMEM117_BASE 0x00007ba8u
#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x00007ba8u
#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x00007bacu
#define CYDEV_PHUB_TDMEM118_BASE 0x00007bb0u
#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x00007bb0u
#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x00007bb4u
#define CYDEV_PHUB_TDMEM119_BASE 0x00007bb8u
#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x00007bb8u
#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x00007bbcu
#define CYDEV_PHUB_TDMEM120_BASE 0x00007bc0u
#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x00007bc0u
#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x00007bc4u
#define CYDEV_PHUB_TDMEM121_BASE 0x00007bc8u
#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x00007bc8u
#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x00007bccu
#define CYDEV_PHUB_TDMEM122_BASE 0x00007bd0u
#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x00007bd0u
#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x00007bd4u
#define CYDEV_PHUB_TDMEM123_BASE 0x00007bd8u
#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x00007bd8u
#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x00007bdcu
#define CYDEV_PHUB_TDMEM124_BASE 0x00007be0u
#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x00007be0u
#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x00007be4u
#define CYDEV_PHUB_TDMEM125_BASE 0x00007be8u
#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x00007be8u
#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x00007becu
#define CYDEV_PHUB_TDMEM126_BASE 0x00007bf0u
#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x00007bf0u
#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x00007bf4u
#define CYDEV_PHUB_TDMEM127_BASE 0x00007bf8u
#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u
#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x00007bf8u
#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x00007bfcu
#define CYDEV_EE_BASE 0x00008000u
#define CYDEV_EE_SIZE 0x00000800u
#define CYREG_EE_DATA_MBASE 0x00008000u
#define CYREG_EE_DATA_MSIZE 0x00000800u
#define CYDEV_CAN0_BASE 0x0000a000u
#define CYDEV_CAN0_SIZE 0x000002a0u
#define CYDEV_CAN0_CSR_BASE 0x0000a000u
#define CYDEV_CAN0_CSR_SIZE 0x00000018u
#define CYREG_CAN0_CSR_INT_SR 0x0000a000u
#define CYREG_CAN0_CSR_INT_EN 0x0000a004u
#define CYREG_CAN0_CSR_BUF_SR 0x0000a008u
#define CYREG_CAN0_CSR_ERR_SR 0x0000a00cu
#define CYREG_CAN0_CSR_CMD 0x0000a010u
#define CYREG_CAN0_CSR_CFG 0x0000a014u
#define CYDEV_CAN0_TX0_BASE 0x0000a020u
#define CYDEV_CAN0_TX0_SIZE 0x00000010u
#define CYREG_CAN0_TX0_CMD 0x0000a020u
#define CYREG_CAN0_TX0_ID 0x0000a024u
#define CYREG_CAN0_TX0_DH 0x0000a028u
#define CYREG_CAN0_TX0_DL 0x0000a02cu
#define CYDEV_CAN0_TX1_BASE 0x0000a030u
#define CYDEV_CAN0_TX1_SIZE 0x00000010u
#define CYREG_CAN0_TX1_CMD 0x0000a030u
#define CYREG_CAN0_TX1_ID 0x0000a034u
#define CYREG_CAN0_TX1_DH 0x0000a038u
#define CYREG_CAN0_TX1_DL 0x0000a03cu
#define CYDEV_CAN0_TX2_BASE 0x0000a040u
#define CYDEV_CAN0_TX2_SIZE 0x00000010u
#define CYREG_CAN0_TX2_CMD 0x0000a040u
#define CYREG_CAN0_TX2_ID 0x0000a044u
#define CYREG_CAN0_TX2_DH 0x0000a048u
#define CYREG_CAN0_TX2_DL 0x0000a04cu
#define CYDEV_CAN0_TX3_BASE 0x0000a050u
#define CYDEV_CAN0_TX3_SIZE 0x00000010u
#define CYREG_CAN0_TX3_CMD 0x0000a050u
#define CYREG_CAN0_TX3_ID 0x0000a054u
#define CYREG_CAN0_TX3_DH 0x0000a058u
#define CYREG_CAN0_TX3_DL 0x0000a05cu
#define CYDEV_CAN0_TX4_BASE 0x0000a060u
#define CYDEV_CAN0_TX4_SIZE 0x00000010u
#define CYREG_CAN0_TX4_CMD 0x0000a060u
#define CYREG_CAN0_TX4_ID 0x0000a064u
#define CYREG_CAN0_TX4_DH 0x0000a068u
#define CYREG_CAN0_TX4_DL 0x0000a06cu
#define CYDEV_CAN0_TX5_BASE 0x0000a070u
#define CYDEV_CAN0_TX5_SIZE 0x00000010u
#define CYREG_CAN0_TX5_CMD 0x0000a070u
#define CYREG_CAN0_TX5_ID 0x0000a074u
#define CYREG_CAN0_TX5_DH 0x0000a078u
#define CYREG_CAN0_TX5_DL 0x0000a07cu
#define CYDEV_CAN0_TX6_BASE 0x0000a080u
#define CYDEV_CAN0_TX6_SIZE 0x00000010u
#define CYREG_CAN0_TX6_CMD 0x0000a080u
#define CYREG_CAN0_TX6_ID 0x0000a084u
#define CYREG_CAN0_TX6_DH 0x0000a088u
#define CYREG_CAN0_TX6_DL 0x0000a08cu
#define CYDEV_CAN0_TX7_BASE 0x0000a090u
#define CYDEV_CAN0_TX7_SIZE 0x00000010u
#define CYREG_CAN0_TX7_CMD 0x0000a090u
#define CYREG_CAN0_TX7_ID 0x0000a094u
#define CYREG_CAN0_TX7_DH 0x0000a098u
#define CYREG_CAN0_TX7_DL 0x0000a09cu
#define CYDEV_CAN0_RX0_BASE 0x0000a0a0u
#define CYDEV_CAN0_RX0_SIZE 0x00000020u
#define CYREG_CAN0_RX0_CMD 0x0000a0a0u
#define CYREG_CAN0_RX0_ID 0x0000a0a4u
#define CYREG_CAN0_RX0_DH 0x0000a0a8u
#define CYREG_CAN0_RX0_DL 0x0000a0acu
#define CYREG_CAN0_RX0_AMR 0x0000a0b0u
#define CYREG_CAN0_RX0_ACR 0x0000a0b4u
#define CYREG_CAN0_RX0_AMRD 0x0000a0b8u
#define CYREG_CAN0_RX0_ACRD 0x0000a0bcu
#define CYDEV_CAN0_RX1_BASE 0x0000a0c0u
#define CYDEV_CAN0_RX1_SIZE 0x00000020u
#define CYREG_CAN0_RX1_CMD 0x0000a0c0u
#define CYREG_CAN0_RX1_ID 0x0000a0c4u
#define CYREG_CAN0_RX1_DH 0x0000a0c8u
#define CYREG_CAN0_RX1_DL 0x0000a0ccu
#define CYREG_CAN0_RX1_AMR 0x0000a0d0u
#define CYREG_CAN0_RX1_ACR 0x0000a0d4u
#define CYREG_CAN0_RX1_AMRD 0x0000a0d8u
#define CYREG_CAN0_RX1_ACRD 0x0000a0dcu
#define CYDEV_CAN0_RX2_BASE 0x0000a0e0u
#define CYDEV_CAN0_RX2_SIZE 0x00000020u
#define CYREG_CAN0_RX2_CMD 0x0000a0e0u
#define CYREG_CAN0_RX2_ID 0x0000a0e4u
#define CYREG_CAN0_RX2_DH 0x0000a0e8u
#define CYREG_CAN0_RX2_DL 0x0000a0ecu
#define CYREG_CAN0_RX2_AMR 0x0000a0f0u
#define CYREG_CAN0_RX2_ACR 0x0000a0f4u
#define CYREG_CAN0_RX2_AMRD 0x0000a0f8u
#define CYREG_CAN0_RX2_ACRD 0x0000a0fcu
#define CYDEV_CAN0_RX3_BASE 0x0000a100u
#define CYDEV_CAN0_RX3_SIZE 0x00000020u
#define CYREG_CAN0_RX3_CMD 0x0000a100u
#define CYREG_CAN0_RX3_ID 0x0000a104u
#define CYREG_CAN0_RX3_DH 0x0000a108u
#define CYREG_CAN0_RX3_DL 0x0000a10cu
#define CYREG_CAN0_RX3_AMR 0x0000a110u
#define CYREG_CAN0_RX3_ACR 0x0000a114u
#define CYREG_CAN0_RX3_AMRD 0x0000a118u
#define CYREG_CAN0_RX3_ACRD 0x0000a11cu
#define CYDEV_CAN0_RX4_BASE 0x0000a120u
#define CYDEV_CAN0_RX4_SIZE 0x00000020u
#define CYREG_CAN0_RX4_CMD 0x0000a120u
#define CYREG_CAN0_RX4_ID 0x0000a124u
#define CYREG_CAN0_RX4_DH 0x0000a128u
#define CYREG_CAN0_RX4_DL 0x0000a12cu
#define CYREG_CAN0_RX4_AMR 0x0000a130u
#define CYREG_CAN0_RX4_ACR 0x0000a134u
#define CYREG_CAN0_RX4_AMRD 0x0000a138u
#define CYREG_CAN0_RX4_ACRD 0x0000a13cu
#define CYDEV_CAN0_RX5_BASE 0x0000a140u
#define CYDEV_CAN0_RX5_SIZE 0x00000020u
#define CYREG_CAN0_RX5_CMD 0x0000a140u
#define CYREG_CAN0_RX5_ID 0x0000a144u
#define CYREG_CAN0_RX5_DH 0x0000a148u
#define CYREG_CAN0_RX5_DL 0x0000a14cu
#define CYREG_CAN0_RX5_AMR 0x0000a150u
#define CYREG_CAN0_RX5_ACR 0x0000a154u
#define CYREG_CAN0_RX5_AMRD 0x0000a158u
#define CYREG_CAN0_RX5_ACRD 0x0000a15cu
#define CYDEV_CAN0_RX6_BASE 0x0000a160u
#define CYDEV_CAN0_RX6_SIZE 0x00000020u
#define CYREG_CAN0_RX6_CMD 0x0000a160u
#define CYREG_CAN0_RX6_ID 0x0000a164u
#define CYREG_CAN0_RX6_DH 0x0000a168u
#define CYREG_CAN0_RX6_DL 0x0000a16cu
#define CYREG_CAN0_RX6_AMR 0x0000a170u
#define CYREG_CAN0_RX6_ACR 0x0000a174u
#define CYREG_CAN0_RX6_AMRD 0x0000a178u
#define CYREG_CAN0_RX6_ACRD 0x0000a17cu
#define CYDEV_CAN0_RX7_BASE 0x0000a180u
#define CYDEV_CAN0_RX7_SIZE 0x00000020u
#define CYREG_CAN0_RX7_CMD 0x0000a180u
#define CYREG_CAN0_RX7_ID 0x0000a184u
#define CYREG_CAN0_RX7_DH 0x0000a188u
#define CYREG_CAN0_RX7_DL 0x0000a18cu
#define CYREG_CAN0_RX7_AMR 0x0000a190u
#define CYREG_CAN0_RX7_ACR 0x0000a194u
#define CYREG_CAN0_RX7_AMRD 0x0000a198u
#define CYREG_CAN0_RX7_ACRD 0x0000a19cu
#define CYDEV_CAN0_RX8_BASE 0x0000a1a0u
#define CYDEV_CAN0_RX8_SIZE 0x00000020u
#define CYREG_CAN0_RX8_CMD 0x0000a1a0u
#define CYREG_CAN0_RX8_ID 0x0000a1a4u
#define CYREG_CAN0_RX8_DH 0x0000a1a8u
#define CYREG_CAN0_RX8_DL 0x0000a1acu
#define CYREG_CAN0_RX8_AMR 0x0000a1b0u
#define CYREG_CAN0_RX8_ACR 0x0000a1b4u
#define CYREG_CAN0_RX8_AMRD 0x0000a1b8u
#define CYREG_CAN0_RX8_ACRD 0x0000a1bcu
#define CYDEV_CAN0_RX9_BASE 0x0000a1c0u
#define CYDEV_CAN0_RX9_SIZE 0x00000020u
#define CYREG_CAN0_RX9_CMD 0x0000a1c0u
#define CYREG_CAN0_RX9_ID 0x0000a1c4u
#define CYREG_CAN0_RX9_DH 0x0000a1c8u
#define CYREG_CAN0_RX9_DL 0x0000a1ccu
#define CYREG_CAN0_RX9_AMR 0x0000a1d0u
#define CYREG_CAN0_RX9_ACR 0x0000a1d4u
#define CYREG_CAN0_RX9_AMRD 0x0000a1d8u
#define CYREG_CAN0_RX9_ACRD 0x0000a1dcu
#define CYDEV_CAN0_RX10_BASE 0x0000a1e0u
#define CYDEV_CAN0_RX10_SIZE 0x00000020u
#define CYREG_CAN0_RX10_CMD 0x0000a1e0u
#define CYREG_CAN0_RX10_ID 0x0000a1e4u
#define CYREG_CAN0_RX10_DH 0x0000a1e8u
#define CYREG_CAN0_RX10_DL 0x0000a1ecu
#define CYREG_CAN0_RX10_AMR 0x0000a1f0u
#define CYREG_CAN0_RX10_ACR 0x0000a1f4u
#define CYREG_CAN0_RX10_AMRD 0x0000a1f8u
#define CYREG_CAN0_RX10_ACRD 0x0000a1fcu
#define CYDEV_CAN0_RX11_BASE 0x0000a200u
#define CYDEV_CAN0_RX11_SIZE 0x00000020u
#define CYREG_CAN0_RX11_CMD 0x0000a200u
#define CYREG_CAN0_RX11_ID 0x0000a204u
#define CYREG_CAN0_RX11_DH 0x0000a208u
#define CYREG_CAN0_RX11_DL 0x0000a20cu
#define CYREG_CAN0_RX11_AMR 0x0000a210u
#define CYREG_CAN0_RX11_ACR 0x0000a214u
#define CYREG_CAN0_RX11_AMRD 0x0000a218u
#define CYREG_CAN0_RX11_ACRD 0x0000a21cu
#define CYDEV_CAN0_RX12_BASE 0x0000a220u
#define CYDEV_CAN0_RX12_SIZE 0x00000020u
#define CYREG_CAN0_RX12_CMD 0x0000a220u
#define CYREG_CAN0_RX12_ID 0x0000a224u
#define CYREG_CAN0_RX12_DH 0x0000a228u
#define CYREG_CAN0_RX12_DL 0x0000a22cu
#define CYREG_CAN0_RX12_AMR 0x0000a230u
#define CYREG_CAN0_RX12_ACR 0x0000a234u
#define CYREG_CAN0_RX12_AMRD 0x0000a238u
#define CYREG_CAN0_RX12_ACRD 0x0000a23cu
#define CYDEV_CAN0_RX13_BASE 0x0000a240u
#define CYDEV_CAN0_RX13_SIZE 0x00000020u
#define CYREG_CAN0_RX13_CMD 0x0000a240u
#define CYREG_CAN0_RX13_ID 0x0000a244u
#define CYREG_CAN0_RX13_DH 0x0000a248u
#define CYREG_CAN0_RX13_DL 0x0000a24cu
#define CYREG_CAN0_RX13_AMR 0x0000a250u
#define CYREG_CAN0_RX13_ACR 0x0000a254u
#define CYREG_CAN0_RX13_AMRD 0x0000a258u
#define CYREG_CAN0_RX13_ACRD 0x0000a25cu
#define CYDEV_CAN0_RX14_BASE 0x0000a260u
#define CYDEV_CAN0_RX14_SIZE 0x00000020u
#define CYREG_CAN0_RX14_CMD 0x0000a260u
#define CYREG_CAN0_RX14_ID 0x0000a264u
#define CYREG_CAN0_RX14_DH 0x0000a268u
#define CYREG_CAN0_RX14_DL 0x0000a26cu
#define CYREG_CAN0_RX14_AMR 0x0000a270u
#define CYREG_CAN0_RX14_ACR 0x0000a274u
#define CYREG_CAN0_RX14_AMRD 0x0000a278u
#define CYREG_CAN0_RX14_ACRD 0x0000a27cu
#define CYDEV_CAN0_RX15_BASE 0x0000a280u
#define CYDEV_CAN0_RX15_SIZE 0x00000020u
#define CYREG_CAN0_RX15_CMD 0x0000a280u
#define CYREG_CAN0_RX15_ID 0x0000a284u
#define CYREG_CAN0_RX15_DH 0x0000a288u
#define CYREG_CAN0_RX15_DL 0x0000a28cu
#define CYREG_CAN0_RX15_AMR 0x0000a290u
#define CYREG_CAN0_RX15_ACR 0x0000a294u
#define CYREG_CAN0_RX15_AMRD 0x0000a298u
#define CYREG_CAN0_RX15_ACRD 0x0000a29cu
#define CYDEV_DFB0_BASE 0x0000c000u
#define CYDEV_DFB0_SIZE 0x000007b5u
#define CYDEV_DFB0_DPA_SRAM_BASE 0x0000c000u
#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u
#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x0000c000u
#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u
#define CYDEV_DFB0_DPB_SRAM_BASE 0x0000c200u
#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u
#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x0000c200u
#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u
#define CYDEV_DFB0_CSA_SRAM_BASE 0x0000c400u
#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u
#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x0000c400u
#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u
#define CYDEV_DFB0_CSB_SRAM_BASE 0x0000c500u
#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u
#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x0000c500u
#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u
#define CYDEV_DFB0_FSM_SRAM_BASE 0x0000c600u
#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u
#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x0000c600u
#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u
#define CYDEV_DFB0_ACU_SRAM_BASE 0x0000c700u
#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u
#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x0000c700u
#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u
#define CYREG_DFB0_CR 0x0000c780u
#define CYREG_DFB0_SR 0x0000c784u
#define CYREG_DFB0_RAM_EN 0x0000c788u
#define CYREG_DFB0_RAM_DIR 0x0000c78cu
#define CYREG_DFB0_SEMA 0x0000c790u
#define CYREG_DFB0_DSI_CTRL 0x0000c794u
#define CYREG_DFB0_INT_CTRL 0x0000c798u
#define CYREG_DFB0_DMA_CTRL 0x0000c79cu
#define CYREG_DFB0_STAGEA 0x0000c7a0u
#define CYREG_DFB0_STAGEAM 0x0000c7a1u
#define CYREG_DFB0_STAGEAH 0x0000c7a2u
#define CYREG_DFB0_STAGEB 0x0000c7a4u
#define CYREG_DFB0_STAGEBM 0x0000c7a5u
#define CYREG_DFB0_STAGEBH 0x0000c7a6u
#define CYREG_DFB0_HOLDA 0x0000c7a8u
#define CYREG_DFB0_HOLDAM 0x0000c7a9u
#define CYREG_DFB0_HOLDAH 0x0000c7aau
#define CYREG_DFB0_HOLDAS 0x0000c7abu
#define CYREG_DFB0_HOLDB 0x0000c7acu
#define CYREG_DFB0_HOLDBM 0x0000c7adu
#define CYREG_DFB0_HOLDBH 0x0000c7aeu
#define CYREG_DFB0_HOLDBS 0x0000c7afu
#define CYREG_DFB0_COHER 0x0000c7b0u
#define CYREG_DFB0_DALIGN 0x0000c7b4u
#define CYDEV_SWV_BASE 0x0000e000u
#define CYDEV_SWV_SIZE 0x00001fd0u
#define CYDEV_SWV_ITM_BASE 0x0000e000u
#define CYDEV_SWV_ITM_SIZE 0x00000efcu
#define CYREG_SWV_ITM_SPR_DATA0 0x0000e000u
#define CYREG_SWV_ITM_SPR_DATA1 0x0000e004u
#define CYREG_SWV_ITM_SPR_DATA2 0x0000e008u
#define CYREG_SWV_ITM_SPR_DATA3 0x0000e00cu
#define CYREG_SWV_ITM_SPR_DATA4 0x0000e010u
#define CYREG_SWV_ITM_SPR_DATA5 0x0000e014u
#define CYREG_SWV_ITM_SPR_DATA6 0x0000e018u
#define CYREG_SWV_ITM_SPR_DATA7 0x0000e01cu
#define CYREG_SWV_ITM_SPR_DATA8 0x0000e020u
#define CYREG_SWV_ITM_SPR_DATA9 0x0000e024u
#define CYREG_SWV_ITM_SPR_DATA10 0x0000e028u
#define CYREG_SWV_ITM_SPR_DATA11 0x0000e02cu
#define CYREG_SWV_ITM_SPR_DATA12 0x0000e030u
#define CYREG_SWV_ITM_SPR_DATA13 0x0000e034u
#define CYREG_SWV_ITM_SPR_DATA14 0x0000e038u
#define CYREG_SWV_ITM_SPR_DATA15 0x0000e03cu
#define CYREG_SWV_ITM_SPR_DATA16 0x0000e040u
#define CYREG_SWV_ITM_SPR_DATA17 0x0000e044u
#define CYREG_SWV_ITM_SPR_DATA18 0x0000e048u
#define CYREG_SWV_ITM_SPR_DATA19 0x0000e04cu
#define CYREG_SWV_ITM_SPR_DATA20 0x0000e050u
#define CYREG_SWV_ITM_SPR_DATA21 0x0000e054u
#define CYREG_SWV_ITM_SPR_DATA22 0x0000e058u
#define CYREG_SWV_ITM_SPR_DATA23 0x0000e05cu
#define CYREG_SWV_ITM_SPR_DATA24 0x0000e060u
#define CYREG_SWV_ITM_SPR_DATA25 0x0000e064u
#define CYREG_SWV_ITM_SPR_DATA26 0x0000e068u
#define CYREG_SWV_ITM_SPR_DATA27 0x0000e06cu
#define CYREG_SWV_ITM_SPR_DATA28 0x0000e070u
#define CYREG_SWV_ITM_SPR_DATA29 0x0000e074u
#define CYREG_SWV_ITM_SPR_DATA30 0x0000e078u
#define CYREG_SWV_ITM_SPR_DATA31 0x0000e07cu
#define CYREG_SWV_ITM_TER 0x0000ee00u
#define CYREG_SWV_ITM_TTR 0x0000ee20u
#define CYREG_SWV_ITM_CR 0x0000ee80u
#define CYREG_SWV_ITM_SCR 0x0000ee90u
#define CYREG_SWV_ITM_ITTOAR 0x0000eee4u
#define CYREG_SWV_ITM_ITTOR 0x0000eee8u
#define CYREG_SWV_ITM_ITDR0 0x0000eeecu
#define CYREG_SWV_ITM_ITCR2 0x0000eef0u
#define CYREG_SWV_ITM_ITCR1 0x0000eef4u
#define CYREG_SWV_ITM_ITCR0 0x0000eef8u
#define CYDEV_SWV_SWO_BASE 0x0000f000u
#define CYDEV_SWV_SWO_SIZE 0x00000fd0u
#define CYREG_SWV_SWO_SSPS 0x0000f000u
#define CYREG_SWV_SWO_CSPS 0x0000f004u
#define CYREG_SWV_SWO_CAOSD 0x0000f010u
#define CYREG_SWV_SWO_SPP 0x0000f0f0u
#define CYREG_SWV_SWO_STM 0x0000f100u
#define CYREG_SWV_SWO_STPM 0x0000f200u
#define CYREG_SWV_SWO_FFS 0x0000f300u
#define CYREG_SWV_SWO_FFC 0x0000f304u
#define CYREG_SWV_SWO_ITDR0 0x0000feecu
#define CYREG_SWV_SWO_ITCR2 0x0000fef0u
#define CYREG_SWV_SWO_ITCR0 0x0000fef8u
#define CYREG_SWV_SWO_ITMCR 0x0000ff00u
#define CYREG_SWV_SWO_CTS 0x0000ffa0u
#define CYREG_SWV_SWO_CTC 0x0000ffa4u
#define CYREG_SWV_SWO_LA 0x0000ffb0u
#define CYREG_SWV_SWO_LS 0x0000ffb4u
#define CYREG_SWV_SWO_AS 0x0000ffb8u
#define CYREG_SWV_SWO_DID 0x0000ffc8u
#define CYREG_SWV_SWO_DTI 0x0000ffccu
#define CYDEV_UCFG_BASE 0x00010000u
#define CYDEV_UCFG_SIZE 0x00005040u
#define CYDEV_UCFG_B0_BASE 0x00010000u
#define CYDEV_UCFG_B0_SIZE 0x00000fefu
#define CYDEV_UCFG_B0_P0_BASE 0x00010000u
#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu
#define CYDEV_UCFG_B0_P0_U0_BASE 0x00010000u
#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u
#define CYREG_B0_P0_U0_PLD_IT0 0x00010000u
#define CYREG_B0_P0_U0_PLD_IT1 0x00010004u
#define CYREG_B0_P0_U0_PLD_IT2 0x00010008u
#define CYREG_B0_P0_U0_PLD_IT3 0x0001000cu
#define CYREG_B0_P0_U0_PLD_IT4 0x00010010u
#define CYREG_B0_P0_U0_PLD_IT5 0x00010014u
#define CYREG_B0_P0_U0_PLD_IT6 0x00010018u
#define CYREG_B0_P0_U0_PLD_IT7 0x0001001cu
#define CYREG_B0_P0_U0_PLD_IT8 0x00010020u
#define CYREG_B0_P0_U0_PLD_IT9 0x00010024u
#define CYREG_B0_P0_U0_PLD_IT10 0x00010028u
#define CYREG_B0_P0_U0_PLD_IT11 0x0001002cu
#define CYREG_B0_P0_U0_PLD_ORT0 0x00010030u
#define CYREG_B0_P0_U0_PLD_ORT1 0x00010032u
#define CYREG_B0_P0_U0_PLD_ORT2 0x00010034u
#define CYREG_B0_P0_U0_PLD_ORT3 0x00010036u
#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x00010038u
#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x0001003au
#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x0001003cu
#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x0001003eu
#define CYREG_B0_P0_U0_CFG0 0x00010040u
#define CYREG_B0_P0_U0_CFG1 0x00010041u
#define CYREG_B0_P0_U0_CFG2 0x00010042u
#define CYREG_B0_P0_U0_CFG3 0x00010043u
#define CYREG_B0_P0_U0_CFG4 0x00010044u
#define CYREG_B0_P0_U0_CFG5 0x00010045u
#define CYREG_B0_P0_U0_CFG6 0x00010046u
#define CYREG_B0_P0_U0_CFG7 0x00010047u
#define CYREG_B0_P0_U0_CFG8 0x00010048u
#define CYREG_B0_P0_U0_CFG9 0x00010049u
#define CYREG_B0_P0_U0_CFG10 0x0001004au
#define CYREG_B0_P0_U0_CFG11 0x0001004bu
#define CYREG_B0_P0_U0_CFG12 0x0001004cu
#define CYREG_B0_P0_U0_CFG13 0x0001004du
#define CYREG_B0_P0_U0_CFG14 0x0001004eu
#define CYREG_B0_P0_U0_CFG15 0x0001004fu
#define CYREG_B0_P0_U0_CFG16 0x00010050u
#define CYREG_B0_P0_U0_CFG17 0x00010051u
#define CYREG_B0_P0_U0_CFG18 0x00010052u
#define CYREG_B0_P0_U0_CFG19 0x00010053u
#define CYREG_B0_P0_U0_CFG20 0x00010054u
#define CYREG_B0_P0_U0_CFG21 0x00010055u
#define CYREG_B0_P0_U0_CFG22 0x00010056u
#define CYREG_B0_P0_U0_CFG23 0x00010057u
#define CYREG_B0_P0_U0_CFG24 0x00010058u
#define CYREG_B0_P0_U0_CFG25 0x00010059u
#define CYREG_B0_P0_U0_CFG26 0x0001005au
#define CYREG_B0_P0_U0_CFG27 0x0001005bu
#define CYREG_B0_P0_U0_CFG28 0x0001005cu
#define CYREG_B0_P0_U0_CFG29 0x0001005du
#define CYREG_B0_P0_U0_CFG30 0x0001005eu
#define CYREG_B0_P0_U0_CFG31 0x0001005fu
#define CYREG_B0_P0_U0_DCFG0 0x00010060u
#define CYREG_B0_P0_U0_DCFG1 0x00010062u
#define CYREG_B0_P0_U0_DCFG2 0x00010064u
#define CYREG_B0_P0_U0_DCFG3 0x00010066u
#define CYREG_B0_P0_U0_DCFG4 0x00010068u
#define CYREG_B0_P0_U0_DCFG5 0x0001006au
#define CYREG_B0_P0_U0_DCFG6 0x0001006cu
#define CYREG_B0_P0_U0_DCFG7 0x0001006eu
#define CYDEV_UCFG_B0_P0_U1_BASE 0x00010080u
#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u
#define CYREG_B0_P0_U1_PLD_IT0 0x00010080u
#define CYREG_B0_P0_U1_PLD_IT1 0x00010084u
#define CYREG_B0_P0_U1_PLD_IT2 0x00010088u
#define CYREG_B0_P0_U1_PLD_IT3 0x0001008cu
#define CYREG_B0_P0_U1_PLD_IT4 0x00010090u
#define CYREG_B0_P0_U1_PLD_IT5 0x00010094u
#define CYREG_B0_P0_U1_PLD_IT6 0x00010098u
#define CYREG_B0_P0_U1_PLD_IT7 0x0001009cu
#define CYREG_B0_P0_U1_PLD_IT8 0x000100a0u
#define CYREG_B0_P0_U1_PLD_IT9 0x000100a4u
#define CYREG_B0_P0_U1_PLD_IT10 0x000100a8u
#define CYREG_B0_P0_U1_PLD_IT11 0x000100acu
#define CYREG_B0_P0_U1_PLD_ORT0 0x000100b0u
#define CYREG_B0_P0_U1_PLD_ORT1 0x000100b2u
#define CYREG_B0_P0_U1_PLD_ORT2 0x000100b4u
#define CYREG_B0_P0_U1_PLD_ORT3 0x000100b6u
#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x000100b8u
#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x000100bau
#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x000100bcu
#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x000100beu
#define CYREG_B0_P0_U1_CFG0 0x000100c0u
#define CYREG_B0_P0_U1_CFG1 0x000100c1u
#define CYREG_B0_P0_U1_CFG2 0x000100c2u
#define CYREG_B0_P0_U1_CFG3 0x000100c3u
#define CYREG_B0_P0_U1_CFG4 0x000100c4u
#define CYREG_B0_P0_U1_CFG5 0x000100c5u
#define CYREG_B0_P0_U1_CFG6 0x000100c6u
#define CYREG_B0_P0_U1_CFG7 0x000100c7u
#define CYREG_B0_P0_U1_CFG8 0x000100c8u
#define CYREG_B0_P0_U1_CFG9 0x000100c9u
#define CYREG_B0_P0_U1_CFG10 0x000100cau
#define CYREG_B0_P0_U1_CFG11 0x000100cbu
#define CYREG_B0_P0_U1_CFG12 0x000100ccu
#define CYREG_B0_P0_U1_CFG13 0x000100cdu
#define CYREG_B0_P0_U1_CFG14 0x000100ceu
#define CYREG_B0_P0_U1_CFG15 0x000100cfu
#define CYREG_B0_P0_U1_CFG16 0x000100d0u
#define CYREG_B0_P0_U1_CFG17 0x000100d1u
#define CYREG_B0_P0_U1_CFG18 0x000100d2u
#define CYREG_B0_P0_U1_CFG19 0x000100d3u
#define CYREG_B0_P0_U1_CFG20 0x000100d4u
#define CYREG_B0_P0_U1_CFG21 0x000100d5u
#define CYREG_B0_P0_U1_CFG22 0x000100d6u
#define CYREG_B0_P0_U1_CFG23 0x000100d7u
#define CYREG_B0_P0_U1_CFG24 0x000100d8u
#define CYREG_B0_P0_U1_CFG25 0x000100d9u
#define CYREG_B0_P0_U1_CFG26 0x000100dau
#define CYREG_B0_P0_U1_CFG27 0x000100dbu
#define CYREG_B0_P0_U1_CFG28 0x000100dcu
#define CYREG_B0_P0_U1_CFG29 0x000100ddu
#define CYREG_B0_P0_U1_CFG30 0x000100deu
#define CYREG_B0_P0_U1_CFG31 0x000100dfu
#define CYREG_B0_P0_U1_DCFG0 0x000100e0u
#define CYREG_B0_P0_U1_DCFG1 0x000100e2u
#define CYREG_B0_P0_U1_DCFG2 0x000100e4u
#define CYREG_B0_P0_U1_DCFG3 0x000100e6u
#define CYREG_B0_P0_U1_DCFG4 0x000100e8u
#define CYREG_B0_P0_U1_DCFG5 0x000100eau
#define CYREG_B0_P0_U1_DCFG6 0x000100ecu
#define CYREG_B0_P0_U1_DCFG7 0x000100eeu
#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x00010100u
#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B0_P1_BASE 0x00010200u
#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu
#define CYDEV_UCFG_B0_P1_U0_BASE 0x00010200u
#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u
#define CYREG_B0_P1_U0_PLD_IT0 0x00010200u
#define CYREG_B0_P1_U0_PLD_IT1 0x00010204u
#define CYREG_B0_P1_U0_PLD_IT2 0x00010208u
#define CYREG_B0_P1_U0_PLD_IT3 0x0001020cu
#define CYREG_B0_P1_U0_PLD_IT4 0x00010210u
#define CYREG_B0_P1_U0_PLD_IT5 0x00010214u
#define CYREG_B0_P1_U0_PLD_IT6 0x00010218u
#define CYREG_B0_P1_U0_PLD_IT7 0x0001021cu
#define CYREG_B0_P1_U0_PLD_IT8 0x00010220u
#define CYREG_B0_P1_U0_PLD_IT9 0x00010224u
#define CYREG_B0_P1_U0_PLD_IT10 0x00010228u
#define CYREG_B0_P1_U0_PLD_IT11 0x0001022cu
#define CYREG_B0_P1_U0_PLD_ORT0 0x00010230u
#define CYREG_B0_P1_U0_PLD_ORT1 0x00010232u
#define CYREG_B0_P1_U0_PLD_ORT2 0x00010234u
#define CYREG_B0_P1_U0_PLD_ORT3 0x00010236u
#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x00010238u
#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x0001023au
#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x0001023cu
#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x0001023eu
#define CYREG_B0_P1_U0_CFG0 0x00010240u
#define CYREG_B0_P1_U0_CFG1 0x00010241u
#define CYREG_B0_P1_U0_CFG2 0x00010242u
#define CYREG_B0_P1_U0_CFG3 0x00010243u
#define CYREG_B0_P1_U0_CFG4 0x00010244u
#define CYREG_B0_P1_U0_CFG5 0x00010245u
#define CYREG_B0_P1_U0_CFG6 0x00010246u
#define CYREG_B0_P1_U0_CFG7 0x00010247u
#define CYREG_B0_P1_U0_CFG8 0x00010248u
#define CYREG_B0_P1_U0_CFG9 0x00010249u
#define CYREG_B0_P1_U0_CFG10 0x0001024au
#define CYREG_B0_P1_U0_CFG11 0x0001024bu
#define CYREG_B0_P1_U0_CFG12 0x0001024cu
#define CYREG_B0_P1_U0_CFG13 0x0001024du
#define CYREG_B0_P1_U0_CFG14 0x0001024eu
#define CYREG_B0_P1_U0_CFG15 0x0001024fu
#define CYREG_B0_P1_U0_CFG16 0x00010250u
#define CYREG_B0_P1_U0_CFG17 0x00010251u
#define CYREG_B0_P1_U0_CFG18 0x00010252u
#define CYREG_B0_P1_U0_CFG19 0x00010253u
#define CYREG_B0_P1_U0_CFG20 0x00010254u
#define CYREG_B0_P1_U0_CFG21 0x00010255u
#define CYREG_B0_P1_U0_CFG22 0x00010256u
#define CYREG_B0_P1_U0_CFG23 0x00010257u
#define CYREG_B0_P1_U0_CFG24 0x00010258u
#define CYREG_B0_P1_U0_CFG25 0x00010259u
#define CYREG_B0_P1_U0_CFG26 0x0001025au
#define CYREG_B0_P1_U0_CFG27 0x0001025bu
#define CYREG_B0_P1_U0_CFG28 0x0001025cu
#define CYREG_B0_P1_U0_CFG29 0x0001025du
#define CYREG_B0_P1_U0_CFG30 0x0001025eu
#define CYREG_B0_P1_U0_CFG31 0x0001025fu
#define CYREG_B0_P1_U0_DCFG0 0x00010260u
#define CYREG_B0_P1_U0_DCFG1 0x00010262u
#define CYREG_B0_P1_U0_DCFG2 0x00010264u
#define CYREG_B0_P1_U0_DCFG3 0x00010266u
#define CYREG_B0_P1_U0_DCFG4 0x00010268u
#define CYREG_B0_P1_U0_DCFG5 0x0001026au
#define CYREG_B0_P1_U0_DCFG6 0x0001026cu
#define CYREG_B0_P1_U0_DCFG7 0x0001026eu
#define CYDEV_UCFG_B0_P1_U1_BASE 0x00010280u
#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u
#define CYREG_B0_P1_U1_PLD_IT0 0x00010280u
#define CYREG_B0_P1_U1_PLD_IT1 0x00010284u
#define CYREG_B0_P1_U1_PLD_IT2 0x00010288u
#define CYREG_B0_P1_U1_PLD_IT3 0x0001028cu
#define CYREG_B0_P1_U1_PLD_IT4 0x00010290u
#define CYREG_B0_P1_U1_PLD_IT5 0x00010294u
#define CYREG_B0_P1_U1_PLD_IT6 0x00010298u
#define CYREG_B0_P1_U1_PLD_IT7 0x0001029cu
#define CYREG_B0_P1_U1_PLD_IT8 0x000102a0u
#define CYREG_B0_P1_U1_PLD_IT9 0x000102a4u
#define CYREG_B0_P1_U1_PLD_IT10 0x000102a8u
#define CYREG_B0_P1_U1_PLD_IT11 0x000102acu
#define CYREG_B0_P1_U1_PLD_ORT0 0x000102b0u
#define CYREG_B0_P1_U1_PLD_ORT1 0x000102b2u
#define CYREG_B0_P1_U1_PLD_ORT2 0x000102b4u
#define CYREG_B0_P1_U1_PLD_ORT3 0x000102b6u
#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x000102b8u
#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x000102bau
#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x000102bcu
#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x000102beu
#define CYREG_B0_P1_U1_CFG0 0x000102c0u
#define CYREG_B0_P1_U1_CFG1 0x000102c1u
#define CYREG_B0_P1_U1_CFG2 0x000102c2u
#define CYREG_B0_P1_U1_CFG3 0x000102c3u
#define CYREG_B0_P1_U1_CFG4 0x000102c4u
#define CYREG_B0_P1_U1_CFG5 0x000102c5u
#define CYREG_B0_P1_U1_CFG6 0x000102c6u
#define CYREG_B0_P1_U1_CFG7 0x000102c7u
#define CYREG_B0_P1_U1_CFG8 0x000102c8u
#define CYREG_B0_P1_U1_CFG9 0x000102c9u
#define CYREG_B0_P1_U1_CFG10 0x000102cau
#define CYREG_B0_P1_U1_CFG11 0x000102cbu
#define CYREG_B0_P1_U1_CFG12 0x000102ccu
#define CYREG_B0_P1_U1_CFG13 0x000102cdu
#define CYREG_B0_P1_U1_CFG14 0x000102ceu
#define CYREG_B0_P1_U1_CFG15 0x000102cfu
#define CYREG_B0_P1_U1_CFG16 0x000102d0u
#define CYREG_B0_P1_U1_CFG17 0x000102d1u
#define CYREG_B0_P1_U1_CFG18 0x000102d2u
#define CYREG_B0_P1_U1_CFG19 0x000102d3u
#define CYREG_B0_P1_U1_CFG20 0x000102d4u
#define CYREG_B0_P1_U1_CFG21 0x000102d5u
#define CYREG_B0_P1_U1_CFG22 0x000102d6u
#define CYREG_B0_P1_U1_CFG23 0x000102d7u
#define CYREG_B0_P1_U1_CFG24 0x000102d8u
#define CYREG_B0_P1_U1_CFG25 0x000102d9u
#define CYREG_B0_P1_U1_CFG26 0x000102dau
#define CYREG_B0_P1_U1_CFG27 0x000102dbu
#define CYREG_B0_P1_U1_CFG28 0x000102dcu
#define CYREG_B0_P1_U1_CFG29 0x000102ddu
#define CYREG_B0_P1_U1_CFG30 0x000102deu
#define CYREG_B0_P1_U1_CFG31 0x000102dfu
#define CYREG_B0_P1_U1_DCFG0 0x000102e0u
#define CYREG_B0_P1_U1_DCFG1 0x000102e2u
#define CYREG_B0_P1_U1_DCFG2 0x000102e4u
#define CYREG_B0_P1_U1_DCFG3 0x000102e6u
#define CYREG_B0_P1_U1_DCFG4 0x000102e8u
#define CYREG_B0_P1_U1_DCFG5 0x000102eau
#define CYREG_B0_P1_U1_DCFG6 0x000102ecu
#define CYREG_B0_P1_U1_DCFG7 0x000102eeu
#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x00010300u
#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B0_P2_BASE 0x00010400u
#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu
#define CYDEV_UCFG_B0_P2_U0_BASE 0x00010400u
#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u
#define CYREG_B0_P2_U0_PLD_IT0 0x00010400u
#define CYREG_B0_P2_U0_PLD_IT1 0x00010404u
#define CYREG_B0_P2_U0_PLD_IT2 0x00010408u
#define CYREG_B0_P2_U0_PLD_IT3 0x0001040cu
#define CYREG_B0_P2_U0_PLD_IT4 0x00010410u
#define CYREG_B0_P2_U0_PLD_IT5 0x00010414u
#define CYREG_B0_P2_U0_PLD_IT6 0x00010418u
#define CYREG_B0_P2_U0_PLD_IT7 0x0001041cu
#define CYREG_B0_P2_U0_PLD_IT8 0x00010420u
#define CYREG_B0_P2_U0_PLD_IT9 0x00010424u
#define CYREG_B0_P2_U0_PLD_IT10 0x00010428u
#define CYREG_B0_P2_U0_PLD_IT11 0x0001042cu
#define CYREG_B0_P2_U0_PLD_ORT0 0x00010430u
#define CYREG_B0_P2_U0_PLD_ORT1 0x00010432u
#define CYREG_B0_P2_U0_PLD_ORT2 0x00010434u
#define CYREG_B0_P2_U0_PLD_ORT3 0x00010436u
#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x00010438u
#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x0001043au
#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x0001043cu
#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x0001043eu
#define CYREG_B0_P2_U0_CFG0 0x00010440u
#define CYREG_B0_P2_U0_CFG1 0x00010441u
#define CYREG_B0_P2_U0_CFG2 0x00010442u
#define CYREG_B0_P2_U0_CFG3 0x00010443u
#define CYREG_B0_P2_U0_CFG4 0x00010444u
#define CYREG_B0_P2_U0_CFG5 0x00010445u
#define CYREG_B0_P2_U0_CFG6 0x00010446u
#define CYREG_B0_P2_U0_CFG7 0x00010447u
#define CYREG_B0_P2_U0_CFG8 0x00010448u
#define CYREG_B0_P2_U0_CFG9 0x00010449u
#define CYREG_B0_P2_U0_CFG10 0x0001044au
#define CYREG_B0_P2_U0_CFG11 0x0001044bu
#define CYREG_B0_P2_U0_CFG12 0x0001044cu
#define CYREG_B0_P2_U0_CFG13 0x0001044du
#define CYREG_B0_P2_U0_CFG14 0x0001044eu
#define CYREG_B0_P2_U0_CFG15 0x0001044fu
#define CYREG_B0_P2_U0_CFG16 0x00010450u
#define CYREG_B0_P2_U0_CFG17 0x00010451u
#define CYREG_B0_P2_U0_CFG18 0x00010452u
#define CYREG_B0_P2_U0_CFG19 0x00010453u
#define CYREG_B0_P2_U0_CFG20 0x00010454u
#define CYREG_B0_P2_U0_CFG21 0x00010455u
#define CYREG_B0_P2_U0_CFG22 0x00010456u
#define CYREG_B0_P2_U0_CFG23 0x00010457u
#define CYREG_B0_P2_U0_CFG24 0x00010458u
#define CYREG_B0_P2_U0_CFG25 0x00010459u
#define CYREG_B0_P2_U0_CFG26 0x0001045au
#define CYREG_B0_P2_U0_CFG27 0x0001045bu
#define CYREG_B0_P2_U0_CFG28 0x0001045cu
#define CYREG_B0_P2_U0_CFG29 0x0001045du
#define CYREG_B0_P2_U0_CFG30 0x0001045eu
#define CYREG_B0_P2_U0_CFG31 0x0001045fu
#define CYREG_B0_P2_U0_DCFG0 0x00010460u
#define CYREG_B0_P2_U0_DCFG1 0x00010462u
#define CYREG_B0_P2_U0_DCFG2 0x00010464u
#define CYREG_B0_P2_U0_DCFG3 0x00010466u
#define CYREG_B0_P2_U0_DCFG4 0x00010468u
#define CYREG_B0_P2_U0_DCFG5 0x0001046au
#define CYREG_B0_P2_U0_DCFG6 0x0001046cu
#define CYREG_B0_P2_U0_DCFG7 0x0001046eu
#define CYDEV_UCFG_B0_P2_U1_BASE 0x00010480u
#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u
#define CYREG_B0_P2_U1_PLD_IT0 0x00010480u
#define CYREG_B0_P2_U1_PLD_IT1 0x00010484u
#define CYREG_B0_P2_U1_PLD_IT2 0x00010488u
#define CYREG_B0_P2_U1_PLD_IT3 0x0001048cu
#define CYREG_B0_P2_U1_PLD_IT4 0x00010490u
#define CYREG_B0_P2_U1_PLD_IT5 0x00010494u
#define CYREG_B0_P2_U1_PLD_IT6 0x00010498u
#define CYREG_B0_P2_U1_PLD_IT7 0x0001049cu
#define CYREG_B0_P2_U1_PLD_IT8 0x000104a0u
#define CYREG_B0_P2_U1_PLD_IT9 0x000104a4u
#define CYREG_B0_P2_U1_PLD_IT10 0x000104a8u
#define CYREG_B0_P2_U1_PLD_IT11 0x000104acu
#define CYREG_B0_P2_U1_PLD_ORT0 0x000104b0u
#define CYREG_B0_P2_U1_PLD_ORT1 0x000104b2u
#define CYREG_B0_P2_U1_PLD_ORT2 0x000104b4u
#define CYREG_B0_P2_U1_PLD_ORT3 0x000104b6u
#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x000104b8u
#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x000104bau
#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x000104bcu
#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x000104beu
#define CYREG_B0_P2_U1_CFG0 0x000104c0u
#define CYREG_B0_P2_U1_CFG1 0x000104c1u
#define CYREG_B0_P2_U1_CFG2 0x000104c2u
#define CYREG_B0_P2_U1_CFG3 0x000104c3u
#define CYREG_B0_P2_U1_CFG4 0x000104c4u
#define CYREG_B0_P2_U1_CFG5 0x000104c5u
#define CYREG_B0_P2_U1_CFG6 0x000104c6u
#define CYREG_B0_P2_U1_CFG7 0x000104c7u
#define CYREG_B0_P2_U1_CFG8 0x000104c8u
#define CYREG_B0_P2_U1_CFG9 0x000104c9u
#define CYREG_B0_P2_U1_CFG10 0x000104cau
#define CYREG_B0_P2_U1_CFG11 0x000104cbu
#define CYREG_B0_P2_U1_CFG12 0x000104ccu
#define CYREG_B0_P2_U1_CFG13 0x000104cdu
#define CYREG_B0_P2_U1_CFG14 0x000104ceu
#define CYREG_B0_P2_U1_CFG15 0x000104cfu
#define CYREG_B0_P2_U1_CFG16 0x000104d0u
#define CYREG_B0_P2_U1_CFG17 0x000104d1u
#define CYREG_B0_P2_U1_CFG18 0x000104d2u
#define CYREG_B0_P2_U1_CFG19 0x000104d3u
#define CYREG_B0_P2_U1_CFG20 0x000104d4u
#define CYREG_B0_P2_U1_CFG21 0x000104d5u
#define CYREG_B0_P2_U1_CFG22 0x000104d6u
#define CYREG_B0_P2_U1_CFG23 0x000104d7u
#define CYREG_B0_P2_U1_CFG24 0x000104d8u
#define CYREG_B0_P2_U1_CFG25 0x000104d9u
#define CYREG_B0_P2_U1_CFG26 0x000104dau
#define CYREG_B0_P2_U1_CFG27 0x000104dbu
#define CYREG_B0_P2_U1_CFG28 0x000104dcu
#define CYREG_B0_P2_U1_CFG29 0x000104ddu
#define CYREG_B0_P2_U1_CFG30 0x000104deu
#define CYREG_B0_P2_U1_CFG31 0x000104dfu
#define CYREG_B0_P2_U1_DCFG0 0x000104e0u
#define CYREG_B0_P2_U1_DCFG1 0x000104e2u
#define CYREG_B0_P2_U1_DCFG2 0x000104e4u
#define CYREG_B0_P2_U1_DCFG3 0x000104e6u
#define CYREG_B0_P2_U1_DCFG4 0x000104e8u
#define CYREG_B0_P2_U1_DCFG5 0x000104eau
#define CYREG_B0_P2_U1_DCFG6 0x000104ecu
#define CYREG_B0_P2_U1_DCFG7 0x000104eeu
#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x00010500u
#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B0_P3_BASE 0x00010600u
#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu
#define CYDEV_UCFG_B0_P3_U0_BASE 0x00010600u
#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u
#define CYREG_B0_P3_U0_PLD_IT0 0x00010600u
#define CYREG_B0_P3_U0_PLD_IT1 0x00010604u
#define CYREG_B0_P3_U0_PLD_IT2 0x00010608u
#define CYREG_B0_P3_U0_PLD_IT3 0x0001060cu
#define CYREG_B0_P3_U0_PLD_IT4 0x00010610u
#define CYREG_B0_P3_U0_PLD_IT5 0x00010614u
#define CYREG_B0_P3_U0_PLD_IT6 0x00010618u
#define CYREG_B0_P3_U0_PLD_IT7 0x0001061cu
#define CYREG_B0_P3_U0_PLD_IT8 0x00010620u
#define CYREG_B0_P3_U0_PLD_IT9 0x00010624u
#define CYREG_B0_P3_U0_PLD_IT10 0x00010628u
#define CYREG_B0_P3_U0_PLD_IT11 0x0001062cu
#define CYREG_B0_P3_U0_PLD_ORT0 0x00010630u
#define CYREG_B0_P3_U0_PLD_ORT1 0x00010632u
#define CYREG_B0_P3_U0_PLD_ORT2 0x00010634u
#define CYREG_B0_P3_U0_PLD_ORT3 0x00010636u
#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x00010638u
#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x0001063au
#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x0001063cu
#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x0001063eu
#define CYREG_B0_P3_U0_CFG0 0x00010640u
#define CYREG_B0_P3_U0_CFG1 0x00010641u
#define CYREG_B0_P3_U0_CFG2 0x00010642u
#define CYREG_B0_P3_U0_CFG3 0x00010643u
#define CYREG_B0_P3_U0_CFG4 0x00010644u
#define CYREG_B0_P3_U0_CFG5 0x00010645u
#define CYREG_B0_P3_U0_CFG6 0x00010646u
#define CYREG_B0_P3_U0_CFG7 0x00010647u
#define CYREG_B0_P3_U0_CFG8 0x00010648u
#define CYREG_B0_P3_U0_CFG9 0x00010649u
#define CYREG_B0_P3_U0_CFG10 0x0001064au
#define CYREG_B0_P3_U0_CFG11 0x0001064bu
#define CYREG_B0_P3_U0_CFG12 0x0001064cu
#define CYREG_B0_P3_U0_CFG13 0x0001064du
#define CYREG_B0_P3_U0_CFG14 0x0001064eu
#define CYREG_B0_P3_U0_CFG15 0x0001064fu
#define CYREG_B0_P3_U0_CFG16 0x00010650u
#define CYREG_B0_P3_U0_CFG17 0x00010651u
#define CYREG_B0_P3_U0_CFG18 0x00010652u
#define CYREG_B0_P3_U0_CFG19 0x00010653u
#define CYREG_B0_P3_U0_CFG20 0x00010654u
#define CYREG_B0_P3_U0_CFG21 0x00010655u
#define CYREG_B0_P3_U0_CFG22 0x00010656u
#define CYREG_B0_P3_U0_CFG23 0x00010657u
#define CYREG_B0_P3_U0_CFG24 0x00010658u
#define CYREG_B0_P3_U0_CFG25 0x00010659u
#define CYREG_B0_P3_U0_CFG26 0x0001065au
#define CYREG_B0_P3_U0_CFG27 0x0001065bu
#define CYREG_B0_P3_U0_CFG28 0x0001065cu
#define CYREG_B0_P3_U0_CFG29 0x0001065du
#define CYREG_B0_P3_U0_CFG30 0x0001065eu
#define CYREG_B0_P3_U0_CFG31 0x0001065fu
#define CYREG_B0_P3_U0_DCFG0 0x00010660u
#define CYREG_B0_P3_U0_DCFG1 0x00010662u
#define CYREG_B0_P3_U0_DCFG2 0x00010664u
#define CYREG_B0_P3_U0_DCFG3 0x00010666u
#define CYREG_B0_P3_U0_DCFG4 0x00010668u
#define CYREG_B0_P3_U0_DCFG5 0x0001066au
#define CYREG_B0_P3_U0_DCFG6 0x0001066cu
#define CYREG_B0_P3_U0_DCFG7 0x0001066eu
#define CYDEV_UCFG_B0_P3_U1_BASE 0x00010680u
#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u
#define CYREG_B0_P3_U1_PLD_IT0 0x00010680u
#define CYREG_B0_P3_U1_PLD_IT1 0x00010684u
#define CYREG_B0_P3_U1_PLD_IT2 0x00010688u
#define CYREG_B0_P3_U1_PLD_IT3 0x0001068cu
#define CYREG_B0_P3_U1_PLD_IT4 0x00010690u
#define CYREG_B0_P3_U1_PLD_IT5 0x00010694u
#define CYREG_B0_P3_U1_PLD_IT6 0x00010698u
#define CYREG_B0_P3_U1_PLD_IT7 0x0001069cu
#define CYREG_B0_P3_U1_PLD_IT8 0x000106a0u
#define CYREG_B0_P3_U1_PLD_IT9 0x000106a4u
#define CYREG_B0_P3_U1_PLD_IT10 0x000106a8u
#define CYREG_B0_P3_U1_PLD_IT11 0x000106acu
#define CYREG_B0_P3_U1_PLD_ORT0 0x000106b0u
#define CYREG_B0_P3_U1_PLD_ORT1 0x000106b2u
#define CYREG_B0_P3_U1_PLD_ORT2 0x000106b4u
#define CYREG_B0_P3_U1_PLD_ORT3 0x000106b6u
#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x000106b8u
#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x000106bau
#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x000106bcu
#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x000106beu
#define CYREG_B0_P3_U1_CFG0 0x000106c0u
#define CYREG_B0_P3_U1_CFG1 0x000106c1u
#define CYREG_B0_P3_U1_CFG2 0x000106c2u
#define CYREG_B0_P3_U1_CFG3 0x000106c3u
#define CYREG_B0_P3_U1_CFG4 0x000106c4u
#define CYREG_B0_P3_U1_CFG5 0x000106c5u
#define CYREG_B0_P3_U1_CFG6 0x000106c6u
#define CYREG_B0_P3_U1_CFG7 0x000106c7u
#define CYREG_B0_P3_U1_CFG8 0x000106c8u
#define CYREG_B0_P3_U1_CFG9 0x000106c9u
#define CYREG_B0_P3_U1_CFG10 0x000106cau
#define CYREG_B0_P3_U1_CFG11 0x000106cbu
#define CYREG_B0_P3_U1_CFG12 0x000106ccu
#define CYREG_B0_P3_U1_CFG13 0x000106cdu
#define CYREG_B0_P3_U1_CFG14 0x000106ceu
#define CYREG_B0_P3_U1_CFG15 0x000106cfu
#define CYREG_B0_P3_U1_CFG16 0x000106d0u
#define CYREG_B0_P3_U1_CFG17 0x000106d1u
#define CYREG_B0_P3_U1_CFG18 0x000106d2u
#define CYREG_B0_P3_U1_CFG19 0x000106d3u
#define CYREG_B0_P3_U1_CFG20 0x000106d4u
#define CYREG_B0_P3_U1_CFG21 0x000106d5u
#define CYREG_B0_P3_U1_CFG22 0x000106d6u
#define CYREG_B0_P3_U1_CFG23 0x000106d7u
#define CYREG_B0_P3_U1_CFG24 0x000106d8u
#define CYREG_B0_P3_U1_CFG25 0x000106d9u
#define CYREG_B0_P3_U1_CFG26 0x000106dau
#define CYREG_B0_P3_U1_CFG27 0x000106dbu
#define CYREG_B0_P3_U1_CFG28 0x000106dcu
#define CYREG_B0_P3_U1_CFG29 0x000106ddu
#define CYREG_B0_P3_U1_CFG30 0x000106deu
#define CYREG_B0_P3_U1_CFG31 0x000106dfu
#define CYREG_B0_P3_U1_DCFG0 0x000106e0u
#define CYREG_B0_P3_U1_DCFG1 0x000106e2u
#define CYREG_B0_P3_U1_DCFG2 0x000106e4u
#define CYREG_B0_P3_U1_DCFG3 0x000106e6u
#define CYREG_B0_P3_U1_DCFG4 0x000106e8u
#define CYREG_B0_P3_U1_DCFG5 0x000106eau
#define CYREG_B0_P3_U1_DCFG6 0x000106ecu
#define CYREG_B0_P3_U1_DCFG7 0x000106eeu
#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x00010700u
#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B0_P4_BASE 0x00010800u
#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu
#define CYDEV_UCFG_B0_P4_U0_BASE 0x00010800u
#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u
#define CYREG_B0_P4_U0_PLD_IT0 0x00010800u
#define CYREG_B0_P4_U0_PLD_IT1 0x00010804u
#define CYREG_B0_P4_U0_PLD_IT2 0x00010808u
#define CYREG_B0_P4_U0_PLD_IT3 0x0001080cu
#define CYREG_B0_P4_U0_PLD_IT4 0x00010810u
#define CYREG_B0_P4_U0_PLD_IT5 0x00010814u
#define CYREG_B0_P4_U0_PLD_IT6 0x00010818u
#define CYREG_B0_P4_U0_PLD_IT7 0x0001081cu
#define CYREG_B0_P4_U0_PLD_IT8 0x00010820u
#define CYREG_B0_P4_U0_PLD_IT9 0x00010824u
#define CYREG_B0_P4_U0_PLD_IT10 0x00010828u
#define CYREG_B0_P4_U0_PLD_IT11 0x0001082cu
#define CYREG_B0_P4_U0_PLD_ORT0 0x00010830u
#define CYREG_B0_P4_U0_PLD_ORT1 0x00010832u
#define CYREG_B0_P4_U0_PLD_ORT2 0x00010834u
#define CYREG_B0_P4_U0_PLD_ORT3 0x00010836u
#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x00010838u
#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x0001083au
#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x0001083cu
#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x0001083eu
#define CYREG_B0_P4_U0_CFG0 0x00010840u
#define CYREG_B0_P4_U0_CFG1 0x00010841u
#define CYREG_B0_P4_U0_CFG2 0x00010842u
#define CYREG_B0_P4_U0_CFG3 0x00010843u
#define CYREG_B0_P4_U0_CFG4 0x00010844u
#define CYREG_B0_P4_U0_CFG5 0x00010845u
#define CYREG_B0_P4_U0_CFG6 0x00010846u
#define CYREG_B0_P4_U0_CFG7 0x00010847u
#define CYREG_B0_P4_U0_CFG8 0x00010848u
#define CYREG_B0_P4_U0_CFG9 0x00010849u
#define CYREG_B0_P4_U0_CFG10 0x0001084au
#define CYREG_B0_P4_U0_CFG11 0x0001084bu
#define CYREG_B0_P4_U0_CFG12 0x0001084cu
#define CYREG_B0_P4_U0_CFG13 0x0001084du
#define CYREG_B0_P4_U0_CFG14 0x0001084eu
#define CYREG_B0_P4_U0_CFG15 0x0001084fu
#define CYREG_B0_P4_U0_CFG16 0x00010850u
#define CYREG_B0_P4_U0_CFG17 0x00010851u
#define CYREG_B0_P4_U0_CFG18 0x00010852u
#define CYREG_B0_P4_U0_CFG19 0x00010853u
#define CYREG_B0_P4_U0_CFG20 0x00010854u
#define CYREG_B0_P4_U0_CFG21 0x00010855u
#define CYREG_B0_P4_U0_CFG22 0x00010856u
#define CYREG_B0_P4_U0_CFG23 0x00010857u
#define CYREG_B0_P4_U0_CFG24 0x00010858u
#define CYREG_B0_P4_U0_CFG25 0x00010859u
#define CYREG_B0_P4_U0_CFG26 0x0001085au
#define CYREG_B0_P4_U0_CFG27 0x0001085bu
#define CYREG_B0_P4_U0_CFG28 0x0001085cu
#define CYREG_B0_P4_U0_CFG29 0x0001085du
#define CYREG_B0_P4_U0_CFG30 0x0001085eu
#define CYREG_B0_P4_U0_CFG31 0x0001085fu
#define CYREG_B0_P4_U0_DCFG0 0x00010860u
#define CYREG_B0_P4_U0_DCFG1 0x00010862u
#define CYREG_B0_P4_U0_DCFG2 0x00010864u
#define CYREG_B0_P4_U0_DCFG3 0x00010866u
#define CYREG_B0_P4_U0_DCFG4 0x00010868u
#define CYREG_B0_P4_U0_DCFG5 0x0001086au
#define CYREG_B0_P4_U0_DCFG6 0x0001086cu
#define CYREG_B0_P4_U0_DCFG7 0x0001086eu
#define CYDEV_UCFG_B0_P4_U1_BASE 0x00010880u
#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u
#define CYREG_B0_P4_U1_PLD_IT0 0x00010880u
#define CYREG_B0_P4_U1_PLD_IT1 0x00010884u
#define CYREG_B0_P4_U1_PLD_IT2 0x00010888u
#define CYREG_B0_P4_U1_PLD_IT3 0x0001088cu
#define CYREG_B0_P4_U1_PLD_IT4 0x00010890u
#define CYREG_B0_P4_U1_PLD_IT5 0x00010894u
#define CYREG_B0_P4_U1_PLD_IT6 0x00010898u
#define CYREG_B0_P4_U1_PLD_IT7 0x0001089cu
#define CYREG_B0_P4_U1_PLD_IT8 0x000108a0u
#define CYREG_B0_P4_U1_PLD_IT9 0x000108a4u
#define CYREG_B0_P4_U1_PLD_IT10 0x000108a8u
#define CYREG_B0_P4_U1_PLD_IT11 0x000108acu
#define CYREG_B0_P4_U1_PLD_ORT0 0x000108b0u
#define CYREG_B0_P4_U1_PLD_ORT1 0x000108b2u
#define CYREG_B0_P4_U1_PLD_ORT2 0x000108b4u
#define CYREG_B0_P4_U1_PLD_ORT3 0x000108b6u
#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x000108b8u
#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x000108bau
#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x000108bcu
#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x000108beu
#define CYREG_B0_P4_U1_CFG0 0x000108c0u
#define CYREG_B0_P4_U1_CFG1 0x000108c1u
#define CYREG_B0_P4_U1_CFG2 0x000108c2u
#define CYREG_B0_P4_U1_CFG3 0x000108c3u
#define CYREG_B0_P4_U1_CFG4 0x000108c4u
#define CYREG_B0_P4_U1_CFG5 0x000108c5u
#define CYREG_B0_P4_U1_CFG6 0x000108c6u
#define CYREG_B0_P4_U1_CFG7 0x000108c7u
#define CYREG_B0_P4_U1_CFG8 0x000108c8u
#define CYREG_B0_P4_U1_CFG9 0x000108c9u
#define CYREG_B0_P4_U1_CFG10 0x000108cau
#define CYREG_B0_P4_U1_CFG11 0x000108cbu
#define CYREG_B0_P4_U1_CFG12 0x000108ccu
#define CYREG_B0_P4_U1_CFG13 0x000108cdu
#define CYREG_B0_P4_U1_CFG14 0x000108ceu
#define CYREG_B0_P4_U1_CFG15 0x000108cfu
#define CYREG_B0_P4_U1_CFG16 0x000108d0u
#define CYREG_B0_P4_U1_CFG17 0x000108d1u
#define CYREG_B0_P4_U1_CFG18 0x000108d2u
#define CYREG_B0_P4_U1_CFG19 0x000108d3u
#define CYREG_B0_P4_U1_CFG20 0x000108d4u
#define CYREG_B0_P4_U1_CFG21 0x000108d5u
#define CYREG_B0_P4_U1_CFG22 0x000108d6u
#define CYREG_B0_P4_U1_CFG23 0x000108d7u
#define CYREG_B0_P4_U1_CFG24 0x000108d8u
#define CYREG_B0_P4_U1_CFG25 0x000108d9u
#define CYREG_B0_P4_U1_CFG26 0x000108dau
#define CYREG_B0_P4_U1_CFG27 0x000108dbu
#define CYREG_B0_P4_U1_CFG28 0x000108dcu
#define CYREG_B0_P4_U1_CFG29 0x000108ddu
#define CYREG_B0_P4_U1_CFG30 0x000108deu
#define CYREG_B0_P4_U1_CFG31 0x000108dfu
#define CYREG_B0_P4_U1_DCFG0 0x000108e0u
#define CYREG_B0_P4_U1_DCFG1 0x000108e2u
#define CYREG_B0_P4_U1_DCFG2 0x000108e4u
#define CYREG_B0_P4_U1_DCFG3 0x000108e6u
#define CYREG_B0_P4_U1_DCFG4 0x000108e8u
#define CYREG_B0_P4_U1_DCFG5 0x000108eau
#define CYREG_B0_P4_U1_DCFG6 0x000108ecu
#define CYREG_B0_P4_U1_DCFG7 0x000108eeu
#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x00010900u
#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B0_P5_BASE 0x00010a00u
#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu
#define CYDEV_UCFG_B0_P5_U0_BASE 0x00010a00u
#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u
#define CYREG_B0_P5_U0_PLD_IT0 0x00010a00u
#define CYREG_B0_P5_U0_PLD_IT1 0x00010a04u
#define CYREG_B0_P5_U0_PLD_IT2 0x00010a08u
#define CYREG_B0_P5_U0_PLD_IT3 0x00010a0cu
#define CYREG_B0_P5_U0_PLD_IT4 0x00010a10u
#define CYREG_B0_P5_U0_PLD_IT5 0x00010a14u
#define CYREG_B0_P5_U0_PLD_IT6 0x00010a18u
#define CYREG_B0_P5_U0_PLD_IT7 0x00010a1cu
#define CYREG_B0_P5_U0_PLD_IT8 0x00010a20u
#define CYREG_B0_P5_U0_PLD_IT9 0x00010a24u
#define CYREG_B0_P5_U0_PLD_IT10 0x00010a28u
#define CYREG_B0_P5_U0_PLD_IT11 0x00010a2cu
#define CYREG_B0_P5_U0_PLD_ORT0 0x00010a30u
#define CYREG_B0_P5_U0_PLD_ORT1 0x00010a32u
#define CYREG_B0_P5_U0_PLD_ORT2 0x00010a34u
#define CYREG_B0_P5_U0_PLD_ORT3 0x00010a36u
#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x00010a38u
#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x00010a3au
#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x00010a3cu
#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x00010a3eu
#define CYREG_B0_P5_U0_CFG0 0x00010a40u
#define CYREG_B0_P5_U0_CFG1 0x00010a41u
#define CYREG_B0_P5_U0_CFG2 0x00010a42u
#define CYREG_B0_P5_U0_CFG3 0x00010a43u
#define CYREG_B0_P5_U0_CFG4 0x00010a44u
#define CYREG_B0_P5_U0_CFG5 0x00010a45u
#define CYREG_B0_P5_U0_CFG6 0x00010a46u
#define CYREG_B0_P5_U0_CFG7 0x00010a47u
#define CYREG_B0_P5_U0_CFG8 0x00010a48u
#define CYREG_B0_P5_U0_CFG9 0x00010a49u
#define CYREG_B0_P5_U0_CFG10 0x00010a4au
#define CYREG_B0_P5_U0_CFG11 0x00010a4bu
#define CYREG_B0_P5_U0_CFG12 0x00010a4cu
#define CYREG_B0_P5_U0_CFG13 0x00010a4du
#define CYREG_B0_P5_U0_CFG14 0x00010a4eu
#define CYREG_B0_P5_U0_CFG15 0x00010a4fu
#define CYREG_B0_P5_U0_CFG16 0x00010a50u
#define CYREG_B0_P5_U0_CFG17 0x00010a51u
#define CYREG_B0_P5_U0_CFG18 0x00010a52u
#define CYREG_B0_P5_U0_CFG19 0x00010a53u
#define CYREG_B0_P5_U0_CFG20 0x00010a54u
#define CYREG_B0_P5_U0_CFG21 0x00010a55u
#define CYREG_B0_P5_U0_CFG22 0x00010a56u
#define CYREG_B0_P5_U0_CFG23 0x00010a57u
#define CYREG_B0_P5_U0_CFG24 0x00010a58u
#define CYREG_B0_P5_U0_CFG25 0x00010a59u
#define CYREG_B0_P5_U0_CFG26 0x00010a5au
#define CYREG_B0_P5_U0_CFG27 0x00010a5bu
#define CYREG_B0_P5_U0_CFG28 0x00010a5cu
#define CYREG_B0_P5_U0_CFG29 0x00010a5du
#define CYREG_B0_P5_U0_CFG30 0x00010a5eu
#define CYREG_B0_P5_U0_CFG31 0x00010a5fu
#define CYREG_B0_P5_U0_DCFG0 0x00010a60u
#define CYREG_B0_P5_U0_DCFG1 0x00010a62u
#define CYREG_B0_P5_U0_DCFG2 0x00010a64u
#define CYREG_B0_P5_U0_DCFG3 0x00010a66u
#define CYREG_B0_P5_U0_DCFG4 0x00010a68u
#define CYREG_B0_P5_U0_DCFG5 0x00010a6au
#define CYREG_B0_P5_U0_DCFG6 0x00010a6cu
#define CYREG_B0_P5_U0_DCFG7 0x00010a6eu
#define CYDEV_UCFG_B0_P5_U1_BASE 0x00010a80u
#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u
#define CYREG_B0_P5_U1_PLD_IT0 0x00010a80u
#define CYREG_B0_P5_U1_PLD_IT1 0x00010a84u
#define CYREG_B0_P5_U1_PLD_IT2 0x00010a88u
#define CYREG_B0_P5_U1_PLD_IT3 0x00010a8cu
#define CYREG_B0_P5_U1_PLD_IT4 0x00010a90u
#define CYREG_B0_P5_U1_PLD_IT5 0x00010a94u
#define CYREG_B0_P5_U1_PLD_IT6 0x00010a98u
#define CYREG_B0_P5_U1_PLD_IT7 0x00010a9cu
#define CYREG_B0_P5_U1_PLD_IT8 0x00010aa0u
#define CYREG_B0_P5_U1_PLD_IT9 0x00010aa4u
#define CYREG_B0_P5_U1_PLD_IT10 0x00010aa8u
#define CYREG_B0_P5_U1_PLD_IT11 0x00010aacu
#define CYREG_B0_P5_U1_PLD_ORT0 0x00010ab0u
#define CYREG_B0_P5_U1_PLD_ORT1 0x00010ab2u
#define CYREG_B0_P5_U1_PLD_ORT2 0x00010ab4u
#define CYREG_B0_P5_U1_PLD_ORT3 0x00010ab6u
#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x00010ab8u
#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x00010abau
#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x00010abcu
#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x00010abeu
#define CYREG_B0_P5_U1_CFG0 0x00010ac0u
#define CYREG_B0_P5_U1_CFG1 0x00010ac1u
#define CYREG_B0_P5_U1_CFG2 0x00010ac2u
#define CYREG_B0_P5_U1_CFG3 0x00010ac3u
#define CYREG_B0_P5_U1_CFG4 0x00010ac4u
#define CYREG_B0_P5_U1_CFG5 0x00010ac5u
#define CYREG_B0_P5_U1_CFG6 0x00010ac6u
#define CYREG_B0_P5_U1_CFG7 0x00010ac7u
#define CYREG_B0_P5_U1_CFG8 0x00010ac8u
#define CYREG_B0_P5_U1_CFG9 0x00010ac9u
#define CYREG_B0_P5_U1_CFG10 0x00010acau
#define CYREG_B0_P5_U1_CFG11 0x00010acbu
#define CYREG_B0_P5_U1_CFG12 0x00010accu
#define CYREG_B0_P5_U1_CFG13 0x00010acdu
#define CYREG_B0_P5_U1_CFG14 0x00010aceu
#define CYREG_B0_P5_U1_CFG15 0x00010acfu
#define CYREG_B0_P5_U1_CFG16 0x00010ad0u
#define CYREG_B0_P5_U1_CFG17 0x00010ad1u
#define CYREG_B0_P5_U1_CFG18 0x00010ad2u
#define CYREG_B0_P5_U1_CFG19 0x00010ad3u
#define CYREG_B0_P5_U1_CFG20 0x00010ad4u
#define CYREG_B0_P5_U1_CFG21 0x00010ad5u
#define CYREG_B0_P5_U1_CFG22 0x00010ad6u
#define CYREG_B0_P5_U1_CFG23 0x00010ad7u
#define CYREG_B0_P5_U1_CFG24 0x00010ad8u
#define CYREG_B0_P5_U1_CFG25 0x00010ad9u
#define CYREG_B0_P5_U1_CFG26 0x00010adau
#define CYREG_B0_P5_U1_CFG27 0x00010adbu
#define CYREG_B0_P5_U1_CFG28 0x00010adcu
#define CYREG_B0_P5_U1_CFG29 0x00010addu
#define CYREG_B0_P5_U1_CFG30 0x00010adeu
#define CYREG_B0_P5_U1_CFG31 0x00010adfu
#define CYREG_B0_P5_U1_DCFG0 0x00010ae0u
#define CYREG_B0_P5_U1_DCFG1 0x00010ae2u
#define CYREG_B0_P5_U1_DCFG2 0x00010ae4u
#define CYREG_B0_P5_U1_DCFG3 0x00010ae6u
#define CYREG_B0_P5_U1_DCFG4 0x00010ae8u
#define CYREG_B0_P5_U1_DCFG5 0x00010aeau
#define CYREG_B0_P5_U1_DCFG6 0x00010aecu
#define CYREG_B0_P5_U1_DCFG7 0x00010aeeu
#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x00010b00u
#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B0_P6_BASE 0x00010c00u
#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu
#define CYDEV_UCFG_B0_P6_U0_BASE 0x00010c00u
#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u
#define CYREG_B0_P6_U0_PLD_IT0 0x00010c00u
#define CYREG_B0_P6_U0_PLD_IT1 0x00010c04u
#define CYREG_B0_P6_U0_PLD_IT2 0x00010c08u
#define CYREG_B0_P6_U0_PLD_IT3 0x00010c0cu
#define CYREG_B0_P6_U0_PLD_IT4 0x00010c10u
#define CYREG_B0_P6_U0_PLD_IT5 0x00010c14u
#define CYREG_B0_P6_U0_PLD_IT6 0x00010c18u
#define CYREG_B0_P6_U0_PLD_IT7 0x00010c1cu
#define CYREG_B0_P6_U0_PLD_IT8 0x00010c20u
#define CYREG_B0_P6_U0_PLD_IT9 0x00010c24u
#define CYREG_B0_P6_U0_PLD_IT10 0x00010c28u
#define CYREG_B0_P6_U0_PLD_IT11 0x00010c2cu
#define CYREG_B0_P6_U0_PLD_ORT0 0x00010c30u
#define CYREG_B0_P6_U0_PLD_ORT1 0x00010c32u
#define CYREG_B0_P6_U0_PLD_ORT2 0x00010c34u
#define CYREG_B0_P6_U0_PLD_ORT3 0x00010c36u
#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x00010c38u
#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x00010c3au
#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x00010c3cu
#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x00010c3eu
#define CYREG_B0_P6_U0_CFG0 0x00010c40u
#define CYREG_B0_P6_U0_CFG1 0x00010c41u
#define CYREG_B0_P6_U0_CFG2 0x00010c42u
#define CYREG_B0_P6_U0_CFG3 0x00010c43u
#define CYREG_B0_P6_U0_CFG4 0x00010c44u
#define CYREG_B0_P6_U0_CFG5 0x00010c45u
#define CYREG_B0_P6_U0_CFG6 0x00010c46u
#define CYREG_B0_P6_U0_CFG7 0x00010c47u
#define CYREG_B0_P6_U0_CFG8 0x00010c48u
#define CYREG_B0_P6_U0_CFG9 0x00010c49u
#define CYREG_B0_P6_U0_CFG10 0x00010c4au
#define CYREG_B0_P6_U0_CFG11 0x00010c4bu
#define CYREG_B0_P6_U0_CFG12 0x00010c4cu
#define CYREG_B0_P6_U0_CFG13 0x00010c4du
#define CYREG_B0_P6_U0_CFG14 0x00010c4eu
#define CYREG_B0_P6_U0_CFG15 0x00010c4fu
#define CYREG_B0_P6_U0_CFG16 0x00010c50u
#define CYREG_B0_P6_U0_CFG17 0x00010c51u
#define CYREG_B0_P6_U0_CFG18 0x00010c52u
#define CYREG_B0_P6_U0_CFG19 0x00010c53u
#define CYREG_B0_P6_U0_CFG20 0x00010c54u
#define CYREG_B0_P6_U0_CFG21 0x00010c55u
#define CYREG_B0_P6_U0_CFG22 0x00010c56u
#define CYREG_B0_P6_U0_CFG23 0x00010c57u
#define CYREG_B0_P6_U0_CFG24 0x00010c58u
#define CYREG_B0_P6_U0_CFG25 0x00010c59u
#define CYREG_B0_P6_U0_CFG26 0x00010c5au
#define CYREG_B0_P6_U0_CFG27 0x00010c5bu
#define CYREG_B0_P6_U0_CFG28 0x00010c5cu
#define CYREG_B0_P6_U0_CFG29 0x00010c5du
#define CYREG_B0_P6_U0_CFG30 0x00010c5eu
#define CYREG_B0_P6_U0_CFG31 0x00010c5fu
#define CYREG_B0_P6_U0_DCFG0 0x00010c60u
#define CYREG_B0_P6_U0_DCFG1 0x00010c62u
#define CYREG_B0_P6_U0_DCFG2 0x00010c64u
#define CYREG_B0_P6_U0_DCFG3 0x00010c66u
#define CYREG_B0_P6_U0_DCFG4 0x00010c68u
#define CYREG_B0_P6_U0_DCFG5 0x00010c6au
#define CYREG_B0_P6_U0_DCFG6 0x00010c6cu
#define CYREG_B0_P6_U0_DCFG7 0x00010c6eu
#define CYDEV_UCFG_B0_P6_U1_BASE 0x00010c80u
#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u
#define CYREG_B0_P6_U1_PLD_IT0 0x00010c80u
#define CYREG_B0_P6_U1_PLD_IT1 0x00010c84u
#define CYREG_B0_P6_U1_PLD_IT2 0x00010c88u
#define CYREG_B0_P6_U1_PLD_IT3 0x00010c8cu
#define CYREG_B0_P6_U1_PLD_IT4 0x00010c90u
#define CYREG_B0_P6_U1_PLD_IT5 0x00010c94u
#define CYREG_B0_P6_U1_PLD_IT6 0x00010c98u
#define CYREG_B0_P6_U1_PLD_IT7 0x00010c9cu
#define CYREG_B0_P6_U1_PLD_IT8 0x00010ca0u
#define CYREG_B0_P6_U1_PLD_IT9 0x00010ca4u
#define CYREG_B0_P6_U1_PLD_IT10 0x00010ca8u
#define CYREG_B0_P6_U1_PLD_IT11 0x00010cacu
#define CYREG_B0_P6_U1_PLD_ORT0 0x00010cb0u
#define CYREG_B0_P6_U1_PLD_ORT1 0x00010cb2u
#define CYREG_B0_P6_U1_PLD_ORT2 0x00010cb4u
#define CYREG_B0_P6_U1_PLD_ORT3 0x00010cb6u
#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x00010cb8u
#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x00010cbau
#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x00010cbcu
#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x00010cbeu
#define CYREG_B0_P6_U1_CFG0 0x00010cc0u
#define CYREG_B0_P6_U1_CFG1 0x00010cc1u
#define CYREG_B0_P6_U1_CFG2 0x00010cc2u
#define CYREG_B0_P6_U1_CFG3 0x00010cc3u
#define CYREG_B0_P6_U1_CFG4 0x00010cc4u
#define CYREG_B0_P6_U1_CFG5 0x00010cc5u
#define CYREG_B0_P6_U1_CFG6 0x00010cc6u
#define CYREG_B0_P6_U1_CFG7 0x00010cc7u
#define CYREG_B0_P6_U1_CFG8 0x00010cc8u
#define CYREG_B0_P6_U1_CFG9 0x00010cc9u
#define CYREG_B0_P6_U1_CFG10 0x00010ccau
#define CYREG_B0_P6_U1_CFG11 0x00010ccbu
#define CYREG_B0_P6_U1_CFG12 0x00010cccu
#define CYREG_B0_P6_U1_CFG13 0x00010ccdu
#define CYREG_B0_P6_U1_CFG14 0x00010cceu
#define CYREG_B0_P6_U1_CFG15 0x00010ccfu
#define CYREG_B0_P6_U1_CFG16 0x00010cd0u
#define CYREG_B0_P6_U1_CFG17 0x00010cd1u
#define CYREG_B0_P6_U1_CFG18 0x00010cd2u
#define CYREG_B0_P6_U1_CFG19 0x00010cd3u
#define CYREG_B0_P6_U1_CFG20 0x00010cd4u
#define CYREG_B0_P6_U1_CFG21 0x00010cd5u
#define CYREG_B0_P6_U1_CFG22 0x00010cd6u
#define CYREG_B0_P6_U1_CFG23 0x00010cd7u
#define CYREG_B0_P6_U1_CFG24 0x00010cd8u
#define CYREG_B0_P6_U1_CFG25 0x00010cd9u
#define CYREG_B0_P6_U1_CFG26 0x00010cdau
#define CYREG_B0_P6_U1_CFG27 0x00010cdbu
#define CYREG_B0_P6_U1_CFG28 0x00010cdcu
#define CYREG_B0_P6_U1_CFG29 0x00010cddu
#define CYREG_B0_P6_U1_CFG30 0x00010cdeu
#define CYREG_B0_P6_U1_CFG31 0x00010cdfu
#define CYREG_B0_P6_U1_DCFG0 0x00010ce0u
#define CYREG_B0_P6_U1_DCFG1 0x00010ce2u
#define CYREG_B0_P6_U1_DCFG2 0x00010ce4u
#define CYREG_B0_P6_U1_DCFG3 0x00010ce6u
#define CYREG_B0_P6_U1_DCFG4 0x00010ce8u
#define CYREG_B0_P6_U1_DCFG5 0x00010ceau
#define CYREG_B0_P6_U1_DCFG6 0x00010cecu
#define CYREG_B0_P6_U1_DCFG7 0x00010ceeu
#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x00010d00u
#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B0_P7_BASE 0x00010e00u
#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu
#define CYDEV_UCFG_B0_P7_U0_BASE 0x00010e00u
#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u
#define CYREG_B0_P7_U0_PLD_IT0 0x00010e00u
#define CYREG_B0_P7_U0_PLD_IT1 0x00010e04u
#define CYREG_B0_P7_U0_PLD_IT2 0x00010e08u
#define CYREG_B0_P7_U0_PLD_IT3 0x00010e0cu
#define CYREG_B0_P7_U0_PLD_IT4 0x00010e10u
#define CYREG_B0_P7_U0_PLD_IT5 0x00010e14u
#define CYREG_B0_P7_U0_PLD_IT6 0x00010e18u
#define CYREG_B0_P7_U0_PLD_IT7 0x00010e1cu
#define CYREG_B0_P7_U0_PLD_IT8 0x00010e20u
#define CYREG_B0_P7_U0_PLD_IT9 0x00010e24u
#define CYREG_B0_P7_U0_PLD_IT10 0x00010e28u
#define CYREG_B0_P7_U0_PLD_IT11 0x00010e2cu
#define CYREG_B0_P7_U0_PLD_ORT0 0x00010e30u
#define CYREG_B0_P7_U0_PLD_ORT1 0x00010e32u
#define CYREG_B0_P7_U0_PLD_ORT2 0x00010e34u
#define CYREG_B0_P7_U0_PLD_ORT3 0x00010e36u
#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x00010e38u
#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x00010e3au
#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x00010e3cu
#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x00010e3eu
#define CYREG_B0_P7_U0_CFG0 0x00010e40u
#define CYREG_B0_P7_U0_CFG1 0x00010e41u
#define CYREG_B0_P7_U0_CFG2 0x00010e42u
#define CYREG_B0_P7_U0_CFG3 0x00010e43u
#define CYREG_B0_P7_U0_CFG4 0x00010e44u
#define CYREG_B0_P7_U0_CFG5 0x00010e45u
#define CYREG_B0_P7_U0_CFG6 0x00010e46u
#define CYREG_B0_P7_U0_CFG7 0x00010e47u
#define CYREG_B0_P7_U0_CFG8 0x00010e48u
#define CYREG_B0_P7_U0_CFG9 0x00010e49u
#define CYREG_B0_P7_U0_CFG10 0x00010e4au
#define CYREG_B0_P7_U0_CFG11 0x00010e4bu
#define CYREG_B0_P7_U0_CFG12 0x00010e4cu
#define CYREG_B0_P7_U0_CFG13 0x00010e4du
#define CYREG_B0_P7_U0_CFG14 0x00010e4eu
#define CYREG_B0_P7_U0_CFG15 0x00010e4fu
#define CYREG_B0_P7_U0_CFG16 0x00010e50u
#define CYREG_B0_P7_U0_CFG17 0x00010e51u
#define CYREG_B0_P7_U0_CFG18 0x00010e52u
#define CYREG_B0_P7_U0_CFG19 0x00010e53u
#define CYREG_B0_P7_U0_CFG20 0x00010e54u
#define CYREG_B0_P7_U0_CFG21 0x00010e55u
#define CYREG_B0_P7_U0_CFG22 0x00010e56u
#define CYREG_B0_P7_U0_CFG23 0x00010e57u
#define CYREG_B0_P7_U0_CFG24 0x00010e58u
#define CYREG_B0_P7_U0_CFG25 0x00010e59u
#define CYREG_B0_P7_U0_CFG26 0x00010e5au
#define CYREG_B0_P7_U0_CFG27 0x00010e5bu
#define CYREG_B0_P7_U0_CFG28 0x00010e5cu
#define CYREG_B0_P7_U0_CFG29 0x00010e5du
#define CYREG_B0_P7_U0_CFG30 0x00010e5eu
#define CYREG_B0_P7_U0_CFG31 0x00010e5fu
#define CYREG_B0_P7_U0_DCFG0 0x00010e60u
#define CYREG_B0_P7_U0_DCFG1 0x00010e62u
#define CYREG_B0_P7_U0_DCFG2 0x00010e64u
#define CYREG_B0_P7_U0_DCFG3 0x00010e66u
#define CYREG_B0_P7_U0_DCFG4 0x00010e68u
#define CYREG_B0_P7_U0_DCFG5 0x00010e6au
#define CYREG_B0_P7_U0_DCFG6 0x00010e6cu
#define CYREG_B0_P7_U0_DCFG7 0x00010e6eu
#define CYDEV_UCFG_B0_P7_U1_BASE 0x00010e80u
#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u
#define CYREG_B0_P7_U1_PLD_IT0 0x00010e80u
#define CYREG_B0_P7_U1_PLD_IT1 0x00010e84u
#define CYREG_B0_P7_U1_PLD_IT2 0x00010e88u
#define CYREG_B0_P7_U1_PLD_IT3 0x00010e8cu
#define CYREG_B0_P7_U1_PLD_IT4 0x00010e90u
#define CYREG_B0_P7_U1_PLD_IT5 0x00010e94u
#define CYREG_B0_P7_U1_PLD_IT6 0x00010e98u
#define CYREG_B0_P7_U1_PLD_IT7 0x00010e9cu
#define CYREG_B0_P7_U1_PLD_IT8 0x00010ea0u
#define CYREG_B0_P7_U1_PLD_IT9 0x00010ea4u
#define CYREG_B0_P7_U1_PLD_IT10 0x00010ea8u
#define CYREG_B0_P7_U1_PLD_IT11 0x00010eacu
#define CYREG_B0_P7_U1_PLD_ORT0 0x00010eb0u
#define CYREG_B0_P7_U1_PLD_ORT1 0x00010eb2u
#define CYREG_B0_P7_U1_PLD_ORT2 0x00010eb4u
#define CYREG_B0_P7_U1_PLD_ORT3 0x00010eb6u
#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x00010eb8u
#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x00010ebau
#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x00010ebcu
#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x00010ebeu
#define CYREG_B0_P7_U1_CFG0 0x00010ec0u
#define CYREG_B0_P7_U1_CFG1 0x00010ec1u
#define CYREG_B0_P7_U1_CFG2 0x00010ec2u
#define CYREG_B0_P7_U1_CFG3 0x00010ec3u
#define CYREG_B0_P7_U1_CFG4 0x00010ec4u
#define CYREG_B0_P7_U1_CFG5 0x00010ec5u
#define CYREG_B0_P7_U1_CFG6 0x00010ec6u
#define CYREG_B0_P7_U1_CFG7 0x00010ec7u
#define CYREG_B0_P7_U1_CFG8 0x00010ec8u
#define CYREG_B0_P7_U1_CFG9 0x00010ec9u
#define CYREG_B0_P7_U1_CFG10 0x00010ecau
#define CYREG_B0_P7_U1_CFG11 0x00010ecbu
#define CYREG_B0_P7_U1_CFG12 0x00010eccu
#define CYREG_B0_P7_U1_CFG13 0x00010ecdu
#define CYREG_B0_P7_U1_CFG14 0x00010eceu
#define CYREG_B0_P7_U1_CFG15 0x00010ecfu
#define CYREG_B0_P7_U1_CFG16 0x00010ed0u
#define CYREG_B0_P7_U1_CFG17 0x00010ed1u
#define CYREG_B0_P7_U1_CFG18 0x00010ed2u
#define CYREG_B0_P7_U1_CFG19 0x00010ed3u
#define CYREG_B0_P7_U1_CFG20 0x00010ed4u
#define CYREG_B0_P7_U1_CFG21 0x00010ed5u
#define CYREG_B0_P7_U1_CFG22 0x00010ed6u
#define CYREG_B0_P7_U1_CFG23 0x00010ed7u
#define CYREG_B0_P7_U1_CFG24 0x00010ed8u
#define CYREG_B0_P7_U1_CFG25 0x00010ed9u
#define CYREG_B0_P7_U1_CFG26 0x00010edau
#define CYREG_B0_P7_U1_CFG27 0x00010edbu
#define CYREG_B0_P7_U1_CFG28 0x00010edcu
#define CYREG_B0_P7_U1_CFG29 0x00010eddu
#define CYREG_B0_P7_U1_CFG30 0x00010edeu
#define CYREG_B0_P7_U1_CFG31 0x00010edfu
#define CYREG_B0_P7_U1_DCFG0 0x00010ee0u
#define CYREG_B0_P7_U1_DCFG1 0x00010ee2u
#define CYREG_B0_P7_U1_DCFG2 0x00010ee4u
#define CYREG_B0_P7_U1_DCFG3 0x00010ee6u
#define CYREG_B0_P7_U1_DCFG4 0x00010ee8u
#define CYREG_B0_P7_U1_DCFG5 0x00010eeau
#define CYREG_B0_P7_U1_DCFG6 0x00010eecu
#define CYREG_B0_P7_U1_DCFG7 0x00010eeeu
#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x00010f00u
#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B1_BASE 0x00011000u
#define CYDEV_UCFG_B1_SIZE 0x00000fefu
#define CYDEV_UCFG_B1_P2_BASE 0x00011400u
#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu
#define CYDEV_UCFG_B1_P2_U0_BASE 0x00011400u
#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u
#define CYREG_B1_P2_U0_PLD_IT0 0x00011400u
#define CYREG_B1_P2_U0_PLD_IT1 0x00011404u
#define CYREG_B1_P2_U0_PLD_IT2 0x00011408u
#define CYREG_B1_P2_U0_PLD_IT3 0x0001140cu
#define CYREG_B1_P2_U0_PLD_IT4 0x00011410u
#define CYREG_B1_P2_U0_PLD_IT5 0x00011414u
#define CYREG_B1_P2_U0_PLD_IT6 0x00011418u
#define CYREG_B1_P2_U0_PLD_IT7 0x0001141cu
#define CYREG_B1_P2_U0_PLD_IT8 0x00011420u
#define CYREG_B1_P2_U0_PLD_IT9 0x00011424u
#define CYREG_B1_P2_U0_PLD_IT10 0x00011428u
#define CYREG_B1_P2_U0_PLD_IT11 0x0001142cu
#define CYREG_B1_P2_U0_PLD_ORT0 0x00011430u
#define CYREG_B1_P2_U0_PLD_ORT1 0x00011432u
#define CYREG_B1_P2_U0_PLD_ORT2 0x00011434u
#define CYREG_B1_P2_U0_PLD_ORT3 0x00011436u
#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x00011438u
#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x0001143au
#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x0001143cu
#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x0001143eu
#define CYREG_B1_P2_U0_CFG0 0x00011440u
#define CYREG_B1_P2_U0_CFG1 0x00011441u
#define CYREG_B1_P2_U0_CFG2 0x00011442u
#define CYREG_B1_P2_U0_CFG3 0x00011443u
#define CYREG_B1_P2_U0_CFG4 0x00011444u
#define CYREG_B1_P2_U0_CFG5 0x00011445u
#define CYREG_B1_P2_U0_CFG6 0x00011446u
#define CYREG_B1_P2_U0_CFG7 0x00011447u
#define CYREG_B1_P2_U0_CFG8 0x00011448u
#define CYREG_B1_P2_U0_CFG9 0x00011449u
#define CYREG_B1_P2_U0_CFG10 0x0001144au
#define CYREG_B1_P2_U0_CFG11 0x0001144bu
#define CYREG_B1_P2_U0_CFG12 0x0001144cu
#define CYREG_B1_P2_U0_CFG13 0x0001144du
#define CYREG_B1_P2_U0_CFG14 0x0001144eu
#define CYREG_B1_P2_U0_CFG15 0x0001144fu
#define CYREG_B1_P2_U0_CFG16 0x00011450u
#define CYREG_B1_P2_U0_CFG17 0x00011451u
#define CYREG_B1_P2_U0_CFG18 0x00011452u
#define CYREG_B1_P2_U0_CFG19 0x00011453u
#define CYREG_B1_P2_U0_CFG20 0x00011454u
#define CYREG_B1_P2_U0_CFG21 0x00011455u
#define CYREG_B1_P2_U0_CFG22 0x00011456u
#define CYREG_B1_P2_U0_CFG23 0x00011457u
#define CYREG_B1_P2_U0_CFG24 0x00011458u
#define CYREG_B1_P2_U0_CFG25 0x00011459u
#define CYREG_B1_P2_U0_CFG26 0x0001145au
#define CYREG_B1_P2_U0_CFG27 0x0001145bu
#define CYREG_B1_P2_U0_CFG28 0x0001145cu
#define CYREG_B1_P2_U0_CFG29 0x0001145du
#define CYREG_B1_P2_U0_CFG30 0x0001145eu
#define CYREG_B1_P2_U0_CFG31 0x0001145fu
#define CYREG_B1_P2_U0_DCFG0 0x00011460u
#define CYREG_B1_P2_U0_DCFG1 0x00011462u
#define CYREG_B1_P2_U0_DCFG2 0x00011464u
#define CYREG_B1_P2_U0_DCFG3 0x00011466u
#define CYREG_B1_P2_U0_DCFG4 0x00011468u
#define CYREG_B1_P2_U0_DCFG5 0x0001146au
#define CYREG_B1_P2_U0_DCFG6 0x0001146cu
#define CYREG_B1_P2_U0_DCFG7 0x0001146eu
#define CYDEV_UCFG_B1_P2_U1_BASE 0x00011480u
#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u
#define CYREG_B1_P2_U1_PLD_IT0 0x00011480u
#define CYREG_B1_P2_U1_PLD_IT1 0x00011484u
#define CYREG_B1_P2_U1_PLD_IT2 0x00011488u
#define CYREG_B1_P2_U1_PLD_IT3 0x0001148cu
#define CYREG_B1_P2_U1_PLD_IT4 0x00011490u
#define CYREG_B1_P2_U1_PLD_IT5 0x00011494u
#define CYREG_B1_P2_U1_PLD_IT6 0x00011498u
#define CYREG_B1_P2_U1_PLD_IT7 0x0001149cu
#define CYREG_B1_P2_U1_PLD_IT8 0x000114a0u
#define CYREG_B1_P2_U1_PLD_IT9 0x000114a4u
#define CYREG_B1_P2_U1_PLD_IT10 0x000114a8u
#define CYREG_B1_P2_U1_PLD_IT11 0x000114acu
#define CYREG_B1_P2_U1_PLD_ORT0 0x000114b0u
#define CYREG_B1_P2_U1_PLD_ORT1 0x000114b2u
#define CYREG_B1_P2_U1_PLD_ORT2 0x000114b4u
#define CYREG_B1_P2_U1_PLD_ORT3 0x000114b6u
#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x000114b8u
#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x000114bau
#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x000114bcu
#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x000114beu
#define CYREG_B1_P2_U1_CFG0 0x000114c0u
#define CYREG_B1_P2_U1_CFG1 0x000114c1u
#define CYREG_B1_P2_U1_CFG2 0x000114c2u
#define CYREG_B1_P2_U1_CFG3 0x000114c3u
#define CYREG_B1_P2_U1_CFG4 0x000114c4u
#define CYREG_B1_P2_U1_CFG5 0x000114c5u
#define CYREG_B1_P2_U1_CFG6 0x000114c6u
#define CYREG_B1_P2_U1_CFG7 0x000114c7u
#define CYREG_B1_P2_U1_CFG8 0x000114c8u
#define CYREG_B1_P2_U1_CFG9 0x000114c9u
#define CYREG_B1_P2_U1_CFG10 0x000114cau
#define CYREG_B1_P2_U1_CFG11 0x000114cbu
#define CYREG_B1_P2_U1_CFG12 0x000114ccu
#define CYREG_B1_P2_U1_CFG13 0x000114cdu
#define CYREG_B1_P2_U1_CFG14 0x000114ceu
#define CYREG_B1_P2_U1_CFG15 0x000114cfu
#define CYREG_B1_P2_U1_CFG16 0x000114d0u
#define CYREG_B1_P2_U1_CFG17 0x000114d1u
#define CYREG_B1_P2_U1_CFG18 0x000114d2u
#define CYREG_B1_P2_U1_CFG19 0x000114d3u
#define CYREG_B1_P2_U1_CFG20 0x000114d4u
#define CYREG_B1_P2_U1_CFG21 0x000114d5u
#define CYREG_B1_P2_U1_CFG22 0x000114d6u
#define CYREG_B1_P2_U1_CFG23 0x000114d7u
#define CYREG_B1_P2_U1_CFG24 0x000114d8u
#define CYREG_B1_P2_U1_CFG25 0x000114d9u
#define CYREG_B1_P2_U1_CFG26 0x000114dau
#define CYREG_B1_P2_U1_CFG27 0x000114dbu
#define CYREG_B1_P2_U1_CFG28 0x000114dcu
#define CYREG_B1_P2_U1_CFG29 0x000114ddu
#define CYREG_B1_P2_U1_CFG30 0x000114deu
#define CYREG_B1_P2_U1_CFG31 0x000114dfu
#define CYREG_B1_P2_U1_DCFG0 0x000114e0u
#define CYREG_B1_P2_U1_DCFG1 0x000114e2u
#define CYREG_B1_P2_U1_DCFG2 0x000114e4u
#define CYREG_B1_P2_U1_DCFG3 0x000114e6u
#define CYREG_B1_P2_U1_DCFG4 0x000114e8u
#define CYREG_B1_P2_U1_DCFG5 0x000114eau
#define CYREG_B1_P2_U1_DCFG6 0x000114ecu
#define CYREG_B1_P2_U1_DCFG7 0x000114eeu
#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x00011500u
#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B1_P3_BASE 0x00011600u
#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu
#define CYDEV_UCFG_B1_P3_U0_BASE 0x00011600u
#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u
#define CYREG_B1_P3_U0_PLD_IT0 0x00011600u
#define CYREG_B1_P3_U0_PLD_IT1 0x00011604u
#define CYREG_B1_P3_U0_PLD_IT2 0x00011608u
#define CYREG_B1_P3_U0_PLD_IT3 0x0001160cu
#define CYREG_B1_P3_U0_PLD_IT4 0x00011610u
#define CYREG_B1_P3_U0_PLD_IT5 0x00011614u
#define CYREG_B1_P3_U0_PLD_IT6 0x00011618u
#define CYREG_B1_P3_U0_PLD_IT7 0x0001161cu
#define CYREG_B1_P3_U0_PLD_IT8 0x00011620u
#define CYREG_B1_P3_U0_PLD_IT9 0x00011624u
#define CYREG_B1_P3_U0_PLD_IT10 0x00011628u
#define CYREG_B1_P3_U0_PLD_IT11 0x0001162cu
#define CYREG_B1_P3_U0_PLD_ORT0 0x00011630u
#define CYREG_B1_P3_U0_PLD_ORT1 0x00011632u
#define CYREG_B1_P3_U0_PLD_ORT2 0x00011634u
#define CYREG_B1_P3_U0_PLD_ORT3 0x00011636u
#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x00011638u
#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x0001163au
#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x0001163cu
#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x0001163eu
#define CYREG_B1_P3_U0_CFG0 0x00011640u
#define CYREG_B1_P3_U0_CFG1 0x00011641u
#define CYREG_B1_P3_U0_CFG2 0x00011642u
#define CYREG_B1_P3_U0_CFG3 0x00011643u
#define CYREG_B1_P3_U0_CFG4 0x00011644u
#define CYREG_B1_P3_U0_CFG5 0x00011645u
#define CYREG_B1_P3_U0_CFG6 0x00011646u
#define CYREG_B1_P3_U0_CFG7 0x00011647u
#define CYREG_B1_P3_U0_CFG8 0x00011648u
#define CYREG_B1_P3_U0_CFG9 0x00011649u
#define CYREG_B1_P3_U0_CFG10 0x0001164au
#define CYREG_B1_P3_U0_CFG11 0x0001164bu
#define CYREG_B1_P3_U0_CFG12 0x0001164cu
#define CYREG_B1_P3_U0_CFG13 0x0001164du
#define CYREG_B1_P3_U0_CFG14 0x0001164eu
#define CYREG_B1_P3_U0_CFG15 0x0001164fu
#define CYREG_B1_P3_U0_CFG16 0x00011650u
#define CYREG_B1_P3_U0_CFG17 0x00011651u
#define CYREG_B1_P3_U0_CFG18 0x00011652u
#define CYREG_B1_P3_U0_CFG19 0x00011653u
#define CYREG_B1_P3_U0_CFG20 0x00011654u
#define CYREG_B1_P3_U0_CFG21 0x00011655u
#define CYREG_B1_P3_U0_CFG22 0x00011656u
#define CYREG_B1_P3_U0_CFG23 0x00011657u
#define CYREG_B1_P3_U0_CFG24 0x00011658u
#define CYREG_B1_P3_U0_CFG25 0x00011659u
#define CYREG_B1_P3_U0_CFG26 0x0001165au
#define CYREG_B1_P3_U0_CFG27 0x0001165bu
#define CYREG_B1_P3_U0_CFG28 0x0001165cu
#define CYREG_B1_P3_U0_CFG29 0x0001165du
#define CYREG_B1_P3_U0_CFG30 0x0001165eu
#define CYREG_B1_P3_U0_CFG31 0x0001165fu
#define CYREG_B1_P3_U0_DCFG0 0x00011660u
#define CYREG_B1_P3_U0_DCFG1 0x00011662u
#define CYREG_B1_P3_U0_DCFG2 0x00011664u
#define CYREG_B1_P3_U0_DCFG3 0x00011666u
#define CYREG_B1_P3_U0_DCFG4 0x00011668u
#define CYREG_B1_P3_U0_DCFG5 0x0001166au
#define CYREG_B1_P3_U0_DCFG6 0x0001166cu
#define CYREG_B1_P3_U0_DCFG7 0x0001166eu
#define CYDEV_UCFG_B1_P3_U1_BASE 0x00011680u
#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u
#define CYREG_B1_P3_U1_PLD_IT0 0x00011680u
#define CYREG_B1_P3_U1_PLD_IT1 0x00011684u
#define CYREG_B1_P3_U1_PLD_IT2 0x00011688u
#define CYREG_B1_P3_U1_PLD_IT3 0x0001168cu
#define CYREG_B1_P3_U1_PLD_IT4 0x00011690u
#define CYREG_B1_P3_U1_PLD_IT5 0x00011694u
#define CYREG_B1_P3_U1_PLD_IT6 0x00011698u
#define CYREG_B1_P3_U1_PLD_IT7 0x0001169cu
#define CYREG_B1_P3_U1_PLD_IT8 0x000116a0u
#define CYREG_B1_P3_U1_PLD_IT9 0x000116a4u
#define CYREG_B1_P3_U1_PLD_IT10 0x000116a8u
#define CYREG_B1_P3_U1_PLD_IT11 0x000116acu
#define CYREG_B1_P3_U1_PLD_ORT0 0x000116b0u
#define CYREG_B1_P3_U1_PLD_ORT1 0x000116b2u
#define CYREG_B1_P3_U1_PLD_ORT2 0x000116b4u
#define CYREG_B1_P3_U1_PLD_ORT3 0x000116b6u
#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x000116b8u
#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x000116bau
#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x000116bcu
#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x000116beu
#define CYREG_B1_P3_U1_CFG0 0x000116c0u
#define CYREG_B1_P3_U1_CFG1 0x000116c1u
#define CYREG_B1_P3_U1_CFG2 0x000116c2u
#define CYREG_B1_P3_U1_CFG3 0x000116c3u
#define CYREG_B1_P3_U1_CFG4 0x000116c4u
#define CYREG_B1_P3_U1_CFG5 0x000116c5u
#define CYREG_B1_P3_U1_CFG6 0x000116c6u
#define CYREG_B1_P3_U1_CFG7 0x000116c7u
#define CYREG_B1_P3_U1_CFG8 0x000116c8u
#define CYREG_B1_P3_U1_CFG9 0x000116c9u
#define CYREG_B1_P3_U1_CFG10 0x000116cau
#define CYREG_B1_P3_U1_CFG11 0x000116cbu
#define CYREG_B1_P3_U1_CFG12 0x000116ccu
#define CYREG_B1_P3_U1_CFG13 0x000116cdu
#define CYREG_B1_P3_U1_CFG14 0x000116ceu
#define CYREG_B1_P3_U1_CFG15 0x000116cfu
#define CYREG_B1_P3_U1_CFG16 0x000116d0u
#define CYREG_B1_P3_U1_CFG17 0x000116d1u
#define CYREG_B1_P3_U1_CFG18 0x000116d2u
#define CYREG_B1_P3_U1_CFG19 0x000116d3u
#define CYREG_B1_P3_U1_CFG20 0x000116d4u
#define CYREG_B1_P3_U1_CFG21 0x000116d5u
#define CYREG_B1_P3_U1_CFG22 0x000116d6u
#define CYREG_B1_P3_U1_CFG23 0x000116d7u
#define CYREG_B1_P3_U1_CFG24 0x000116d8u
#define CYREG_B1_P3_U1_CFG25 0x000116d9u
#define CYREG_B1_P3_U1_CFG26 0x000116dau
#define CYREG_B1_P3_U1_CFG27 0x000116dbu
#define CYREG_B1_P3_U1_CFG28 0x000116dcu
#define CYREG_B1_P3_U1_CFG29 0x000116ddu
#define CYREG_B1_P3_U1_CFG30 0x000116deu
#define CYREG_B1_P3_U1_CFG31 0x000116dfu
#define CYREG_B1_P3_U1_DCFG0 0x000116e0u
#define CYREG_B1_P3_U1_DCFG1 0x000116e2u
#define CYREG_B1_P3_U1_DCFG2 0x000116e4u
#define CYREG_B1_P3_U1_DCFG3 0x000116e6u
#define CYREG_B1_P3_U1_DCFG4 0x000116e8u
#define CYREG_B1_P3_U1_DCFG5 0x000116eau
#define CYREG_B1_P3_U1_DCFG6 0x000116ecu
#define CYREG_B1_P3_U1_DCFG7 0x000116eeu
#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x00011700u
#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B1_P4_BASE 0x00011800u
#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu
#define CYDEV_UCFG_B1_P4_U0_BASE 0x00011800u
#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u
#define CYREG_B1_P4_U0_PLD_IT0 0x00011800u
#define CYREG_B1_P4_U0_PLD_IT1 0x00011804u
#define CYREG_B1_P4_U0_PLD_IT2 0x00011808u
#define CYREG_B1_P4_U0_PLD_IT3 0x0001180cu
#define CYREG_B1_P4_U0_PLD_IT4 0x00011810u
#define CYREG_B1_P4_U0_PLD_IT5 0x00011814u
#define CYREG_B1_P4_U0_PLD_IT6 0x00011818u
#define CYREG_B1_P4_U0_PLD_IT7 0x0001181cu
#define CYREG_B1_P4_U0_PLD_IT8 0x00011820u
#define CYREG_B1_P4_U0_PLD_IT9 0x00011824u
#define CYREG_B1_P4_U0_PLD_IT10 0x00011828u
#define CYREG_B1_P4_U0_PLD_IT11 0x0001182cu
#define CYREG_B1_P4_U0_PLD_ORT0 0x00011830u
#define CYREG_B1_P4_U0_PLD_ORT1 0x00011832u
#define CYREG_B1_P4_U0_PLD_ORT2 0x00011834u
#define CYREG_B1_P4_U0_PLD_ORT3 0x00011836u
#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x00011838u
#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x0001183au
#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x0001183cu
#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x0001183eu
#define CYREG_B1_P4_U0_CFG0 0x00011840u
#define CYREG_B1_P4_U0_CFG1 0x00011841u
#define CYREG_B1_P4_U0_CFG2 0x00011842u
#define CYREG_B1_P4_U0_CFG3 0x00011843u
#define CYREG_B1_P4_U0_CFG4 0x00011844u
#define CYREG_B1_P4_U0_CFG5 0x00011845u
#define CYREG_B1_P4_U0_CFG6 0x00011846u
#define CYREG_B1_P4_U0_CFG7 0x00011847u
#define CYREG_B1_P4_U0_CFG8 0x00011848u
#define CYREG_B1_P4_U0_CFG9 0x00011849u
#define CYREG_B1_P4_U0_CFG10 0x0001184au
#define CYREG_B1_P4_U0_CFG11 0x0001184bu
#define CYREG_B1_P4_U0_CFG12 0x0001184cu
#define CYREG_B1_P4_U0_CFG13 0x0001184du
#define CYREG_B1_P4_U0_CFG14 0x0001184eu
#define CYREG_B1_P4_U0_CFG15 0x0001184fu
#define CYREG_B1_P4_U0_CFG16 0x00011850u
#define CYREG_B1_P4_U0_CFG17 0x00011851u
#define CYREG_B1_P4_U0_CFG18 0x00011852u
#define CYREG_B1_P4_U0_CFG19 0x00011853u
#define CYREG_B1_P4_U0_CFG20 0x00011854u
#define CYREG_B1_P4_U0_CFG21 0x00011855u
#define CYREG_B1_P4_U0_CFG22 0x00011856u
#define CYREG_B1_P4_U0_CFG23 0x00011857u
#define CYREG_B1_P4_U0_CFG24 0x00011858u
#define CYREG_B1_P4_U0_CFG25 0x00011859u
#define CYREG_B1_P4_U0_CFG26 0x0001185au
#define CYREG_B1_P4_U0_CFG27 0x0001185bu
#define CYREG_B1_P4_U0_CFG28 0x0001185cu
#define CYREG_B1_P4_U0_CFG29 0x0001185du
#define CYREG_B1_P4_U0_CFG30 0x0001185eu
#define CYREG_B1_P4_U0_CFG31 0x0001185fu
#define CYREG_B1_P4_U0_DCFG0 0x00011860u
#define CYREG_B1_P4_U0_DCFG1 0x00011862u
#define CYREG_B1_P4_U0_DCFG2 0x00011864u
#define CYREG_B1_P4_U0_DCFG3 0x00011866u
#define CYREG_B1_P4_U0_DCFG4 0x00011868u
#define CYREG_B1_P4_U0_DCFG5 0x0001186au
#define CYREG_B1_P4_U0_DCFG6 0x0001186cu
#define CYREG_B1_P4_U0_DCFG7 0x0001186eu
#define CYDEV_UCFG_B1_P4_U1_BASE 0x00011880u
#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u
#define CYREG_B1_P4_U1_PLD_IT0 0x00011880u
#define CYREG_B1_P4_U1_PLD_IT1 0x00011884u
#define CYREG_B1_P4_U1_PLD_IT2 0x00011888u
#define CYREG_B1_P4_U1_PLD_IT3 0x0001188cu
#define CYREG_B1_P4_U1_PLD_IT4 0x00011890u
#define CYREG_B1_P4_U1_PLD_IT5 0x00011894u
#define CYREG_B1_P4_U1_PLD_IT6 0x00011898u
#define CYREG_B1_P4_U1_PLD_IT7 0x0001189cu
#define CYREG_B1_P4_U1_PLD_IT8 0x000118a0u
#define CYREG_B1_P4_U1_PLD_IT9 0x000118a4u
#define CYREG_B1_P4_U1_PLD_IT10 0x000118a8u
#define CYREG_B1_P4_U1_PLD_IT11 0x000118acu
#define CYREG_B1_P4_U1_PLD_ORT0 0x000118b0u
#define CYREG_B1_P4_U1_PLD_ORT1 0x000118b2u
#define CYREG_B1_P4_U1_PLD_ORT2 0x000118b4u
#define CYREG_B1_P4_U1_PLD_ORT3 0x000118b6u
#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x000118b8u
#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x000118bau
#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x000118bcu
#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x000118beu
#define CYREG_B1_P4_U1_CFG0 0x000118c0u
#define CYREG_B1_P4_U1_CFG1 0x000118c1u
#define CYREG_B1_P4_U1_CFG2 0x000118c2u
#define CYREG_B1_P4_U1_CFG3 0x000118c3u
#define CYREG_B1_P4_U1_CFG4 0x000118c4u
#define CYREG_B1_P4_U1_CFG5 0x000118c5u
#define CYREG_B1_P4_U1_CFG6 0x000118c6u
#define CYREG_B1_P4_U1_CFG7 0x000118c7u
#define CYREG_B1_P4_U1_CFG8 0x000118c8u
#define CYREG_B1_P4_U1_CFG9 0x000118c9u
#define CYREG_B1_P4_U1_CFG10 0x000118cau
#define CYREG_B1_P4_U1_CFG11 0x000118cbu
#define CYREG_B1_P4_U1_CFG12 0x000118ccu
#define CYREG_B1_P4_U1_CFG13 0x000118cdu
#define CYREG_B1_P4_U1_CFG14 0x000118ceu
#define CYREG_B1_P4_U1_CFG15 0x000118cfu
#define CYREG_B1_P4_U1_CFG16 0x000118d0u
#define CYREG_B1_P4_U1_CFG17 0x000118d1u
#define CYREG_B1_P4_U1_CFG18 0x000118d2u
#define CYREG_B1_P4_U1_CFG19 0x000118d3u
#define CYREG_B1_P4_U1_CFG20 0x000118d4u
#define CYREG_B1_P4_U1_CFG21 0x000118d5u
#define CYREG_B1_P4_U1_CFG22 0x000118d6u
#define CYREG_B1_P4_U1_CFG23 0x000118d7u
#define CYREG_B1_P4_U1_CFG24 0x000118d8u
#define CYREG_B1_P4_U1_CFG25 0x000118d9u
#define CYREG_B1_P4_U1_CFG26 0x000118dau
#define CYREG_B1_P4_U1_CFG27 0x000118dbu
#define CYREG_B1_P4_U1_CFG28 0x000118dcu
#define CYREG_B1_P4_U1_CFG29 0x000118ddu
#define CYREG_B1_P4_U1_CFG30 0x000118deu
#define CYREG_B1_P4_U1_CFG31 0x000118dfu
#define CYREG_B1_P4_U1_DCFG0 0x000118e0u
#define CYREG_B1_P4_U1_DCFG1 0x000118e2u
#define CYREG_B1_P4_U1_DCFG2 0x000118e4u
#define CYREG_B1_P4_U1_DCFG3 0x000118e6u
#define CYREG_B1_P4_U1_DCFG4 0x000118e8u
#define CYREG_B1_P4_U1_DCFG5 0x000118eau
#define CYREG_B1_P4_U1_DCFG6 0x000118ecu
#define CYREG_B1_P4_U1_DCFG7 0x000118eeu
#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x00011900u
#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_B1_P5_BASE 0x00011a00u
#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu
#define CYDEV_UCFG_B1_P5_U0_BASE 0x00011a00u
#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u
#define CYREG_B1_P5_U0_PLD_IT0 0x00011a00u
#define CYREG_B1_P5_U0_PLD_IT1 0x00011a04u
#define CYREG_B1_P5_U0_PLD_IT2 0x00011a08u
#define CYREG_B1_P5_U0_PLD_IT3 0x00011a0cu
#define CYREG_B1_P5_U0_PLD_IT4 0x00011a10u
#define CYREG_B1_P5_U0_PLD_IT5 0x00011a14u
#define CYREG_B1_P5_U0_PLD_IT6 0x00011a18u
#define CYREG_B1_P5_U0_PLD_IT7 0x00011a1cu
#define CYREG_B1_P5_U0_PLD_IT8 0x00011a20u
#define CYREG_B1_P5_U0_PLD_IT9 0x00011a24u
#define CYREG_B1_P5_U0_PLD_IT10 0x00011a28u
#define CYREG_B1_P5_U0_PLD_IT11 0x00011a2cu
#define CYREG_B1_P5_U0_PLD_ORT0 0x00011a30u
#define CYREG_B1_P5_U0_PLD_ORT1 0x00011a32u
#define CYREG_B1_P5_U0_PLD_ORT2 0x00011a34u
#define CYREG_B1_P5_U0_PLD_ORT3 0x00011a36u
#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x00011a38u
#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x00011a3au
#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x00011a3cu
#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x00011a3eu
#define CYREG_B1_P5_U0_CFG0 0x00011a40u
#define CYREG_B1_P5_U0_CFG1 0x00011a41u
#define CYREG_B1_P5_U0_CFG2 0x00011a42u
#define CYREG_B1_P5_U0_CFG3 0x00011a43u
#define CYREG_B1_P5_U0_CFG4 0x00011a44u
#define CYREG_B1_P5_U0_CFG5 0x00011a45u
#define CYREG_B1_P5_U0_CFG6 0x00011a46u
#define CYREG_B1_P5_U0_CFG7 0x00011a47u
#define CYREG_B1_P5_U0_CFG8 0x00011a48u
#define CYREG_B1_P5_U0_CFG9 0x00011a49u
#define CYREG_B1_P5_U0_CFG10 0x00011a4au
#define CYREG_B1_P5_U0_CFG11 0x00011a4bu
#define CYREG_B1_P5_U0_CFG12 0x00011a4cu
#define CYREG_B1_P5_U0_CFG13 0x00011a4du
#define CYREG_B1_P5_U0_CFG14 0x00011a4eu
#define CYREG_B1_P5_U0_CFG15 0x00011a4fu
#define CYREG_B1_P5_U0_CFG16 0x00011a50u
#define CYREG_B1_P5_U0_CFG17 0x00011a51u
#define CYREG_B1_P5_U0_CFG18 0x00011a52u
#define CYREG_B1_P5_U0_CFG19 0x00011a53u
#define CYREG_B1_P5_U0_CFG20 0x00011a54u
#define CYREG_B1_P5_U0_CFG21 0x00011a55u
#define CYREG_B1_P5_U0_CFG22 0x00011a56u
#define CYREG_B1_P5_U0_CFG23 0x00011a57u
#define CYREG_B1_P5_U0_CFG24 0x00011a58u
#define CYREG_B1_P5_U0_CFG25 0x00011a59u
#define CYREG_B1_P5_U0_CFG26 0x00011a5au
#define CYREG_B1_P5_U0_CFG27 0x00011a5bu
#define CYREG_B1_P5_U0_CFG28 0x00011a5cu
#define CYREG_B1_P5_U0_CFG29 0x00011a5du
#define CYREG_B1_P5_U0_CFG30 0x00011a5eu
#define CYREG_B1_P5_U0_CFG31 0x00011a5fu
#define CYREG_B1_P5_U0_DCFG0 0x00011a60u
#define CYREG_B1_P5_U0_DCFG1 0x00011a62u
#define CYREG_B1_P5_U0_DCFG2 0x00011a64u
#define CYREG_B1_P5_U0_DCFG3 0x00011a66u
#define CYREG_B1_P5_U0_DCFG4 0x00011a68u
#define CYREG_B1_P5_U0_DCFG5 0x00011a6au
#define CYREG_B1_P5_U0_DCFG6 0x00011a6cu
#define CYREG_B1_P5_U0_DCFG7 0x00011a6eu
#define CYDEV_UCFG_B1_P5_U1_BASE 0x00011a80u
#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u
#define CYREG_B1_P5_U1_PLD_IT0 0x00011a80u
#define CYREG_B1_P5_U1_PLD_IT1 0x00011a84u
#define CYREG_B1_P5_U1_PLD_IT2 0x00011a88u
#define CYREG_B1_P5_U1_PLD_IT3 0x00011a8cu
#define CYREG_B1_P5_U1_PLD_IT4 0x00011a90u
#define CYREG_B1_P5_U1_PLD_IT5 0x00011a94u
#define CYREG_B1_P5_U1_PLD_IT6 0x00011a98u
#define CYREG_B1_P5_U1_PLD_IT7 0x00011a9cu
#define CYREG_B1_P5_U1_PLD_IT8 0x00011aa0u
#define CYREG_B1_P5_U1_PLD_IT9 0x00011aa4u
#define CYREG_B1_P5_U1_PLD_IT10 0x00011aa8u
#define CYREG_B1_P5_U1_PLD_IT11 0x00011aacu
#define CYREG_B1_P5_U1_PLD_ORT0 0x00011ab0u
#define CYREG_B1_P5_U1_PLD_ORT1 0x00011ab2u
#define CYREG_B1_P5_U1_PLD_ORT2 0x00011ab4u
#define CYREG_B1_P5_U1_PLD_ORT3 0x00011ab6u
#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x00011ab8u
#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x00011abau
#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x00011abcu
#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x00011abeu
#define CYREG_B1_P5_U1_CFG0 0x00011ac0u
#define CYREG_B1_P5_U1_CFG1 0x00011ac1u
#define CYREG_B1_P5_U1_CFG2 0x00011ac2u
#define CYREG_B1_P5_U1_CFG3 0x00011ac3u
#define CYREG_B1_P5_U1_CFG4 0x00011ac4u
#define CYREG_B1_P5_U1_CFG5 0x00011ac5u
#define CYREG_B1_P5_U1_CFG6 0x00011ac6u
#define CYREG_B1_P5_U1_CFG7 0x00011ac7u
#define CYREG_B1_P5_U1_CFG8 0x00011ac8u
#define CYREG_B1_P5_U1_CFG9 0x00011ac9u
#define CYREG_B1_P5_U1_CFG10 0x00011acau
#define CYREG_B1_P5_U1_CFG11 0x00011acbu
#define CYREG_B1_P5_U1_CFG12 0x00011accu
#define CYREG_B1_P5_U1_CFG13 0x00011acdu
#define CYREG_B1_P5_U1_CFG14 0x00011aceu
#define CYREG_B1_P5_U1_CFG15 0x00011acfu
#define CYREG_B1_P5_U1_CFG16 0x00011ad0u
#define CYREG_B1_P5_U1_CFG17 0x00011ad1u
#define CYREG_B1_P5_U1_CFG18 0x00011ad2u
#define CYREG_B1_P5_U1_CFG19 0x00011ad3u
#define CYREG_B1_P5_U1_CFG20 0x00011ad4u
#define CYREG_B1_P5_U1_CFG21 0x00011ad5u
#define CYREG_B1_P5_U1_CFG22 0x00011ad6u
#define CYREG_B1_P5_U1_CFG23 0x00011ad7u
#define CYREG_B1_P5_U1_CFG24 0x00011ad8u
#define CYREG_B1_P5_U1_CFG25 0x00011ad9u
#define CYREG_B1_P5_U1_CFG26 0x00011adau
#define CYREG_B1_P5_U1_CFG27 0x00011adbu
#define CYREG_B1_P5_U1_CFG28 0x00011adcu
#define CYREG_B1_P5_U1_CFG29 0x00011addu
#define CYREG_B1_P5_U1_CFG30 0x00011adeu
#define CYREG_B1_P5_U1_CFG31 0x00011adfu
#define CYREG_B1_P5_U1_DCFG0 0x00011ae0u
#define CYREG_B1_P5_U1_DCFG1 0x00011ae2u
#define CYREG_B1_P5_U1_DCFG2 0x00011ae4u
#define CYREG_B1_P5_U1_DCFG3 0x00011ae6u
#define CYREG_B1_P5_U1_DCFG4 0x00011ae8u
#define CYREG_B1_P5_U1_DCFG5 0x00011aeau
#define CYREG_B1_P5_U1_DCFG6 0x00011aecu
#define CYREG_B1_P5_U1_DCFG7 0x00011aeeu
#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x00011b00u
#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu
#define CYDEV_UCFG_DSI0_BASE 0x00014000u
#define CYDEV_UCFG_DSI0_SIZE 0x000000efu
#define CYDEV_UCFG_DSI1_BASE 0x00014100u
#define CYDEV_UCFG_DSI1_SIZE 0x000000efu
#define CYDEV_UCFG_DSI2_BASE 0x00014200u
#define CYDEV_UCFG_DSI2_SIZE 0x000000efu
#define CYDEV_UCFG_DSI3_BASE 0x00014300u
#define CYDEV_UCFG_DSI3_SIZE 0x000000efu
#define CYDEV_UCFG_DSI4_BASE 0x00014400u
#define CYDEV_UCFG_DSI4_SIZE 0x000000efu
#define CYDEV_UCFG_DSI5_BASE 0x00014500u
#define CYDEV_UCFG_DSI5_SIZE 0x000000efu
#define CYDEV_UCFG_DSI6_BASE 0x00014600u
#define CYDEV_UCFG_DSI6_SIZE 0x000000efu
#define CYDEV_UCFG_DSI7_BASE 0x00014700u
#define CYDEV_UCFG_DSI7_SIZE 0x000000efu
#define CYDEV_UCFG_DSI8_BASE 0x00014800u
#define CYDEV_UCFG_DSI8_SIZE 0x000000efu
#define CYDEV_UCFG_DSI9_BASE 0x00014900u
#define CYDEV_UCFG_DSI9_SIZE 0x000000efu
#define CYDEV_UCFG_DSI12_BASE 0x00014c00u
#define CYDEV_UCFG_DSI12_SIZE 0x000000efu
#define CYDEV_UCFG_DSI13_BASE 0x00014d00u
#define CYDEV_UCFG_DSI13_SIZE 0x000000efu
#define CYDEV_UCFG_BCTL0_BASE 0x00015000u
#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u
#define CYREG_BCTL0_MDCLK_EN 0x00015000u
#define CYREG_BCTL0_MBCLK_EN 0x00015001u
#define CYREG_BCTL0_WAIT_CFG 0x00015002u
#define CYREG_BCTL0_BANK_CTL 0x00015003u
#define CYREG_BCTL0_UDB_TEST_3 0x00015007u
#define CYREG_BCTL0_DCLK_EN0 0x00015008u
#define CYREG_BCTL0_BCLK_EN0 0x00015009u
#define CYREG_BCTL0_DCLK_EN1 0x0001500au
#define CYREG_BCTL0_BCLK_EN1 0x0001500bu
#define CYREG_BCTL0_DCLK_EN2 0x0001500cu
#define CYREG_BCTL0_BCLK_EN2 0x0001500du
#define CYREG_BCTL0_DCLK_EN3 0x0001500eu
#define CYREG_BCTL0_BCLK_EN3 0x0001500fu
#define CYDEV_UCFG_BCTL1_BASE 0x00015010u
#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u
#define CYREG_BCTL1_MDCLK_EN 0x00015010u
#define CYREG_BCTL1_MBCLK_EN 0x00015011u
#define CYREG_BCTL1_WAIT_CFG 0x00015012u
#define CYREG_BCTL1_BANK_CTL 0x00015013u
#define CYREG_BCTL1_UDB_TEST_3 0x00015017u
#define CYREG_BCTL1_DCLK_EN0 0x00015018u
#define CYREG_BCTL1_BCLK_EN0 0x00015019u
#define CYREG_BCTL1_DCLK_EN1 0x0001501au
#define CYREG_BCTL1_BCLK_EN1 0x0001501bu
#define CYREG_BCTL1_DCLK_EN2 0x0001501cu
#define CYREG_BCTL1_BCLK_EN2 0x0001501du
#define CYREG_BCTL1_DCLK_EN3 0x0001501eu
#define CYREG_BCTL1_BCLK_EN3 0x0001501fu
#define CYDEV_IDMUX_BASE 0x00015100u
#define CYDEV_IDMUX_SIZE 0x00000016u
#define CYREG_IDMUX_IRQ_CTL0 0x00015100u
#define CYREG_IDMUX_IRQ_CTL1 0x00015101u
#define CYREG_IDMUX_IRQ_CTL2 0x00015102u
#define CYREG_IDMUX_IRQ_CTL3 0x00015103u
#define CYREG_IDMUX_IRQ_CTL4 0x00015104u
#define CYREG_IDMUX_IRQ_CTL5 0x00015105u
#define CYREG_IDMUX_IRQ_CTL6 0x00015106u
#define CYREG_IDMUX_IRQ_CTL7 0x00015107u
#define CYREG_IDMUX_DRQ_CTL0 0x00015110u
#define CYREG_IDMUX_DRQ_CTL1 0x00015111u
#define CYREG_IDMUX_DRQ_CTL2 0x00015112u
#define CYREG_IDMUX_DRQ_CTL3 0x00015113u
#define CYREG_IDMUX_DRQ_CTL4 0x00015114u
#define CYREG_IDMUX_DRQ_CTL5 0x00015115u
#define CYDEV_IRAM_BASE 0x00050000u
#define CYDEV_IRAM_SIZE 0x00000100u
#define CYDEV_IRAM_IRAM_L_BASE 0x00050000u
#define CYDEV_IRAM_IRAM_L_SIZE 0x00000080u
#define CYREG_IRAM_IRAM_L_DATA_RAM_L_MBASE 0x00050000u
#define CYREG_IRAM_IRAM_L_DATA_RAM_L_MSIZE 0x00000080u
#define CYDEV_IRAM_IRAM_H_BASE 0x00050080u
#define CYDEV_IRAM_IRAM_H_SIZE 0x00000080u
#define CYREG_IRAM_IRAM_H_DATA_RAM_H_MBASE 0x00050080u
#define CYREG_IRAM_IRAM_H_DATA_RAM_H_MSIZE 0x00000080u
#define CYDEV_ECC_BASE 0x00080000u
#define CYDEV_ECC_SIZE 0x00002000u
#define CYREG_ECC_DATA_MBASE 0x00080000u
#define CYREG_ECC_DATA_MSIZE 0x00002000u
#define CYDEV_FLSHID_BASE 0x000c0000u
#define CYDEV_FLSHID_SIZE 0x00000200u
#define CYREG_FLSHID_RSVD_MBASE 0x000c0000u
#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u
#define CYREG_FLSHID_CUST_MDATA_MBASE 0x000c0080u
#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u
#define CYDEV_FLSHID_CUST_TABLES_BASE 0x000c0100u
#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u
#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x000c0100u
#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x000c0101u
#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x000c0102u
#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x000c0103u
#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x000c0104u
#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x000c0105u
#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x000c0106u
#define CYREG_FLSHID_CUST_TABLES_MINOR 0x000c0107u
#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x000c0108u
#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x000c0109u
#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x000c010au
#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x000c010bu
#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x000c010cu
#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x000c010du
#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x000c010eu
#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x000c010fu
#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x000c0110u
#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x000c0111u
#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x000c0112u
#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x000c0113u
#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x000c0114u
#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x000c0115u
#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x000c0116u
#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x000c0117u
#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x000c0118u
#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x000c0119u
#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x000c011au
#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x000c011bu
#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x000c011cu
#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x000c011du
#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x000c011eu
#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x000c011fu
#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x000c0120u
#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x000c0121u
#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x000c0122u
#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x000c0123u
#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x000c0124u
#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x000c0125u
#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x000c0126u
#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x000c0127u
#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x000c0128u
#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x000c0129u
#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x000c012au
#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x000c012bu
#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x000c012cu
#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x000c012du
#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x000c012eu
#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x000c012fu
#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x000c0130u
#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x000c0131u
#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x000c0132u
#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x000c0133u
#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x000c0134u
#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x000c0135u
#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x000c0136u
#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x000c0137u
#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x000c0138u
#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x000c0139u
#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x000c013au
#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x000c013bu
#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x000c013cu
#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x000c013du
#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x000c013eu
#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x000c013fu
#define CYDEV_FLSHID_MFG_CFG_BASE 0x000c0180u
#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u
#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x000c0188u
#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x000c01acu
#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x000c01aeu
#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x000c01b0u
#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x000c01b2u
#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x000c01b4u
#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x000c01b6u
#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x000c01b8u
#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x000c01bau
#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x000c01ceu
#define CYDEV_FLS_BASE 0x00100000u
#define CYDEV_FLS_SIZE 0x00010000u
#define CYREG_FLS_DATA_MBASE 0x00100000u
#define CYREG_FLS_DATA_MSIZE 0x00010000u
#define CYDEV_EXTMEM_BASE 0x00800000u
#define CYDEV_EXTMEM_SIZE 0x00800000u
#define CYREG_EXTMEM_DATA_MBASE 0x00800000u
#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u
#define CYDEV_FLS_SECTOR_SIZE 0x00010000u
#define CYDEV_FLS_ROW_SIZE 0x00000100u
#define CYDEV_ECC_SECTOR_SIZE 0x00002000u
#define CYDEV_ECC_ROW_SIZE 0x00000020u
#define CYDEV_EEPROM_ROW_SIZE 0x00000010u
#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE
#define CYCLK_LD_DISABLE 0x00000004u
#define CYCLK_LD_SYNC_EN 0x00000002u
#define CYCLK_LD_LOAD 0x00000001u
#define CYCLK_PIPE 0x00000080u
#define CYCLK_SSS 0x00000040u
#define CYCLK_EARLY 0x00000020u
#define CYCLK_DUTY 0x00000010u
#define CYCLK_SYNC 0x00000008u
#define CYCLK_SRC_SEL_CLK_SYNC_D 0
#define CYCLK_SRC_SEL_SYNC_DIG 0
#define CYCLK_SRC_SEL_IMO 1
#define CYCLK_SRC_SEL_XTAL_MHZ 2
#define CYCLK_SRC_SEL_XTALM 2
#define CYCLK_SRC_SEL_ILO 3
#define CYCLK_SRC_SEL_PLL 4
#define CYCLK_SRC_SEL_XTAL_KHZ 5
#define CYCLK_SRC_SEL_XTALK 5
#define CYCLK_SRC_SEL_DSI_G 6
#define CYCLK_SRC_SEL_DSI_D 7
#define CYCLK_SRC_SEL_CLK_SYNC_A 0
#define CYCLK_SRC_SEL_DSI_A 7
#endif /* CYDEVICE_TRM_H */
