Static Timing Analysis

Project : PWM_Out_LED
Build Time : 04/12/12 23:08:19
Device : CY8C3866LTI-030
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
ClockBlock/dclk_0 Async 10.000 kHz 10.000 kHz N/A
Clock_1 Sync 10.000 kHz 10.000 kHz 56.641 MHz
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.641 MHz 17.655 99982.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.285
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.348 MHz 15.072 99984.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.302
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_4/main_1 87.108 MHz 11.480 99988.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM:PWMUDB:compare1\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_4/main_1 2.290
macrocell1 U(0,3) 1 Net_4 SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 87.108 MHz 11.480 99988.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM:PWMUDB:compare1\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 2.290
macrocell3 U(0,3) 1 \PWM:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_0 87.108 MHz 11.480 99988.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM:PWMUDB:compare1\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_0 2.290
macrocell6 U(0,3) 1 \PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:final_kill_reg\/q \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 92.911 MHz 10.763 99989.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \PWM:PWMUDB:final_kill_reg\ \PWM:PWMUDB:final_kill_reg\/clock_0 \PWM:PWMUDB:final_kill_reg\/q 1.250
Route 1 \PWM:PWMUDB:final_kill_reg\ \PWM:PWMUDB:final_kill_reg\/q \PWM:PWMUDB:status_5\/main_0 2.289
macrocell8 U(0,3) 1 \PWM:PWMUDB:status_5\ \PWM:PWMUDB:status_5\/main_0 \PWM:PWMUDB:status_5\/q 3.350
Route 1 \PWM:PWMUDB:status_5\ \PWM:PWMUDB:status_5\/q \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 2.304
statusicell1 U(0,3) 1 \PWM:PWMUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_4/main_0 118.680 MHz 8.426 99991.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \PWM:PWMUDB:ctrl_enable\ \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_4/main_0 2.336
macrocell1 U(0,3) 1 Net_4 SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 118.680 MHz 8.426 99991.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \PWM:PWMUDB:ctrl_enable\ \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.336
macrocell5 U(0,3) 1 \PWM:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 129.634 MHz 7.714 99992.286
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
Route 1 \PWM:PWMUDB:tc_i\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 2.294
statusicell1 U(0,3) 1 \PWM:PWMUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM:PWMUDB:prevCompare2\/q \PWM:PWMUDB:status_1\/main_1 141.643 MHz 7.060 99992.940
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,3) 1 \PWM:PWMUDB:prevCompare2\ \PWM:PWMUDB:prevCompare2\/clock_0 \PWM:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare2\ \PWM:PWMUDB:prevCompare2\/q \PWM:PWMUDB:status_1\/main_1 2.300
macrocell7 U(0,3) 1 \PWM:PWMUDB:status_1\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM:PWMUDB:status_0\/q \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 1.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,3) 1 \PWM:PWMUDB:status_0\ \PWM:PWMUDB:status_0\/clock_0 \PWM:PWMUDB:status_0\/q 1.250
Route 1 \PWM:PWMUDB:status_0\ \PWM:PWMUDB:status_0\/q \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 2.323
statusicell1 U(0,3) 1 \PWM:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM:PWMUDB:status_1\/q \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_1 1.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,3) 1 \PWM:PWMUDB:status_1\ \PWM:PWMUDB:status_1\/clock_0 \PWM:PWMUDB:status_1\/q 1.250
Route 1 \PWM:PWMUDB:status_1\ \PWM:PWMUDB:status_1\/q \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_1 2.323
statusicell1 U(0,3) 1 \PWM:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_1 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/clock_0 \PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_1 2.295
macrocell6 U(0,3) 1 \PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:prevCompare2\/q \PWM:PWMUDB:status_1\/main_1 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,3) 1 \PWM:PWMUDB:prevCompare2\ \PWM:PWMUDB:prevCompare2\/clock_0 \PWM:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare2\ \PWM:PWMUDB:prevCompare2\/q \PWM:PWMUDB:status_1\/main_1 2.300
macrocell7 U(0,3) 1 \PWM:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.302
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 3.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.270
Route 1 \PWM:PWMUDB:tc_i\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 2.294
statusicell1 U(0,3) 1 \PWM:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_4/main_0 4.376
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM:PWMUDB:ctrl_enable\ \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_4/main_0 2.336
macrocell1 U(0,3) 1 Net_4 HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 4.376
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \PWM:PWMUDB:ctrl_enable\ \PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.336
macrocell5 U(0,3) 1 \PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_4/main_1 5.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM:PWMUDB:compare1\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_4/main_1 2.290
macrocell1 U(0,3) 1 Net_4 HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 5.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM:PWMUDB:compare1\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 2.290
macrocell3 U(0,3) 1 \PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_4/q Pin_LED(0)_PAD 23.800
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,3) 1 Net_4 Net_4/clock_0 Net_4/q 1.250
Route 1 Net_4 Net_4/q Pin_LED(0)/pin_input 6.350
iocell P2[7] 1 Pin_LED(0) Pin_LED(0)/pin_input Pin_LED(0)/pad_out 16.200
Route 1 Pin_LED(0)_PAD Pin_LED(0)/pad_out Pin_LED(0)_PAD 0.000
Clock Clock path delay 0.000