# Static Timing Analysis

Project : | USBUART
Build Time : | 04/13/12 06:26:14
Device : | CY8C3866LTI-030
Temperature : | -40C - 85C
Vio0 : | 5.0
Vio1 : | 5.0
Vio2 : | 5.0
Vio3 : | 5.0
Voltage : | 5.0

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Type | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
ADC_DelSig_1_Ext_CP_Clk | Sync | 1.000 MHz | 1.000 MHz | N/A |
ADC_DelSig_1_theACLK | Sync | 160.000 kHz | 160.000 kHz | N/A |
ClockBlock/aclk_0 | Async | 160.000 kHz | 160.000 kHz | N/A |
ClockBlock/clk_bus | Async | 48.000 MHz | 48.000 MHz | N/A |
ClockBlock/dclk_0 | Async | 1.000 MHz | 1.000 MHz | N/A |
CyBUS_CLK | Sync | 48.000 MHz | 48.000 MHz | N/A |
CyILO | Async | 100.000 kHz | 100.000 kHz | N/A |
CyIMO | Async | 24.000 MHz | 24.000 MHz | N/A |
CyMASTER_CLK | Sync | 48.000 MHz | 48.000 MHz | N/A |
CyPLL_OUT | Async | 48.000 MHz | 48.000 MHz | N/A |