ARTICLES The River Runs Deep [The first part] The PCI Bus As one example, the VESA Local Bus easily could have presented Intel serious problems for future processor designs because it directly attached to the 80486 processor local bus ? the bus between main memory and the processor. If Intel had lost control to an outside organization for their processor local bus architecture design, it would have little flexibility to produce new processor designs. To address the need for a higher performance bus and to retain control of critical processor considerations, Intel announced the PCI bus in 1992. Subsequent to its release and to accelerate PCI bus adoption, Intel turned over the PCI standardization process to the PCI Special Interest Group (PCI-SIG), an industry standards group (see http://www.pcisig.com/). This first PCI bus specification was for a 32-bit 33 MHz bus. The specification allowed the bus to burst 133 Mbytes a second. Actual sustained throughput was noticeably slower because of bus arbitration and other inefficiencies. Unfortunately, the specification was interpreted in different ways by different manufacturers and interoperability problems continued until the PCI 2.1 specification replaced the PCI 2.0 that added parity to the original PCI 1.0 specification. The first reliable PCI bus had arrived and swept the competing buses away. To ARTICLE Top page <<Former / Next>> To DESIGN WAVE MAGAZINE's Homepage (English) To CQ Publishing's Homepage (Japanese) Copyright(C) 1996-2002 CQ Publishing Co., Ltd.