# Generation Report - DDR SDRAM High Performance Controller v8.1
Entity Name | ddr_sdram_controller_phy
Variation Name | ddr_sdram
Variation HDL | Verilog HDL
Output Directory | C:\hhagiwar\cqweb\graphics_equalizer
## File Summary The MegaWizard interface is creating the following files in the output directory:
File | Description
--- | ---
ddr_sdram.v | A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
ddr_sdram.qip | Contains Quartus II project information for your MegaCore function variation.
ddr_sdram.html | The MegaCore function report file.
testbench | ddr_sdram_example_top_tb.v |
testbench | ddr_sdram_mem_model.v |
## MegaCore Function Variation File Ports
Name | Direction | Width
--- | --- | ---
local_address | INPUT | 22
local_write_req | INPUT | 1
local_read_req | INPUT | 1
local_burstbegin | INPUT | 1
local_ready | OUTPUT | 1
local_rdata | OUTPUT | 64
local_rdata_valid | OUTPUT | 1
local_wdata | INPUT | 64
local_be | INPUT | 8
local_size | INPUT | 1
reset_request_n | OUTPUT | 1
mem_clk | BIDIR | 1
mem_clk_n | BIDIR | 1
mem_cs_n | OUTPUT | 1
mem_cke | OUTPUT | 1
mem_addr | OUTPUT | 13
mem_ba | OUTPUT | 2
mem_ras_n | OUTPUT | 1
mem_cas_n | OUTPUT | 1
mem_we_n | OUTPUT | 1
mem_dq | BIDIR | 16
mem_dqs | BIDIR | 2
mem_dm | OUTPUT | 2
local_refresh_ack | OUTPUT | 1
local_wdata_req | OUTPUT | 1
local_init_done | OUTPUT | 1
reset_phy_clk_n | OUTPUT | 1
global_reset_n | INPUT | 1
pll_ref_clk | INPUT | 1
phy_clk | OUTPUT | 1
aux_full_rate_clk | OUTPUT | 1
aux_half_rate_clk | OUTPUT | 1
soft_reset_n | INPUT | 1