                                                               +-------------+
                                                               | IO91310-01E |
                                                               +-------------+























                           SAMPLE I/O REGISTER FILES
                       FOR FR/FRex FAMILY MB91310 SERIES

                                 USERS MANUAL

                                FUJITSU LIMITED

                                 VERSION 1.0

Preface

  The sample I/O register files for MB91310 series declares and defines
  variables, thereby enabling the I/O registers of the MB91310 series to be
  handled as C variables.
  This manual describes the configuration of the I/O register files, variable
  declaration and definition.




Items to note before using I/O register files

  - The I/O register files are intended for specific series of MB91310 series.
    Before applying these programs to any other series of MB91310 series,
    therefore, be sure to modify the I/O register files.

  - When a program for I/O register operation is coded, the I/O register
    access sequence and timing must be considered. Please refer to the
    related hardware manuals.

  - The I/O register files are provided as valuable aids in developing the
    application programs for MB91310 series. In practice, however, some of
    these programs may need be modified depending on the target system.
    Before using any of them, therefore, be sure to verify the actual
    operation of the program.

  - Fujitsu may assume no liability for errors in the I/O register files
    and no responsibility for correcting errors immediately even if they
    are found.




Reference manuals

  I/O register files for MB91310 series are made based on the
  following manuals.

    -  MB91310 LSI manual Prototype Version 1.2 2002.10.07
       (MB91V310lsi_rev1_2.pdf)

Contents

CHAPTER 1  CONFIGURATION OF I/O REGISTER FILES FOR MB91310 series

CHAPTER 2  USAGE OF I/O REGISTER FILES FOR MB91310 series

CHAPTER 3  DECLARATION OF I/O REGISTER DECLARATION FILES FOR MB91310 series

CHAPTER 4  VARIABLE AND MEMBER NAMES USED IN I/O REGISTER DECLARATION FILES
           FOR MB91310 series

CHAPTER 1  CONFIGURATION OF SAMPLE I/O REGISTER FILES FOR MB91310 series

 ${FETOOL}         (Directory set in environment variable FETOOL)
  +-lib
    +-911
      +-include
        +-sample
          +-mb91310
            +-_fr.h (I/O register declaration file)
            |
            +-_mb91310.h (I/O register declaration file for MB91310 series)
            +-_r91310.h  (I/O register structure declaration file
            |                                           for MB91310 series)
            |
            +-*.c   (I/O register definition file)


  - I/O register declaration file

    This file declares all the associated I/O register variables (variables
    corresponding to I/O registers). 
    Please include this file when coding a program that handles associated
    I/O registers.

  - I/O register declaration file for MB91310 series

    This file declares all the associated I/O register variables
    for MB91310 series.

  - I/O register structure declaration file for MB91310 series

    This file declares all the structure types corresponding to I/O registers
    for MB91310 series.

  - I/O register definition file for each I/O register

    This file defines each the associated I/O register variable and specifies
    arrangement address.

CHAPTER 2  USAGE OF I/O REGISTER FILES FOR MB91310 series

  (1) Please compile the all I/O register definition files with the CPU option
      of using MB number, and make the relocatable load module by linker.

        example:  > fcc911s  -cpu mb91*** -c *.c
                  > flnk911s -cpu mb91*** -r -o io91***.rel *.obj

  (2) When you describe the application program which refers to the I/O
      registers, please include the I/O register declaration file.

        example:  #include "_fr.h"

                  void func(){
                         .....
                    IO_TCCS.bit.MODE = 1;
                         .....
                  }

  (3) Please compile the application program file with the CPU option of
      using MB number.

        example:  > fcc911s -cpu mb91*** -c sample.c

        Note: When the MB number of the specified CPU option cannot be used
              for the I/O register file, the following messages are output.

                #error "The I/O register file of the specified CPU option
                        does not exist"

  (4) Please link the relocatable load module and the application program
      object file.

        example:  > flnk911s -cpu mb91*** -o sample.abs io91***.rel sample.obj

CHAPTER 3  DECLARATION OF I/O REGISTER DECLARATION FILES FOR MB91310 series

  Each I/O register declaration file declares the variables and the bit field
  members corresponding to I/O register names and bit names as follows:

    - The I/O register variables that can be accessed in bits, bytes or words
      are declared in union type (except some declared in structure type).

    - The I/O register variables that must be accessed in 1, 2 or 4 bytes
      are declared in integer type.

    - Basically, each variable name is declared in the form of the
      corresponding I/O  register name plus 'IO_'.
      (However, for access convenience, two or more I/O registers may be
       declared by one variable name.)

    - A bit field member name is declared by the corresponding bit name.
      (some bits are declared in one member name for access convenience)


  [Example]  Declaration for I/O register PDR0

    - I/O register structure

          7       6       5       4       3       2       1       0    bit No.
      +-------+-------+-------+-------+-------+-------+-------+-------+
      |  P07  |  P06  |  P05  |  P04  |  P03  |  P02  |  P01  |  P00  | PDR0
      +-------+-------+-------+-------+-------+-------+-------+-------+

    - Contents of declaration

        union io_pdr0 {
                unsigned char    byte;
                struct {
                        unsigned char    P07:1;
                        unsigned char    P06:1;
                        unsigned char    P05:1;
                        unsigned char    P04:1;
                        unsigned char    P03:1;
                        unsigned char    P02:1;
                        unsigned char    P01:1;
                        unsigned char    P00:1;
                } bit;
        };

        extern __io union io_pdr0   IO_PDR0;

CHAPTER 4  VARIABLE AND MEMBER NAMES USED IN I/O REGISTER DECLARATION FILES
           FOR MB91310 series

<<I/O Ports>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  Pn7  |  Pn6  |  Pn5  |  Pn4  |  Pn3  |  Pn2  |  Pn1  |  Pn0  | PDRn,
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | I2CTST|   -   |   -   | I2CE4 | I2CE3 | I2CE2 | I2CE1 | I2CE0 | PFR0
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | UART3 | SCKE3 | UART2 | SCKE2 | UART1 | SCKE1 | UART0 | SCKE0 | PFR1
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TOE2 |  TOE1 |  TOE0 |   -   |   -   |   -   | UART4 | SCKE4 | PFR2
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TME3 |  TME2 |  TME1 |  TME0 | PPGE3 | PPGE2 | PPGE1 | PPGE0 | PFR3
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  MSE  |   -   |   -   |   -   |   -   |   -   |   -   |   -   | PFR4
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      PDRn(n:0-7)      IO_PDRn.byte           IO_PDRn.bit.Pnx(x:0-7)

      DDRn(n:0-7)      IO_PORT.IO_DDRn.byte   IO_PORT.IO_DDRn.bit.Pnx(x:0-7)

      PFR0             IO_PORT.IO_PFR0.byte   IO_PORT.IO_PFR0.bit.I2CTST
                                              IO_PORT.IO_PFR0.bit.I2CEx(x:0-4)

      PFR1             IO_PORT.IO_PFR1.byte   IO_PORT.IO_PFR1.bit.UARTx(x:0-3)
                                              IO_PORT.IO_PFR1.bit.SCKEx(x:0-3)

      PFR2             IO_PORT.IO_PFR2.byte   IO_PORT.IO_PFR2.bit.TOEx(x:0-2)
                                              IO_PORT.IO_PFR2.bit.UART4
                                              IO_PORT.IO_PFR2.bit.SCKE4

      PFR3             IO_PORT.IO_PFR3.byte   IO_PORT.IO_PFR3.bit.TMEx (x:0-3)
                                              IO_PORT.IO_PFR3.bit.PPGEx(x:0-3)

      PFR4             IO_PORT.IO_PFR4.byte   IO_PORT.IO_PFR4.bit.MSE
    --------------------------------------------------------------------------
      Note: The following bits do not exist;
            members to be accessed in bits are not declared.

              PDR2,DDR2 : P26-P27
              PDR3,DDR3 : P37
              PDR6,DDR6 : P66-P67
              PDR7,DDR7 : P75-P77

<<A/D Converter>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   | 0 |   |   | ADCTH,
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ADCTL
                              |  STR  |  ASS2 |  ASS0 |       |  INTE
                             TRG     ASS3    ASS1    BUSY    INT 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | 0 | 0 | 0 | 0 | 0 | 0 | i9| i8| i7| i6| i5| i4| i3| i2| i1| i0| ADCH
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | 0 | 0 | 0 | 0 | 0 | 0 | d9| d8| d7| d6| d5| d4| d3| d2| d1| d0| ADATn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      ADCTH/ADCHL      IO_ADCT.hword          IO_ADCT.bit.TRG
                                              IO_ADCT.bit.STR
                                              IO_ADCT.bit.ASS  [ASS0 - ASS3]
                                              IO_ADCT.bit.BUSY
                                              IO_ADCT.bit.INT
                                              IO_ADCT.bit.INTE

      ADCH             IO_ADCH                none

      ADATn(n:0 - 9)   IO_ADATn               none
    --------------------------------------------------------------------------

<<External Interrupt>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  EN7  |  EN6  |  EN5  |  EN4  |  EN3  |  EN2  |  EN1  |  EN0  | ENIR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  ER7  |  ER6  |  ER5  |  ER4  |  ER3  |  ER2  |  ER1  |  ER0  | EIRR
    +-------+-------+-------+-------+-------+-------+-------+-------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | ELVR
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  LA7  |  LA6  |  LA5  |  LA4  |  LA3  |  LA2  |  LA1  |  LA0
     LB7     LB6     LB5     LB4     LB3     LB2     LB1     LB0

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      ENIR             IO_ENIR.byte           IO_ENIR.bit.ENx(x:0 - 7)

      EIRR             IO_EIRR.byte           IO_EIRR.bit.ERx(x:0 - 7)

      ELVR             IO_ELVR.hword          IO_ELVR.bit.LBLAx(x:0 - 7)
                                                                  [LBx,LAx]
    --------------------------------------------------------------------------

<<Delayed Interrupt Control Register>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |   -   |   -   |  DLYI | DICR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      DICR             IO_DICR.byte           IO_DICR.bit.DLYI
    --------------------------------------------------------------------------

<<Interrupt Controller>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |  ICR4 |  ICR3 |  ICR2 |  ICR1 |  ICR0 | ICRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |MHALTI |   -   |   -   |  LVL4 |  LVL3 |  LVL2 |  LVL1 |  LVL0 | HRCL
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      ICRn(n:00 - 47)  IO_ICR[n].byte         IO_ICR[n].bit.ICR   [ICR0 - ICR4]

      HRCL             IO_HRCL.byte           IO_HRCL.bit.LVL     [LVL0 - LVL4]
                                              IO_HRCL.bit.MHALTI
    --------------------------------------------------------------------------
      Note : ICR4 bits of ICRn(n:00-47) and LVL4 bit of HRCL are fixed at 1.
             You cannot write 0.

<<16-bit Reload Timer>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | - | - | - | - |   |   |   |   |   | - | - |   |   |   |   |   | TMCSRn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      |  CSL0 |  MOD1 |          RELD |   UF  |  TRG
                     CSL1    MOD2    MOD0            INTE    CNTE

      15                                                           0  bit No.
    +---------------------------------------------------------------+
    |                                                               | TMRn
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | TMRLRn
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      TMCSRn(n:0 - 2)  IO_TMCSRn.hword        IO_TMCSRn.bit.CSL   [CSL0 - CSL1]
                                              IO_TMCSRn.bit.MOD   [MOD0 - MOD2]
                                              IO_TMCSRn.bit.RELD
                                              IO_TMCSRn.bit.INTE
                                              IO_TMCSRn.bit.UF
                                              IO_TMCSRn.bit.CNTE
                                              IO_TMCSRn.bit.TRG

      TMRn  (n:0 - 2)  IO_TMRn                none

      TMRLRn(n:0 - 2)  IO_TMRLRn              none
    --------------------------------------------------------------------------
      Note: Always write 0 to No 5,12,13 bit of TMCSRn.

<<UART>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  MD1  |  MD0  |   -   |   -   |  CS0  |   -   |   -   |   -   | SMRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  PEN  |    P  |  SBL  |   CL  |  A/D  |  REC  |  RXE  |  TXE  | SCRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   D7  |   D6  |   D5  |   D4  |   D3  |   D2  |   D1  |   D0  | SIDRn/
    +-------+-------+-------+-------+-------+-------+-------+-------+ SODRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   PE  |  ORE  |  FRE  |  RDRF |  TDRE |  BDS  |  RIE  |  TIE  | SSRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   | DRCLn
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      SMRn(n:0 - 4)    IO_SMRn.byte           IO_SMRn.bit.MD      [MD0 - MD1]

      SCRn(n:0 - 4)    IO_SCRn.byte           IO_SCRn.bit.PEN
                                              IO_SCRn.bit.P
                                              IO_SCRn.bit.SBL
                                              IO_SCRn.bit.CL
                                              IO_SCRn.bit.AD
                                              IO_SCRn.bit.REC
                                              IO_SCRn.bit.RXE
                                              IO_SCRn.bit.TXE

      SIDRn/           IO_SIDRn               none
      SODRn(n:0 - 4)

      SSRn(n:0 - 4)    IO_SSRn.byte           IO_SSRn.bit.PE
                                              IO_SSRn.bit.ORE
                                              IO_SSRn.bit.FRE
                                              IO_SSRn.bit.RDRF
                                              IO_SSRn.bit.TDRE
                                              IO_SSRn.bit.BDS
                                              IO_SSRn.bit.RIE
                                              IO_SSRn.bit.TIE

      DRCLn(n:0 - 4)   IO_DRCLn               none
    --------------------------------------------------------------------------
      Note 1: CS0 bit of SMRn is a write-only bit;
              members to be accessed in bits are not declared.
      Note 2: The usage of bit access members of SMRn are limited to the
              reading description.
      Note 3: Data write to SMRn is enabled by assigning a variable or constant
              to member IO_SMRn.byte with a simple assignment expression.
              (Always write 0 to bit No.1-2, 1 to bit No.4-5)

<<U-Timer>>

  - I/O register structure

      15                                                           0  bit No.
    +---------------------------------------------------------------+
    |                                                               | UTIMn/
    +---------------------------------------------------------------+ UTIMRn

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  UCC1 |   -   |   -   |  UTIE |  UNDR |  CLKS |  UTST |  UTCR | UTIMCn
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      UTIMn/           IO_UTIMn               none
      UTIMRn(n:0 - 4)

      UTIMCn(n:0 - 4)  IO_UTIMCn.byte         IO_UTIMCn.bit.UCC1
                                              IO_UTIMCn.bit.UTIE
                                              IO_UTIMCn.bit.UNDR
                                              IO_UTIMCn.bit.CLKS
                                              IO_UTIMCn.bit.UTST
                                              IO_UTIMCn.bit.UTCR
    --------------------------------------------------------------------------
      Note: Always write 0 to CLKS bit of UTIMCn.

<<16bit PWC timer>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   | - | - |   |   |   |   | - | - |   |   |   |   | PWCC
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  INTE | OVFLE         |   ST  | TEST0   CSFL1 |  CSK2 |  CSK0
     INT     OVFL            MSKE   TEST1           CSFL0    CSK1
    +---------------------------------------------------------------+
    |                                                               | PWCD
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
      Register name  At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      PWCC              IO_PWCC.hword         IO_PWCC.bit.INT
                                              IO_PWCC.bit.INTE
                                              IO_PWCC.bit.OVFL
                                              IO_PWCC.bit.OVFLE
                                              IO_PWCC.bit.MSKE
                                              IO_PWCC.bit.ST
                                              IO_PWCC.bit.TEST1
                                              IO_PWCC.bit.TEST0
                                              IO_PWCC.bit.CSLF [CSLF0 - CSLF1]
                                              IO_PWCC.bit.CSK  [CSK0 - CSK2]

      PWCD              IO_PWCD               none
    --------------------------------------------------------------------------

<<IIC Interface>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  BER  |  BEIE |  SCC  |  MSS  |  ACK  |  GCAA |  INTE |  INT  | IBCRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   BB  |  RSC  |   AL  |  LRB  |  TRX  |  AAS  |  GCA  |  ADT  | IBSRn
    +-------+-------+-------+-------+-------+-------+-------+-------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | - | - | - | - | - | - |   |   |   |   |   |   |   |   |   |   | ITBAn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                              |  TA8  |  TA6  |  TA4  |  TA2  |  TA0
                             TA9     TA7     TA5     TA3     TA1
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   | - | - | - | - |   |   |   |   |   |   |   |   |   |   | ITMKn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  RAL                  |  TM8  |  TM6  |  TM4  |  TM2  |  TM0
     ENTB                    TM9     TM7     TM5     TM3     TM1

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |  SA6  |  SA5  |  SA4  |  SA3  |  SA2  |  SA1  |  SA0  | ISBAn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  ENSB |  SM6  |  SM5  |  SM4  |  SM3  |  SM2  |  SM1  |  SM0  | ISMKn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   D7  |   D6  |   D5  |   D4  |   D3  |   D2  |   D1  |   D0  | IDARn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TEST |   -   |   EN  |  CS4  |  CS3  |  CS2  |  CS1  |  CS0  | ICCRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |   -   |   -   |  DBL  | IDBLn
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      IBCRn(n:0 - 3)   IO_IBCRn.byte          IO_IBCRn.bit.BER
                                              IO_IBCRn.bit.BEIE
                                              IO_IBCRn.bit.SCC
                                              IO_IBCRn.bit.MSS
                                              IO_IBCRn.bit.ACK
                                              IO_IBCRn.bit.GCAA
                                              IO_IBCRn.bit.INTE
                                              IO_IBCRn.bit.INT

      IBSRn(n:0 - 3)   IO_IBSRn.byte          IO_IBSRn.bit.BB
                                              IO_IBSRn.bit.RSC
                                              IO_IBSRn.bit.AL
                                              IO_IBSRn.bit.LRB
                                              IO_IBSRn.bit.TRX
                                              IO_IBSRn.bit.AAS
                                              IO_IBSRn.bit.GCA
                                              IO_IBSRn.bit.ADT

      ITBAn(n:0 - 3)   IO_ITBAn.hword         IO_ITBAn.bit.TA  [TA0 - TA9]

      ITMKn(n:0 - 3)   IO_ITMKn.hword         IO_ITMKn.bit.ENTB
                                              IO_ITMKn.bit.RAL
                                              IO_ITMKn.bit.TM  [TM0 - TM9]

      ISBAn(n:0 - 3)   IO_ISBAn.byte          IO_ISBAn.bit.SA  [SA0 - SA6]

      ISMKn(n:0 - 3)   IO_ISMKn.byte          IO_ISMKn.bit.ENSB
                                              IO_ISMKn.bit.SM  [SM0 - SM6]

      IDARn(n:0 - 3)   IO_IDARn               none

      ICCRn(n:0 - 3)   IO_ICCRn.byte          IO_ICCRn.bit.TEST
                                              IO_ICCRn.bit.EN
                                              IO_ICCRn.bit.CS  [CS0 - CS4]

      IDBLn(n:0 - 3)   IO_IDBLn.byte          IO_IDBLn.bit.DBL
    --------------------------------------------------------------------------
      Note: When using a simple assignment statement to write data to ICCRn
            (member IO_ICCRn.byte),
            be sure to write 0 to TEST bit and bit No.6.

<<Multi function timer>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |  FCn1 |  FCn0 |  FnEN | TnLPCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  CPF  |   -   |  CPST |  CPED |  CPIE |  CPOV |  CPMD |  CPIS | TnCCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TCF  |  TSES |  TCC  |  TIE  |  CINV |  TCS2 |  TCS1 |  TCS0 | TnTCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |  TST2 |  TST2 |  MD1  |  MD0  |   ST  | TnR
    +-------+-------+-------+-------+-------+-------+-------+-------+

      15                                                          0   bit No.
    +---------------------------------------------------------------+
    |                                                               | TnDRR
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | TnCRR
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      TnLPCR(n:0 - 3)  IO_TnLPCR.byte         IO_TnLPCR.bit.FCn  [FCn0 - FCn1]
                                              IO_TnLPCR.bit.FnEN

      TnCCR(n:0 - 3)   IO_TnCCR.byte          IO_TnCCR.bit.CPF
                                              IO_TnCCR.bit.CPST
                                              IO_TnCCR.bit.CPED
                                              IO_TnCCR.bit.CPIE
                                              IO_TnCCR.bit.CPOV
                                              IO_TnCCR.bit.CPMD
                                              IO_TnCCR.bit.CPIS

      TnTCR(n:0 - 3)   IO_TnTCR.byte          IO_TnTCR.bit.TCF
                                              IO_TnTCR.bit.TSES
                                              IO_TnTCR.bit.TCC
                                              IO_TnTCR.bit.TIE
                                              IO_TnTCR.bit.CNIV
                                              IO_TnTCR.bit.TCS  [TCS0 - TCS2]

      TnR  (n:0 - 3)   IO_TnR.byte            IO_TnR.bit.TST2
                                              IO_TnR.bit.TST1
                                              IO_TnR.bit.MD     [MD0 - MD1]
                                              IO_TnR.bit.ST

      TnDRR(n:0 - 3)   IO_TnDRR               none

      TnCRR(n:0 - 3)   IO_TnCRR               none
    --------------------------------------------------------------------------
      Note: When using a simple assignment statement to write data to TnR
            (member IO_TnR.byte),
            be sure to write 0 to TST1, TST2 bit.

<<PPG Timer>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   | - |   |   |   |   |   |   | - |   | PCNn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  STGR |  RTRG |  CKS0 |       |  EGS0 |  IRQF |  IRS0    OSEL
     CNTE    MDSE    CKS1    PGMS    EGS1    IREN    IRS1
    +---------------------------------------------------------------+
    |                                                               | PCSRn,
    +---------------------------------------------------------------+ PDUTn
    +---------------------------------------------------------------+
    |                                                               | PTMRn
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      PCNn (n:0 - 3)   IO_PCNn.hword          IO_PCNn.bit.CNTE
                                              IO_PCNn.bit.STGR
                                              IO_PCNn.bit.MDSE
                                              IO_PCNn.bit.RTRG
                                              IO_PCNn.bit.CKS     [CKS0 - CKS1]
                                              IO_PCNn.bit.PGMS
                                              IO_PCNn.bit.EGS     [EGS0 - EGS1]
                                              IO_PCNn.bit.IREN
                                              IO_PCNn.bit.IRQF
                                              IO_PCNn.bit.IRS     [IRS0 - IRS1]
                                              IO_PCNn.bit.OSEL

      PCSRn(n:0 - 3)   IO_PCSRn               none

      PDUTn(n:0 - 3)   IO_PDUTn               none

      PTMRn(n:0 - 3)   IO_PTMRn               none
    --------------------------------------------------------------------------

<<DMAC>>

  - I/O register structure

      31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  bit No.
    +---+---+---+-------------------+---------------+---------------+-
    |   |   |   |       IS[4:0]     |   DDNO[3:0]   |    BLK[3:0]   |
    +---+---+---+-------------------+---------------+---------------+-
      |  PAUS |
     DENB    STRG
        15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
     -+---------------------------------------------------------------+
      |                           DTC[15:0]                           | DMACAn
     -+---------------------------------------------------------------+

      31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  bit No.
    +-------+-------+-------+---+---+---+---+---+---+---+-----------+-
    |  TYPE |  MOD  |   WS  |   |   |   |   |   |   |   |  DSS[2:0] |
    +-------+-------+-------+---+---+---+---+---+---+---+-----------+-
                              |  DADM |  SADR |  ERIE |
                             SADM    DTCR    DADR    EDIE
        15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
     -+-------------------------------+-------------------------------+
      |           SASZ[7:0]           |           DASZ[7:0]           | DMACBn
     -+-------------------------------+-------------------------------+

      31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  bit No.
    +---+---+---+---+---------------+---+---+---+---+---+---+---+---+-
    |   | - | - |   |   DMAH[3:0]   | - | - | - | - | - | - | - | - |
    +---+---+---+---+---------------+---+---+---+---+---+---+---+---+-
     DMAE        PM01
        15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DMACR
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

      31                                                           0  bit No.
    +---------------------------------------------------------------+
    |                                                               | DMASAm,
    +---------------------------------------------------------------+ DMADAm

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      DMACAn(n:0 - 4)  IO_DMACAn.word         IO_DMACAn.bit.DENB
                                              IO_DMACAn.bit.PAUS
                                              IO_DMACAn.bit.STRG
                                              IO_DMACAn.bit.IS    [IS0 - IS4]
                                              IO_DMACAn.bit.DDNO  [DDNO0-DDNO3]
                                              IO_DMACAn.bit.BLK   [BLK0 - BLK3]

      DMACBn(n:0 - 4)  IO_DMACBn.word         IO_DMACBn.bit.TYPE  [TYPE0-TYPE1]
                                              IO_DMACBn.bit.MOD   [MOD0 - MOD1]
                                              IO_DMACBn.bit.WS    [WS0  - WS1]
                                              IO_DMACBn.bit.SADM
                                              IO_DMACBn.bit.DADM
                                              IO_DMACBn.bit.DTCR
                                              IO_DMACBn.bit.SADR
                                              IO_DMACBn.bit.DADR
                                              IO_DMACBn.bit.ERIE
                                              IO_DMACBn.bit.EDIE
                                              IO_DMACBn.bit.DSS   [DSS0 - DSS2]


      DMACR            IO_DMACR.word          IO_DMACR.bit.DMAE
                                              IO_DMACR.bit.PM01
                                              IO_DMACR.bit.DMAH   [DMAH0-DMAH3]

      DMASAn(n:0 - 4)  IO_DMAD.IO_DMASAn      none

      DMADAn(n:0 - 4)  IO_DMAD.IO_DMADAn      none
    --------------------------------------------------------------------------
      Note 1: When you access DTC of DMACAn, please handle to bit No.0-15
              bits of member IO_DMACAn.word.
      Note 2: When you access SASZ and DASZ of DMACBn, please handle to bit
              No.0-15 bits of member IO_DMACBn.word.

<<Bit Search Module>>

  - I/O register structure

      31                                                           0  bit No.
    +---------------------------------------------------------------+
    |                                                               | BSD0
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | BSD1
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | BSDC
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | BSRR
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      BSD0             IO_BSD0                none

      BSD1             IO_BSD1                none

      BSDC             IO_BSDC                none

      BSRR             IO_BSRR                none
    --------------------------------------------------------------------------

<<Clock control unit>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  INIT |   -   |  WDOG |   -   |  SRST |   -   |  WT1  |  WT0  | RSRR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  STOP | SLEEP |  HIZ  |  SRST |  OS1  |  OS0  | OSCD2 | OSCD1 | STCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TBIF |  TBIE |  TBC2 |  TBC1 |  TBC0 |   -   | SYNCR | SYNCS | TBCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   D7  |   D6  |   D5  |   D4  |   D3  |   D2  |   D1  |   D0  | CTBR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | PLL2S0| PLL1S2| PLL1S1| PLL1S0| PLL2EN| PLL1EN| CLKS1 | CLKS0 | CLKR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   D7  |   D6  |   D5  |   D4  |   D3  |   D2  |   D1  |   D0  | WPR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   B3  |   B2  |   B1  |   B0  |   P3  |   P2  |   P1  |   P0  | DIVR0
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   T3  |   T2  |   T1  |   T0  |   -   |   -   |   -   |   -   | DIVR1
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |   -   |   -   | OSCDS1| OSCCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      RSRR             IO_CLK.IO_RSRR.byte   IO_CLK.IO_RSRR.bit.INIT
                                             IO_CLK.IO_RSRR.bit.WDOG
                                             IO_CLK.IO_RSRR.bit.SRST
                                             IO_CLK.IO_RSRR.bit.WT [WT0 - WT1]

      STCR             IO_CLK.IO_STCR.byte   IO_CLK.IO_STCR.bit.STOP
                                             IO_CLK.IO_STCR.bit.SLEEP
                                             IO_CLK.IO_STCR.bit.HIZ
                                             IO_CLK.IO_STCR.bit.SRST
                                             IO_CLK.IO_STCR.bit.OS [OS0 - OS1]
                                             IO_CLK.IO_STCR.bit.OSCD2
                                             IO_CLK.IO_STCR.bit.OSCD1

      TBCR             IO_CLK.IO_TBCR.byte   IO_CLK.IO_TBCR.bit.TBIF
                                             IO_CLK.IO_TBCR.bit.TBIE
                                             IO_CLK.IO_TBCR.bit.TBC [TBC0-TBC2]
                                             IO_CLK.IO_TBCR.bit.SYNCR
                                             IO_CLK.IO_TBCR.bit.SYNCS

      CTBR             IO_CLK.IO_CTBR        none

      CLKR             IO_CLK.IO_CLKR.byte   IO_CLK.IO_CLKR.bit.PLL2S0
                                             IO_CLK.IO_CLKR.bit.PLL1S[PLL1S0-2]
                                             IO_CLK.IO_CLKR.bit.PLL2EN
                                             IO_CLK.IO_CLKR.bit.PLL1EN
                                             IO_CLK.IO_CLKR.bit.CLKS [CLKS0-1]

      WPR              IO_CLK.IO_WPR         none

      DIVR0            IO_CLK.IO_DIVR0.byte  IO_CLK.IO_DIVR0.bit.B  [B0 - B3]
                                             IO_CLK.IO_DIVR0.bit.P  [P0 - P3]

      DIVR1            IO_CLK.IO_DIVR1.byte  IO_CLK.IO_DIVR1.bit.T  [T0 - T3]

      OSCCR            IO_CLK.IO_OSCCR.byte  IO_CLK.IO_OSCCR.bit.OSCDS1
    --------------------------------------------------------------------------

<<Watch timer>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  WIF  |  WIE  |   -   |   -   |   -   |  WS1  |  WS0  |  WCL  | WPCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      WPCR             IO_WPCR.byte           IO_WPCR.bit.WIF
                                              IO_WPCR.bit.WIE
                                              IO_WPCR.bit.WS  [WS0 - WS1]
                                              IO_WPCR.bit.WCL
    --------------------------------------------------------------------------
      Note: Always write 0 to bit No.3-5 of WPCR.

<<Wait main oscilate timer>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  WIF  |  WIE  |   -   |   -   |   -   |  WS1  |  WS0  |  WCL  | OSCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      OSCR             IO_OSCR.byte           IO_OSCR.bit.WIF
                                              IO_OSCR.bit.WIE
                                              IO_OSCR.bit.WS  [WS0 - WS1]
                                              IO_OSCR.bit.WCL
    --------------------------------------------------------------------------
      Note: Always write 0 to bit No.3-5 of OSCR.

<<External Bus Interface>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | ASRn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  A30  |  A28  |  A26  |  A24  |  A22  |  A20  |  A18  |  A16
     A31     A29     A27     A25     A23     A21     A19     A17
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | ACRn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  ASZ2 |  ASZ0 |  DBW0 |  BST0 |  PFEN |  LEND |  TYP2 |  TYP0
     ASZ3    ASZ1    DBW1    BST1    SREN    WREN    TYP3    TYP1
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | AWRn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  W14  |  W12  |  W10  |  W08  |  W06  |  W04  |  W02  |  W00
     W15     W13     W11     W09     W07     W05     W03     W01

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  RYEn |  HLDn |  WRn1 |  WRn0 |  IWn3 |  IWn2 |  IWn1 |  IWn0 | IOWRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  CSE7 |  CSE6 |  CSE5 |  CSE4 |  CSE3 |  CSE2 |  CSE1 |  CSE0 | CSER
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  CHE7 |  CHE6 |  CHE5 |  CHE4 |  CHE3 |  CHE2 |  CHE1 |  CHE0 | CHER
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  BREN |  PSUS |  PCLR |reserve|  OHT1 |  OHT0 |  RWD1 |  RWD0 | TCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      ASRn(n:0 - 7)   IO_EBUS.IO_ASRn       none

      ACRn(n:0 - 7)   IO_EBUS.IO_ACRn.hword IO_EBUS.IO_ACRn.bit.ASZ [ASZ0-ASZ3]
                                            IO_EBUS.IO_ACRn.bit.DBW [DBW0-DBW1]
                                            IO_EBUS.IO_ACRn.bit.BST [BST0-BST1]
                                            IO_EBUS.IO_ACRn.bit.SREN
                                            IO_EBUS.IO_ACRn.bit.PFEN
                                            IO_EBUS.IO_ACRn.bit.WREN
                                            IO_EBUS.IO_ACRn.bit.LEND
                                            IO_EBUS.IO_ACRn.bit.TYP [TYP0-TYP3]

      AWRn(n:0 - 7)   IO_EBUS.IO_AWRn       none

      IOWRn(n:0 - 2)  IO_EBUS.IO_IOWRn.byte IO_EBUS.IO_IOWRn.bit.RYEn
                                            IO_EBUS.IO_IOWRn.bit.HLDn
                                            IO_EBUS.IO_IOWRn.bit.WRn[WRn1-WRn0]
                                            IO_EBUS.IO_IOWRn.bit.IWn[IWn3-IWn0]

      CSER            IO_EBUS.IO_CSER.byte  IO_EBUS.IO_CSER.bit.CSEz(z:0 - 7)

      CHER            IO_EBUS.IO_CHER.byte  IO_EBUS.IO_CHER.bit.CHEz(z:0 - 7)

      TCR             IO_EBUS.IO_TCR.byte   IO_EBUS.IO_TCR.bit.BREN
                                            IO_EBUS.IO_TCR.bit.PSUS
                                            IO_EBUS.IO_TCR.bit.PCLR
                                            IO_EBUS.IO_TCR.bit.OHT  [OHT0-OHT1]
                                            IO_EBUS.IO_TCR.bit.RDW  [RDW0-RDW1]
    --------------------------------------------------------------------------
      Note: Always write 0 to reserved bits of TCR.

<<Mode Data>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   *   |   *   |   *   |   *   |   *   |  ROMA |  WTH1 |  WTH0 | MODR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      MODR             IO_MODR                none
    --------------------------------------------------------------------------
      Note: MODR is a write-only register; members to be accessed in bits
            are not declared.
            Data write to MODR is enabled by assigning a variable or constant
            to variable IO_MODR with a simple assignment expression.
            (Always write 0 to * bits.)

<<Flush memory interface>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |  RDY  |   -   |   WE  |   -   | FLCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |  FAC1 |  FAC0 |   -   |  WTC1 |  WTC1 |  WTC0 | FLWC
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      FLCR             IO_FLCR.byte           IO_FLCR.bit.RDY
                                              IO_FLCR.bit.WE

      FLWC             IO_FLWC.byte           IO_FLWC.bit.FAC   [FAC0 - FAC1]
                                              IO_FLWC.bit.WTC   [WTC0 - WTC2]
    --------------------------------------------------------------------------
      Note1: Always write 0 to bit No.2,4,7 and 1 to bit No.5,6 of FLCR.
      Note2: Always write 0 to bit No.3,6,7 of FLWC.

<<USB Host>>

  - I/O register structure

    31                              8   7   6   5   4   3   2   1   0   bit No.
  +-----------------------------------+-------------------------------+
  |                 -                 |              REV              | HR
  +-----------------------------------+-------------------------------+

    31                  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +-----------------------+---+---+---+-------+---+---+---+---+-------+
  |           -           |RWE|RWC| IR|  HCFS |BLE|CLE| IE|PLE|  CBSR | HC
  +-----------------------+---+---+---+-------+---+---+---+---+-------+

    31    18  17  16  15                            4   3   2   1   0   bit No.
  +---------+-------+---------------------------------+---+---+---+---+
  |         |  SOC  |                      -          |OCR|BLF|CLF|HCR| HCS
  +---------+-------+---------------------------------+---+---+---+---+

    31  30  29                          7   6   5   4   3   2   1   0   bit No.
  +---+---+-------------------------------+---+---+---+---+---+---+---+
  | --| OC|               -               |   |FNO| UE| RD| SF|WDH| SO| HIS
  +---+---+-------------------------------+---+---+---+---+---+---+---+
                                          RHSC
  +---+---+-------------------------------+---+---+---+---+---+---+---+
  |MIE| OC|               -               |   |FNO| UE| RD| SF|WDH| SO| HIE
  +---+---+-------------------------------+---+---+---+---+---+---+---+
                                          RHSC
  +---+---+-------------------------------+---+---+---+---+---+---+---+
  | ME| OC|               -               |   |FNO| UE| RD| SF|WDH| SO| HID
  +---+---+-------------------------------+---+---+---+---+---+---+---+
                                          RHSC

    31                              8   7                           0   bit No.
  +-----------------------------------+-------------------------------+
  |                HCCA               |               -               | HHCCA
  +-----------------------------------+-------------------------------+

    31                                          4   3               0   bit No.
  +-----------------------------------------------+-------------------+
  |                        PCED                   |         -         | HPCED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                        CHED                   |         -         | HCHED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                        CCED                   |         -         | HCCED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                        BHED                   |         -         | HBHED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                        BCED                   |         -         | HBCED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                         DH                    |         -         | HDH
  +-----------------------------------------------+-------------------+

    31  30                  16  15  14  13                          0   bit No.
  +---+-----------------------+-------+-------------------------------+
  |FIT|           FSMPS       |   -   |                 FI            | HFI
  +---+-----------------------+-------+-------------------------------+
    31  30                          14  13                          0   bit No.
  +---+-------------------------------+-------------------------------+
  |FRT|                  -            |                 FR            | HFR
  +---+-------------------------------+-------------------------------+
    31                    16  15                                    0   bit No.
  +-------------------------+-----------------------------------------+
  |               -         |                       FN                | HFN
  +-------------------------+-----------------------------------------+
    31                            14  13                            0   bit No.
  +---------------------------------+---------------------------------+
  |               -                 |               PS                | HPS
  +---------------------------------+---------------------------------+
    31                                    12  11                    0   bit No.
  +-----------------------------------------+-------------------------+
  |               -                         |             LST         | HLST
  +-----------------------------------------+-------------------------+

    31    24  23                      13  12  11  10  9   8   7     0   bit No.
  +---------+---------------------------+---+---+---+---+---+---------+
  |  POTPGT |              -            |   |   | DT|NPS|PSM|   NDP   | HRDA
  +---------+---------------------------+---+---+---+---+---+---------+
                                        NOCP OCPM
    31                    16  15                                    0   bit No.
  +-------------------------+-----------------------------------------+
  |          PPCM           |                       DR                | HRDB
  +-------------------------+-----------------------------------------+

    31  30        18  17  16  15  14                        2   1   0   bit No.
  +---+-------------+---+---+---+-----------------------------+---+---+
  |   |      -      |   |   |   |                -            |OCI|LPS| HRS
  +---+-------------+---+---+---+-----------------------------+---+---+
   CWRE             OCIC LPSC DRWE

    31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16      bit No.
  +-------------------------------------------+---+---+---+---+---+-
  |                       -                   |   |   |   |   |CSC| 
  +-------------------------------------------+---+---+---+---+---+-
                                               PRSC |  PSSC |
                                                   OCIC    PESC
        15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
     -+-----------------------+---+---+-----------+---+---+---+---+---+
      |           -           |   |PPS|     -     |PRS|   |PSS|PES|CCS| HRPSn
     -+-----------------------+---+---+-----------+---+---+---+---+---+
                              LSDA                    POCI

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      HR               IO_USBH.IO_HR.word     IO_USBH.IO_HR.bit.REV

      HC               IO_USBH.IO_HC.word     IO_USBH.IO_HC.bit.RWE
                                              IO_USBH.IO_HC.bit.RWC
                                              IO_USBH.IO_HC.bit.IR
                                              IO_USBH.IO_HC.bit.HCFS
                                              IO_USBH.IO_HC.bit.BLE
                                              IO_USBH.IO_HC.bit.CLE
                                              IO_USBH.IO_HC.bit.IE
                                              IO_USBH.IO_HC.bit.PLE
                                              IO_USBH.IO_HC.bit.CBSR

      HCS              IO_USBH.IO_HCS.word    IO_USBH.IO_HCS.bit.SOC
                                              IO_USBH.IO_HCS.bit.OCR
                                              IO_USBH.IO_HCS.bit.BLF
                                              IO_USBH.IO_HCS.bit.CLF
                                              IO_USBH.IO_HCS.bit.HCR

      HIS              IO_USBH.IO_HIS.word    IO_USBH.IO_HIS.bit.OC
                                              IO_USBH.IO_HIS.bit.RHSC
                                              IO_USBH.IO_HIS.bit.FNO
                                              IO_USBH.IO_HIS.bit.UE
                                              IO_USBH.IO_HIS.bit.RD
                                              IO_USBH.IO_HIS.bit.SF
                                              IO_USBH.IO_HIS.bit.WDH
                                              IO_USBH.IO_HIS.bit.SO

      HIE              IO_USBH.IO_HIE.word    IO_USBH.IO_HIE.bit.MIE
                                              IO_USBH.IO_HIE.bit.OC
                                              IO_USBH.IO_HIE.bit.RHSC
                                              IO_USBH.IO_HIE.bit.FNO
                                              IO_USBH.IO_HIE.bit.UE
                                              IO_USBH.IO_HIE.bit.RD
                                              IO_USBH.IO_HIE.bit.SF
                                              IO_USBH.IO_HIE.bit.WDH
                                              IO_USBH.IO_HIE.bit.SO

      HID              IO_USBH.IO_HID.word    IO_USBH.IO_HID.bit.ME
                                              IO_USBH.IO_HID.bit.OC
                                              IO_USBH.IO_HID.bit.RHSC
                                              IO_USBH.IO_HID.bit.FNO
                                              IO_USBH.IO_HID.bit.UE
                                              IO_USBH.IO_HID.bit.RD
                                              IO_USBH.IO_HID.bit.SF
                                              IO_USBH.IO_HID.bit.WDH
                                              IO_USBH.IO_HID.bit.SO

      HHCCA            IO_USBH.IO_HHCCA.word  IO_USBH.IO_HHCCA.bit.HCCA

      HPCED            IO_USBH.IO_HPCED.word  IO_USBH.IO_HPCED.bit.PCED

      HCHED            IO_USBH.IO_HCHED.word  IO_USBH.IO_HCHED.bit.CHED

      HCCED            IO_USBH.IO_HCCED.word  IO_USBH.IO_HCCED.bit.CCED

      HBHED            IO_USBH.IO_HBHED.word  IO_USBH.IO_HBHED.bit.BHED

      HBCED            IO_USBH.IO_HBCED.word  IO_USBH.IO_HBCED.bit.BCED

      HDH              IO_USBH.IO_HDH.word    IO_USBH.IO_HDH.bit.DH

      HFI              IO_USBH.IO_HFI.word    IO_USBH.IO_HFI.bit.FIT
                                              IO_USBH.IO_HFI.bit.FSMPS
                                              IO_USBH.IO_HFI.bit.FI

      HFR              IO_USBH.IO_HFR.word    IO_USBH.IO_HFR.bit.FRT
                                              IO_USBH.IO_HFR.bit.FR

      HFN              IO_USBH.IO_HFN.word    IO_USBH.IO_HFN.bit.FN

      HPS              IO_USBH.IO_HPS.word    IO_USBH.IO_HPS.bit.PS

      HLST             IO_USBH.IO_HLST.word   IO_USBH.IO_HLST.bit.LST

      HRDA             IO_USBH.IO_HRDA.word   IO_USBH.IO_HRDA.bit.POTPGT
                                              IO_USBH.IO_HRDA.bit.NOCP
                                              IO_USBH.IO_HRDA.bit.OCPM
                                              IO_USBH.IO_HRDA.bit.DT
                                              IO_USBH.IO_HRDA.bit.NPS
                                              IO_USBH.IO_HRDA.bit.PSM
                                              IO_USBH.IO_HRDA.bit.NDP

      HRDB             IO_USBH.IO_HRDB.word   IO_USBH.IO_HRDB.bit.PPCM
                                              IO_USBH.IO_HRDB.bit.DR

      HRS              IO_USBH.IO_HRS.word    IO_USBH.IO_HRS.bit.CRWE
                                              IO_USBH.IO_HRS.bit.OCIC
                                              IO_USBH.IO_HRS.bit.LPSC
                                              IO_USBH.IO_HRS.bit.DRWE
                                              IO_USBH.IO_HRS.bit.OCI
                                              IO_USBH.IO_HRS.bit.LPS

      HRPSn(n:1 - 2)   IO_USBH.IO_HRPSn.word  IO_USBH.IO_HRPSn.bit.PRSC
                                              IO_USBH.IO_HRPSn.bit.OCIC
                                              IO_USBH.IO_HRPSn.bit.PSSC
                                              IO_USBH.IO_HRPSn.bit.PESC
                                              IO_USBH.IO_HRPSn.bit.CSC
                                              IO_USBH.IO_HRPSn.bit.LSDA
                                              IO_USBH.IO_HRPSn.bit.PPS
                                              IO_USBH.IO_HRPSn.bit.PRS
                                              IO_USBH.IO_HRPSn.bit.POCI
                                              IO_USBH.IO_HRPSn.bit.PSS
                                              IO_USBH.IO_HRPSn.bit.PES
                                              IO_USBH.IO_HRPSn.bit.CCS
    --------------------------------------------------------------------------

<<USB Function>>

  - I/O register structure

      15                                                          0   bit No.
    +---------------------------------------------------------------+
    |                                                               | FIFO0o,
    +---------------------------------------------------------------+ FIFO0i
    +---------------------------------------------------------------+
    |                                                               | FIFOn
    +---------------------------------------------------------------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   | N | A | N | A | N | A | N | A | N | A | 
    |   |   |   |   |   |   | A | C | A | C | A | C | A | C | A | C | 
    | - | - | - | - | - | - | C | K | C | K | C | K | C | K | C | K | ST1
    |   |   |   |   |   |   | K | 3 | K | 2 | K | 1 | K | 0 | K | 0 | 
    |   |   |   |   |   |   | 3 |   | 2 |   | 1 |   | 0 | i | 0 | o | 
    |   |   |   |   |   |   |   |   |   |   |   |   | i |   | o |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   | D | D | D | D | D | D | D | 
    | - | - | - | - | - | - | - | - | - | C | C | C | C | C | C | C | 
    |   |   |   |   |   |   |   |   |   | T | T | T | T | T | T | T | ST2
    |   |   |   |   |   |   |   |   |   | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | S | C | S | S | N | 
    |   |   |   |   |   |   |   |   |   |   |   | E | F | O | U | A | 
    | - | - | - | - | - | - | - | - | - | - | - | T | E | F | S | C | ST3
    |   |   |   |   |   |   |   |   |   |   |   | U | N |   | F | K | 
    |   |   |   |   |   |   |   |   |   |   |   | P | D |   |   | O | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | S | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   | F | F | F | F | F | F | F | F | F | F | F | 
    |   |   |   |   |   | M | M | M | M | M | M | M | M | M | M | M | 
    | - | - | - | - | - | R | R | R | R | R | R | R | R | R | R | R | ST4
    |   |   |   |   |   | 1 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
    |   |   |   |   |   | 0 |   |   |   |   |   |   |   |   |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   | U |   |   |   |   |   | S | S | S | S | T | T | 
    |   |   |   |   | S |   |   |   |   |   | T | T | T | T | R | T | 
    |   |   |   |   | B |   |   |   |   |   | S | S | S | S | C | R | 
    | - | - | - | - | R | - | - | - | - | - | T | T | T | T | V | S | ST5
    |   |   |   |   | E |   |   |   |   |   | A | A | A | A | E | E | 
    |   |   |   |   | S |   |   |   |   |   | L | L | L | L | N | N | 
    |   |   |   |   | E |   |   |   |   |   | L | L | L | L | D | D | 
    |   |   |   |   | T |   |   |   |   |   | 3 | 2 | 1 | 0 |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   | R | R | R | R | 
    |   |   |   |   |   |   |   |   |   |   |   |   | S | S | S | S | 
    |   |   |   |   |   |   |   |   |   |   |   |   | I | I | I | I | 
    | - | - | - | - | - | - | - | - | - | - | - | - | Z | Z | Z | Z | RSIZE0
    |   |   |   |   |   |   |   |   |   |   |   |   | E | E | E | E | 
    |   |   |   |   |   |   |   |   |   |   |   |   | 0 | 0 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   | R | R | R | R | R | R | R | 
    |   |   |   |   |   |   |   |   |   | S | S | S | S | S | S | S | 
    |   |   |   |   |   |   |   |   |   | I | I | I | I | I | I | I | 
    | - | - | - | - | - | - | - | - | - | Z | Z | Z | Z | Z | Z | Z | RSIZE1
    |   |   |   |   |   |   |   |   |   | E | E | E | E | E | E | E | 
    |   |   |   |   |   |   |   |   |   | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 
    |   |   |   |   |   |   |   |   |   | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   | R |   |   |   |   |   | S | S | S | S | C | 
    |   |   |   |   |   | E |   |   |   |   |   | T | T | T | T | F | 
    |   |   |   |   |   | S |   |   |   |   |   | A | A | A | A | G | 
    | - | - | - | - | - | U | - | - | - | - | - | L | L | L | L | E | CONT1
    |   |   |   |   |   | M |   |   |   |   |   | L | L | L | L | N | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | I | I | I | I | I | 
    |   |   |   |   |   |   |   |   |   |   |   | N | N | N | N | N | 
    | - | - | - | - | - | - | - | - | - | - | - | I | I | I | I | I | CONT2
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | B | B | B | B | B | 
    |   |   |   |   |   |   |   |   |   |   |   | F | F | F | F | F | 
    | - | - | - | - | - | - | - | - | - | - | - | O | O | O | O | O | CONT3
    |   |   |   |   |   |   |   |   |   |   |   | K | K | K | K | K | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | B | B | B | B | B | 
    |   |   |   |   |   |   |   |   |   |   |   | I | I | I | I | I | 
    |   |   |   |   |   |   |   |   |   |   |   | F | F | F | F | F | 
    |   |   |   |   |   |   |   |   |   |   |   | O | O | O | O | O | 
    | - | - | - | - | - | - | - | - | - | - | - | B | B | B | B | B | CONT3
    |   |   |   |   |   |   |   |   |   |   |   | U | U | U | U | U | 
    |   |   |   |   |   |   |   |   |   |   |   | S | S | S | S | S | 
    |   |   |   |   |   |   |   |   |   |   |   | Y | Y | Y | Y | Y | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | F | F | F | F | F | 
    |   |   |   |   |   |   |   |   |   |   |   | I | I | I | I | I | 
    |   |   |   |   |   |   |   |   |   |   |   | F | F | F | F | F | 
    |   |   |   |   |   |   |   |   |   |   |   | O | O | O | O | O | 
    | - | - | - | - | - | - | - | - | - | - | - | B | B | B | B | B | CONT4
    |   |   |   |   |   |   |   |   |   |   |   | U | U | U | U | U | 
    |   |   |   |   |   |   |   |   |   |   |   | S | S | S | S | S | 
    |   |   |   |   |   |   |   |   |   |   |   | Y | Y | Y | Y | Y | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   | D | D |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | I | I |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | F | F |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | O | O |   |   | 
    | - | - | - | - | - | - | - | - | - | - | - | - | B | B | - | - | CONT5
    |   |   |   |   |   |   |   |   |   |   |   |   | U | U |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | S | S |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | Y | Y |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | 2 | 1 |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   | M | M |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | D | D |   |   | 
    | - | - | - | - | - | - | - | - | - | - | - | - | R | R | - | - | CONT6
    |   |   |   |   |   |   |   |   |   |   |   |   | E | E |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | Q | Q |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | 2 | 1 |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | M | M | M | M | M | 
    |   |   |   |   |   |   |   |   |   |   |   | A | A | A | A | A | 
    | - | - | - | - | - | - | - | - | - | - | - | C | C | C | C | C | CONT7
    |   |   |   |   |   |   |   |   |   |   |   | K | K | K | K | K | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | M | M | M | M | M | 
    |   |   |   |   |   |   |   |   |   |   |   | N | N | N | N | N | 
    |   |   |   |   |   |   |   |   |   |   |   | A | A | A | A | A | 
    | - | - | - | - | - | - | - | - | - | - | - | C | C | C | C | C | CONT8
    |   |   |   |   |   |   |   |   |   |   |   | K | K | K | K | K | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   | M |   |   |   |   | M | M | M | M | 
    |   |   |   |   |   |   |   | U |   |   |   |   | S | S | S | S | 
    |   |   |   |   |   |   |   | S |   |   |   |   | T | T | T | T | 
    |   |   |   |   |   |   |   | B |   |   |   |   | A | A | A | A | 
    | - | - | - | - | - | - | - | R | - | - | - | - | L | L | L | L | CONT9
    |   |   |   |   |   |   |   | E |   |   |   |   | L | L | L | L | 
    |   |   |   |   |   |   |   | S |   |   |   |   | 3 | 2 | 1 | 0 | 
    |   |   |   |   |   |   |   | E |   |   |   |   |   |   |   |   | 
    |   |   |   |   |   |   |   | T |   |   |   |   |   |   |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   | N | N | N | D |   | L | L | L | T | T | O |   | 
    |   |   |   |   | U | U | U | M |   | S | S | S | R | T | D |   | 
    |   |   |   |   | L | L | L | A |   | T | T | T | C | C | D |   | 
    | - | - | - | - | L | L | L | M | - | D | D | D | N | N |   | - | CONT10
    |   |   |   |   | S | S | S | O |   | 3 | 2 | 0 | T | T |   |   | 
    |   |   |   |   | E | E | E | D |   |   |   |   | E | E |   |   | 
    |   |   |   |   | T | T | T | E |   |   |   |   | N | N |   |   | 
    |   |   |   |   | 3 | 2 | 0 |   |   |   |   |   |   |   |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

      15                                                          0   bit No.
    +----------------------------------------------------------------+
    |                                                               | TTSIZE
    +---------------------------------------------------------------+
    +----------------------------------------------------------------+
    |                                                               | TRSIZE
    +---------------------------------------------------------------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | S | R | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | U | E | 
    | - | - | - | - | - | - | - | - | - | - | - | - | - | - | S | S | RESET
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | P | E | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | E | T | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | N | X | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      FIFO0o         IO_USBF.IO_FIFO0o        none

      FIFO0i         IO_USBF.IO_FIFO0i        none

      FIFOn(n:1 - 3) IO_USBF.IO_FIFOn         none

      ST1            IO_USBF.IO_ST1.hword     IO_USBF.IO_ST1.bit.NACKx(x:1-3)
                                              IO_USBF.IO_ST1.bit.ACKx (x:1-3)
                                              IO_USBF.IO_ST1.bit.NACK0i
                                              IO_USBF.IO_ST1.bit.ACK0i
                                              IO_USBF.IO_ST1.bit.NACK0o
                                              IO_USBF.IO_ST1.bit.ACK0o

      ST2            IO_USBF.IO_ST2.hword     IO_USBF.IO_ST2.bit.DCT
                                                                [DCT0-DCT6]

      ST3            IO_USBF.IO_ST3.hword     IO_USBF.IO_ST3.bit.SETUP
                                              IO_USBF.IO_ST3.bit.CFEND
                                              IO_USBF.IO_ST3.bit.SOF
                                              IO_USBF.IO_ST3.bit.SUSP
                                              IO_USBF.IO_ST3.bit.NACKOS

      ST4            IO_USBF.IO_ST4.hword     IO_USBF.IO_ST4.bit.FMR
                                                                [FMR0-FMR10]

      ST5            IO_USBF.IO_ST5.hword     IO_USBF.IO_ST5.bit.USBRESET
                                              IO_USBF.IO_ST5.bit.STSTALLx
                                                                 (x:0-3)
                                              IO_USBF.IO_ST5.bit.TRCVEND
                                              IO_USBF.IO_ST5.bit.TTRSEND

      RSIZE0         IO_USBF.IO_RSIZE0.hword  IO_USBF.IO_RSIZE0.bit.RSIZE0
                                                           [RSIZE00-RSIZE03]

      RSIZE1         IO_USBF.IO_RSIZE1.hword  IO_USBF.IO_RSIZE1.bit.RSIZE1
                                                           [RSIZE10-RSIZE16]

      CONT1          IO_USBF.IO_CONT1.hword   IO_USBF.IO_CONT1.bit.RESUM
                                              IO_USBF.IO_CONT1.bit.STALLx
                                                                   (x:0-3)
                                              IO_USBF.IO_CONT1.bit.CFGEN

      CONT2          IO_USBF.IO_CONT2.hword   IO_USBF.IO_CONT2.bit.INIx
                                                                   (x:1-3)
                                              IO_USBF.IO_CONT2.bit.INI0i
                                              IO_USBF.IO_CONT2.bit.INI0o

      CONT3          IO_USBF.IO_CONT3.hword   IO_USBF.IO_CONT3.bit.BFOKx
                                                                   (x:1-3)
                                              IO_USBF.IO_CONT3.bit.BFOK0i
                                              IO_USBF.IO_CONT3.bit.BFOK0o

      CONT4          IO_USBF.IO_CONT4.hword   IO_USBF.IO_CONT4.bit.FIFOBUSYx
                                                                   (x:1-3)
                                              IO_USBF.IO_CONT4.bit.FIFOBUSY0i
                                              IO_USBF.IO_CONT4.bit.FIFOBUSY0o

      CONT5          IO_USBF.IO_CONT5.hword   IO_USBF.IO_CONT5.bit.DFIFOBUSYx
                                                                   (x:1-2)

      CONT6          IO_USBF.IO_CONT6.hword   IO_USBF.IO_CONT6.bit.MDREQx
                                                                   (x:1-2)

      CONT7          IO_USBF.IO_CONT7.hword   IO_USBF.IO_CONT7.bit.MACKx
                                                                   (x:1-3)
                                              IO_USBF.IO_CONT7.bit.MACK0i
                                              IO_USBF.IO_CONT7.bit.MACK0o

      CONT8          IO_USBF.IO_CONT8.hword   IO_USBF.IO_CONT8.bit.MNACKx
                                                                   (x:1-3)
                                              IO_USBF.IO_CONT8.bit.MNACK0i
                                              IO_USBF.IO_CONT8.bit.MNACK0o

      CONT9          IO_USBF.IO_CONT9.hword   IO_USBF.IO_CONT9.bit.MUSBRESET
                                              IO_USBF.IO_CONT9.bit.MSTALLx
                                                                   (x:0-3)

      CONT10         IO_USBF.IO_CONT10.hword  IO_USBF.IO_CONT10.bit.MULLSETx
                                                                   (x:0,2,3)
                                              IO_USBF.IO_CONT10.bit.DMAMODE
                                              IO_USBF.IO_CONT10.bit.LSTDx
                                                                   (x:0,2,3)
                                              IO_USBF.IO_CONT10.bit.TRCNTEN
                                              IO_USBF.IO_CONT10.bit.TTCNTEN
                                              IO_USBF.IO_CONT10.bit.ODD

      TTSIZE         IO_USBF.IO_TTSIZE        none

      TRSIZE         IO_USBF.IO_TRSIZE        none

      RESET          IO_USBF.IO_RESET.hword   IO_USBF.IO_RESET.bit.SUSPEN
                                              IO_USBF.IO_RESET.bit.RESETX
    --------------------------------------------------------------------------

<<Memory stichk>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---------------+-------+---------------------------------------+
    |      PID      |       |               DATASIZE                | MSCR
    +---------------+-------+---------------------------------------+

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  INT  |  DRQ  |   -   |   -   |  RBE  |  RBF  |  TBE  |  TBF  | MSSR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-----------------------+
    |  RST  |  PWS  |  SIEN | DAKEN | NONCRC|         BSYCNT        | MSCNTR
    +-------+-------+-------+-------+-------+-----------------------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---------------------------------------------------------------+
    |                           RTDB[0:15]                          | MSRTDR
    +---------------------------------------------------------------+

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  RDY  |  SIF  |  DREQ |  PIN  |   -   |   -   |  CRC  |  TOE  | MSIDR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  INT  |  DREQ |  PIN  |   -   |   -   |   -   |   -   |   -   | MSIR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | XPIN3 | XPIN2 | XPIN1 | XPIN0 | POUT3 | POUT2 | POUT1 | POUT0 | MSPPDR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | PIEN3 | PIEN2 | PIEN1 | PIEN0 | POEN3 | POEN2 | POEN1 | POEN0 | MSPPCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      MSCR           IO_MEMS.IO_MSCR.hword    IO_MEMS.IO_MSCR.bit.PID
                                              IO_MEMS.IO_MSCR.bit.DATASIZE

      MSSR           IO_MEMS.IO_MSSR.byte     IO_MEMS.IO_MSSR.bit.INT
                                              IO_MEMS.IO_MSSR.bit.DRQ
                                              IO_MEMS.IO_MSSR.bit.RBE
                                              IO_MEMS.IO_MSSR.bit.RBF
                                              IO_MEMS.IO_MSSR.bit.TBE
                                              IO_MEMS.IO_MSSR.bit.TBF

      MSCNTR         IO_MEMS.IO_MSCNTR.byte   IO_MEMS.IO_MSCNTR.bit.RST
                                              IO_MEMS.IO_MSCNTR.bit.PWS
                                              IO_MEMS.IO_MSCNTR.bit.SIEN
                                              IO_MEMS.IO_MSCNTR.bit.DAKEN
                                              IO_MEMS.IO_MSCNTR.bit.NONCRC
                                              IO_MEMS.IO_MSCNTR.bit.BSYCNT

      MSRTDR         IO_MEMS.IO_MSRTDR        none

      MSIDR          IO_MEMS.IO_MSIDR.byte    IO_MEMS.IO_MSIDR.bit.RDY
                                              IO_MEMS.IO_MSIDR.bit.SIF
                                              IO_MEMS.IO_MSIDR.bit.DREQ
                                              IO_MEMS.IO_MSIDR.bit.PIN
                                              IO_MEMS.IO_MSIDR.bit.CRC
                                              IO_MEMS.IO_MSIDR.bit.TOE

      MSIR           IO_MEMS.IO_MSIR.byte     IO_MEMS.IO_MSIR.bit.INT
                                              IO_MEMS.IO_MSIR.bit.DREQ
                                              IO_MEMS.IO_MSIR.bit.PIN

      MSPPDR         IO_MEMS.IO_MSPPDR.byte   IO_MEMS.IO_MSPPDR.bit.XPINx
                                                                    (x:0-3)
                                              IO_MEMS.IO_MSPPDR.bit.POUTx
                                                                    (x:0-3)

      MSPPCR         IO_MEMS.IO_MSPPCR.byte   IO_MEMS.IO_MSPPCR.bit.PIENx
                                                                    (x:0-3)
                                              IO_MEMS.IO_MSPPCR.bit.POENx
                                                                    (x:0-3)
    --------------------------------------------------------------------------

<<OSDC>>

  - I/O register structure

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | FL| 0 | 0 | 0 |   |   |   |   | 0 | 0 |   |   |   |   |   |   | OSD_VADR
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                    |  AY2  |  AY0          |  AX4  |  AX2  |  AX0
                   AY3     AY1             AX5     AX3     AX1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | OSD_CD1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |  MUL  |  MBB  |  MS0  |  MM0  |  MB2  |  MB0  |  MC2  |  MC0
   MIT     MBL     MS1     MM1     MB3     MB1     MC3     MC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | MR| MG| 0 | 0 | 0 |   | M9| M8| M7| M6| M5| M4| M3| M2| M1| M0| OSD_CD2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                       M10

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 |   | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_RCD1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
               LHS     LW2  |  LW0  |  LFC  |  LFA  |  LF2  |  LF0
                           LW1     LFD     LFB     LF3     LF1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 |   |   |   |   |   | LD| LE|   |   | L3| L2| L1| L0| OSD_RCD2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
               LDS  |  LGY0 |  LGX0         |  LM0
                   LGY1    LGX1            LM1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   | 0 | 0 | 0 | 0 | OSD_SOC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                    |  UDS  |  DSP
                                   SDS     PDS
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   | 0 | 0 | 0 | 0 | OSD_SOC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  FM0  |  BT0  |  BD0
                           FM1     BT1     BD1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Y8| Y7| Y6| Y5| Y4| Y3| Y2| Y1| Y0| OSD_VDPC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | X8| X7| X6| X5| X4| X3| X2| X1| X0| OSD_HDPC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   | 0 |   |   |   | OSD_CVSC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                       HB2  |  HB0     HA2  |  HA0
                                           HB1             HA1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   | OSD_SBFCC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                    |  BH2  |  BH0  |  BS2  |  BS0
                                   BH3     BH1     BS3     BS1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   | OSD_THCC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  HCC  |  TCC2 |  TCC0 |  HCC2 |  HCC0
                           TCC     TCC3    TCC1    HCC3    HCC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   | OSD_GFCC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  GCC  |  GFC2 |  GFC0 |  GC2  |  GC0
                           GFC     GFC3    GFC1    GC3     GC1 

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |   | 0 |   |   | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_SBCC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |       |  PD0     PM10 |  PM8  |  PM6  |  PM4  |  PM2  |  PM0
   PCUT    PD1             PM9     PM7     PM5     PM3     PM1 
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   | U3| U2| U1| U0| OSD_SBCC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                       PH2  |  PH0
                                           PH1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |   | 0 |   |   | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_SPCC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |       |  SD0     SM10 |  SM8  |  SM6  |  SM4  |  SM2  |  SM0
   SCUT    SD1             SM9     SM7     SM5     SM3     SM1 
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   | 0 |   |   |   | 0 | 0 | 0 | 0 | OSD_SPCC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                               SBL     SH2  |  SH0
                                           SH1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   | OSD_SPCC3
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  SY8  |  SY6  |  SY4  |  SY2  |  SY0
                           SY9     SY7     SY5     SY3     SY1 
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   | OSD_SPCC4
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  SX8  |  SX6  |  SX4  |  SX2  |  SX0
                           SX9     SX7     SX5     SX3     SX1 

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | IN| 0 | FC| 0 | 0 | 0 | 0 | OSD_SYNCC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   | 0 | 0 | 0 |   |   | OSD_DCLKC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                    |  DR0  |  DP0          |  DC0
                                   DR1     DP1             DHRS
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   |   | OSD_DCLKC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                    |  DK10 |  DK8  |  DK6  |  DK4  |  DK2  |  DK0
                   DK11    DK9     DK7     DK5     DK3     DK1 
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   | OSD_DCLKC3
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                    |  VSL2 |  VSL0 |  CPB0 |  PDE
                                    VC     VSL1    CPB1    CPE 

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   | OSD_IOC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                                       OHX  |  OCX
                                                           OBX
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   | 0 | 0 | 0 | 0 |   |   | 0 | OSD_IOC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                               VHE  |                  IHX  | 
                                    HE                     IVX

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_DPC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      DYS10 |  DYS8 |  DYS6 |  DYS4 |  DYS2 |  DYS0
                           DYS9    DYS7    DYS5    DYS3    DYS1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_DPC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      DYE10 |  DYE8 |  DYE6 |  DYE4 |  DYE2 |  DYE0
                           DYE9    DYE7    DYE5    DYE3    DYE1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_DPC3
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      DXS10 |  DXS8 |  DXS6 |  DXS4 |  DXS2 |  DXS0
                           DXS9    DXS7    DXS5    DXS3    DXS1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_DPC4
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      DXE10 |  DXE8 |  DXE6 |  DXE4 |  DXE2 |  DXE0
                           DXE9    DXE7    DXE5    DXE3    DXE1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   | 0 | 0 | 0 | 0 | 0 |   |   |   | OSD_JRC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                       FIF  |  VIF                     FIE  |  VIE
                           LIF                             LIE
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   | 0 |   |   |   | 0 |   |   |   | OSD_PLTn
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                       PLR2 |  PLR0    PLG2 |  PLG0    PLB2 |  PLB0
                           PLR1            PLG1            PLB1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   | 0 | 0 | 0 |   | OSD_ACT1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                               DCK             DPD
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   | 0 |   |   |   | OSD_ACT2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                              OSDEN    FHO  |  ANO
                                                           DGO

  - Usable variable and member name

   --------------------------------------------------------------------------
    Register   At access in 1/2/4bytes     At access in bits
   --------------------------------------------------------------------------
    OSD_VADR   IO_OSDC.IO_OSD_VADR.hword   IO_OSDC.IO_OSD_VADR.bit.FL
                                           IO_OSDC.IO_OSD_VADR.bit.AY[AY0-AY3]
                                           IO_OSDC.IO_OSD_VADR.bit.AX[AX0-AX5]

    OSD_CD1    IO_OSDC.IO_OSD_CD1.hword    IO_OSDC.IO_OSD_CD1.bit.MIT
                                           IO_OSDC.IO_OSD_CD1.bit.MUL
                                           IO_OSDC.IO_OSD_CD1.bit.MBL
                                           IO_OSDC.IO_OSD_CD1.bit.MBB
                                           IO_OSDC.IO_OSD_CD1.bit.MS[MS0-MS1]
                                           IO_OSDC.IO_OSD_CD1.bit.MM[MM0-MM1]
                                           IO_OSDC.IO_OSD_CD1.bit.MB[MB0-MB3]
                                           IO_OSDC.IO_OSD_CD1.bit.MC[MC0-MC3]

    OSD_CD2    IO_OSDC.IO_OSD_CD2.hword    IO_OSDC.IO_OSD_CD2.bit.MR
                                           IO_OSDC.IO_OSD_CD2.bit.MG
                                           IO_OSDC.IO_OSD_CD2.bit.M[M0-M10]

    OSD_RCD1   IO_OSDC.IO_OSD_RCD1.hword   IO_OSDC.IO_OSD_RCD1.bit.LHS
                                           IO_OSDC.IO_OSD_RCD1.bit.LW[LW0-LW2]
                                           IO_OSDC.IO_OSD_RCD1.bit.LFCD
                                                                     [LFC-LFD]
                                           IO_OSDC.IO_OSD_RCD1.bit.LFAB
                                                                     [LFA-LFB]
                                           IO_OSDC.IO_OSD_RCD1.bit.LF[LF0-LF3]

    OSD_RCD2   IO_OSDC.IO_OSD_RCD2.hword   IO_OSDC.IO_OSD_RCD2.bit.LDS
                                           IO_OSDC.IO_OSD_RCD2.bit.LGY
                                                                  [LGY0-LGY1]
                                           IO_OSDC.IO_OSD_RCD2.bit.LGX
                                                                  [LGX0-LGX1]
                                           IO_OSDC.IO_OSD_RCD2.bit.LD
                                           IO_OSDC.IO_OSD_RCD2.bit.LE
                                           IO_OSDC.IO_OSD_RCD2.bit.LM[LM0-LM1]
                                           IO_OSDC.IO_OSD_RCD2.bit.L [L0-L3]

    OSD_SOC1   IO_OSDC.IO_OSD_SOC1.hword   IO_OSDC.IO_OSD_SOC1.bit.SDS
                                           IO_OSDC.IO_OSD_SOC1.bit.UDS
                                           IO_OSDC.IO_OSD_SOC1.bit.PDS
                                           IO_OSDC.IO_OSD_SOC1.bit.DSP

    OSD_SOC2   IO_OSDC.IO_OSD_SOC2.hword   IO_OSDC.IO_OSD_SOC2.bit.FM[FM0-FM1]
                                           IO_OSDC.IO_OSD_SOC2.bit.BT[BT0-BT1]
                                           IO_OSDC.IO_OSD_SOC2.bit.BD[BD0-BD1]

    OSD_VDPC   IO_OSDC.IO_OSD_VDPC.hword   IO_OSDC.IO_OSD_VDPC.bit.Y [Y0-Y8]

    OSD_HDPC   IO_OSDC.IO_OSD_HDPC.hword   IO_OSDC.IO_OSD_HDPC.bit.X [X0-X8]

    OSD_CVSC   IO_OSDC.IO_OSD_CVSC.hword   IO_OSDC.IO_OSD_CVSC.bit.HB[HB0-HB2]
                                           IO_OSDC.IO_OSD_CVSC.bit.HA[HA0-HA2]

    OSD_SBFCC  IO_OSDC.IO_OSD_SBFCC.hword  IO_OSDC.IO_OSD_SBFCC.bit.BH[BH0-BH3]
                                           IO_OSDC.IO_OSD_SBFCC.bit.BS[BS0-BS3]

    OSD_THCC   IO_OSDC.IO_OSD_THCC.hword   IO_OSDC.IO_OSD_THCC.bit.TCC
                                           IO_OSDC.IO_OSD_THCC.bit.HCC
                                           IO_OSDC.IO_OSD_THCC.bit.TCC03
                                                                  [TCC0-TCC3]
                                           IO_OSDC.IO_OSD_THCC.bit.HCC03
                                                                  [HCC0-HCC3]

    OSD_GFCC   IO_OSDC.IO_OSD_GFCC.hword   IO_OSDC.IO_OSD_GFCC.bit.GFC
                                           IO_OSDC.IO_OSD_GFCC.bit.GCC
                                           IO_OSDC.IO_OSD_GFCC.bit.GFC03
                                                                  [GFC0-GFC3]
                                           IO_OSDC.IO_OSD_GFCC.bit.GC
                                                                  [GC0-GC3]

    OSD_SBCC1  IO_OSDC.IO_OSD_SBCC1.hword  IO_OSDC.IO_OSD_SBCC1.bit.PCUT
                                           IO_OSDC.IO_OSD_SBCC1.bit.PD
                                                                   [PD0-PD1]
                                           IO_OSDC.IO_OSD_SBCC1.bit.PM
                                                                   [PM0-PM10]

    OSD_SBCC2  IO_OSDC.IO_OSD_SBCC2.hword  IO_OSDC.IO_OSD_SBCC2.bit.PH[PH0-PH2]
                                           IO_OSDC.IO_OSD_SBCC2.bit.U [U0-U3]

    OSD_SPCC1  IO_OSDC.IO_OSD_SPCC1.hword  IO_OSDC.IO_OSD_SPCC1.bit.SCUT
                                           IO_OSDC.IO_OSD_SPCC1.bit.SD
                                                                   [SD0-SD1]
                                           IO_OSDC.IO_OSD_SPCC1.bit.SM
                                                                   [SM0-SM10]

    OSD_SPCC2  IO_OSDC.IO_OSD_SPCC2.hword  IO_OSDC.IO_OSD_SPCC2.bit.SBL
                                           IO_OSDC.IO_OSD_SPCC2.bit.SH[SH0-SH2]

    OSD_SPCC3  IO_OSDC.IO_OSD_SPCC3.hword  IO_OSDC.IO_OSD_SPCC3.bit.SY[SY0-SY9]

    OSD_SPCC4  IO_OSDC.IO_OSD_SPCC4.hword  IO_OSDC.IO_OSD_SPCC4.bit.SX[SX0-SX9]

    OSD_SYNCC  IO_OSDC.IO_OSD_SYNCC.hword  IO_OSDC.IO_OSD_SYNCC.bit.IN
                                           IO_OSDC.IO_OSD_SYNCC.bit.FC

    OSD_DCLKC1 IO_OSDC.IO_OSD_DCLKC1.hword IO_OSDC.IO_OSD_DCLKC1.bit.DR
                                                                    [DR0-DR1]
                                           IO_OSDC.IO_OSD_DCLKC1.bit.DP
                                                                    [DP0-DP1]
                                           IO_OSDC.IO_OSD_DCLKC1.bit.DHRS
                                           IO_OSDC.IO_OSD_DCLKC1.bit.DCO

    OSD_DCLKC2 IO_OSDC.IO_OSD_DCLKC2.hword IO_OSDC.IO_OSD_DCLKC2.bit.DK
                                                                    [DK0-DK11]

    OSD_DCLKC3 IO_OSDC.IO_OSD_DCLKC3.hword IO_OSDC.IO_OSD_DCLKC3.bit.VC
                                           IO_OSDC.IO_OSD_DCLKC3.bit.VSL
                                                                    [VSL0-VSL2]
                                           IO_OSDC.IO_OSD_DCLKC3.bit.CPB
                                                                    [CPB0-CPB1]
                                           IO_OSDC.IO_OSD_DCLKC3.bit.CPE
                                           IO_OSDC.IO_OSD_DCLKC3.bit.PDE

    OSD_IOC1   IO_OSDC.IO_OSD_IOC1.hword   IO_OSDC.IO_OSD_IOC1.bit.OHX
                                           IO_OSDC.IO_OSD_IOC1.bit.OBX
                                           IO_OSDC.IO_OSD_IOC1.bit.OCX

    OSD_IOC2   IO_OSDC.IO_OSD_IOC2.hword   IO_OSDC.IO_OSD_IOC2.bit.VHE
                                           IO_OSDC.IO_OSD_IOC2.bit.HE
                                           IO_OSDC.IO_OSD_IOC2.bit.IHX
                                           IO_OSDC.IO_OSD_IOC2.bit.IVX

    OSD_DPC1   IO_OSDC.IO_OSD_DPC1.hword   IO_OSDC.IO_OSD_DPC1.bit.DYS
                                                                  [DYS0-DYS10]

    OSD_DPC2   IO_OSDC.IO_OSD_DPC2.hword   IO_OSDC.IO_OSD_DPC2.bit.DYE
                                                                  [DYE0-DYE10]

    OSD_DPC3   IO_OSDC.IO_OSD_DPC3.hword   IO_OSDC.IO_OSD_DPC3.bit.DXS
                                                                  [DXS0-DXS10]

    OSD_DPC4   IO_OSDC.IO_OSD_DPC4.hword   IO_OSDC.IO_OSD_DPC4.bit.DXE
                                                                  [DXE0-DXE10]

    OSD_JRC    IO_OSDC.IO_OSD_JRC.hword    IO_OSDC.IO_OSD_JRC.bit.FIF
                                           IO_OSDC.IO_OSD_JRC.bit.LIF
                                           IO_OSDC.IO_OSD_JRC.bit.VIF
                                           IO_OSDC.IO_OSD_JRC.bit.FIE
                                           IO_OSDC.IO_OSD_JRC.bit.LIE
                                           IO_OSDC.IO_OSD_JRC.bit.VIE

    OSD_PLRn   IO_OSDC.IO_OSD_PLRn.hword   IO_OSDC.IO_OSD_PLRn.bit.PLR
    (n:0 - 15)                                                    [PLR0-PLR2]
                                           IO_OSDC.IO_OSD_PLRn.bit.PLG
                                                                  [PLG0-PLG2]
                                           IO_OSDC.IO_OSD_PLRn.bit.PLB
                                                                  [PLB0-PLB2]

    OSD_ACT1   IO_OSDC.IO_OSD_ACT1.hword   IO_OSDC.IO_OSD_ACT1.bit.DCK
                                           IO_OSDC.IO_OSD_ACT1.bit.DPD

    OSD_ACT2   IO_OSDC.IO_OSD_ACT2.hword   IO_OSDC.IO_OSD_ACT2.bit.OSDEN
                                           IO_OSDC.IO_OSD_ACT2.bit.FHO
                                           IO_OSDC.IO_OSD_ACT2.bit.DGO
                                           IO_OSDC.IO_OSD_ACT2.bit.ANO
    --------------------------------------------------------------------------





















+-----------------------------------------------------------------------------+
|1. The contents of this document are subject to change without notice.       |
|   Customers are advised to consult with FUJITSU sales representatives       |
|   beforeordering.                                                           |
|2. The information and circuit diagrems in this document presented as        |
|   examples of semiconductor device applications, and are not intended to be |
|   incorporated in devices for actual use. Also FUJITSU is unable to assume  |
|   responsibility for infringement of any patent rights or other rights of   |
|   third parties arising from the use of this information or circuit         |
|   diagrams.                                                                 |
|3. The contents of this document may not be reproduced or copied without the |
|   permission of FUJITSU LIMITED.                                            |
|4. FUJITSU semiconductor devices are intended for use in standard            |
|   applications (computers, office automation and other office equipments,   |
|   industrial, communications, and measurement equipments, personal or       |
|   household devices, etc.).                                                 |
|   CAUTION:                                                                  |
|   Customers considering the use of our products in special applications     |
|   where failure or abnormal operation may directly affect human lives or    |
|   cause physical injury or property damage, or where extremely high levels  |
|   of reliability are demanded (such as aerospace systems, atomic energy     |
|   controls, sea floor repeaters, vehicle operating controls, medical        |
|   devices for life support, etc.) are requested to consult with FUJITSU     |
|   sales representatives before such use. The company will not be            |
|   responsible for damages arising from such use without prior approval.     |
|5. Any semiconductor devices have inherently a certain rate of failure. You  |
|   must protect against injury, damage or loss from such failures by         |
|   incorporating safety design measures into your facility and equipment     |
|   such as redundancy, fire protection, and prevention of over-current       |
|   levels and other abnormal operating conditions.                           |
|6. If any products described in this document represent goods or             |
|   technologies subject to certain restrictions on export under the Foreign  |
|   Exchange and Foreign Trade Control Law of Japan, the prior authorization  |
|   by japanese government should be required for export of those products    |
|   from Japan.                                                               |
+-----------------------------------------------------------------------------+
 (C)2002  FUJITSU LIMITED Printed in Japan
