                                                               +-------------+
                                                               | IO91310-01E |
                                                               +-------------+























                           SAMPLE I/O REGISTER FILES
                       FOR FR/FRex FAMILY MB91310 SERIES

                                 USERS MANUAL

                                FUJITSU LIMITED

                                 VERSION 1.0

Preface

  The sample I/O register files for MB91310 series declares and defines
  symbols, thereby enabling the I/O registersof the MB91310 series 
  to be handled as Asembler symbols.
  This manual describes the configuration of the I/O register files,
  symbol declaration and definition.




Items to note before using I/O register files

  - The I/O register files are intended for specific series of MB91310 series.
    Before applying these programs to any other series of MB91310 series,
    therefore, be sure to modify the I/O register files.

  - When a program for I/O register operation is coded, the I/O register
    access sequence and timing must be considered. Please refer to the
    related hardware manuals.

  - The I/O register files are provided as valuable aids in developing the
    application programs for MB91310 series. In practice, however, some of
    these programs may need be modified depending on the target system.
    Before using any of them, therefore, be sure to verify the actual
    operation of the program.

  - Fujitsu may assume no liability for errors in the I/O register files
    and no responsibility for correcting errors immediately even if they
    are found.




Reference manuals

  I/O register files for MB91310 series are made based on the
  following manuals.

    -  MB91310 LSI manual Prototype Version 1.2 2002.10.07
       (MB91V310lsi_rev1_2.pdf)

Contents

CHAPTER 1  CONFIGURATION OF I/O REGISTER FILES FOR MB91310 series

CHAPTER 2  USAGE OF I/O REGISTER FILES FOR MB91310 series

CHAPTER 3  DECLARATION OF I/O REGISTER DECLARATION FILES FOR MB91310 series

CHAPTER 4  VARIABLE AND MEMBER NAMES USED IN I/O REGISTER DECLARATION FILES
           FOR MB91310 series

CHAPTER 1  CONFIGURATION OF SAMPLE I/O REGISTER FILES FOR MB91310 series

 ${FETOOL}         (Directory set in environment variable FETOOL)
  +-lib
    +-911
      +-include
        +-sample
          +-mb91310
            +-_fr.h (I/O register declaration file)
            |
            +-_mb91310.h (I/O register declaration file for MB91310 series)
            +-_r91310.h  (I/O register structure declaration file
            |                                           for MB91310 series)
            |
            +-_fr_a.asm  (I/O register definition file)


  - I/O register declaration file

    This file declares all the associated I/O register symbols (symbols
    corresponding to I/O registers).
    Please include this file when coding a program that handles associated
    I/O registers.

  - I/O register declaration file for MB91310 series

    This file declares all the associated I/O register symbols
    for MB91310 series.

  - I/O register structure declaration file for MB91310 series

    This file declares all the structure types corresponding to I/O registers
    for MB91310 series.

  - I/O register definition file for each I/O register

    This file defines each the associated I/O register symbol and specifies
    arrangement address.


CHAPTER 2  USAGE OF I/O REGISTER FILES FOR MB91310 series

  (1) Please assemble the I/O register definition file with the CPU option
      of using MB number.

        example:  > fasm911s -cpu mb91*** _fr_a.asm

  (2) When you describe the application program which refers to the I/O
      registers, please include the I/O register declaration file.

        example:  #include "_fr.h"
                    .....
                    LDI:32  #_IO_PDR2,  R4
                    .....

  (3) Please compile the application program file with the CPU option of
      using MB number.

        example:  > fasm911s  -cpu mb91*** sample.asm

        Note: When the MB number of the specified CPU option cannot be used
              for the I/O register file, the following messages are output.

                #error "The I/O register file of the specified CPU option
                        does not exist"

  (4) Please link the relocatable load module and the application program
      object file.

        example:  > flnk911s -cpu mb91*** -o sample.abs _fr_a.obj sample.obj

CHAPTER 3  DECLARATION OF I/O REGISTER DECLARATION FILES FOR MB91310 series

  Each I/O register declaration file declares the symbols corresponding to
  I/O register names as follows:

  note:
    FR/FRex family assembler cannot access for bit type.

    - The I/O register symbols that must be accessed in 1, 2 or 4 bytes
      are declared in byte type.

    - Basically, each symbol name is declared in the form of the
      corresponding I/O  register name plus '_IO_'.
      (However, for access convenience, two or more I/O registers may be
       declared by one symbol name.)


  [Example]  Declaration for I/O register PDR0

    - I/O register structure

          7       6       5       4       3       2       1       0    bit No.
      +-------+-------+-------+-------+-------+-------+-------+-------+
      |  P07  |  P06  |  P05  |  P04  |  P03  |  P02  |  P01  |  P00  | PDR0
      +-------+-------+-------+-------+-------+-------+-------+-------+

    - Contents of declaration

        #macro io_pdr0 symbol
                BYTE_MEM
                STRUCT_TYPE_B
                        UCHARBIT(	P00, 1)
                        UCHARBIT(	P01, 1)
                        UCHARBIT(	P02, 1)
                        UCHARBIT(	P03, 1)
                        UCHARBIT(	P04, 1)
                        UCHARBIT(	P05, 1)
                        UCHARBIT(	P06, 1)
                        UCHARBIT(	P07, 1)
                STRUCT_TYPE_E(bit)
        #endm

        __IO_EXTERN  UNION_D(io_pdr0,   IO_PDR0)

    - Contents of macro spread

        [At I/O register define]                 [At I/O register declare]
                      .GLOBAL _IO_PDR0             .GLOBAL _IO_PDR0
        _IO_PDR0      .res.b  1

CHAPTER 4  VARIABLE AND MEMBER NAMES USED IN I/O REGISTER DECLARATION FILES
           FOR MB91310 series

<<I/O Ports>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  Pn7  |  Pn6  |  Pn5  |  Pn4  |  Pn3  |  Pn2  |  Pn1  |  Pn0  | PDRn,
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | I2CTST|   -   |   -   | I2CE4 | I2CE3 | I2CE2 | I2CE1 | I2CE0 | PFR0
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | UART3 | SCKE3 | UART2 | SCKE2 | UART1 | SCKE1 | UART0 | SCKE0 | PFR1
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TOE2 |  TOE1 |  TOE0 |   -   |   -   |   -   | UART4 | SCKE4 | PFR2
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TME3 |  TME2 |  TME1 |  TME0 | PPGE3 | PPGE2 | PPGE1 | PPGE0 | PFR3
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  MSE  |   -   |   -   |   -   |   -   |   -   |   -   |   -   | PFR4
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      PDRn(n:0-7)      _IO_PDRn               none

      DDRn(n:0-7)      _IO_PORT_IO_DDRn       none

      PFR0             _IO_PORT_IO_PFR0       none

      PFR1             _IO_PORT_IO_PFR1       none

      PFR2             _IO_PORT_IO_PFR2       none

      PFR3             _IO_PORT_IO_PFR3       none

      PFR4             _IO_PORT_IO_PFR4       none
    --------------------------------------------------------------------------
      Note: The following bits do not exist.

              PDR2,DDR2 : P26-P27
              PDR3,DDR3 : P37
              PDR6,DDR6 : P66-P67
              PDR7,DDR7 : P75-P77

<<A/D Converter>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   | 0 |   |   | ADCTH,
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ADCTL
                              |  STR  |  ASS2 |  ASS0 |       |  INTE
                             TRG     ASS3    ASS1    BUSY    INT 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | 0 | 0 | 0 | 0 | 0 | 0 | i9| i8| i7| i6| i5| i4| i3| i2| i1| i0| ADCH
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | 0 | 0 | 0 | 0 | 0 | 0 | d9| d8| d7| d6| d5| d4| d3| d2| d1| d0| ADATn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      ADCTH/ADCHL      _IO_ADCT               none

      ADCH             _IO_ADCH               none

      ADATn(n:0 - 9)   _IO_ADATn              none
    --------------------------------------------------------------------------

<<External Interrupt>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  EN7  |  EN6  |  EN5  |  EN4  |  EN3  |  EN2  |  EN1  |  EN0  | ENIR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  ER7  |  ER6  |  ER5  |  ER4  |  ER3  |  ER2  |  ER1  |  ER0  | EIRR
    +-------+-------+-------+-------+-------+-------+-------+-------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | ELVR
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  LA7  |  LA6  |  LA5  |  LA4  |  LA3  |  LA2  |  LA1  |  LA0
     LB7     LB6     LB5     LB4     LB3     LB2     LB1     LB0

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      ENIR             _IO_ENIR               none

      EIRR             _IO_EIRR               none

      ELVR             _IO_ELVR               none
    --------------------------------------------------------------------------

<<Delayed Interrupt Control Register>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |   -   |   -   |  DLYI | DICR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      DICR             _IO_DICR               none
    --------------------------------------------------------------------------

<<Interrupt Controller>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |  ICR4 |  ICR3 |  ICR2 |  ICR1 |  ICR0 | ICRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |MHALTI |   -   |   -   |  LVL4 |  LVL3 |  LVL2 |  LVL1 |  LVL0 | HRCL
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      ICRn(n:00 - 47)  _IO_ICR_n              none

      HRCL             _IO_HRCL               none
    --------------------------------------------------------------------------
      Note : ICR4 bits of ICRn(n:00-47) and LVL4 bit of HRCL are fixed at 1.
             You cannot write 0.

<<16-bit Reload Timer>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | - | - | - | - |   |   |   |   |   | - | - |   |   |   |   |   | TMCSRn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      |  CSL0 |  MOD1 |          RELD |   UF  |  TRG
                     CSL1    MOD2    MOD0            INTE    CNTE

      15                                                           0  bit No.
    +---------------------------------------------------------------+
    |                                                               | TMRn
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | TMRLRn
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      TMCSRn(n:0 - 2)  _IO_TMCSRn             none

      TMRn  (n:0 - 2)  _IO_TMRn               none

      TMRLRn(n:0 - 2)  _IO_TMRLRn             none
    --------------------------------------------------------------------------
      Note: Always write 0 to No 5,12,13 bit of TMCSRn.

<<UART>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  MD1  |  MD0  |   -   |   -   |  CS0  |   -   |   -   |   -   | SMRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  PEN  |    P  |  SBL  |   CL  |  A/D  |  REC  |  RXE  |  TXE  | SCRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   D7  |   D6  |   D5  |   D4  |   D3  |   D2  |   D1  |   D0  | SIDRn/
    +-------+-------+-------+-------+-------+-------+-------+-------+ SODRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   PE  |  ORE  |  FRE  |  RDRF |  TDRE |  BDS  |  RIE  |  TIE  | SSRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |   -   |   -   |   -   | DRCLn
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      SMRn(n:0 - 4)    _IO_SMRn               none

      SCRn(n:0 - 4)    _IO_SCRn               none

      SIDRn/           _IO_SIDRn              none
      SODRn(n:0 - 4)

      SSRn(n:0 - 4)    _IO_SSRn               none

      DRCLn(n:0 - 4)   _IO_DRCLn              none
    --------------------------------------------------------------------------
      Note: Always write 0 to bit No.1-2, 1 to bit No.4-5 of SMRn.

<<U-Timer>>

  - I/O register structure

      15                                                           0  bit No.
    +---------------------------------------------------------------+
    |                                                               | UTIMn/
    +---------------------------------------------------------------+ UTIMRn

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  UCC1 |   -   |   -   |  UTIE |  UNDR |  CLKS |  UTST |  UTCR | UTIMCn
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      UTIMn/           _IO_UTIMn              none
      UTIMRn(n:0 - 4)

      UTIMCn(n:0 - 4)  _IO_UTIMCn             none
    --------------------------------------------------------------------------
      Note: Always write 0 to CLKS bit of UTIMCn.

<<16bit PWC timer>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   | - | - |   |   |   |   | - | - |   |   |   |   | PWCC
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  INTE | OVFLE         |   ST  | TEST0   CSFL1 |  CSK2 |  CSK0
     INT     OVFL            MSKE   TEST1           CSFL0    CSK1
    +---------------------------------------------------------------+
    |                                                               | PWCD
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
      Register name  At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      PWCC              IO_PWCC               none

      PWCD              IO_PWCD               none
    --------------------------------------------------------------------------

<<IIC Interface>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  BER  |  BEIE |  SCC  |  MSS  |  ACK  |  GCAA |  INTE |  INT  | IBCRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   BB  |  RSC  |   AL  |  LRB  |  TRX  |  AAS  |  GCA  |  ADT  | IBSRn
    +-------+-------+-------+-------+-------+-------+-------+-------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    | - | - | - | - | - | - |   |   |   |   |   |   |   |   |   |   | ITBAn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                              |  TA8  |  TA6  |  TA4  |  TA2  |  TA0
                             TA9     TA7     TA5     TA3     TA1
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   | - | - | - | - |   |   |   |   |   |   |   |   |   |   | ITMKn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  RAL                  |  TM8  |  TM6  |  TM4  |  TM2  |  TM0
     ENTB                    TM9     TM7     TM5     TM3     TM1

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |  SA6  |  SA5  |  SA4  |  SA3  |  SA2  |  SA1  |  SA0  | ISBAn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  ENSB |  SM6  |  SM5  |  SM4  |  SM3  |  SM2  |  SM1  |  SM0  | ISMKn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   D7  |   D6  |   D5  |   D4  |   D3  |   D2  |   D1  |   D0  | IDARn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TEST |   -   |   EN  |  CS4  |  CS3  |  CS2  |  CS1  |  CS0  | ICCRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |   -   |   -   |  DBL  | IDBLn
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      IBCRn(n:0 - 3)   _IO_IBCRn              none

      IBSRn(n:0 - 3)   _IO_IBSRn              none

      ITBAn(n:0 - 3)   _IO_ITBAn              none

      ITMKn(n:0 - 3)   _IO_ITMKn              none

      ISBAn(n:0 - 3)   _IO_ISBAn              none

      ISMKn(n:0 - 3)   _IO_ISMKn              none

      IDARn(n:0 - 3)   _IO_IDARn              none

      ICCRn(n:0 - 3)   _IO_ICCRn              none

      IDBLn(n:0 - 3)   _IO_IDBLn              none
    --------------------------------------------------------------------------
      Note: Always write 0 to TEST bit and bit No.6 of ICCRn.

<<Multi function timer>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |  FCn1 |  FCn0 |  FnEN | TnLPCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  CPF  |   -   |  CPST |  CPED |  CPIE |  CPOV |  CPMD |  CPIS | TnCCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TCF  |  TSES |  TCC  |  TIE  |  CINV |  TCS2 |  TCS1 |  TCS0 | TnTCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |  TST2 |  TST2 |  MD1  |  MD0  |   ST  | TnR
    +-------+-------+-------+-------+-------+-------+-------+-------+

      15                                                          0   bit No.
    +---------------------------------------------------------------+
    |                                                               | TnDRR
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | TnCRR
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      TnLPCR(n:0 - 3)  _IO_TnLPCR             none

      TnCCR(n:0 - 3)   _IO_TnCCR              none

      TnTCR(n:0 - 3)   _IO_TnTCR              none

      TnR  (n:0 - 3)   _IO_TnR                none

      TnDRR(n:0 - 3)   _IO_TnDRR              none

      TnCRR(n:0 - 3)   _IO_TnCRR              none
    --------------------------------------------------------------------------
      Note: Always write 0 to TST1, TST2 bit of TnR.

<<PPG Timer>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   | - |   |   |   |   |   |   | - |   | PCNn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  STGR |  RTRG |  CKS0 |       |  EGS0 |  IRQF |  IRS0    OSEL
     CNTE    MDSE    CKS1    PGMS    EGS1    IREN    IRS1
    +---------------------------------------------------------------+
    |                                                               | PCSRn,
    +---------------------------------------------------------------+ PDUTn
    +---------------------------------------------------------------+
    |                                                               | PTMRn
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      PCNn (n:0 - 3)   _IO_PCNn               none

      PCSRn(n:0 - 3)   _IO_PCSRn              none

      PDUTn(n:0 - 3)   _IO_PDUTn              none

      PTMRn(n:0 - 3)   _IO_PTMRn              none
    --------------------------------------------------------------------------

<<DMAC>>

  - I/O register structure

      31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  bit No.
    +---+---+---+-------------------+---------------+---------------+-
    |   |   |   |       IS[4:0]     |   DDNO[3:0]   |    BLK[3:0]   |
    +---+---+---+-------------------+---------------+---------------+-
      |  PAUS |
     DENB    STRG
        15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
     -+---------------------------------------------------------------+
      |                           DTC[15:0]                           | DMACAn
     -+---------------------------------------------------------------+

      31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  bit No.
    +-------+-------+-------+---+---+---+---+---+---+---+-----------+-
    |  TYPE |  MOD  |   WS  |   |   |   |   |   |   |   |  DSS[2:0] |
    +-------+-------+-------+---+---+---+---+---+---+---+-----------+-
                              |  DADM |  SADR |  ERIE |
                             SADM    DTCR    DADR    EDIE
        15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
     -+-------------------------------+-------------------------------+
      |           SASZ[7:0]           |           DASZ[7:0]           | DMACBn
     -+-------------------------------+-------------------------------+

      31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  bit No.
    +---+---+---+---+---------------+---+---+---+---+---+---+---+---+-
    |   | - | - |   |   DMAH[3:0]   | - | - | - | - | - | - | - | - |
    +---+---+---+---+---------------+---+---+---+---+---+---+---+---+-
     DMAE        PM01
        15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | DMACR
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

      31                                                           0  bit No.
    +---------------------------------------------------------------+
    |                                                               | DMASAn,
    +---------------------------------------------------------------+ DMADAn

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      DMACAn(n:0 - 4)  _IO_DMACAn             none

      DMACBn(n:0 - 4)  _IO_DMACBn             none

      DMACR            _IO_DMACR              none

      DMASAn(n:0 - 4)  _IO_DMAD_IO_DMASAn     none

      DMADAn(n:0 - 4)  _IO_DMAD_IO_DMADAn     none
    --------------------------------------------------------------------------

<<Bit Search Module>>

  - I/O register structure

      31                                                           0  bit No.
    +---------------------------------------------------------------+
    |                                                               | BSD0
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | BSD1
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | BSDC
    +---------------------------------------------------------------+
    +---------------------------------------------------------------+
    |                                                               | BSRR
    +---------------------------------------------------------------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      BSD0             _IO_BSD0               none

      BSD1             _IO_BSD1               none

      BSDC             _IO_BSDC               none

      BSRR             _IO_BSRR               none
    --------------------------------------------------------------------------

<<Clock control unit>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  INIT |   -   |  WDOG |   -   |  SRST |   -   |  WT1  |  WT0  | RSRR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  STOP | SLEEP |  HIZ  |  SRST |  OS1  |  OS0  | OSCD2 | OSCD1 | STCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  TBIF |  TBIE |  TBC2 |  TBC1 |  TBC0 |   -   | SYNCR | SYNCS | TBCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   D7  |   D6  |   D5  |   D4  |   D3  |   D2  |   D1  |   D0  | CTBR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | PLL2S0| PLL1S2| PLL1S1| PLL1S0| PLL2EN| PLL1EN| CLKS1 | CLKS0 | CLKR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   D7  |   D6  |   D5  |   D4  |   D3  |   D2  |   D1  |   D0  | WPR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   B3  |   B2  |   B1  |   B0  |   P3  |   P2  |   P1  |   P0  | DIVR0
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   T3  |   T2  |   T1  |   T0  |   -   |   -   |   -   |   -   | DIVR1
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |   -   |   -   |   -   | OSCDS1| OSCCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      RSRR             _IO_CLK_IO_RSRR        none

      STCR             _IO_CLK_IO_STCR        none

      TBCR             _IO_CLK_IO_TBCR        none

      CTBR             _IO_CLK_IO_CTBR        none

      CLKR             _IO_CLK_IO_CLKR        none

      WPR              _IO_CLK_IO_WPR         none

      DIVR0            _IO_CLK_IO_DIVR0       none

      DIVR1            _IO_CLK_IO_DIVR1       none

      OSCCR            _IO_CLK_IO_OSCCR       none
    --------------------------------------------------------------------------

<<Watch timer>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  WIF  |  WIE  |   -   |   -   |   -   |  WS1  |  WS0  |  WCL  | WPCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      WPCR             _IO_WPCR               none
    --------------------------------------------------------------------------
      Note: Always write 0 to bit No.3-5 of WPCR.

<<Wait main oscilate timer>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  WIF  |  WIE  |   -   |   -   |   -   |  WS1  |  WS0  |  WCL  | OSCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      OSCR             _IO_OSCR               none
    --------------------------------------------------------------------------
      Note: Always write 0 to bit No.3-5 of OSCR.

<<External Bus Interface>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | ASRn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  A30  |  A28  |  A26  |  A24  |  A22  |  A20  |  A18  |  A16
     A31     A29     A27     A25     A23     A21     A19     A17
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | ACRn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  ASZ2 |  ASZ0 |  DBW0 |  BST0 |  PFEN |  LEND |  TYP2 |  TYP0
     ASZ3    ASZ1    DBW1    BST1    SREN    WREN    TYP3    TYP1
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | AWRn
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      |  W14  |  W12  |  W10  |  W08  |  W06  |  W04  |  W02  |  W00
     W15     W13     W11     W09     W07     W05     W03     W01

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  RYEn |  HLDn |  WRn1 |  WRn0 |  IWn3 |  IWn2 |  IWn1 |  IWn0 | IOWRn
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  CSE7 |  CSE6 |  CSE5 |  CSE4 |  CSE3 |  CSE2 |  CSE1 |  CSE0 | CSER
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  CHE7 |  CHE6 |  CHE5 |  CHE4 |  CHE3 |  CHE2 |  CHE1 |  CHE0 | CHER
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  BREN |  PSUS |  PCLR |reserve|  OHT1 |  OHT0 |  RWD1 |  RWD0 | TCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      ASRn(n:0 - 7)    _IO_EBUS_IO_ASRn       none

      ACRn(n:0 - 7)    _IO_EBUS_IO_ACRn       none

      AWRn(n:0 - 7)    _IO_EBUS_IO_AWRn       none

      IOWRn(n:0 - 2)   _IO_EBUS_IO_IOWRn      none

      CSER             _IO_EBUS_IO_CSER       none

      CHER             _IO_EBUS_IO_CHER       none

      TCR              _IO_EBUS_IO_TCR        none
    --------------------------------------------------------------------------
      Note: Always write 0 to reserved bits of TCR.

<<Mode Data>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   *   |   *   |   *   |   *   |   *   |  ROMA |  WTH1 |  WTH0 | MODR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      MODR             _IO_MODR               none
    --------------------------------------------------------------------------
      Note: Always write 0 to * bits.

<<Flush memory interface>>

  - I/O register structure

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |   -   |   -   |  RDY  |   -   |   WE  |   -   | FLCR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |   -   |   -   |  FAC1 |  FAC0 |   -   |  WTC1 |  WTC1 |  WTC0 | FLWC
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      FLCR             _IO_FLCR               none

      FLWC             _IO_FLWC               none
    --------------------------------------------------------------------------
      Note1: Always write 0 to bit No.2,4,7 and 1 to bit No.5,6 of FLCR.
      Note2: Always write 0 to bit No.3,6,7 of FLWC.

<<USB Host>>

  - I/O register structure

    31                              8   7   6   5   4   3   2   1   0   bit No.
  +-----------------------------------+-------------------------------+
  |                 -                 |              REV              | HR
  +-----------------------------------+-------------------------------+

    31                  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +-----------------------+---+---+---+-------+---+---+---+---+-------+
  |           -           |RWE|RWC| IR|  HCFS |BLE|CLE| IE|PLE|  CBSR | HC
  +-----------------------+---+---+---+-------+---+---+---+---+-------+

    31    18  17  16  15                            4   3   2   1   0   bit No.
  +---------+-------+---------------------------------+---+---+---+---+
  |         |  SOC  |                      -          |OCR|BLF|CLF|HCR| HCS
  +---------+-------+---------------------------------+---+---+---+---+

    31  30  29                          7   6   5   4   3   2   1   0   bit No.
  +---+---+-------------------------------+---+---+---+---+---+---+---+
  | --| OC|               -               |   |FNO| UE| RD| SF|WDH| SO| HIS
  +---+---+-------------------------------+---+---+---+---+---+---+---+
                                          RHSC
  +---+---+-------------------------------+---+---+---+---+---+---+---+
  |MIE| OC|               -               |   |FNO| UE| RD| SF|WDH| SO| HIE
  +---+---+-------------------------------+---+---+---+---+---+---+---+
                                          RHSC
  +---+---+-------------------------------+---+---+---+---+---+---+---+
  | ME| OC|               -               |   |FNO| UE| RD| SF|WDH| SO| HID
  +---+---+-------------------------------+---+---+---+---+---+---+---+
                                          RHSC

    31                              8   7                           0   bit No.
  +-----------------------------------+-------------------------------+
  |                HCCA               |               -               | HHCCA
  +-----------------------------------+-------------------------------+

    31                                          4   3               0   bit No.
  +-----------------------------------------------+-------------------+
  |                        PCED                   |         -         | HPCED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                        CHED                   |         -         | HCHED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                        CCED                   |         -         | HCCED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                        BHED                   |         -         | HBHED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                        BCED                   |         -         | HBCED
  +-----------------------------------------------+-------------------+
  +-----------------------------------------------+-------------------+
  |                         DH                    |         -         | HDH
  +-----------------------------------------------+-------------------+

    31  30                  16  15  14  13                          0   bit No.
  +---+-----------------------+-------+-------------------------------+
  |FIT|           FSMPS       |   -   |                 FI            | HFI
  +---+-----------------------+-------+-------------------------------+
    31  30                          14  13                          0   bit No.
  +---+-------------------------------+-------------------------------+
  |FRT|                  -            |                 FR            | HFR
  +---+-------------------------------+-------------------------------+
    31                    16  15                                    0   bit No.
  +-------------------------+-----------------------------------------+
  |               -         |                       FN                | HFN
  +-------------------------+-----------------------------------------+
    31                            14  13                            0   bit No.
  +---------------------------------+---------------------------------+
  |               -                 |               PS                | HPS
  +---------------------------------+---------------------------------+
    31                                    12  11                    0   bit No.
  +-----------------------------------------+-------------------------+
  |               -                         |             LST         | HLST
  +-----------------------------------------+-------------------------+

    31    24  23                      13  12  11  10  9   8   7     0   bit No.
  +---------+---------------------------+---+---+---+---+---+---------+
  |  POTPGT |              -            |   |   | DT|NPS|PSM|   NDP   | HRDA
  +---------+---------------------------+---+---+---+---+---+---------+
                                        NOCP OCPM
    31                    16  15                                    0   bit No.
  +-------------------------+-----------------------------------------+
  |          PPCM           |                       DR                | HRDB
  +-------------------------+-----------------------------------------+

    31  30        18  17  16  15  14                        2   1   0   bit No.
  +---+-------------+---+---+---+-----------------------------+---+---+
  |   |      -      |   |   |   |                -            |OCI|LPS| HRS
  +---+-------------+---+---+---+-----------------------------+---+---+
   CWRE             OCIC LPSC DRWE

    31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16      bit No.
  +-------------------------------------------+---+---+---+---+---+-
  |                       -                   |   |   |   |   |CSC| 
  +-------------------------------------------+---+---+---+---+---+-
                                               PRSC |  PSSC |
                                                   OCIC    PESC
        15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
     -+-----------------------+---+---+-----------+---+---+---+---+---+
      |           -           |   |PPS|     -     |PRS|   |PSS|PES|CCS| HRPSn
     -+-----------------------+---+---+-----------+---+---+---+---+---+
                              LSDA                    POCI

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      HR               _IO_USBH_IO_HR         none

      HC               _IO_USBH_IO_HC         none

      HCS              _IO_USBH_IO_HCS        none

      HIS              _IO_USBH_IO_HIS        none

      HIE              _IO_USBH_IO_HIE        none

      HID              _IO_USBH_IO_HID        none

      HHCCA            _IO_USBH_IO_HHCCA      none

      HPCED            _IO_USBH_IO_HPCED      none

      HCHED            _IO_USBH_IO_HCHED      none

      HCCED            _IO_USBH_IO_HCCED      none

      HBHED            _IO_USBH_IO_HBHED      none

      HBCED            _IO_USBH_IO_HBCED      none

      HDH              _IO_USBH_IO_HDH        none

      HFI              _IO_USBH_IO_HFI        none

      HFR              _IO_USBH_IO_HFR        none

      HFN              _IO_USBH_IO_HFN        none

      HPS              _IO_USBH_IO_HPS        none

      HLST             _IO_USBH_IO_HLST       none

      HRDA             _IO_USBH_IO_HRDA       none

      HRDB             _IO_USBH_IO_HRDB       none

      HRS              _IO_USBH_IO_HRS        none

      HRPSn(n:1 - 2)   _IO_USBH_IO_HRPSn      none
    --------------------------------------------------------------------------

<<USB Function>>

  - I/O register structure

      15                                                          0   bit No.
    +---------------------------------------------------------------+
    |                                                               | FIFO0o,
    +---------------------------------------------------------------+ FIFO0i
    +---------------------------------------------------------------+
    |                                                               | FIFOn
    +---------------------------------------------------------------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   | N | A | N | A | N | A | N | A | N | A | 
    |   |   |   |   |   |   | A | C | A | C | A | C | A | C | A | C | 
    | - | - | - | - | - | - | C | K | C | K | C | K | C | K | C | K | ST1
    |   |   |   |   |   |   | K | 3 | K | 2 | K | 1 | K | 0 | K | 0 | 
    |   |   |   |   |   |   | 3 |   | 2 |   | 1 |   | 0 | i | 0 | o | 
    |   |   |   |   |   |   |   |   |   |   |   |   | i |   | o |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   | D | D | D | D | D | D | D | 
    | - | - | - | - | - | - | - | - | - | C | C | C | C | C | C | C | 
    |   |   |   |   |   |   |   |   |   | T | T | T | T | T | T | T | ST2
    |   |   |   |   |   |   |   |   |   | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | S | C | S | S | N | 
    |   |   |   |   |   |   |   |   |   |   |   | E | F | O | U | A | 
    | - | - | - | - | - | - | - | - | - | - | - | T | E | F | S | C | ST3
    |   |   |   |   |   |   |   |   |   |   |   | U | N |   | F | K | 
    |   |   |   |   |   |   |   |   |   |   |   | P | D |   |   | O | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | S | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   | F | F | F | F | F | F | F | F | F | F | F | 
    |   |   |   |   |   | M | M | M | M | M | M | M | M | M | M | M | 
    | - | - | - | - | - | R | R | R | R | R | R | R | R | R | R | R | ST4
    |   |   |   |   |   | 1 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
    |   |   |   |   |   | 0 |   |   |   |   |   |   |   |   |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   | U |   |   |   |   |   | S | S | S | S | T | T | 
    |   |   |   |   | S |   |   |   |   |   | T | T | T | T | R | T | 
    |   |   |   |   | B |   |   |   |   |   | S | S | S | S | C | R | 
    | - | - | - | - | R | - | - | - | - | - | T | T | T | T | V | S | ST5
    |   |   |   |   | E |   |   |   |   |   | A | A | A | A | E | E | 
    |   |   |   |   | S |   |   |   |   |   | L | L | L | L | N | N | 
    |   |   |   |   | E |   |   |   |   |   | L | L | L | L | D | D | 
    |   |   |   |   | T |   |   |   |   |   | 3 | 2 | 1 | 0 |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   | R | R | R | R | 
    |   |   |   |   |   |   |   |   |   |   |   |   | S | S | S | S | 
    |   |   |   |   |   |   |   |   |   |   |   |   | I | I | I | I | 
    | - | - | - | - | - | - | - | - | - | - | - | - | Z | Z | Z | Z | RSIZE0
    |   |   |   |   |   |   |   |   |   |   |   |   | E | E | E | E | 
    |   |   |   |   |   |   |   |   |   |   |   |   | 0 | 0 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   | R | R | R | R | R | R | R | 
    |   |   |   |   |   |   |   |   |   | S | S | S | S | S | S | S | 
    |   |   |   |   |   |   |   |   |   | I | I | I | I | I | I | I | 
    | - | - | - | - | - | - | - | - | - | Z | Z | Z | Z | Z | Z | Z | RSIZE1
    |   |   |   |   |   |   |   |   |   | E | E | E | E | E | E | E | 
    |   |   |   |   |   |   |   |   |   | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 
    |   |   |   |   |   |   |   |   |   | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   | R |   |   |   |   |   | S | S | S | S | C | 
    |   |   |   |   |   | E |   |   |   |   |   | T | T | T | T | F | 
    |   |   |   |   |   | S |   |   |   |   |   | A | A | A | A | G | 
    | - | - | - | - | - | U | - | - | - | - | - | L | L | L | L | E | CONT1
    |   |   |   |   |   | M |   |   |   |   |   | L | L | L | L | N | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | I | I | I | I | I | 
    |   |   |   |   |   |   |   |   |   |   |   | N | N | N | N | N | 
    | - | - | - | - | - | - | - | - | - | - | - | I | I | I | I | I | CONT2
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | B | B | B | B | B | 
    |   |   |   |   |   |   |   |   |   |   |   | F | F | F | F | F | 
    | - | - | - | - | - | - | - | - | - | - | - | O | O | O | O | O | CONT3
    |   |   |   |   |   |   |   |   |   |   |   | K | K | K | K | K | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | B | B | B | B | B | 
    |   |   |   |   |   |   |   |   |   |   |   | I | I | I | I | I | 
    |   |   |   |   |   |   |   |   |   |   |   | F | F | F | F | F | 
    |   |   |   |   |   |   |   |   |   |   |   | O | O | O | O | O | 
    | - | - | - | - | - | - | - | - | - | - | - | B | B | B | B | B | CONT3
    |   |   |   |   |   |   |   |   |   |   |   | U | U | U | U | U | 
    |   |   |   |   |   |   |   |   |   |   |   | S | S | S | S | S | 
    |   |   |   |   |   |   |   |   |   |   |   | Y | Y | Y | Y | Y | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | F | F | F | F | F | 
    |   |   |   |   |   |   |   |   |   |   |   | I | I | I | I | I | 
    |   |   |   |   |   |   |   |   |   |   |   | F | F | F | F | F | 
    |   |   |   |   |   |   |   |   |   |   |   | O | O | O | O | O | 
    | - | - | - | - | - | - | - | - | - | - | - | B | B | B | B | B | CONT4
    |   |   |   |   |   |   |   |   |   |   |   | U | U | U | U | U | 
    |   |   |   |   |   |   |   |   |   |   |   | S | S | S | S | S | 
    |   |   |   |   |   |   |   |   |   |   |   | Y | Y | Y | Y | Y | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   | D | D |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | I | I |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | F | F |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | O | O |   |   | 
    | - | - | - | - | - | - | - | - | - | - | - | - | B | B | - | - | CONT5
    |   |   |   |   |   |   |   |   |   |   |   |   | U | U |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | S | S |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | Y | Y |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | 2 | 1 |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   | M | M |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | D | D |   |   | 
    | - | - | - | - | - | - | - | - | - | - | - | - | R | R | - | - | CONT6
    |   |   |   |   |   |   |   |   |   |   |   |   | E | E |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | Q | Q |   |   | 
    |   |   |   |   |   |   |   |   |   |   |   |   | 2 | 1 |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | M | M | M | M | M | 
    |   |   |   |   |   |   |   |   |   |   |   | A | A | A | A | A | 
    | - | - | - | - | - | - | - | - | - | - | - | C | C | C | C | C | CONT7
    |   |   |   |   |   |   |   |   |   |   |   | K | K | K | K | K | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   | M | M | M | M | M | 
    |   |   |   |   |   |   |   |   |   |   |   | N | N | N | N | N | 
    |   |   |   |   |   |   |   |   |   |   |   | A | A | A | A | A | 
    | - | - | - | - | - | - | - | - | - | - | - | C | C | C | C | C | CONT8
    |   |   |   |   |   |   |   |   |   |   |   | K | K | K | K | K | 
    |   |   |   |   |   |   |   |   |   |   |   | 3 | 2 | 1 | 0 | 0 | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | i | o | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   | M |   |   |   |   | M | M | M | M | 
    |   |   |   |   |   |   |   | U |   |   |   |   | S | S | S | S | 
    |   |   |   |   |   |   |   | S |   |   |   |   | T | T | T | T | 
    |   |   |   |   |   |   |   | B |   |   |   |   | A | A | A | A | 
    | - | - | - | - | - | - | - | R | - | - | - | - | L | L | L | L | CONT9
    |   |   |   |   |   |   |   | E |   |   |   |   | L | L | L | L | 
    |   |   |   |   |   |   |   | S |   |   |   |   | 3 | 2 | 1 | 0 | 
    |   |   |   |   |   |   |   | E |   |   |   |   |   |   |   |   | 
    |   |   |   |   |   |   |   | T |   |   |   |   |   |   |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   | N | N | N | D |   | L | L | L | T | T | O |   | 
    |   |   |   |   | U | U | U | M |   | S | S | S | R | T | D |   | 
    |   |   |   |   | L | L | L | A |   | T | T | T | C | C | D |   | 
    | - | - | - | - | L | L | L | M | - | D | D | D | N | N |   | - | CONT10
    |   |   |   |   | S | S | S | O |   | 3 | 2 | 0 | T | T |   |   | 
    |   |   |   |   | E | E | E | D |   |   |   |   | E | E |   |   | 
    |   |   |   |   | T | T | T | E |   |   |   |   | N | N |   |   | 
    |   |   |   |   | 3 | 2 | 0 |   |   |   |   |   |   |   |   |   | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

      15                                                          0   bit No.
    +----------------------------------------------------------------+
    |                                                               | TTSIZE
    +---------------------------------------------------------------+
    +----------------------------------------------------------------+
    |                                                               | TRSIZE
    +---------------------------------------------------------------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | S | R | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | U | E | 
    | - | - | - | - | - | - | - | - | - | - | - | - | - | - | S | S | RESET
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | P | E | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | E | T | 
    |   |   |   |   |   |   |   |   |   |   |   |   |   |   | N | X | 
    +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      FIFO0o         _IO_USBF_IO_FIFO0o       none
      FIFO0i         _IO_USBF_IO_FIFO0i       none
      FIFOn(n:1 - 3) _IO_USBF_IO_FIFOn        none

      ST1            _IO_USBF_IO_ST1          none
      ST2            _IO_USBF_IO_ST2          none
      ST3            _IO_USBF_IO_ST3          none
      ST4            _IO_USBF_IO_ST4          none
      ST5            _IO_USBF_IO_ST5          none

      RSIZE0         _IO_USBF_IO_RSIZE0       none
      RSIZE1         _IO_USBF_IO_RSIZE1       none

      CONT1          _IO_USBF_IO_CONT1        none
      CONT2          _IO_USBF_IO_CONT2        none
      CONT3          _IO_USBF_IO_CONT3        none
      CONT4          _IO_USBF_IO_CONT4        none
      CONT5          _IO_USBF_IO_CONT5        none
      CONT6          _IO_USBF_IO_CONT6        none
      CONT7          _IO_USBF_IO_CONT7        none
      CONT8          _IO_USBF_IO_CONT8        none
      CONT9          _IO_USBF_IO_CONT9        none
      CONT10         _IO_USBF_IO_CONT10       none

      TTSIZE         _IO_USBF_IO_TTSIZE       none
      TRSIZE         _IO_USBF_IO_TRSIZE       none

      RESET          _IO_USBF_IO_RESET        none
    --------------------------------------------------------------------------

<<Memory stichk>>

  - I/O register structure

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---------------+-------+---------------------------------------+
    |      PID      |       |               DATASIZE                | MSCR
    +---------------+-------+---------------------------------------+

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  INT  |  DRQ  |   -   |   -   |  RBE  |  RBF  |  TBE  |  TBF  | MSSR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-----------------------+
    |  RST  |  PWS  |  SIEN | DAKEN | NONCRC|         BSYCNT        | MSCNTR
    +-------+-------+-------+-------+-------+-----------------------+

      15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
    +---------------------------------------------------------------+
    |                           RTDB[0:15]                          | MSRTDR
    +---------------------------------------------------------------+

        7       6       5       4       3       2       1       0     bit No.
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  RDY  |  SIF  |  DREQ |  PIN  |   -   |   -   |  CRC  |  TOE  | MSIDR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    |  INT  |  DREQ |  PIN  |   -   |   -   |   -   |   -   |   -   | MSIR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | XPIN3 | XPIN2 | XPIN1 | XPIN0 | POUT3 | POUT2 | POUT1 | POUT0 | MSPPDR
    +-------+-------+-------+-------+-------+-------+-------+-------+
    +-------+-------+-------+-------+-------+-------+-------+-------+
    | PIEN3 | PIEN2 | PIEN1 | PIEN0 | POEN3 | POEN2 | POEN1 | POEN0 | MSPPCR
    +-------+-------+-------+-------+-------+-------+-------+-------+

  - Usable variable and member name

    --------------------------------------------------------------------------
     Register name   At access in 1/2/4bytes  At access in bits
    --------------------------------------------------------------------------
      MSCR           _IO_MEMS_IO_MSCR         none

      MSSR           _IO_MEMS_IO_MSSR         none

      MSCNTR         _IO_MEMS_IO_MSCNTR       none

      MSRTDR         _IO_MEMS_IO_MSRTDR       none

      MSIDR          _IO_MEMS_IO_MSIDR        none

      MSIR           _IO_MEMS_IO_MSIR         none

      MSPPDR         _IO_MEMS_IO_MSPPDR       none

      MSPPCR         _IO_MEMS_IO_MSPPCR       none
    --------------------------------------------------------------------------

<<OSDC>>

  - I/O register structure

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | FL| 0 | 0 | 0 |   |   |   |   | 0 | 0 |   |   |   |   |   |   | OSD_VADR
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                    |  AY2  |  AY0          |  AX4  |  AX2  |  AX0
                   AY3     AY1             AX5     AX3     AX1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   | OSD_CD1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |  MUL  |  MBB  |  MS0  |  MM0  |  MB2  |  MB0  |  MC2  |  MC0
   MIT     MBL     MS1     MM1     MB3     MB1     MC3     MC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | MR| MG| 0 | 0 | 0 |   | M9| M8| M7| M6| M5| M4| M3| M2| M1| M0| OSD_CD2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                       M10

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 |   | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_RCD1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
               LHS     LW2  |  LW0  |  LFC  |  LFA  |  LF2  |  LF0
                           LW1     LFD     LFB     LF3     LF1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 |   |   |   |   |   | LD| LE|   |   | L3| L2| L1| L0| OSD_RCD2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
               LDS  |  LGY0 |  LGX0         |  LM0
                   LGY1    LGX1            LM1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   | 0 | 0 | 0 | 0 | OSD_SOC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                    |  UDS  |  DSP
                                   SDS     PDS
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   | 0 | 0 | 0 | 0 | OSD_SOC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  FM0  |  BT0  |  BD0
                           FM1     BT1     BD1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Y8| Y7| Y6| Y5| Y4| Y3| Y2| Y1| Y0| OSD_VDPC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | X8| X7| X6| X5| X4| X3| X2| X1| X0| OSD_HDPC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   | 0 |   |   |   | OSD_CVSC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                       HB2  |  HB0     HA2  |  HA0
                                           HB1             HA1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   | OSD_SBFCC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                    |  BH2  |  BH0  |  BS2  |  BS0
                                   BH3     BH1     BS3     BS1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   | OSD_THCC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  HCC  |  TCC2 |  TCC0 |  HCC2 |  HCC0
                           TCC     TCC3    TCC1    HCC3    HCC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   | OSD_GFCC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  GCC  |  GFC2 |  GFC0 |  GC2  |  GC0
                           GFC     GFC3    GFC1    GC3     GC1 

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |   | 0 |   |   | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_SBCC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |       |  PD0     PM10 |  PM8  |  PM6  |  PM4  |  PM2  |  PM0
   PCUT    PD1             PM9     PM7     PM5     PM3     PM1 
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   | U3| U2| U1| U0| OSD_SBCC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                       PH2  |  PH0
                                           PH1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |   | 0 |   |   | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_SPCC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    |       |  SD0     SM10 |  SM8  |  SM6  |  SM4  |  SM2  |  SM0
   SCUT    SD1             SM9     SM7     SM5     SM3     SM1 
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   | 0 |   |   |   | 0 | 0 | 0 | 0 | OSD_SPCC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                               SBL     SH2  |  SH0
                                           SH1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   | OSD_SPCC3
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  SY8  |  SY6  |  SY4  |  SY2  |  SY0
                           SY9     SY7     SY5     SY3     SY1 
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   | OSD_SPCC4
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                            |  SX8  |  SX6  |  SX4  |  SX2  |  SX0
                           SX9     SX7     SX5     SX3     SX1 

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | IN| 0 | FC| 0 | 0 | 0 | 0 | OSD_SYNCC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   | 0 | 0 | 0 |   |   | OSD_DCLKC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                    |  DR0  |  DP0          |  DC0
                                   DR1     DP1             DHRS
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   |   | OSD_DCLKC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                    |  DK10 |  DK8  |  DK6  |  DK4  |  DK2  |  DK0
                   DK11    DK9     DK7     DK5     DK3     DK1 
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   | OSD_DCLKC3
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                    |  VSL2 |  VSL0 |  CPB0 |  PDE
                                    VC     VSL1    CPB1    CPE 

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   |   | OSD_IOC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                                       OHX  |  OCX
                                                           OBX
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |   | 0 | 0 | 0 | 0 |   |   | 0 | OSD_IOC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                               VHE  |                  IHX  | 
                                    HE                     IVX

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_DPC1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      DYS10 |  DYS8 |  DYS6 |  DYS4 |  DYS2 |  DYS0
                           DYS9    DYS7    DYS5    DYS3    DYS1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_DPC2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      DYE10 |  DYE8 |  DYE6 |  DYE4 |  DYE2 |  DYE0
                           DYE9    DYE7    DYE5    DYE3    DYE1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_DPC3
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      DXS10 |  DXS8 |  DXS6 |  DXS4 |  DXS2 |  DXS0
                           DXS9    DXS7    DXS5    DXS3    DXS1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   |   |   |   |   |   |   |   |   | OSD_DPC4
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                      DXE10 |  DXE8 |  DXE6 |  DXE4 |  DXE2 |  DXE0
                           DXE9    DXE7    DXE5    DXE3    DXE1

    15  14  13  12  11  10  9   8   7   6   5   4   3   2   1   0   bit No.
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   | 0 | 0 | 0 | 0 | 0 |   |   |   | OSD_JRC
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                       FIF  |  VIF                     FIE  |  VIE
                           LIF                             LIE
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 |   |   |   | 0 |   |   |   | 0 |   |   |   | OSD_PLTn
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                       PLR2 |  PLR0    PLG2 |  PLG0    PLB2 |  PLB0
                           PLR1            PLG1            PLB1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   | 0 | 0 | 0 |   | OSD_ACT1
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                               DCK             DPD
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   | 0 |   |   |   | OSD_ACT2
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
                                              OSDEN    FHO  |  ANO
                                                           DGO

  - Usable variable and member name

   --------------------------------------------------------------------------
    Register   At access in 1/2/4bytes     At access in bits
   --------------------------------------------------------------------------
    OSD_VADR   _IO_OSDC_IO_OSD_VADR        none

    OSD_CD1    _IO_OSDC_IO_OSD_CD1         none
    OSD_CD2    _IO_OSDC_IO_OSD_CD2         none

    OSD_RCD1   _IO_OSDC_IO_OSD_RCD1        none
    OSD_RCD2   _IO_OSDC_IO_OSD_RCD2        none

    OSD_SOC1   _IO_OSDC_IO_OSD_SOC1        none
    OSD_SOC2   _IO_OSDC_IO_OSD_SOC2        none

    OSD_VDPC   _IO_OSDC_IO_OSD_VDPC        none
    OSD_HDPC   _IO_OSDC_IO_OSD_HDPC        none

    OSD_CVSC   _IO_OSDC_IO_OSD_CVSC        none

    OSD_SBFCC  _IO_OSDC_IO_OSD_SBFCC       none

    OSD_THCC   _IO_OSDC_IO_OSD_THCC        none

    OSD_GFCC   _IO_OSDC_IO_OSD_GFCC        none

    OSD_SBCC1  _IO_OSDC_IO_OSD_SBCC1       none
    OSD_SBCC2  _IO_OSDC_IO_OSD_SBCC2       none

    OSD_SPCC1  _IO_OSDC_IO_OSD_SPCC1       none
    OSD_SPCC2  _IO_OSDC_IO_OSD_SPCC2       none
    OSD_SPCC3  _IO_OSDC_IO_OSD_SPCC3       none
    OSD_SPCC4  _IO_OSDC_IO_OSD_SPCC4       none

    OSD_SYNCC  _IO_OSDC_IO_OSD_SYNCC       none

    OSD_DCLKC1 _IO_OSDC_IO_OSD_DCLKC1      none
    OSD_DCLKC2 _IO_OSDC_IO_OSD_DCLKC2      none
    OSD_DCLKC3 _IO_OSDC_IO_OSD_DCLKC3      none

    OSD_IOC1   _IO_OSDC_IO_OSD_IOC1        none
    OSD_IOC2   _IO_OSDC_IO_OSD_IOC2        none

    OSD_DPC1   _IO_OSDC_IO_OSD_DPC1        none
    OSD_DPC2   _IO_OSDC_IO_OSD_DPC2        none
    OSD_DPC3   _IO_OSDC_IO_OSD_DPC3        none
    OSD_DPC4   _IO_OSDC_IO_OSD_DPC4        none

    OSD_JRC    _IO_OSDC_IO_OSD_JRC         none

    OSD_PLRn   _IO_OSDC_IO_OSD_PLRn        none
    (n:0 - 15)

    OSD_ACT1   _IO_OSDC_IO_OSD_ACT1        none
    OSD_ACT2   _IO_OSDC_IO_OSD_ACT2        none
    --------------------------------------------------------------------------





















+-----------------------------------------------------------------------------+
|1. The contents of this document are subject to change without notice.       |
|   Customers are advised to consult with FUJITSU sales representatives       |
|   beforeordering.                                                           |
|2. The information and circuit diagrems in this document presented as        |
|   examples of semiconductor device applications, and are not intended to be |
|   incorporated in devices for actual use. Also FUJITSU is unable to assume  |
|   responsibility for infringement of any patent rights or other rights of   |
|   third parties arising from the use of this information or circuit         |
|   diagrams.                                                                 |
|3. The contents of this document may not be reproduced or copied without the |
|   permission of FUJITSU LIMITED.                                            |
|4. FUJITSU semiconductor devices are intended for use in standard            |
|   applications (computers, office automation and other office equipments,   |
|   industrial, communications, and measurement equipments, personal or       |
|   household devices, etc.).                                                 |
|   CAUTION:                                                                  |
|   Customers considering the use of our products in special applications     |
|   where failure or abnormal operation may directly affect human lives or    |
|   cause physical injury or property damage, or where extremely high levels  |
|   of reliability are demanded (such as aerospace systems, atomic energy     |
|   controls, sea floor repeaters, vehicle operating controls, medical        |
|   devices for life support, etc.) are requested to consult with FUJITSU     |
|   sales representatives before such use. The company will not be            |
|   responsible for damages arising from such use without prior approval.     |
|5. Any semiconductor devices have inherently a certain rate of failure. You  |
|   must protect against injury, damage or loss from such failures by         |
|   incorporating safety design measures into your facility and equipment     |
|   such as redundancy, fire protection, and prevention of over-current       |
|   levels and other abnormal operating conditions.                           |
|6. If any products described in this document represent goods or             |
|   technologies subject to certain restrictions on export under the Foreign  |
|   Exchange and Foreign Trade Control Law of Japan, the prior authorization  |
|   by japanese government should be required for export of those products    |
|   from Japan.                                                               |
+-----------------------------------------------------------------------------+
 (C)2002  FUJITSU LIMITED Printed in Japan
