//------------------------------------------------------------------------------
//
//  lynx_dvi.v : Spartan3A dvi display test top module
//
//  LICENSE : "as-is"
//  copyright (C) 2006, TakeshiNagashima caramelgate@gmail.com
//------------------------------------------------------------------------------
//  2009/mar/03 release 0.0  xilinx sp3a
//       aug/17 release 0.0a HDL xc-303/sp3an50 + CQ BLANCA
//       aug/24 release 0.1  lynx-sp3an50
//
//------------------------------------------------------------------------------

module lynx_dvi(
//--------------------------------------------------------------
//  port

	output			DVI_TX0_N,					// out   [DVI] ch0-n tmds33(CML)/lvds
	output			DVI_TX0_P,					// out   [DVI] ch0-p tmds33(CML)/lvds
	output			DVI_TX1_N,					// out   [DVI] ch1-n tmds33(CML)/lvds
	output			DVI_TX1_P,					// out   [DVI] ch1-p tmds33(CML)/lvds
	output			DVI_TX2_N,					// out   [DVI] ch2-n tmds33(CML)/lvds
	output			DVI_TX2_P,					// out   [DVI] ch2-p tmds33(CML)/lvds
	output			DVI_TXC_N,					// out   [DVI] clk-n tmds33(CML)/lvds
	output			DVI_TXC_P,					// out   [DVI] clk-p tmds33(CML)/lvds
	inout			DVI_TX_SDA,					// inout [DVI] dcc sda
	inout			DVI_TX_SCL,					// inout [DVI] dcc scl
	inout			DVI_TX_CEC,					// inout [DVI] cec
	input			DVI_TX_HPD,					// in    [DVI] detect

	output			DVI_RX0_N,					// out   [DVI] ch0-n tmds33(CML)/lvds
	output			DVI_RX0_P,					// out   [DVI] ch0-p tmds33(CML)/lvds
	output			DVI_RX1_N,					// out   [DVI] ch1-n tmds33(CML)/lvds
	output			DVI_RX1_P,					// out   [DVI] ch1-p tmds33(CML)/lvds
	output			DVI_RX2_N,					// out   [DVI] ch2-n tmds33(CML)/lvds
	output			DVI_RX2_P,					// out   [DVI] ch2-p tmds33(CML)/lvds
	output			DVI_RXC_N,					// out   [DVI] clk-n tmds33(CML)/lvds
	output			DVI_RXC_P,					// out   [DVI] clk-p tmds33(CML)/lvds
	inout			DVI_RX_SDA,					// inout [DVI] dcc sda
	inout			DVI_RX_SCL,					// inout [DVI] dcc scl
	inout			DVI_RX_CEC,					// inout [DVI] cec
	input			DVI_RX_HPD,					// in    [DVI] detect

	output			LCD_TX0_N,					// out   [LCD] ch0-n lvds
	output			LCD_TX0_P,					// out   [LCD] ch0-p lvds
	output			LCD_TX1_N,					// out   [LCD] ch1-n lvds
	output			LCD_TX1_P,					// out   [LCD] ch1-p lvds
	output			LCD_TX2_N,					// out   [LCD] ch2-n lvds
	output			LCD_TX2_P,					// out   [LCD] ch2-p lvds
	output			LCD_TX3_N,					// out   [LCD] ch3-n lvds
	output			LCD_TX3_P,					// out   [LCD] ch3-p lvds
	output			LCD_TXC_N,					// out   [LCD] clk-n lvds
	output			LCD_TXC_P,					// out   [LCD] clk-p lvds

//	input			TX_OE_N,					// in    [RGB] tx #oe

	input	[7:0]	TX_RED,						// in    [RGB] red [7:0]
	input	[7:0]	TX_GRN,						// in    [RGB] grn [7:0]
	input	[7:0]	TX_BLU,						// in    [RGB] blu [7:0]
	input			TX_HS,						// in    [RGB] #hsync
	input			TX_VS,						// in    [RGB] #vsync
//	input			TX_C0,						// in    [RGB] c0
//	input			TX_C1,						// in    [RGB] c1
//	input			TX_C2,						// in    [RGB] c2
//	input			TX_C3,						// in    [RGB] c3
	input			TX_DE,						// in    [RGB] de
	input			TX_CLK,						// in    [RGB] clock

	input			sys_clk,					// in    [SYS] clock
	input			sys_rst_n					// in    [SYS] #reset
);

//--------------------------------------------------------------
//  override parameter

//--------------------------------------------------------------
//  local parameter

//--------------------------------------------------------------
//  signal

	wire	clk25;
	wire	clk25x5;
	wire	clk50;
	wire	clk65;
	wire	clk65x5;
	wire	clk65x7;
	wire	clk65div2;
	wire	clk65div2x7;
	wire	clk100;

	wire	rst_n;

	reg		[7:0] disp_red_r;
	reg		[7:0] disp_grn_r;
	reg		[7:0] disp_blu_r;
	reg		disp_de_r;
	reg		disp_hsync_n_r;
	reg		disp_vsync_n_r;
	reg		disp_c0_r;
	reg		disp_c1_r;
	reg		disp_c2_r;
	reg		disp_c3_r;

	wire	[7:0] disp_red;
	wire	[7:0] disp_grn;
	wire	[7:0] disp_blu;
	wire	disp_de;
	wire	disp_hsync_n;
	wire	disp_vsync_n;
	wire	disp_c0;
	wire	disp_c1;
	wire	disp_c2;
	wire	disp_c3;

	wire	TX_C0;
	wire	TX_C1;
	wire	TX_C2;
	wire	TX_C3;

	wire	TX_CLK_DDR;

//--------------------------------------------------------------
//  design

	// ---- dvi output ----

	assign disp_red[7:0]=TX_RED[7:0];
	assign disp_grn[7:0]=TX_GRN[7:0];
	assign disp_blu[7:0]=TX_BLU[7:0];
	assign disp_de=TX_DE;
	assign disp_hsync_n=TX_HS;
	assign disp_vsync_n=TX_VS;
	assign disp_c0=1'b0;
	assign disp_c1=1'b0;
	assign disp_c2=1'b0;
	assign disp_c3=1'b0;

xil_dcm_x5 dcm_x5(
	.CLKIN_IN(TX_CLK), 
	.RST_IN(!sys_rst_n), 
	.CLKFX_OUT(clk25x5), 
	.CLKFX180_OUT(), 
	.CLK0_OUT(clk25), 
	.LOCKED_OUT(rst_n)
);

	assign DVI_TX_SDA=1'bz;
	assign DVI_TX_SCL=1'bz;
	assign DVI_TX_CEC=1'bz;

	assign DVI_RX0_N=1'bz;
	assign DVI_RX0_P=1'bz;
	assign DVI_RX1_N=1'bz;
	assign DVI_RX1_P=1'bz;
	assign DVI_RX2_N=1'bz;
	assign DVI_RX2_P=1'bz;
	assign DVI_RXC_N=1'bz;
	assign DVI_RXC_P=1'bz;

	assign DVI_RX_SDA=1'bz;
	assign DVI_RX_SCL=1'bz;
	assign DVI_RX_CEC=1'bz;

	always @(negedge clk25 or negedge rst_n)
	begin
		if (rst_n==1'b0)
			begin
				disp_red_r[7:0] <= 8'b0;
				disp_grn_r[7:0] <= 8'b0;
				disp_blu_r[7:0] <= 8'b0;
				disp_de_r <= 1'b0;
				disp_hsync_n_r <= 1'b0;
				disp_vsync_n_r <= 1'b0;
				disp_c0_r <= 1'b0;
				disp_c1_r <= 1'b0;
				disp_c2_r <= 1'b0;
				disp_c3_r <= 1'b0;
			end
		else
			begin
				disp_red_r[7:0] <= disp_red[7:0];
				disp_grn_r[7:0] <= disp_grn[7:0];
				disp_blu_r[7:0] <= disp_blu[7:0];
				disp_de_r <= disp_de;
				disp_hsync_n_r <= disp_hsync_n;
				disp_vsync_n_r <= disp_vsync_n;
				disp_c0_r <= disp_c0;
				disp_c1_r <= disp_c1;
				disp_c2_r <= disp_c2;
				disp_c3_r <= disp_c3;
			end
	end

xil_dvi #(
	.DVI_TX0(1),						// polarity 0=normal / 1=invert
	.DVI_TX1(1),						// polarity 0=normal / 1=invert
	.DVI_TX2(1),						// polarity 0=normal / 1=invert
	.DVI_TXC(1)							// polarity 0=normal / 1=invert
) xil_dvi(
	.DVI_TX0_N(DVI_TX0_N),				// out   [TX] TX[0]-N (CML)
	.DVI_TX0_P(DVI_TX0_P),				// out   [TX] TX[0]-P (CML)
	.DVI_TX1_N(DVI_TX1_N),				// out   [TX] TX[1]-N (CML)
	.DVI_TX1_P(DVI_TX1_P),				// out   [TX] TX[1]-P (CML)
	.DVI_TX2_N(DVI_TX2_N),				// out   [TX] TX[2]-N (CML)
	.DVI_TX2_P(DVI_TX2_P),				// out   [TX] TX[2]-P (CML)
	.DVI_TXC_N(DVI_TXC_N),				// out   [TX] TX_CLK-N (CML)
	.DVI_TXC_P(DVI_TXC_P),				// out   [TX] TX_CLK-P (CML)

/*
	.DVI2_TX0_N(DVI_RX0_N),				// out   [TX] TX[0]-N (CML)
	.DVI2_TX0_P(DVI_RX0_P),				// out   [TX] TX[0]-P (CML)
	.DVI2_TX1_N(DVI_RX1_N),				// out   [TX] TX[1]-N (CML)
	.DVI2_TX1_P(DVI_RX1_P),				// out   [TX] TX[1]-P (CML)
	.DVI2_TX2_N(DVI_RX2_N),				// out   [TX] TX[2]-N (CML)
	.DVI2_TX2_P(DVI_RX2_P),				// out   [TX] TX[2]-P (CML)
	.DVI2_TXC_N(DVI_RXC_N),				// out   [TX] TX_CLK-N (CML)
	.DVI2_TXC_P(DVI_RXC_P),				// out   [TX] TX_CLK-P (CML)
*/
	.DVI2_TX0_N(),						// out   [TX] TX[0]-N (CML)
	.DVI2_TX0_P(),						// out   [TX] TX[0]-P (CML)
	.DVI2_TX1_N(),						// out   [TX] TX[1]-N (CML)
	.DVI2_TX1_P(),						// out   [TX] TX[1]-P (CML)
	.DVI2_TX2_N(),						// out   [TX] TX[2]-N (CML)
	.DVI2_TX2_P(),						// out   [TX] TX[2]-P (CML)
	.DVI2_TXC_N(),						// out   [TX] TX_CLK-N (CML)
	.DVI2_TXC_P(),						// out   [TX] TX_CLK-P (CML)

	.TX_RED(disp_red_r[7:0]),			// in    [TX] red [7:0]
	.TX_GRN(disp_grn_r[7:0]),			// in    [TX] grn [7:0]
	.TX_BLU(disp_blu_r[7:0]),			// in    [TX] blu [7:0]
	.TX_HS(disp_hsync_n_r),				// in    [TX] #hsync
	.TX_VS(disp_vsync_n_r),				// in    [TX] #vsync
	.TX_C0(disp_c0_r),					// in    [TX] c0
	.TX_C1(disp_c1_r),					// in    [TX] c1
	.TX_C2(disp_c2_r),					// in    [TX] c2
	.TX_C3(disp_c3_r),					// in    [TX] c3
	.TX_DE(disp_de_r),					// in    [TX] de

	.CLK(clk25),						// in    [DVI] clock
	.CLKx5(clk25x5),					// in    [DVI] clk x5 : dvi ddr
	.RESET_N(rst_n)						// in    [DVI] #reset
);

	assign LCD_TX0_N=1'bz;
	assign LCD_TX0_P=1'bz;
	assign LCD_TX1_N=1'bz;
	assign LCD_TX1_P=1'bz;
	assign LCD_TX2_N=1'bz;
	assign LCD_TX2_P=1'bz;
	assign LCD_TX3_N=1'bz;
	assign LCD_TX3_P=1'bz;
	assign LCD_TXC_N=1'bz;
	assign LCD_TXC_P=1'bz;

/*
	assign clk65=clk25;

	reg		clk65div2_r;

	assign clk65div2=clk65div2_r;

	always @(posedge clk65 or negedge rst_n)
	begin
		if (rst_n==1'b0)
			begin
				clk65div2_r <= 1'b0;
			end
		else
			begin
				clk65div2_r <= !clk65div2_r;
			end
	end

xil_dcm_x7d2 dcm_x7d2(
	.CLKIN_IN(clk65), 
	.RST_IN(!rst_n), 
	.CLKFX_OUT(clk65div2x7), 
	.CLKFX180_OUT(), 
	.CLK0_OUT(), 
	.LOCKED_OUT()
);

xil_lvds666 lvds666(
	.LCD_TX0_N(LCD_TX0_N),				// out   [LCD] ch0-n lvds
	.LCD_TX0_P(LCD_TX0_P),				// out   [LCD] ch0-p lvds
	.LCD_TX1_N(LCD_TX1_N),				// out   [LCD] ch1-n lvds
	.LCD_TX1_P(LCD_TX1_P),				// out   [LCD] ch1-p lvds
	.LCD_TX2_N(LCD_TX2_N),				// out   [LCD] ch2-n lvds
	.LCD_TX2_P(LCD_TX2_P),				// out   [LCD] ch2-p lvds
	.LCD_TX3_N(LCD_TX3_N),				// out   [LCD] ch3-n lvds
	.LCD_TX3_P(LCD_TX3_P),				// out   [LCD] ch3-p lvds
	.LCD_TXC_N(LCD_TXC_N),				// out   [LCD] clk-n lvds
	.LCD_TXC_P(LCD_TXC_P),				// out   [LCD] clk-p lvds

	.TX_RED(disp_red_r[7:0]),			// in    [TX] red [7:0]
	.TX_GRN(disp_grn_r[7:0]),			// in    [TX] grn [7:0]
	.TX_BLU(disp_blu_r[7:0]),			// in    [TX] blu [7:0]
	.TX_HS(disp_hsync_n_r),				// in    [TX] #hsync
	.TX_VS(disp_vsync_n_r),				// in    [TX] #vsync
	.TX_C0(1'b0),					// in    [TX] c0
	.TX_C1(1'b0),					// in    [TX] c1
	.TX_C2(1'b0),					// in    [TX] c2
	.TX_C3(1'b0),					// in    [TX] c3
	.TX_DE(disp_de_r),					// in    [TX] de

	.CLK(clk65),					// in    [TX] clock
	.CLK_div2(clk65div2),				// in    [DVI] clk /2
	.CLK_div2x7(clk65div2x7),			// in    [DVI] clk /2x7 : lvds ddr
	.RESET_N(rst_n)						// in    [TX] #reset
);
*/
endmodule
