//------------------------------------------------------------------------------
//
//  lynx_disp_tb.v : Spartan3A display test testbench
//
//  LICENSE : "as-is"
//  copyright (C) 2009, TakeshiNagashima caramelgate@gmail.com
//------------------------------------------------------------------------------
//  2009/aug/17 release 0.0  
//
//------------------------------------------------------------------------------

`include "sim_xilinx_inc.v"
`include "lynx_disp.v"
`include "xil_dvi.v"
`include "dvi_data_enc.v"
`include "xil_dcm_sp_50x65.v"
`include "xil_dcm_x5.v"
`include "dispgen_xga.v"

`timescale 1ns / 100ps

module tb(
);

	wire	CLK50;
	wire	RST_N;

	// ---- 50MHz ----

	reg		CLK50_r;

	initial
	begin
		forever
		begin
			CLK50_r <= 1'b0; #10;
			CLK50_r <= 1'b1; #10;
		end
	end

	assign CLK50=CLK50_r;

	// ---- reset ----

	reg		[8:0] RST_N_r;

	initial
	begin
		RST_N_r[0] <= 'b1; #2;
		RST_N_r[0] <= 'b0; #200;
		RST_N_r[0] <= 'b1; #1;
	end

	always @(posedge CLK50 or negedge RST_N_r[0])
	begin
		if (RST_N_r[0]==1'b0)
			begin
				RST_N_r[8:1] <= 8'h00;
			end
		else
			begin
				RST_N_r[8] <= (RST_N_r[7:1]==7'h0f) ? 1'b1 : RST_N_r[8];
				RST_N_r[7:1] <= RST_N_r[7:1]+7'h01;
			end
	end

	assign RST_N=RST_N_r[8];

	// ---- standalone test ----

lynx_disp lynx_disp(
	.DVI_TX0_N(),					// out   [DVI] ch0-n tmds33(CML)/lvds
	.DVI_TX0_P(),					// out   [DVI] ch0-p tmds33(CML)/lvds
	.DVI_TX1_N(),					// out   [DVI] ch1-n tmds33(CML)/lvds
	.DVI_TX1_P(),					// out   [DVI] ch1-p tmds33(CML)/lvds
	.DVI_TX2_N(),					// out   [DVI] ch2-n tmds33(CML)/lvds
	.DVI_TX2_P(),					// out   [DVI] ch2-p tmds33(CML)/lvds
	.DVI_TXC_N(),					// out   [DVI] clk-n tmds33(CML)/lvds
	.DVI_TXC_P(),					// out   [DVI] clk-p tmds33(CML)/lvds
	.DVI_TX_SDA(),					// inout [DVI] dcc sda
	.DVI_TX_SCL(),					// inout [DVI] dcc scl
	.DVI_TX_CEC(),					// inout [DVI] cec
	.DVI_TX_HPD(1'b1),				// in    [DVI] detect

	.DVI_RX0_N(),					// out   [DVI] ch0-n tmds33(CML)/lvds
	.DVI_RX0_P(),					// out   [DVI] ch0-p tmds33(CML)/lvds
	.DVI_RX1_N(),					// out   [DVI] ch1-n tmds33(CML)/lvds
	.DVI_RX1_P(),					// out   [DVI] ch1-p tmds33(CML)/lvds
	.DVI_RX2_N(),					// out   [DVI] ch2-n tmds33(CML)/lvds
	.DVI_RX2_P(),					// out   [DVI] ch2-p tmds33(CML)/lvds
	.DVI_RXC_N(),					// out   [DVI] clk-n tmds33(CML)/lvds
	.DVI_RXC_P(),					// out   [DVI] clk-p tmds33(CML)/lvds
	.DVI_RX_SDA(),					// inout [DVI] dcc sda
	.DVI_RX_SCL(),					// inout [DVI] dcc scl
	.DVI_RX_CEC(),					// inout [DVI] cec
	.DVI_RX_HPD(1'b1),				// in    [DVI] detect

	.LCD_TX0_N(),					// out   [LCD] ch0-n lvds
	.LCD_TX0_P(),					// out   [LCD] ch0-p lvds
	.LCD_TX1_N(),					// out   [LCD] ch1-n lvds
	.LCD_TX1_P(),					// out   [LCD] ch1-p lvds
	.LCD_TX2_N(),					// out   [LCD] ch2-n lvds
	.LCD_TX2_P(),					// out   [LCD] ch2-p lvds
	.LCD_TX3_N(),					// out   [LCD] ch3-n lvds
	.LCD_TX3_P(),					// out   [LCD] ch3-p lvds
	.LCD_TXC_N(),					// out   [LCD] clk-n lvds
	.LCD_TXC_P(),					// out   [LCD] clk-p lvds

//	.TX_OE_N(1'b0),					// in    [RGB] tx #oe

	.TX_RED(),						// out   [RGB] red [7:0]
	.TX_GRN(),						// out   [RGB] grn [7:0]
	.TX_BLU(),						// out   [RGB] blu [7:0]
	.TX_HS(),						// out   [RGB] #hsync
	.TX_VS(),						// out   [RGB] #vsync
//	.TX_C0(),						// out   [RGB] c0
//	.TX_C1(),						// out   [RGB] c1
//	.TX_C2(),						// out   [RGB] c2
//	.TX_C3(),						// out   [RGB] c3
	.TX_DE(),						// out   [RGB] de
	.TX_CLK(),						// out   [RGB] clock

	.sys_clk(CLK50),					// in    [SYS] clock
	.sys_rst_n(RST_N)					// in    [SYS] #reset
);

/*

	// ---- video dac : de1 ----

	wire	[35:0] GPIO_1;

	assign {GPIO_1[15],GPIO_1[13],GPIO_1[11],GPIO_1[9]}=TX_BLU[7:4];
	assign {GPIO_1[23],GPIO_1[21],GPIO_1[19],GPIO_1[17]}=TX_GRN[7:4];
	assign {GPIO_1[31],GPIO_1[29],GPIO_1[27],GPIO_1[25]}=TX_RED[7:4];
	assign GPIO_1[3]=TX_HS;
	assign GPIO_1[4]=TX_VS;

	assign GPIO_1[2:0]=3'b0;
	assign GPIO_1[8:5]=4'b0;
	assign GPIO_1[10]=1'b0;
	assign GPIO_1[10]=1'b0;
	assign GPIO_1[12]=1'b0;
	assign GPIO_1[13]=1'b0;
	assign GPIO_1[16]=1'b0;
	assign GPIO_1[18]=1'b0;
	assign GPIO_1[20]=1'b0;
	assign GPIO_1[22]=1'b0;
	assign GPIO_1[24]=1'b0;
	assign GPIO_1[26]=1'b0;
	assign GPIO_1[28]=1'b0;
	assign GPIO_1[30]=1'b0;
	assign GPIO_1[35:32]=4'b0;

de1_rgb de1_rgb(
	.GPIO_0(),	// Altera SC conv
	.GPIO_1(GPIO_1[35:0]),

	// global signals
	.CLK50(1'b0),
	.CLK27(1'b0),
	.CLK27a(1'b0),
	.CLK24(1'b0),
	.CLK24a(1'b0),
	.CLKEXT(1'b0),

	// the_ps2_0
	.PS2_CLK(),
	.PS2_DATA(),

	// the_vga_controller_0
	.VGA_B(VGA_B[3:0]),
	.VGA_G(VGA_G[3:0]),
	.VGA_R(VGA_R[3:0]),
	.VGA_HS(VGA_HS),
	.VGA_VS(VGA_VS),

	// the_Audio_0
	.I2C_SDAT(),
	.I2C_SCLK(),
	.AUD_ADCLRCK(),
	.AUD_ADCDAT(),
	.AUD_DACLRCK(),
	.AUD_DACDAT(),
	.AUD_BCLK(),
	.AUD_XCK(),

	// the_SEG7_Display
	.HEX0(),
	.HEX1(),
	.HEX2(),
	.HEX3(),

	// the_button_pio
	.KEY0(),
	.KEY1(),
	.KEY2(),
	.KEY3(),

	// the_led_green
	.LEDG(),

	// the_led_red
	.LEDR(),

	// the_sdram_0
	.DRAM_ADDR(),
	.DRAM_BA_0(),
	.DRAM_BA_1(),
	.DRAM_CAS_N(),
	.DRAM_CKE(),
	.DRAM_CLK(),
	.DRAM_CS_N(),
	.DRAM_DATA(),
	.DRAM_LDQM(),
	.DRAM_UDQM(),
	.DRAM_RAS_N(),
	.DRAM_WE_N(),

	// the_spi_0
	.SD_DAT(),
	.SD_CMD(),
	.SD_CLK(),
	.SD_DAT3(),

	// the_sram_0
	.SRAM_ADDR(),
	.SRAM_CE_N(),
	.SRAM_DATA(),
	.SRAM_LB_N(),
	.SRAM_OE_N(),
	.SRAM_UB_N(),
	.SRAM_WE_N(),

	// the_switch_pio
	.SW(),

	// the_tri_state_bridge_0_avalon_slave
	.FL_CE_N(),
	.FL_ADDR(),
	.FL_DATA(),
	.FL_OE_N(),
	.FL_WE_N(),
	.FL_RST_N(),

	// the_uart_0
	.UART_RXD(),
	.UART_TXD()
);

*/

endmodule
