//------------------------------------------------------------------------------
//
//  lynx_rgb.v : Spartan3A dvi recieve test top module
//
//  LICENSE : "as-is"
//  copyright (C) 2006, TakeshiNagashima caramelgate@gmail.com
//------------------------------------------------------------------------------
//  2009/mar/03 release 0.0  xilinx sp3a
//       aug/17 release 0.0a hdl xc-303/sp3an50
//       aug/24 release 0.1  lynx-sp3an50
//
//------------------------------------------------------------------------------

module lynx_rgb(
//--------------------------------------------------------------
//  port

	output			DVI_TX0_N,					// out   [DVI] ch0-n tmds33(CML)/lvds
	output			DVI_TX0_P,					// out   [DVI] ch0-p tmds33(CML)/lvds
	output			DVI_TX1_N,					// out   [DVI] ch1-n tmds33(CML)/lvds
	output			DVI_TX1_P,					// out   [DVI] ch1-p tmds33(CML)/lvds
	output			DVI_TX2_N,					// out   [DVI] ch2-n tmds33(CML)/lvds
	output			DVI_TX2_P,					// out   [DVI] ch2-p tmds33(CML)/lvds
	output			DVI_TXC_N,					// out   [DVI] clk-n tmds33(CML)/lvds
	output			DVI_TXC_P,					// out   [DVI] clk-p tmds33(CML)/lvds
	inout			DVI_TX_SDA,					// inout [DVI] dcc sda
	inout			DVI_TX_SCL,					// inout [DVI] dcc scl
	inout			DVI_TX_CEC,					// inout [DVI] cec
	input			DVI_TX_HPD,					// in    [DVI] detect

	input			DVI_RX0_N,					// in    [DVI] ch0-n tmds33(CML)/lvds
	input			DVI_RX0_P,					// in    [DVI] ch0-p tmds33(CML)/lvds
	input			DVI_RX1_N,					// in    [DVI] ch1-n tmds33(CML)/lvds
	input			DVI_RX1_P,					// in    [DVI] ch1-p tmds33(CML)/lvds
	input			DVI_RX2_N,					// in    [DVI] ch2-n tmds33(CML)/lvds
	input			DVI_RX2_P,					// in    [DVI] ch2-p tmds33(CML)/lvds
	input			DVI_RXC_N,					// in    [DVI] clk-n tmds33(CML)/lvds
	input			DVI_RXC_P,					// in    [DVI] clk-p tmds33(CML)/lvds
	inout			DVI_RX_SDA,					// inout [DVI] dcc sda
	inout			DVI_RX_SCL,					// inout [DVI] dcc scl
	inout			DVI_RX_CEC,					// inout [DVI] cec
	input			DVI_RX_HPD,					// in    [DVI] detect

	input	[7:0]	TX_RED,						// in    [RGB] red [7:0]
	input	[7:0]	TX_GRN,						// in    [RGB] grn [7:0]
	input	[7:0]	TX_BLU,						// in    [RGB] blu [7:0]
	input			TX_HS,						// in    [RGB] #hsync
	input			TX_VS,						// in    [RGB] #vsync
//	input			TX_C0,						// in    [RGB] c0
//	input			TX_C1,						// in    [RGB] c1
//	input			TX_C2,						// in    [RGB] c2
//	input			TX_C3,						// in    [RGB] c3
	input			TX_DE,						// in    [RGB] de
	input			TX_CLK,						// in    [RGB] clock

	output	[7:0]	RX_RED,						// out   [RGB] red [7:0]
	output	[7:0]	RX_GRN,						// out   [RGB] grn [7:0]
	output	[7:0]	RX_BLU,						// out   [RGB] blu [7:0]
	output			RX_HS,						// out   [RGB] #hsync
	output			RX_VS,						// out   [RGB] #vsync
//	output			RX_C0,						// out   [RGB] c0
//	output			RX_C1,						// out   [RGB] c1
//	output			RX_C2,						// out   [RGB] c2
//	output			RX_C3,						// out   [RGB] c3
	output			RX_DE,						// out   [RGB] de
	output			RX_CLK,						// out   [RGB] clock

	input			sys_clk,					// in    [SYS] clock
	input			sys_rst_n					// in    [SYS] #reset
);

//--------------------------------------------------------------
//  override parameter

//--------------------------------------------------------------
//  local parameter

//--------------------------------------------------------------
//  signal

	wire	clk25;
	wire	clk25x5;
	wire	clk50;
	wire	clk65;
	wire	clk65x5;
	wire	clk65x7;
	wire	clk65div2;
	wire	clk65div2x7;
	wire	clk100;

	wire	rst_n;

	reg		[7:0] disp_red_r;
	reg		[7:0] disp_grn_r;
	reg		[7:0] disp_blu_r;
	reg		disp_de_r;
	reg		disp_hsync_n_r;
	reg		disp_vsync_n_r;
	reg		disp_c0_r;
	reg		disp_c1_r;
	reg		disp_c2_r;
	reg		disp_c3_r;

	wire	[7:0] disp_red;
	wire	[7:0] disp_grn;
	wire	[7:0] disp_blu;
	wire	disp_de;
	wire	disp_hsync_n;
	wire	disp_vsync_n;
	wire	disp_c0;
	wire	disp_c1;
	wire	disp_c2;
	wire	disp_c3;

	wire	TX_C0;
	wire	TX_C1;
	wire	TX_C2;
	wire	TX_C3;

	wire	RX_C0;
	wire	RX_C1;
	wire	RX_C2;
	wire	RX_C3;

	wire	TX_CLK_DDR;
	wire	RX_CLK_OUT;
	wire	RX_CLK_DDR;

//--------------------------------------------------------------
//  design

xil_dvi_rx rx(
	.DVI_RX0_N(DVI_RX0_N),				// in    [RX] 
	.DVI_RX0_P(DVI_RX0_P),				// in    [RX] 
	.DVI_RX1_N(DVI_RX1_N),				// in    [RX] 
	.DVI_RX1_P(DVI_RX1_P),				// in    [RX] 
	.DVI_RX2_N(DVI_RX2_N),				// in    [RX] 
	.DVI_RX2_P(DVI_RX2_P),				// in    [RX] 
	.DVI_RXC_N(DVI_RXC_N),				// in    [RX] 
	.DVI_RXC_P(DVI_RXC_P),				// in    [RX] 

	.RX_RED(RX_RED[7:0]),				// out   [RX] [7:0]
	.RX_GRN(RX_GRN[7:0]),				// out   [RX] [7:0]
	.RX_BLU(RX_BLU[7:0]),				// out   [RX] [7:0]
	.RX_HS(RX_HS),						// out   [RX] 
	.RX_VS(RX_VS),						// out   [RX] 
	.RX_C0(RX_C0),						// out   [RX] 
	.RX_C1(RX_C1),						// out   [RX] 
	.RX_C2(RX_C2),						// out   [RX] 
	.RX_C3(RX_C3),						// out   [RX] 
	.RX_DE(RX_DE),						// out   [RX] 

	.CLK_LOCK(),						// out   [RX] test sinal
	.CLKx10(),							// out   [RX] test sinal
	.CLK(RX_CLK_OUT),					// out   [RX] clock
	.RESET_N(sys_rst_n)					// in    [RX] #reset
);

FDDRRSE DDR_RX_CLK(.Q(RX_CLK_DDR),.C0(RX_CLK_OUT),.C1(!RX_CLK_OUT),.CE(1'b1),.D0(1'b1),.D1(1'b0),.R(1'b0),.S(1'b0));

	assign RX_CLK=RX_CLK_DDR;

endmodule
