//------------------------------------------------------------------------------
//
//  de1_rgb.v : de1_rgb top module
//
//  LICENSE : "as-is"
//  TakeshiNagashima(T.NG) caramelgete@gmail.com
//------------------------------------------------------------------------------
//  2009/sep/23 release 0.0  
//
//------------------------------------------------------------------------------

module de1_rgb (
	inout	[35:0]	GPIO_0,	// Altera SC conv
	inout	[35:0]	GPIO_1,

	// global signals
	input			CLK50,
	input			CLK27,
	input			CLK27a,
	input			CLK24,
	input			CLK24a,
	input			CLKEXT,

	// the_ps2_0
	inout			PS2_CLK,
	inout			PS2_DATA,

	// the_vga_controller_0
	output	[3:0]	VGA_B,
	output	[3:0]	VGA_G,
	output	[3:0]	VGA_R,
	output			VGA_HS,
	output			VGA_VS,

	// the_Audio_0
	inout			I2C_SDAT,
	output			I2C_SCLK,
	inout			AUD_ADCLRCK,
	input			AUD_ADCDAT,
	inout			AUD_DACLRCK,
	output			AUD_DACDAT,
	inout			AUD_BCLK,
	output			AUD_XCK,

	// the_SEG7_Display
	output	[6:0]	HEX0,
	output	[6:0]	HEX1,
	output	[6:0]	HEX2,
	output	[6:0]	HEX3,

	// the_button_pio
	input			KEY0,
	input			KEY1,
	input			KEY2,
	input			KEY3,

	// the_led_green
	output	[7:0]	LEDG,

	// the_led_red
	output	[9:0]	LEDR,

	// the_sdram_0
	output	[11:0]	DRAM_ADDR,
	output			DRAM_BA_0,
	output			DRAM_BA_1,
	output			DRAM_CAS_N,
	output			DRAM_CKE,
	output			DRAM_CLK,
	output			DRAM_CS_N,
	inout	[15:0]	DRAM_DATA,
	output			DRAM_LDQM,
	output			DRAM_UDQM,
	output			DRAM_RAS_N,
	output			DRAM_WE_N,

	// the_spi_0
	input			SD_DAT,
	output			SD_CMD,
	output			SD_CLK,
	output			SD_DAT3,

	// the_sram_0
	output	[17:0]	SRAM_ADDR,
	output			SRAM_CE_N,
	inout	[15:0]	SRAM_DATA,
	output			SRAM_LB_N,
	output			SRAM_OE_N,
	output			SRAM_UB_N,
	output			SRAM_WE_N,

	// the_switch_pio
	input	[9:0]	SW,

	// the_tri_state_bridge_0_avalon_slave
	output			FL_CE_N,
	output	[21:0]	FL_ADDR,
	inout	[7:0]	FL_DATA,
	output			FL_OE_N,
	output			FL_WE_N,
	output			FL_RST_N,

	// the_uart_0
	input			UART_RXD,
	output			UART_TXD
);

//--------------------------------------------------------------
//  override parameter

//--------------------------------------------------------------
//  local parameter

//--------------------------------------------------------------
//  signal

//	inout	[35:0]	GPIO_0,	// Altera SC conv
//	inout	[35:0]	GPIO_1,

	// global signals
//	input			CLK50,
//	input			CLK27,
//	input			CLK27a,
//	input			CLK24,
//	input			CLK24a,
//	input			CLKEXT,

	// the_ps2_0
	assign PS2_CLK=1'bz;
	assign PS2_DATA=1'bz;

	// the_vga_controller_0
	assign VGA_B[3:0]={GPIO_1[15],GPIO_1[13],GPIO_1[11],GPIO_1[9]};
	assign VGA_G[3:0]={GPIO_1[23],GPIO_1[21],GPIO_1[19],GPIO_1[17]};
	assign VGA_R[3:0]={GPIO_1[31],GPIO_1[29],GPIO_1[27],GPIO_1[25]};
	assign VGA_HS=GPIO_1[3];
	assign VGA_VS=GPIO_1[4];

	// the_Audio_0
	assign I2C_SDAT=1'bz;
	assign I2C_SCLK=1'b0;
	assign AUD_ADCLRCK=1'bz;
//	input			AUD_ADCDAT,
	assign AUD_DACLRCK=1'bz;
	assign AUD_DACDAT=1'b0;
	assign AUD_BCLK=1'bz;
	assign AUD_XCK=1'b0;

	// the_SEG7_Display
	assign HEX0=7'b0000000;
	assign HEX1=7'b0000000;
	assign HEX2=7'b0000000;
	assign HEX3=7'b0000000;

	// the_button_pio
//	input			KEY0,
//	input			KEY1,
//	input			KEY2,
//	input			KEY3,

	// the_led_green
	assign LEDG=8'b0;

	// the_led_red
	assign LEDR=10'b0;

	// the_sdram_0
	assign DRAM_ADDR=12'b0;
	assign DRAM_BA_0=1'b0;
	assign DRAM_BA_1=1'b0;
	assign DRAM_CAS_N=1'b1;
	assign DRAM_CKE=1'b0;
	assign DRAM_CLK=1'b0;
	assign DRAM_CS_N=1'b1;
	assign DRAM_DATA=16'hzzzz;
	assign DRAM_LDQM=1'b1;
	assign DRAM_UDQM=1'b1;
	assign DRAM_RAS_N=1'b1;
	assign DRAM_WE_N=1'b1;

	// the_spi_0
//	input			SD_DAT,
	assign SD_CMD=1'bz;
	assign SD_CLK=1'bz;
	assign SD_DAT3=1'bz;

	// the_sram_0
	assign SRAM_ADDR=18'b0;
	assign SRAM_CE_N=1'b1;
	assign SRAM_DATA=16'hzzzz;
	assign SRAM_LB_N=1'b1;
	assign SRAM_OE_N=1'b1;
	assign SRAM_UB_N=1'b1;
	assign SRAM_WE_N=1'b1;

	// the_switch_pio
//	input	[9:0]	SW,

	// the_tri_state_bridge_0_avalon_slave
	assign FL_CE_N=1'b1;
	assign FL_ADDR=22'b0;
	assign FL_DATA=8'hzz;
	assign FL_OE_N=1'b1;
	assign FL_WE_N=1'b1;
	assign FL_RST_N=1'b0;

	// the_uart_0
//	input			UART_RXD,
	assign UART_TXD=1'bz;

endmodule
