//------------------------------------------------------------------------------
//
//  lynx_dvi_tb.v : Spartan3A display test testbench
//
//  LICENSE : "as-is"
//  copyright (C) 2009, TakeshiNagashima caramelgate@gmail.com
//------------------------------------------------------------------------------
//  2009/aug/17 release 0.0  
//
//------------------------------------------------------------------------------

`include "sim_xilinx_inc.v"
`include "lynx_dvi.v"
`include "xil_dvi.v"
`include "dvi_data_enc.v"
`include "xil_dcm_x5.v"
`include "dispgen.v"

`timescale 1ns / 100ps

module tb(
);

	wire	CLK25;
	wire	CLK50;
	wire	RST_N;

	// ---- 25MHz ----

	reg		CLK25_r;

	initial
	begin
		forever
		begin
			CLK25_r <= 1'b0; #20;
			CLK25_r <= 1'b1; #20;
		end
	end

	assign CLK25=CLK25_r;

	// ---- 50MHz ----

	reg		CLK50_r;

	initial
	begin
		forever
		begin
			CLK50_r <= 1'b0; #10;
			CLK50_r <= 1'b1; #10;
		end
	end

	assign CLK50=CLK50_r;

	// ---- reset ----

	reg		[8:0] RST_N_r;

	initial
	begin
		RST_N_r[0] <= 'b1; #2;
		RST_N_r[0] <= 'b0; #200;
		RST_N_r[0] <= 'b1; #1;
	end

	always @(posedge CLK50 or negedge RST_N_r[0])
	begin
		if (RST_N_r[0]==1'b0)
			begin
				RST_N_r[8:1] <= 8'h00;
			end
		else
			begin
				RST_N_r[8] <= (RST_N_r[7:1]==7'h0f) ? 1'b1 : RST_N_r[8];
				RST_N_r[7:1] <= RST_N_r[7:1]+7'h01;
			end
	end

	assign RST_N=RST_N_r[8];

	wire	[7:0] TX_RED;
	wire	[7:0] TX_GRN;
	wire	[7:0] TX_BLU;
	wire	TX_HS;
	wire	TX_VS;
//	wire	TX_C0;
//	wire	TX_C1;
//	wire	TX_C2;
//	wire	TX_C3;
	wire	TX_DE;
	wire	TX_CLK;

	assign TX_CLK=CLK25;

dispgen dispgen(
	.D_RED(TX_RED[7:0]),			// out   [CRT] [7:0] red
	.D_GRN(TX_GRN[7:0]),			// out   [CRT] [7:0] green
	.D_BLU(TX_BLU[7:0]),			// out   [CRT] [7:0] blue
	.D_HSYNC_N(TX_HS),				// out   [CRT] #hsync
	.D_VSYNC_N(TX_VS),				// out   [CRT] #vsync
	.D_BLANK_N(TX_DE),				// out   [CRT] #blank

	.D_MODE(4'b0),					// in    [] [3:0] sim/#normal

	.D_RST_N(RST_N),				// in    [] : #reset
	.D_CLK(TX_CLK)					// in    [CRT] dot clock
);

lynx_dvi lynx_dvi(
	.DVI_TX0_N(),					// out   [DVI] ch0-n tmds33(CML)/lvds
	.DVI_TX0_P(),					// out   [DVI] ch0-p tmds33(CML)/lvds
	.DVI_TX1_N(),					// out   [DVI] ch1-n tmds33(CML)/lvds
	.DVI_TX1_P(),					// out   [DVI] ch1-p tmds33(CML)/lvds
	.DVI_TX2_N(),					// out   [DVI] ch2-n tmds33(CML)/lvds
	.DVI_TX2_P(),					// out   [DVI] ch2-p tmds33(CML)/lvds
	.DVI_TXC_N(),					// out   [DVI] clk-n tmds33(CML)/lvds
	.DVI_TXC_P(),					// out   [DVI] clk-p tmds33(CML)/lvds
	.DVI_TX_SDA(),					// inout [DVI] dcc sda
	.DVI_TX_SCL(),					// inout [DVI] dcc scl
	.DVI_TX_CEC(),					// inout [DVI] cec
	.DVI_TX_HPD(1'b1),				// in    [DVI] detect

	.DVI_RX0_N(),					// out   [DVI] ch0-n tmds33(CML)/lvds
	.DVI_RX0_P(),					// out   [DVI] ch0-p tmds33(CML)/lvds
	.DVI_RX1_N(),					// out   [DVI] ch1-n tmds33(CML)/lvds
	.DVI_RX1_P(),					// out   [DVI] ch1-p tmds33(CML)/lvds
	.DVI_RX2_N(),					// out   [DVI] ch2-n tmds33(CML)/lvds
	.DVI_RX2_P(),					// out   [DVI] ch2-p tmds33(CML)/lvds
	.DVI_RXC_N(),					// out   [DVI] clk-n tmds33(CML)/lvds
	.DVI_RXC_P(),					// out   [DVI] clk-p tmds33(CML)/lvds
	.DVI_RX_SDA(),					// inout [DVI] dcc sda
	.DVI_RX_SCL(),					// inout [DVI] dcc scl
	.DVI_RX_CEC(),					// inout [DVI] cec
	.DVI_RX_HPD(1'b1),				// in    [DVI] detect

	.LCD_TX0_N(),					// out   [LCD] ch0-n lvds
	.LCD_TX0_P(),					// out   [LCD] ch0-p lvds
	.LCD_TX1_N(),					// out   [LCD] ch1-n lvds
	.LCD_TX1_P(),					// out   [LCD] ch1-p lvds
	.LCD_TX2_N(),					// out   [LCD] ch2-n lvds
	.LCD_TX2_P(),					// out   [LCD] ch2-p lvds
	.LCD_TX3_N(),					// out   [LCD] ch3-n lvds
	.LCD_TX3_P(),					// out   [LCD] ch3-p lvds
	.LCD_TXC_N(),					// out   [LCD] clk-n lvds
	.LCD_TXC_P(),					// out   [LCD] clk-p lvds

//	.TX_OE_N(1'b0),					// in    [RGB] tx #oe

	.TX_RED(TX_RED[7:0]),			// in    [RGB] red [7:0]
	.TX_GRN(TX_GRN[7:0]),			// in    [RGB] grn [7:0]
	.TX_BLU(TX_BLU[7:0]),			// in    [RGB] blu [7:0]
	.TX_HS(TX_HS),					// in    [RGB] #hsync
	.TX_VS(TX_VS),					// in    [RGB] #vsync
//	.TX_C0(TX_C0),					// in    [RGB] c0
//	.TX_C1(TX_C1),					// in    [RGB] c1
//	.TX_C2(TX_C2),					// in    [RGB] c2
//	.TX_C3(TX_C3),					// in    [RGB] c3
	.TX_DE(TX_DE),					// in    [RGB] de
	.TX_CLK(TX_CLK),				// in    [RGB] clock

	.sys_clk(CLK50),				// in    [SYS] clock
	.sys_rst_n(RST_N)				// in    [SYS] #reset
);

endmodule
