The following files were generated for 'textram' in directory 
C:\CVS\SP3A\SP3A-TMDS\coregen\:

textram_blk_mem_gen_v2_5_xst_1_vhdl.prj:
   Please see the core data sheet.

textram.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

textram.veo:
   VEO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a Verilog design.

textram.ngc:
   Binary Xilinx implementation netlist file containing the information
   required to implement the module in a Xilinx (R) FPGA.

textram.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

textram_xmdf.tcl:
   ISE Project Navigator interface file. ISE uses this file to determine
   how the files output by CORE Generator for the core can be integrated
   into your ISE project.

textram_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

textram_readme.txt:
   Text file indicating the files generated and how they are used.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

