Xilinx Design Summary

LYNX_DISP Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	629	1,408	44%
Number of 4 input LUTs	1,032	1,408	73%
Logic Distribution
Number of occupied Slices	702	704	99%
Number of Slices containing only related logic	575	702	81%
Number of Slices containing unrelated logic	127	702	18%
Total Number of 4 input LUTs	1,097	1,408	77%
Number used as logic	1,032
Number used as a route-thru	65
Number of bonded IOBs	54	108	50%
IOB Flip Flops	27
IOB Master Pads	8
IOB Slave Pads	8
Number of ODDR2s used	9
Number of GCLKs	4	24	16%
Number of DCMs	2	2	100%
Total equivalent gate count for design	27,276
Additional JTAG gate count for IOBs	2,592

Performance Summary
Final Timing Score:	8409	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	1 Failing Constraint