Xilinx Design Summary

LYNX_RGB Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	161	1,408	11%
Number of 4 input LUTs	136	1,408	9%
Logic Distribution
Number of occupied Slices	113	704	16%
Number of Slices containing only related logic	113	113	100%
Number of Slices containing unrelated logic	0	113	0%
Total Number of 4 input LUTs	136	1,408	9%
Number of bonded IOBs	70	108	64%
IOB Flip Flops	4
IOB Master Pads	4
IOB Slave Pads	4
Number of ODDR2s used	1
Number of GCLKs	3	24	12%
Number of DCMs	1	2	50%
Total equivalent gate count for design	9,176
Additional JTAG gate count for IOBs	3,360

Performance Summary
Final Timing Score:	39	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	1 Failing Constraint