// --------------------------------------------------------------------------------------------
// © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, 
// patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All 
// other trademarks and registered trademarks are the property of their respective owners. 
// All specifications are subject to change without notice.
// --------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------
// 
// 
// Constant Mutliplier for RGB to YCbCr Conversion
//
// Benoit Payette, Xilinx AE, Montreal 
// July 09, 2002
// 
// SynplifyPRO v7.1 for synthesis
// MTI v5.6 for simulation
//
// This file is the Verilog const_mult
//
// Description: This is a parameterizable constant multiplier
//
//

`timescale 1ns / 10ps

module xapp637_const_mult 
(
  Clock,
  ClockEnable,
  Reset,
  Color,
  Color_Out
);

  parameter IN_SIZE   =  8;
  parameter OUT_SIZE  = 16;  // output size width (integer)
  parameter CST_MULT  = 66;  // constant multiplicand (integer)

  input Clock; 
  input ClockEnable; 
  input Reset; 
  input [ (IN_SIZE - 1):0] Color; 
  output[(OUT_SIZE - 1):0] Color_Out; 

  reg   [(OUT_SIZE - 1):0] Color_Out;

// ------------------------------
// RTL code for COLOR_KCM process
// ------------------------------
  always @(posedge Clock or posedge Reset)
  begin : COLOR_KCM
    if (Reset)
      Color_Out <= 0; 
    else if (ClockEnable)
      Color_Out <= CST_MULT * Color; 
   end 


endmodule
