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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file xil_dpram_2048x8.v when simulating
// the core, xil_dpram_2048x8. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module xil_dpram_2048x8(
	clka,
	dina,
	addra,
	wea,
	clkb,
	addrb,
	doutb);


input clka;
input [7 : 0] dina;
input [10 : 0] addra;
input [0 : 0] wea;
input clkb;
input [10 : 0] addrb;
output [7 : 0] doutb;

// synthesis translate_off

      BLK_MEM_GEN_V2_6 #(
		.C_ADDRA_WIDTH(11),
		.C_ADDRB_WIDTH(11),
		.C_ALGORITHM(0),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("spartan3"),
		.C_HAS_ENA(0),
		.C_HAS_ENB(0),
		.C_HAS_MEM_OUTPUT_REGS_A(0),
		.C_HAS_MEM_OUTPUT_REGS_B(0),
		.C_HAS_MUX_OUTPUT_REGS_A(0),
		.C_HAS_MUX_OUTPUT_REGS_B(1),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_SSRA(0),
		.C_HAS_SSRB(0),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_MUX_PIPELINE_STAGES(0),
		.C_PRIM_TYPE(3),
		.C_READ_DEPTH_A(2048),
		.C_READ_DEPTH_B(2048),
		.C_READ_WIDTH_A(8),
		.C_READ_WIDTH_B(8),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_SINITA_VAL("0"),
		.C_SINITB_VAL("0"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_USE_RAMB16BWER_RST_BHV(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(2048),
		.C_WRITE_DEPTH_B(2048),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("WRITE_FIRST"),
		.C_WRITE_WIDTH_A(8),
		.C_WRITE_WIDTH_B(8),
		.C_XDEVICEFAMILY("spartan3a"))
	inst (
		.CLKA(clka),
		.DINA(dina),
		.ADDRA(addra),
		.WEA(wea),
		.CLKB(clkb),
		.ADDRB(addrb),
		.DOUTB(doutb),
		.ENA(),
		.REGCEA(),
		.SSRA(),
		.DOUTA(),
		.DINB(),
		.ENB(),
		.REGCEB(),
		.WEB(),
		.SSRB(),
		.DBITERR(),
		.SBITERR());


// synthesis translate_on

endmodule

