/************************************************************************/
/* lpc2388def.hファイル                                                 */
/* CPU(LPC2388) 関連ヘッダファイル                                      */
/************************************************************************/
#ifndef _lpc2388def_h_
#define _lpc2388def_h_

/* PIN mode register values */

#define PIN_MODE_PULL_UP   0
#define PIN_MODE_NO_PULLS  2
#define PIN_MODE_PULL_DOWN 3
#define PIN_MODE_MASK      3

#define PINMODE_GET_0_TO_15(PIN_NUMBER,PIN_MODE)\
	((PIN_MODE)<<PIN_NUMBER)

#define PINMODE_GET_16_TO_31(PIN_NUMBER,PIN_MODE)\
	((PIN_MODE)<<(PIN_NUMBER-16))

/* PINSEL P00..P015 0 masks */

#define	PS0_P00_SDA1_MASK				(3<<0)
#define	PS0_P01_SCL1_MASK				(3<<2)
#define PS0_P02_TXD0_MASK				(3<<4)
#define PS0_P03_RXD0_MASK				(3<<6)
#define PS0_P015_TXD1_SCK0_SCK_MASK			(3<<30)

/* PS 0 functions */

#define PS0_P02_TXD0     (1<<4)
#define PS0_P03_RXD0	 (1<<6)
#define PS0_P015_TXD1    (1<<30)

/* PINSEL 1 P016 P031 masks */

#define PS1_P016_RXD1_SSEL0_SSEL_MASK	    (3)
#define PS1_P017_CTS_MISO0_MISO_MASK	    (3<<2)
#define PS1_P018_DCD_MOSI0_MOSI_MASK	    (3<<4)
#define PS1_P019_DSR_MCICLK_SDA1_MASK	    (3<<6)
#define PS1_P020_DTR_MCISMD_RCL1_MASK	    (3<<8)

#define PS1_P022_RTS_MCIDAT0_TD1						(3<<12)
/* PINSEL 1 functions */

#define PS1_P016_RXD1		 (1)
#define PS1_P017_CTS		 (1<<2)
#define PS1_P018_DCD		 (1<<4)
#define PS1_P019_DSR		 (1<<6)
#define PS1_P020_DTR		 (1<<8)

/* PINSEL 2 1.00 ... P1.15 masks */
/* *PINSEL 2 functions */

/* PINSEL 3 1.16 ... P1.31 masks */
/* *PINSEL 3 functions */

/* PINSEL 4 2.00 ... P2.15 masks */
/* *PINSEL 4 functions */

/* PINSEL 5 2.16 ... P2.31 masks */
/* *PINSEL 5 functions */


/* PINSEL 6 3.00 ... P3.15 masks */
/* *PINSEL 6 functions */

/* PINSEL 7 3.16 ... P3.31 masks */
#define PS7_P316_D16_PWM01_TXD1_MASK	 (3)
#define PS7_P317_D17_PWM02_RXD1_MASK	 (3<<2)
#define PS7_P318_D18_PWM03_CTS1_MASK	 (3<<4)
#define PS7_P319_D19_PWM04_DCD1_MASK	 (3<<6)
#define PS7_P320_D20_PWM05_DSR1_MASK	 (3<<8)
#define PS7_P321_D21_PWM06_DTR1_MASK	 (3<<10)
#define PS7_P322_D22_PCAP00_RI1_MASK	 (3<<12)
#define PS7_P323_D23_CAP00_PCAP10_MASK	 (3<<14)

#define PS7_P330_D30_MAT11_RTS1_MASK	 (3<<28)

/* *PINSEL 7 functions */
#define PS7_P316_TXD1     		(3)
#define PS7_P317_RXD1			(3<<2)
#define PS7_P318_CTS1			(3<<4)
#define PS7_P319_DCD1			(3<<6)
#define PS7_P320_DSR1			(3<<8)
#define PS7_P321_DTR1			(3<<10)
#define PS7_P322_RI1			(3<<12)

#define PS7_P330_RTS1			(3<<28)

#define MSEL_MASK			 0x7FFF /*MSEL Read-back for the PLL Multiplier value. 
																This is the value currently used by the PLL, 
																and is one less than the actual multiplier.*/
#define NSEL_MASK      0xFF0000 /*NSEL Read-back for the PLL Pre-Divider value. This is the value currently
  																used by the PLL, and is one less than the actual divider.*/

/* PLL enable and connect bit */
#define PLLE		(0x01)
#define PLLC		(0x02)

#define PLLSTAT_ENABLE    (1<<24) /* PLL Enable bit.*/
#define PLLSTAT_CONNECT   (1<<25) /* When PLLC and PLLE are both one, the PLL is connected as the clock source for the LPC2400.*/
#define PLOCK         (1<<26) /* When one, the PLL is locked onto the requested frequency.*/

/* PCONP register values
   at the end of the comment are the values after reset
	 A means the peripheral block is enabled
*/
#define PCTIM0 	(1<<1) /* Timer/Counter 0 power/clock control bit. 1 */
#define PCTIM1 	(1<<2) /* Timer/Counter 1 power/clock control bit. 1 */
#define PCUART0 (1<<3) /* UART0 power/clock control bit. 1 */
#define PCUART1	(1<<4) /* PCUART1 UART1 power/clock control bit. 1 */

#define PCI2C1 	(1<<19) /* PCI2C1 The I2C1 interface power/clock control bit. 1 */
#define PCSSP0 	(1<<21) /* The SSP0 interface power/clock control bit. 1 */
#define PCTIM2 	(1<<22) /* Timer 2 power/clock control bit. 0	*/
#define PCTIM3	(1<<23) /* Timer 3 power/clock control bit. 0  */
#define PCUART2 (1<<24) /* UART 2 power/clock control bit. 0 */
#define PCUART3	(1<<25) /* UART 3 power/clock control bit. 0 */
#define PCI2C2	(1<<26) /* I2S interface 2 power/clock control bit. 1 */
#define PCI2S 	(1<<27) /* I2S interface power/clock control bit. 0 */
#define PCSDC		(1<<28) /* SD card interface power/clock control bit. 0	*/
#define PCGPDMA (1<<29) /* GP DMA function power/clock control bit. 0 */
#define PCENET 	(1<<30) /* Ethernet block power/clock control bit. 0 */


#define CLKSRC_MASK      (0x03)   /* CLKSRCSEL CLKSRC MASK */
#define CLKSRC_RC_OSC    (0x0)   /* internal RC ca. 4Mhz */
#define CLKSRC_MAIN_OSC  (0x01)	 /* main oscillator */
#define CLKSRC_RTC_OSC   (0x02)	 /* RTC oscillator integrated RTC */

#define PCLKSEL0_UART0_MASK (3<<6)
#define PCLKSEL0_UART1_MASK (3<<8)
#define PCLKSEL1_UART2_MASK (3<<16)
#define PCLKSEL1_UART3_MASK (3<<18)

#define PCLKSEL_TIMER_MASK (0x03)

#define PCLKSEL_DIV_1		1
#define PCLKSEL_DIV_2		2
#define PCLKSEL_DIV_4		0
#define PCLKSEL_DIV_8		3 		/* pll output clock divide by 8 not cpi clock */


#define PCLKSEL0_UART0(PCLK_DIV)\
	((PCLK_DIV)<<6)
#define PCLKSEL0_UART1(PCLK_DIV)\
	((PCLK_DIV)<<8)

#define PCLKSEL1_UART2(PCLK_DIV)\
	((PCLK_DIV)<<16)
#define PCLKSEL1_UART3(PCLK_DIV)\
	((PCLK_DIV)<<18)

#define SCS_GPIO_HIGH_SPEED (0x01)
#define SCS_EXT_MEM_RESET_DISABLE (0x02)  /* disable reset of external memory controller */
#define SCS_MCIPWR_PIN_ACTIVE_HIGH (1<<3)
/* Main oscillator range select.
	0 The frequency range of the main oscillator is 1 MHz to 20 MHz.
	1 The frequency range of the main oscillator is 15 MHz to 24 MHz.
*/
#define SCS_OSCRANGE (1<<4) 
/* OSCEN Main oscillator enable. */
#define SCS_OSCEN (1<<5)   
/*
main oscillator status 
0 The main oscillator is not ready to be used as a clock source.
1 The main oscillator is ready to be used as a clock source. The main
	oscillator must be enabled via the OSCEN bit.
*/
#define SCS_OSCSTAT (1<<6)   

/* UART fractional register macros*/
#define UFDR_GETMULVAL(Mulval)\
	((Mulval)<<4)

/* UART LCR line control register values */

#define LCR_5_DATABITS	0x00 /*5 bit character length 0*/
#define LCR_6_DATABITS	0x01 /*6 bit character length */
#define LCR_7_DATABITS	0x02 /*7 bit character length*/
#define LCR_8_DATABITS	0x03 /*8 bit character length*/
#define LCR_2_STOPBITS  0x04  /* 1.5 or 2 stop bits */ 

#define LCR_ENABLE_PARITY 0x08 /* enable  parity generation and checking */

#define LCR_ODD_PARITY				0
#define LCR_EVEN_PARITY				(1<<4)
#define LCR_FORCED_1_PARITY   (2<<4)
#define LCR_FORCED_0_PARITY   (3<<4)

#define LCR_ENABLE_BREAK      (1<<6)/* Enable break transmission.
                                       output pin UART0 TXD is forced to logic 0. */
#define LCR_DVISOR_LATCH      (1<<7) /* DLAB bit 1=Enable access to Divisor Latches*/

#define __UART0_BASE   0xE000C000
#define __UART1_BASE   0xE0010000
#define __UART2_BASE   0xE0078000
#define __UART3_BASE   0xE007C000

#define __UART_RBR_OFFS    0x00
#define __UART_THR_OFFS    0x00
#define __UART_DLL_OFFS    0x00
#define __UART_DLM_OFFS    0x04
#define __UART_IER_OFFS    0x04
#define __UART_IIR_OFFS    0x08
#define __UART_FCR_OFFS    0x08
#define __UART_LCR_OFFS    0x0C  
#define __UART_MCR_OFFS    0x10 /* UART1 */  
#define __UART_LSR_OFFS    0x14
#define __UART_MSR_OFFS    0x18 /* UART1 */
#define __UART_SCR_OFFS    0x1C
#define __UART_ACR_OFFS    0x20
#define __UART_ICR_OFFS    0x24 /* UART 0,2,3*/
#define __UART_FDR_OFFS    0x28
#define __UART_TER_OFFS    0x30

#define U1MCR_DTR	0x01 /* Source for modem output pin */
#define U1MCR_CTS	0x02 /* Source for modem output pin */


/* interrupt channels */

#define WDT_CHANNEL  0 /*WDT Watchdog Interrupt*/
#define SOFT_CHANNEL 1  /*Reserved for Software Interrupts only*/
//ARM Core Embedded ICE
#define DBG_COMMRX_CHANNEL 2
#define DBG_COMMTX_CHANNEL 3
#define TIMER0_CHANNEL 4
#define TIMER1_CHANNEL 5
#define UART0_CHANNEL 6
#define UART1_CHANNEL 7
#define PWM_01_CHANNEL 8
#define I2C_STATE_CHANGE_CHANNEL 9
#define SPI_SSP0_CHANNEL 10
#define SSP1_CHANNEL 11
#define PLL_CHANNEL  12
#define RTC_CHANNEL  13
#define EINT0_CHANNEL  14
#define EINT1_CHANNEL  15
#define EINT2_CHANNEL  16
#define EINT3_CHANNEL  17
#define ADC0_CHANNEL  18
#define I2C1_CHANNEL  19
#define BOD_CHANNEL  20
#define ETHERNET_CHANNEL  21
#define USB_CHANNEL  22
#define CAN_CHANNEL  23
#define SD_MMC_CHANNEL  24
#define GP_DMA_CHANNEL  25
#define TIMER2_CHANNEL  26
#define TIMER3_CHANNEL  27
#define UART2_CHANNEL  28
#define UART3_CHANNEL  29
#define I2C2_CHANNEL  30
#define I2S_CHANNEL  31


#define VIC_VECT_PRIORITY_MASK 0x0f

/************************/
/* USB specific defines */
/************************/


/* 16 kbyte length */
#define USB_RAM_ADDR	0x7FD00000
#define USB_RAM_SIZE	0x4000


/*	register PCONP */
#define PCUSB 	((unsigned long)1<<31) /* USB interface power/clock 0 */

/* USB clock configuration,
   allowed clock control bits in register USBCLKCFG */
#define USBCLKCFG_MASK      0x0f			/* allowed bits */


/* USB interrupt status register USB_INT_STAT */
#define USB_INT_REQ_LP (1<<0)  /*Low priority interrupt line status. This bit is read only. 0*/
#define USB_INT_REQ_HP (1<<1)	  /*High priority interrupt line status. This bit is read only. 0*/
#define USB_INT_REQ_DMA (1<<2)	/* DMA interrupt line status. This bit is read only. 0 */
#define USB_HOST_INT		(1<<3) 	/* USB host interrupt line status. This bit is read only. */
#define USB_ATX_INT			(1<<4) 	/*External ATX interrupt line status. This bit is read only. 0*/
#define USB_OTG_INT			(1<<5) 	/*OTG interrupt line status. This bit is read only. 0*/
#define USB_I2C_INT			(1<<6)  /*I2C module interrupt line status. This bit is read only. 0*/
#define USB_NEED_CLK    (1<<8)	/*USB_NEED_CLK USB need clock indicator. This bit is read only. ??*/

/* USB PIN selection masks */

/*** PINSEL0 ***/

/*Port Power enable signal for USB port 2. */
#define PS0_P012_USB_PPWR2  (1<<24)  
/* USB port 2 GoodLink LED indicator.
	 It is LOW when
	 device is configured (non-control endpoints enabled).
	 It is HIGH when the device is not configured or during global suspend.
*/
#define PS0_P013_USB_UP_LED2  (1<<26)

/* Host Enabled status for USB port 2.*/
#define PS0_P014_USB_HSTEN2  (1<<28)
/* USB device SoftConnect control for USB port 2.*/
#define PS0_P014_USB_CONN2  (2<<28)

/*** PINSEL1 ***/

/* USB port 1 bidirectional D+ line. */
#define PS1_P029_USB_DP1  (1<<26)
/*USB port 1 bidirectional D-line, USB DM2 has an own pin! */
#define PS1_P030_USB_DM1  (1<<28)
/* USB port 2 bidirectional D+ Line*/
#define PS1_P031_USB_DP2  (1<<30)

/*** PINSEL3 ***/

/* USB port 1 GoodLink LED indicator. It is LOW when
device is configured (non-control endpoints enabled).*/
#define PS3_P118_USB_UP_LED1 (1<<4)

/* Transmit Enable signal for USB port 1 (OTG transceiver). */
#define PS3_P119_USB_TX_E1  (1<<6)
/* Port Power enable signal for USB port 1. */
#define PS3_P119_USB_PPWR1  (2<<6)

/***** OTG TRANCEIVER and Port 1 Power Overcurrent ****/

/* D+ transmit data for USB port 1 (OTG transceiver). */
#define PS3_P120_USB_TX_DP1  (1<<8)
/* D- transmit data for USB port 1 (OTG transceiver).*/
#define PS3_P121_USB_TX_DM1  (1<<10)

/* Differential receive data for USB port 1 (OTG transceiver). */
#define PS3_P122_USB_RCV1  (1<<12)
/* Power Status for USB port 1 (host power switch). */
#define PS3_P122_USB_PWRD1 (2<<12)

/* D+ receive data for USB port 1 (OTG transceiver). */
#define PS3_P123_USB_RX_DP1  (1<<14)
/*D- receive data for USB port 1 (OTG transceiver).*/
#define PS3_P124_USB_RX_DM1  (1<<16)

/* Low-speed status for USB port 1 (OTG transceiver). */
#define PS3_P125_USB_LS1    (1<<18)
/* Host Enabled status for USB port 1. */
#define PS3_P125_USB_HSTEN1 (2<<18)

/*USB port 1 Bus Suspend status (OTG transceiver). */
#define PS3_P126_USB_SSPND1 (1<<20)

/* USB port 1 OTG ATX interrupt (OTG transceiver). */
#define PS3_P127_USB_INT1  (1<<22)
/* USB port 1 Over-Current status. */
#define PS3_P127_USB_OVRCR1 (2<<22)

/*USB port 1 I2C serial clock (OTG transceiver). */
#define PS3_P128_USB_SCL1  (1<<24)
/* USB port 1 I2C serial data (OTG transceiver). */
#define PS3_P129_USB_SDA1  (1<<26)

/***** Port 2 Power Overcurrent ****/

/* Power Status for USB port 2. */
#define PS3_P130_USB_PWRD2 (1<<28)
/* Indicates the presence of USB bus power. */
#define PS3_P130_USB_VBUS (2<<28)

/* Over-Current status for USB port 2. */
#define PS3_P131_USB_OVECR2  (1<<30)

/* USB clock control 
   USBClkCtrl reg. OTG clock control register,
	 also referred as OTG clock control register!!!	 
*/   
#define USB_HOST_CLK_EN	(1<<0)
#define USB_DEV_CLK_EN	(1<<1)
#define USB_I2C_CLK_EN	(1<<2)
#define USB_OTG_CLK_EN	(1<<3)
#define USB_AHB_CLK_EN	(1<<4)



/* OTG Status Control register (OTGStCtrl*/

#define OTCTRL_PORT_FUNC 0x03
#define OTCTRL_PORT2_HOST 0x00
#define OTCTRL_PORT12_HOST 0x01
#define OTCTRL_PORT1_HOST 0x03


/****************************/
/* ADC DAC specific defines */
/****************************/

/*	register PCONP */
#define PCAD 	((unsigned long)1 << 12)                                /* A/D D/Aコンバータ power/clock 0 */

#define PS1_P0_25   (1 << 18)                                           /* A/D D/Aコンバータ PINファンクション */
#define T0TCR_CE    (1 << 0)                                            /* タイマ０カウンタ */
#define T0TCR_CR    (1 << 1)                                            /* タイマ０カウンタリセット解除 */
#define T0CTCR_CTM  0x03                                                /* タイマ動作モード設定：PCLKの立ち上がりエッジ */
#define T0MCR_MR0I  (1 << 0)                                            /* MR0割り込み許可 */
#define T0MCR_MR0R  (1 << 1)                                            /* MR0リセット */
#define T0MCR_MR0S  (1 << 2)                                            /* MR0リセット解除 */
#define AD0CR_START (1 << 24)                                           /* A/D変換を開始 */
#define PS1_P0_26   (2 << 20)                                           /* D/Aコンバータ PINファンクション */

#define TIMER0_PCLK_OFFSET      2

#endif //#define _lpc2388def_h_
