HDL04

AeMegaWizardуUCNXCORE Generatorō쐬t@ĆAꂼ̃c[K肷郉CZXɏ]܂B

DVI TMDSGR[h/fR[h̃ASYDDWGLĂ܂B
dvi_data_enc.vdvi_data_dec.v́ADDWGJdlɎ̂łB
pɍۂĂDDWG̃CZXɏ]܂B

҂쐬t@ĆA{I"as-is"CZXłB
gpɍۂĂ̐͂܂B
Agp̍ۂɕsĂȂۏ؂Ȃ܂B

 ms104_nios2_crt_q9 : ms104 cyclone3 dvi with nios2 synthesis

At@vWFNg MS104-FPGA/C3DVIo͂Ȃ܂B
Cyclone3LVDSo͂OTMDSɕϊ܂B

rfIRg[[Nios2uClinuxT|[gĂ̂gpĂ܂B
Nios2uClinuxɂĂ͈ȉ̃TCgQƂĂB

http://www.nioswiki.com
http://www.niosforum.com

 arria_disp_640x480_dvi : CQ-AGX20 dvi output simulation and synthesis

CQoŎА Arria GX]LbgDVIo͂Ȃ܂B


zzt@C

ms104_nios2_crt_q9\
	eagle\			: H}
		LYNX-104D.sch	: MS104 p
		sp3a-cml.sch	: LVDS-TMDSϊ
		N2SCUSB-A2.sch	: ISP1362 USB
	software\		: FatFs Nios2(SOPC Builder SPI)ڐA
	ms104_nios2_crt.qpf	: Ae Quartus2 vWFNgt@C
	ms104_nios2_crt.qsf	: Ae Quartus2 vWFNgt@C
	ms104_nios2_crt.v	: top
	alt_clkbuf.v		: SDRAMp NbNobt@
	alt_ddio_bidir.v	: SDRAMp NbNhCo
	alt_dvi.v		: Aep DVIW[
	dvi_data_enc.v		: TMDS GR[hW[
	alt_dvi_out_x4_raw.v	: DVIp serdes
	alt_pll_40x25x125.v	: DVIp PLL
	alt_pll_40x100.v	: SDRAMp PLL

	nios2_crt.ptf		: Nios2 PTF
	nios2_crt.sopc		: Nios2 SOPC

arria_disp_640x480_dvi\
	arria_dvi.qpf		: Ae Quartus2 vWFNgt@C
	arria_dvi.qsf		: Ae Quartus2 vWFNgt@C
	arria_dvi.v		: top
	alt_alt2gxb_x4.v	: alt2gxb DVIo͗p
	alt_clkbuf.v		: NbNobt@
	dvi_data_enc.v		: TMDS GR[hW[
	dispgen_vga.v		: 640x480(VGA)

	arria_dvi_tb.v		: V~[VpeXgx`
	arria_dvi.vtakprj	: veritak vWFNgt@C
	sim_altera_inc.v	: V~[Vpt@C


