HDL05

AeMegaWizardуUCNXCORE Generatorō쐬t@ĆAꂼ̃c[K肷郉CZXɏ]܂B

҂쐬t@ĆA{I"as-is"CZXłB
gpɍۂĂ̐͂܂B
Agp̍ۂɕsĂȂۏ؂Ȃ܂B

 arria_disp_640x480_dp : Arria GX]Lbgp simulaton and synthesis

Arria GX]LbgpDisplayPort\TvłB

 arria_disp_loop_10jan24_4lane : 

Arria GX]LbgpDisplayPort\f[^͗pTvłB
MainStreamAttributeoĎ荞݂܂B

 arria_disp_loop_10jan27_1lane : 

Arria GX]LbgpDisplayPort\f[^͗pTvłB
DispSWŃgKw肵ăf[^荞݂܂B

zzt@C

lynx-05-10-aR5xBE.PNG		: aR5x BEgK̔g` arria_disp_loop_10jan27_1lanegp
lynx-05-10-aR5xSS.PNG		: aR5x MSA̔g` arria_disp_loop_10jan24_4lanegp
lynx-05-10-iG4xBE.PNG		: iG4x BEgK̔g` arria_disp_loop_10jan27_1lanegp
lynx-05-10-iG4xSS.PNG		: iG4x MSA̔g` arria_disp_loop_10jan24_4lanegp
ss_g43.txt			: MSA iG4x
ss_r5.txt			: MSA aR5x

arria_disp_640x480_dp\
	sim_altera\		: Ae V~[Vpt@C

	arria_lvds.qpf		: Ae QuartusII vWFNgt@C
	arria_lvds.qsf		: Ae QuartusII vWFNgt@C
	arria_lvds.v		: top
	alt_clkbuf.v		: 
	alt_ddio_bidir.v	: 
	alt_pll_27x162.v	: PLL

	dp_main_linkup.v	: AUX-CH NAbv
	dp_aux_tx.v		: AUX-CH M
	dp_aux_rx.v		: AUX-CH M

	dispgen.v		: \p^[
	dp_main_crtc.v		: CRTC
	dp_main_tbc.v		: DP TBC+PACK
	dp_main_scramble.v	: DP SCRAMBLE
	alt_ram_dp108x256.v	: TBCpFIFO

	alt_alt2gxb_tx4.vo	: MgV[o[

	arria_lvds.vtakprj	: veritak vWFNgt@C
	arria_lvds_tb.v		: V~[VpeXgx`
	dp_sink_aux_rx.v	: V~[Vp AUX-CH SINK
	dp_sink_aux_tx.v	: V~[Vp AUX-CH SINK
	xil_8b10b_enc.v		: 
	ENCODE_8B10B_V5_0.v	: 
	alt_alt2gxb_rx1.vo	: V~[Vp MgV[o[

arria_disp_loop_10jan24_4lane\
	arria_lvds.qpf		: Ae QuartusII vWFNgt@C
	arria_lvds.qsf		: Ae QuartusII vWFNgt@C
	arria_lvds.v		: top
	alt_clkbuf.v		: 
	alt_ddio_bidir.v	: 
	alt_pll_27x81.v		: PLL
	alt_alt2gxb_loop.v	: [vobNgV[o[

arria_disp_loop_10jan27_1lane\
	arria_lvds.qpf		: Ae QuartusII vWFNgt@C
	arria_lvds.qsf		: Ae QuartusII vWFNgt@C
	arria_lvds.v		: top
	alt_clkbuf.v		: 
	alt_ddio_bidir.v	: 
	alt_pll_27x81.v		: PLL
	alt_alt2gxb_loop.v	: [vobNgV[o[
	alt_ram_dp_36x8k.v	: 荞ݗpFIFO
	dp_aux_rx.v		: AUX-CH SOURCEMp
	dp_sink_aux_rx.v	: AUX-CH SINKMp
