Interface2010N89f

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@SH-2A/SH2A-FPUpTvEvOQ


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test_regbank--+--01_non_bank WX^oNgpȂLED̓_vO
              +--02_use_bank WX^oNgpLED̓_vO
@SH7262CPU{[hgp

test_fpu--+--01_sh2a_float      SH-2Aɂfloat^sinf/cosf]vO
          +--02_sh2a_double     SH-2Aɂdouble^sin/cos]vO
          +--03_sh2a_fpu_float  SH2A-FPUɂfloat^sinf/cosf]vO
          +--04_sh2a_fpu_double SH2A-FPUɂdouble^sin/cos]vO
          +--05_sh2a_fpu_single SH2A-FPU(SingleIvVw)ɂfloat^sinf/cosf]vO
          +--06_sh2a_fpu_double SH2A-FPU(doubleIvVw)ɂdouble^sin/cos]vO
@SH7262CPU{[hgp

warning_fpu--+--01_use_suffix ڔqȂ̕_萔̕]vO
             +--02_non_suffix ڔq̕_萔̕]vO
             +--03_non_ifunc  ifuncwȂ̊荞݊֐̕]vO
             +--04_use_ifunc  ifuncw肠̊荞݊֐̕]vO
@0102̓V~[^gpA0304SH7262CPU{[hgp

test_cache--+--01_non_cache        LbV̕]vO
            +--02_use_cache        LbVL̕]vO
            +--03_non_cache_vram   LbV̈悩VRAMvO
            +--04_use_cache_vram   LbVL̈悩VRAMvO
            +--05_purge_cache_vram p[WtLbVL̈悩VRAMvO
@SH7262CPU{[hgp

cache_sample-----SH7262pLbṼTvvO

test_option--+--01_non_align16    aling16IvVݒ̃vO
             +--02_use_align16    aling16IvVݒ̃vO
             +--03_non_align4     aling4IvVݒ̃vO
             +--04_use_align4     aling4IvVݒ̃vO
             +--05_use_align4_16  aling4+16IvVݒ̃vO
             +--06_non_map        mapIvVݒ̃vO
             +--07_use_map        mapIvVݒ̃vO
             +--08_non_loop       loopIvVݒ̃vO
             +--09_use_loop       loopIvVݒ̃vO
             +--10_max_unroll     max_unrollIvVݒ̃vO
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