HDL06

AeMegaWizardуUCNXCORE Generatorō쐬t@ĆAꂼ̃c[K肷郉CZXɏ]܂B

҂쐬t@ĆA{I"as-is"CZXłB
gpɍۂĂ̐͂܂B
Agp̍ۂɕsĂȂۏ؂Ȃ܂B

 arria_disp_640x480_dp1 : mainlink x1 simulation and synthesis

Arria GX]Lbgp̃CN x1[ TvłB
CRTC1\^C~Ô܂ܕ\Ɏgp܂B


zzt@C

arria_disp_640x480_dp1\
	sim_altera\		: Ae V~[Vpt@C

	arria_lvds.qpf		: Ae QuartusII vWFNgt@C
	arria_lvds.qsf		: Ae QuartusII vWFNgt@C
	arria_lvds.v		: top
	alt_clkbuf.v		: 
	alt_ddio_bidir.v	: 
	alt_pll_27x162.v	: PLL

	dp_main_linkup1.v	: AUX-CH NAbv x1[Ή
	dp_aux_tx.v		: AUX-CH M
	dp_aux_rx.v		: AUX-CH M

	dispgen.v		: \p^[ (gp)
	dp_main_crtc1.v		: CRTC x1[Ή
	dp_main_tbc.v		: DP TBC+PACK (gp)
	dp_main_scramble.v	: DP SCRAMBLE
	alt_ram_dp108x256.v	: TBCpFIFO

	alt_alt2gxb_tx4.vo	: MgV[o[

	arria_lvds.vtakprj	: veritak vWFNgt@C
	arria_lvds_tb.v		: V~[VpeXgx`
	dp_sink_aux_rx.v	: V~[Vp AUX-CH SINK
	dp_sink_aux_tx.v	: V~[Vp AUX-CH SINK
	xil_8b10b_enc.v		: 
	ENCODE_8B10B_V5_0.v	: 

