

                    Core Name: Xilinx Virtex-5 GTP Transceiver Wizard
                    Version: 1.8
                    Release Date: March 24, 2008


===============================================================================

This document contains the following sections:

1. Introduction
2. New Features
3. Resolved Issues
4. Known Issues
5. Technical Support
6. Core Release History

===============================================================================

1. INTRODUCTION

For the most recent updates to the IP installation instructions for this core,
please go to:

   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm


For system requirements:

   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm



This file contains release notes for the Xilinx LogiCORE Virtex-5 GTP
Transceiver Wizard v1.8. For the latest core updates, see the product
page at:

   http://www.xilinx.com/products/ipcenter/V5_RocketIO_Wizard.htm


2. NEW FEATURES

   - ISE 10.1 software support
   - Virtex-5 SX240T package support
   - IPProtect (secureip) libraries support
   - Xilinx ISE Simulator (ISim) support
   - SRIO single lane, multilane protocols support


3. RESOLVED ISSUES

   - No error message if design fails to meet timing - The current build
     script will always produce a bit file if PAR fails to meet timing.
      - CR442193
        Script used for Implementation has been updated to give a warning
        when timing fails in PAR.

   - Enable SATA auto-negotiation option not present in Wizard - This option
     is not available if RXSTATUS encoding format is set to PCI Express.
      - CR447749
        GSUG updated with description for new parameter used to enable
        second-order loop.

   - Unknown terminology - "Transmitter swing turbo mode" terminology does not
     exist in other documentation.
      - CR451300
        GUI updated with new terminology: "Pre-emphasis Boost" instead of
        "Transmitter Swing Turbo mode".

   - Part selection causes error - Selecting V5LX20T-ff323 results in error:
     "At least one GTP_DUAL must be selected".
      - CR450121
        Hold-Time workaround not needed for LX20T (Production Silicon).

   - Missing design rule - When the TX buffer is bypassed, the Wizard does not
     ensure individual output dividers are set to 1 and TXCOMM_OUT is used.
      - CR451416
        TX Buffer can be bypassed only when GTP0 TX Line Rate equals GTP1 TX
        Line Rate.


4. KNOWN ISSUES

   The following are known issues for v1.8 of this core at time of release:

   - If you set the comma alignment smaller than the datapath width, incoming
     data can be aligned to multiple positions.  The example design does not
     account for this, and may indicate errors even though data is being
     received correctly.

   - In the case of Clock correction, the GTP wrapper in the Example design is
     configured correctly but the BRAM data does not have embedded
     Clock-correction characters.

   - In ES silicon, the logic added to make TX timing more reliable, timing
     closure at fabric rates of 312.5 MHz and higher may require significant
     effort.  For best results, use a 16 or 20 bit interface for line rates
     higher than 1.25 Gbps.

   - There is an issue with 10.1 where designs which use GREFCLK fail with a
     DRC error. To work around this, an enviroment variable called
     XIL_MAP_NO_GT_CLKIN_DRC needs to be set. Please refer to AR#25316 for
     more details. This variable has been set in the build_script.pl for
     designs using GREFCLK.

   - RX buffer bypass in Oversampling mode is not supported.

   The most recent information, including known issues, workarounds, and
   resolutions for this version is provided in the release notes Answer Record
   for the ISE 10.1 IP Update at

   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=29767


5. TECHNICAL SUPPORT

   To obtain technical support, create a WebCase at www.xilinx.com/support.
   Questions are routed to a team with expertise using this product.

   Xilinx provides technical support for use of this product when used
   according to the guidelines described in the core documentation, and
   cannot guarantee timing, functionality, or support of this product for
   designs that do not follow specified guidelines.


6. CORE RELEASE HISTORY

Date        By            Version      Description
===============================================================================
03/24/2008  Xilinx, Inc.  1.8          ISim,IPProtect,SRIO,SX240T support
10/10/2007  Xilinx, Inc.  1.7          Extended lxt package support
08/15/2007  Xilinx, Inc.  1.6          9.2i support
05/17/2007  Xilinx, Inc.  1.5          CPRI and OBSAI support
03/01/2007  Xilinx, Inc.  1.4          Extensive new features
11/30/2006  Xilinx, Inc.  1.3          Bug fixes
10/10/2006  Xilinx, Inc.  1.2          Initial release
===============================================================================


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