/*
 Produced by NSL Core, IP ARCH, Inc. Sat Dec 04 18:25:58 2010
 Licensed to yujiro_kaneko:overtone:zyangalianhamster01@gmail.com :EVALUATION USER:
*/

module timer7seg ( p_reset , m_clock , reset , seg1_o , seg2_o , seg_figure );
  input p_reset, m_clock;
  input reset;
  output [7:0] seg1_o;
  output [7:0] seg2_o;
  output [1:0] seg_figure;
  reg [31:0] cnt_1sec;
  reg [18:0] cnt_100Hz;
  reg [1:0] seg_figure_buffer;
  wire [7:0] _u_counter_0to9_seg0to9_o;
  wire [7:0] _u_counter_0to9_seg0to5_o;
  wire _u_counter_0to9_countup;
  wire _u_counter_0to9_reset;
  wire _u_counter_0to9_p_reset;
  wire _u_counter_0to9_m_clock;
  wire _net_0;
  wire _net_1;
  wire _net_2;
  wire _net_3;
  wire _net_4;
  wire _net_5;
  wire _net_6;
  wire _net_7;
  wire _net_8;
  wire _net_9;
  wire _net_10;
counter_0to9 u_counter_0to9 (.p_reset(p_reset), .m_clock(m_clock), .reset(_u_counter_0to9_reset), .countup(_u_counter_0to9_countup), .seg0to5_o(_u_counter_0to9_seg0to5_o), .seg0to9_o(_u_counter_0to9_seg0to9_o));

   assign #1 _u_counter_0to9_countup = _net_3;
   assign #1 _u_counter_0to9_reset = _net_2;
   assign #1 _net_0 = (cnt_1sec)==((32'b00000010111110101111000010000000)-(32'b00000000000000000000000000000001));
   assign #1 _net_1 = ~reset;
   assign #1 _net_2 = _net_0&_net_1;
   assign #1 _net_3 = _net_0&(~_net_1);
   assign #1 _net_4 = ~_net_0;
   assign #1 _net_5 = (cnt_100Hz)==(19'b1001001001111100000);
   assign #1 _net_6 = (seg_figure_buffer)==(2'b10);
   assign #1 _net_7 = _net_5&_net_6;
   assign #1 _net_8 = (seg_figure_buffer)==(2'b01);
   assign #1 _net_9 = _net_5&_net_8;
   assign #1 _net_10 = ~_net_5;
   assign #1 seg1_o = ~_u_counter_0to9_seg0to9_o;
   assign #1 seg2_o = ~_u_counter_0to9_seg0to5_o;
   assign #1 seg_figure = seg_figure_buffer;
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     cnt_1sec <= 32'b00000000000000000000000000000000;
else if ((_net_4)|(_net_0)) 
      cnt_1sec <= ((_net_4) ?(cnt_1sec)+(32'b00000000000000000000000000000001):32'b0)|
    ((_net_0) ?32'b00000000000000000000000000000000:32'b0);

end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     cnt_100Hz <= 19'b0000000000000000000;
else if ((_net_10)|(_net_5)) 
      cnt_100Hz <= ((_net_10) ?(cnt_100Hz)+(19'b0000000000000000001):19'b0)|
    ((_net_5) ?19'b0000000000000000000:19'b0);

end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     seg_figure_buffer <= 2'b01;
else if ((_net_9)|(_net_7)) 
      seg_figure_buffer <= ((_net_9) ?2'b10:2'b0)|
    ((_net_7) ?2'b01:2'b0);

end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Sat Dec 04 18:25:58 2010
 Licensed to yujiro_kaneko:overtone:zyangalianhamster01@gmail.com 
*/

module counter_0to9 ( p_reset , m_clock , seg0to9_o , seg0to5_o , countup , reset );
  input p_reset, m_clock;
  output [7:0] seg0to9_o;
  output [7:0] seg0to5_o;
  input countup;
  input reset;
  reg [3:0] counter;
  wire [7:0] _u_counter_0to5_seg0to5_o;
  wire _u_counter_0to5_countup;
  wire _u_counter_0to5_reset;
  wire _u_counter_0to5_p_reset;
  wire _u_counter_0to5_m_clock;
  wire [3:0] _u_hex_to_7segout_hexdata;
  wire [7:0] _u_hex_to_7segout_segdata_o;
  wire _u_hex_to_7segout_output7seg;
  wire _u_hex_to_7segout_p_reset;
  wire _u_hex_to_7segout_m_clock;
  wire _net_11;
  wire _net_12;
  wire _net_13;
  wire _net_14;
hex_to_7segout u_hex_to_7segout (.p_reset(p_reset), .m_clock(m_clock), .output7seg(_u_hex_to_7segout_output7seg), .segdata_o(_u_hex_to_7segout_segdata_o), .hexdata(_u_hex_to_7segout_hexdata));
counter_0to5 u_counter_0to5 (.p_reset(p_reset), .m_clock(m_clock), .reset(_u_counter_0to5_reset), .countup(_u_counter_0to5_countup), .seg0to5_o(_u_counter_0to5_seg0to5_o));

   assign #1 _u_counter_0to5_countup = _net_12;
   assign #1 _u_counter_0to5_reset = reset;
   assign #1 _u_hex_to_7segout_hexdata = counter;
   assign #1 _u_hex_to_7segout_output7seg = 1'b1;
   assign #1 _net_11 = (counter)==(4'b1001);
   assign #1 _net_12 = countup&_net_11;
   assign #1 _net_13 = countup&_net_11;
   assign #1 _net_14 = countup&(~_net_11);
   assign #1 seg0to9_o = _u_hex_to_7segout_segdata_o;
   assign #1 seg0to5_o = _u_counter_0to5_seg0to5_o;
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     counter <= 4'b0000;
else if ((_net_14)|(reset|_net_13)) 
      counter <= ((_net_14) ?(counter)+(4'b0001):4'b0)|
    ((reset|_net_13) ?4'b0000:4'b0);

end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Sat Dec 04 18:25:58 2010
 Licensed to yujiro_kaneko:overtone:zyangalianhamster01@gmail.com 
*/

module counter_0to5 ( p_reset , m_clock , seg0to5_o , countup , reset );
  input p_reset, m_clock;
  output [7:0] seg0to5_o;
  input countup;
  input reset;
  reg [2:0] counter;
  wire [3:0] _u_hex_to_7segout_hexdata;
  wire [7:0] _u_hex_to_7segout_segdata_o;
  wire _u_hex_to_7segout_output7seg;
  wire _u_hex_to_7segout_p_reset;
  wire _u_hex_to_7segout_m_clock;
  wire _net_15;
  wire _net_16;
  wire _net_17;
hex_to_7segout u_hex_to_7segout (.p_reset(p_reset), .m_clock(m_clock), .output7seg(_u_hex_to_7segout_output7seg), .segdata_o(_u_hex_to_7segout_segdata_o), .hexdata(_u_hex_to_7segout_hexdata));

   assign #1 _u_hex_to_7segout_hexdata = {1'b0,counter};
   assign #1 _u_hex_to_7segout_output7seg = 1'b1;
   assign #1 _net_15 = (counter)==(3'b101);
   assign #1 _net_16 = countup&_net_15;
   assign #1 _net_17 = countup&(~_net_15);
   assign #1 seg0to5_o = _u_hex_to_7segout_segdata_o;
always @(posedge m_clock)
  begin
if ((_net_17)|(reset|_net_16)) 
      counter <= ((_net_17) ?(counter)+(3'b001):3'b0)|
    ((reset|_net_16) ?3'b000:3'b0);

end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Sat Dec 04 18:25:58 2010
 Licensed to yujiro_kaneko:overtone:zyangalianhamster01@gmail.com 
*/

module hex_to_7segout ( p_reset , m_clock , hexdata , segdata_o , output7seg );
  input p_reset, m_clock;
  input [3:0] hexdata;
  output [7:0] segdata_o;
  input output7seg;
  wire [3:0] hex_value;
  wire [7:0] seg_value;
  wire seg_decode;
  wire _net_18;
  wire _net_19;
  wire _net_20;
  wire _net_21;
  wire _net_22;
  wire _net_23;
  wire _net_24;
  wire _net_25;
  wire _net_26;
  wire _net_27;
  wire _net_28;
  wire _net_29;
  wire _net_30;
  wire _net_31;
  wire _net_32;
  wire _net_33;
  wire _net_34;
  wire _net_35;
  wire _net_36;
  wire _net_37;

   assign #1 hex_value = hexdata;
   assign #1 seg_value = ((_net_37)?8'b00111111:8'b0)|
    ((_net_35)?8'b00000110:8'b0)|
    ((_net_33)?8'b01011011:8'b0)|
    ((_net_31)?8'b01001111:8'b0)|
    ((_net_29)?8'b01100110:8'b0)|
    ((_net_27)?8'b01101101:8'b0)|
    ((_net_25)?8'b01111101:8'b0)|
    ((_net_23)?8'b00100111:8'b0)|
    ((_net_21)?8'b01111111:8'b0)|
    ((_net_19)?8'b01101111:8'b0);
   assign #1 seg_decode = 1'b1;
   assign #1 _net_18 = (hex_value)==(4'b1001);
   assign #1 _net_19 = seg_decode&_net_18;
   assign #1 _net_20 = (hex_value)==(4'b1000);
   assign #1 _net_21 = seg_decode&_net_20;
   assign #1 _net_22 = (hex_value)==(4'b0111);
   assign #1 _net_23 = seg_decode&_net_22;
   assign #1 _net_24 = (hex_value)==(4'b0110);
   assign #1 _net_25 = seg_decode&_net_24;
   assign #1 _net_26 = (hex_value)==(4'b0101);
   assign #1 _net_27 = seg_decode&_net_26;
   assign #1 _net_28 = (hex_value)==(4'b0100);
   assign #1 _net_29 = seg_decode&_net_28;
   assign #1 _net_30 = (hex_value)==(4'b0011);
   assign #1 _net_31 = seg_decode&_net_30;
   assign #1 _net_32 = (hex_value)==(4'b0010);
   assign #1 _net_33 = seg_decode&_net_32;
   assign #1 _net_34 = (hex_value)==(4'b0001);
   assign #1 _net_35 = seg_decode&_net_34;
   assign #1 _net_36 = (hex_value)==(4'b0000);
   assign #1 _net_37 = seg_decode&_net_36;
   assign #1 segdata_o = seg_value;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Sat Dec 04 18:25:58 2010
 Licensed to yujiro_kaneko:overtone:zyangalianhamster01@gmail.com 
*/
