Interface2011N3

Verilog HDLɂCRC32ZHC++ēmF鎖Ŏ
t[E\tgVerilog HDLV~[^Verilator̊p@
 BV

EREADME.TXT@c@{t@C

E<Icarus>@c@IcarusVerilogptH_
    rnd.bat c 10mbytest@Cpob`t@C
    sim.bat c CRC32V~[Vpob`t@C

E<ISE>@c@ISIM Litept@C
    crc32test/crc32test.xise c Xilinx ISEpvWFNgt@C

E<ModelSimASE> ModelSim AlteraStarterEditionpt@C
    crc32test.mpf c vWFNgt@C

E<RTL>@c@^[QbgVerilogHDL RTLR[h
    crc32_async.v c CRC32ZRA
    crc32_sync8.v c CRC32ZH
    crc32_if.v    c crc32_sync8pC^[tF[XH

E<SIM>@c@VerilogHDLeXgx`R[h
    random10mb.v      c _t@CR[h
    sim_crc32s_file.v c crc32_sync8pV~[VeXgx`
    sim_crc32s_top.v  c g`o͂}邽߂̃_~[bp

E<Verilator>@c@VerilatorpV~[Vspt@C
    makefile        c V~[Vst@Cpmakefile
    vcrc32.exe      c ꂽV~[V^eXgst@C
    <Verilator/src> c C++ŋLqꂽVerilatorpeXgx`ƎsR[h
    <Verilator/obj> c Verilatort@C

F

eV~[V̎sɂ10MBytes_f[^L^t@C
"rand10mb.bin"bhCũJgfBNgɕKvłB
IcarusVerililogsłł<Icarus/rnd.bat>s
܂B

VerilatorɂV~[Vst@C̐菇
<Verilator/makefile>̖`VT_DIRϐVerilator̃CXg[
tH_w肵āAGNU makesVerilogHDLAC++AFPGA{[h
CRČvZƌʂ\st@Cvcrc32.exe܂B
st@CiV~[Vj̃gbv<Verilator/sim_crc32.cpp>
ɂȂ܂B
AVA|[gɐڑFPGA{[h̉ȂƃvO
I܂񂪁AsɂFPGApH̃fUC͎^ĂȂ̂
Verilator/src/sim_crc32.cpp>187-192sڂRgAEgĂ
vcrc32.exe𐶐^sĂB

