#####################################################################
#
# makefile for Verilated VerilogHDL / C++ Simulatior
#
#####################################################################

#####################################################################
# directory setting

#----- Verilator̈ʒu
VT_DIR      =c:/verilator-3.804/
#----- VerilatorVerilogHDLTuW[fBNg
VT_SRC_DIR  = -y ../SIM -y ../RTL
#----- \[XfBNg
VPATH = ./src:../rtl:../sim
#----- temporary object output directory
OBJ_DIR = obj

#####################################################################
# object setting

#----- ^[QbgAvP[V
TARGET = vcrc32
#----- verilogHDL̃gbvW[
VLG_TOP = crc32_sync8
#----- verilogHDL̃gbvW[t@C
VLG_SRC = $(VLG_TOP).v

#----- g[X(vcdg`ójݒ
VM_TRACE = 0

#----- C++ eXgx`^AvP[VIuWFNg
OBJ_CXX = \
  $(OBJ_DIR)/sim_crc32.o \
  $(OBJ_DIR)/fpga_crc32.o \
  $(OBJ_DIR)/cpp_crc32.o \

#####################################################################
# Verilator file setting

#----- verilator^CCu
VTD_RUNTIME = \
  $(OBJ_DIR)/verilated.o\

#----- VerilatedIuWFNg
#VTD_OBJ = \
#  $(OBJ_DIR)/V$(VLG_TOP).o \
#  $(OBJ_DIR)/V$(VLG_TOP)__Syms.o \

VTD_OBJ  = $(OBJ_DIR)/V$(VLG_SRC:%.v=%.o)
VTD_OBJ += $(OBJ_DIR)/V$(VLG_SRC:%.v=%__Syms.o)

#####################################################################
# tool assign

CC := gcc
CXX := g++
LD := g++
OD := objdump
RM := rm -f
RD := rm -rf
MD := mkdir
VT := verilator_bin

#####################################################################
# command options

#----- verilator IvVݒ
VTRFLAGS = --cc --compiler gcc -O3 -Wno-CASEX -Mdir $(OBJ_DIR)
#VTRFLAGS +=-Wno-WIDTH

#----- C++ IvVݒ
CXXFLAGS     = -O3 -I $(VT_DIR)include -I $(OBJ_DIR)

#----- MinGWstaticCugp
LDFLAGS = -static
LIBS   = 

#####################################################################
# vcd dump mode 
#----- .vcd[h
ifeq ($(VM_TRACE),1)
 #----- verilator̃R}hIvV
 VTRFLAGS += --trace
 #----- C++eXgx`֒ʒm
 CXXFLAGS += -DVM_TRACE=1
 #----- .vcdnh[
 VTD_RUNTIME += $(OBJ_DIR)/verilated_vcd_c.o
 #----- VerilogHDL g[NX
 VTD_OBJ += $(OBJ_DIR)/V$(VLG_SRC:%.v=%__Trace.o)
 VTD_OBJ += $(OBJ_DIR)/V$(VLG_SRC:%.v=%__Trace__Slow.o)
endif

#####################################################################
# make target

OBJ = $(VTD_OBJ) $(VTD_RUNTIME) $(OBJ_CXX)
VTD_SRC = $(VTD_OBJ:%.o=%.cpp)

$(TARGET).exe:$(OBJ)
	@echo --------------------------- Linking ---------------------------
	$(LD) $^ $(LDFLAGS) $(LIBS) -o $@

$(OBJ_DIR)/%.o: %.cpp makefile
	@echo ---------- Complie User C++ $<
	$(CXX) -c $(CXXFLAGS) $< -o $@

$(OBJ_DIR)/%.o: $(OBJ_DIR)/%.cpp makefile
	@echo ---------- Complie Verilated C++ $<
	$(CXX) -c $(CXXFLAGS) $< -o $@

$(VTD_SRC): $(VLG_SRC)
	@echo ---------- Transrate VerilogHDL to C++  $<
	$(VT_DIR)$(VT) $(VTRFLAGS) $(VT_SRC_DIR) $^

$(OBJ_DIR)/%.o: $(VT_DIR)include/%.cpp makefile
	@echo ---------- Complie Verilator Runtime Library $<
	$(CXX) -c $(CXXFLAGS) $< -o $@

#
.PHONY: clean
clean:
	$(RM) $(TARGET).map
	$(RM) $(TARGET).exe
	$(RD) $(OBJ_DIR)

#
.PHONY: run
run:
	$(TARGET).exe

