/***********************************************************************/
/*                                                                     */
/*  FILE        :hwsetup.cpp                                           */
/*  DATE        :Wed, Apr 22, 2009                                     */
/*  DESCRIPTION :Hardware Setup file                                   */
/*  CPU TYPE    :SH7262                                                */
/*                                                                     */
/*  This file is generated by Renesas Project Generator (Ver.4.9).     */
/*                                                                     */
/***********************************************************************/


#include    <machine.h>
#include <tinyhal.h>

#ifdef __cplusplus
extern "C" {
#endif
extern void HardwareSetup(void);
#ifdef __cplusplus
}
#endif

#pragma section ResetPRG

#define SDRAM_MODE      (*(volatile unsigned short *)(0xfffc5040))

void HardwareSetup(void)
{
    long addr;

    /*====CPG setting====*/ 
	CPG.FRQCR.WORD = 0x1104;

    /* ---- The clock of all modules is permitted. ---- */
    CPG.STBCR3.BYTE = 0x02; 
    CPG.STBCR4.BYTE = 0x00; 
    CPG.STBCR5.BYTE = 0x10; 
    CPG.STBCR6.BYTE = 0x02; 
    CPG.STBCR7.BYTE = 0x2a; 
    CPG.STBCR8.BYTE = 0x7e;     
    
	set_imask(15);
	
	PORT.PBCR5.WORD = 0x0111;	//A22..A20(*A22 or CS4)
	PORT.PBCR4.WORD = 0x1111;	//A19..A16
	PORT.PBCR3.WORD = 0x1111;	//A15..A12
	PORT.PBCR2.WORD = 0x1111;	//A11..A8
	PORT.PBCR1.WORD = 0x1111;	//A7..A4
	PORT.PBCR0.WORD = 0x1110;	//A3..A1

	PORT.PDCR3.WORD = 0x1111;	//D15..12
	PORT.PDCR2.WORD = 0x1111;	//D11..8
	PORT.PDCR1.WORD = 0x1111;	//D7..4
	PORT.PDCR0.WORD = 0x1111;	//D3..0
    
	PORT.PCCR2.WORD = 0x0001; //CS3#
	PORT.PCCR1.WORD = 0x0001; //CKE CAS# RAS# DQMU#
	PORT.PCCR0.WORD = 0x1011; //DQML# RD/WR# RD# CS0#
    
	// CS2 8bit I/O
	BSC.CS2BCR.LONG = 0x12490a00;
	BSC.CS2WCR.NORMAL.LONG = 0x00000140;

	// CS3 SRAM
	BSC.CS3BCR.LONG = 0x00000400;
	BSC.CS3WCR.NORMAL.LONG = 0x00000140;

    //PORT.PJCR0.WORD = 0x0300;
	PORT.PJCR0.WORD = (PORT.PJCR0.WORD & 0xF0F0) | 0x0305;
	PORT.PFCR0.WORD = (PORT.PFCR0.WORD & 0xFFF0) | 0x0001;

    /* WDT setting */
    WDT.WTCSR.WORD = 0xA502;
    
    /* Cache setting */
    CCNT.CCR1.LONG = 0x00000909;

    nop();
    nop();
    nop();
    nop();
    nop();

    /* ==== Written in SDRAM Mode Register ==== */
    (*(volatile unsigned short *)(0xfffc5040)) = 0; 

    /*  RAM clear from 0c000000 to 0c0fffff */
    //for (addr = 0x2C000000; addr<0x2C100000; addr+=4) (*(volatile long *)addr) = 0x00000000;
}