| gplvds_hd Project Status | |||
| Project File: | gplvds_hd.xise | Parser Errors: | No Errors |
| Module Name: | gplvds_hd | Implementation State: | Programming File Generated |
| Target Device: | xc3s50a-4vq100 |
|
No Errors |
| Product Version: | ISE 12.2 |
|
437 Warnings (3 new) |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
X 2 Failing Constraints |
| Environment: | System Settings |
|
68051 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 380 | 1,408 | 26% | ||
| Number of 4 input LUTs | 573 | 1,408 | 40% | ||
| Number of occupied Slices | 425 | 704 | 60% | ||
| Number of Slices containing only related logic | 425 | 425 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 425 | 0% | ||
| Total Number of 4 input LUTs | 617 | 1,408 | 43% | ||
| Number used as logic | 571 | ||||
| Number used as a route-thru | 44 | ||||
| Number used as Shift registers | 2 | ||||
| Number of bonded IOBs | 61 | 68 | 89% | ||
| IOB Master Pads | 4 | ||||
| IOB Slave Pads | 4 | ||||
| Number of ODDR2s used | 4 | ||||
| Number of BUFGMUXs | 4 | 24 | 16% | ||
| Number of DCMs | 2 | 2 | 100% | ||
| Average Fanout of Non-Clock Nets | 3.03 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 68051 (Setup: 36435, Hold: 0, Component Switching Limit: 31616) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | X 2 Failing Constraints | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 日 7 17 16:58:49 2011 | 0 | 256 Warnings (3 new) | 89 Infos (24 new) | |
| Translation Report | Current | 日 7 17 16:59:01 2011 | 0 | 25 Warnings (0 new) | 2 Infos (0 new) | |
| Map Report | Current | 日 7 17 16:59:56 2011 | 0 | 55 Warnings (0 new) | 10 Infos (0 new) | |
| Place and Route Report | Current | 日 7 17 17:00:49 2011 | 0 | 53 Warnings (0 new) | 1 Info (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | 日 7 17 17:00:56 2011 | 0 | 0 | 4 Infos (0 new) | |
| Bitgen Report | Current | 日 7 17 17:01:13 2011 | 0 | 48 Warnings (0 new) | 2 Infos (0 new) | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| Physical Synthesis Report | Current | 日 7 17 16:59:56 2011 | |
| WebTalk Log File | Current | 日 7 17 17:01:13 2011 | |