xil_dvi Project Status (06/10/2011 - 00:43:01)
Project File: gplvds_hd.xise Parser Errors: No Errors
Module Name: xil_dvi Implementation State: Programming File Not Generated
Target Device: xc3s50a-4vq100
  • Errors:
  
Product Version:ISE 12.2
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrent‹à 6 10 00:43:00 2011

Date Generated: 06/10/2011 - 00:43:01