| gplvds_vga Project Status (07/17/2011 - 17:08:16) | |||
| Project File: | gplvds_vga.xise | Parser Errors: | No Errors |
| Module Name: | gplvds_vga | Implementation State: | Programming File Generated |
| Target Device: | xc3s50a-4vq100 |
|
No Errors |
| Product Version: | ISE 12.2 |
|
432 Warnings (0 new) |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
All Constraints Met |
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 367 | 1,408 | 26% | ||
| Number of 4 input LUTs | 571 | 1,408 | 40% | ||
| Number of occupied Slices | 417 | 704 | 59% | ||
| Number of Slices containing only related logic | 417 | 417 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 417 | 0% | ||
| Total Number of 4 input LUTs | 615 | 1,408 | 43% | ||
| Number used as logic | 569 | ||||
| Number used as a route-thru | 44 | ||||
| Number used as Shift registers | 2 | ||||
| Number of bonded IOBs | 61 | 68 | 89% | ||
| IOB Flip Flops | 1 | ||||
| IOB Master Pads | 4 | ||||
| IOB Slave Pads | 4 | ||||
| Number of ODDR2s used | 4 | ||||
| Number of BUFGMUXs | 3 | 24 | 12% | ||
| Number of DCMs | 1 | 2 | 50% | ||
| Average Fanout of Non-Clock Nets | 3.07 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 日 7 17 17:06:40 2011 | 0 | 256 Warnings (0 new) | 90 Infos (0 new) | |
| Translation Report | Current | 日 7 17 17:06:49 2011 | 0 | 24 Warnings (0 new) | 1 Info (0 new) | |
| Map Report | Current | 日 7 17 17:07:28 2011 | 0 | 54 Warnings (0 new) | 8 Infos (0 new) | |
| Place and Route Report | Current | 日 7 17 17:07:53 2011 | 0 | 50 Warnings (0 new) | 0 | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | 日 7 17 17:08:00 2011 | 0 | 0 | 4 Infos (0 new) | |
| Bitgen Report | Current | 日 7 17 17:08:15 2011 | 0 | 48 Warnings (0 new) | 1 Info (0 new) | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| Physical Synthesis Report | Current | 日 7 17 17:07:28 2011 | |
| WebTalk Log File | Current | 日 7 17 17:08:15 2011 | |