
`define simulation

`include "agx20_disp_dvi_hd.v"
//`include "alt_altclkctrl.v"
//`include "alt_pll_50x100x100d.v"
//`include "alt_pll_24x65x325.v"
//`include "alt_pll_50x65.v"
//`include "alt_pll_50x64.v"
//`include "alt_pll_x5.v"
//`include "altpllpll_0.v"
//`include "alt_clkbuf.v"
`include "alt_ddio_bidir.v"
//`include "alt_dvi.v"
//`include "alt_dvi_out_x4_raw.v"
`include "LYNX/dvi_data_enc.v"
`include "dispgen_hd.v"
`include "alt_alt2gxb_x4.vo"
`include "alt_pll_50x138.v"
`include "alt_pll_50x137.v"

`include "sim_altera/220model.v"
`include "sim_altera/altera_mf.v"
`include "sim_altera/arriagx_atoms.v"
`include "sim_altera/arriagx_hssi_atoms.v"
`include "sim_altera/sgate.v"

`timescale 1 ns / 1 ns

module tb(
);

	wire	CLK0;
	wire	CLK1;
	wire	CLK2;
	wire	RST_N;

	// ---- CLK0 (48MHz) ----

	reg		CLK0_r;

	initial
	begin
		forever
		begin
			CLK0_r <= 1'b0; #10;
			CLK0_r <= 1'b1; #11;
		end
	end

	assign CLK0=CLK0_r;

	// ---- CLK1 (25MHz) ----

	reg		CLK1_r;

	initial
	begin
		forever
		begin
			CLK1_r <= 1'b0; #20;
			CLK1_r <= 1'b1; #20;
		end
	end

	assign CLK1=CLK1_r;

	// ---- CLK2 (50MHz) ----

	reg		CLK2_r;

	initial
	begin
		forever
		begin
			CLK2_r <= 1'b0; #10;
			CLK2_r <= 1'b1; #10;
		end
	end

	assign CLK2=CLK2_r;

	// ---- RESET async ----

	reg		RST_N_r;

	initial
	begin
		RST_N_r <= 'b1; #1;
		RST_N_r <= 'b0; #200;
		RST_N_r <= 'b1; #1;
	end

	assign RST_N=RST_N_r;

	// ---- ----

	wire	CLK50;
	wire	CLK100;

	wire	CLK_FB;

	assign CLK50=CLK2;

agx20_disp_dvi_hd disp_dv_hd(
	.TX_P(),			// out
	.TX_SCL(),			// inout
	.TX_SDA(),			// inout
	.TX_HPD(1'b1),		// in
	.CLK1(CLK50),		// in
	.CLK2(1'b0),		// in
	.CLK3(),			// inout
	.CLK4(),			// inout
	.SYSRST_N(RST_N)	// in
);

endmodule
