//------------------------------------------------------------------------
//   This Verilog file was developed by Altera Corporation.  It may be
// freely copied and/or distributed at no cost.  Any persons using this
// file for any purpose do so at their own risk, and are responsible for
// the results of such use.  Altera Corporation does not guarantee that
// this file is complete, correct, or fit for any particular purpose.
// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED.  This notice must
// accompany any copy of this file.
//
//------------------------------------------------------------------------
//
// Mechanism for disabling PLI calls to convert_hex2ver for memory 
// initialization 
// -----------------------------------------------------------------------
// Version 1.0          Date 08/28/01
//
// Define Verilog directive NO_PLI .
// -----------------------------------------------------------------------

`define NO_PLI 1
