// Copyright (C) 2005 - Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

///////////////////////////////////////////////////////////////////////////////
//                                                                           //
// Containing Verilog Model for the Atoms:                                   //
//                                                                           //
//                         arriagx_hssi_receiver                         //
//                         arriagx_hssi_transmitter                      //
//                         arriagx_hssi_central_management_unit          //
//                         arriagx_hssi_cmu_pll                          //
//                         arriagx_hssi_cmu_clock_divider                //
//                         arriagx_hssi_refclk_divider                   //
//                         arriagx_hssi_calibration_block                //
//                                                                           //
///////////////////////////////////////////////////////////////////////////////



`timescale 1 ps / 1 ps
module arriagx_hssi_aux_clock_div (
    clk,     // input clock
    reset,   // reset
    enable_d, // enable DPRIO
    d,        // division factor for DPRIO support
    clkout   // divided clock
);
input clk,reset;
input enable_d;
input [7:0] d;
output clkout;


parameter clk_divide_by  = 1;
parameter extra_latency  = 0;

integer clk_edges,m;
reg [2*extra_latency:0] div_n_register;

wire [7:0] d_factor;


assign d_factor = (enable_d === 1'b1) ? d : clk_divide_by;

initial
begin
    div_n_register = 'b0;
    clk_edges = -1;
    m = 0;
end

always @(d_factor)
begin
    div_n_register = 'b0;
    clk_edges = -1;
    m = 0;
end

always @(posedge clk or negedge clk or posedge reset)
begin
    if (reset === 1'b1) 
    begin
        clk_edges = -1;
        div_n_register <= 'b0;
    end
    else
    begin
        if (clk_edges == -1) 
        begin
            div_n_register[0] <= clk;
            if (clk == 1'b1) clk_edges = 0;
        end
        else if (clk_edges % d_factor == 0) 
            div_n_register[0] <= ~div_n_register[0];
        if (clk_edges >= 0 || clk == 1'b1)
            clk_edges = (clk_edges + 1) % (2*d_factor) ;
    end
    for (m = 0; m < 2*extra_latency; m=m+1)
            div_n_register[m+1] <= div_n_register[m];
end

assign clkout = div_n_register[2*extra_latency];

endmodule


`timescale 1 ps / 1 ps

module arriagx_hssi_aux_clock_mult (
    clk,     // input clock
    adjust,  // adjust frequency
    adjust_without_lol,
    reset,   // reset
    enable_m, // enable DPRIO
    m,        // multiplication factor for DPRIO support
    clkout,  // multiplied clock
    busy     // state
);
input clk,adjust,reset;
input adjust_without_lol;
input enable_m;
input [7:0] m; 
output clkout;
output [1:0] busy;
reg [1:0] busy;


parameter clk_multiply_by  = 1;

`define S2GX_HSSI_CLOCK_MULT_INITIAL 2'b01
`define S2GX_HSSI_CLOCK_MULT_ACTIVE  2'b11
`define S2GX_HSSI_CLOCK_MULT_INACTIVE  2'b00

reg  clk_adjust_settled;
real last_rising_edge,clk_period;
integer clk_fast_period,clk_adjust,clk_adjust_interval,clk_adjust_running,clk_sync_period;
reg  mult_n;
integer n;

wire [7:0] m_factor;

assign m_factor = (enable_m === 1'b1) ? m : clk_multiply_by;

// At start of reconfiguration, set multiplier to reset state

always @(m_factor)
begin
    busy <= `S2GX_HSSI_CLOCK_MULT_INITIAL;
    last_rising_edge = 0;
    mult_n = 'b0;
    n = 0;
end

initial
begin
    busy = `S2GX_HSSI_CLOCK_MULT_INITIAL;
    last_rising_edge = 0;
    mult_n = 'b0;
    n = 0;
end


always @(posedge adjust) busy <= `S2GX_HSSI_CLOCK_MULT_INITIAL;

always @(posedge clk or posedge reset)
begin
    if (reset === 1'b1) 
    begin
        mult_n = 1'b0;
        busy <= `S2GX_HSSI_CLOCK_MULT_INITIAL;
    end
    else
    begin
        if (busy == `S2GX_HSSI_CLOCK_MULT_INITIAL && adjust_without_lol == 1'b0)        // first rising edge
        begin 
            mult_n = 1'b0;
            last_rising_edge = $realtime;
            busy <= `S2GX_HSSI_CLOCK_MULT_ACTIVE;
        end
        else 
        begin
            if (busy == `S2GX_HSSI_CLOCK_MULT_INITIAL && adjust_without_lol == 1'b1)
            begin 
                mult_n = 1'b0;
                last_rising_edge = $realtime;
                busy <= `S2GX_HSSI_CLOCK_MULT_ACTIVE;
            end
            if (busy == `S2GX_HSSI_CLOCK_MULT_ACTIVE)    // second rising edge
            begin
                clk_period = $realtime - last_rising_edge;
                clk_fast_period = clk_period/m_factor - 0.5;
                clk_adjust = clk_period - clk_fast_period * m_factor;
                busy <= `S2GX_HSSI_CLOCK_MULT_INACTIVE;
            end
            mult_n = ~mult_n;
            if (clk_adjust > 0) clk_adjust_running = clk_adjust + 1;
            clk_adjust_settled = (clk_adjust == 0);                    // if no adjustment necessary
            for (n = m_factor; n >= 1 ; n=n-1)
            begin
                if (clk_adjust_settled == 1'b0) 
                begin
                    clk_adjust_running = clk_adjust_running - 1;
                    clk_adjust_interval = n/clk_adjust_running;
                    if (n % clk_adjust_running == 0) 
                        clk_adjust_settled = 1'b1;
                    clk_sync_period = clk_fast_period + 1;       
                end
                else
                begin
                    if (clk_adjust == 0)
                        clk_sync_period = clk_fast_period;
                    else
                    begin
                        if (n % clk_adjust_interval == 0) 
                            clk_sync_period = clk_fast_period + 1;     
                        else
                            clk_sync_period = clk_fast_period;
                    end
                end
                if (reset == 1'b1) mult_n = 1'b0;
                else
                begin
                    #(clk_sync_period/2) mult_n = ~mult_n; 
                    if (n > 1) #(clk_sync_period - clk_sync_period/2) mult_n = ~mult_n; 
                end
            end
        end
    end
end

assign clkout = mult_n;

endmodule


`timescale 1 ps / 1 ps
module arriagx_hssi_aux_clock_phaseshift (
    clk,     // input clock
    clkout   // delayed clock
);
input clk;
output clkout;
parameter clk_phase_shift_by  = 0;

reg pclk;

always @(clk) pclk <=  #(clk_phase_shift_by) clk;

assign clkout = pclk;
endmodule


`timescale 1 ps / 1 ps
module arriagx_hssi_tx_channel_clk_div (
    dpriodisable,
    dprioin,
    clkin0,clkin1,     // CMU PLL clocks
    reset,
    vcobypassin,       // VCO Bypass
    lclkout,           // Low speed clock
    fclkout            // Fast speed clock
);
input  dpriodisable;
input [9:0] dprioin;
input  clkin0,clkin1;
input  reset;
input  vcobypassin;
output lclkout,fclkout;

parameter clkin0_select = "true"; // true => select clkin0, false => select clkin1
parameter clk_divide_by_n = 1;    // n=1,2,4
parameter clk_divide_by_m = 4;    // m=4,5
parameter clk_divide_by_2_select = "true"; // true => use /2 divider, false => bypass
parameter allow_vco_bypass = "false";
parameter lclkout_latency = 0;
parameter fclkout_latency = 0;
parameter lclkout_phase_shift = 0;
parameter fclkout_phase_shift = 0; 

wire divide_by_n_in,divide_by_n_out,divide_by_m_out,divide_by_2_out; // divider i/o
wire lclkout_undelayed,hclkout_undelayed;     // before phase shift
wire lclkout_pre_latency,hclkout_pre_latency; // before latency

// begin dprio
// clkin0 selection
wire cram_rtx_cmu_sel;
wire dprio_divide_by_n_in;

// by n
wire [1:0] cram_m_sel;
wire cram_rpma_doublewidth_tx;
wire cram_rpmadwidth_tx;

wire nondprio_divide_by_n_out;
wire dprio_divide_by_n_out;
wire dprio_divide_by_n_out_by1;
wire dprio_divide_by_n_out_by2;
wire dprio_divide_by_n_out_by4;

// by m
wire nondprio_divide_by_m_out;
wire dprio_divide_by_m_out;
wire dprio_divide_by_m_out_by4;
wire dprio_divide_by_m_out_by5;

assign cram_rtx_cmu_sel = dprioin[4];

assign cram_m_sel = dprioin[1:0];
assign cram_rpmadwidth_tx = dprioin[3];
assign cram_rpma_doublewidth_tx = dprioin[2];

// by n
assign dprio_divide_by_n_out =(cram_m_sel === 2'b10) ? dprio_divide_by_n_out_by4 :
                              (cram_m_sel === 2'b01) ? dprio_divide_by_n_out_by2 :
                              dprio_divide_by_n_out_by1;
                              
assign divide_by_n_out = (dpriodisable !== 1'b0) ? nondprio_divide_by_n_out : dprio_divide_by_n_out;

// by m
assign dprio_divide_by_m_out = (cram_rpmadwidth_tx == 1'b1) ? dprio_divide_by_m_out_by5 : dprio_divide_by_m_out_by4;
assign divide_by_m_out= (dpriodisable !== 1'b0) ? nondprio_divide_by_m_out : dprio_divide_by_m_out;

// end dprio

// refclkin selection
assign dprio_divide_by_n_in = (cram_rtx_cmu_sel === 1'b0) ? clkin0 : clkin1;
assign divide_by_n_in = (allow_vco_bypass == "true") ? vcobypassin : 
                        (dpriodisable === 1'b0) ? dprio_divide_by_n_in :
                        ((clkin0_select == "true") ? clkin0 : clkin1);

// N divider
arriagx_hssi_aux_clock_div divide_by_n (
    .clk(divide_by_n_in),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(nondprio_divide_by_n_out)
);
defparam divide_by_n.clk_divide_by = clk_divide_by_n;
defparam divide_by_n.extra_latency = 0;
// N = 1
arriagx_hssi_aux_clock_div divide_by_n_by1 (
    .clk(divide_by_n_in),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprio_divide_by_n_out_by1)
);
defparam divide_by_n_by1.clk_divide_by = 1;
defparam divide_by_n_by1.extra_latency = 0;
// N = 2
arriagx_hssi_aux_clock_div divide_by_n_by2 (
    .clk(divide_by_n_in),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprio_divide_by_n_out_by2)
);
defparam divide_by_n_by2.clk_divide_by = 2;
defparam divide_by_n_by2.extra_latency = 0;
// N = 4
arriagx_hssi_aux_clock_div divide_by_n_by4 (
    .clk(divide_by_n_in),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprio_divide_by_n_out_by4)
);
defparam divide_by_n_by4.clk_divide_by = 4;
defparam divide_by_n_by4.extra_latency = 0;

// 4,5 divider
arriagx_hssi_aux_clock_div divide_by_m (
    .clk(divide_by_n_out),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(nondprio_divide_by_m_out)
);
defparam divide_by_m.clk_divide_by = clk_divide_by_m;
defparam divide_by_m.extra_latency = 0;
// m=4
arriagx_hssi_aux_clock_div divide_by_m_by4 (
    .clk(divide_by_n_out),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprio_divide_by_m_out_by4)
);
defparam divide_by_m_by4.clk_divide_by = 4;
defparam divide_by_m_by4.extra_latency = 0;
// m=5
arriagx_hssi_aux_clock_div divide_by_m_by5 (
    .clk(divide_by_n_out),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprio_divide_by_m_out_by5)
);
defparam divide_by_m_by5.clk_divide_by = 5;
defparam divide_by_m_by5.extra_latency = 0;

// 2 divider - moved to SERDES
arriagx_hssi_aux_clock_div divide_by_2 (
    .clk(divide_by_m_out),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(divide_by_2_out)
);
defparam divide_by_2.clk_divide_by = 2;
defparam divide_by_2.extra_latency = 0;

assign lclkout_undelayed = (clk_divide_by_2_select == "true") ? divide_by_2_out : divide_by_m_out;
assign hclkout_undelayed = divide_by_n_out;

// Low speed clock phase shift
arriagx_hssi_aux_clock_phaseshift lclk_phase_shift (
    .clk(lclkout_undelayed),
    .clkout(lclkout_pre_latency)
);
defparam lclk_phase_shift.clk_phase_shift_by = lclkout_phase_shift;

// High speed clock phase shift
arriagx_hssi_aux_clock_phaseshift hclk_phase_shift (
    .clk(hclkout_undelayed),
    .clkout(hclkout_pre_latency)
);
defparam hclk_phase_shift.clk_phase_shift_by = fclkout_phase_shift;

// Low speed clock latency
arriagx_hssi_aux_clock_div lclk_latency (
    .clk(lclkout_pre_latency),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(lclkout)
);
defparam lclk_latency.clk_divide_by = 1;
defparam lclk_latency.extra_latency = lclkout_latency;

// High speed clock latency
arriagx_hssi_aux_clock_div hclk_latency (
    .clk(hclkout_pre_latency),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(fclkout)
);
defparam hclk_latency.clk_divide_by = 1;
defparam hclk_latency.extra_latency = fclkout_latency;

endmodule


`timescale 1 ps / 1 ps
module arriagx_hssi_refclk_divider (
    inclk,       // input from REFCLK pin
    dprioin,
    dpriodisable,
    clkout,      // clock output
    dprioout
);
input inclk,dprioin,dpriodisable;
output clkout,dprioout;

wire inclk_ipd;
wire dprioin_ipd;
wire dpriodisable_ipd;

buf buf_inclk (inclk_ipd,inclk);
buf buf_dprioin (dprioin_ipd,dprioin);
buf buf_dpriodisable (dpriodisable_ipd,dpriodisable);

specify
    (inclk => clkout) = (0,0);
endspecify

parameter enable_divider = "true"; // true -> use /2 divider, false -> bypass
parameter divider_number = 0;      // 0 or 1 for logical numbering
parameter refclk_coupling_termination = "dc_coupling_external_termination"; // new in 5.1 SP1
parameter dprio_config_mode        = 0;               // 6.1

wire divide_by_2_out;

arriagx_hssi_aux_clock_div divide_by_2 (
    .clk(inclk_ipd),
    .reset(1'b0),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(divide_by_2_out)
);
defparam divide_by_2.clk_divide_by = 2;
defparam divide_by_2.extra_latency = 0;

assign clkout = (enable_divider == "true") ? divide_by_2_out : inclk_ipd;
assign dprioout = (dpriodisable_ipd == 1'b1) ? 1'b0 : dprioin_ipd; // temporary, needs to be changed later

endmodule

`timescale 1 ps / 1 ps
module arriagx_hssi_cmu_clock_divider (
    clk,                 // CMU PLL clocks 0,1,2
    pclkin,              // pclk from adjacent QUAD
    dprioin,           
    dpriodisable,
    powerdn,
    quadreset,
    refclkdig,
    scanclk,
    scanin,
    vcobypassin,
    scanshift,
    scanmode,
    analogrefclkout,     // output of /4/5 divider
    analogfastrefclkout, // output of /N divider
    digitalrefclkout,    // refclk_pma
    pclkx8out,           // pclk output to adjacent QUAD
    coreclkout,          // coreclk output to PLD
    dprioout,
    scanout
);
input  [2:0] clk;
input  pclkin;
input  [29:0] dprioin;
input  dpriodisable;
input  powerdn,quadreset;
input  refclkdig,scanclk,scanshift,scanmode;
input  [22:0] scanin;
input  vcobypassin;
output analogrefclkout,analogfastrefclkout,digitalrefclkout,coreclkout;
output pclkx8out;
output [29:0] dprioout;
output [22:0] scanout;

wire pclkin_ipd;
wire  [2:0] clk_ipd;
wire [29:0] dprioin_ipd;
wire dpriodisable_ipd;
wire powerdn_ipd;
wire quadreset_ipd;
wire refclkdig_ipd;
wire scanclk_ipd;
wire scanshift_ipd;
wire scanmode_ipd;
wire [22:0] scanin_ipd;

buf buf_pclkin (pclkin_ipd,pclkin);
buf buf_clk  [2:0] (clk_ipd,clk);
buf buf_dprioin [29:0] (dprioin_ipd,dprioin);
buf buf_dpriodisable (dpriodisable_ipd,dpriodisable);
buf buf_powerdn (powerdn_ipd,powerdn);
buf buf_quadreset (quadreset_ipd,quadreset);
buf buf_refclkdig (refclkdig_ipd,refclkdig);
buf buf_scanclk (scanclk_ipd,scanclk);
buf buf_scanshift (scanshift_ipd,scanshift);
buf buf_scanmode (scanmode_ipd,scanmode);
buf buf_scanin [22:0] (scanin_ipd,scanin);

specify
    (clk => coreclkout)    = (0,0);
    (clk => pclkx8out)     = (0,0);
    (pclkin => coreclkout) = (0,0);
endspecify

parameter inclk_select   = 0;   // 0-2 logical index for clk
parameter use_vco_bypass = "false"; 
parameter use_digital_refclk_post_divider = "false"; // true -> /2 div, false -> bypass
parameter use_coreclk_out_post_divider = "false";    // true -> /2 div, false -> bypass
parameter divide_by = 4; // /4 or /5 div
parameter enable_refclk_out = "true";
parameter enable_pclk_x8_out = "false";
parameter select_neighbor_pclk = "false";
parameter coreclk_out_gated_by_quad_reset = "false";
parameter select_refclk_dig = "false";
parameter dprio_config_mode        = 0;               // 6.1

// Simulation only
parameter sim_analogrefclkout_phase_shift = 0;
parameter sim_analogfastrefclkout_phase_shift = 0;
parameter sim_digitalrefclkout_phase_shift = 0;
parameter sim_pclkx8out_phase_shift = 0;
parameter sim_coreclkout_phase_shift = 0;

wire divide_by_n_out,divide_by_m_out,divide_by_2_dig_out,divide_by_2_core_out; // divider i/o
wire mux_pclk,mux_digrefclk,mux_coreclk;
wire reset_divs,reset_coreclk_only;
wire vco_bypass_mux;

wire analogrefclkout_undelayed,analogfastrefclkout_undelayed,digitalrefclkout_undelayed,
     coreclkout_undelayed,pclkx8out_undelayed;

assign reset_divs = powerdn_ipd | quadreset_ipd;
assign reset_coreclk_only = (coreclk_out_gated_by_quad_reset == "false") ? 1'b0 : quadreset_ipd;

// /N=1 divider

arriagx_hssi_aux_clock_div divide_by_n (
    .clk(clk_ipd[inclk_select]),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .reset(reset_divs),
    .clkout(divide_by_n_out)
);
defparam divide_by_n.clk_divide_by = 1;
defparam divide_by_n.extra_latency = 0;

// 4,5 divider
arriagx_hssi_aux_clock_div divide_by_m (
    .clk(divide_by_n_out),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .reset(reset_divs),
    .clkout(divide_by_m_out)
);
defparam divide_by_m.clk_divide_by = divide_by;
defparam divide_by_m.extra_latency = 0;

assign vco_bypass_mux = (use_vco_bypass == "true") ? vcobypassin : divide_by_m_out;

// 2 divider for refclk_pma
arriagx_hssi_aux_clock_div divide_by_2_dig (
    .clk(vco_bypass_mux),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .reset(reset_divs),
    .clkout(divide_by_2_dig_out)
);
defparam divide_by_2_dig.clk_divide_by = 2;
defparam divide_by_2_dig.extra_latency = 0;

// 2 divider for coreclk
arriagx_hssi_aux_clock_div divide_by_2_core (
    .clk(mux_digrefclk),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .reset(reset_coreclk_only),
    .clkout(divide_by_2_core_out)
);
defparam divide_by_2_core.clk_divide_by = 2;
defparam divide_by_2_core.extra_latency = 0;

assign analogfastrefclkout_undelayed = divide_by_n_out;
assign analogrefclkout_undelayed = (enable_refclk_out == "false") ? 1'bz : divide_by_m_out;
assign mux_pclk = (use_digital_refclk_post_divider == "true") ? divide_by_2_dig_out : vco_bypass_mux;
assign mux_digrefclk = (select_neighbor_pclk == "true") ? pclkin_ipd : mux_pclk;
assign pclkx8out_undelayed = (enable_pclk_x8_out == "false") ? 1'bz : mux_pclk;
assign digitalrefclkout_undelayed = (select_refclk_dig == "true") ? refclkdig_ipd : mux_digrefclk;
assign mux_coreclk = (use_coreclk_out_post_divider == "false") ? mux_digrefclk : divide_by_2_core_out;
assign coreclkout_undelayed = mux_coreclk;

arriagx_hssi_aux_clock_phaseshift extra_ps_afrc (
    .clk(analogfastrefclkout_undelayed),
    .clkout(analogfastrefclkout)
);
defparam extra_ps_afrc.clk_phase_shift_by = sim_analogfastrefclkout_phase_shift;

arriagx_hssi_aux_clock_phaseshift extra_ps_arc (
    .clk(analogrefclkout_undelayed),
    .clkout(analogrefclkout)
);
defparam extra_ps_arc.clk_phase_shift_by = sim_analogrefclkout_phase_shift;

arriagx_hssi_aux_clock_phaseshift extra_ps_drc (
    .clk(digitalrefclkout_undelayed),
    .clkout(digitalrefclkout)
);
defparam extra_ps_drc.clk_phase_shift_by = sim_digitalrefclkout_phase_shift;

arriagx_hssi_aux_clock_phaseshift extra_ps_cc (
    .clk(coreclkout_undelayed),
    .clkout(coreclkout)
);
defparam extra_ps_cc.clk_phase_shift_by = sim_coreclkout_phase_shift;

arriagx_hssi_aux_clock_phaseshift extra_ps_p8c (
    .clk(pclkx8out_undelayed),
    .clkout(pclkx8out)
);
defparam extra_ps_p8c.clk_phase_shift_by = sim_pclkx8out_phase_shift;


endmodule


`timescale 1 ps/1 ps
module arriagx_hssi_cmu_pll (
   clk,dprioin,dpriodisable,
   pllreset,pllpowerdn,
   clkout,locked,
   dprioout,
   fbclkout,
   vcobypassout
);
input [7:0] clk;
input [39:0] dprioin;
input dpriodisable;
input pllreset,pllpowerdn;
output clkout,locked;
output [39:0] dprioout;
output fbclkout;
output vcobypassout;

wire dpriodisable_ipd;
wire [7:0] clk_ipd;
wire [39:0] dprioin_ipd;
wire pllreset_ipd;
wire pllpowerdn_ipd;

// DPRIO
wire dprioenable;
reg  dprioen_reg;
wire [7:0] m;
wire [7:0] cru_m_chn;
wire [7:0] cru_l_chn;


buf buf_dpriodisable (dpriodisable_ipd,dpriodisable);
buf buf_clk [7:0] (clk_ipd,clk);
buf buf_dprioin [39:0] (dprioin_ipd,dprioin);
buf buf_pllreset (pllreset_ipd,pllreset);
buf buf_pllpowerdn (pllpowerdn_ipd,pllpowerdn);

specify
    (clk => clkout) = (0,0);
endspecify
parameter inclk0_period = 0;  // time period in ps
parameter inclk1_period = 0;
parameter inclk2_period = 0;
parameter inclk3_period = 0;
parameter inclk4_period = 0;
parameter inclk5_period = 0;
parameter inclk6_period = 0;
parameter inclk7_period = 0;

parameter pfd_clk_select = 0; // logical clock select 0-7
parameter multiply_by = 1;    // feedback loop divider 1,4,5,8,10,16,20,25
parameter divide_by = 1;      // post divider 1,2,4
parameter low_speed_test_sel = 4'b0000;
parameter pll_type = "normal"; // normal,fast,auto
parameter charge_pump_current_test_enable = 2'b00;
parameter vco_range = "low";   // CMU_CTL[0]
parameter loop_filter_resistor_control = 2'b00; // CMU_CTL[2:1]
parameter loop_filter_ripple_capacitor_control = 2'b00; // CMU_CTL[4:3].
parameter use_default_charge_pump_current_selection = "false"; // CMU_CTL[5]
parameter use_default_charge_pump_supply_vccm_vod_control  = "false"; // CMU_CTL[6]
parameter pll_number = 0; // PLL 0-2 
parameter charge_pump_current_control = 2'b00;
parameter up_down_control_percent = 4'b0000;
parameter charge_pump_tristate_enable = "false";
parameter enable_pll_cascade = "false";             // 6.1
parameter dprio_config_mode = 0;                    // 6.1
parameter protocol_hint = "basic";                  // 6.1

parameter remapped_to_new_loop_filter_charge_pump_settings = "false"; // 7.2 sp1

// Simulation only
parameter sim_clkout_phase_shift = 0;
parameter sim_clkout_latency = 0;

`define S2GX_CMU_PLL_INITIAL 2'b01
`define S2GX_CMU_PLL_ACTIVE  2'b11
`define S2GX_CMU_PLL_INACTIVE  2'b00

wire pll_clkin_pre_latency;
wire pll_clkin,clk_pll,clk_div,clk_div_delayed,clk_vco;
reg  charge_pump; // re-adjust VCO frequency
reg  adjust_without_lol;
wire charge_pump_delayed;
wire [1:0] busy;  // VCO state

real last_fb_clk_edge;
wire check_phase;
real expected_clk_period,clk_tolerance,real_clk_period,last_pll_clkin_edge,last_real_clk_period;
reg  first_pll_clkin_edge_detect;
reg  display_msgs,freq_viol_msg_sem;
wire reset;
reg locked_real;

wire         dprio_reset; // reset through DPRIO CRAM in 7.1
wire [2:0]   dprio_pfd_clk_select;

function real select_clock_period;
input clk_select;
integer clk_select;
real period;
begin
    case (clk_select)
        0 : period = inclk0_period;
        1 : period = inclk1_period;
        2 : period = inclk2_period;
        3 : period = inclk3_period;
        4 : period = inclk4_period;
        5 : period = inclk5_period;
        6 : period = inclk6_period;
        7 : period = inclk7_period;
        default : $display("Invalid logical clock select");
    endcase
    select_clock_period = period;
end
endfunction

    // get the absolute value
    function integer abs;
    input value;
    integer value;
    begin
        if (value < 0)
            abs = value * -1;
        else abs = value;
    end
    endfunction

initial
begin
    charge_pump = 1'b1;
    first_pll_clkin_edge_detect = 1'b0;
    expected_clk_period = select_clock_period(pfd_clk_select);
    clk_tolerance = 0.1 * expected_clk_period; // same as Stratix
    display_msgs = 1'b1;
    freq_viol_msg_sem = 1'b1;
    locked_real = 1'b0;
    adjust_without_lol = 1'b0;
end

assign pll_clkin_pre_latency = (dprioenable === 1'b1) ? clk_ipd[dprio_pfd_clk_select] : clk_ipd[pfd_clk_select];
assign reset = pllreset_ipd | pllpowerdn_ipd | dprio_reset;

// DPRIO
assign dprioenable = ((dprio_config_mode & 6'b010000) != 0) ? ~dpriodisable_ipd : 1'b0;
assign cru_m_chn = dprioin_ipd[7:0];
assign cru_l_chn = dprioin_ipd[15:8];
assign dprio_reset = ((dprioenable === 1'b1) &&
                     (dprioin_ipd[16] === 1'b1 || dprioin_ipd[17] === 1'b1)) ? 1'b1 : 1'b0;
assign dprio_pfd_clk_select = dprioin_ipd[20:18];

assign dprioout[7:0]  = multiply_by;
assign dprioout[15:8] = divide_by;
assign dprioout[20:18] = pfd_clk_select;


assign m = cru_m_chn;

// Clock latency

arriagx_hssi_aux_clock_div clock_latency (
    .clk(pll_clkin_pre_latency),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .reset(reset),
    .clkout(pll_clkin)
);
defparam clock_latency.clk_divide_by = 1;
defparam clock_latency.extra_latency = sim_clkout_latency;

// DPRIO : Register the dprioenable signal to avoid asynchronous reconfiguration
always @(posedge pll_clkin)
begin
    dprioen_reg <= dprioenable;
end

// Input frequency checks

always @(posedge pll_clkin)
begin
    if (first_pll_clkin_edge_detect == 1'b0)
        first_pll_clkin_edge_detect = 1'b1; 
    else 
    begin
        real_clk_period = $realtime - last_pll_clkin_edge;
        if ((real_clk_period < expected_clk_period - clk_tolerance) ||
            (real_clk_period > expected_clk_period + clk_tolerance))
        begin
            if (freq_viol_msg_sem == 1'b1)
            begin
                $display("Warning : CMU PLL input frequency mismatch between parameter-specified period and real clock period");
                $display("Time: %0t  Instance: %m", $time);
                $display("Clock period specified in parameter is %0t but real clock period is %0t",expected_clk_period,real_clk_period);
                freq_viol_msg_sem = 1'b0;
            end
        end
        if ((real_clk_period != last_real_clk_period) && (last_real_clk_period > 0)) 
        begin
            charge_pump = 1'b1;
            if ( abs(real_clk_period - last_real_clk_period) <= 2 )
                adjust_without_lol = 1'b1;
        end
        last_real_clk_period = real_clk_period;
    end
    last_pll_clkin_edge = $realtime;
end

// PFD

always @(posedge clk_pll)   last_fb_clk_edge = $realtime;

always @(negedge pll_clkin) 
begin
    if (($realtime > 0) && (busy != `S2GX_CMU_PLL_ACTIVE) && (busy != `S2GX_CMU_PLL_INITIAL))
    begin
        if (last_pll_clkin_edge != last_fb_clk_edge)
        begin
            charge_pump = 1'b1;
            if (locked == 1'b1)
                adjust_without_lol = 1'b1;
        end
        else charge_pump = 1'b0;
    end
end

always @(negedge reset)
begin
    charge_pump = 1'b1;
    adjust_without_lol = 1'b0;
//    display_msgs = 1'b0;
end

always @(posedge reset)
begin
    if (reset == 1'b1) 
    begin
        $display ("Note : CMU PLL is reset");
        $display ("Time: %0t  Instance: %m", $time);
        display_msgs = 1'b0;
    end
end
always @(charge_pump)
begin
    if (charge_pump == 1'b1 && adjust_without_lol == 1'b0) 
    begin
        if (display_msgs == 1'b0)
        begin
            $display ("Note : CMU PLL lost lock due to reset or change in frequency of input clock");
            $display ("Time: %0t  Instance: %m", $time);
            display_msgs = 1'b1;
        end
    end
    else
    begin
        if (display_msgs == 1'b1)
        begin
            $display ("Note : CMU PLL locked to incoming clock");
            $display ("Time: %0t  Instance: %m", $time);
            display_msgs = 1'b0;
        end
    end
end

// VCO
always @(busy)
begin
    if (busy == `S2GX_CMU_PLL_INACTIVE)
    begin
        charge_pump = 1'b0;
        adjust_without_lol = 1'b0;
    end
end

arriagx_hssi_aux_clock_mult vco (
    .clk(pll_clkin),
    .adjust(charge_pump),
    .adjust_without_lol(adjust_without_lol),
    .reset(reset),
    .enable_m(dprioenable),
    .m(m),
    .clkout(clk_vco), // VCO output
    .busy(busy)
);
defparam vco.clk_multiply_by = multiply_by;

// Feedback

arriagx_hssi_aux_clock_div divide_by_M (
    .clk(clk_vco),
    .reset(reset),
    .enable_d(dprioen_reg),
    .d(m),
    .clkout(clk_pll)
);
defparam divide_by_M.clk_divide_by = multiply_by;
defparam divide_by_M.extra_latency = 0;

// Extra phase shift on output

arriagx_hssi_aux_clock_phaseshift extra_ps_clkout (
    .clk(clk_vco),
    .clkout(clk_div_delayed)
);
defparam extra_ps_clkout.clk_phase_shift_by = sim_clkout_phase_shift;
        
// Extra phase shift on lock

arriagx_hssi_aux_clock_phaseshift extra_ps_lock (
    .clk(charge_pump),
    .clkout(charge_pump_delayed)
);
defparam extra_ps_lock.clk_phase_shift_by = sim_clkout_phase_shift;

always @(busy or reset)
begin
    if (reset  ===  1'b1)
        locked_real <= 1'b0;
    else if (busy == `S2GX_CMU_PLL_INACTIVE || adjust_without_lol == 1'b1) 
        locked_real <= 1'b1;
    else
        locked_real <= 1'b0;
end

assign clkout = clk_div_delayed && locked; 
assign locked = locked_real;
assign fbclkout = clk_pll;
assign vcobypassout = pll_clkin;

endmodule
module arriagx_hssi_tx_rx_det_DIV_BY_2 (CLK, RESET_N, CLKOUT); // synthesis syn_black_box

   input         CLK, RESET_N;
   output        CLKOUT;
   reg           CLKOUT;
   wire 	 NEXT_VAL;
   
   // state definition
   always @ (posedge CLK or negedge RESET_N)
     if (!RESET_N)
	  CLKOUT <= 1'b0;
     else
          CLKOUT <= NEXT_VAL;
   
    assign   NEXT_VAL = ~CLKOUT;

endmodule // div_by_2
// synchronizer to synchronize the receiver

module arriagx_hssi_tx_rx_det_CLK_GEN (CLK, RESET_N, CLKOUT);

   input         CLK, RESET_N;
   output	 CLKOUT;
   wire 	 CLKOUT;

   wire 	 CLK8M, CLK4M, CLK2M;
 	 
   arriagx_hssi_tx_rx_det_DIV_BY_2         DIV_1(.CLK(CLK), .RESET_N(RESET_N), .CLKOUT(CLK8M));
   arriagx_hssi_tx_rx_det_DIV_BY_2         DIV_2(.CLK(CLK8M), .RESET_N(RESET_N), .CLKOUT(CLK4M));
   arriagx_hssi_tx_rx_det_DIV_BY_2         DIV_3(.CLK(CLK4M), .RESET_N(RESET_N), .CLKOUT(CLK2M));
   arriagx_hssi_tx_rx_det_DIV_BY_2         DIV_4(.CLK(CLK2M), .RESET_N(RESET_N), .CLKOUT(CLKOUT));

endmodule // clk_gen
module arriagx_hssi_tx_rx_det_RCV_DET_SYNC (CLK, RESET_N, RCV_DET, RCV_DET_OUT); // synthesis syn_black_box

   input         CLK, RESET_N, RCV_DET;
   output        RCV_DET_OUT;
   reg           RCV_DET_OUT;
   reg 		 RCV_DET_MID; 	 

   always @ (posedge CLK or negedge RESET_N)
     if (!RESET_N)
       begin
	  RCV_DET_OUT <= 1'b0;
	  RCV_DET_MID <= 1'b0;
       end
     else
       begin
          RCV_DET_OUT <= RCV_DET_MID;
	  RCV_DET_MID <= RCV_DET;
       end

endmodule // rcv_det_sync
// receiver detect finite state machine
module arriagx_hssi_tx_rx_det_RCV_DET_FSM (CLK, RESET_N, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND); // synthesis syn_black_box

   input         CLK, RESET_N, COM_PASS, PROBE_PASS;
   
   output 	 RCV_FOUND, DET_ON, DETECT_VALID;
   reg [2:0] 	 STATE;
   reg [2:0] 	 NEXTSTATE;
   reg 		 RCV_FOUND, DET_ON, NEXT_RCV_FOUND, DETECT_VALID;
   
   reg		FAKE_RCV_PRESENT;
   
 // state definition
   parameter RESET   = 3'b000;
   parameter WAKE    = 3'b001;
   parameter STATE_1 = 3'b011;
   parameter STATE_2 = 3'b101;
   parameter HOLD    = 3'b100;
   
 
   initial
   begin
   	FAKE_RCV_PRESENT = 1'b1;
   end

// State logic and FSM
   always @ (posedge CLK or negedge RESET_N)
     if(!RESET_N)
       STATE <= RESET;
     else
       STATE <= NEXTSTATE;

   always @ (STATE or COM_PASS)
     begin
	case (STATE)
	  RESET: NEXTSTATE = WAKE;
	  WAKE: begin
	     if (COM_PASS) 
	     	NEXTSTATE = STATE_1;
	     else NEXTSTATE = WAKE;
	  end
	  STATE_1: NEXTSTATE = STATE_2;
	  STATE_2: NEXTSTATE = HOLD;
	  HOLD: NEXTSTATE = HOLD;
	  default: NEXTSTATE = RESET;
	endcase // case(state)
     end // always @ (state or com_pass)

// Output logic
   always @ (posedge CLK or negedge RESET_N)
     if(!RESET_N)
	  RCV_FOUND <= 1'b0;
     else
          RCV_FOUND <= NEXT_RCV_FOUND;

    always @ (NEXTSTATE or PROBE_PASS or FAKE_RCV_PRESENT)
      begin
	 if ((NEXTSTATE == STATE_2) && (!PROBE_PASS) && FAKE_RCV_PRESENT)  // probe pass goes up slow -> there is rx 
	   NEXT_RCV_FOUND = 1'b1;
	 else if ((NEXTSTATE == HOLD) && FAKE_RCV_PRESENT)
	   NEXT_RCV_FOUND = RCV_FOUND;
	 else    // probe pass goes up fast -> no rx
	   NEXT_RCV_FOUND = 1'b0;
      end
      
// there is no rcv_det_syn
   always @ (STATE)
     if (STATE == RESET)
       DET_ON = 1'b0;
     else
       DET_ON = 1'b1;
   	
   always @ (STATE)
     if (STATE == HOLD)
       DETECT_VALID = 1'b1;
     else
       DETECT_VALID = 1'b0;
   
endmodule // rcv_det_fsm
module arriagx_hssi_tx_rx_det_RCV_DET_CONTROL (CLK, RCV_DET_EN, RCV_DET_PDB, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND);
   input         CLK, RCV_DET_EN, RCV_DET_PDB, COM_PASS, PROBE_PASS;
   output 	 DET_ON, DETECT_VALID, RCV_FOUND;
   wire 	 RCV_DET_SYN;
   
   arriagx_hssi_tx_rx_det_RCV_DET_SYNC  XRCV_DET_SYNC (CLK, RCV_DET_PDB, RCV_DET_EN, RCV_DET_SYN);
   arriagx_hssi_tx_rx_det_RCV_DET_FSM   XRCV_DET_FSM (CLK, RCV_DET_SYN, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND);
endmodule // rcv_det_control
// Digital part of the receiver detection
module arriagx_hssi_tx_rx_det_RCV_DET_DIGITAL (OSCCLK, RCV_DET_PDB, RCV_DET_EN, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND);

   input  OSCCLK, RCV_DET_PDB, RCV_DET_EN, COM_PASS, PROBE_PASS;
   output DET_ON, RCV_FOUND, DETECT_VALID;
   wire   CLK;

   arriagx_hssi_tx_rx_det_CLK_GEN         XCLK_GEN (OSCCLK, RCV_DET_PDB, CLK);
   arriagx_hssi_tx_rx_det_RCV_DET_CONTROL XRCV_DET_CTRL(CLK, RCV_DET_EN, RCV_DET_PDB, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND);
   
endmodule // rcv_det_digital
// This module is the behavior model for rx_det block
// If there is rx -  set parameter RX_EXIST to 1, set to 0 otherwise

`timescale 1ps / 1ps

module arriagx_hssi_tx_rx_det (RX_DET_PDB, CLK15M, TX_DET_RX, RX_FOUND, RX_DET_VALID);

input           RX_DET_PDB, CLK15M, TX_DET_RX;
output 	        RX_FOUND, RX_DET_VALID;
wire            RX_FOUND, RX_DET_VALID;
wire 	        COM_PASS, PROBE_PASS, DET_ON;
   
   parameter 	RX_EXIST = 1'b1;

   assign #100000	COM_PASS = DET_ON;
   assign #100000 	PROBE_PASS = ~RX_EXIST;
   
   
    
arriagx_hssi_tx_rx_det_RCV_DET_DIGITAL XRCV_DET_DIGITAL (.OSCCLK (CLK15M), 
				  .RCV_DET_PDB (RX_DET_PDB), 
				  .RCV_DET_EN (TX_DET_RX), 
				  .COM_PASS (COM_PASS), 
				  .PROBE_PASS (PROBE_PASS), 
				  .DET_ON (DET_ON),
				  .DETECT_VALID (RX_DET_VALID),
				  .RCV_FOUND (RX_FOUND));

endmodule // RX_DET

`timescale 1 ps / 1 ps
module arriagx_hssi_tx_ser (
    serialclk,
    parallelclk,
    datain,
    reset,
    elecreset,
    rseriallpbkdatain,
    rseriallpbkctrl,
    rdwidth,
    rdoublewidth,
    serialdataout,
    seriallpbkdataout,
    clkout
);

input serialclk;
input parallelclk;
input [19:0] datain;
input reset;
input elecreset;           // Z dataout buf
input rseriallpbkdatain;
input rseriallpbkctrl;
input rdwidth;             // 0 => 8-bit, 1 => 10-bit
input rdoublewidth;        // 0 => 8/10,  1 => 16/20

output serialdataout;
output seriallpbkdataout;
output clkout;             // = parallelclk/2 when doublewidth 

wire         dataout_tmp;
reg          VOP_int;      // serial data from serializer
wire   [9:0] PUDR;         // parallel data from Byte Deserializer

reg    [9:0] PUDR_int;     // one latency
reg    [9:0] PUDR_sync_1;  // second latency
reg    [9:0] PUDR_sync;    // may be 1 fastclk latency: loaded with cmuclk0

reg          CMUCLKL_sync_1;
reg          CMUCLKL_sync; // parallel clock synch'd to cmuclk0 - 2/3rd fastclk latency

reg    [3:0] cnt;
reg    [3:0] index;
reg    [3:0] cnt1;
wire         load_cnt;
wire         CMUCLK0;
wire         CMUCLK0_dly;
wire         CMUCLK0_dly2;

reg          elecreset1, elecreset2;
reg          elecreset_dly;   // delay electric idle

// Byte Deserializer
wire       mux_clkin;
wire [9:0] mux_a_in;
wire [9:0] mux_b_in;
reg        mux_clk_by2;
reg  [9:0] mux_a_in_sync;
reg  [9:0] mux_b_in_sync;
wire [9:0] mux_d;
wire       mux_select;
reg  [9:0] mux_dataout;
wire       mux_clkout;

assign mux_clkin = parallelclk;
assign mux_a_in = {datain[9],datain[8],datain[7],datain[6],datain[5],
                   datain[4],datain[3],datain[2],datain[1],datain[0]};
assign mux_b_in = {datain[19],datain[18],datain[17],datain[16],datain[15],
                   datain[14],datain[13],datain[12],datain[11],datain[10]};
assign PUDR = mux_dataout;
assign mux_clkout = (rdoublewidth === 1'b1) ? mux_clk_by2 : mux_clkin;

initial 
begin
    mux_clk_by2 = 1'b0;
end

always @(posedge reset or posedge mux_clkin)
begin
    if (reset === 1'b1)
        mux_clk_by2 <= 1'b0;
    else if (mux_clkin)
        mux_clk_by2 <= ~mux_clk_by2;
end 

always @(posedge reset or posedge mux_clkout)
begin
    if (reset === 1'b1)
        begin
            mux_a_in_sync <= 10'd0;
            mux_b_in_sync <= 10'd0;
        end
    else if (mux_clkout)
        begin
            mux_a_in_sync <= mux_a_in;
            mux_b_in_sync <= mux_b_in;
        end
end 

assign mux_select = (rdoublewidth === 1'b1 && mux_clk_by2 === 1'b1) ? 1'b1 : 1'b0;
assign mux_d = (rdoublewidth !== 1'b1) ? mux_a_in_sync : (mux_select === 1'b1) ? mux_a_in_sync : mux_b_in_sync;

always @(posedge reset or posedge mux_clkin)
begin
    if (reset === 1'b1)
        mux_dataout <= 10'd0;
    else if (mux_clkin)
        mux_dataout <= mux_d;
end 


initial
begin
    CMUCLKL_sync_1 = 1'b0;
    CMUCLKL_sync   = 1'b0;
    cnt            = 4'd8;
    cnt1           = 4'd9;
    PUDR_sync_1    = 10'd0;
    PUDR_int       = 10'd0;
    PUDR_sync      = 10'd0;
end

always @ (posedge parallelclk)
begin
    elecreset1 <= elecreset;
    elecreset2 <= elecreset1;
    elecreset_dly <= elecreset2;
end

assign seriallpbkdataout = VOP_int;

assign dataout_tmp = (rseriallpbkctrl === 1'b1) ? rseriallpbkdatain : VOP_int;
assign serialdataout = (elecreset_dly === 1'b1) ? 1'bz : dataout_tmp;
assign clkout = mux_clkout;

assign CMUCLK0 = serialclk;
assign #100 CMUCLK0_dly = serialclk;
assign #10  CMUCLK0_dly2 = CMUCLK0_dly;

// 110 ps phase offset on serial bit
always @ (CMUCLK0_dly2)
      VOP_int <= PUDR_sync[index];

// LFCLKP is synchronized by 2 flops
always @ (posedge reset or posedge CMUCLK0)
begin
   if (reset)
      begin
         CMUCLKL_sync_1   <= 1'b0;
         CMUCLKL_sync     <= 1'b0;
      end
   else
      begin
         CMUCLKL_sync_1   <= parallelclk;
         CMUCLKL_sync     <= CMUCLKL_sync_1;
      end
end

// Load counter with 0   at rising edge of syncd slow clock
assign load_cnt = CMUCLKL_sync_1 & ~CMUCLKL_sync;

// counter to div by 5
always @ (posedge reset or posedge CMUCLK0)
begin
   if (reset === 1'b1)
      begin
         cnt <= 4'd8;
         cnt1 <= 4'd9;
      end
   else if (load_cnt === 1'b1 || ((cnt>=4'd8) && rdwidth) || ((cnt>=4'd6) && ~rdwidth))
      begin
         cnt <= 4'd0;
         cnt1 <= 4'd1;
      end
   else
      begin
         cnt <= cnt + 2;
         cnt1 <= cnt1 + 2;
      end
end

// Latch PUDR_int using parallelclk
always @ (posedge reset or posedge parallelclk)
begin
   if (reset === 1'b1)
      begin
         PUDR_sync_1 <= 10'd0;
         PUDR_int <= 10'd0;
      end
   else
      begin
         PUDR_int <= PUDR;
         PUDR_sync_1 <= PUDR_int;
      end
end

// Latch PUDR_sync using CMUCLK0
always @ (posedge reset or posedge CMUCLK0)
begin
   if (reset === 1'b1)
      PUDR_sync <= 10'd0;
   else if (load_cnt === 1'b1)
      PUDR_sync <= {PUDR_sync_1[9], PUDR_sync_1[8], PUDR_sync_1[7], PUDR_sync_1[6],
                    PUDR_sync_1[5], PUDR_sync_1[4], PUDR_sync_1[3], PUDR_sync_1[2],
                    PUDR_sync_1[1], PUDR_sync_1[0]};
end

       
// index will change from 0 to 9 incrementally at 2x speed as CMUCLK0
always @ (CMUCLK0_dly or cnt or cnt1)
   if (CMUCLK0_dly)
      index <= cnt;  
   else
      index <= cnt1;

endmodule


// 
// no digital behavior to simulate
//

`timescale 1 ps / 1 ps
module arriagx_hssi_calibration_block (
    clk,
    powerdn,
    enabletestbus,
    calibrationstatus
);

input  clk;
input  powerdn;
input  enabletestbus;
output [4:0] calibrationstatus;

parameter use_continuous_calibration_mode = "false";
parameter rx_calibration_write_test_value = 0;
parameter tx_calibration_write_test_value = 0;
parameter enable_rx_calibration_test_write = "false";
parameter enable_tx_calibration_test_write = "false";
parameter send_rx_calibration_status = "true";

endmodule

//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 65 mux21 7 
`timescale 1 ps / 1 ps
module  arriagx_hssi_phystatus_generator
	( 
	clk,
	latched_p0,
	latched_p0s,
	latched_p1,
	latched_p2,
	phystat_ena,
	phystatus,
	power_state_transition_done,
	power_state_transition_done_ena,
	powerdown,
	reset_n,
	rphystatus_rst_toggle,
	rx_detect_valid) /* synthesis synthesis_clearbox=1 */;
	input   clk;
	input   latched_p0;
	input   latched_p0s;
	input   latched_p1;
	input   latched_p2;
	input   phystat_ena;
	output   phystatus;
	input   power_state_transition_done;
	input   power_state_transition_done_ena;
	input   [1:0]  powerdown;
	input   reset_n;
	input   rphystatus_rst_toggle;
	input   rx_detect_valid;

	reg	nli0O27;
	reg	nli0O28;
	reg	nliil25;
	reg	nliil26;
	reg	nlili23;
	reg	nlili24;
	reg	nlilO21;
	reg	nlilO22;
	reg	nliOO19;
	reg	nliOO20;
	reg	nll0i15;
	reg	nll0i16;
	reg	nll0O13;
	reg	nll0O14;
	reg	nll1l17;
	reg	nll1l18;
	reg	nllil11;
	reg	nllil12;
	reg	nllli10;
	reg	nllli9;
	reg	nllll7;
	reg	nllll8;
	reg	nllOi5;
	reg	nllOi6;
	reg	nllOO3;
	reg	nllOO4;
	reg	nlO1l1;
	reg	nlO1l2;
	reg	n01i;
	reg	n1lO;
	reg	n1Oi;
	reg	n1Ol;
	reg	nl0l;
	reg	nl1O;
	reg	nl0i_clk_prev;
	wire	wire_nl0i_CLRN;
	wire	wire_nl0i_PRN;
	reg	n00i;
	reg	n00l;
	reg	n00O;
	reg	n01l;
	reg	n01O;
	reg	n0ii;
	reg	n0il;
	reg	n0iO;
	reg	n0li;
	reg	n10i;
	reg	n10l;
	reg	n10O;
	reg	n11i;
	reg	n11l;
	reg	n11O;
	reg	n1il;
	reg	n1iO;
	reg	n1li;
	reg	n1ll;
	reg	ni1i;
	reg	ni1l;
	reg	ni1O;
	reg	niii;
	reg	niil;
	reg	niiO;
	reg	nili;
	reg	niOi;
	reg	niOl;
	reg	niOO;
	reg	nl1l;
	reg	nlOOO;
	wire	wire_nl1i_CLRN;
	wire	wire_ni0i_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nlll_dataout;
	wire  nliOl;
	wire  nlliO;
	wire  nlllO;

	initial
		nli0O27 = 0;
	always @ ( posedge clk)
		  nli0O27 <= nli0O28;
	event nli0O27_event;
	initial
		#1 ->nli0O27_event;
	always @(nli0O27_event)
		nli0O27 <= {1{1'b1}};
	initial
		nli0O28 = 0;
	always @ ( posedge clk)
		  nli0O28 <= nli0O27;
	initial
		nliil25 = 0;
	always @ ( posedge clk)
		  nliil25 <= nliil26;
	event nliil25_event;
	initial
		#1 ->nliil25_event;
	always @(nliil25_event)
		nliil25 <= {1{1'b1}};
	initial
		nliil26 = 0;
	always @ ( posedge clk)
		  nliil26 <= nliil25;
	initial
		nlili23 = 0;
	always @ ( posedge clk)
		  nlili23 <= nlili24;
	event nlili23_event;
	initial
		#1 ->nlili23_event;
	always @(nlili23_event)
		nlili23 <= {1{1'b1}};
	initial
		nlili24 = 0;
	always @ ( posedge clk)
		  nlili24 <= nlili23;
	initial
		nlilO21 = 0;
	always @ ( posedge clk)
		  nlilO21 <= nlilO22;
	event nlilO21_event;
	initial
		#1 ->nlilO21_event;
	always @(nlilO21_event)
		nlilO21 <= {1{1'b1}};
	initial
		nlilO22 = 0;
	always @ ( posedge clk)
		  nlilO22 <= nlilO21;
	initial
		nliOO19 = 0;
	always @ ( posedge clk)
		  nliOO19 <= nliOO20;
	event nliOO19_event;
	initial
		#1 ->nliOO19_event;
	always @(nliOO19_event)
		nliOO19 <= {1{1'b1}};
	initial
		nliOO20 = 0;
	always @ ( posedge clk)
		  nliOO20 <= nliOO19;
	initial
		nll0i15 = 0;
	always @ ( posedge clk)
		  nll0i15 <= nll0i16;
	event nll0i15_event;
	initial
		#1 ->nll0i15_event;
	always @(nll0i15_event)
		nll0i15 <= {1{1'b1}};
	initial
		nll0i16 = 0;
	always @ ( posedge clk)
		  nll0i16 <= nll0i15;
	initial
		nll0O13 = 0;
	always @ ( posedge clk)
		  nll0O13 <= nll0O14;
	event nll0O13_event;
	initial
		#1 ->nll0O13_event;
	always @(nll0O13_event)
		nll0O13 <= {1{1'b1}};
	initial
		nll0O14 = 0;
	always @ ( posedge clk)
		  nll0O14 <= nll0O13;
	initial
		nll1l17 = 0;
	always @ ( posedge clk)
		  nll1l17 <= nll1l18;
	event nll1l17_event;
	initial
		#1 ->nll1l17_event;
	always @(nll1l17_event)
		nll1l17 <= {1{1'b1}};
	initial
		nll1l18 = 0;
	always @ ( posedge clk)
		  nll1l18 <= nll1l17;
	initial
		nllil11 = 0;
	always @ ( posedge clk)
		  nllil11 <= nllil12;
	event nllil11_event;
	initial
		#1 ->nllil11_event;
	always @(nllil11_event)
		nllil11 <= {1{1'b1}};
	initial
		nllil12 = 0;
	always @ ( posedge clk)
		  nllil12 <= nllil11;
	initial
		nllli10 = 0;
	always @ ( posedge clk)
		  nllli10 <= nllli9;
	initial
		nllli9 = 0;
	always @ ( posedge clk)
		  nllli9 <= nllli10;
	event nllli9_event;
	initial
		#1 ->nllli9_event;
	always @(nllli9_event)
		nllli9 <= {1{1'b1}};
	initial
		nllll7 = 0;
	always @ ( posedge clk)
		  nllll7 <= nllll8;
	event nllll7_event;
	initial
		#1 ->nllll7_event;
	always @(nllll7_event)
		nllll7 <= {1{1'b1}};
	initial
		nllll8 = 0;
	always @ ( posedge clk)
		  nllll8 <= nllll7;
	initial
		nllOi5 = 0;
	always @ ( posedge clk)
		  nllOi5 <= nllOi6;
	event nllOi5_event;
	initial
		#1 ->nllOi5_event;
	always @(nllOi5_event)
		nllOi5 <= {1{1'b1}};
	initial
		nllOi6 = 0;
	always @ ( posedge clk)
		  nllOi6 <= nllOi5;
	initial
		nllOO3 = 0;
	always @ ( posedge clk)
		  nllOO3 <= nllOO4;
	event nllOO3_event;
	initial
		#1 ->nllOO3_event;
	always @(nllOO3_event)
		nllOO3 <= {1{1'b1}};
	initial
		nllOO4 = 0;
	always @ ( posedge clk)
		  nllOO4 <= nllOO3;
	initial
		nlO1l1 = 0;
	always @ ( posedge clk)
		  nlO1l1 <= nlO1l2;
	event nlO1l1_event;
	initial
		#1 ->nlO1l1_event;
	always @(nlO1l1_event)
		nlO1l1 <= {1{1'b1}};
	initial
		nlO1l2 = 0;
	always @ ( posedge clk)
		  nlO1l2 <= nlO1l1;
	initial
	begin
		n01i = 0;
		n1lO = 0;
		n1Oi = 0;
		n1Ol = 0;
	end
	always @ ( posedge clk or  negedge reset_n)
	begin
		if (reset_n == 1'b0) 
		begin
			n01i <= 0;
			n1lO <= 0;
			n1Oi <= 0;
			n1Ol <= 0;
		end
		else if  (nliOl == 1'b1) 
		begin
			n01i <= n00l;
			n1lO <= n01l;
			n1Oi <= n01O;
			n1Ol <= n00i;
		end
	end
	initial
	begin
		nl0l = 0;
		nl1O = 0;
	end
	always @ (clk or wire_nl0i_PRN or wire_nl0i_CLRN)
	begin
		if (wire_nl0i_PRN == 1'b0) 
		begin
			nl0l <= 1;
			nl1O <= 1;
		end
		else if  (wire_nl0i_CLRN == 1'b0) 
		begin
			nl0l <= 0;
			nl1O <= 0;
		end
		else 
		if (clk != nl0i_clk_prev && clk == 1'b1) 
		begin
			nl0l <= nlllO;
			nl1O <= wire_nl0O_dataout;
		end
		nl0i_clk_prev <= clk;
	end
	assign
		wire_nl0i_CLRN = (nllll8 ^ nllll7),
		wire_nl0i_PRN = ((nllli10 ^ nllli9) & reset_n);
	initial
	begin
		n00i = 0;
		n00l = 0;
		n00O = 0;
		n01l = 0;
		n01O = 0;
		n0ii = 0;
		n0il = 0;
		n0iO = 0;
		n0li = 0;
		n10i = 0;
		n10l = 0;
		n10O = 0;
		n11i = 0;
		n11l = 0;
		n11O = 0;
		n1il = 0;
		n1iO = 0;
		n1li = 0;
		n1ll = 0;
		ni1i = 0;
		ni1l = 0;
		ni1O = 0;
		niii = 0;
		niil = 0;
		niiO = 0;
		nili = 0;
		niOi = 0;
		niOl = 0;
		niOO = 0;
		nl1l = 0;
		nlOOO = 0;
	end
	always @ ( posedge clk or  negedge wire_nl1i_CLRN)
	begin
		if (wire_nl1i_CLRN == 1'b0) 
		begin
			n00i <= 0;
			n00l <= 0;
			n00O <= 0;
			n01l <= 0;
			n01O <= 0;
			n0ii <= 0;
			n0il <= 0;
			n0iO <= 0;
			n0li <= 0;
			n10i <= 0;
			n10l <= 0;
			n10O <= 0;
			n11i <= 0;
			n11l <= 0;
			n11O <= 0;
			n1il <= 0;
			n1iO <= 0;
			n1li <= 0;
			n1ll <= 0;
			ni1i <= 0;
			ni1l <= 0;
			ni1O <= 0;
			niii <= 0;
			niil <= 0;
			niiO <= 0;
			nili <= 0;
			niOi <= 0;
			niOl <= 0;
			niOO <= 0;
			nl1l <= 0;
			nlOOO <= 0;
		end
		else 
		begin
			n00i <= n0il;
			n00l <= n0iO;
			n00O <= latched_p0;
			n01l <= n00O;
			n01O <= n0ii;
			n0ii <= latched_p0s;
			n0il <= latched_p1;
			n0iO <= latched_p2;
			n0li <= nlOOO;
			n10i <= n10l;
			n10l <= (((phystat_ena & (~ power_state_transition_done_ena)) & n10O) & (nli0O28 ^ nli0O27));
			n10O <= (~ (((((~ ((n1lO ^ n1il) ^ (~ (nlilO22 ^ nlilO21)))) & (~ ((n1Oi ^ n1iO) ^ (~ (nlili24 ^ nlili23))))) & (~ (n1Ol ^ n1li))) & (~ (n01i ^ n1ll))) & (nliil26 ^ nliil25)));
			n11i <= n11l;
			n11l <= n11O;
			n11O <= n10i;
			n1il <= n1lO;
			n1iO <= n1Oi;
			n1li <= n1Ol;
			n1ll <= n01i;
			ni1i <= ni1l;
			ni1l <= wire_nlil_dataout;
			ni1O <= ((rx_detect_valid & niil) & (~ niii));
			niii <= rx_detect_valid;
			niil <= niiO;
			niiO <= latched_p1;
			nili <= wire_nliO_dataout;
			niOi <= wire_ni0i_dataout;
			niOl <= niOO;
			niOO <= nl1l;
			nl1l <= power_state_transition_done;
			nlOOO <= n11i;
		end
	end
	assign
		wire_nl1i_CLRN = ((nllil12 ^ nllil11) & reset_n);
	or(wire_ni0i_dataout, wire_ni0l_dataout, (((~ wire_nlil_dataout) & ni1l) & (nll0O14 ^ nll0O13)));
	and(wire_ni0l_dataout, niOi, ~(wire_nliO_dataout));
	and(wire_nl0O_dataout, wire_nlii_dataout, ~(rphystatus_rst_toggle));
	and(wire_nlii_dataout, nl1O, ~(wire_nliO_dataout));
	and(wire_nlil_dataout, phystat_ena, (powerdown[0] & powerdown[1]));
	assign		wire_nliO_dataout = (power_state_transition_done_ena === 1'b1) ? (niOO & (~ niOl)) : n0li;
	or(wire_nlll_dataout, (((((nl0l | nili) | (~ (nlO1l2 ^ nlO1l1))) | ni1O) | nl1O) | (~ (nllOO4 ^ nllOO3))), ((((~ wire_nlil_dataout) & ni1i) | niOi) | (~ (nllOi6 ^ nllOi5))));
	assign
		nliOl = ((((((((~ n00l) & (~ n00i)) & (~ n01O)) & n01l) | (((((~ n00l) & (~ n00i)) & n01O) & (~ n01l)) & (nll0i16 ^ nll0i15))) | ((((~ n00l) & n00i) & (~ n01O)) & (~ n01l))) | (~ (nll1l18 ^ nll1l17))) | ((((n00l & (~ n00i)) & (~ n01O)) & (~ n01l)) & (nliOO20 ^ nliOO19))),
		nlliO = 1'b1,
		nlllO = 1'b0,
		phystatus = wire_nlll_dataout;
endmodule //arriagx_hssi_phystatus_generator
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 125 mux21 128 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_pipe_interface
	( 
	clk,
	latched_p0,
	latched_p0s,
	latched_p1,
	latched_p2,
	polinv_rx,
	polinv_rx_int,
	rclkcmpinsertpad,
	reset_n,
	rrdwidth_rx,
	rrx_pipe_enable,
	rx_detect_valid,
	rx_detect_valid_sync,
	rx_found,
	rxbeacon,
	rxd,
	rxd_ch,
	rxelecidle,
	rxelectricalidle,
	rxpolarity,
	rxstatus,
	rxvalid) /* synthesis synthesis_clearbox=1 */;
	input   clk;
	input   latched_p0;
	input   latched_p0s;
	input   latched_p1;
	input   latched_p2;
	input   polinv_rx;
	output   polinv_rx_int;
	input   rclkcmpinsertpad;
	input   reset_n;
	input   rrdwidth_rx;
	input   rrx_pipe_enable;
	input   rx_detect_valid;
	input   rx_detect_valid_sync;
	input   rx_found;
	input   rxbeacon;
	input   [63:0]  rxd;
	output   [63:0]  rxd_ch;
	output   rxelecidle;
	input   rxelectricalidle;
	input   rxpolarity;
	output   [2:0]  rxstatus;
	output   rxvalid;

	reg	nlllli41;
	reg	nlllli42;
	reg	nllllO39;
	reg	nllllO40;
	reg	nlllOl37;
	reg	nlllOl38;
	reg	nllO0i35;
	reg	nllO0i36;
	reg	nllOii33;
	reg	nllOii34;
	reg	nllOll31;
	reg	nllOll32;
	reg	nllOOl29;
	reg	nllOOl30;
	reg	nlO00O15;
	reg	nlO00O16;
	reg	nlO01l17;
	reg	nlO01l18;
	reg	nlO0ll13;
	reg	nlO0ll14;
	reg	nlO0Ol11;
	reg	nlO0Ol12;
	reg	nlO10l25;
	reg	nlO10l26;
	reg	nlO11i27;
	reg	nlO11i28;
	reg	nlO1ii23;
	reg	nlO1ii24;
	reg	nlO1iO21;
	reg	nlO1iO22;
	reg	nlO1Ol19;
	reg	nlO1Ol20;
	reg	nlOi0l7;
	reg	nlOi0l8;
	reg	nlOi1l10;
	reg	nlOi1l9;
	reg	nlOili5;
	reg	nlOili6;
	reg	nlOiOi3;
	reg	nlOiOi4;
	reg	nlOiOl1;
	reg	nlOiOl2;
	reg	n100l;
	reg	n100O;
	reg	n10i;
	reg	n10ii;
	reg	n10il;
	reg	n10iO;
	reg	n11il;
	reg	n11iO;
	reg	n11li;
	reg	n1lil;
	reg	n1lli;
	reg	n1llO;
	reg	niO0i;
	reg	niO0l;
	reg	niO0O;
	reg	niO1l;
	reg	niO1O;
	reg	niOii;
	reg	niOil;
	reg	niOiO;
	reg	niOli;
	reg	niOll;
	reg	niOlO;
	reg	niOOi;
	reg	niOOl;
	reg	niOOO;
	reg	nl00i;
	reg	nl00l;
	reg	nl00O;
	reg	nl01i;
	reg	nl01l;
	reg	nl01O;
	reg	nl0ii;
	reg	nl0il;
	reg	nl0iO;
	reg	nl0li;
	reg	nl0ll;
	reg	nl0lO;
	reg	nl0Oi;
	reg	nl0Ol;
	reg	nl0OO;
	reg	nl10i;
	reg	nl10l;
	reg	nl10O;
	reg	nl11i;
	reg	nl11l;
	reg	nl11O;
	reg	nl1ii;
	reg	nl1il;
	reg	nl1iO;
	reg	nl1li;
	reg	nl1ll;
	reg	nl1lO;
	reg	nl1Oi;
	reg	nl1Ol;
	reg	nl1OO;
	reg	nli0i;
	reg	nli0l;
	reg	nli0O;
	reg	nli1i;
	reg	nli1l;
	reg	nli1O;
	reg	nliii;
	reg	nliil;
	reg	nliiO;
	reg	nlili;
	reg	nlill;
	reg	nlilO;
	reg	nliOi;
	reg	nliOl;
	reg	nliOO;
	reg	nll0i;
	reg	nll0l;
	reg	nll0O;
	reg	nll1i;
	reg	nll1l;
	reg	nll1O;
	reg	nlOli;
	reg	nlOliO;
	reg	nlOlli;
	reg	nlOlll;
	reg	nlOllO;
	reg	nlOlOi;
	wire	wire_n11O_CLRN;
	wire	wire_n00i_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10li_dataout;
	wire	wire_n10ll_dataout;
	wire	wire_n10lO_dataout;
	wire	wire_n10Oi_dataout;
	wire	wire_n10Ol_dataout;
	wire	wire_n10OO_dataout;
	wire	wire_n11ll_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1i0i_dataout;
	wire	wire_n1i0l_dataout;
	wire	wire_n1i0O_dataout;
	wire	wire_n1i1i_dataout;
	wire	wire_n1i1l_dataout;
	wire	wire_n1i1O_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1iii_dataout;
	wire	wire_n1iil_dataout;
	wire	wire_n1iiO_dataout;
	wire	wire_n1ili_dataout;
	wire	wire_n1ill_dataout;
	wire	wire_n1ilO_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1iOi_dataout;
	wire	wire_n1iOl_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1liO_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1lOi_dataout;
	wire	wire_n1lOl_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_ni_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_nii_dataout;
	wire	wire_niii_dataout;
	wire	wire_niil_dataout;
	wire	wire_niiO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nili_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nli_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nllii_dataout;
	wire	wire_nllil_dataout;
	wire	wire_nlliO_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllli_dataout;
	wire	wire_nllll_dataout;
	wire	wire_nlllO_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nllOi_dataout;
	wire	wire_nllOl_dataout;
	wire	wire_nllOO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlO0i_dataout;
	wire	wire_nlO0l_dataout;
	wire	wire_nlO0O_dataout;
	wire	wire_nlO1i_dataout;
	wire	wire_nlO1l_dataout;
	wire	wire_nlO1O_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOlOl_dataout;
	wire	wire_nlOlOO_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOO0i_dataout;
	wire	wire_nlOO0l_dataout;
	wire	wire_nlOO0O_dataout;
	wire	wire_nlOO1i_dataout;
	wire	wire_nlOO1l_dataout;
	wire	wire_nlOO1O_dataout;
	wire	wire_nlOOii_dataout;
	wire	wire_nlOOil_dataout;
	wire	wire_nlOOiO_dataout;
	wire	wire_nlOOli_dataout;
	wire	wire_nlOOll_dataout;
	wire	wire_nlOOlO_dataout;
	wire	wire_nlOOOi_dataout;
	wire	wire_nlOOOl_dataout;
	wire	wire_nO_dataout;
	wire  nllO0O;
	wire  nllO1i;
	wire  nllO1l;
	wire  nllO1O;
	wire  nllOiO;
	wire  nllOli;
	wire  nllOOi;
	wire  nlO00i;
	wire  nlO00l;
	wire  nlO01i;
	wire  nlO0il;
	wire  nlO0iO;
	wire  nlO0li;
	wire  nlO0Oi;
	wire  nlO10i;
	wire  nlO11O;
	wire  nlO1ll;
	wire  nlO1lO;
	wire  nlO1Oi;
	wire  nlOi0i;
	wire  nlOi1i;
	wire  nlOiii;
	wire  nlOiil;
	wire  nlOiiO;
	wire  nlOilO;

	initial
		nlllli41 = 0;
	always @ ( posedge clk)
		  nlllli41 <= nlllli42;
	event nlllli41_event;
	initial
		#1 ->nlllli41_event;
	always @(nlllli41_event)
		nlllli41 <= {1{1'b1}};
	initial
		nlllli42 = 0;
	always @ ( posedge clk)
		  nlllli42 <= nlllli41;
	initial
		nllllO39 = 0;
	always @ ( posedge clk)
		  nllllO39 <= nllllO40;
	event nllllO39_event;
	initial
		#1 ->nllllO39_event;
	always @(nllllO39_event)
		nllllO39 <= {1{1'b1}};
	initial
		nllllO40 = 0;
	always @ ( posedge clk)
		  nllllO40 <= nllllO39;
	initial
		nlllOl37 = 0;
	always @ ( posedge clk)
		  nlllOl37 <= nlllOl38;
	event nlllOl37_event;
	initial
		#1 ->nlllOl37_event;
	always @(nlllOl37_event)
		nlllOl37 <= {1{1'b1}};
	initial
		nlllOl38 = 0;
	always @ ( posedge clk)
		  nlllOl38 <= nlllOl37;
	initial
		nllO0i35 = 0;
	always @ ( posedge clk)
		  nllO0i35 <= nllO0i36;
	event nllO0i35_event;
	initial
		#1 ->nllO0i35_event;
	always @(nllO0i35_event)
		nllO0i35 <= {1{1'b1}};
	initial
		nllO0i36 = 0;
	always @ ( posedge clk)
		  nllO0i36 <= nllO0i35;
	initial
		nllOii33 = 0;
	always @ ( posedge clk)
		  nllOii33 <= nllOii34;
	event nllOii33_event;
	initial
		#1 ->nllOii33_event;
	always @(nllOii33_event)
		nllOii33 <= {1{1'b1}};
	initial
		nllOii34 = 0;
	always @ ( posedge clk)
		  nllOii34 <= nllOii33;
	initial
		nllOll31 = 0;
	always @ ( posedge clk)
		  nllOll31 <= nllOll32;
	event nllOll31_event;
	initial
		#1 ->nllOll31_event;
	always @(nllOll31_event)
		nllOll31 <= {1{1'b1}};
	initial
		nllOll32 = 0;
	always @ ( posedge clk)
		  nllOll32 <= nllOll31;
	initial
		nllOOl29 = 0;
	always @ ( posedge clk)
		  nllOOl29 <= nllOOl30;
	event nllOOl29_event;
	initial
		#1 ->nllOOl29_event;
	always @(nllOOl29_event)
		nllOOl29 <= {1{1'b1}};
	initial
		nllOOl30 = 0;
	always @ ( posedge clk)
		  nllOOl30 <= nllOOl29;
	initial
		nlO00O15 = 0;
	always @ ( posedge clk)
		  nlO00O15 <= nlO00O16;
	event nlO00O15_event;
	initial
		#1 ->nlO00O15_event;
	always @(nlO00O15_event)
		nlO00O15 <= {1{1'b1}};
	initial
		nlO00O16 = 0;
	always @ ( posedge clk)
		  nlO00O16 <= nlO00O15;
	initial
		nlO01l17 = 0;
	always @ ( posedge clk)
		  nlO01l17 <= nlO01l18;
	event nlO01l17_event;
	initial
		#1 ->nlO01l17_event;
	always @(nlO01l17_event)
		nlO01l17 <= {1{1'b1}};
	initial
		nlO01l18 = 0;
	always @ ( posedge clk)
		  nlO01l18 <= nlO01l17;
	initial
		nlO0ll13 = 0;
	always @ ( posedge clk)
		  nlO0ll13 <= nlO0ll14;
	event nlO0ll13_event;
	initial
		#1 ->nlO0ll13_event;
	always @(nlO0ll13_event)
		nlO0ll13 <= {1{1'b1}};
	initial
		nlO0ll14 = 0;
	always @ ( posedge clk)
		  nlO0ll14 <= nlO0ll13;
	initial
		nlO0Ol11 = 0;
	always @ ( posedge clk)
		  nlO0Ol11 <= nlO0Ol12;
	event nlO0Ol11_event;
	initial
		#1 ->nlO0Ol11_event;
	always @(nlO0Ol11_event)
		nlO0Ol11 <= {1{1'b1}};
	initial
		nlO0Ol12 = 0;
	always @ ( posedge clk)
		  nlO0Ol12 <= nlO0Ol11;
	initial
		nlO10l25 = 0;
	always @ ( posedge clk)
		  nlO10l25 <= nlO10l26;
	event nlO10l25_event;
	initial
		#1 ->nlO10l25_event;
	always @(nlO10l25_event)
		nlO10l25 <= {1{1'b1}};
	initial
		nlO10l26 = 0;
	always @ ( posedge clk)
		  nlO10l26 <= nlO10l25;
	initial
		nlO11i27 = 0;
	always @ ( posedge clk)
		  nlO11i27 <= nlO11i28;
	event nlO11i27_event;
	initial
		#1 ->nlO11i27_event;
	always @(nlO11i27_event)
		nlO11i27 <= {1{1'b1}};
	initial
		nlO11i28 = 0;
	always @ ( posedge clk)
		  nlO11i28 <= nlO11i27;
	initial
		nlO1ii23 = 0;
	always @ ( posedge clk)
		  nlO1ii23 <= nlO1ii24;
	event nlO1ii23_event;
	initial
		#1 ->nlO1ii23_event;
	always @(nlO1ii23_event)
		nlO1ii23 <= {1{1'b1}};
	initial
		nlO1ii24 = 0;
	always @ ( posedge clk)
		  nlO1ii24 <= nlO1ii23;
	initial
		nlO1iO21 = 0;
	always @ ( posedge clk)
		  nlO1iO21 <= nlO1iO22;
	event nlO1iO21_event;
	initial
		#1 ->nlO1iO21_event;
	always @(nlO1iO21_event)
		nlO1iO21 <= {1{1'b1}};
	initial
		nlO1iO22 = 0;
	always @ ( posedge clk)
		  nlO1iO22 <= nlO1iO21;
	initial
		nlO1Ol19 = 0;
	always @ ( posedge clk)
		  nlO1Ol19 <= nlO1Ol20;
	event nlO1Ol19_event;
	initial
		#1 ->nlO1Ol19_event;
	always @(nlO1Ol19_event)
		nlO1Ol19 <= {1{1'b1}};
	initial
		nlO1Ol20 = 0;
	always @ ( posedge clk)
		  nlO1Ol20 <= nlO1Ol19;
	initial
		nlOi0l7 = 0;
	always @ ( posedge clk)
		  nlOi0l7 <= nlOi0l8;
	event nlOi0l7_event;
	initial
		#1 ->nlOi0l7_event;
	always @(nlOi0l7_event)
		nlOi0l7 <= {1{1'b1}};
	initial
		nlOi0l8 = 0;
	always @ ( posedge clk)
		  nlOi0l8 <= nlOi0l7;
	initial
		nlOi1l10 = 0;
	always @ ( posedge clk)
		  nlOi1l10 <= nlOi1l9;
	initial
		nlOi1l9 = 0;
	always @ ( posedge clk)
		  nlOi1l9 <= nlOi1l10;
	event nlOi1l9_event;
	initial
		#1 ->nlOi1l9_event;
	always @(nlOi1l9_event)
		nlOi1l9 <= {1{1'b1}};
	initial
		nlOili5 = 0;
	always @ ( posedge clk)
		  nlOili5 <= nlOili6;
	event nlOili5_event;
	initial
		#1 ->nlOili5_event;
	always @(nlOili5_event)
		nlOili5 <= {1{1'b1}};
	initial
		nlOili6 = 0;
	always @ ( posedge clk)
		  nlOili6 <= nlOili5;
	initial
		nlOiOi3 = 0;
	always @ ( posedge clk)
		  nlOiOi3 <= nlOiOi4;
	event nlOiOi3_event;
	initial
		#1 ->nlOiOi3_event;
	always @(nlOiOi3_event)
		nlOiOi3 <= {1{1'b1}};
	initial
		nlOiOi4 = 0;
	always @ ( posedge clk)
		  nlOiOi4 <= nlOiOi3;
	initial
		nlOiOl1 = 0;
	always @ ( posedge clk)
		  nlOiOl1 <= nlOiOl2;
	event nlOiOl1_event;
	initial
		#1 ->nlOiOl1_event;
	always @(nlOiOl1_event)
		nlOiOl1 <= {1{1'b1}};
	initial
		nlOiOl2 = 0;
	always @ ( posedge clk)
		  nlOiOl2 <= nlOiOl1;
	initial
	begin
		n100l = 0;
		n100O = 0;
		n10i = 0;
		n10ii = 0;
		n10il = 0;
		n10iO = 0;
		n11il = 0;
		n11iO = 0;
		n11li = 0;
		n1lil = 0;
		n1lli = 0;
		n1llO = 0;
		niO0i = 0;
		niO0l = 0;
		niO0O = 0;
		niO1l = 0;
		niO1O = 0;
		niOii = 0;
		niOil = 0;
		niOiO = 0;
		niOli = 0;
		niOll = 0;
		niOlO = 0;
		niOOi = 0;
		niOOl = 0;
		niOOO = 0;
		nl00i = 0;
		nl00l = 0;
		nl00O = 0;
		nl01i = 0;
		nl01l = 0;
		nl01O = 0;
		nl0ii = 0;
		nl0il = 0;
		nl0iO = 0;
		nl0li = 0;
		nl0ll = 0;
		nl0lO = 0;
		nl0Oi = 0;
		nl0Ol = 0;
		nl0OO = 0;
		nl10i = 0;
		nl10l = 0;
		nl10O = 0;
		nl11i = 0;
		nl11l = 0;
		nl11O = 0;
		nl1ii = 0;
		nl1il = 0;
		nl1iO = 0;
		nl1li = 0;
		nl1ll = 0;
		nl1lO = 0;
		nl1Oi = 0;
		nl1Ol = 0;
		nl1OO = 0;
		nli0i = 0;
		nli0l = 0;
		nli0O = 0;
		nli1i = 0;
		nli1l = 0;
		nli1O = 0;
		nliii = 0;
		nliil = 0;
		nliiO = 0;
		nlili = 0;
		nlill = 0;
		nlilO = 0;
		nliOi = 0;
		nliOl = 0;
		nliOO = 0;
		nll0i = 0;
		nll0l = 0;
		nll0O = 0;
		nll1i = 0;
		nll1l = 0;
		nll1O = 0;
		nlOli = 0;
		nlOliO = 0;
		nlOlli = 0;
		nlOlll = 0;
		nlOllO = 0;
		nlOlOi = 0;
	end
	always @ ( posedge clk or  negedge wire_n11O_CLRN)
	begin
		if (wire_n11O_CLRN == 1'b0) 
		begin
			n100l <= 0;
			n100O <= 0;
			n10i <= 0;
			n10ii <= 0;
			n10il <= 0;
			n10iO <= 0;
			n11il <= 0;
			n11iO <= 0;
			n11li <= 0;
			n1lil <= 0;
			n1lli <= 0;
			n1llO <= 0;
			niO0i <= 0;
			niO0l <= 0;
			niO0O <= 0;
			niO1l <= 0;
			niO1O <= 0;
			niOii <= 0;
			niOil <= 0;
			niOiO <= 0;
			niOli <= 0;
			niOll <= 0;
			niOlO <= 0;
			niOOi <= 0;
			niOOl <= 0;
			niOOO <= 0;
			nl00i <= 0;
			nl00l <= 0;
			nl00O <= 0;
			nl01i <= 0;
			nl01l <= 0;
			nl01O <= 0;
			nl0ii <= 0;
			nl0il <= 0;
			nl0iO <= 0;
			nl0li <= 0;
			nl0ll <= 0;
			nl0lO <= 0;
			nl0Oi <= 0;
			nl0Ol <= 0;
			nl0OO <= 0;
			nl10i <= 0;
			nl10l <= 0;
			nl10O <= 0;
			nl11i <= 0;
			nl11l <= 0;
			nl11O <= 0;
			nl1ii <= 0;
			nl1il <= 0;
			nl1iO <= 0;
			nl1li <= 0;
			nl1ll <= 0;
			nl1lO <= 0;
			nl1Oi <= 0;
			nl1Ol <= 0;
			nl1OO <= 0;
			nli0i <= 0;
			nli0l <= 0;
			nli0O <= 0;
			nli1i <= 0;
			nli1l <= 0;
			nli1O <= 0;
			nliii <= 0;
			nliil <= 0;
			nliiO <= 0;
			nlili <= 0;
			nlill <= 0;
			nlilO <= 0;
			nliOi <= 0;
			nliOl <= 0;
			nliOO <= 0;
			nll0i <= 0;
			nll0l <= 0;
			nll0O <= 0;
			nll1i <= 0;
			nll1l <= 0;
			nll1O <= 0;
			nlOli <= 0;
			nlOliO <= 0;
			nlOlli <= 0;
			nlOlll <= 0;
			nlOllO <= 0;
			nlOlOi <= 0;
		end
		else 
		begin
			n100l <= wire_n10li_dataout;
			n100O <= wire_n10ll_dataout;
			n10i <= wire_n1ii_dataout;
			n10ii <= wire_n10lO_dataout;
			n10il <= wire_n10Oi_dataout;
			n10iO <= wire_n1liO_dataout;
			n11il <= rxd[9];
			n11iO <= wire_n11ll_dataout;
			n11li <= rx_detect_valid_sync;
			n1lil <= wire_n1lll_dataout;
			n1lli <= wire_n1lOi_dataout;
			n1llO <= rx_detect_valid_sync;
			niO0i <= rxd[3];
			niO0l <= rxd[4];
			niO0O <= rxd[5];
			niO1l <= rxd[1];
			niO1O <= rxd[2];
			niOii <= rxd[6];
			niOil <= rxd[7];
			niOiO <= rxd[8];
			niOli <= rxd[9];
			niOll <= rxd[10];
			niOlO <= rxd[11];
			niOOi <= rxd[12];
			niOOl <= rxd[13];
			niOOO <= rxd[14];
			nl00i <= rxd[33];
			nl00l <= rxd[34];
			nl00O <= rxd[35];
			nl01i <= rxd[30];
			nl01l <= rxd[31];
			nl01O <= rxd[32];
			nl0ii <= rxd[36];
			nl0il <= rxd[37];
			nl0iO <= rxd[38];
			nl0li <= rxd[39];
			nl0ll <= rxd[40];
			nl0lO <= rxd[41];
			nl0Oi <= rxd[42];
			nl0Ol <= rxd[43];
			nl0OO <= rxd[44];
			nl10i <= rxd[18];
			nl10l <= rxd[19];
			nl10O <= rxd[20];
			nl11i <= rxd[15];
			nl11l <= rxd[16];
			nl11O <= rxd[17];
			nl1ii <= rxd[21];
			nl1il <= rxd[22];
			nl1iO <= rxd[23];
			nl1li <= rxd[24];
			nl1ll <= rxd[25];
			nl1lO <= rxd[26];
			nl1Oi <= rxd[27];
			nl1Ol <= rxd[28];
			nl1OO <= rxd[29];
			nli0i <= rxd[48];
			nli0l <= rxd[49];
			nli0O <= rxd[50];
			nli1i <= rxd[45];
			nli1l <= rxd[46];
			nli1O <= rxd[47];
			nliii <= rxd[51];
			nliil <= rxd[52];
			nliiO <= rxd[53];
			nlili <= rxd[54];
			nlill <= rxd[55];
			nlilO <= rxd[56];
			nliOi <= rxd[57];
			nliOl <= rxd[58];
			nliOO <= rxd[59];
			nll0i <= rxd[63];
			nll0l <= rxpolarity;
			nll0O <= wire_n10l_dataout;
			nll1i <= rxd[60];
			nll1l <= rxd[61];
			nll1O <= rxd[62];
			nlOli <= rxd[0];
			nlOliO <= wire_nlOlOl_dataout;
			nlOlli <= wire_nlOlOO_dataout;
			nlOlll <= wire_nlOO1i_dataout;
			nlOllO <= wire_nlOO1l_dataout;
			nlOlOi <= rxd[11];
		end
	end
	assign
		wire_n11O_CLRN = ((nlOiOi4 ^ nlOiOi3) & reset_n);
	assign		wire_n00i_dataout = (rrx_pipe_enable === 1'b1) ? niOil : rxd[7];
	assign		wire_n00l_dataout = (rrx_pipe_enable === 1'b1) ? niOiO : rxd[8];
	assign		wire_n00O_dataout = (rrx_pipe_enable === 1'b1) ? niOli : rxd[9];
	assign		wire_n01i_dataout = (rrx_pipe_enable === 1'b1) ? niO0l : rxd[4];
	assign		wire_n01l_dataout = (rrx_pipe_enable === 1'b1) ? niO0O : rxd[5];
	assign		wire_n01O_dataout = (rrx_pipe_enable === 1'b1) ? niOii : rxd[6];
	assign		wire_n0i_dataout = (rrx_pipe_enable === 1'b1) ? nliil : rxd[52];
	assign		wire_n0ii_dataout = (rrx_pipe_enable === 1'b1) ? niOll : rxd[10];
	assign		wire_n0il_dataout = (rrx_pipe_enable === 1'b1) ? niOlO : rxd[11];
	assign		wire_n0iO_dataout = (rrx_pipe_enable === 1'b1) ? niOOi : rxd[12];
	assign		wire_n0l_dataout = (rrx_pipe_enable === 1'b1) ? nliiO : rxd[53];
	assign		wire_n0li_dataout = (rrx_pipe_enable === 1'b1) ? niOOl : rxd[13];
	assign		wire_n0ll_dataout = (rrx_pipe_enable === 1'b1) ? niOOO : rxd[14];
	assign		wire_n0lO_dataout = (rrx_pipe_enable === 1'b1) ? nl11i : rxd[15];
	assign		wire_n0O_dataout = (rrx_pipe_enable === 1'b1) ? nlili : rxd[54];
	assign		wire_n0Oi_dataout = (rrx_pipe_enable === 1'b1) ? nl11l : rxd[16];
	assign		wire_n0Ol_dataout = (rrx_pipe_enable === 1'b1) ? nl11O : rxd[17];
	assign		wire_n0OO_dataout = (rrx_pipe_enable === 1'b1) ? nl10i : rxd[18];
	and(wire_n10l_dataout, rxelectricalidle, ~((latched_p2 & rxbeacon)));
	and(wire_n10li_dataout, wire_n10Ol_dataout, ~((~ rrdwidth_rx)));
	and(wire_n10ll_dataout, wire_n10OO_dataout, ~((~ rrdwidth_rx)));
	and(wire_n10lO_dataout, wire_n1i1i_dataout, ~((~ rrdwidth_rx)));
	and(wire_n10Oi_dataout, wire_n1i1l_dataout, ~((~ rrdwidth_rx)));
	and(wire_n10Ol_dataout, wire_n1i1O_dataout, ~(nlO1ll));
	and(wire_n10OO_dataout, nlO1lO, ~(nlO1ll));
	and(wire_n11ll_dataout, (((rx_found & rx_detect_valid_sync) & (nlO10l26 ^ nlO10l25)) & (~ n11li)), latched_p1);
	assign		wire_n1i_dataout = (rrx_pipe_enable === 1'b1) ? nli0l : rxd[49];
	and(wire_n1i0i_dataout, wire_n1iii_dataout, ~(nlO1lO));
	and(wire_n1i0l_dataout, wire_n1iil_dataout, ~(nlO1lO));
	and(wire_n1i0O_dataout, wire_n1iiO_dataout, ~(nlO0il));
	and(wire_n1i1i_dataout, wire_n1i0i_dataout, ~(nlO1ll));
	and(wire_n1i1l_dataout, wire_n1i0l_dataout, ~(nlO1ll));
	and(wire_n1i1O_dataout, wire_n1i0O_dataout, ~(nlO1lO));
	assign		wire_n1ii_dataout = (rrdwidth_rx === 1'b1) ? ((rxd[10] & rxd[42]) & (nlOiOl2 ^ nlOiOl1)) : rxd[10];
	or(wire_n1iii_dataout, wire_n1ili_dataout, nlO0il);
	and(wire_n1iil_dataout, wire_n1ill_dataout, ~(nlO0il));
	or(wire_n1iiO_dataout, wire_n1ilO_dataout, nlO00l);
	and(wire_n1ili_dataout, nlO01i, ~(nlO00l));
	and(wire_n1ill_dataout, wire_n1iOi_dataout, ~(nlO00l));
	and(wire_n1ilO_dataout, nlO1Oi, ~(nlO01i));
	assign		wire_n1iO_dataout = (rrx_pipe_enable === 1'b1) ? nll0O : rxelectricalidle;
	and(wire_n1iOi_dataout, wire_n1iOl_dataout, ~(nlO01i));
	and(wire_n1iOl_dataout, (rxd[45] & rxd[46]), ~(nlO1Oi));
	assign		wire_n1l_dataout = (rrx_pipe_enable === 1'b1) ? nli0O : rxd[50];
	and(wire_n1li_dataout, n10i, rrx_pipe_enable);
	and(wire_n1liO_dataout, rxd[43], rrdwidth_rx);
	assign		wire_n1ll_dataout = (rrx_pipe_enable === 1'b1) ? nll0l : polinv_rx;
	and(wire_n1lll_dataout, rxd[41], rrdwidth_rx);
	assign		wire_n1lO_dataout = (rrx_pipe_enable === 1'b1) ? nlOli : rxd[0];
	and(wire_n1lOi_dataout, wire_n1lOl_dataout, rrdwidth_rx);
	and(wire_n1lOl_dataout, (((rx_found & rx_detect_valid_sync) & (nlO0ll14 ^ nlO0ll13)) & (~ n1llO)), latched_p1);
	assign		wire_n1O_dataout = (rrx_pipe_enable === 1'b1) ? nliii : rxd[51];
	assign		wire_n1Oi_dataout = (rrx_pipe_enable === 1'b1) ? niO1l : rxd[1];
	assign		wire_n1Ol_dataout = (rrx_pipe_enable === 1'b1) ? niO1O : rxd[2];
	assign		wire_n1OO_dataout = (rrx_pipe_enable === 1'b1) ? niO0i : rxd[3];
	assign		wire_ni_dataout = (rrx_pipe_enable === 1'b1) ? nll1l : rxd[61];
	assign		wire_ni0i_dataout = (rrx_pipe_enable === 1'b1) ? nl1il : rxd[22];
	assign		wire_ni0l_dataout = (rrx_pipe_enable === 1'b1) ? nl1iO : rxd[23];
	assign		wire_ni0O_dataout = (rrx_pipe_enable === 1'b1) ? nl1li : rxd[24];
	assign		wire_ni1i_dataout = (rrx_pipe_enable === 1'b1) ? nl10l : rxd[19];
	assign		wire_ni1l_dataout = (rrx_pipe_enable === 1'b1) ? nl10O : rxd[20];
	assign		wire_ni1O_dataout = (rrx_pipe_enable === 1'b1) ? nl1ii : rxd[21];
	assign		wire_nii_dataout = (rrx_pipe_enable === 1'b1) ? nlill : rxd[55];
	assign		wire_niii_dataout = (rrx_pipe_enable === 1'b1) ? nl1ll : rxd[25];
	assign		wire_niil_dataout = (rrx_pipe_enable === 1'b1) ? nl1lO : rxd[26];
	assign		wire_niiO_dataout = (rrx_pipe_enable === 1'b1) ? nl1Oi : rxd[27];
	assign		wire_nil_dataout = (rrx_pipe_enable === 1'b1) ? nlilO : rxd[56];
	assign		wire_nili_dataout = (rrx_pipe_enable === 1'b1) ? nl1Ol : rxd[28];
	assign		wire_nill_dataout = (rrx_pipe_enable === 1'b1) ? nl1OO : rxd[29];
	assign		wire_nilO_dataout = (rrx_pipe_enable === 1'b1) ? nl01i : rxd[30];
	assign		wire_niO_dataout = (rrx_pipe_enable === 1'b1) ? nliOi : rxd[57];
	assign		wire_niOi_dataout = (rrx_pipe_enable === 1'b1) ? nl01l : rxd[31];
	assign		wire_niOl_dataout = (rrx_pipe_enable === 1'b1) ? nl01O : rxd[32];
	assign		wire_niOO_dataout = (rrx_pipe_enable === 1'b1) ? nl00i : rxd[33];
	assign		wire_nl_dataout = (rrx_pipe_enable === 1'b1) ? nll1O : rxd[62];
	assign		wire_nl0i_dataout = (rrx_pipe_enable === 1'b1) ? nl0il : rxd[37];
	assign		wire_nl0l_dataout = (rrx_pipe_enable === 1'b1) ? nl0iO : rxd[38];
	assign		wire_nl0O_dataout = (rrx_pipe_enable === 1'b1) ? nl0li : rxd[39];
	assign		wire_nl1i_dataout = (rrx_pipe_enable === 1'b1) ? nl00l : rxd[34];
	assign		wire_nl1l_dataout = (rrx_pipe_enable === 1'b1) ? nl00O : rxd[35];
	assign		wire_nl1O_dataout = (rrx_pipe_enable === 1'b1) ? nl0ii : rxd[36];
	assign		wire_nli_dataout = (rrx_pipe_enable === 1'b1) ? nliOl : rxd[58];
	assign		wire_nlii_dataout = (rrx_pipe_enable === 1'b1) ? nl0ll : rxd[40];
	assign		wire_nlil_dataout = (rrx_pipe_enable === 1'b1) ? nl0lO : rxd[41];
	assign		wire_nliO_dataout = (rrx_pipe_enable === 1'b1) ? nl0Oi : rxd[42];
	assign		wire_nll_dataout = (rrx_pipe_enable === 1'b1) ? nliOO : rxd[59];
	assign		wire_nlli_dataout = (rrx_pipe_enable === 1'b1) ? nl0Ol : rxd[43];
	assign		wire_nllii_dataout = ((~ rrx_pipe_enable) === 1'b1) ? rx_found : wire_nllli_dataout;
	assign		wire_nllil_dataout = ((~ rrx_pipe_enable) === 1'b1) ? rx_detect_valid : wire_nllll_dataout;
	assign		wire_nlliO_dataout = ((~ rrx_pipe_enable) === 1'b1) ? rxbeacon : wire_nlllO_dataout;
	assign		wire_nlll_dataout = (rrx_pipe_enable === 1'b1) ? nl0OO : rxd[44];
	or(wire_nllli_dataout, wire_nllOi_dataout, nlOiiO);
	or(wire_nllll_dataout, wire_nllOl_dataout, nlOiiO);
	and(wire_nlllO_dataout, wire_nllOO_dataout, ~(nlOiiO));
	assign		wire_nllO_dataout = (rrx_pipe_enable === 1'b1) ? nli1i : rxd[45];
	and(wire_nllOi_dataout, wire_nlO1i_dataout, ~(nlOiil));
	and(wire_nllOl_dataout, wire_nlO1l_dataout, ~(nlOiil));
	or(wire_nllOO_dataout, wire_nlO1O_dataout, nlOiil);
	assign		wire_nlO_dataout = (rrx_pipe_enable === 1'b1) ? nll1i : rxd[60];
	and(wire_nlO0i_dataout, wire_nlOii_dataout, ~(nlOi0i));
	or(wire_nlO0l_dataout, wire_nlOil_dataout, nlOi0i);
	or(wire_nlO0O_dataout, nlOi1i, nlOi0i);
	or(wire_nlO1i_dataout, wire_nlO0i_dataout, nlOiii);
	and(wire_nlO1l_dataout, wire_nlO0l_dataout, ~(nlOiii));
	or(wire_nlO1O_dataout, wire_nlO0O_dataout, nlOiii);
	assign		wire_nlOi_dataout = (rrx_pipe_enable === 1'b1) ? nli1l : rxd[46];
	or(wire_nlOii_dataout, wire_nlOiO_dataout, nlOi1i);
	or(wire_nlOil_dataout, nlO0Oi, nlOi1i);
	and(wire_nlOiO_dataout, (nlOliO | n100l), ~(nlO0Oi));
	assign		wire_nlOl_dataout = (rrx_pipe_enable === 1'b1) ? nli1O : rxd[47];
	and(wire_nlOlOl_dataout, wire_nlOO1O_dataout, ~(nllO1i));
	and(wire_nlOlOO_dataout, nllO1l, ~(nllO1i));
	assign		wire_nlOO_dataout = (rrx_pipe_enable === 1'b1) ? nli0i : rxd[48];
	and(wire_nlOO0i_dataout, wire_nlOOii_dataout, ~(nllO1l));
	and(wire_nlOO0l_dataout, wire_nlOOil_dataout, ~(nllO1l));
	and(wire_nlOO0O_dataout, wire_nlOOiO_dataout, ~(nllOOi));
	and(wire_nlOO1i_dataout, wire_nlOO0i_dataout, ~(nllO1i));
	and(wire_nlOO1l_dataout, wire_nlOO0l_dataout, ~(nllO1i));
	and(wire_nlOO1O_dataout, wire_nlOO0O_dataout, ~(nllO1l));
	or(wire_nlOOii_dataout, wire_nlOOli_dataout, nllOOi);
	and(wire_nlOOil_dataout, wire_nlOOll_dataout, ~(nllOOi));
	or(wire_nlOOiO_dataout, wire_nlOOlO_dataout, nllOli);
	and(wire_nlOOli_dataout, nllO0O, ~(nllOli));
	and(wire_nlOOll_dataout, wire_nlOOOi_dataout, ~(nllOli));
	and(wire_nlOOlO_dataout, nllO1O, ~(nllO0O));
	and(wire_nlOOOi_dataout, wire_nlOOOl_dataout, ~(nllO0O));
	and(wire_nlOOOl_dataout, (rxd[13] & rxd[14]), ~(nllO1O));
	assign		wire_nO_dataout = (rrx_pipe_enable === 1'b1) ? nll0i : rxd[63];
	assign
		nllO0O = (rclkcmpinsertpad & ((nlO11O & nllOiO) & (nllOii34 ^ nllOii33))),
		nllO1i = (((~ rxd[13]) & (~ rxd[14])) & (nlllOl38 ^ nlllOl37)),
		nllO1l = (rxd[13] & (~ rxd[14])),
		nllO1O = (rclkcmpinsertpad & ((nlO11O & (~ nllOiO)) & (nllO0i36 ^ nllO0i35))),
		nllOiO = ((((((((rxd[0] & rxd[1]) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]) & (nlllli42 ^ nlllli41)),
		nllOli = ((~ rclkcmpinsertpad) & (((~ nlO10i) & nlO11O) & (nllOll32 ^ nllOll31))),
		nllOOi = (((~ rclkcmpinsertpad) & ((nlO10i & nlO11O) & (nlO11i28 ^ nlO11i27))) & (nllOOl30 ^ nllOOl29)),
		nlO00i = (((((((rxd[32] & rxd[33]) & rxd[34]) & (~ rxd[35])) & rxd[36]) & rxd[37]) & rxd[38]) & rxd[39]),
		nlO00l = ((~ rclkcmpinsertpad) & (((~ nlO0li) & nlO0iO) & (nlO00O16 ^ nlO00O15))),
		nlO01i = ((rclkcmpinsertpad & (nlO0iO & nlO00i)) & (nlO01l18 ^ nlO01l17)),
		nlO0il = ((~ rclkcmpinsertpad) & (nlO0li & nlO0iO)),
		nlO0iO = ((~ rxd[45]) & rxd[46]),
		nlO0li = (((((((((~ rxd[32]) & rxd[33]) & rxd[34]) & rxd[35]) & rxd[36]) & rxd[37]) & rxd[38]) & rxd[39]) & (nlO1ii24 ^ nlO1ii23)),
		nlO0Oi = ((nlOlli | n100O) | (~ (nlO0Ol12 ^ nlO0Ol11))),
		nlO10i = ((((((((~ rxd[0]) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		nlO11O = (((~ rxd[13]) & rxd[14]) & (nllllO40 ^ nllllO39)),
		nlO1ll = ((~ rxd[45]) & (~ rxd[46])),
		nlO1lO = ((rxd[45] & (~ rxd[46])) & (nlO1iO22 ^ nlO1iO21)),
		nlO1Oi = (rclkcmpinsertpad & ((nlO0iO & (~ nlO00i)) & (nlO1Ol20 ^ nlO1Ol19))),
		nlOi0i = ((nlOlll | n10ii) | (~ (nlOi0l8 ^ nlOi0l7))),
		nlOi1i = ((nlOlOi | n10iO) | (~ (nlOi1l10 ^ nlOi1l9))),
		nlOiii = (nlOllO | n10il),
		nlOiil = (n11il | n1lil),
		nlOiiO = ((n11iO | n1lli) | (~ (nlOili6 ^ nlOili5))),
		nlOilO = 1'b1,
		polinv_rx_int = wire_n1ll_dataout,
		rxd_ch = {wire_nO_dataout, wire_nl_dataout, wire_ni_dataout, wire_nlO_dataout, wire_nll_dataout, wire_nli_dataout, wire_niO_dataout, wire_nil_dataout, wire_nii_dataout, wire_n0O_dataout, wire_n0l_dataout, wire_n0i_dataout, wire_n1O_dataout, wire_n1l_dataout, wire_n1i_dataout, wire_nlOO_dataout, wire_nlOl_dataout, wire_nlOi_dataout, wire_nllO_dataout, wire_nlll_dataout, wire_nlli_dataout, wire_nliO_dataout, wire_nlil_dataout, wire_nlii_dataout, wire_nl0O_dataout, wire_nl0l_dataout, wire_nl0i_dataout, wire_nl1O_dataout, wire_nl1l_dataout, wire_nl1i_dataout, wire_niOO_dataout, wire_niOl_dataout, wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout, wire_n0iO_dataout, wire_n0il_dataout, wire_n0ii_dataout, wire_n00O_dataout, wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout},
		rxelecidle = wire_n1iO_dataout,
		rxstatus = {wire_nlliO_dataout, wire_nllil_dataout, wire_nllii_dataout},
		rxvalid = wire_n1li_dataout;
endmodule //arriagx_hssi_rx_pipe_interface
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 86 mux21 56 oper_mux 1 
`timescale 1 ps / 1 ps
module  arriagx_hssi_tx_pipe_interface
	( 
	clk,
	powerdown,
	powerstate,
	refclk_b,
	refclk_b_reset_n,
	reset_n,
	rev_loopbk,
	revloopback,
	rtx_elec_idle_delay,
	rtx_pipe_enable,
	tx_elec_idle,
	tx_elec_idle_comp,
	txbeacon,
	txcompliance,
	txd,
	txd_ch,
	txdetectrx,
	txdetectrxloopback,
	txelecidle) /* synthesis synthesis_clearbox=1 */;
	input   clk;
	input   [1:0]  powerdown;
	output   [3:0]  powerstate;
	input   refclk_b;
	input   refclk_b_reset_n;
	input   reset_n;
	output   rev_loopbk;
	input   revloopback;
	input   [1:0]  rtx_elec_idle_delay;
	input   rtx_pipe_enable;
	output   tx_elec_idle;
	input   tx_elec_idle_comp;
	output   txbeacon;
	input   txcompliance;
	output   [43:0]  txd;
	input   [43:0]  txd_ch;
	output   txdetectrx;
	input   txdetectrxloopback;
	input   txelecidle;

	reg	n00li27;
	reg	n00li28;
	reg	n00lO25;
	reg	n00lO26;
	reg	n00Ol23;
	reg	n00Ol24;
	reg	n0i0O17;
	reg	n0i0O18;
	reg	n0i1i21;
	reg	n0i1i22;
	reg	n0i1O19;
	reg	n0i1O20;
	reg	n0iii15;
	reg	n0iii16;
	reg	n0ili13;
	reg	n0ili14;
	reg	n0ilO11;
	reg	n0ilO12;
	reg	n0iOl10;
	reg	n0iOl9;
	reg	n0l0l3;
	reg	n0l0l4;
	reg	n0l1i7;
	reg	n0l1i8;
	reg	n0l1O5;
	reg	n0l1O6;
	reg	n0lii1;
	reg	n0lii2;
	reg	n0OOl;
	reg	ni11i;
	reg	ni0lO;
	reg	ni0ll_clk_prev;
	wire	wire_ni0ll_CLRN;
	reg	n0Oli;
	reg	n0Oll;
	reg	n0OlO;
	reg	n0OOi;
	reg	ni1ii;
	wire	wire_ni10O_PRN;
	reg	ni11O;
	wire	wire_ni11l_ENA;
	reg	n0lOl;
	reg	n0lOO;
	reg	n0O0i;
	reg	n0O1i;
	reg	ni00O;
	reg	ni01i;
	reg	ni0Oi;
	reg	ni0Ol;
	reg	ni0OO;
	reg	nii0i;
	reg	nii0l;
	reg	nii0O;
	reg	nii1i;
	reg	nii1l;
	reg	nii1O;
	reg	niiii;
	reg	niiil;
	reg	niiiO;
	reg	niili;
	reg	niill;
	reg	niilO;
	reg	niiOi;
	reg	niiOl;
	reg	niiOO;
	reg	nil0i;
	reg	nil0l;
	reg	nil0O;
	reg	nil1i;
	reg	nil1l;
	reg	nil1O;
	reg	nilii;
	reg	nilil;
	reg	niliO;
	reg	nilli;
	reg	nilll;
	reg	nillO;
	reg	nilOi;
	reg	nilOl;
	reg	nilOO;
	reg	niO0i;
	reg	niO0l;
	reg	niO0O;
	reg	niO1i;
	reg	niO1l;
	reg	niO1O;
	reg	niOii;
	reg	niOil;
	reg	niOiO;
	reg	niOll;
	wire	wire_niOli_CLRN;
	wire	wire_n0Oii_dataout;
	wire	wire_n0Oil_dataout;
	wire	wire_ni00i_dataout;
	wire	wire_ni00l_dataout;
	wire	wire_ni01l_dataout;
	wire	wire_ni01O_dataout;
	wire	wire_ni0ii_dataout;
	wire	wire_ni0il_dataout;
	wire	wire_ni1iO_dataout;
	wire	wire_ni1ll_dataout;
	wire	wire_ni1Oi_dataout;
	wire	wire_ni1Ol_dataout;
	wire	wire_niOlO_dataout;
	wire	wire_niOOi_dataout;
	wire	wire_niOOl_dataout;
	wire	wire_niOOO_dataout;
	wire	wire_nl00i_dataout;
	wire	wire_nl00l_dataout;
	wire	wire_nl00O_dataout;
	wire	wire_nl01i_dataout;
	wire	wire_nl01l_dataout;
	wire	wire_nl01O_dataout;
	wire	wire_nl0ii_dataout;
	wire	wire_nl0il_dataout;
	wire	wire_nl0iO_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0ll_dataout;
	wire	wire_nl0lO_dataout;
	wire	wire_nl0Oi_dataout;
	wire	wire_nl0Ol_dataout;
	wire	wire_nl0OO_dataout;
	wire	wire_nl10i_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl10O_dataout;
	wire	wire_nl11i_dataout;
	wire	wire_nl11l_dataout;
	wire	wire_nl11O_dataout;
	wire	wire_nl1ii_dataout;
	wire	wire_nl1il_dataout;
	wire	wire_nl1iO_dataout;
	wire	wire_nl1li_dataout;
	wire	wire_nl1ll_dataout;
	wire	wire_nl1lO_dataout;
	wire	wire_nl1Oi_dataout;
	wire	wire_nl1Ol_dataout;
	wire	wire_nl1OO_dataout;
	wire	wire_nli0i_dataout;
	wire	wire_nli0l_dataout;
	wire	wire_nli0O_dataout;
	wire	wire_nli1i_dataout;
	wire	wire_nli1l_dataout;
	wire	wire_nli1O_dataout;
	wire	wire_nliii_dataout;
	wire	wire_nliil_dataout;
	wire	wire_nliiO_dataout;
	wire	wire_nlili_dataout;
	wire  wire_n0OiO_o;
	wire  n0i0l;
	wire  n0iiO;
	wire  n0ill;
	wire  n0l0O;

	initial
		n00li27 = 0;
	always @ ( posedge clk)
		  n00li27 <= n00li28;
	event n00li27_event;
	initial
		#1 ->n00li27_event;
	always @(n00li27_event)
		n00li27 <= {1{1'b1}};
	initial
		n00li28 = 0;
	always @ ( posedge clk)
		  n00li28 <= n00li27;
	initial
		n00lO25 = 0;
	always @ ( posedge clk)
		  n00lO25 <= n00lO26;
	event n00lO25_event;
	initial
		#1 ->n00lO25_event;
	always @(n00lO25_event)
		n00lO25 <= {1{1'b1}};
	initial
		n00lO26 = 0;
	always @ ( posedge clk)
		  n00lO26 <= n00lO25;
	initial
		n00Ol23 = 0;
	always @ ( posedge clk)
		  n00Ol23 <= n00Ol24;
	event n00Ol23_event;
	initial
		#1 ->n00Ol23_event;
	always @(n00Ol23_event)
		n00Ol23 <= {1{1'b1}};
	initial
		n00Ol24 = 0;
	always @ ( posedge clk)
		  n00Ol24 <= n00Ol23;
	initial
		n0i0O17 = 0;
	always @ ( posedge clk)
		  n0i0O17 <= n0i0O18;
	event n0i0O17_event;
	initial
		#1 ->n0i0O17_event;
	always @(n0i0O17_event)
		n0i0O17 <= {1{1'b1}};
	initial
		n0i0O18 = 0;
	always @ ( posedge clk)
		  n0i0O18 <= n0i0O17;
	initial
		n0i1i21 = 0;
	always @ ( posedge clk)
		  n0i1i21 <= n0i1i22;
	event n0i1i21_event;
	initial
		#1 ->n0i1i21_event;
	always @(n0i1i21_event)
		n0i1i21 <= {1{1'b1}};
	initial
		n0i1i22 = 0;
	always @ ( posedge clk)
		  n0i1i22 <= n0i1i21;
	initial
		n0i1O19 = 0;
	always @ ( posedge clk)
		  n0i1O19 <= n0i1O20;
	event n0i1O19_event;
	initial
		#1 ->n0i1O19_event;
	always @(n0i1O19_event)
		n0i1O19 <= {1{1'b1}};
	initial
		n0i1O20 = 0;
	always @ ( posedge clk)
		  n0i1O20 <= n0i1O19;
	initial
		n0iii15 = 0;
	always @ ( posedge clk)
		  n0iii15 <= n0iii16;
	event n0iii15_event;
	initial
		#1 ->n0iii15_event;
	always @(n0iii15_event)
		n0iii15 <= {1{1'b1}};
	initial
		n0iii16 = 0;
	always @ ( posedge clk)
		  n0iii16 <= n0iii15;
	initial
		n0ili13 = 0;
	always @ ( posedge clk)
		  n0ili13 <= n0ili14;
	event n0ili13_event;
	initial
		#1 ->n0ili13_event;
	always @(n0ili13_event)
		n0ili13 <= {1{1'b1}};
	initial
		n0ili14 = 0;
	always @ ( posedge clk)
		  n0ili14 <= n0ili13;
	initial
		n0ilO11 = 0;
	always @ ( posedge clk)
		  n0ilO11 <= n0ilO12;
	event n0ilO11_event;
	initial
		#1 ->n0ilO11_event;
	always @(n0ilO11_event)
		n0ilO11 <= {1{1'b1}};
	initial
		n0ilO12 = 0;
	always @ ( posedge clk)
		  n0ilO12 <= n0ilO11;
	initial
		n0iOl10 = 0;
	always @ ( posedge clk)
		  n0iOl10 <= n0iOl9;
	initial
		n0iOl9 = 0;
	always @ ( posedge clk)
		  n0iOl9 <= n0iOl10;
	event n0iOl9_event;
	initial
		#1 ->n0iOl9_event;
	always @(n0iOl9_event)
		n0iOl9 <= {1{1'b1}};
	initial
		n0l0l3 = 0;
	always @ ( posedge clk)
		  n0l0l3 <= n0l0l4;
	event n0l0l3_event;
	initial
		#1 ->n0l0l3_event;
	always @(n0l0l3_event)
		n0l0l3 <= {1{1'b1}};
	initial
		n0l0l4 = 0;
	always @ ( posedge clk)
		  n0l0l4 <= n0l0l3;
	initial
		n0l1i7 = 0;
	always @ ( posedge clk)
		  n0l1i7 <= n0l1i8;
	event n0l1i7_event;
	initial
		#1 ->n0l1i7_event;
	always @(n0l1i7_event)
		n0l1i7 <= {1{1'b1}};
	initial
		n0l1i8 = 0;
	always @ ( posedge clk)
		  n0l1i8 <= n0l1i7;
	initial
		n0l1O5 = 0;
	always @ ( posedge clk)
		  n0l1O5 <= n0l1O6;
	event n0l1O5_event;
	initial
		#1 ->n0l1O5_event;
	always @(n0l1O5_event)
		n0l1O5 <= {1{1'b1}};
	initial
		n0l1O6 = 0;
	always @ ( posedge clk)
		  n0l1O6 <= n0l1O5;
	initial
		n0lii1 = 0;
	always @ ( posedge clk)
		  n0lii1 <= n0lii2;
	event n0lii1_event;
	initial
		#1 ->n0lii1_event;
	always @(n0lii1_event)
		n0lii1 <= {1{1'b1}};
	initial
		n0lii2 = 0;
	always @ ( posedge clk)
		  n0lii2 <= n0lii1;
	initial
	begin
		n0OOl = 0;
		ni11i = 0;
	end
	always @ ( posedge refclk_b or  negedge refclk_b_reset_n)
	begin
		if (refclk_b_reset_n == 1'b0) 
		begin
			n0OOl <= 0;
			ni11i <= 0;
		end
		else 
		begin
			n0OOl <= ni11i;
			ni11i <= tx_elec_idle_comp;
		end
	end
	initial
	begin
		ni0lO = 0;
	end
	always @ (clk or reset_n or wire_ni0ll_CLRN)
	begin
		if (reset_n == 1'b0) 
		begin
			ni0lO <= 1;
		end
		else if  (wire_ni0ll_CLRN == 1'b0) 
		begin
			ni0lO <= 0;
		end
		else 
		if (clk != ni0ll_clk_prev && clk == 1'b1) 
		begin
			ni0lO <= txelecidle;
		end
		ni0ll_clk_prev <= clk;
	end
	assign
		wire_ni0ll_CLRN = (n0l0l4 ^ n0l0l3);
	initial
	begin
		n0Oli = 0;
		n0Oll = 0;
		n0OlO = 0;
		n0OOi = 0;
		ni1ii = 0;
	end
	always @ ( posedge refclk_b or  negedge wire_ni10O_PRN)
	begin
		if (wire_ni10O_PRN == 1'b0) 
		begin
			n0Oli <= 1;
			n0Oll <= 1;
			n0OlO <= 1;
			n0OOi <= 1;
			ni1ii <= 1;
		end
		else 
		begin
			n0Oli <= n0Oll;
			n0Oll <= n0OlO;
			n0OlO <= n0OOi;
			n0OOi <= n0ill;
			ni1ii <= n0Oli;
		end
	end
	assign
		wire_ni10O_PRN = ((n0ili14 ^ n0ili13) & refclk_b_reset_n);
	initial
	begin
		ni11O = 0;
	end
	always @ ( posedge refclk_b or  negedge refclk_b_reset_n)
	begin
		if (refclk_b_reset_n == 1'b0) 
		begin
			ni11O <= 1;
		end
		else if  (wire_ni11l_ENA == 1'b1) 
		begin
			ni11O <= n0iiO;
		end
	end
	assign
		wire_ni11l_ENA = (((ni11O & ni11i) & (~ n0OOl)) & (n0iii16 ^ n0iii15));
	initial
	begin
		n0lOl = 0;
		n0lOO = 0;
		n0O0i = 0;
		n0O1i = 0;
		ni00O = 0;
		ni01i = 0;
		ni0Oi = 0;
		ni0Ol = 0;
		ni0OO = 0;
		nii0i = 0;
		nii0l = 0;
		nii0O = 0;
		nii1i = 0;
		nii1l = 0;
		nii1O = 0;
		niiii = 0;
		niiil = 0;
		niiiO = 0;
		niili = 0;
		niill = 0;
		niilO = 0;
		niiOi = 0;
		niiOl = 0;
		niiOO = 0;
		nil0i = 0;
		nil0l = 0;
		nil0O = 0;
		nil1i = 0;
		nil1l = 0;
		nil1O = 0;
		nilii = 0;
		nilil = 0;
		niliO = 0;
		nilli = 0;
		nilll = 0;
		nillO = 0;
		nilOi = 0;
		nilOl = 0;
		nilOO = 0;
		niO0i = 0;
		niO0l = 0;
		niO0O = 0;
		niO1i = 0;
		niO1l = 0;
		niO1O = 0;
		niOii = 0;
		niOil = 0;
		niOiO = 0;
		niOll = 0;
	end
	always @ ( posedge clk or  negedge wire_niOli_CLRN)
	begin
		if (wire_niOli_CLRN == 1'b0) 
		begin
			n0lOl <= 0;
			n0lOO <= 0;
			n0O0i <= 0;
			n0O1i <= 0;
			ni00O <= 0;
			ni01i <= 0;
			ni0Oi <= 0;
			ni0Ol <= 0;
			ni0OO <= 0;
			nii0i <= 0;
			nii0l <= 0;
			nii0O <= 0;
			nii1i <= 0;
			nii1l <= 0;
			nii1O <= 0;
			niiii <= 0;
			niiil <= 0;
			niiiO <= 0;
			niili <= 0;
			niill <= 0;
			niilO <= 0;
			niiOi <= 0;
			niiOl <= 0;
			niiOO <= 0;
			nil0i <= 0;
			nil0l <= 0;
			nil0O <= 0;
			nil1i <= 0;
			nil1l <= 0;
			nil1O <= 0;
			nilii <= 0;
			nilil <= 0;
			niliO <= 0;
			nilli <= 0;
			nilll <= 0;
			nillO <= 0;
			nilOi <= 0;
			nilOl <= 0;
			nilOO <= 0;
			niO0i <= 0;
			niO0l <= 0;
			niO0O <= 0;
			niO1i <= 0;
			niO1l <= 0;
			niO1O <= 0;
			niOii <= 0;
			niOil <= 0;
			niOiO <= 0;
			niOll <= 0;
		end
		else 
		begin
			n0lOl <= ((rtx_pipe_enable & (((~ powerdown[0]) & powerdown[1]) & (n00Ol24 ^ n00Ol23))) & (n00lO26 ^ n00lO25));
			n0lOO <= (rtx_pipe_enable & ((powerdown[0] & (~ powerdown[1])) & (n0i1i22 ^ n0i1i21)));
			n0O0i <= (rtx_pipe_enable & ((powerdown[0] & powerdown[1]) & (n0i1O20 ^ n0i1O19)));
			n0O1i <= (rtx_pipe_enable & n0i0l);
			ni00O <= txelecidle;
			ni01i <= txdetectrxloopback;
			ni0Oi <= txcompliance;
			ni0Ol <= txd_ch[0];
			ni0OO <= txd_ch[1];
			nii0i <= txd_ch[5];
			nii0l <= txd_ch[6];
			nii0O <= txd_ch[7];
			nii1i <= txd_ch[2];
			nii1l <= txd_ch[3];
			nii1O <= txd_ch[4];
			niiii <= txd_ch[8];
			niiil <= txd_ch[9];
			niiiO <= txd_ch[11];
			niili <= txd_ch[12];
			niill <= txd_ch[13];
			niilO <= txd_ch[14];
			niiOi <= txd_ch[15];
			niiOl <= txd_ch[16];
			niiOO <= txd_ch[17];
			nil0i <= txd_ch[21];
			nil0l <= txd_ch[22];
			nil0O <= txd_ch[23];
			nil1i <= txd_ch[18];
			nil1l <= txd_ch[19];
			nil1O <= txd_ch[20];
			nilii <= txd_ch[24];
			nilil <= txd_ch[25];
			niliO <= txd_ch[26];
			nilli <= txd_ch[27];
			nilll <= txd_ch[28];
			nillO <= txd_ch[29];
			nilOi <= txd_ch[30];
			nilOl <= txd_ch[33];
			nilOO <= wire_n0Oii_dataout;
			niO0i <= txd_ch[37];
			niO0l <= txd_ch[38];
			niO0O <= txd_ch[39];
			niO1i <= txd_ch[34];
			niO1l <= txd_ch[35];
			niO1O <= txd_ch[36];
			niOii <= txd_ch[40];
			niOil <= txd_ch[41];
			niOiO <= txd_ch[42];
			niOll <= txd_ch[43];
		end
	end
	assign
		wire_niOli_CLRN = ((n0lii2 ^ n0lii1) & reset_n);
	and(wire_n0Oii_dataout, rtx_pipe_enable, n0i0l);
	assign		wire_n0Oil_dataout = ((~ n0ill) === 1'b1) ? n0OOi : wire_n0OiO_o;
	and(wire_ni00i_dataout, n0lOl, rtx_pipe_enable);
	and(wire_ni00l_dataout, n0O0i, rtx_pipe_enable);
	and(wire_ni01l_dataout, n0O1i, rtx_pipe_enable);
	and(wire_ni01O_dataout, n0lOO, rtx_pipe_enable);
	or(wire_ni0ii_dataout, wire_ni0il_dataout, (nilOO & ni0Oi));
	and(wire_ni0il_dataout, niiil, ~(((nilOO & (~ ni0Oi)) & (n0l1O6 ^ n0l1O5))));
	and(wire_ni1iO_dataout, (((~ ni00O) & n0O0i) & (n0iOl10 ^ n0iOl9)), ~((~ rtx_pipe_enable)));
	assign		wire_ni1ll_dataout = ((~ rtx_pipe_enable) === 1'b1) ? txdetectrxloopback : ((ni01i & n0lOl) & (n0l1i8 ^ n0l1i7));
	assign		wire_ni1Oi_dataout = ((~ rtx_pipe_enable) === 1'b1) ? txelecidle : wire_n0Oil_dataout;
	assign		wire_ni1Ol_dataout = ((~ rtx_pipe_enable) === 1'b1) ? revloopback : (ni01i & n0O1i);
	assign		wire_niOlO_dataout = (rtx_pipe_enable === 1'b1) ? ni0Ol : txd_ch[0];
	assign		wire_niOOi_dataout = (rtx_pipe_enable === 1'b1) ? ni0OO : txd_ch[1];
	assign		wire_niOOl_dataout = (rtx_pipe_enable === 1'b1) ? nii1i : txd_ch[2];
	assign		wire_niOOO_dataout = (rtx_pipe_enable === 1'b1) ? nii1l : txd_ch[3];
	assign		wire_nl00i_dataout = (rtx_pipe_enable === 1'b1) ? nil0l : txd_ch[22];
	assign		wire_nl00l_dataout = (rtx_pipe_enable === 1'b1) ? nil0O : txd_ch[23];
	assign		wire_nl00O_dataout = (rtx_pipe_enable === 1'b1) ? nilii : txd_ch[24];
	assign		wire_nl01i_dataout = (rtx_pipe_enable === 1'b1) ? nil1l : txd_ch[19];
	assign		wire_nl01l_dataout = (rtx_pipe_enable === 1'b1) ? nil1O : txd_ch[20];
	assign		wire_nl01O_dataout = (rtx_pipe_enable === 1'b1) ? nil0i : txd_ch[21];
	assign		wire_nl0ii_dataout = (rtx_pipe_enable === 1'b1) ? nilil : txd_ch[25];
	assign		wire_nl0il_dataout = (rtx_pipe_enable === 1'b1) ? niliO : txd_ch[26];
	assign		wire_nl0iO_dataout = (rtx_pipe_enable === 1'b1) ? nilli : txd_ch[27];
	assign		wire_nl0li_dataout = (rtx_pipe_enable === 1'b1) ? nilll : txd_ch[28];
	assign		wire_nl0ll_dataout = (rtx_pipe_enable === 1'b1) ? nillO : txd_ch[29];
	assign		wire_nl0lO_dataout = (rtx_pipe_enable === 1'b1) ? nilOi : txd_ch[30];
	and(wire_nl0Oi_dataout, txd_ch[31], ~(rtx_pipe_enable));
	assign		wire_nl0Ol_dataout = (rtx_pipe_enable === 1'b1) ? ni0lO : txd_ch[32];
	assign		wire_nl0OO_dataout = (rtx_pipe_enable === 1'b1) ? nilOl : txd_ch[33];
	assign		wire_nl10i_dataout = (rtx_pipe_enable === 1'b1) ? nii0O : txd_ch[7];
	assign		wire_nl10l_dataout = (rtx_pipe_enable === 1'b1) ? niiii : txd_ch[8];
	assign		wire_nl10O_dataout = (rtx_pipe_enable === 1'b1) ? wire_ni0ii_dataout : txd_ch[9];
	assign		wire_nl11i_dataout = (rtx_pipe_enable === 1'b1) ? nii1O : txd_ch[4];
	assign		wire_nl11l_dataout = (rtx_pipe_enable === 1'b1) ? nii0i : txd_ch[5];
	assign		wire_nl11O_dataout = (rtx_pipe_enable === 1'b1) ? nii0l : txd_ch[6];
	assign		wire_nl1ii_dataout = (rtx_pipe_enable === 1'b1) ? ni0lO : txd_ch[10];
	assign		wire_nl1il_dataout = (rtx_pipe_enable === 1'b1) ? niiiO : txd_ch[11];
	assign		wire_nl1iO_dataout = (rtx_pipe_enable === 1'b1) ? niili : txd_ch[12];
	assign		wire_nl1li_dataout = (rtx_pipe_enable === 1'b1) ? niill : txd_ch[13];
	assign		wire_nl1ll_dataout = (rtx_pipe_enable === 1'b1) ? niilO : txd_ch[14];
	assign		wire_nl1lO_dataout = (rtx_pipe_enable === 1'b1) ? niiOi : txd_ch[15];
	assign		wire_nl1Oi_dataout = (rtx_pipe_enable === 1'b1) ? niiOl : txd_ch[16];
	assign		wire_nl1Ol_dataout = (rtx_pipe_enable === 1'b1) ? niiOO : txd_ch[17];
	assign		wire_nl1OO_dataout = (rtx_pipe_enable === 1'b1) ? nil1i : txd_ch[18];
	assign		wire_nli0i_dataout = (rtx_pipe_enable === 1'b1) ? niO0i : txd_ch[37];
	assign		wire_nli0l_dataout = (rtx_pipe_enable === 1'b1) ? niO0l : txd_ch[38];
	assign		wire_nli0O_dataout = (rtx_pipe_enable === 1'b1) ? niO0O : txd_ch[39];
	assign		wire_nli1i_dataout = (rtx_pipe_enable === 1'b1) ? niO1i : txd_ch[34];
	assign		wire_nli1l_dataout = (rtx_pipe_enable === 1'b1) ? niO1l : txd_ch[35];
	assign		wire_nli1O_dataout = (rtx_pipe_enable === 1'b1) ? niO1O : txd_ch[36];
	assign		wire_nliii_dataout = (rtx_pipe_enable === 1'b1) ? niOii : txd_ch[40];
	assign		wire_nliil_dataout = (rtx_pipe_enable === 1'b1) ? niOil : txd_ch[41];
	assign		wire_nliiO_dataout = (rtx_pipe_enable === 1'b1) ? niOiO : txd_ch[42];
	assign		wire_nlili_dataout = (rtx_pipe_enable === 1'b1) ? niOll : txd_ch[43];
	oper_mux   n0OiO
	( 
	.data({ni1ii, n0Oli, ((n0i0O18 ^ n0i0O17) & n0Oll), n0OlO}),
	.o(wire_n0OiO_o),
	.sel({rtx_elec_idle_delay[1:0]}));
	defparam
		n0OiO.width_data = 4,
		n0OiO.width_sel = 2;
	assign
		n0i0l = (((~ powerdown[0]) & (~ powerdown[1])) & (n00li28 ^ n00li27)),
		n0iiO = 1'b0,
		n0ill = ((tx_elec_idle_comp | ni11O) | (~ (n0ilO12 ^ n0ilO11))),
		n0l0O = 1'b1,
		powerstate = {wire_ni00l_dataout, wire_ni00i_dataout, wire_ni01O_dataout, wire_ni01l_dataout},
		rev_loopbk = wire_ni1Ol_dataout,
		tx_elec_idle = wire_ni1Oi_dataout,
		txbeacon = wire_ni1iO_dataout,
		txd = {wire_nlili_dataout, wire_nliiO_dataout, wire_nliil_dataout, wire_nliii_dataout, wire_nli0O_dataout, wire_nli0l_dataout, wire_nli0i_dataout, wire_nli1O_dataout, wire_nli1l_dataout, wire_nli1i_dataout, wire_nl0OO_dataout, wire_nl0Ol_dataout, wire_nl0Oi_dataout, wire_nl0lO_dataout, wire_nl0ll_dataout, wire_nl0li_dataout, wire_nl0iO_dataout, wire_nl0il_dataout, wire_nl0ii_dataout, wire_nl00O_dataout, wire_nl00l_dataout, wire_nl00i_dataout, wire_nl01O_dataout, wire_nl01l_dataout, wire_nl01i_dataout, wire_nl1OO_dataout, wire_nl1Ol_dataout, wire_nl1Oi_dataout, wire_nl1lO_dataout, wire_nl1ll_dataout, wire_nl1li_dataout, wire_nl1iO_dataout, wire_nl1il_dataout, wire_nl1ii_dataout, wire_nl10O_dataout, wire_nl10l_dataout, wire_nl10i_dataout, wire_nl11O_dataout, wire_nl11l_dataout, wire_nl11i_dataout, wire_niOOO_dataout, wire_niOOl_dataout, wire_niOOi_dataout, wire_niOlO_dataout},
		txdetectrx = wire_ni1ll_dataout;
endmodule //arriagx_hssi_tx_pipe_interface
//synopsys translate_on
//VALID FILE

//************************************************************
// Description:
// pipe_interface_top
//
// This is the top module for the PIPE Interface.
// 
//************************************************************


`timescale 1 ns / 1 ps

module arriagx_hssi_q_pipe_interface_top (

	// General signals
	pipe_tx_clk,
	pipe_rx_clk,
	refclk_b,
	tx_pipe_reset,
	rx_pipe_reset,
	refclk_b_reset,
	
	// CRAM 
	rtx_pipe_enable,
	rrx_pipe_enable,
	rrdwidth_rx,
	rtx_elec_idle_delay,
	rrx_detect_bypass,
	rclkcmpinsertpad,
	rphystatus_rst_toggle,
	

	// PLD - PIPE Interface
	// TX PIPE Interface: Command 
	txdetectrxloopback,
	txelecidle,
	txcompliance,
	powerdown,
	
	// TX PIPE Interface: Data
	txd_ch,
	
	// RX PIPE Interface: Command/Status
	rxpolarity,
	
	rxvalid,
	rxelecidle,
	rxstatus,
	
	// RX PIPE Interface: Data
	rxd_ch,
	
	// PHYStatus Generator
	phystatus,
	
	// Commands
	revloopback,
	polinv_rx,
	
	// PIPE - PCS Inteface
	// TX PIPE Interface
	txd,
	rev_loopbk,
	tx_elec_idle_comp,

	// RX PIPE Interface
	rxd,
	polinv_rx_int,
	
	// PIPE - PMA Interface
	// TX PIPE Interface
	tx_elec_idle,
	txdetectrx,
	powerstate,
	txbeacon,
	
	// RX PIPE Interface
	rx_found,
	rx_detect_valid,
	rxelectricalidle,
	rxbeacon,

	txdetectrxin, //shawn
	powerstatein, //shawn
	use_powerstatein, //shawn

	
	// PHYStatus Generator
	power_state_transition_done,
	power_state_transition_done_ena
);

//********************************************************************************
// INCLUDE STATEMENTS
//********************************************************************************

//********************************************************************************
// I/O SIGNALS
//********************************************************************************
	// General signals
input           txdetectrxin; //shawn
input [3:0]		powerstatein; //shawn
input           use_powerstatein; //shawn

input			pipe_tx_clk;
input			pipe_rx_clk;
input			refclk_b;
input			tx_pipe_reset;
input			rx_pipe_reset;
input			refclk_b_reset;
	
	// CRAM 
input			rtx_pipe_enable;
input			rrx_pipe_enable;
input			rrdwidth_rx;
input	[1:0]	rtx_elec_idle_delay;
input			rrx_detect_bypass;
input			rclkcmpinsertpad;
input			rphystatus_rst_toggle;

	// PLD - PIPE Interface
	// TX PIPE Interface: Command 
input			txdetectrxloopback;
input			txelecidle;
input			txcompliance;
input	[1:0]	powerdown;
	
	// TX PIPE Interface: Data
input	[43:0]	txd_ch;
	
	// RX PIPE Interface: Command/Status
input			rxpolarity;
	
output			rxvalid;
output			rxelecidle;
output	[2:0]	rxstatus;
	
	// RX PIPE Interface: Data
output	[63:0]	rxd_ch;
	
	// PHYStatus Generator
output			phystatus;
	
	// Commands
input			revloopback;
input			polinv_rx;
	
	// PIPE - PCS Inteface
	// TX PIPE Interface
output	[43:0]	txd;
output			rev_loopbk;
input			tx_elec_idle_comp;

	// RX PIPE Interface
input	[63:0]	rxd;
output			polinv_rx_int;
	
	// PIPE - PMA Interface
	// TX PIPE Interface
output			tx_elec_idle;
output			txdetectrx;
output	[3:0]	powerstate;
output			txbeacon;
	
	// RX PIPE Interface
input			rx_found;
input			rx_detect_valid;
input			rxelectricalidle;
input			rxbeacon;
	
	// PHYStatus Generator
input			power_state_transition_done;
input			power_state_transition_done_ena;

//********************************************************************************
// PARAMETERS
//********************************************************************************

//********************************************************************************
// DECLARATIONS
//********************************************************************************

wire			phystat_ena;


reg			rx_detect_valid_reg_0;
reg			rx_detect_valid_reg_1;

wire			tx_pipe_reset_n;
wire			rx_pipe_reset_n;
wire			refclk_b_reset_n;	// reset for txelecidle_d_generator

reg			txdetectrx_reg_0;
reg			txdetectrx_reg_1;
reg			txdetectrx_reg_2;
reg			txdetectrx_reg_3;
reg			txdetectrx_reg_4;
reg			txdetectrx_reg_5;
reg			txdetectrx_reg_6;

reg			bypass_rx_found;
reg			bypass_rx_detect_valid;

wire			rx_found_int;
wire			rx_detect_valid_int;

wire			latched_p0;
wire			latched_p0s;
wire			latched_p1;
wire			latched_p2;

wire            tmp_txdetectrxin;   //shawn

//********************************************************************************
// ASSIGN STATEMENTS
//********************************************************************************
assign phystat_ena = rtx_pipe_enable || rrx_pipe_enable;

assign tx_pipe_reset_n = ~tx_pipe_reset;
assign rx_pipe_reset_n = ~rx_pipe_reset;
assign refclk_b_reset_n = ~refclk_b_reset;

assign rx_found_int = rrx_detect_bypass? bypass_rx_found: rx_found;
assign rx_detect_valid_int = rrx_detect_bypass? bypass_rx_detect_valid: rx_detect_valid_reg_1;

assign tmp_txdetectrxin = (use_powerstatein == 1'b1) ? txdetectrxin : txdetectrx;  //shawn

assign latched_p0 = (use_powerstatein == 1'b1) ? powerstatein[0] : powerstate [0]; //shawn
assign latched_p0s = (use_powerstatein == 1'b1) ? powerstatein[1] : powerstate [1]; //shawn;
assign latched_p1 = (use_powerstatein == 1'b1) ? powerstatein[2] : powerstate [2]; //shawn;
assign latched_p2 = (use_powerstatein == 1'b1) ? powerstatein[3] : powerstate [3]; //shawn;
//********************************************************************************
// SUBMODULE INSTANTIATIONS
//********************************************************************************

arriagx_hssi_tx_pipe_interface tx_pipe_interface_inst (

	// General signals
	.clk							(pipe_tx_clk),
	.refclk_b						(refclk_b),
	.reset_n						(tx_pipe_reset_n),
	.refclk_b_reset_n				(refclk_b_reset_n),
	
	// CRAM 
	.rtx_pipe_enable				(rtx_pipe_enable),
	.rtx_elec_idle_delay			(rtx_elec_idle_delay),
	
	// PLD - PIPE Interface
	// TX PIPE Interface: Command
	.txdetectrxloopback				(txdetectrxloopback),
	.txelecidle					(txelecidle),
	.txcompliance					(txcompliance),
	.powerdown					(powerdown),
	
	// TX PIPE Interface: Data
	.txd_ch						(txd_ch),
	
	// Commands
	.revloopback					(revloopback),
	
	// PIPE - PCS Inteface
	// TX PIPE Interface
	.txd							(txd),
	.rev_loopbk					(rev_loopbk),
	.tx_elec_idle_comp				(tx_elec_idle_comp),
	
	
	// PIPE - PMA Interface
	.tx_elec_idle					(tx_elec_idle),
	.txdetectrx					(txdetectrx),
	.txbeacon						(txbeacon),

	// Central PCS
	.powerstate					(powerstate)
	
);


arriagx_hssi_rx_pipe_interface rx_pipe_interface_inst (

	// General signals
	.clk							(pipe_rx_clk),
	.reset_n						(rx_pipe_reset_n),
	
	// CRAM 
	.rrx_pipe_enable				(rrx_pipe_enable),
	.rrdwidth_rx					(rrdwidth_rx),
	.rclkcmpinsertpad				(rclkcmpinsertpad),
	
	// PLD - PIPE Interface
	// RX PIPE Interface: Command/Status
	.rxpolarity					(rxpolarity),
	
	.rxvalid						(rxvalid),
	.rxelecidle					(rxelecidle),
	.rxstatus						(rxstatus),
	
	// RX PIPE Interface: Data
	.rxd_ch						(rxd_ch),
	
	// Commands
	.polinv_rx					(polinv_rx),
	
	// PIPE - PCS Inteface
	// RX PIPE Interface
	.rxd							(rxd),
	.polinv_rx_int					(polinv_rx_int),

	// Latched Power State Signals
	.latched_p0					(latched_p0),
	.latched_p0s					(latched_p0s),
	.latched_p1					(latched_p1),
	.latched_p2					(latched_p2),
	
	// PIPE - PMA Interface
	// TX PIPE Interface
	.rx_found						(rx_found_int),
	.rx_detect_valid				(rx_detect_valid),
	.rx_detect_valid_sync			(rx_detect_valid_int),	
	
	// RX PIPE Interface
	.rxelectricalidle				(rxelectricalidle),
	.rxbeacon						(rxbeacon)
	
);

arriagx_hssi_phystatus_generator phystatus_generator_inst (

	// General signals
	.clk							(pipe_rx_clk),
	.reset_n						(rx_pipe_reset_n),
	
	//CRAM
	.phystat_ena					(phystat_ena),
	.rphystatus_rst_toggle			(rphystatus_rst_toggle),

	// PLD Interface
	.powerdown					(powerdown),
	.phystatus					(phystatus),
	
	// Latched Power State Signals
	.latched_p0					(latched_p0),
	.latched_p0s					(latched_p0s),
	.latched_p1					(latched_p1),
	.latched_p2					(latched_p2),

	// PMA interface
	// TX PMA Interface
	.rx_detect_valid				(rx_detect_valid_int),

	// RX PMA Interface
	.power_state_transition_done		(power_state_transition_done),
	.power_state_transition_done_ena	(power_state_transition_done_ena)
	
);

//********************************************************************************
// MAIN CODE 
//********************************************************************************

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		rx_detect_valid_reg_0	<= 1'b0;
	end
	else
	begin
		rx_detect_valid_reg_0	<= rx_detect_valid;
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		rx_detect_valid_reg_1	<= 1'b0;
	end
	else
	begin
		rx_detect_valid_reg_1	<= rx_detect_valid_reg_0;
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		txdetectrx_reg_0	<= 1'b0;
	end
	else
	begin
		txdetectrx_reg_0	<= tmp_txdetectrxin;      // txdetectrx; shawn
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		txdetectrx_reg_1	<= 1'b0;
	end
	else
	begin
		txdetectrx_reg_1	<= txdetectrx_reg_0;
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		txdetectrx_reg_2	<= 1'b0;
	end
	else
	begin
		txdetectrx_reg_2	<= txdetectrx_reg_1;
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		txdetectrx_reg_3	<= 1'b0;
	end
	else
	begin
		txdetectrx_reg_3	<= txdetectrx_reg_2;
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		txdetectrx_reg_4	<= 1'b0;
	end
	else
	begin
		txdetectrx_reg_4	<= txdetectrx_reg_3;
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		txdetectrx_reg_5	<= 1'b0;
	end
	else
	begin
		txdetectrx_reg_5	<= txdetectrx_reg_4;
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		txdetectrx_reg_6	<= 1'b0;
	end
	else
	begin
		txdetectrx_reg_6	<= txdetectrx_reg_5;
	end
end

always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		bypass_rx_found		<= 1'b0;
		bypass_rx_detect_valid	<= 1'b0;
	end
	else
	begin
		bypass_rx_found		<= txdetectrx_reg_6;
		bypass_rx_detect_valid	<= txdetectrx_reg_6;
	end
end

	// Synchronize powerstate to rx clk domain
/*
always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		powerstate_0	<= 1'b0;
		powerstate_1	<= 1'b0;
		powerstate_2	<= 1'b0;
		powerstate_3	<= 1'b0;
	end
	else
	begin
		powerstate_0	<= powerstate[0];
		powerstate_1	<= powerstate[1];
		powerstate_2	<= powerstate[2];
		powerstate_3	<= powerstate[3];
	end
end
always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n)
begin
	if (!rx_pipe_reset_n)
	begin
		latched_p0	<= 1'b0;
		latched_p0s	<= 1'b0;
		latched_p1	<= 1'b0;
		latched_p2	<= 1'b0;
	end
	else
	begin
		latched_p0	<= powerstate_0;
		latched_p0s	<= powerstate_1;
		latched_p1	<= powerstate_2;
		latched_p2	<= powerstate_3;
	end
end*/
endmodule

`timescale 1 ns / 1 ps

module arriagx_hssi_pcs_reset (hard_reset, clk_2_b, refclk_b_in, scan_mode, rxpcs_rst, txpcs_rst,
                  rxrst_int, txrst_int);

input   hard_reset;
input   clk_2_b;
input   refclk_b_in;
input   scan_mode;
input   rxpcs_rst;
input   txpcs_rst;

output  rxrst_int;
output  txrst_int;

reg 	txrst_sync1, txrst_sync2;
reg     rxrst_sync1, rxrst_sync2;
wire    txrst_int, rxrst_int;


always @(posedge hard_reset or posedge clk_2_b)
begin
	if (hard_reset)
		begin
		 rxrst_sync2	<= 1'b1;
		 rxrst_sync1 	<= 1'b1;
		end
	else
		begin
		 rxrst_sync2	<= #1 rxrst_sync1;
		 rxrst_sync1	<= rxpcs_rst;
		end
end

always @(posedge hard_reset or posedge refclk_b_in)
begin
	if (hard_reset)
		begin
		 txrst_sync2	<= 1'b1;
		 txrst_sync1 	<= 1'b1;
		end
	else
		begin
		 txrst_sync2	<= #1 txrst_sync1;
		 txrst_sync1	<= txpcs_rst;
		end
end

// 06-14-02 BT Changed SCAN_SHIFT signal to SCAN_MODE
//assign rxrst_int = !SCAN_SHIFT & rxrst_sync2;
//assign txrst_int = !SCAN_SHIFT & txrst_sync2;
assign rxrst_int = !scan_mode & rxrst_sync2;
assign txrst_int = !scan_mode & txrst_sync2;

endmodule

`timescale 1 ps / 1 ps

module arriagx_hssi_tx_txclk_ctl (txrst, pld_tx_clk, refclk_pma, txpma_local_clk, 
                  tx_div2_sync_in_ch0, tx_div2_sync_in_q0_ch0,
                  rindv_tx, rtxwrclksel, rtxrdclksel, rdwidth_tx,            
                  rfreerun_tx, rphfifo_master_sel_tx, scan_mode,             
                  tx_clk_out, tx_div2_sync_out, wr_clk_pos,            
                  fifo_rd_clk, refclk_b
                 );

input        txrst;                  // reset for the tx_pcs
input        pld_tx_clk;             // The transmit clock from XGMII.
input        refclk_pma;             // from the root clock tree
input        txpma_local_clk;        // Local channel TX PMA clock.
input        tx_div2_sync_in_ch0;    // from the channel zero tx_div2_sync_out
input        tx_div2_sync_in_q0_ch0; // From channel0 of Master Quad
input	     rindv_tx;               // Selects between indiv chan. mode and bundled mode
input        rtxwrclksel;            // Selects which clock writes into FIFO
input        rtxrdclksel;            // Selects which clock reads from FIFO and also clocks reest of TX logic
input  	     rdwidth_tx;             // divide by 1 or 2 before feeding to FIFO read clock
input        rfreerun_tx;            // Select whether divider is permamently enabled (free -running) or
			             // divider should be enabled / reset by TX PCS reset  
input        rphfifo_master_sel_tx;  // TX Phase comp. FIFO tx_div2_sync selection CRAM
input        scan_mode;              // Scan mode enable signal for selecting scan_clk from refclk_pma

output       tx_clk_out;             // Drives to the PLD clock tree -- unconnected
output       tx_div2_sync_out;       // Synchronizes the divided by two clock
output       wr_clk_pos;             // Drives tx phase comp fifo write side
output       fifo_rd_clk;            // Drives tx phase comp fifo read side
output       refclk_b;               // Drives the tx channel clock

wire tx_rst_n,tx_div2_sync;
reg fifo_rd_clk_by2;
wire rd_clk_before_div;  //Same as refclk_b. Different name for clarity.

// initial begin ------
initial begin
    fifo_rd_clk_by2 = 1'b0;
end             
// initial end   ------

// Select between the local synchronization signal or the global synchronization signal (either from Channel0 or 
// Channel0 of Master Quad
//assign tx_div2_sync = rindv_tx ? tx_div2_sync_out : tx_div2_sync_in;
assign tx_div2_sync = (rphfifo_master_sel_tx == 1'b0) ? tx_div2_sync_in_q0_ch0 :
                      (rindv_tx == 1'b0) ? tx_div2_sync_in_ch0 : tx_div2_sync_out;

assign tx_div2_sync_out = ~fifo_rd_clk_by2;

// Divide-by-2 FF
always @(negedge tx_rst_n or posedge rd_clk_before_div)
begin
	if (~tx_rst_n)
		fifo_rd_clk_by2 <= 1'b0;
	else if (rd_clk_before_div)
		fifo_rd_clk_by2 <= tx_div2_sync; // local divided clock
end

// Reset for Divide-by-2 FF
assign tx_rst_n = (rfreerun_tx) ? 1'b1 : ~txrst;

// Full speed clock for TX PCS
assign refclk_b = rd_clk_before_div;	// Internal

// Output clock for PLD
assign tx_clk_out = fifo_rd_clk;	// to PLD

// TX FIFO read clock: could be fast or divided by 2
assign fifo_rd_clk = ((rdwidth_tx == 1'b0) || scan_mode) ? rd_clk_before_div : fifo_rd_clk_by2;
assign rd_clk_before_div = (rtxrdclksel || scan_mode) ? refclk_pma : txpma_local_clk; //Same as refclk_b. Different name for clarity.

// TX FIFO write clock: used internal clock when in BIST 
assign wr_clk_pos = (rtxwrclksel || scan_mode) ? fifo_rd_clk : pld_tx_clk;


endmodule

`timescale 1ps / 1ps

module arriagx_hssi_tx_ram8x44_syn (
    data_in,
    clk,
    fifo_wr,
    rst_l, 
    fifo_re,
    data_out
    );

input 		clk;
input 		rst_l;
input 	[7:0]	fifo_wr;
input 	[7:0] 	fifo_re;
input 	[43:0] 	data_in;
output 	[43:0] 	data_out;

parameter read_access_time = 0;
parameter write_access_time = 0;
parameter ram_width = 44;

reg [ram_width-1:0] data_out_i;
reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, 
                    ram_array_d_3, ram_array_d_4, ram_array_d_5, 
                    ram_array_d_6, ram_array_d_7, 
 		    ram_array_q_0, ram_array_q_1, ram_array_q_2, 
                    ram_array_q_3, ram_array_q_4, ram_array_q_5, 
                    ram_array_q_6, ram_array_q_7;

wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, data_reg_3,
		     data_reg_4, data_reg_5, data_reg_6, data_reg_7;

wire 		we, re_l;

assign we = 1'b1;
assign re_l = 1'b0;

/* Modelling the read port */
/* Assuming address trigerred operation only */
assign
    data_reg_0 = ( fifo_wr[0] == 1'b1 ) ? data_in : ram_array_q_0,
    data_reg_1 = ( fifo_wr[1] == 1'b1 ) ? data_in : ram_array_q_1,
    data_reg_2 = ( fifo_wr[2] == 1'b1 ) ? data_in : ram_array_q_2,
    data_reg_3 = ( fifo_wr[3] == 1'b1 ) ? data_in : ram_array_q_3,
    data_reg_4 = ( fifo_wr[4] == 1'b1 ) ? data_in : ram_array_q_4,
    data_reg_5 = ( fifo_wr[5] == 1'b1 ) ? data_in : ram_array_q_5,
    data_reg_6 = ( fifo_wr[6] == 1'b1 ) ? data_in : ram_array_q_6,
    data_reg_7 = ( fifo_wr[7] == 1'b1 ) ? data_in : ram_array_q_7;

assign  data_out = re_l ? 44'b0 : data_out_i;

always @(
    ram_array_q_0	or 
    ram_array_q_1	or 
    ram_array_q_2	or 
    ram_array_q_3	or 
    ram_array_q_4       or
    ram_array_q_5       or
    ram_array_q_6       or
    ram_array_q_7       or 
    fifo_re		
    )
begin
    case ( fifo_re )  // synopsys parallel_case full_case
    8'b00000001 : data_out_i = ram_array_q_0;
    8'b00000010 : data_out_i = ram_array_q_1;
    8'b00000100 : data_out_i = ram_array_q_2;
    8'b00001000 : data_out_i = ram_array_q_3;
    8'b00010000 : data_out_i = ram_array_q_4;
    8'b00100000 : data_out_i = ram_array_q_5;
    8'b01000000 : data_out_i = ram_array_q_6;
    8'b10000000 : data_out_i = ram_array_q_7;
    default     : data_out_i = ram_array_q_0;
    endcase
end


/* Modelling the write port */
always @(posedge clk or negedge rst_l) 
begin
    if(~rst_l) begin
	ram_array_q_0 <= #write_access_time 0;
	ram_array_q_1 <= #write_access_time 0;
	ram_array_q_2 <= #write_access_time 0; 
	ram_array_q_3 <= #write_access_time 0; 
        ram_array_q_4 <= #write_access_time 0;
        ram_array_q_5 <= #write_access_time 0;
        ram_array_q_6 <= #write_access_time 0;
        ram_array_q_7 <= #write_access_time 0; 
    end
    else begin
	ram_array_q_0 <= #write_access_time ram_array_d_0;
	ram_array_q_1 <= #write_access_time ram_array_d_1;
	ram_array_q_2 <= #write_access_time ram_array_d_2;
	ram_array_q_3 <= #write_access_time ram_array_d_3;
        ram_array_q_4 <= #write_access_time ram_array_d_4;
        ram_array_q_5 <= #write_access_time ram_array_d_5;
        ram_array_q_6 <= #write_access_time ram_array_d_6;
        ram_array_q_7 <= #write_access_time ram_array_d_7;
    end
end
         
always @( 
    we 			or 
    data_reg_0 		or 
    data_reg_1 		or 
    data_reg_2		or 
    data_reg_3		or
    data_reg_4          or
    data_reg_5          or
    data_reg_6          or
    data_reg_7          or
    ram_array_q_0 	or 
    ram_array_q_1	or
    ram_array_q_2	or
    ram_array_q_3	or
    ram_array_q_4       or
    ram_array_q_5       or
    ram_array_q_6       or
    ram_array_q_7	
       )
begin
    if(we) begin
	ram_array_d_0 <=  data_reg_0;
	ram_array_d_1 <=  data_reg_1;
	ram_array_d_2 <=  data_reg_2;
	ram_array_d_3 <=  data_reg_3;
        ram_array_d_4 <=  data_reg_4;
        ram_array_d_5 <=  data_reg_5;
        ram_array_d_6 <=  data_reg_6;
        ram_array_d_7 <=  data_reg_7; 
    end
    else begin
	ram_array_d_0 <=  ram_array_q_0;
	ram_array_d_1 <=  ram_array_q_1;
	ram_array_d_2 <=  ram_array_q_2;
	ram_array_d_3 <=  ram_array_q_3;
        ram_array_d_4 <=  ram_array_q_4;
        ram_array_d_5 <=  ram_array_q_5;
        ram_array_d_6 <=  ram_array_q_6;
        ram_array_d_7 <=  ram_array_q_7;
    end
end

endmodule

`timescale 1 ps / 1 ps

module arriagx_hssi_tx_ph_fifo (
// inputs
	rst_wclk,
	rst_rclk,
	wr_clk,
	rd_clk,
	bypass_en,
	//en,
	lowlatency_en,
	we,
	re,
	din,
// outputs
	data_out,
	ph_fifo_full,
	ph_fifo_empty,
	wptr_bin,
	rptr_bin
);

// =======
// inputs
// =======
input         rst_wclk;		// wr clk rst
input         rst_rclk;		// rd clk rst
input         wr_clk;		// Write Clock
input         rd_clk;		// Read Clock
input         bypass_en;	// FIFO bypass enable - only for Altera internal debug
//input         en;		// Disable FIFO, reset wptr and rptr 
				// only for Altera internal debug
input         lowlatency_en;	// Enable low latency option 
input         we;		// PLD dynamic write pointer enable  
input         re;		// PLD dynamic read pointer enable  
input  [43:0] din;		// 10-bit code-group bus from deskew module.

// =======
// outputs
// =======
output        ph_fifo_full;	// Indicates overflow (rd_clk)
output        ph_fifo_empty;	// FIFO empty (rd_clk)
output [43:0] data_out;		// output data (rd_clk synchronous if not FIFO bypass)
output  [2:0] wptr_bin;		// wptr test bus
output  [2:0] rptr_bin;		// rptr test bus

// ===================
// signal declaration
// ===================
reg  [ 7:0] wptr, rptr;
reg  [ 7:0] wptr0;
reg  [ 7:0] wptr1;
reg  [ 3:0] rptr_gray;
reg  [ 2:0] rptr0;
reg  [ 2:0] rptr1;
reg  [ 7:0] rptr1_onehot;
reg  [ 2:0] wptr_bin;		// wptr test bus
reg  [ 2:0] rptr_bin;		// rptr test bus
reg         first_rd;		// first read after reset
reg  [43:0] ram_data_out;
wire [43:0] ram_data_out_pre;

reg  ph_fifo_full, ph_fifo_empty;

// Invert rst for new FIFO     
wire rst_n;

// =============
// functionality
// =============
assign rst_n = ~rst_wclk;

assign data_out[43:0] = (bypass_en)? din : ram_data_out;

always @ (posedge rst_wclk or posedge wr_clk)
begin
   if (rst_wclk == 1'b1)
   begin
      wptr  <= 8'h01;
      wptr0 <= 8'h01;
      wptr1 <= 8'h01;
      rptr0 <= 3'h0;
      rptr1 <= 3'h0;
      ph_fifo_full <= 1'b0;
      ph_fifo_empty <= 1'b0;
   end
   else
   begin

      wptr0 <= wptr;
      wptr1 <= wptr0;

      rptr0 <= rptr_gray;
      rptr1 <= rptr0;

      // wptr operation
      if (we == 1'b1)
         wptr <= {wptr[6:0],wptr[7]};

      // full condition
      if ({wptr1[6:0],wptr1[7]} == rptr1_onehot)
         ph_fifo_full <= 1'b1;
      else if (ph_fifo_full == 1'b1 & ({wptr1[6:0],wptr1[7]} != rptr1_onehot) & (wptr1 != rptr1_onehot))
         ph_fifo_full <= 1'b0;

      // empty condition
      if ({rptr1_onehot[6:0],rptr1_onehot[7]} == wptr1)
         ph_fifo_empty <= 1'b1;
      else if (ph_fifo_empty == 1'b1 & ({rptr1_onehot[6:0],rptr1_onehot[7]} != wptr1) & (wptr1 != rptr1_onehot))
         ph_fifo_empty <= 1'b0;
   end
end


always @ (posedge rst_rclk or posedge rd_clk)
begin
   if (rst_rclk == 1'b1)
   begin
      first_rd <= 1'b1;
      rptr  <= 8'h20;
   end
   else
   begin

      if (first_rd == 1'b1 && re == 1'b1)
          first_rd <= 1'b0;

      // read pointer operation
      if (re == 1'b1)
         // low latency option, advance 2 on the first read 
         if (first_rd == 1'b1 && lowlatency_en == 1'b1)
            rptr <= {rptr[5:0],rptr[7:6]};	
         else
            rptr <= {rptr[6:0],rptr[7]};
   end

end

// Instantiate FIFO CORE Module. Fifo 8 words deep, 44 bits wide
arriagx_hssi_tx_ram8x44_syn   ram8x44_syn_1 (
                                  .rst_l (rst_n),
                                  .clk (wr_clk),
                                  .fifo_wr (wptr),
                                  .data_in (din),
                                  .fifo_re (rptr),
                                  .data_out (ram_data_out_pre)
		        	);

always @ (posedge rst_rclk or posedge rd_clk)
begin
   if (rst_rclk)
   begin
	ram_data_out <= 44'h00000000000;
   end
   else  
        ram_data_out <= ram_data_out_pre;
end

always@(wptr)
begin
  case(wptr)
  8'h01: wptr_bin = 3'h0;
  8'h02: wptr_bin = 3'h1;
  8'h04: wptr_bin = 3'h2;
  8'h08: wptr_bin = 3'h3;
  8'h10: wptr_bin = 3'h4;
  8'h20: wptr_bin = 3'h5;
  8'h40: wptr_bin = 3'h6;
  8'h80: wptr_bin = 3'h7;
  default: wptr_bin = 3'h7;
  endcase
end

always@(rptr)
begin
  case(rptr)
  8'h01: rptr_bin = 3'h0;
  8'h02: rptr_bin = 3'h1;
  8'h04: rptr_bin = 3'h2;
  8'h08: rptr_bin = 3'h3;
  8'h10: rptr_bin = 3'h4;
  8'h20: rptr_bin = 3'h5;
  8'h40: rptr_bin = 3'h6;
  8'h80: rptr_bin = 3'h7;
  default: rptr_bin = 3'h7;
  endcase
end

always@(rptr)
begin
  case(rptr)
  8'h01: rptr_gray = 3'h0;
  8'h02: rptr_gray = 3'h1;
  8'h04: rptr_gray = 3'h3;
  8'h08: rptr_gray = 3'h2;
  8'h10: rptr_gray = 3'h6;
  8'h20: rptr_gray = 3'h7;
  8'h40: rptr_gray = 3'h5;
  8'h80: rptr_gray = 3'h4;
  default: rptr_gray = 3'h0;
  endcase
end

always@(rptr1)
begin
  case(rptr1)
  3'h0: rptr1_onehot = 8'h01;
  3'h1: rptr1_onehot = 8'h02;
  3'h3: rptr1_onehot = 8'h04;
  3'h2: rptr1_onehot = 8'h08;
  3'h6: rptr1_onehot = 8'h10;
  3'h7: rptr1_onehot = 8'h20;
  3'h5: rptr1_onehot = 8'h40;
  3'h4: rptr1_onehot = 8'h80;
  default: rptr1_onehot = 8'h01;
  endcase
end

endmodule
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 120 mux21 250 arriagx_hssi_tx_ph_fifo 1 
`timescale 1 ps / 1 ps
module  arriagx_hssi_tx_ctrl
	( 
	d21_5_eq_n,
	d2_2_eq_n,
	dwidth,
	fifo_rd_clk,
	fifo_select_in_ch0,
	fifo_select_in_q0_ch0,
	fifo_select_out,
	fifo_wr_clk,
	indv,
	k_det,
	p_rlpbk,
	ph_fifo_empty,
	ph_fifo_full,
	pipe_electric_idle,
	pld_rd_dis,
	pld_we,
	rd_enable2,
	rd_enable_ch0,
	rd_enable_out,
	rd_enable_q0_ch0,
	rd_enable_sync,
	redund_ctl,
	refclk_b_in,
	rforce_disp,
	rforce_echar,
	rforce_kchar,
	rphfifo_master_sel_tx,
	rptr_bin,
	rtx_pipe_enable,
	rtxfifo_lowlatency_en,
	rtxfifo_urst_en,
	rtxphfifopldctl_en,
	rxd_lpbk,
	scan_mode,
	selftest_en,
	soft_reset,
	soft_reset_wclk1,
	tx_control_sg,
	tx_ctl_tc,
	tx_data_9_tc,
	tx_data_sg,
	tx_data_tc,
	txd,
	txd_extend,
	txd_extend_tc,
	txd_redun,
	txfifo_dis,
	txfifo_urst,
	wptr_bin,
	wr_enable2,
	wr_enable_ch0,
	wr_enable_out,
	wr_enable_q0_ch0) /* synthesis synthesis_clearbox=1 */;
	output   [1:0]  d21_5_eq_n;
	output   [1:0]  d2_2_eq_n;
	input   dwidth;
	input   fifo_rd_clk;
	input   fifo_select_in_ch0;
	input   fifo_select_in_q0_ch0;
	output   fifo_select_out;
	input   fifo_wr_clk;
	input   indv;
	output   [1:0]  k_det;
	input   p_rlpbk;
	output   ph_fifo_empty;
	output   ph_fifo_full;
	output   pipe_electric_idle;
	input   pld_rd_dis;
	input   pld_we;
	output   rd_enable2;
	input   rd_enable_ch0;
	output   rd_enable_out;
	input   rd_enable_q0_ch0;
	output   rd_enable_sync;
	input   [3:0]  redund_ctl;
	input   refclk_b_in;
	input   rforce_disp;
	input   rforce_echar;
	input   rforce_kchar;
	input   rphfifo_master_sel_tx;
	output   [2:0]  rptr_bin;
	input   rtx_pipe_enable;
	input   rtxfifo_lowlatency_en;
	input   rtxfifo_urst_en;
	input   rtxphfifopldctl_en;
	input   [39:0]  rxd_lpbk;
	input   scan_mode;
	input   selftest_en;
	input   soft_reset;
	output   soft_reset_wclk1;
	input   [3:0]  tx_control_sg;
	output   [1:0]  tx_ctl_tc;
	output   [1:0]  tx_data_9_tc;
	input   [31:0]  tx_data_sg;
	output   [15:0]  tx_data_tc;
	input   [39:0]  txd;
	input   [3:0]  txd_extend;
	output   [1:0]  txd_extend_tc;
	input   [39:0]  txd_redun;
	input   txfifo_dis;
	input   txfifo_urst;
	output   [2:0]  wptr_bin;
	output   wr_enable2;
	input   wr_enable_ch0;
	output   wr_enable_out;
	input   wr_enable_q0_ch0;

	reg	nl000i43;
	reg	nl000i44;
	reg	nl001l45;
	reg	nl001l46;
	reg	nl00ll41;
	reg	nl00ll42;
	reg	nl00Oi39;
	reg	nl00Oi40;
	reg	nl00Ol37;
	reg	nl00Ol38;
	reg	nl0i0i31;
	reg	nl0i0i32;
	reg	nl0i0O29;
	reg	nl0i0O30;
	reg	nl0i1i35;
	reg	nl0i1i36;
	reg	nl0i1l33;
	reg	nl0i1l34;
	reg	nl0iil27;
	reg	nl0iil28;
	reg	nl0ili25;
	reg	nl0ili26;
	reg	nl0ilO23;
	reg	nl0ilO24;
	reg	nl0iOl21;
	reg	nl0iOl22;
	reg	nl0l0i17;
	reg	nl0l0i18;
	reg	nl0l1i19;
	reg	nl0l1i20;
	reg	nl0llO15;
	reg	nl0llO16;
	reg	nl0lOi13;
	reg	nl0lOi14;
	reg	nl0lOO11;
	reg	nl0lOO12;
	reg	nl0O0O5;
	reg	nl0O0O6;
	reg	nl0O1i10;
	reg	nl0O1i9;
	reg	nl0O1O7;
	reg	nl0O1O8;
	reg	nl0OiO3;
	reg	nl0OiO4;
	reg	nl0OlO1;
	reg	nl0OlO2;
	reg	n000i;
	reg	n001i;
	reg	n001l;
	reg	n010l;
	reg	n01iO;
	reg	n01li;
	reg	n01ll;
	reg	n01lO;
	reg	n01Oi;
	reg	n01Ol;
	reg	n01OO;
	wire	wire_n001O_CLRN;
	reg	n010i;
	reg	n011i;
	reg	n011l;
	reg	n011O;
	reg	n01ii;
	reg	n100i;
	reg	n100l;
	reg	n100O;
	reg	n10ii;
	reg	n10Oi;
	reg	n10Ol;
	reg	n10OO;
	reg	n1i1i;
	reg	n1lOi;
	reg	n1lOl;
	reg	n1lOO;
	reg	n1O0i;
	reg	n1O0l;
	reg	n1O0O;
	reg	n1O1i;
	reg	n1O1l;
	reg	n1O1O;
	reg	n1Oii;
	reg	n1Oil;
	reg	n1OiO;
	reg	n1Oli;
	reg	n1Oll;
	reg	n1OlO;
	reg	n1OOi;
	reg	n1OOl;
	reg	n1OOO;
	reg	n1i0i;
	reg	n1i0O;
	reg	n1i1l;
	reg	n1i1O;
	wire	wire_n1i0l_PRN;
	reg	n1iii;
	reg	n1iil;
	reg	n1iiO;
	reg	n1ili;
	reg	n1ill;
	reg	n1ilO;
	reg	n1iOi;
	reg	n1iOl;
	reg	n1iOO;
	reg	n1l0i;
	reg	n1l0l;
	reg	n1l0O;
	reg	n1l1i;
	reg	n1l1l;
	reg	n1l1O;
	reg	n1lii;
	reg	n1lil;
	reg	n1liO;
	reg	n1lli;
	reg	n1llO;
	wire	wire_n1lll_CLRN;
	reg	nl00i;
	reg	nl0ii;
	reg	nl00O_clk_prev;
	wire	wire_nl00O_CLRN;
	reg	nl01O;
	reg	nl1ll;
	reg	nl01l_clk_prev;
	wire	wire_nl01l_CLRN;
	wire	wire_nl01l_PRN;
	reg	n000l;
	reg	nl1ii;
	reg	nl1il;
	reg	nl1li;
	reg	nl1iO_clk_prev;
	wire	wire_nl1iO_PRN;
	wire	wire_n000O_dataout;
	wire	wire_n00i_dataout;
	wire	wire_n00ii_dataout;
	wire	wire_n00il_dataout;
	wire	wire_n00iO_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00ll_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n00Ol_dataout;
	wire	wire_n00OO_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01il_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0i0i_dataout;
	wire	wire_n0i0l_dataout;
	wire	wire_n0i0O_dataout;
	wire	wire_n0i1i_dataout;
	wire	wire_n0i1l_dataout;
	wire	wire_n0i1O_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0iii_dataout;
	wire	wire_n0iil_dataout;
	wire	wire_n0iiO_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0ili_dataout;
	wire	wire_n0ill_dataout;
	wire	wire_n0ilO_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0iOi_dataout;
	wire	wire_n0iOl_dataout;
	wire	wire_n0iOO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0l0i_dataout;
	wire	wire_n0l0l_dataout;
	wire	wire_n0l0O_dataout;
	wire	wire_n0l1i_dataout;
	wire	wire_n0l1l_dataout;
	wire	wire_n0l1O_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0lii_dataout;
	wire	wire_n0lil_dataout;
	wire	wire_n0liO_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lli_dataout;
	wire	wire_n0lll_dataout;
	wire	wire_n0llO_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0lOi_dataout;
	wire	wire_n0lOl_dataout;
	wire	wire_n0lOO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0O0i_dataout;
	wire	wire_n0O1i_dataout;
	wire	wire_n0O1l_dataout;
	wire	wire_n0O1O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0Oli_dataout;
	wire	wire_n0Oll_dataout;
	wire	wire_n0OlO_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n0OOi_dataout;
	wire	wire_n0OOl_dataout;
	wire	wire_n0OOO_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10il_dataout;
	wire	wire_n10iO_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10li_dataout;
	wire	wire_n10ll_dataout;
	wire	wire_n10lO_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_ni_dataout;
	wire	wire_ni00i_dataout;
	wire	wire_ni00l_dataout;
	wire	wire_ni00O_dataout;
	wire	wire_ni01i_dataout;
	wire	wire_ni01l_dataout;
	wire	wire_ni01O_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0ii_dataout;
	wire	wire_ni0il_dataout;
	wire	wire_ni0iO_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0li_dataout;
	wire	wire_ni0ll_dataout;
	wire	wire_ni0lO_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni0Oi_dataout;
	wire	wire_ni0Ol_dataout;
	wire	wire_ni0OO_dataout;
	wire	wire_ni10i_dataout;
	wire	wire_ni10l_dataout;
	wire	wire_ni10O_dataout;
	wire	wire_ni11i_dataout;
	wire	wire_ni11l_dataout;
	wire	wire_ni11O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1ii_dataout;
	wire	wire_ni1il_dataout;
	wire	wire_ni1iO_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1li_dataout;
	wire	wire_ni1ll_dataout;
	wire	wire_ni1lO_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_ni1Oi_dataout;
	wire	wire_ni1Ol_dataout;
	wire	wire_ni1OO_dataout;
	wire	wire_nii_dataout;
	wire	wire_nii0i_dataout;
	wire	wire_nii0l_dataout;
	wire	wire_nii0O_dataout;
	wire	wire_nii1i_dataout;
	wire	wire_nii1l_dataout;
	wire	wire_nii1O_dataout;
	wire	wire_niii_dataout;
	wire	wire_niiii_dataout;
	wire	wire_niiil_dataout;
	wire	wire_niiiO_dataout;
	wire	wire_niil_dataout;
	wire	wire_niili_dataout;
	wire	wire_niill_dataout;
	wire	wire_niilO_dataout;
	wire	wire_niiO_dataout;
	wire	wire_niiOi_dataout;
	wire	wire_niiOl_dataout;
	wire	wire_niiOO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nil1i_dataout;
	wire	wire_nil1l_dataout;
	wire	wire_nil1O_dataout;
	wire	wire_nili_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niO0i_dataout;
	wire	wire_niO0l_dataout;
	wire	wire_niO0O_dataout;
	wire	wire_niO1l_dataout;
	wire	wire_niO1O_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOii_dataout;
	wire	wire_niOil_dataout;
	wire	wire_niOiO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOli_dataout;
	wire	wire_niOll_dataout;
	wire	wire_niOlO_dataout;
	wire	wire_niOO_dataout;
	wire	wire_niOOi_dataout;
	wire	wire_niOOl_dataout;
	wire	wire_niOOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl00l_dataout;
	wire	wire_nl01i_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0ll_dataout;
	wire	wire_nl0lO_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl0Oi_dataout;
	wire	wire_nl0Ol_dataout;
	wire	wire_nl0OO_dataout;
	wire	wire_nl10i_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl10O_dataout;
	wire	wire_nl11i_dataout;
	wire	wire_nl11l_dataout;
	wire	wire_nl11O_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1lO_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nl1Oi_dataout;
	wire	wire_nl1Ol_dataout;
	wire	wire_nli_dataout;
	wire	wire_nli0i_dataout;
	wire	wire_nli0l_dataout;
	wire	wire_nli0O_dataout;
	wire	wire_nli1i_dataout;
	wire	wire_nli1l_dataout;
	wire	wire_nli1O_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nliii_dataout;
	wire	wire_nliil_dataout;
	wire	wire_nliiO_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nlili_dataout;
	wire	wire_nlill_dataout;
	wire	wire_nlilO_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nliOi_dataout;
	wire	wire_nliOl_dataout;
	wire	wire_nliOO_dataout;
	wire	wire_nll0i_dataout;
	wire	wire_nll0l_dataout;
	wire	wire_nll0O_dataout;
	wire	wire_nll1i_dataout;
	wire	wire_nll1l_dataout;
	wire	wire_nll1O_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nllii_dataout;
	wire	wire_nllil_dataout;
	wire	wire_nlliO_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllli_dataout;
	wire	wire_nllll_dataout;
	wire	wire_nlllO_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nllOi_dataout;
	wire	wire_nllOl_dataout;
	wire	wire_nllOO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlO0i_dataout;
	wire	wire_nlO0l_dataout;
	wire	wire_nlO0O_dataout;
	wire	wire_nlO1i_dataout;
	wire	wire_nlO1l_dataout;
	wire	wire_nlO1O_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOli_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOO_dataout;
	wire	wire_nO_dataout;
	wire  [43:0]   wire_nli11i_data_out;
	wire  wire_nli11i_ph_fifo_empty;
	wire  wire_nli11i_ph_fifo_full;
	wire  [2:0]   wire_nli11i_rptr_bin;
	wire  [2:0]   wire_nli11i_wptr_bin;
	wire  nl000O;
	wire  nl00ii;
	wire  nl00il;
	wire  nl00iO;
	wire  nl00li;
	wire  nl00lO;
	wire  nl0l0O;
	wire  nl0l1O;
	wire  nl0lii;
	wire  nl0lil;
	wire  nl0liO;
	wire  nl0lli;
	wire  nl0lll;
	wire  nl0O0i;
	wire  nl0O0l;
	wire  nl0O1l;
	wire  nl0Oil;
	wire  nl0Oll;

	initial
		nl000i43 = 0;
	always @ ( posedge refclk_b_in)
		  nl000i43 <= nl000i44;
	event nl000i43_event;
	initial
		#1 ->nl000i43_event;
	always @(nl000i43_event)
		nl000i43 <= {1{1'b1}};
	initial
		nl000i44 = 0;
	always @ ( posedge refclk_b_in)
		  nl000i44 <= nl000i43;
	initial
		nl001l45 = 0;
	always @ ( posedge refclk_b_in)
		  nl001l45 <= nl001l46;
	event nl001l45_event;
	initial
		#1 ->nl001l45_event;
	always @(nl001l45_event)
		nl001l45 <= {1{1'b1}};
	initial
		nl001l46 = 0;
	always @ ( posedge refclk_b_in)
		  nl001l46 <= nl001l45;
	initial
		nl00ll41 = 0;
	always @ ( posedge refclk_b_in)
		  nl00ll41 <= nl00ll42;
	event nl00ll41_event;
	initial
		#1 ->nl00ll41_event;
	always @(nl00ll41_event)
		nl00ll41 <= {1{1'b1}};
	initial
		nl00ll42 = 0;
	always @ ( posedge refclk_b_in)
		  nl00ll42 <= nl00ll41;
	initial
		nl00Oi39 = 0;
	always @ ( posedge refclk_b_in)
		  nl00Oi39 <= nl00Oi40;
	event nl00Oi39_event;
	initial
		#1 ->nl00Oi39_event;
	always @(nl00Oi39_event)
		nl00Oi39 <= {1{1'b1}};
	initial
		nl00Oi40 = 0;
	always @ ( posedge refclk_b_in)
		  nl00Oi40 <= nl00Oi39;
	initial
		nl00Ol37 = 0;
	always @ ( posedge refclk_b_in)
		  nl00Ol37 <= nl00Ol38;
	event nl00Ol37_event;
	initial
		#1 ->nl00Ol37_event;
	always @(nl00Ol37_event)
		nl00Ol37 <= {1{1'b1}};
	initial
		nl00Ol38 = 0;
	always @ ( posedge refclk_b_in)
		  nl00Ol38 <= nl00Ol37;
	initial
		nl0i0i31 = 0;
	always @ ( posedge refclk_b_in)
		  nl0i0i31 <= nl0i0i32;
	event nl0i0i31_event;
	initial
		#1 ->nl0i0i31_event;
	always @(nl0i0i31_event)
		nl0i0i31 <= {1{1'b1}};
	initial
		nl0i0i32 = 0;
	always @ ( posedge refclk_b_in)
		  nl0i0i32 <= nl0i0i31;
	initial
		nl0i0O29 = 0;
	always @ ( posedge refclk_b_in)
		  nl0i0O29 <= nl0i0O30;
	event nl0i0O29_event;
	initial
		#1 ->nl0i0O29_event;
	always @(nl0i0O29_event)
		nl0i0O29 <= {1{1'b1}};
	initial
		nl0i0O30 = 0;
	always @ ( posedge refclk_b_in)
		  nl0i0O30 <= nl0i0O29;
	initial
		nl0i1i35 = 0;
	always @ ( posedge refclk_b_in)
		  nl0i1i35 <= nl0i1i36;
	event nl0i1i35_event;
	initial
		#1 ->nl0i1i35_event;
	always @(nl0i1i35_event)
		nl0i1i35 <= {1{1'b1}};
	initial
		nl0i1i36 = 0;
	always @ ( posedge refclk_b_in)
		  nl0i1i36 <= nl0i1i35;
	initial
		nl0i1l33 = 0;
	always @ ( posedge refclk_b_in)
		  nl0i1l33 <= nl0i1l34;
	event nl0i1l33_event;
	initial
		#1 ->nl0i1l33_event;
	always @(nl0i1l33_event)
		nl0i1l33 <= {1{1'b1}};
	initial
		nl0i1l34 = 0;
	always @ ( posedge refclk_b_in)
		  nl0i1l34 <= nl0i1l33;
	initial
		nl0iil27 = 0;
	always @ ( posedge refclk_b_in)
		  nl0iil27 <= nl0iil28;
	event nl0iil27_event;
	initial
		#1 ->nl0iil27_event;
	always @(nl0iil27_event)
		nl0iil27 <= {1{1'b1}};
	initial
		nl0iil28 = 0;
	always @ ( posedge refclk_b_in)
		  nl0iil28 <= nl0iil27;
	initial
		nl0ili25 = 0;
	always @ ( posedge refclk_b_in)
		  nl0ili25 <= nl0ili26;
	event nl0ili25_event;
	initial
		#1 ->nl0ili25_event;
	always @(nl0ili25_event)
		nl0ili25 <= {1{1'b1}};
	initial
		nl0ili26 = 0;
	always @ ( posedge refclk_b_in)
		  nl0ili26 <= nl0ili25;
	initial
		nl0ilO23 = 0;
	always @ ( posedge refclk_b_in)
		  nl0ilO23 <= nl0ilO24;
	event nl0ilO23_event;
	initial
		#1 ->nl0ilO23_event;
	always @(nl0ilO23_event)
		nl0ilO23 <= {1{1'b1}};
	initial
		nl0ilO24 = 0;
	always @ ( posedge refclk_b_in)
		  nl0ilO24 <= nl0ilO23;
	initial
		nl0iOl21 = 0;
	always @ ( posedge refclk_b_in)
		  nl0iOl21 <= nl0iOl22;
	event nl0iOl21_event;
	initial
		#1 ->nl0iOl21_event;
	always @(nl0iOl21_event)
		nl0iOl21 <= {1{1'b1}};
	initial
		nl0iOl22 = 0;
	always @ ( posedge refclk_b_in)
		  nl0iOl22 <= nl0iOl21;
	initial
		nl0l0i17 = 0;
	always @ ( posedge refclk_b_in)
		  nl0l0i17 <= nl0l0i18;
	event nl0l0i17_event;
	initial
		#1 ->nl0l0i17_event;
	always @(nl0l0i17_event)
		nl0l0i17 <= {1{1'b1}};
	initial
		nl0l0i18 = 0;
	always @ ( posedge refclk_b_in)
		  nl0l0i18 <= nl0l0i17;
	initial
		nl0l1i19 = 0;
	always @ ( posedge refclk_b_in)
		  nl0l1i19 <= nl0l1i20;
	event nl0l1i19_event;
	initial
		#1 ->nl0l1i19_event;
	always @(nl0l1i19_event)
		nl0l1i19 <= {1{1'b1}};
	initial
		nl0l1i20 = 0;
	always @ ( posedge refclk_b_in)
		  nl0l1i20 <= nl0l1i19;
	initial
		nl0llO15 = 0;
	always @ ( posedge refclk_b_in)
		  nl0llO15 <= nl0llO16;
	event nl0llO15_event;
	initial
		#1 ->nl0llO15_event;
	always @(nl0llO15_event)
		nl0llO15 <= {1{1'b1}};
	initial
		nl0llO16 = 0;
	always @ ( posedge refclk_b_in)
		  nl0llO16 <= nl0llO15;
	initial
		nl0lOi13 = 0;
	always @ ( posedge refclk_b_in)
		  nl0lOi13 <= nl0lOi14;
	event nl0lOi13_event;
	initial
		#1 ->nl0lOi13_event;
	always @(nl0lOi13_event)
		nl0lOi13 <= {1{1'b1}};
	initial
		nl0lOi14 = 0;
	always @ ( posedge refclk_b_in)
		  nl0lOi14 <= nl0lOi13;
	initial
		nl0lOO11 = 0;
	always @ ( posedge refclk_b_in)
		  nl0lOO11 <= nl0lOO12;
	event nl0lOO11_event;
	initial
		#1 ->nl0lOO11_event;
	always @(nl0lOO11_event)
		nl0lOO11 <= {1{1'b1}};
	initial
		nl0lOO12 = 0;
	always @ ( posedge refclk_b_in)
		  nl0lOO12 <= nl0lOO11;
	initial
		nl0O0O5 = 0;
	always @ ( posedge refclk_b_in)
		  nl0O0O5 <= nl0O0O6;
	event nl0O0O5_event;
	initial
		#1 ->nl0O0O5_event;
	always @(nl0O0O5_event)
		nl0O0O5 <= {1{1'b1}};
	initial
		nl0O0O6 = 0;
	always @ ( posedge refclk_b_in)
		  nl0O0O6 <= nl0O0O5;
	initial
		nl0O1i10 = 0;
	always @ ( posedge refclk_b_in)
		  nl0O1i10 <= nl0O1i9;
	initial
		nl0O1i9 = 0;
	always @ ( posedge refclk_b_in)
		  nl0O1i9 <= nl0O1i10;
	event nl0O1i9_event;
	initial
		#1 ->nl0O1i9_event;
	always @(nl0O1i9_event)
		nl0O1i9 <= {1{1'b1}};
	initial
		nl0O1O7 = 0;
	always @ ( posedge refclk_b_in)
		  nl0O1O7 <= nl0O1O8;
	event nl0O1O7_event;
	initial
		#1 ->nl0O1O7_event;
	always @(nl0O1O7_event)
		nl0O1O7 <= {1{1'b1}};
	initial
		nl0O1O8 = 0;
	always @ ( posedge refclk_b_in)
		  nl0O1O8 <= nl0O1O7;
	initial
		nl0OiO3 = 0;
	always @ ( posedge refclk_b_in)
		  nl0OiO3 <= nl0OiO4;
	event nl0OiO3_event;
	initial
		#1 ->nl0OiO3_event;
	always @(nl0OiO3_event)
		nl0OiO3 <= {1{1'b1}};
	initial
		nl0OiO4 = 0;
	always @ ( posedge refclk_b_in)
		  nl0OiO4 <= nl0OiO3;
	initial
		nl0OlO1 = 0;
	always @ ( posedge refclk_b_in)
		  nl0OlO1 <= nl0OlO2;
	event nl0OlO1_event;
	initial
		#1 ->nl0OlO1_event;
	always @(nl0OlO1_event)
		nl0OlO1 <= {1{1'b1}};
	initial
		nl0OlO2 = 0;
	always @ ( posedge refclk_b_in)
		  nl0OlO2 <= nl0OlO1;
	initial
	begin
		n000i = 0;
		n001i = 0;
		n001l = 0;
		n010l = 0;
		n01iO = 0;
		n01li = 0;
		n01ll = 0;
		n01lO = 0;
		n01Oi = 0;
		n01Ol = 0;
		n01OO = 0;
	end
	always @ ( posedge fifo_rd_clk or  negedge wire_n001O_CLRN)
	begin
		if (wire_n001O_CLRN == 1'b0) 
		begin
			n000i <= 0;
			n001i <= 0;
			n001l <= 0;
			n010l <= 0;
			n01iO <= 0;
			n01li <= 0;
			n01ll <= 0;
			n01lO <= 0;
			n01Oi <= 0;
			n01Ol <= 0;
			n01OO <= 0;
		end
		else 
		begin
			n000i <= pld_rd_dis;
			n001i <= n001l;
			n001l <= n000i;
			n010l <= wire_n000O_dataout;
			n01iO <= n01li;
			n01li <= nl0O1l;
			n01ll <= wire_n00il_dataout;
			n01lO <= wire_n00ll_dataout;
			n01Oi <= n01Ol;
			n01Ol <= nl0O1l;
			n01OO <= ((n001l ^ n001i) ^ (~ (nl00Ol38 ^ nl00Ol37)));
		end
	end
	assign
		wire_n001O_CLRN = ((nl0i1i36 ^ nl0i1i35) & (~ wire_nl01i_dataout));
	initial
	begin
		n010i = 0;
		n011i = 0;
		n011l = 0;
		n011O = 0;
		n01ii = 0;
		n100i = 0;
		n100l = 0;
		n100O = 0;
		n10ii = 0;
		n10Oi = 0;
		n10Ol = 0;
		n10OO = 0;
		n1i1i = 0;
		n1lOi = 0;
		n1lOl = 0;
		n1lOO = 0;
		n1O0i = 0;
		n1O0l = 0;
		n1O0O = 0;
		n1O1i = 0;
		n1O1l = 0;
		n1O1O = 0;
		n1Oii = 0;
		n1Oil = 0;
		n1OiO = 0;
		n1Oli = 0;
		n1Oll = 0;
		n1OlO = 0;
		n1OOi = 0;
		n1OOl = 0;
		n1OOO = 0;
	end
	always @ ( posedge refclk_b_in or  posedge soft_reset)
	begin
		if (soft_reset == 1'b1) 
		begin
			n010i <= 0;
			n011i <= 0;
			n011l <= 0;
			n011O <= 0;
			n01ii <= 0;
			n100i <= 0;
			n100l <= 0;
			n100O <= 0;
			n10ii <= 0;
			n10Oi <= 0;
			n10Ol <= 0;
			n10OO <= 0;
			n1i1i <= 0;
			n1lOi <= 0;
			n1lOl <= 0;
			n1lOO <= 0;
			n1O0i <= 0;
			n1O0l <= 0;
			n1O0O <= 0;
			n1O1i <= 0;
			n1O1l <= 0;
			n1O1O <= 0;
			n1Oii <= 0;
			n1Oil <= 0;
			n1OiO <= 0;
			n1Oli <= 0;
			n1Oll <= 0;
			n1OlO <= 0;
			n1OOi <= 0;
			n1OOl <= 0;
			n1OOO <= 0;
		end
		else 
		begin
			n010i <= wire_nl11l_dataout;
			n011i <= wire_niO0O_dataout;
			n011l <= wire_niOii_dataout;
			n011O <= wire_nl11i_dataout;
			n01ii <= wire_n10il_dataout;
			n100i <= n100l;
			n100l <= nl0O1l;
			n100O <= wire_n10ll_dataout;
			n10ii <= wire_ni1ll_dataout;
			n10Oi <= n10OO;
			n10Ol <= n1i1i;
			n10OO <= nl000O;
			n1i1i <= nl00ii;
			n1lOi <= wire_n01il_dataout;
			n1lOl <= wire_ni1lO_dataout;
			n1lOO <= wire_n0Oli_dataout;
			n1O0i <= wire_n0OOl_dataout;
			n1O0l <= wire_n0OOO_dataout;
			n1O0O <= wire_ni11i_dataout;
			n1O1i <= wire_n0Oll_dataout;
			n1O1l <= wire_n0OlO_dataout;
			n1O1O <= wire_n0OOi_dataout;
			n1Oii <= wire_ni11l_dataout;
			n1Oil <= wire_ni11O_dataout;
			n1OiO <= wire_ni10i_dataout;
			n1Oli <= wire_ni10l_dataout;
			n1Oll <= wire_ni10O_dataout;
			n1OlO <= wire_ni1ii_dataout;
			n1OOi <= wire_ni1il_dataout;
			n1OOl <= wire_ni1iO_dataout;
			n1OOO <= wire_ni1li_dataout;
		end
	end
	initial
	begin
		n1i0i = 0;
		n1i0O = 0;
		n1i1l = 0;
		n1i1O = 0;
	end
	always @ ( posedge refclk_b_in or  negedge wire_n1i0l_PRN)
	begin
		if (wire_n1i0l_PRN == 1'b0) 
		begin
			n1i0i <= 1;
			n1i0O <= 1;
			n1i1l <= 1;
			n1i1O <= 1;
		end
		else 
		begin
			n1i0i <= (~ nl00li);
			n1i0O <= (~ nl00lO);
			n1i1l <= (~ nl00il);
			n1i1O <= (~ nl00iO);
		end
	end
	assign
		wire_n1i0l_PRN = ((nl00ll42 ^ nl00ll41) & (~ soft_reset));
	initial
	begin
		n1iii = 0;
		n1iil = 0;
		n1iiO = 0;
		n1ili = 0;
		n1ill = 0;
		n1ilO = 0;
		n1iOi = 0;
		n1iOl = 0;
		n1iOO = 0;
		n1l0i = 0;
		n1l0l = 0;
		n1l0O = 0;
		n1l1i = 0;
		n1l1l = 0;
		n1l1O = 0;
		n1lii = 0;
		n1lil = 0;
		n1liO = 0;
		n1lli = 0;
		n1llO = 0;
	end
	always @ ( posedge refclk_b_in or  negedge wire_n1lll_CLRN)
	begin
		if (wire_n1lll_CLRN == 1'b0) 
		begin
			n1iii <= 0;
			n1iil <= 0;
			n1iiO <= 0;
			n1ili <= 0;
			n1ill <= 0;
			n1ilO <= 0;
			n1iOi <= 0;
			n1iOl <= 0;
			n1iOO <= 0;
			n1l0i <= 0;
			n1l0l <= 0;
			n1l0O <= 0;
			n1l1i <= 0;
			n1l1l <= 0;
			n1l1O <= 0;
			n1lii <= 0;
			n1lil <= 0;
			n1liO <= 0;
			n1lli <= 0;
			n1llO <= 0;
		end
		else if  (nl0l1O == 1'b1) 
		begin
			n1iii <= wire_nl0li_dataout;
			n1iil <= wire_nl0ll_dataout;
			n1iiO <= wire_nl0lO_dataout;
			n1ili <= wire_nl0Oi_dataout;
			n1ill <= wire_nl0Ol_dataout;
			n1ilO <= wire_nl0OO_dataout;
			n1iOi <= wire_nli1i_dataout;
			n1iOl <= wire_nli1l_dataout;
			n1iOO <= wire_nli1O_dataout;
			n1l0i <= wire_nliii_dataout;
			n1l0l <= wire_nliil_dataout;
			n1l0O <= wire_nliiO_dataout;
			n1l1i <= wire_nli0i_dataout;
			n1l1l <= wire_nli0l_dataout;
			n1l1O <= wire_nli0O_dataout;
			n1lii <= wire_nlili_dataout;
			n1lil <= wire_nlill_dataout;
			n1liO <= wire_nlilO_dataout;
			n1lli <= wire_nliOi_dataout;
			n1llO <= wire_nliOl_dataout;
		end
	end
	assign
		wire_n1lll_CLRN = ((nl00Oi40 ^ nl00Oi39) & (~ soft_reset));
	initial
	begin
		nl00i = 0;
		nl0ii = 0;
	end
	always @ (fifo_wr_clk or nl0O0l or wire_nl00O_CLRN)
	begin
		if (nl0O0l == 1'b1) 
		begin
			nl00i <= 1;
			nl0ii <= 1;
		end
		else if  (wire_nl00O_CLRN == 1'b0) 
		begin
			nl00i <= 0;
			nl0ii <= 0;
		end
		else 
		if (fifo_wr_clk != nl00O_clk_prev && fifo_wr_clk == 1'b1) 
		begin
			nl00i <= nl0ii;
			nl0ii <= nl0O0i;
		end
		nl00O_clk_prev <= fifo_wr_clk;
	end
	assign
		wire_nl00O_CLRN = (nl0O1O8 ^ nl0O1O7);
	initial
	begin
		nl01O = 0;
		nl1ll = 0;
	end
	always @ (fifo_rd_clk or wire_nl01l_PRN or wire_nl01l_CLRN)
	begin
		if (wire_nl01l_PRN == 1'b0) 
		begin
			nl01O <= 1;
			nl1ll <= 1;
		end
		else if  (wire_nl01l_CLRN == 1'b0) 
		begin
			nl01O <= 0;
			nl1ll <= 0;
		end
		else 
		if (fifo_rd_clk != nl01l_clk_prev && fifo_rd_clk == 1'b1) 
		begin
			nl01O <= nl0O0i;
			nl1ll <= nl01O;
		end
		nl01l_clk_prev <= fifo_rd_clk;
	end
	assign
		wire_nl01l_CLRN = (nl0O1i10 ^ nl0O1i9),
		wire_nl01l_PRN = ((nl0lOO12 ^ nl0lOO11) & (~ nl0O0l));
	initial
	begin
		n000l = 0;
		nl1ii = 0;
		nl1il = 0;
		nl1li = 0;
	end
	always @ (fifo_wr_clk or wire_nl1iO_PRN or wire_nl00l_dataout)
	begin
		if (wire_nl1iO_PRN == 1'b0) 
		begin
			n000l <= 1;
			nl1ii <= 1;
			nl1il <= 1;
			nl1li <= 1;
		end
		else if  (wire_nl00l_dataout == 1'b1) 
		begin
			n000l <= 0;
			nl1ii <= 0;
			nl1il <= 0;
			nl1li <= 0;
		end
		else 
		if (fifo_wr_clk != nl1iO_clk_prev && fifo_wr_clk == 1'b1) 
		begin
			n000l <= wire_nl1lO_dataout;
			nl1ii <= wire_nl1Ol_dataout;
			nl1il <= nl1li;
			nl1li <= nl0O1l;
		end
		nl1iO_clk_prev <= fifo_wr_clk;
	end
	assign
		wire_nl1iO_PRN = (nl0llO16 ^ nl0llO15);
	assign		wire_n000O_dataout = (((~ n010l) & ((((~ wire_nli11i_rptr_bin[0]) & (~ wire_nli11i_rptr_bin[1])) & (~ wire_nli11i_rptr_bin[2])) & (nl0i1l34 ^ nl0i1l33))) === 1'b1) ? wire_n00il_dataout : wire_n00ii_dataout;
	assign		wire_n00i_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[8] : wire_niiO_dataout;
	and(wire_n00ii_dataout, n010l, n01iO);
	assign		wire_n00il_dataout = (rphfifo_master_sel_tx === 1'b1) ? wire_n00iO_dataout : rd_enable_q0_ch0;
	assign		wire_n00iO_dataout = (indv === 1'b1) ? n01lO : rd_enable_ch0;
	assign		wire_n00l_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[9] : wire_nili_dataout;
	assign		wire_n00ll_dataout = (rtxphfifopldctl_en === 1'b1) ? (((~ n01OO) & n01Oi) & (nl0i0i32 ^ nl0i0i31)) : n01Oi;
	assign		wire_n00O_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[10] : wire_nill_dataout;
	and(wire_n00Ol_dataout, wire_n0l1l_dataout, ~(nl0lii));
	or(wire_n00OO_dataout, wire_n0l1O_dataout, nl0lii);
	assign		wire_n01i_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[5] : wire_ni0O_dataout;
	assign		wire_n01il_dataout = (rtx_pipe_enable === 1'b1) ? wire_nl11i_dataout : wire_ni1ll_dataout;
	assign		wire_n01l_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[6] : wire_niii_dataout;
	assign		wire_n01O_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[7] : wire_niil_dataout;
	assign		wire_n0i_dataout = (nl0Oll === 1'b1) ? txd_redun[13] : txd[13];
	or(wire_n0i0i_dataout, wire_n0lii_dataout, nl0lii);
	or(wire_n0i0l_dataout, wire_n0lil_dataout, nl0lii);
	or(wire_n0i0O_dataout, wire_n0liO_dataout, nl0lii);
	or(wire_n0i1i_dataout, wire_n0l0i_dataout, nl0lii);
	or(wire_n0i1l_dataout, wire_n0l0l_dataout, nl0lii);
	or(wire_n0i1O_dataout, wire_n0l0O_dataout, nl0lii);
	assign		wire_n0ii_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[11] : wire_nilO_dataout;
	and(wire_n0iii_dataout, wire_n0lli_dataout, ~(nl0lii));
	or(wire_n0iil_dataout, wire_n0lll_dataout, nl0lii);
	or(wire_n0iiO_dataout, wire_n0llO_dataout, nl0lii);
	assign		wire_n0il_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[12] : wire_niOi_dataout;
	or(wire_n0ili_dataout, wire_n0lOi_dataout, nl0lii);
	or(wire_n0ill_dataout, wire_n0lOl_dataout, nl0lii);
	or(wire_n0ilO_dataout, wire_n0lOO_dataout, nl0lii);
	assign		wire_n0iO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[13] : wire_niOl_dataout;
	or(wire_n0iOi_dataout, wire_n0O1i_dataout, nl0lii);
	or(wire_n0iOl_dataout, wire_n0O1l_dataout, nl0lii);
	and(wire_n0iOO_dataout, wire_n0O1O_dataout, ~(nl0lii));
	assign		wire_n0l_dataout = (nl0Oll === 1'b1) ? txd_redun[14] : txd[14];
	or(wire_n0l0i_dataout, n1iiO, ~(nl0lil));
	assign		wire_n0l0l_dataout = (nl0lil === 1'b1) ? n1ili : indv;
	assign		wire_n0l0O_dataout = (nl0lil === 1'b1) ? n1ill : indv;
	and(wire_n0l1i_dataout, wire_n0O0i_dataout, ~(nl0lii));
	assign		wire_n0l1l_dataout = (nl0lil === 1'b1) ? n1iii : (~ indv);
	assign		wire_n0l1O_dataout = (nl0lil === 1'b1) ? n1iil : (~ indv);
	assign		wire_n0li_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[14] : wire_niOO_dataout;
	assign		wire_n0lii_dataout = (nl0lil === 1'b1) ? n1ilO : indv;
	and(wire_n0lil_dataout, n1iOi, nl0lil);
	assign		wire_n0liO_dataout = (nl0lil === 1'b1) ? n1iOl : indv;
	assign		wire_n0ll_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[15] : wire_nl1i_dataout;
	assign		wire_n0lli_dataout = (nl0lil === 1'b1) ? n1l1l : (~ indv);
	assign		wire_n0lll_dataout = (nl0lil === 1'b1) ? n1l1O : (~ indv);
	or(wire_n0llO_dataout, n1l0i, ~(nl0lil));
	assign		wire_n0lO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[16] : wire_nl1l_dataout;
	assign		wire_n0lOi_dataout = (nl0lil === 1'b1) ? n1l0l : indv;
	assign		wire_n0lOl_dataout = (nl0lil === 1'b1) ? n1l0O : indv;
	assign		wire_n0lOO_dataout = (nl0lil === 1'b1) ? n1lii : indv;
	assign		wire_n0O_dataout = (nl0Oll === 1'b1) ? txd_redun[15] : txd[15];
	and(wire_n0O0i_dataout, wire_nO_dataout, nl0lil);
	and(wire_n0O1i_dataout, n1lil, nl0lil);
	assign		wire_n0O1l_dataout = (nl0lil === 1'b1) ? n1liO : indv;
	and(wire_n0O1O_dataout, wire_nl_dataout, nl0lil);
	assign		wire_n0Oi_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[17] : wire_nl1O_dataout;
	assign		wire_n0Ol_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[18] : wire_nl0i_dataout;
	assign		wire_n0Oli_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[0] : wire_ni1Oi_dataout;
	assign		wire_n0Oll_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[1] : wire_ni1Ol_dataout;
	assign		wire_n0OlO_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[2] : wire_ni1OO_dataout;
	assign		wire_n0OO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[19] : wire_nl0l_dataout;
	assign		wire_n0OOi_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[3] : wire_ni01i_dataout;
	assign		wire_n0OOl_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[4] : wire_ni01l_dataout;
	assign		wire_n0OOO_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[5] : wire_ni01O_dataout;
	assign		wire_n10i_dataout = (nl0Oil === 1'b1) ? txd_redun[34] : txd[34];
	and(wire_n10il_dataout, wire_n10iO_dataout, n100O);
	assign		wire_n10iO_dataout = (rphfifo_master_sel_tx === 1'b1) ? wire_n10li_dataout : (~ fifo_select_in_q0_ch0);
	assign		wire_n10l_dataout = (nl0Oil === 1'b1) ? txd_redun[35] : txd[35];
	assign		wire_n10li_dataout = (indv === 1'b1) ? (~ n01ii) : (~ fifo_select_in_ch0);
	and(wire_n10ll_dataout, wire_n10lO_dataout, n100i);
	or(wire_n10lO_dataout, n01ll, n100O);
	assign		wire_n10O_dataout = (nl0Oil === 1'b1) ? txd_redun[36] : txd[36];
	assign		wire_n11i_dataout = (nl0Oil === 1'b1) ? txd_redun[31] : txd[31];
	assign		wire_n11l_dataout = (nl0Oil === 1'b1) ? txd_redun[32] : txd[32];
	assign		wire_n11O_dataout = (nl0Oil === 1'b1) ? txd_redun[33] : txd[33];
	assign		wire_n1i_dataout = (nl0Oll === 1'b1) ? txd_redun[10] : txd[10];
	assign		wire_n1ii_dataout = (nl0Oil === 1'b1) ? txd_redun[37] : txd[37];
	assign		wire_n1il_dataout = (nl0Oil === 1'b1) ? txd_redun[38] : txd[38];
	assign		wire_n1iO_dataout = (nl0Oil === 1'b1) ? txd_redun[39] : txd[39];
	assign		wire_n1l_dataout = (nl0Oll === 1'b1) ? txd_redun[11] : txd[11];
	assign		wire_n1ll_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[0] : wire_ni1i_dataout;
	assign		wire_n1lO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[1] : wire_ni1l_dataout;
	assign		wire_n1O_dataout = (nl0Oll === 1'b1) ? txd_redun[12] : txd[12];
	assign		wire_n1Oi_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[2] : wire_ni1O_dataout;
	assign		wire_n1Ol_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[3] : wire_ni0i_dataout;
	assign		wire_n1OO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[4] : wire_ni0l_dataout;
	and(wire_ni_dataout, txd_extend[1], rforce_disp);
	assign		wire_ni00i_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[28] : wire_niiii_dataout;
	assign		wire_ni00l_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[29] : wire_niiil_dataout;
	assign		wire_ni00O_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[32] : wire_niiiO_dataout;
	assign		wire_ni01i_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[25] : wire_nii0i_dataout;
	assign		wire_ni01l_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[26] : wire_nii0l_dataout;
	assign		wire_ni01O_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[27] : wire_nii0O_dataout;
	assign		wire_ni0i_dataout = (selftest_en === 1'b1) ? tx_data_sg[3] : wire_nliO_dataout;
	assign		wire_ni0ii_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[33] : wire_niili_dataout;
	assign		wire_ni0il_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[34] : wire_niill_dataout;
	assign		wire_ni0iO_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[35] : wire_niilO_dataout;
	assign		wire_ni0l_dataout = (selftest_en === 1'b1) ? tx_data_sg[4] : wire_nlli_dataout;
	assign		wire_ni0li_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[36] : wire_niiOi_dataout;
	assign		wire_ni0ll_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[37] : wire_niiOl_dataout;
	assign		wire_ni0lO_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[38] : wire_niiOO_dataout;
	assign		wire_ni0O_dataout = (selftest_en === 1'b1) ? tx_data_sg[5] : wire_nlll_dataout;
	assign		wire_ni0Oi_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[39] : wire_nil1i_dataout;
	assign		wire_ni0Ol_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[42] : wire_nil1l_dataout;
	assign		wire_ni0OO_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[43] : wire_nil1O_dataout;
	assign		wire_ni10i_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[11] : wire_ni0ii_dataout;
	assign		wire_ni10l_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[12] : wire_ni0il_dataout;
	assign		wire_ni10O_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[13] : wire_ni0iO_dataout;
	assign		wire_ni11i_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[6] : wire_ni00i_dataout;
	assign		wire_ni11l_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[7] : wire_ni00l_dataout;
	assign		wire_ni11O_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[10] : wire_ni00O_dataout;
	assign		wire_ni1i_dataout = (selftest_en === 1'b1) ? tx_data_sg[0] : wire_nl0O_dataout;
	assign		wire_ni1ii_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[14] : wire_ni0li_dataout;
	assign		wire_ni1il_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[15] : wire_ni0ll_dataout;
	assign		wire_ni1iO_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[16] : wire_ni0lO_dataout;
	assign		wire_ni1l_dataout = (selftest_en === 1'b1) ? tx_data_sg[1] : wire_nlii_dataout;
	assign		wire_ni1li_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[17] : wire_ni0Oi_dataout;
	assign		wire_ni1ll_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[20] : wire_ni0Ol_dataout;
	assign		wire_ni1lO_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[21] : wire_ni0OO_dataout;
	assign		wire_ni1O_dataout = (selftest_en === 1'b1) ? tx_data_sg[2] : wire_nlil_dataout;
	assign		wire_ni1Oi_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[22] : wire_nii1i_dataout;
	assign		wire_ni1Ol_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[23] : wire_nii1l_dataout;
	assign		wire_ni1OO_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[24] : wire_nii1O_dataout;
	assign		wire_nii_dataout = (nl0Oll === 1'b1) ? txd_redun[16] : txd[16];
	assign		wire_nii0i_dataout = (nl0lll === 1'b1) ? wire_n1Ol_dataout : wire_n0i1l_dataout;
	assign		wire_nii0l_dataout = (nl0lll === 1'b1) ? wire_n1OO_dataout : wire_n0i1O_dataout;
	assign		wire_nii0O_dataout = (nl0lll === 1'b1) ? wire_n01i_dataout : wire_n0i0i_dataout;
	assign		wire_nii1i_dataout = (nl0lll === 1'b1) ? wire_n1ll_dataout : wire_n00Ol_dataout;
	assign		wire_nii1l_dataout = (nl0lll === 1'b1) ? wire_n1lO_dataout : wire_n00OO_dataout;
	assign		wire_nii1O_dataout = (nl0lll === 1'b1) ? wire_n1Oi_dataout : wire_n0i1i_dataout;
	assign		wire_niii_dataout = (selftest_en === 1'b1) ? tx_data_sg[6] : wire_nllO_dataout;
	assign		wire_niiii_dataout = (nl0lll === 1'b1) ? wire_n01l_dataout : wire_n0i0l_dataout;
	assign		wire_niiil_dataout = (nl0lll === 1'b1) ? wire_n01O_dataout : wire_n0i0O_dataout;
	assign		wire_niiiO_dataout = (nl0lll === 1'b1) ? wire_n00O_dataout : wire_n0iii_dataout;
	assign		wire_niil_dataout = (selftest_en === 1'b1) ? tx_data_sg[7] : wire_nlOi_dataout;
	assign		wire_niili_dataout = (nl0lll === 1'b1) ? wire_n0ii_dataout : wire_n0iil_dataout;
	assign		wire_niill_dataout = (nl0lll === 1'b1) ? wire_n0il_dataout : wire_n0iiO_dataout;
	assign		wire_niilO_dataout = (nl0lll === 1'b1) ? wire_n0iO_dataout : wire_n0ili_dataout;
	assign		wire_niiO_dataout = (selftest_en === 1'b1) ? tx_control_sg[0] : wire_nlOl_dataout;
	assign		wire_niiOi_dataout = (nl0lll === 1'b1) ? wire_n0li_dataout : wire_n0ill_dataout;
	assign		wire_niiOl_dataout = (nl0lll === 1'b1) ? wire_n0ll_dataout : wire_n0ilO_dataout;
	assign		wire_niiOO_dataout = (nl0lll === 1'b1) ? wire_n0lO_dataout : wire_n0iOi_dataout;
	assign		wire_nil_dataout = (nl0Oll === 1'b1) ? txd_redun[17] : txd[17];
	assign		wire_nil1i_dataout = (nl0lll === 1'b1) ? wire_n0Oi_dataout : wire_n0iOl_dataout;
	assign		wire_nil1l_dataout = (nl0lll === 1'b1) ? wire_nlO_dataout : wire_n0iOO_dataout;
	assign		wire_nil1O_dataout = (nl0lll === 1'b1) ? wire_ni_dataout : wire_n0l1i_dataout;
	and(wire_nili_dataout, wire_nlOO_dataout, ~(selftest_en));
	assign		wire_nill_dataout = (selftest_en === 1'b1) ? tx_data_sg[8] : wire_n1i_dataout;
	assign		wire_nilO_dataout = (selftest_en === 1'b1) ? tx_data_sg[9] : wire_n1l_dataout;
	assign		wire_niO_dataout = (nl0Oll === 1'b1) ? txd_redun[18] : txd[18];
	or(wire_niO0i_dataout, n1iOO, ~(nl0lil));
	or(wire_niO0l_dataout, n1lli, ~(nl0lil));
	assign		wire_niO0O_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[8] : wire_niOil_dataout;
	or(wire_niO1l_dataout, wire_niO0i_dataout, nl0lii);
	or(wire_niO1O_dataout, wire_niO0l_dataout, nl0lii);
	assign		wire_niOi_dataout = (selftest_en === 1'b1) ? tx_data_sg[10] : wire_n1O_dataout;
	assign		wire_niOii_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[18] : wire_niOiO_dataout;
	assign		wire_niOil_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[30] : wire_niOli_dataout;
	assign		wire_niOiO_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[40] : wire_niOll_dataout;
	assign		wire_niOl_dataout = (selftest_en === 1'b1) ? tx_data_sg[11] : wire_n0i_dataout;
	assign		wire_niOli_dataout = (nl0lll === 1'b1) ? wire_n00i_dataout : wire_niO1l_dataout;
	assign		wire_niOll_dataout = (nl0lll === 1'b1) ? wire_n0Ol_dataout : wire_niO1O_dataout;
	and(wire_niOlO_dataout, wire_niOOl_dataout, ~(nl0lii));
	assign		wire_niOO_dataout = (selftest_en === 1'b1) ? tx_data_sg[12] : wire_n0l_dataout;
	and(wire_niOOi_dataout, wire_niOOO_dataout, ~(nl0lii));
	and(wire_niOOl_dataout, n1l1i, nl0lil);
	and(wire_niOOO_dataout, n1llO, nl0lil);
	and(wire_nl_dataout, txd_extend[2], rforce_disp);
	and(wire_nl00l_dataout, nl00i, ~(scan_mode));
	and(wire_nl01i_dataout, nl1ll, ~(scan_mode));
	assign		wire_nl0i_dataout = (selftest_en === 1'b1) ? tx_control_sg[1] : wire_niO_dataout;
	and(wire_nl0l_dataout, wire_nli_dataout, ~(selftest_en));
	assign		wire_nl0li_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[20] : wire_nliOO_dataout;
	assign		wire_nl0ll_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[21] : wire_nll1i_dataout;
	assign		wire_nl0lO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[22] : wire_nll1l_dataout;
	assign		wire_nl0O_dataout = (nl0Oll === 1'b1) ? txd_redun[0] : txd[0];
	assign		wire_nl0Oi_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[23] : wire_nll1O_dataout;
	assign		wire_nl0Ol_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[24] : wire_nll0i_dataout;
	assign		wire_nl0OO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[25] : wire_nll0l_dataout;
	assign		wire_nl10i_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[41] : wire_nl10O_dataout;
	assign		wire_nl10l_dataout = (nl0lll === 1'b1) ? wire_n00l_dataout : wire_niOlO_dataout;
	assign		wire_nl10O_dataout = (nl0lll === 1'b1) ? wire_n0OO_dataout : wire_niOOi_dataout;
	assign		wire_nl11i_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[9] : wire_nl11O_dataout;
	assign		wire_nl11l_dataout = (nl0liO === 1'b1) ? wire_nli11i_data_out[19] : wire_nl10i_dataout;
	assign		wire_nl11O_dataout = (nl0lli === 1'b1) ? wire_nli11i_data_out[31] : wire_nl10l_dataout;
	assign		wire_nl1i_dataout = (selftest_en === 1'b1) ? tx_data_sg[13] : wire_n0O_dataout;
	assign		wire_nl1l_dataout = (selftest_en === 1'b1) ? tx_data_sg[14] : wire_nii_dataout;
	assign		wire_nl1lO_dataout = (rphfifo_master_sel_tx === 1'b1) ? wire_nl1Oi_dataout : wr_enable_q0_ch0;
	assign		wire_nl1O_dataout = (selftest_en === 1'b1) ? tx_data_sg[15] : wire_nil_dataout;
	assign		wire_nl1Oi_dataout = (indv === 1'b1) ? nl1ii : wr_enable_ch0;
	assign		wire_nl1Ol_dataout = (rtxphfifopldctl_en === 1'b1) ? ((nl1il & pld_we) & (nl0lOi14 ^ nl0lOi13)) : nl1il;
	assign		wire_nli_dataout = (nl0Oll === 1'b1) ? txd_redun[19] : txd[19];
	assign		wire_nli0i_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[29] : wire_nlliO_dataout;
	assign		wire_nli0l_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[30] : wire_nllli_dataout;
	assign		wire_nli0O_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[31] : wire_nllll_dataout;
	assign		wire_nli1i_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[26] : wire_nll0O_dataout;
	assign		wire_nli1l_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[27] : wire_nllii_dataout;
	assign		wire_nli1O_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[28] : wire_nllil_dataout;
	assign		wire_nlii_dataout = (nl0Oll === 1'b1) ? txd_redun[1] : txd[1];
	assign		wire_nliii_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[32] : wire_nlllO_dataout;
	assign		wire_nliil_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[33] : wire_nllOi_dataout;
	assign		wire_nliiO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[34] : wire_nllOl_dataout;
	assign		wire_nlil_dataout = (nl0Oll === 1'b1) ? txd_redun[2] : txd[2];
	assign		wire_nlili_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[35] : wire_nllOO_dataout;
	assign		wire_nlill_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[36] : wire_nlO1i_dataout;
	assign		wire_nlilO_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[37] : wire_nlO1l_dataout;
	assign		wire_nliO_dataout = (nl0Oll === 1'b1) ? txd_redun[3] : txd[3];
	assign		wire_nliOi_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[38] : wire_nlO1O_dataout;
	assign		wire_nliOl_dataout = (p_rlpbk === 1'b1) ? rxd_lpbk[39] : wire_nlO0i_dataout;
	assign		wire_nliOO_dataout = (selftest_en === 1'b1) ? tx_data_sg[8] : wire_nlO0l_dataout;
	assign		wire_nll0i_dataout = (selftest_en === 1'b1) ? tx_data_sg[12] : wire_nlOiO_dataout;
	assign		wire_nll0l_dataout = (selftest_en === 1'b1) ? tx_data_sg[13] : wire_nlOli_dataout;
	assign		wire_nll0O_dataout = (selftest_en === 1'b1) ? tx_data_sg[14] : wire_nlOll_dataout;
	assign		wire_nll1i_dataout = (selftest_en === 1'b1) ? tx_data_sg[9] : wire_nlO0O_dataout;
	assign		wire_nll1l_dataout = (selftest_en === 1'b1) ? tx_data_sg[10] : wire_nlOii_dataout;
	assign		wire_nll1O_dataout = (selftest_en === 1'b1) ? tx_data_sg[11] : wire_nlOil_dataout;
	assign		wire_nlli_dataout = (nl0Oll === 1'b1) ? txd_redun[4] : txd[4];
	assign		wire_nllii_dataout = (selftest_en === 1'b1) ? tx_data_sg[15] : wire_nlOlO_dataout;
	assign		wire_nllil_dataout = (selftest_en === 1'b1) ? tx_control_sg[1] : wire_nlOOi_dataout;
	and(wire_nlliO_dataout, wire_nlOOl_dataout, ~(selftest_en));
	assign		wire_nlll_dataout = (nl0Oll === 1'b1) ? txd_redun[5] : txd[5];
	assign		wire_nllli_dataout = (selftest_en === 1'b1) ? tx_data_sg[24] : wire_nlOOO_dataout;
	assign		wire_nllll_dataout = (selftest_en === 1'b1) ? tx_data_sg[25] : wire_n11i_dataout;
	assign		wire_nlllO_dataout = (selftest_en === 1'b1) ? tx_data_sg[26] : wire_n11l_dataout;
	assign		wire_nllO_dataout = (nl0Oll === 1'b1) ? txd_redun[6] : txd[6];
	assign		wire_nllOi_dataout = (selftest_en === 1'b1) ? tx_data_sg[27] : wire_n11O_dataout;
	assign		wire_nllOl_dataout = (selftest_en === 1'b1) ? tx_data_sg[28] : wire_n10i_dataout;
	assign		wire_nllOO_dataout = (selftest_en === 1'b1) ? tx_data_sg[29] : wire_n10l_dataout;
	and(wire_nlO_dataout, txd_extend[0], rforce_disp);
	and(wire_nlO0i_dataout, wire_n1iO_dataout, ~(selftest_en));
	assign		wire_nlO0l_dataout = (nl0Oil === 1'b1) ? txd_redun[20] : txd[20];
	assign		wire_nlO0O_dataout = (nl0Oil === 1'b1) ? txd_redun[21] : txd[21];
	assign		wire_nlO1i_dataout = (selftest_en === 1'b1) ? tx_data_sg[30] : wire_n10O_dataout;
	assign		wire_nlO1l_dataout = (selftest_en === 1'b1) ? tx_data_sg[31] : wire_n1ii_dataout;
	assign		wire_nlO1O_dataout = (selftest_en === 1'b1) ? tx_control_sg[3] : wire_n1il_dataout;
	assign		wire_nlOi_dataout = (nl0Oll === 1'b1) ? txd_redun[7] : txd[7];
	assign		wire_nlOii_dataout = (nl0Oil === 1'b1) ? txd_redun[22] : txd[22];
	assign		wire_nlOil_dataout = (nl0Oil === 1'b1) ? txd_redun[23] : txd[23];
	assign		wire_nlOiO_dataout = (nl0Oil === 1'b1) ? txd_redun[24] : txd[24];
	assign		wire_nlOl_dataout = (nl0Oll === 1'b1) ? txd_redun[8] : txd[8];
	assign		wire_nlOli_dataout = (nl0Oil === 1'b1) ? txd_redun[25] : txd[25];
	assign		wire_nlOll_dataout = (nl0Oil === 1'b1) ? txd_redun[26] : txd[26];
	assign		wire_nlOlO_dataout = (nl0Oil === 1'b1) ? txd_redun[27] : txd[27];
	assign		wire_nlOO_dataout = (nl0Oll === 1'b1) ? txd_redun[9] : txd[9];
	assign		wire_nlOOi_dataout = (nl0Oil === 1'b1) ? txd_redun[28] : txd[28];
	assign		wire_nlOOl_dataout = (nl0Oil === 1'b1) ? txd_redun[29] : txd[29];
	assign		wire_nlOOO_dataout = (nl0Oil === 1'b1) ? txd_redun[30] : txd[30];
	and(wire_nO_dataout, txd_extend[3], rforce_disp);
	arriagx_hssi_tx_ph_fifo   nli11i
	( 
	.bypass_en(txfifo_dis),
	.data_out(wire_nli11i_data_out),
	.din({wire_nO_dataout, wire_nl_dataout, wire_nliOl_dataout, wire_nliOi_dataout, wire_nlilO_dataout, wire_nlill_dataout, wire_nlili_dataout, wire_nliiO_dataout, wire_nliil_dataout, wire_nliii_dataout, wire_nli0O_dataout, wire_nli0l_dataout, wire_nli0i_dataout, wire_nli1O_dataout, wire_nli1l_dataout, wire_nli1i_dataout, wire_nl0OO_dataout, wire_nl0Ol_dataout, wire_nl0Oi_dataout, wire_nl0lO_dataout, wire_nl0ll_dataout, wire_nl0li_dataout, wire_ni_dataout, wire_nlO_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout, wire_n0iO_dataout, wire_n0il_dataout, wire_n0ii_dataout, wire_n00O_dataout, wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout}),
	.lowlatency_en(rtxfifo_lowlatency_en),
	.ph_fifo_empty(wire_nli11i_ph_fifo_empty),
	.ph_fifo_full(wire_nli11i_ph_fifo_full),
	.rd_clk(fifo_rd_clk),
	.re(n01ll),
	.rptr_bin(wire_nli11i_rptr_bin),
	.rst_rclk(wire_nl01i_dataout),
	.rst_wclk(wire_nl00l_dataout),
	.we(n000l),
	.wptr_bin(wire_nli11i_wptr_bin),
	.wr_clk(fifo_wr_clk));
	assign
		d21_5_eq_n = {n1i0O, n1i0i},
		d2_2_eq_n = {n1i1O, n1i1l},
		fifo_select_out = n01ii,
		k_det = {n10Ol, n10Oi},
		nl000O = ((((((((wire_niO0O_dataout & wire_ni11l_dataout) & (~ wire_ni11i_dataout)) & wire_n0OOO_dataout) & wire_n0OOl_dataout) & wire_n0OOi_dataout) & wire_n0OlO_dataout) & (~ wire_n0Oll_dataout)) & (~ wire_n0Oli_dataout)),
		nl00ii = (((((((((wire_niOii_dataout & wire_ni1li_dataout) & (~ wire_ni1iO_dataout)) & wire_ni1il_dataout) & wire_ni1ii_dataout) & wire_ni10O_dataout) & wire_ni10l_dataout) & (~ wire_ni10i_dataout)) & (~ wire_ni11O_dataout)) & (nl001l46 ^ nl001l45)),
		nl00il = (((((((((~ wire_niO0O_dataout) & (~ wire_ni11l_dataout)) & wire_ni11i_dataout) & (~ wire_n0OOO_dataout)) & (~ wire_n0OOl_dataout)) & (~ wire_n0OOi_dataout)) & (~ wire_n0OlO_dataout)) & wire_n0Oll_dataout) & (~ wire_n0Oli_dataout)),
		nl00iO = (((((((((~ wire_niOii_dataout) & (~ wire_ni1li_dataout)) & wire_ni1iO_dataout) & (~ wire_ni1il_dataout)) & (~ wire_ni1ii_dataout)) & (~ wire_ni10O_dataout)) & (~ wire_ni10l_dataout)) & wire_ni10i_dataout) & (~ wire_ni11O_dataout)),
		nl00li = ((((((((((~ wire_niO0O_dataout) & wire_ni11l_dataout) & (~ wire_ni11i_dataout)) & wire_n0OOO_dataout) & wire_n0OOl_dataout) & (~ wire_n0OOi_dataout)) & wire_n0OlO_dataout) & (~ wire_n0Oll_dataout)) & wire_n0Oli_dataout) & (nl000i44 ^ nl000i43)),
		nl00lO = (((((((((~ wire_niOii_dataout) & wire_ni1li_dataout) & (~ wire_ni1iO_dataout)) & wire_ni1il_dataout) & wire_ni1ii_dataout) & (~ wire_ni10O_dataout)) & wire_ni10l_dataout) & (~ wire_ni10i_dataout)) & wire_ni11O_dataout),
		nl0l0O = (n010l & (~ txfifo_dis)),
		nl0l1O = ((~ n01ii) & dwidth),
		nl0lii = ((~ rforce_kchar) & rforce_echar),
		nl0lil = ((((((dwidth & txfifo_dis) & n01ii) & (nl0iil28 ^ nl0iil27)) & (~ rforce_kchar)) & (~ rforce_echar)) & (nl0i0O30 ^ nl0i0O29)),
		nl0liO = (((((n01ii | (~ dwidth)) & nl0l0O) & (~ rforce_kchar)) & (~ rforce_echar)) & (nl0l0i18 ^ nl0l0i17)),
		nl0lli = (((((nl0l0O & nl0l1O) & (nl0l1i20 ^ nl0l1i19)) & (~ rforce_kchar)) & (nl0iOl22 ^ nl0iOl21)) & (~ rforce_echar)),
		nl0lll = (((((((~ n01ii) | (~ dwidth)) & txfifo_dis) & (~ rforce_kchar)) & (nl0ilO24 ^ nl0ilO23)) & (~ rforce_echar)) & (nl0ili26 ^ nl0ili25)),
		nl0O0i = 1'b0,
		nl0O0l = (((rtxfifo_urst_en & txfifo_urst) | soft_reset) | (~ (nl0O0O6 ^ nl0O0O5))),
		nl0O1l = 1'b1,
		nl0Oil = ((((redund_ctl[0] | redund_ctl[1]) | redund_ctl[2]) | redund_ctl[3]) | (~ (nl0OiO4 ^ nl0OiO3))),
		nl0Oll = ((((redund_ctl[0] | redund_ctl[1]) | redund_ctl[2]) | redund_ctl[3]) | (~ (nl0OlO2 ^ nl0OlO1))),
		ph_fifo_empty = wire_nli11i_ph_fifo_empty,
		ph_fifo_full = wire_nli11i_ph_fifo_full,
		pipe_electric_idle = n10ii,
		rd_enable2 = n01ll,
		rd_enable_out = n01lO,
		rd_enable_sync = n010l,
		rptr_bin = {wire_nli11i_rptr_bin[2:0]},
		soft_reset_wclk1 = wire_nl00l_dataout,
		tx_ctl_tc = {n011l, n011i},
		tx_data_9_tc = {n010i, n011O},
		tx_data_tc = {n1OOO, n1OOl, n1OOi, n1OlO, n1Oll, n1Oli, n1OiO, n1Oil, n1Oii, n1O0O, n1O0l, n1O0i, n1O1O, n1O1l, n1O1i, n1lOO},
		txd_extend_tc = {n1lOl, n1lOi},
		wptr_bin = {wire_nli11i_wptr_bin[2:0]},
		wr_enable2 = n000l,
		wr_enable_out = nl1ii;
endmodule //arriagx_hssi_tx_ctrl
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



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// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 211 mux21 446 oper_add 10 oper_selector 88 
`timescale 1 ps / 1 ps
module  arriagx_hssi_tx_bist_gen
	( 
	bist_ctl_sg,
	bist_data_sg,
	rbist_sel,
	rbisten_tx,
	rcxpat_chnl_sel,
	rdwidth_tx,
	rpma_doublewidth_tx,
	rpmadwidth_tx,
	soft_reset,
	tx_clk) /* synthesis synthesis_clearbox=1 */;
	output   [1:0]  bist_ctl_sg;
	output   [15:0]  bist_data_sg;
	input   [1:0]  rbist_sel;
	input   rbisten_tx;
	input   [1:0]  rcxpat_chnl_sel;
	input   rdwidth_tx;
	input   rpma_doublewidth_tx;
	input   rpmadwidth_tx;
	input   soft_reset;
	input   tx_clk;

	reg	ni001l45;
	reg	ni001l46;
	reg	nii00O39;
	reg	nii00O40;
	reg	nii01O41;
	reg	nii01O42;
	reg	nii0il37;
	reg	nii0il38;
	reg	nii0li35;
	reg	nii0li36;
	reg	nii0lO33;
	reg	nii0lO34;
	reg	nii0OO31;
	reg	nii0OO32;
	reg	nii1OO43;
	reg	nii1OO44;
	reg	niii0i23;
	reg	niii0i24;
	reg	niii0O21;
	reg	niii0O22;
	reg	niii1i29;
	reg	niii1i30;
	reg	niii1l27;
	reg	niii1l28;
	reg	niii1O25;
	reg	niii1O26;
	reg	niillO19;
	reg	niillO20;
	reg	niilOi17;
	reg	niilOi18;
	reg	niilOO15;
	reg	niilOO16;
	reg	niiO0i10;
	reg	niiO0i9;
	reg	niiO0O7;
	reg	niiO0O8;
	reg	niiO1i13;
	reg	niiO1i14;
	reg	niiO1l11;
	reg	niiO1l12;
	reg	niiOll5;
	reg	niiOll6;
	reg	niiOOl3;
	reg	niiOOl4;
	reg	nil11i1;
	reg	nil11i2;
	reg	n100i;
	reg	n100l;
	reg	n100O;
	reg	n101i;
	reg	n101l;
	reg	n101O;
	reg	n10ii;
	reg	n10il;
	reg	n10iO;
	reg	n10li;
	reg	n10ll;
	reg	n10lO;
	reg	n10Oi;
	reg	n10Ol;
	reg	n10OO;
	reg	n110i;
	reg	n110l;
	reg	n110O;
	reg	n111i;
	reg	n111l;
	reg	n111O;
	reg	n11ii;
	reg	n11il;
	reg	n11iO;
	reg	n11li;
	reg	n11ll;
	reg	n11lO;
	reg	n11Oi;
	reg	n11Ol;
	reg	n11OO;
	reg	n1i0i;
	reg	n1i0l;
	reg	n1i0O;
	reg	n1i1i;
	reg	n1i1l;
	reg	n1i1O;
	reg	n1iii;
	reg	n1iil;
	reg	n1iiO;
	reg	n1ili;
	reg	n1ill;
	reg	n1ilO;
	reg	n1iOi;
	reg	n1iOl;
	reg	n1iOO;
	reg	n1l0i;
	reg	n1l0l;
	reg	n1l1i;
	reg	n1l1l;
	reg	n1l1O;
	reg	n1lii;
	reg	nliliO;
	reg	nlOOil;
	reg	nlOOiO;
	reg	nlOOli;
	reg	nlOOll;
	reg	nlOOlO;
	reg	nlOOOi;
	reg	nlOOOl;
	reg	nlOOOO;
	reg	n1liO;
	reg	nl00il;
	reg	nl00iO;
	reg	nl00li;
	reg	nl00ll;
	reg	nl00lO;
	reg	nl00Oi;
	reg	nl00Ol;
	reg	nl00OO;
	reg	nl0i0i;
	reg	nl0i0l;
	reg	nl0i0O;
	reg	nl0i1i;
	reg	nl0i1l;
	reg	nl0i1O;
	reg	nl0iii;
	reg	nl0iil;
	reg	nl0iiO;
	reg	nl0ili;
	reg	nl0ill;
	reg	nl0ilO;
	reg	nl0iOi;
	reg	nl0iOl;
	reg	nl0iOO;
	reg	nl0l0i;
	reg	nl0l0l;
	reg	nl0l0O;
	reg	nl0l1i;
	reg	nl0l1l;
	reg	nl0l1O;
	reg	nl0lii;
	reg	nl0lil;
	reg	nl0liO;
	reg	nl0lli;
	reg	nl0lll;
	reg	nl0llO;
	reg	nl0lOi;
	reg	nl0lOl;
	reg	nl0lOO;
	reg	nl0O0i;
	reg	nl0O0l;
	reg	nl0O0O;
	reg	nl0O1i;
	reg	nl0O1l;
	reg	nl0O1O;
	reg	nl0Oii;
	reg	nl0Oil;
	reg	nl0OiO;
	reg	nl0Oli;
	reg	nl0Oll;
	reg	nl0OlO;
	reg	nl0OOi;
	reg	nl0OOl;
	reg	nli11i;
	reg	nl0OOO_clk_prev;
	wire	wire_nl0OOO_PRN;
	reg	nli11O;
	reg	n0lOi;
	reg	niO0l;
	reg	niO0O;
	reg	niOii;
	reg	niOil;
	reg	niOiO;
	reg	niOli;
	reg	niOll;
	reg	niOlO;
	reg	niOOi;
	reg	niOOl;
	reg	niOOO;
	reg	nl00i;
	reg	nl00l;
	reg	nl00O;
	reg	nl01i;
	reg	nl01l;
	reg	nl01O;
	reg	nl0ii;
	reg	nl0il;
	reg	nl0iO;
	reg	nl0li;
	reg	nl0ll;
	reg	nl0lO;
	reg	nl0Oi;
	reg	nl0Ol;
	reg	nl0OO;
	reg	nl10i;
	reg	nl10l;
	reg	nl10O;
	reg	nl11i;
	reg	nl11l;
	reg	nl11O;
	reg	nl1ii;
	reg	nl1il;
	reg	nl1iO;
	reg	nl1li;
	reg	nl1ll;
	reg	nl1lO;
	reg	nl1Oi;
	reg	nl1Ol;
	reg	nl1OO;
	reg	nli0i;
	reg	nli0l;
	reg	nli0O;
	reg	nli1i;
	reg	nli1l;
	reg	nli1O;
	reg	nliil;
	reg	nlili;
	reg	nliiO_clk_prev;
	wire	wire_nliiO_CLRN;
	wire	wire_nliiO_PRN;
	wire	wire_n000i_dataout;
	wire	wire_n000l_dataout;
	wire	wire_n000O_dataout;
	wire	wire_n001i_dataout;
	wire	wire_n001l_dataout;
	wire	wire_n001O_dataout;
	wire	wire_n00i_dataout;
	wire	wire_n00ii_dataout;
	wire	wire_n00il_dataout;
	wire	wire_n00iO_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00li_dataout;
	wire	wire_n00ll_dataout;
	wire	wire_n00lO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n010i_dataout;
	wire	wire_n010l_dataout;
	wire	wire_n010O_dataout;
	wire	wire_n011i_dataout;
	wire	wire_n011l_dataout;
	wire	wire_n011O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01ii_dataout;
	wire	wire_n01il_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01li_dataout;
	wire	wire_n01ll_dataout;
	wire	wire_n01lO_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n01Oi_dataout;
	wire	wire_n01Ol_dataout;
	wire	wire_n01OO_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0l0O_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0llO_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0O0i_dataout;
	wire	wire_n0O1i_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Oii_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0Oli_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n0OOi_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1lli_dataout;
	wire	wire_n1lll_dataout;
	wire	wire_n1llO_dataout;
	wire	wire_n1lOl_dataout;
	wire	wire_n1lOO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1O0i_dataout;
	wire	wire_n1O0l_dataout;
	wire	wire_n1O0O_dataout;
	wire	wire_n1O1i_dataout;
	wire	wire_n1O1l_dataout;
	wire	wire_n1O1O_dataout;
	wire	wire_n1Oii_dataout;
	wire	wire_n1Oil_dataout;
	wire	wire_n1OiO_dataout;
	wire	wire_n1Oli_dataout;
	wire	wire_n1OlO_dataout;
	wire	wire_n1OOi_dataout;
	wire	wire_n1OOl_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni0OO_dataout;
	wire	wire_ni11i_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_nii_dataout;
	wire	wire_nii0i_dataout;
	wire	wire_nii0l_dataout;
	wire	wire_nii0O_dataout;
	wire	wire_nii1i_dataout;
	wire	wire_nii1l_dataout;
	wire	wire_nii1O_dataout;
	wire	wire_niii_dataout;
	wire	wire_niiii_dataout;
	wire	wire_niiil_dataout;
	wire	wire_niiiO_dataout;
	wire	wire_niil_dataout;
	wire	wire_niili_dataout;
	wire	wire_niill_dataout;
	wire	wire_niilO_dataout;
	wire	wire_niiO_dataout;
	wire	wire_niiOi_dataout;
	wire	wire_niiOl_dataout;
	wire	wire_niiOO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nil0i_dataout;
	wire	wire_nil0l_dataout;
	wire	wire_nil0O_dataout;
	wire	wire_nil1i_dataout;
	wire	wire_nil1l_dataout;
	wire	wire_nil1O_dataout;
	wire	wire_nili_dataout;
	wire	wire_nilii_dataout;
	wire	wire_nilil_dataout;
	wire	wire_niliO_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilli_dataout;
	wire	wire_nilll_dataout;
	wire	wire_nillO_dataout;
	wire	wire_nilO_dataout;
	wire	wire_nilOi_dataout;
	wire	wire_nilOl_dataout;
	wire	wire_nilOO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niO00i_dataout;
	wire	wire_niO00l_dataout;
	wire	wire_niO00O_dataout;
	wire	wire_niO01i_dataout;
	wire	wire_niO01l_dataout;
	wire	wire_niO01O_dataout;
	wire	wire_niO0ii_dataout;
	wire	wire_niO0il_dataout;
	wire	wire_niO0iO_dataout;
	wire	wire_niO0li_dataout;
	wire	wire_niO0ll_dataout;
	wire	wire_niO0lO_dataout;
	wire	wire_niO0Oi_dataout;
	wire	wire_niO0Ol_dataout;
	wire	wire_niO0OO_dataout;
	wire	wire_niO10i_dataout;
	wire	wire_niO10l_dataout;
	wire	wire_niO10O_dataout;
	wire	wire_niO11l_dataout;
	wire	wire_niO11O_dataout;
	wire	wire_niO1i_dataout;
	wire	wire_niO1ii_dataout;
	wire	wire_niO1il_dataout;
	wire	wire_niO1iO_dataout;
	wire	wire_niO1l_dataout;
	wire	wire_niO1li_dataout;
	wire	wire_niO1ll_dataout;
	wire	wire_niO1lO_dataout;
	wire	wire_niO1O_dataout;
	wire	wire_niO1Oi_dataout;
	wire	wire_niO1Ol_dataout;
	wire	wire_niO1OO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOi0i_dataout;
	wire	wire_niOi0l_dataout;
	wire	wire_niOi0O_dataout;
	wire	wire_niOi1i_dataout;
	wire	wire_niOi1l_dataout;
	wire	wire_niOi1O_dataout;
	wire	wire_niOiii_dataout;
	wire	wire_niOiil_dataout;
	wire	wire_niOiiO_dataout;
	wire	wire_niOili_dataout;
	wire	wire_niOill_dataout;
	wire	wire_niOilO_dataout;
	wire	wire_niOiOi_dataout;
	wire	wire_niOiOl_dataout;
	wire	wire_niOiOO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOl0i_dataout;
	wire	wire_niOl0l_dataout;
	wire	wire_niOl0O_dataout;
	wire	wire_niOl1i_dataout;
	wire	wire_niOl1l_dataout;
	wire	wire_niOl1O_dataout;
	wire	wire_niOlii_dataout;
	wire	wire_niOlil_dataout;
	wire	wire_niOliO_dataout;
	wire	wire_niOlli_dataout;
	wire	wire_niOlll_dataout;
	wire	wire_niOllO_dataout;
	wire	wire_niOlOi_dataout;
	wire	wire_niOlOl_dataout;
	wire	wire_niOlOO_dataout;
	wire	wire_niOO_dataout;
	wire	wire_niOO0i_dataout;
	wire	wire_niOO0l_dataout;
	wire	wire_niOO0O_dataout;
	wire	wire_niOO1i_dataout;
	wire	wire_niOO1l_dataout;
	wire	wire_niOO1O_dataout;
	wire	wire_niOOii_dataout;
	wire	wire_niOOil_dataout;
	wire	wire_niOOiO_dataout;
	wire	wire_niOOli_dataout;
	wire	wire_niOOll_dataout;
	wire	wire_niOOlO_dataout;
	wire	wire_niOOOi_dataout;
	wire	wire_niOOOl_dataout;
	wire	wire_niOOOO_dataout;
	wire	wire_nl000i_dataout;
	wire	wire_nl000l_dataout;
	wire	wire_nl000O_dataout;
	wire	wire_nl001i_dataout;
	wire	wire_nl001l_dataout;
	wire	wire_nl001O_dataout;
	wire	wire_nl00ii_dataout;
	wire	wire_nl010i_dataout;
	wire	wire_nl010l_dataout;
	wire	wire_nl010O_dataout;
	wire	wire_nl011i_dataout;
	wire	wire_nl011l_dataout;
	wire	wire_nl011O_dataout;
	wire	wire_nl01ii_dataout;
	wire	wire_nl01il_dataout;
	wire	wire_nl01iO_dataout;
	wire	wire_nl01li_dataout;
	wire	wire_nl01ll_dataout;
	wire	wire_nl01lO_dataout;
	wire	wire_nl01Oi_dataout;
	wire	wire_nl01Ol_dataout;
	wire	wire_nl01OO_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl100i_dataout;
	wire	wire_nl100l_dataout;
	wire	wire_nl100O_dataout;
	wire	wire_nl101i_dataout;
	wire	wire_nl101l_dataout;
	wire	wire_nl101O_dataout;
	wire	wire_nl10ii_dataout;
	wire	wire_nl10il_dataout;
	wire	wire_nl10iO_dataout;
	wire	wire_nl10li_dataout;
	wire	wire_nl10ll_dataout;
	wire	wire_nl10lO_dataout;
	wire	wire_nl10Oi_dataout;
	wire	wire_nl10Ol_dataout;
	wire	wire_nl10OO_dataout;
	wire	wire_nl110i_dataout;
	wire	wire_nl110l_dataout;
	wire	wire_nl110O_dataout;
	wire	wire_nl111i_dataout;
	wire	wire_nl111l_dataout;
	wire	wire_nl111O_dataout;
	wire	wire_nl11ii_dataout;
	wire	wire_nl11il_dataout;
	wire	wire_nl11iO_dataout;
	wire	wire_nl11li_dataout;
	wire	wire_nl11ll_dataout;
	wire	wire_nl11lO_dataout;
	wire	wire_nl11Oi_dataout;
	wire	wire_nl11Ol_dataout;
	wire	wire_nl11OO_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1i0i_dataout;
	wire	wire_nl1i0l_dataout;
	wire	wire_nl1i0O_dataout;
	wire	wire_nl1i1i_dataout;
	wire	wire_nl1i1l_dataout;
	wire	wire_nl1i1O_dataout;
	wire	wire_nl1iii_dataout;
	wire	wire_nl1iil_dataout;
	wire	wire_nl1iiO_dataout;
	wire	wire_nl1ili_dataout;
	wire	wire_nl1ill_dataout;
	wire	wire_nl1ilO_dataout;
	wire	wire_nl1iOi_dataout;
	wire	wire_nl1iOl_dataout;
	wire	wire_nl1iOO_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1l0i_dataout;
	wire	wire_nl1l0l_dataout;
	wire	wire_nl1l0O_dataout;
	wire	wire_nl1l1i_dataout;
	wire	wire_nl1l1l_dataout;
	wire	wire_nl1l1O_dataout;
	wire	wire_nl1lii_dataout;
	wire	wire_nl1lil_dataout;
	wire	wire_nl1liO_dataout;
	wire	wire_nl1lli_dataout;
	wire	wire_nl1lll_dataout;
	wire	wire_nl1llO_dataout;
	wire	wire_nl1lOi_dataout;
	wire	wire_nl1lOl_dataout;
	wire	wire_nl1lOO_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nl1O0i_dataout;
	wire	wire_nl1O0l_dataout;
	wire	wire_nl1O0O_dataout;
	wire	wire_nl1O1i_dataout;
	wire	wire_nl1O1l_dataout;
	wire	wire_nl1O1O_dataout;
	wire	wire_nl1Oii_dataout;
	wire	wire_nl1Oil_dataout;
	wire	wire_nl1OiO_dataout;
	wire	wire_nl1Oli_dataout;
	wire	wire_nl1Oll_dataout;
	wire	wire_nl1OlO_dataout;
	wire	wire_nl1OOi_dataout;
	wire	wire_nl1OOl_dataout;
	wire	wire_nl1OOO_dataout;
	wire	wire_nli_dataout;
	wire	wire_nli00i_dataout;
	wire	wire_nli00l_dataout;
	wire	wire_nli00O_dataout;
	wire	wire_nli01i_dataout;
	wire	wire_nli01l_dataout;
	wire	wire_nli01O_dataout;
	wire	wire_nli0ii_dataout;
	wire	wire_nli0il_dataout;
	wire	wire_nli0iO_dataout;
	wire	wire_nli0li_dataout;
	wire	wire_nli10i_dataout;
	wire	wire_nli10l_dataout;
	wire	wire_nli10O_dataout;
	wire	wire_nli1ii_dataout;
	wire	wire_nli1il_dataout;
	wire	wire_nli1iO_dataout;
	wire	wire_nli1li_dataout;
	wire	wire_nli1ll_dataout;
	wire	wire_nli1lO_dataout;
	wire	wire_nli1Oi_dataout;
	wire	wire_nli1Ol_dataout;
	wire	wire_nli1OO_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nlil0O_dataout;
	wire	wire_nlilii_dataout;
	wire	wire_nlilil_dataout;
	wire	wire_nlill_dataout;
	wire	wire_nlilli_dataout;
	wire	wire_nlilll_dataout;
	wire	wire_nlillO_dataout;
	wire	wire_nlilO_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nliOi_dataout;
	wire	wire_nliOll_dataout;
	wire	wire_nliOO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nll0i_dataout;
	wire	wire_nll0l_dataout;
	wire	wire_nll0O_dataout;
	wire	wire_nll11i_dataout;
	wire	wire_nll1i_dataout;
	wire	wire_nll1l_dataout;
	wire	wire_nll1O_dataout;
	wire	wire_nll1Oi_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nllii_dataout;
	wire	wire_nllil_dataout;
	wire	wire_nlliO_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nlllil_dataout;
	wire	wire_nllliO_dataout;
	wire	wire_nlllli_dataout;
	wire	wire_nlllll_dataout;
	wire	wire_nllllO_dataout;
	wire	wire_nlllOi_dataout;
	wire	wire_nlllOl_dataout;
	wire	wire_nlllOO_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nllO0i_dataout;
	wire	wire_nllO0l_dataout;
	wire	wire_nllO0O_dataout;
	wire	wire_nllO1i_dataout;
	wire	wire_nllO1l_dataout;
	wire	wire_nllO1O_dataout;
	wire	wire_nllOii_dataout;
	wire	wire_nllOil_dataout;
	wire	wire_nllOiO_dataout;
	wire	wire_nllOli_dataout;
	wire	wire_nllOll_dataout;
	wire	wire_nllOlO_dataout;
	wire	wire_nllOOi_dataout;
	wire	wire_nllOOl_dataout;
	wire	wire_nllOOO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlO00i_dataout;
	wire	wire_nlO00l_dataout;
	wire	wire_nlO00O_dataout;
	wire	wire_nlO01i_dataout;
	wire	wire_nlO01l_dataout;
	wire	wire_nlO01O_dataout;
	wire	wire_nlO0ii_dataout;
	wire	wire_nlO0il_dataout;
	wire	wire_nlO0iO_dataout;
	wire	wire_nlO0li_dataout;
	wire	wire_nlO0ll_dataout;
	wire	wire_nlO0lO_dataout;
	wire	wire_nlO0Oi_dataout;
	wire	wire_nlO0Ol_dataout;
	wire	wire_nlO0OO_dataout;
	wire	wire_nlO10i_dataout;
	wire	wire_nlO10l_dataout;
	wire	wire_nlO10O_dataout;
	wire	wire_nlO11i_dataout;
	wire	wire_nlO11l_dataout;
	wire	wire_nlO11O_dataout;
	wire	wire_nlO1ii_dataout;
	wire	wire_nlO1il_dataout;
	wire	wire_nlO1iO_dataout;
	wire	wire_nlO1li_dataout;
	wire	wire_nlO1ll_dataout;
	wire	wire_nlO1lO_dataout;
	wire	wire_nlO1Oi_dataout;
	wire	wire_nlO1Ol_dataout;
	wire	wire_nlO1OO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOi0i_dataout;
	wire	wire_nlOi0O_dataout;
	wire	wire_nlOi1i_dataout;
	wire	wire_nlOi1l_dataout;
	wire	wire_nlOi1O_dataout;
	wire	wire_nlOiii_dataout;
	wire	wire_nlOiil_dataout;
	wire	wire_nlOiiO_dataout;
	wire	wire_nlOili_dataout;
	wire	wire_nlOill_dataout;
	wire	wire_nlOilO_dataout;
	wire	wire_nlOiOi_dataout;
	wire	wire_nlOiOl_dataout;
	wire	wire_nlOiOO_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOl0i_dataout;
	wire	wire_nlOl0l_dataout;
	wire	wire_nlOl0O_dataout;
	wire	wire_nlOl1i_dataout;
	wire	wire_nlOl1l_dataout;
	wire	wire_nlOl1O_dataout;
	wire	wire_nlOlii_dataout;
	wire	wire_nlOlil_dataout;
	wire	wire_nlOliO_dataout;
	wire	wire_nlOlli_dataout;
	wire	wire_nlOlll_dataout;
	wire	wire_nlOllO_dataout;
	wire	wire_nlOlOi_dataout;
	wire	wire_nlOlOl_dataout;
	wire	wire_nlOlOO_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOO0i_dataout;
	wire	wire_nlOO0l_dataout;
	wire	wire_nlOO0O_dataout;
	wire	wire_nlOO1i_dataout;
	wire	wire_nlOO1l_dataout;
	wire	wire_nlOO1O_dataout;
	wire  [8:0]   wire_n00Oi_o;
	wire  [3:0]   wire_n01iO_o;
	wire  [2:0]   wire_n1lOi_o;
	wire  [5:0]   wire_n1Oll_o;
	wire  [2:0]   wire_n1OOO_o;
	wire  [6:0]   wire_nli0ll_o;
	wire  [6:0]   wire_nli0lO_o;
	wire  [7:0]   wire_nli0Oi_o;
	wire  [2:0]   wire_nliOl_o;
	wire  [4:0]   wire_nllli_o;
	wire  wire_n0iii_o;
	wire  wire_n0iil_o;
	wire  wire_n0iiO_o;
	wire  wire_n0ilO_o;
	wire  wire_n0iOl_o;
	wire  wire_n0l1i_o;
	wire  wire_n0l1O_o;
	wire  wire_n0lii_o;
	wire  wire_n0lil_o;
	wire  wire_n0liO_o;
	wire  wire_n0lli_o;
	wire  wire_n0lOl_o;
	wire  wire_n0O0l_o;
	wire  wire_n0O1l_o;
	wire  wire_n0Oil_o;
	wire  wire_n0Oll_o;
	wire  wire_n0OOl_o;
	wire  wire_ni00l_o;
	wire  wire_ni01i_o;
	wire  wire_ni01O_o;
	wire  wire_ni0ii_o;
	wire  wire_ni0iO_o;
	wire  wire_ni0ll_o;
	wire  wire_ni0Oi_o;
	wire  wire_ni10i_o;
	wire  wire_ni11l_o;
	wire  wire_ni1Ol_o;
	wire  wire_nil00l_o;
	wire  wire_nil01O_o;
	wire  wire_nil0il_o;
	wire  wire_nil0li_o;
	wire  wire_nil0Oi_o;
	wire  wire_nil1li_o;
	wire  wire_nil1lO_o;
	wire  wire_nil1OO_o;
	wire  wire_nili0i_o;
	wire  wire_nili0O_o;
	wire  wire_nili1i_o;
	wire  wire_niliil_o;
	wire  wire_nilili_o;
	wire  wire_nililO_o;
	wire  wire_niliOl_o;
	wire  wire_nill0O_o;
	wire  wire_nill1i_o;
	wire  wire_nill1O_o;
	wire  wire_nillil_o;
	wire  wire_nillli_o;
	wire  wire_nilllO_o;
	wire  wire_nillOl_o;
	wire  wire_nilO0l_o;
	wire  wire_nilO1i_o;
	wire  wire_nilO1O_o;
	wire  wire_nilOii_o;
	wire  wire_nilOiO_o;
	wire  wire_nilOli_o;
	wire  wire_nilOlO_o;
	wire  wire_nilOOl_o;
	wire  wire_niO11i_o;
	wire  wire_nlilOi_o;
	wire  wire_nliO0l_o;
	wire  wire_nliO1i_o;
	wire  wire_nliO1O_o;
	wire  wire_nliOii_o;
	wire  wire_nliOli_o;
	wire  wire_nliOlO_o;
	wire  wire_nliOOi_o;
	wire  wire_nliOOl_o;
	wire  wire_nll00O_o;
	wire  wire_nll01i_o;
	wire  wire_nll01O_o;
	wire  wire_nll0iO_o;
	wire  wire_nll0lO_o;
	wire  wire_nll0OO_o;
	wire  wire_nll10i_o;
	wire  wire_nll10O_o;
	wire  wire_nll11l_o;
	wire  wire_nll1il_o;
	wire  wire_nll1ll_o;
	wire  wire_nll1Ol_o;
	wire  wire_nlli0i_o;
	wire  wire_nlliil_o;
	wire  wire_nllili_o;
	wire  wire_nllilO_o;
	wire  wire_nlliOi_o;
	wire  wire_nlliOO_o;
	wire  wire_nlll0i_o;
	wire  wire_nlll0O_o;
	wire  wire_nlll1l_o;
	wire  ni000i;
	wire  ni000l;
	wire  ni000O;
	wire  ni001i;
	wire  ni001O;
	wire  ni00ii;
	wire  ni00il;
	wire  ni00iO;
	wire  ni00li;
	wire  ni00ll;
	wire  ni00lO;
	wire  ni00Oi;
	wire  ni00Ol;
	wire  ni00OO;
	wire  ni010i;
	wire  ni010l;
	wire  ni010O;
	wire  ni011i;
	wire  ni011l;
	wire  ni011O;
	wire  ni01ii;
	wire  ni01il;
	wire  ni01iO;
	wire  ni01li;
	wire  ni01ll;
	wire  ni01lO;
	wire  ni01Oi;
	wire  ni01Ol;
	wire  ni01OO;
	wire  ni0i0i;
	wire  ni0i0l;
	wire  ni0i0O;
	wire  ni0i1i;
	wire  ni0i1l;
	wire  ni0i1O;
	wire  ni0iii;
	wire  ni0iil;
	wire  ni0iiO;
	wire  ni0ili;
	wire  ni0ill;
	wire  ni0ilO;
	wire  ni0iOi;
	wire  ni0iOl;
	wire  ni0iOO;
	wire  ni0l0i;
	wire  ni0l0l;
	wire  ni0l0O;
	wire  ni0l1i;
	wire  ni0l1l;
	wire  ni0l1O;
	wire  ni0lii;
	wire  ni0lil;
	wire  ni0liO;
	wire  ni0lli;
	wire  ni0lll;
	wire  ni0llO;
	wire  ni0lOi;
	wire  ni0lOl;
	wire  ni0lOO;
	wire  ni0O0i;
	wire  ni0O0l;
	wire  ni0O0O;
	wire  ni0O1i;
	wire  ni0O1l;
	wire  ni0O1O;
	wire  ni0Oii;
	wire  ni0Oil;
	wire  ni0OiO;
	wire  ni0Oli;
	wire  ni0Oll;
	wire  ni0OlO;
	wire  ni0OOi;
	wire  ni0OOl;
	wire  ni0OOO;
	wire  ni1lll;
	wire  ni1llO;
	wire  ni1lOi;
	wire  ni1lOl;
	wire  ni1lOO;
	wire  ni1O0i;
	wire  ni1O0l;
	wire  ni1O0O;
	wire  ni1O1i;
	wire  ni1O1l;
	wire  ni1O1O;
	wire  ni1Oii;
	wire  ni1Oil;
	wire  ni1OiO;
	wire  ni1Oli;
	wire  ni1Oll;
	wire  ni1OlO;
	wire  ni1OOi;
	wire  ni1OOl;
	wire  ni1OOO;
	wire  nii00l;
	wire  nii01i;
	wire  nii01l;
	wire  nii0ii;
	wire  nii0ll;
	wire  nii0Ol;
	wire  nii10i;
	wire  nii10l;
	wire  nii10O;
	wire  nii11i;
	wire  nii11l;
	wire  nii11O;
	wire  nii1ii;
	wire  nii1il;
	wire  nii1iO;
	wire  nii1li;
	wire  nii1ll;
	wire  nii1lO;
	wire  nii1Oi;
	wire  nii1Ol;
	wire  niii0l;
	wire  niiiil;
	wire  niiiiO;
	wire  niiili;
	wire  niiill;
	wire  niiilO;
	wire  niiiOi;
	wire  niiiOl;
	wire  niiiOO;
	wire  niil0i;
	wire  niil0l;
	wire  niil0O;
	wire  niil1i;
	wire  niil1l;
	wire  niil1O;
	wire  niilii;
	wire  niilil;
	wire  niiliO;
	wire  niilli;
	wire  niilll;
	wire  niilOl;
	wire  niiOil;
	wire  niiOiO;
	wire  niiOli;
	wire  niiOOi;

	initial
		ni001l45 = 0;
	always @ ( posedge tx_clk)
		  ni001l45 <= ni001l46;
	event ni001l45_event;
	initial
		#1 ->ni001l45_event;
	always @(ni001l45_event)
		ni001l45 <= {1{1'b1}};
	initial
		ni001l46 = 0;
	always @ ( posedge tx_clk)
		  ni001l46 <= ni001l45;
	initial
		nii00O39 = 0;
	always @ ( posedge tx_clk)
		  nii00O39 <= nii00O40;
	event nii00O39_event;
	initial
		#1 ->nii00O39_event;
	always @(nii00O39_event)
		nii00O39 <= {1{1'b1}};
	initial
		nii00O40 = 0;
	always @ ( posedge tx_clk)
		  nii00O40 <= nii00O39;
	initial
		nii01O41 = 0;
	always @ ( posedge tx_clk)
		  nii01O41 <= nii01O42;
	event nii01O41_event;
	initial
		#1 ->nii01O41_event;
	always @(nii01O41_event)
		nii01O41 <= {1{1'b1}};
	initial
		nii01O42 = 0;
	always @ ( posedge tx_clk)
		  nii01O42 <= nii01O41;
	initial
		nii0il37 = 0;
	always @ ( posedge tx_clk)
		  nii0il37 <= nii0il38;
	event nii0il37_event;
	initial
		#1 ->nii0il37_event;
	always @(nii0il37_event)
		nii0il37 <= {1{1'b1}};
	initial
		nii0il38 = 0;
	always @ ( posedge tx_clk)
		  nii0il38 <= nii0il37;
	initial
		nii0li35 = 0;
	always @ ( posedge tx_clk)
		  nii0li35 <= nii0li36;
	event nii0li35_event;
	initial
		#1 ->nii0li35_event;
	always @(nii0li35_event)
		nii0li35 <= {1{1'b1}};
	initial
		nii0li36 = 0;
	always @ ( posedge tx_clk)
		  nii0li36 <= nii0li35;
	initial
		nii0lO33 = 0;
	always @ ( posedge tx_clk)
		  nii0lO33 <= nii0lO34;
	event nii0lO33_event;
	initial
		#1 ->nii0lO33_event;
	always @(nii0lO33_event)
		nii0lO33 <= {1{1'b1}};
	initial
		nii0lO34 = 0;
	always @ ( posedge tx_clk)
		  nii0lO34 <= nii0lO33;
	initial
		nii0OO31 = 0;
	always @ ( posedge tx_clk)
		  nii0OO31 <= nii0OO32;
	event nii0OO31_event;
	initial
		#1 ->nii0OO31_event;
	always @(nii0OO31_event)
		nii0OO31 <= {1{1'b1}};
	initial
		nii0OO32 = 0;
	always @ ( posedge tx_clk)
		  nii0OO32 <= nii0OO31;
	initial
		nii1OO43 = 0;
	always @ ( posedge tx_clk)
		  nii1OO43 <= nii1OO44;
	event nii1OO43_event;
	initial
		#1 ->nii1OO43_event;
	always @(nii1OO43_event)
		nii1OO43 <= {1{1'b1}};
	initial
		nii1OO44 = 0;
	always @ ( posedge tx_clk)
		  nii1OO44 <= nii1OO43;
	initial
		niii0i23 = 0;
	always @ ( posedge tx_clk)
		  niii0i23 <= niii0i24;
	event niii0i23_event;
	initial
		#1 ->niii0i23_event;
	always @(niii0i23_event)
		niii0i23 <= {1{1'b1}};
	initial
		niii0i24 = 0;
	always @ ( posedge tx_clk)
		  niii0i24 <= niii0i23;
	initial
		niii0O21 = 0;
	always @ ( posedge tx_clk)
		  niii0O21 <= niii0O22;
	event niii0O21_event;
	initial
		#1 ->niii0O21_event;
	always @(niii0O21_event)
		niii0O21 <= {1{1'b1}};
	initial
		niii0O22 = 0;
	always @ ( posedge tx_clk)
		  niii0O22 <= niii0O21;
	initial
		niii1i29 = 0;
	always @ ( posedge tx_clk)
		  niii1i29 <= niii1i30;
	event niii1i29_event;
	initial
		#1 ->niii1i29_event;
	always @(niii1i29_event)
		niii1i29 <= {1{1'b1}};
	initial
		niii1i30 = 0;
	always @ ( posedge tx_clk)
		  niii1i30 <= niii1i29;
	initial
		niii1l27 = 0;
	always @ ( posedge tx_clk)
		  niii1l27 <= niii1l28;
	event niii1l27_event;
	initial
		#1 ->niii1l27_event;
	always @(niii1l27_event)
		niii1l27 <= {1{1'b1}};
	initial
		niii1l28 = 0;
	always @ ( posedge tx_clk)
		  niii1l28 <= niii1l27;
	initial
		niii1O25 = 0;
	always @ ( posedge tx_clk)
		  niii1O25 <= niii1O26;
	event niii1O25_event;
	initial
		#1 ->niii1O25_event;
	always @(niii1O25_event)
		niii1O25 <= {1{1'b1}};
	initial
		niii1O26 = 0;
	always @ ( posedge tx_clk)
		  niii1O26 <= niii1O25;
	initial
		niillO19 = 0;
	always @ ( posedge tx_clk)
		  niillO19 <= niillO20;
	event niillO19_event;
	initial
		#1 ->niillO19_event;
	always @(niillO19_event)
		niillO19 <= {1{1'b1}};
	initial
		niillO20 = 0;
	always @ ( posedge tx_clk)
		  niillO20 <= niillO19;
	initial
		niilOi17 = 0;
	always @ ( posedge tx_clk)
		  niilOi17 <= niilOi18;
	event niilOi17_event;
	initial
		#1 ->niilOi17_event;
	always @(niilOi17_event)
		niilOi17 <= {1{1'b1}};
	initial
		niilOi18 = 0;
	always @ ( posedge tx_clk)
		  niilOi18 <= niilOi17;
	initial
		niilOO15 = 0;
	always @ ( posedge tx_clk)
		  niilOO15 <= niilOO16;
	event niilOO15_event;
	initial
		#1 ->niilOO15_event;
	always @(niilOO15_event)
		niilOO15 <= {1{1'b1}};
	initial
		niilOO16 = 0;
	always @ ( posedge tx_clk)
		  niilOO16 <= niilOO15;
	initial
		niiO0i10 = 0;
	always @ ( posedge tx_clk)
		  niiO0i10 <= niiO0i9;
	initial
		niiO0i9 = 0;
	always @ ( posedge tx_clk)
		  niiO0i9 <= niiO0i10;
	event niiO0i9_event;
	initial
		#1 ->niiO0i9_event;
	always @(niiO0i9_event)
		niiO0i9 <= {1{1'b1}};
	initial
		niiO0O7 = 0;
	always @ ( posedge tx_clk)
		  niiO0O7 <= niiO0O8;
	event niiO0O7_event;
	initial
		#1 ->niiO0O7_event;
	always @(niiO0O7_event)
		niiO0O7 <= {1{1'b1}};
	initial
		niiO0O8 = 0;
	always @ ( posedge tx_clk)
		  niiO0O8 <= niiO0O7;
	initial
		niiO1i13 = 0;
	always @ ( posedge tx_clk)
		  niiO1i13 <= niiO1i14;
	event niiO1i13_event;
	initial
		#1 ->niiO1i13_event;
	always @(niiO1i13_event)
		niiO1i13 <= {1{1'b1}};
	initial
		niiO1i14 = 0;
	always @ ( posedge tx_clk)
		  niiO1i14 <= niiO1i13;
	initial
		niiO1l11 = 0;
	always @ ( posedge tx_clk)
		  niiO1l11 <= niiO1l12;
	event niiO1l11_event;
	initial
		#1 ->niiO1l11_event;
	always @(niiO1l11_event)
		niiO1l11 <= {1{1'b1}};
	initial
		niiO1l12 = 0;
	always @ ( posedge tx_clk)
		  niiO1l12 <= niiO1l11;
	initial
		niiOll5 = 0;
	always @ ( posedge tx_clk)
		  niiOll5 <= niiOll6;
	event niiOll5_event;
	initial
		#1 ->niiOll5_event;
	always @(niiOll5_event)
		niiOll5 <= {1{1'b1}};
	initial
		niiOll6 = 0;
	always @ ( posedge tx_clk)
		  niiOll6 <= niiOll5;
	initial
		niiOOl3 = 0;
	always @ ( posedge tx_clk)
		  niiOOl3 <= niiOOl4;
	event niiOOl3_event;
	initial
		#1 ->niiOOl3_event;
	always @(niiOOl3_event)
		niiOOl3 <= {1{1'b1}};
	initial
		niiOOl4 = 0;
	always @ ( posedge tx_clk)
		  niiOOl4 <= niiOOl3;
	initial
		nil11i1 = 0;
	always @ ( posedge tx_clk)
		  nil11i1 <= nil11i2;
	event nil11i1_event;
	initial
		#1 ->nil11i1_event;
	always @(nil11i1_event)
		nil11i1 <= {1{1'b1}};
	initial
		nil11i2 = 0;
	always @ ( posedge tx_clk)
		  nil11i2 <= nil11i1;
	initial
	begin
		n100i = 0;
		n100l = 0;
		n100O = 0;
		n101i = 0;
		n101l = 0;
		n101O = 0;
		n10ii = 0;
		n10il = 0;
		n10iO = 0;
		n10li = 0;
		n10ll = 0;
		n10lO = 0;
		n10Oi = 0;
		n10Ol = 0;
		n10OO = 0;
		n110i = 0;
		n110l = 0;
		n110O = 0;
		n111i = 0;
		n111l = 0;
		n111O = 0;
		n11ii = 0;
		n11il = 0;
		n11iO = 0;
		n11li = 0;
		n11ll = 0;
		n11lO = 0;
		n11Oi = 0;
		n11Ol = 0;
		n11OO = 0;
		n1i0i = 0;
		n1i0l = 0;
		n1i0O = 0;
		n1i1i = 0;
		n1i1l = 0;
		n1i1O = 0;
		n1iii = 0;
		n1iil = 0;
		n1iiO = 0;
		n1ili = 0;
		n1ill = 0;
		n1ilO = 0;
		n1iOi = 0;
		n1iOl = 0;
		n1iOO = 0;
		n1l0i = 0;
		n1l0l = 0;
		n1l1i = 0;
		n1l1l = 0;
		n1l1O = 0;
		n1lii = 0;
		nliliO = 0;
		nlOOil = 0;
		nlOOiO = 0;
		nlOOli = 0;
		nlOOll = 0;
		nlOOlO = 0;
		nlOOOi = 0;
		nlOOOl = 0;
		nlOOOO = 0;
	end
	always @ ( posedge tx_clk or  posedge soft_reset)
	begin
		if (soft_reset == 1'b1) 
		begin
			n100i <= 0;
			n100l <= 0;
			n100O <= 0;
			n101i <= 0;
			n101l <= 0;
			n101O <= 0;
			n10ii <= 0;
			n10il <= 0;
			n10iO <= 0;
			n10li <= 0;
			n10ll <= 0;
			n10lO <= 0;
			n10Oi <= 0;
			n10Ol <= 0;
			n10OO <= 0;
			n110i <= 0;
			n110l <= 0;
			n110O <= 0;
			n111i <= 0;
			n111l <= 0;
			n111O <= 0;
			n11ii <= 0;
			n11il <= 0;
			n11iO <= 0;
			n11li <= 0;
			n11ll <= 0;
			n11lO <= 0;
			n11Oi <= 0;
			n11Ol <= 0;
			n11OO <= 0;
			n1i0i <= 0;
			n1i0l <= 0;
			n1i0O <= 0;
			n1i1i <= 0;
			n1i1l <= 0;
			n1i1O <= 0;
			n1iii <= 0;
			n1iil <= 0;
			n1iiO <= 0;
			n1ili <= 0;
			n1ill <= 0;
			n1ilO <= 0;
			n1iOi <= 0;
			n1iOl <= 0;
			n1iOO <= 0;
			n1l0i <= 0;
			n1l0l <= 0;
			n1l1i <= 0;
			n1l1l <= 0;
			n1l1O <= 0;
			n1lii <= 0;
			nliliO <= 0;
			nlOOil <= 0;
			nlOOiO <= 0;
			nlOOli <= 0;
			nlOOll <= 0;
			nlOOlO <= 0;
			nlOOOi <= 0;
			nlOOOl <= 0;
			nlOOOO <= 0;
		end
		else if  (wire_nll_dataout == 1'b1) 
		begin
			n100i <= wire_nll01O_o;
			n100l <= wire_nll00O_o;
			n100O <= wire_nll0iO_o;
			n101i <= wire_n001O_dataout;
			n101l <= ni0OlO;
			n101O <= wire_nliO1i_o;
			n10ii <= wire_nll0lO_o;
			n10il <= wire_nll0OO_o;
			n10iO <= (~ ni0OOi);
			n10li <= wire_nlli0i_o;
			n10ll <= (~ ni0OOl);
			n10lO <= wire_nlliil_o;
			n10Oi <= wire_nllili_o;
			n10Ol <= wire_nllilO_o;
			n10OO <= wire_nlliOi_o;
			n110i <= wire_n011i_dataout;
			n110l <= wire_n011l_dataout;
			n110O <= wire_n011O_dataout;
			n111i <= wire_n1OlO_dataout;
			n111l <= wire_n1OOi_dataout;
			n111O <= wire_n1OOl_dataout;
			n11ii <= wire_n010i_dataout;
			n11il <= wire_n01li_dataout;
			n11iO <= wire_n01ll_dataout;
			n11li <= wire_n01lO_dataout;
			n11ll <= wire_n01Oi_dataout;
			n11lO <= wire_n01Ol_dataout;
			n11Oi <= wire_n01OO_dataout;
			n11Ol <= wire_n001i_dataout;
			n11OO <= wire_n001l_dataout;
			n1i0i <= wire_nlll0O_o;
			n1i0l <= wire_nliO1O_o;
			n1i0O <= wire_nliO0l_o;
			n1i1i <= wire_nlliOO_o;
			n1i1l <= wire_nlll1l_o;
			n1i1O <= wire_nlll0i_o;
			n1iii <= wire_nliOii_o;
			n1iil <= wire_nliOli_o;
			n1iiO <= wire_nliOll_dataout;
			n1ili <= wire_nliOlO_o;
			n1ill <= wire_nliOOi_o;
			n1ilO <= wire_nliOOl_o;
			n1iOi <= wire_nll11i_dataout;
			n1iOl <= wire_nll11l_o;
			n1iOO <= wire_nll10i_o;
			n1l0i <= wire_nll1Oi_dataout;
			n1l0l <= wire_nll1Ol_o;
			n1l1i <= wire_nll10O_o;
			n1l1l <= wire_nll1il_o;
			n1l1O <= wire_nll1ll_o;
			n1lii <= wire_nll01i_o;
			nliliO <= wire_n1lli_dataout;
			nlOOil <= wire_n1lll_dataout;
			nlOOiO <= wire_n1llO_dataout;
			nlOOli <= wire_n1lOl_dataout;
			nlOOll <= wire_n1lOO_dataout;
			nlOOlO <= wire_n1O1i_dataout;
			nlOOOi <= wire_n1O1l_dataout;
			nlOOOl <= wire_n1O1O_dataout;
			nlOOOO <= wire_n1O0i_dataout;
		end
	end
	initial
	begin
		n1liO = 0;
	end
	always @ ( posedge tx_clk or  posedge soft_reset)
	begin
		if (soft_reset == 1'b1) 
		begin
			n1liO <= 1;
		end
		else if  (wire_nll_dataout == 1'b1) 
		begin
			n1liO <= niilOl;
		end
	end
	initial
	begin
		nl00il = 0;
		nl00iO = 0;
		nl00li = 0;
		nl00ll = 0;
		nl00lO = 0;
		nl00Oi = 0;
		nl00Ol = 0;
		nl00OO = 0;
		nl0i0i = 0;
		nl0i0l = 0;
		nl0i0O = 0;
		nl0i1i = 0;
		nl0i1l = 0;
		nl0i1O = 0;
		nl0iii = 0;
		nl0iil = 0;
		nl0iiO = 0;
		nl0ili = 0;
		nl0ill = 0;
		nl0ilO = 0;
		nl0iOi = 0;
		nl0iOl = 0;
		nl0iOO = 0;
		nl0l0i = 0;
		nl0l0l = 0;
		nl0l0O = 0;
		nl0l1i = 0;
		nl0l1l = 0;
		nl0l1O = 0;
		nl0lii = 0;
		nl0lil = 0;
		nl0liO = 0;
		nl0lli = 0;
		nl0lll = 0;
		nl0llO = 0;
		nl0lOi = 0;
		nl0lOl = 0;
		nl0lOO = 0;
		nl0O0i = 0;
		nl0O0l = 0;
		nl0O0O = 0;
		nl0O1i = 0;
		nl0O1l = 0;
		nl0O1O = 0;
		nl0Oii = 0;
		nl0Oil = 0;
		nl0OiO = 0;
		nl0Oli = 0;
		nl0Oll = 0;
		nl0OlO = 0;
		nl0OOi = 0;
		nl0OOl = 0;
		nli11i = 0;
	end
	always @ (tx_clk or wire_nl0OOO_PRN or soft_reset)
	begin
		if (wire_nl0OOO_PRN == 1'b0) 
		begin
			nl00il <= 1;
			nl00iO <= 1;
			nl00li <= 1;
			nl00ll <= 1;
			nl00lO <= 1;
			nl00Oi <= 1;
			nl00Ol <= 1;
			nl00OO <= 1;
			nl0i0i <= 1;
			nl0i0l <= 1;
			nl0i0O <= 1;
			nl0i1i <= 1;
			nl0i1l <= 1;
			nl0i1O <= 1;
			nl0iii <= 1;
			nl0iil <= 1;
			nl0iiO <= 1;
			nl0ili <= 1;
			nl0ill <= 1;
			nl0ilO <= 1;
			nl0iOi <= 1;
			nl0iOl <= 1;
			nl0iOO <= 1;
			nl0l0i <= 1;
			nl0l0l <= 1;
			nl0l0O <= 1;
			nl0l1i <= 1;
			nl0l1l <= 1;
			nl0l1O <= 1;
			nl0lii <= 1;
			nl0lil <= 1;
			nl0liO <= 1;
			nl0lli <= 1;
			nl0lll <= 1;
			nl0llO <= 1;
			nl0lOi <= 1;
			nl0lOl <= 1;
			nl0lOO <= 1;
			nl0O0i <= 1;
			nl0O0l <= 1;
			nl0O0O <= 1;
			nl0O1i <= 1;
			nl0O1l <= 1;
			nl0O1O <= 1;
			nl0Oii <= 1;
			nl0Oil <= 1;
			nl0OiO <= 1;
			nl0Oli <= 1;
			nl0Oll <= 1;
			nl0OlO <= 1;
			nl0OOi <= 1;
			nl0OOl <= 1;
			nli11i <= 1;
		end
		else if  (soft_reset == 1'b1) 
		begin
			nl00il <= 0;
			nl00iO <= 0;
			nl00li <= 0;
			nl00ll <= 0;
			nl00lO <= 0;
			nl00Oi <= 0;
			nl00Ol <= 0;
			nl00OO <= 0;
			nl0i0i <= 0;
			nl0i0l <= 0;
			nl0i0O <= 0;
			nl0i1i <= 0;
			nl0i1l <= 0;
			nl0i1O <= 0;
			nl0iii <= 0;
			nl0iil <= 0;
			nl0iiO <= 0;
			nl0ili <= 0;
			nl0ill <= 0;
			nl0ilO <= 0;
			nl0iOi <= 0;
			nl0iOl <= 0;
			nl0iOO <= 0;
			nl0l0i <= 0;
			nl0l0l <= 0;
			nl0l0O <= 0;
			nl0l1i <= 0;
			nl0l1l <= 0;
			nl0l1O <= 0;
			nl0lii <= 0;
			nl0lil <= 0;
			nl0liO <= 0;
			nl0lli <= 0;
			nl0lll <= 0;
			nl0llO <= 0;
			nl0lOi <= 0;
			nl0lOl <= 0;
			nl0lOO <= 0;
			nl0O0i <= 0;
			nl0O0l <= 0;
			nl0O0O <= 0;
			nl0O1i <= 0;
			nl0O1l <= 0;
			nl0O1O <= 0;
			nl0Oii <= 0;
			nl0Oil <= 0;
			nl0OiO <= 0;
			nl0Oli <= 0;
			nl0Oll <= 0;
			nl0OlO <= 0;
			nl0OOi <= 0;
			nl0OOl <= 0;
			nli11i <= 0;
		end
		else 
		if (tx_clk != nl0OOO_clk_prev && tx_clk == 1'b1) 
		begin
			nl00il <= wire_nli10i_dataout;
			nl00iO <= wire_nli10l_dataout;
			nl00li <= wire_nli10O_dataout;
			nl00ll <= wire_nli1ii_dataout;
			nl00lO <= wire_nli1il_dataout;
			nl00Oi <= wire_nli1iO_dataout;
			nl00Ol <= wire_nli1li_dataout;
			nl00OO <= wire_nli1ll_dataout;
			nl0i0i <= wire_nli1OO_dataout;
			nl0i0l <= wire_nli01i_dataout;
			nl0i0O <= wire_nli01l_dataout;
			nl0i1i <= wire_nli1lO_dataout;
			nl0i1l <= wire_nli1Oi_dataout;
			nl0i1O <= wire_nli1Ol_dataout;
			nl0iii <= wire_nli01O_dataout;
			nl0iil <= wire_nli00i_dataout;
			nl0iiO <= wire_nli00l_dataout;
			nl0ili <= wire_nli00O_dataout;
			nl0ill <= wire_nli0ii_dataout;
			nl0ilO <= wire_nli0il_dataout;
			nl0iOi <= wire_nli0iO_dataout;
			nl0iOl <= wire_nli0li_dataout;
			nl0iOO <= (~ (nli11O | nl0OOi));
			nl0l0i <= wire_nil01O_o;
			nl0l0l <= wire_nil00l_o;
			nl0l0O <= wire_nil0il_o;
			nl0l1i <= wire_nil1li_o;
			nl0l1l <= wire_nil1lO_o;
			nl0l1O <= wire_nil1OO_o;
			nl0lii <= wire_nil0li_o;
			nl0lil <= wire_nil0Oi_o;
			nl0liO <= wire_nili1i_o;
			nl0lli <= wire_nili0i_o;
			nl0lll <= wire_nili0O_o;
			nl0llO <= wire_niliil_o;
			nl0lOi <= wire_nilili_o;
			nl0lOl <= wire_nililO_o;
			nl0lOO <= wire_niliOl_o;
			nl0O0i <= wire_nillil_o;
			nl0O0l <= wire_nillli_o;
			nl0O0O <= wire_nilllO_o;
			nl0O1i <= wire_nill1i_o;
			nl0O1l <= wire_nill1O_o;
			nl0O1O <= wire_nill0O_o;
			nl0Oii <= wire_nillOl_o;
			nl0Oil <= wire_nilO1i_o;
			nl0OiO <= wire_nilO1O_o;
			nl0Oli <= wire_nilO0l_o;
			nl0Oll <= wire_nilOii_o;
			nl0OlO <= wire_nilOiO_o;
			nl0OOi <= wire_nilOli_o;
			nl0OOl <= wire_nilOlO_o;
			nli11i <= wire_nilOOl_o;
		end
		nl0OOO_clk_prev <= tx_clk;
	end
	assign
		wire_nl0OOO_PRN = (ni001l46 ^ ni001l45);
	initial
	begin
		nli11O = 0;
	end
	always @ ( posedge tx_clk or  posedge soft_reset)
	begin
		if (soft_reset == 1'b1) 
		begin
			nli11O <= 1;
		end
		else 
		begin
			nli11O <= wire_niO11i_o;
		end
	end
	initial
	begin
		n0lOi = 0;
		niO0l = 0;
		niO0O = 0;
		niOii = 0;
		niOil = 0;
		niOiO = 0;
		niOli = 0;
		niOll = 0;
		niOlO = 0;
		niOOi = 0;
		niOOl = 0;
		niOOO = 0;
		nl00i = 0;
		nl00l = 0;
		nl00O = 0;
		nl01i = 0;
		nl01l = 0;
		nl01O = 0;
		nl0ii = 0;
		nl0il = 0;
		nl0iO = 0;
		nl0li = 0;
		nl0ll = 0;
		nl0lO = 0;
		nl0Oi = 0;
		nl0Ol = 0;
		nl0OO = 0;
		nl10i = 0;
		nl10l = 0;
		nl10O = 0;
		nl11i = 0;
		nl11l = 0;
		nl11O = 0;
		nl1ii = 0;
		nl1il = 0;
		nl1iO = 0;
		nl1li = 0;
		nl1ll = 0;
		nl1lO = 0;
		nl1Oi = 0;
		nl1Ol = 0;
		nl1OO = 0;
		nli0i = 0;
		nli0l = 0;
		nli0O = 0;
		nli1i = 0;
		nli1l = 0;
		nli1O = 0;
		nliil = 0;
	end
	always @ ( posedge tx_clk or  posedge soft_reset)
	begin
		if (soft_reset == 1'b1) 
		begin
			n0lOi <= 0;
			niO0l <= 0;
			niO0O <= 0;
			niOii <= 0;
			niOil <= 0;
			niOiO <= 0;
			niOli <= 0;
			niOll <= 0;
			niOlO <= 0;
			niOOi <= 0;
			niOOl <= 0;
			niOOO <= 0;
			nl00i <= 0;
			nl00l <= 0;
			nl00O <= 0;
			nl01i <= 0;
			nl01l <= 0;
			nl01O <= 0;
			nl0ii <= 0;
			nl0il <= 0;
			nl0iO <= 0;
			nl0li <= 0;
			nl0ll <= 0;
			nl0lO <= 0;
			nl0Oi <= 0;
			nl0Ol <= 0;
			nl0OO <= 0;
			nl10i <= 0;
			nl10l <= 0;
			nl10O <= 0;
			nl11i <= 0;
			nl11l <= 0;
			nl11O <= 0;
			nl1ii <= 0;
			nl1il <= 0;
			nl1iO <= 0;
			nl1li <= 0;
			nl1ll <= 0;
			nl1lO <= 0;
			nl1Oi <= 0;
			nl1Ol <= 0;
			nl1OO <= 0;
			nli0i <= 0;
			nli0l <= 0;
			nli0O <= 0;
			nli1i <= 0;
			nli1l <= 0;
			nli1O <= 0;
			nliil <= 0;
		end
		else if  (wire_nli_dataout == 1'b1) 
		begin
			n0lOi <= wire_nlill_dataout;
			niO0l <= wire_nlilO_dataout;
			niO0O <= wire_nliOi_dataout;
			niOii <= wire_nliOO_dataout;
			niOil <= wire_nll1i_dataout;
			niOiO <= wire_nll1l_dataout;
			niOli <= wire_nll1O_dataout;
			niOll <= wire_nll0i_dataout;
			niOlO <= niil1l;
			niOOi <= wire_n0ilO_o;
			niOOl <= (~ niil1O);
			niOOO <= niil0i;
			nl00i <= wire_n0lii_o;
			nl00l <= wire_n0lil_o;
			nl00O <= wire_n0liO_o;
			nl01i <= wire_n0l1i_o;
			nl01l <= wire_n0l1O_o;
			nl01O <= wire_n0l0O_dataout;
			nl0ii <= wire_n0lli_o;
			nl0il <= wire_n0llO_dataout;
			nl0iO <= wire_n0lOl_o;
			nl0li <= wire_n0O1i_dataout;
			nl0ll <= wire_n0O1l_o;
			nl0lO <= wire_n0O0i_dataout;
			nl0Oi <= wire_n0O0l_o;
			nl0Ol <= wire_n0Oii_dataout;
			nl0OO <= wire_n0Oil_o;
			nl10i <= (~ niilil);
			nl10l <= (~ niiliO);
			nl10O <= niilli;
			nl11i <= (~ niil0l);
			nl11l <= (~ niil0O);
			nl11O <= (~ niilii);
			nl1ii <= wire_ni1Ol_o;
			nl1il <= wire_ni01i_o;
			nl1iO <= wire_ni01O_o;
			nl1li <= wire_ni00l_o;
			nl1ll <= wire_ni0ii_o;
			nl1lO <= wire_ni0iO_o;
			nl1Oi <= wire_ni0ll_o;
			nl1Ol <= wire_ni0Oi_o;
			nl1OO <= wire_n0iOl_o;
			nli0i <= wire_n0OOl_o;
			nli0l <= wire_ni11i_dataout;
			nli0O <= wire_ni11l_o;
			nli1i <= wire_n0Oli_dataout;
			nli1l <= wire_n0Oll_o;
			nli1O <= wire_n0OOi_dataout;
			nliil <= wire_ni10i_o;
		end
	end
	initial
	begin
		nlili = 0;
	end
	always @ (tx_clk or wire_nliiO_PRN or wire_nliiO_CLRN)
	begin
		if (wire_nliiO_PRN == 1'b0) 
		begin
			nlili <= 1;
		end
		else if  (wire_nliiO_CLRN == 1'b0) 
		begin
			nlili <= 0;
		end
		else if  (wire_nli_dataout == 1'b1) 
		if (tx_clk != nliiO_clk_prev && tx_clk == 1'b1) 
		begin
			nlili <= niilOl;
		end
		nliiO_clk_prev <= tx_clk;
	end
	assign
		wire_nliiO_CLRN = (niilOi18 ^ niilOi17),
		wire_nliiO_PRN = ((niillO20 ^ niillO19) & (~ soft_reset));
	assign		wire_n000i_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[0] : n11il;
	assign		wire_n000l_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[1] : n11iO;
	assign		wire_n000O_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[2] : n11li;
	and(wire_n001i_dataout, wire_n00li_dataout, ~(wire_nlillO_dataout));
	and(wire_n001l_dataout, wire_n00ll_dataout, ~(wire_nlillO_dataout));
	and(wire_n001O_dataout, wire_n00lO_dataout, ~(wire_nlillO_dataout));
	assign		wire_n00i_dataout = (niiOil === 1'b1) ? nl0l0l : wire_niii_dataout;
	assign		wire_n00ii_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[3] : n11ll;
	assign		wire_n00il_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[4] : n11lO;
	assign		wire_n00iO_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[5] : n11Oi;
	assign		wire_n00l_dataout = (niiOil === 1'b1) ? nl0l0O : wire_niil_dataout;
	assign		wire_n00li_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[6] : n11Ol;
	assign		wire_n00ll_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[7] : n11OO;
	assign		wire_n00lO_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[8] : n101i;
	assign		wire_n00O_dataout = (niiOil === 1'b1) ? nl0lii : wire_niiO_dataout;
	and(wire_n010i_dataout, wire_n01il_dataout, ~(wire_nlilll_dataout));
	assign		wire_n010l_dataout = (wire_nlilli_dataout === 1'b1) ? wire_n01iO_o[0] : n110i;
	assign		wire_n010O_dataout = (wire_nlilli_dataout === 1'b1) ? wire_n01iO_o[1] : n110l;
	and(wire_n011i_dataout, wire_n010l_dataout, ~(wire_nlilll_dataout));
	and(wire_n011l_dataout, wire_n010O_dataout, ~(wire_nlilll_dataout));
	and(wire_n011O_dataout, wire_n01ii_dataout, ~(wire_nlilll_dataout));
	assign		wire_n01i_dataout = (niiOil === 1'b1) ? nl0l1l : wire_ni0i_dataout;
	assign		wire_n01ii_dataout = (wire_nlilli_dataout === 1'b1) ? wire_n01iO_o[2] : n110O;
	assign		wire_n01il_dataout = (wire_nlilli_dataout === 1'b1) ? wire_n01iO_o[3] : n11ii;
	assign		wire_n01l_dataout = (niiOil === 1'b1) ? nl0l1O : wire_ni0l_dataout;
	and(wire_n01li_dataout, wire_n000i_dataout, ~(wire_nlillO_dataout));
	and(wire_n01ll_dataout, wire_n000l_dataout, ~(wire_nlillO_dataout));
	and(wire_n01lO_dataout, wire_n000O_dataout, ~(wire_nlillO_dataout));
	assign		wire_n01O_dataout = (niiOil === 1'b1) ? nl0l0i : wire_ni0O_dataout;
	and(wire_n01Oi_dataout, wire_n00ii_dataout, ~(wire_nlillO_dataout));
	and(wire_n01Ol_dataout, wire_n00il_dataout, ~(wire_nlillO_dataout));
	and(wire_n01OO_dataout, wire_n00iO_dataout, ~(wire_nlillO_dataout));
	and(wire_n0i_dataout, nl1ll, niiOli);
	assign		wire_n0ii_dataout = (niiOil === 1'b1) ? nl0lil : wire_nili_dataout;
	assign		wire_n0il_dataout = (niiOil === 1'b1) ? nl0liO : wire_nill_dataout;
	assign		wire_n0iO_dataout = (niiOil === 1'b1) ? nl0lli : wire_nilO_dataout;
	and(wire_n0l_dataout, nl1lO, niiOli);
	and(wire_n0l0O_dataout, (~ niiOOi), nl0ii);
	assign		wire_n0li_dataout = (niiOil === 1'b1) ? nl0lll : wire_niOi_dataout;
	assign		wire_n0ll_dataout = (niiOil === 1'b1) ? nl0llO : wire_niOl_dataout;
	and(wire_n0llO_dataout, (~ niiOOi), nl0iO);
	assign		wire_n0lO_dataout = (niiOil === 1'b1) ? nl0lOi : wire_niOO_dataout;
	and(wire_n0O_dataout, nl1Oi, niiOli);
	and(wire_n0O0i_dataout, (~ niiOOi), nl0Oi);
	and(wire_n0O1i_dataout, (~ niiOOi), nl0ll);
	assign		wire_n0Oi_dataout = (niiOil === 1'b1) ? nl0lOl : wire_nl1i_dataout;
	and(wire_n0Oii_dataout, (~ niiOOi), nl0OO);
	assign		wire_n0Ol_dataout = (niiOil === 1'b1) ? nl0lOO : wire_nl1l_dataout;
	and(wire_n0Oli_dataout, (~ niiOOi), nli1l);
	assign		wire_n0OO_dataout = (niiOil === 1'b1) ? nl0O1i : wire_nl1O_dataout;
	and(wire_n0OOi_dataout, (~ niiOOi), nli0i);
	and(wire_n1i_dataout, nl1il, niiOli);
	and(wire_n1l_dataout, nl1iO, niiOli);
	and(wire_n1lli_dataout, wire_n1lOi_o[0], wire_nlilOi_o);
	and(wire_n1lll_dataout, wire_n1lOi_o[1], wire_nlilOi_o);
	and(wire_n1llO_dataout, wire_n1lOi_o[2], wire_nlilOi_o);
	assign		wire_n1lOl_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[0] : wire_n1O0l_dataout;
	assign		wire_n1lOO_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[1] : wire_n1O0O_dataout;
	and(wire_n1O_dataout, nl1li, niiOli);
	assign		wire_n1O0i_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[5] : wire_n1Oli_dataout;
	and(wire_n1O0l_dataout, nlOOli, ~(wire_nlilii_dataout));
	and(wire_n1O0O_dataout, nlOOll, ~(wire_nlilii_dataout));
	assign		wire_n1O1i_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[2] : wire_n1Oii_dataout;
	assign		wire_n1O1l_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[3] : wire_n1Oil_dataout;
	assign		wire_n1O1O_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[4] : wire_n1OiO_dataout;
	and(wire_n1Oii_dataout, nlOOlO, ~(wire_nlilii_dataout));
	and(wire_n1Oil_dataout, nlOOOi, ~(wire_nlilii_dataout));
	and(wire_n1OiO_dataout, nlOOOl, ~(wire_nlilii_dataout));
	and(wire_n1Oli_dataout, nlOOOO, ~(wire_nlilii_dataout));
	assign		wire_n1OlO_dataout = (wire_nlilil_dataout === 1'b1) ? wire_n1OOO_o[0] : n111i;
	assign		wire_n1OOi_dataout = (wire_nlilil_dataout === 1'b1) ? wire_n1OOO_o[1] : n111l;
	assign		wire_n1OOl_dataout = (wire_nlilil_dataout === 1'b1) ? wire_n1OOO_o[2] : n111O;
	assign		wire_ni0i_dataout = (niiOiO === 1'b1) ? n100i : wire_nlii_dataout;
	assign		wire_ni0l_dataout = (niiOiO === 1'b1) ? n100l : wire_nlil_dataout;
	assign		wire_ni0O_dataout = (niiOiO === 1'b1) ? n100O : wire_nliO_dataout;
	and(wire_ni0OO_dataout, niiiil, ~(niiilO));
	and(wire_ni11i_dataout, wire_nillO_dataout, nli0O);
	assign		wire_ni1i_dataout = (niiOil === 1'b1) ? nl0O1l : wire_nl0i_dataout;
	assign		wire_ni1l_dataout = (niiOil === 1'b1) ? nl0iOO : wire_nl0l_dataout;
	assign		wire_ni1O_dataout = (niiOil === 1'b1) ? nl0l1i : wire_nl0O_dataout;
	and(wire_nii_dataout, nl1Ol, niiOli);
	and(wire_nii0i_dataout, wire_niiil_dataout, niiOOi);
	and(wire_nii0l_dataout, wire_niiiO_dataout, niiOOi);
	assign		wire_nii0O_dataout = (niiilO === 1'b1) ? niiiil : niiiiO;
	and(wire_nii1i_dataout, niiiil, niiilO);
	and(wire_nii1l_dataout, wire_nii0O_dataout, ~(niiOOi));
	assign		wire_nii1O_dataout = (niiOOi === 1'b1) ? (~ niiili) : wire_niiii_dataout;
	assign		wire_niii_dataout = (niiOiO === 1'b1) ? n10ii : wire_nlli_dataout;
	assign		wire_niiii_dataout = (niiilO === 1'b1) ? (~ niiiil) : (~ niiiiO);
	and(wire_niiil_dataout, niiili, ~(niiilO));
	and(wire_niiiO_dataout, niiili, niiilO);
	assign		wire_niil_dataout = (niiOiO === 1'b1) ? n10il : wire_nlll_dataout;
	and(wire_niili_dataout, wire_nil1i_dataout, niiOOi);
	and(wire_niill_dataout, wire_nil1l_dataout, niiOOi);
	and(wire_niilO_dataout, wire_nil1O_dataout, niiOOi);
	assign		wire_niiO_dataout = (niiOiO === 1'b1) ? n10iO : wire_nllO_dataout;
	and(wire_niiOi_dataout, wire_nil0i_dataout, niiOOi);
	and(wire_niiOl_dataout, (~ niiill), niiOOi);
	and(wire_niiOO_dataout, niiill, niiOOi);
	and(wire_nil_dataout, niOlO, niiOli);
	and(wire_nil0i_dataout, niiilO, niiill);
	and(wire_nil0l_dataout, wire_nilil_dataout, ~(niiilO));
	and(wire_nil0O_dataout, wire_niliO_dataout, ~(niiilO));
	and(wire_nil1i_dataout, wire_nil0l_dataout, niiill);
	and(wire_nil1l_dataout, wire_nil0O_dataout, niiill);
	and(wire_nil1O_dataout, wire_nilii_dataout, niiill);
	assign		wire_nili_dataout = (niiOiO === 1'b1) ? n10li : wire_nlOi_dataout;
	and(wire_nilii_dataout, niil1i, ~(niiilO));
	and(wire_nilil_dataout, (~ niiiOO), ~(niil1i));
	and(wire_niliO_dataout, niiiOO, ~(niil1i));
	assign		wire_nill_dataout = (niiOiO === 1'b1) ? n10ll : wire_nlOl_dataout;
	and(wire_nilli_dataout, (~ niiiOl), niiOOi);
	or(wire_nilll_dataout, wire_nilOl_dataout, niiOOi);
	and(wire_nillO_dataout, wire_nilOO_dataout, ~(niiOOi));
	assign		wire_nilO_dataout = (niiOiO === 1'b1) ? n10lO : wire_nlOO_dataout;
	and(wire_nilOi_dataout, wire_niO1i_dataout, ~(niiOOi));
	or(wire_nilOl_dataout, wire_niO1l_dataout, niiilO);
	and(wire_nilOO_dataout, (~ niiiOl), ~(niiilO));
	and(wire_niO_dataout, niOOi, niiOli);
	assign		wire_niO00i_dataout = (niiOOi === 1'b1) ? nl00OO : nl0iil;
	assign		wire_niO00l_dataout = (niiOOi === 1'b1) ? nl0i1i : nl0iiO;
	assign		wire_niO00O_dataout = (niiOOi === 1'b1) ? nl0i1l : nl0ili;
	assign		wire_niO01i_dataout = (niiOOi === 1'b1) ? wire_niOOOi_dataout : wire_niOiOO_dataout;
	assign		wire_niO01l_dataout = (niiOOi === 1'b1) ? wire_niOOOl_dataout : wire_niOl1i_dataout;
	and(wire_niO01O_dataout, nl0iii, ~(niiOOi));
	assign		wire_niO0ii_dataout = (niiOOi === 1'b1) ? nl0i1O : nl0ill;
	assign		wire_niO0il_dataout = (niiOOi === 1'b1) ? nl0i0i : nl0ilO;
	assign		wire_niO0iO_dataout = (niiOOi === 1'b1) ? nl0i0l : nl0iOi;
	assign		wire_niO0li_dataout = (niiOOi === 1'b1) ? nl0i0O : nl0iOl;
	and(wire_niO0ll_dataout, nl00il, niiOOi);
	and(wire_niO0lO_dataout, nl00iO, niiOOi);
	and(wire_niO0Oi_dataout, nl00li, niiOOi);
	and(wire_niO0Ol_dataout, nl00ll, niiOOi);
	and(wire_niO0OO_dataout, nl00lO, niiOOi);
	assign		wire_niO10i_dataout = (niiOOi === 1'b1) ? wire_niOO1i_dataout : wire_niOi1O_dataout;
	assign		wire_niO10l_dataout = (niiOOi === 1'b1) ? wire_niOO1l_dataout : wire_niOi0i_dataout;
	assign		wire_niO10O_dataout = (niiOOi === 1'b1) ? wire_niOO1O_dataout : wire_niOi0l_dataout;
	and(wire_niO11l_dataout, wire_nlO_dataout, niiOOi);
	and(wire_niO11O_dataout, wire_nlO_dataout, ~(niiOOi));
	and(wire_niO1i_dataout, wire_niO1O_dataout, ~(niiilO));
	assign		wire_niO1ii_dataout = (niiOOi === 1'b1) ? wire_niOO0i_dataout : wire_niOi0O_dataout;
	assign		wire_niO1il_dataout = (niiOOi === 1'b1) ? wire_niOO0l_dataout : wire_niOiii_dataout;
	assign		wire_niO1iO_dataout = (niiOOi === 1'b1) ? wire_niOO0O_dataout : wire_niOiil_dataout;
	and(wire_niO1l_dataout, niiiOi, niiiOl);
	assign		wire_niO1li_dataout = (niiOOi === 1'b1) ? wire_niOOii_dataout : wire_niOiiO_dataout;
	assign		wire_niO1ll_dataout = (niiOOi === 1'b1) ? wire_niOOil_dataout : wire_niOili_dataout;
	assign		wire_niO1lO_dataout = (niiOOi === 1'b1) ? wire_niOOiO_dataout : wire_niOill_dataout;
	and(wire_niO1O_dataout, (~ niiiOi), niiiOl);
	assign		wire_niO1Oi_dataout = (niiOOi === 1'b1) ? wire_niOOli_dataout : wire_niOilO_dataout;
	assign		wire_niO1Ol_dataout = (niiOOi === 1'b1) ? wire_niOOll_dataout : wire_niOiOi_dataout;
	assign		wire_niO1OO_dataout = (niiOOi === 1'b1) ? wire_niOOlO_dataout : wire_niOiOl_dataout;
	assign		wire_niOi_dataout = (niiOiO === 1'b1) ? n10Oi : wire_n1i_dataout;
	and(wire_niOi0i_dataout, wire_niOl1O_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOi0l_dataout, wire_niOl0i_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOi0O_dataout, wire_niOl0l_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOi1i_dataout, nl00Oi, niiOOi);
	and(wire_niOi1l_dataout, nl00Ol, niiOOi);
	and(wire_niOi1O_dataout, wire_niOl1l_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOiii_dataout, wire_niOl0O_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOiil_dataout, wire_niOlii_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOiiO_dataout, wire_niOlil_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOili_dataout, wire_niOliO_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOill_dataout, wire_niOlli_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOilO_dataout, wire_niOlll_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOiOi_dataout, wire_niOllO_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOiOl_dataout, wire_niOlOi_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOiOO_dataout, wire_niOlOl_dataout, ~((~ wire_nlO_dataout)));
	assign		wire_niOl_dataout = (niiOiO === 1'b1) ? n10Ol : wire_n1l_dataout;
	and(wire_niOl0i_dataout, nl0O0l, ~(ni01Oi));
	and(wire_niOl0l_dataout, nl0O0O, ~(ni01Oi));
	and(wire_niOl0O_dataout, nl0Oii, ~(ni01Oi));
	or(wire_niOl1i_dataout, wire_niOlOO_dataout, (~ wire_nlO_dataout));
	and(wire_niOl1l_dataout, nl0O1O, ~(ni01Oi));
	and(wire_niOl1O_dataout, nl0O0i, ~(ni01Oi));
	and(wire_niOlii_dataout, nl0Oil, ~(ni01Oi));
	and(wire_niOlil_dataout, nl0OiO, ~(ni01Oi));
	and(wire_niOliO_dataout, nl0Oli, ~(ni01Oi));
	and(wire_niOlli_dataout, nl0Oll, ~(ni01Oi));
	or(wire_niOlll_dataout, nl0OlO, ni01Oi);
	and(wire_niOllO_dataout, nl0OOi, ~(ni01Oi));
	and(wire_niOlOi_dataout, nl0OOl, ~(ni01Oi));
	and(wire_niOlOl_dataout, nli11i, ~(ni01Oi));
	and(wire_niOlOO_dataout, nli11O, ~(ni01Oi));
	assign		wire_niOO_dataout = (niiOiO === 1'b1) ? n10OO : wire_n1O_dataout;
	and(wire_niOO0i_dataout, wire_nl111O_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOO0l_dataout, wire_nl110i_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOO0O_dataout, wire_nl110l_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOO1i_dataout, wire_niOOOO_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOO1l_dataout, wire_nl111i_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOO1O_dataout, wire_nl111l_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOOii_dataout, wire_nl110O_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOOil_dataout, wire_nl11ii_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOOiO_dataout, wire_nl11il_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOOli_dataout, wire_nl11iO_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOOll_dataout, wire_nl11li_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOOlO_dataout, wire_nl11ll_dataout, ~((~ wire_nlO_dataout)));
	and(wire_niOOOi_dataout, wire_nl11lO_dataout, ~((~ wire_nlO_dataout)));
	or(wire_niOOOl_dataout, wire_nl11Oi_dataout, (~ wire_nlO_dataout));
	and(wire_niOOOO_dataout, nl0O1O, ~(ni01Ol));
	and(wire_nl000i_dataout, nl0OOi, ~(wire_nlO_dataout));
	and(wire_nl000l_dataout, nl0OOl, ~(wire_nlO_dataout));
	or(wire_nl000O_dataout, nli11i, wire_nlO_dataout);
	and(wire_nl001i_dataout, nl0Oli, ~(wire_nlO_dataout));
	and(wire_nl001l_dataout, nl0Oll, ~(wire_nlO_dataout));
	and(wire_nl001O_dataout, nl0OlO, ~(wire_nlO_dataout));
	and(wire_nl00ii_dataout, nli11O, ~(wire_nlO_dataout));
	and(wire_nl010i_dataout, nl0OlO, ~(ni001i));
	and(wire_nl010l_dataout, nl0OOi, ~(ni001i));
	or(wire_nl010O_dataout, nl0OOl, ni001i);
	and(wire_nl011i_dataout, nl0OiO, ~(ni001i));
	and(wire_nl011l_dataout, nl0Oli, ~(ni001i));
	and(wire_nl011O_dataout, nl0Oll, ~(ni001i));
	and(wire_nl01ii_dataout, nli11i, ~(ni001i));
	and(wire_nl01il_dataout, nli11O, ~(ni001i));
	and(wire_nl01iO_dataout, nl0O1O, ~(wire_nlO_dataout));
	and(wire_nl01li_dataout, nl0O0i, ~(wire_nlO_dataout));
	and(wire_nl01ll_dataout, nl0O0l, ~(wire_nlO_dataout));
	and(wire_nl01lO_dataout, nl0O0O, ~(wire_nlO_dataout));
	and(wire_nl01Oi_dataout, nl0Oii, ~(wire_nlO_dataout));
	and(wire_nl01Ol_dataout, nl0Oil, ~(wire_nlO_dataout));
	and(wire_nl01OO_dataout, nl0OiO, ~(wire_nlO_dataout));
	assign		wire_nl0i_dataout = (niiOiO === 1'b1) ? n1i0i : wire_nii_dataout;
	assign		wire_nl0l_dataout = (niiOiO === 1'b1) ? n101l : wire_nil_dataout;
	assign		wire_nl0O_dataout = (niiOiO === 1'b1) ? n101O : wire_niO_dataout;
	assign		wire_nl100i_dataout = (niiOOi === 1'b1) ? wire_nl1O1i_dataout : wire_nl1i1O_dataout;
	assign		wire_nl100l_dataout = (niiOOi === 1'b1) ? wire_nl1O1l_dataout : wire_nl1i0i_dataout;
	assign		wire_nl100O_dataout = (niiOOi === 1'b1) ? wire_nl1O1O_dataout : wire_nl1i0l_dataout;
	assign		wire_nl101i_dataout = (niiOOi === 1'b1) ? wire_nl1lOi_dataout : wire_nl10OO_dataout;
	assign		wire_nl101l_dataout = (niiOOi === 1'b1) ? wire_nl1lOl_dataout : wire_nl1i1i_dataout;
	assign		wire_nl101O_dataout = (niiOOi === 1'b1) ? wire_nl1lOO_dataout : wire_nl1i1l_dataout;
	assign		wire_nl10ii_dataout = (niiOOi === 1'b1) ? wire_nl1O0i_dataout : wire_nl1i0O_dataout;
	assign		wire_nl10il_dataout = (niiOOi === 1'b1) ? wire_nl1O0l_dataout : wire_nl1iii_dataout;
	assign		wire_nl10iO_dataout = (niiOOi === 1'b1) ? wire_nl1O0O_dataout : wire_nl1iil_dataout;
	assign		wire_nl10li_dataout = (niiOOi === 1'b1) ? wire_nl1Oii_dataout : wire_nl1iiO_dataout;
	assign		wire_nl10ll_dataout = (niiOOi === 1'b1) ? wire_nl1Oil_dataout : wire_nl1ili_dataout;
	assign		wire_nl10lO_dataout = (niiOOi === 1'b1) ? wire_nl1OiO_dataout : wire_nl1ill_dataout;
	and(wire_nl10Oi_dataout, wire_nl1ilO_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl10Ol_dataout, wire_nl1iOi_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl10OO_dataout, wire_nl1iOl_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl110i_dataout, nl0Oii, ~(ni01Ol));
	and(wire_nl110l_dataout, nl0Oil, ~(ni01Ol));
	and(wire_nl110O_dataout, nl0OiO, ~(ni01Ol));
	and(wire_nl111i_dataout, nl0O0i, ~(ni01Ol));
	and(wire_nl111l_dataout, nl0O0l, ~(ni01Ol));
	and(wire_nl111O_dataout, nl0O0O, ~(ni01Ol));
	and(wire_nl11ii_dataout, nl0Oli, ~(ni01Ol));
	and(wire_nl11il_dataout, nl0Oll, ~(ni01Ol));
	or(wire_nl11iO_dataout, nl0OlO, ni01Ol);
	and(wire_nl11li_dataout, nl0OOi, ~(ni01Ol));
	and(wire_nl11ll_dataout, nl0OOl, ~(ni01Ol));
	and(wire_nl11lO_dataout, nli11i, ~(ni01Ol));
	and(wire_nl11Oi_dataout, nli11O, ~(ni01Ol));
	assign		wire_nl11Ol_dataout = (niiOOi === 1'b1) ? wire_nl1lll_dataout : wire_nl10Oi_dataout;
	assign		wire_nl11OO_dataout = (niiOOi === 1'b1) ? wire_nl1llO_dataout : wire_nl10Ol_dataout;
	assign		wire_nl1i_dataout = (niiOiO === 1'b1) ? n1i1i : wire_n0i_dataout;
	and(wire_nl1i0i_dataout, wire_nl1l1O_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1i0l_dataout, wire_nl1l0i_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1i0O_dataout, wire_nl1l0l_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1i1i_dataout, wire_nl1iOO_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1i1l_dataout, wire_nl1l1i_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1i1O_dataout, wire_nl1l1l_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1iii_dataout, wire_nl1l0O_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1iil_dataout, wire_nl1lii_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1iiO_dataout, wire_nl1lil_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1ili_dataout, wire_nl1liO_dataout, ~((~ wire_nlO_dataout)));
	or(wire_nl1ill_dataout, wire_nl1lli_dataout, (~ wire_nlO_dataout));
	and(wire_nl1ilO_dataout, nl0O1O, ~(ni01OO));
	and(wire_nl1iOi_dataout, nl0O0i, ~(ni01OO));
	and(wire_nl1iOl_dataout, nl0O0l, ~(ni01OO));
	and(wire_nl1iOO_dataout, nl0O0O, ~(ni01OO));
	assign		wire_nl1l_dataout = (niiOiO === 1'b1) ? n1i1l : wire_n0l_dataout;
	and(wire_nl1l0i_dataout, nl0Oli, ~(ni01OO));
	and(wire_nl1l0l_dataout, nl0Oll, ~(ni01OO));
	and(wire_nl1l0O_dataout, nl0OlO, ~(ni01OO));
	and(wire_nl1l1i_dataout, nl0Oii, ~(ni01OO));
	and(wire_nl1l1l_dataout, nl0Oil, ~(ni01OO));
	and(wire_nl1l1O_dataout, nl0OiO, ~(ni01OO));
	and(wire_nl1lii_dataout, nl0OOi, ~(ni01OO));
	or(wire_nl1lil_dataout, nl0OOl, ni01OO);
	and(wire_nl1liO_dataout, nli11i, ~(ni01OO));
	and(wire_nl1lli_dataout, nli11O, ~(ni01OO));
	and(wire_nl1lll_dataout, wire_nl1Oli_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1llO_dataout, wire_nl1Oll_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1lOi_dataout, wire_nl1OlO_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1lOl_dataout, wire_nl1OOi_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1lOO_dataout, wire_nl1OOl_dataout, ~((~ wire_nlO_dataout)));
	assign		wire_nl1O_dataout = (niiOiO === 1'b1) ? n1i1O : wire_n0O_dataout;
	and(wire_nl1O0i_dataout, wire_nl011O_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1O0l_dataout, wire_nl010i_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1O0O_dataout, wire_nl010l_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1O1i_dataout, wire_nl1OOO_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1O1l_dataout, wire_nl011i_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1O1O_dataout, wire_nl011l_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1Oii_dataout, wire_nl010O_dataout, ~((~ wire_nlO_dataout)));
	and(wire_nl1Oil_dataout, wire_nl01ii_dataout, ~((~ wire_nlO_dataout)));
	or(wire_nl1OiO_dataout, wire_nl01il_dataout, (~ wire_nlO_dataout));
	and(wire_nl1Oli_dataout, nl0O1O, ~(ni001i));
	and(wire_nl1Oll_dataout, nl0O0i, ~(ni001i));
	and(wire_nl1OlO_dataout, nl0O0l, ~(ni001i));
	and(wire_nl1OOi_dataout, nl0O0O, ~(ni001i));
	and(wire_nl1OOl_dataout, nl0Oii, ~(ni001i));
	and(wire_nl1OOO_dataout, nl0Oil, ~(ni001i));
	and(wire_nli_dataout, rbisten_tx, ((~ rbist_sel[0]) & rbist_sel[1]));
	and(wire_nli00i_dataout, wire_nli0Oi_o[1], ni001O);
	and(wire_nli00l_dataout, wire_nli0Oi_o[2], ni001O);
	and(wire_nli00O_dataout, wire_nli0Oi_o[3], ni001O);
	and(wire_nli01i_dataout, wire_nli0lO_o[5], ni001O);
	and(wire_nli01l_dataout, wire_nli0lO_o[6], ni001O);
	and(wire_nli01O_dataout, wire_nli0Oi_o[0], ni001O);
	and(wire_nli0ii_dataout, wire_nli0Oi_o[4], ni001O);
	and(wire_nli0il_dataout, wire_nli0Oi_o[5], ni001O);
	and(wire_nli0iO_dataout, wire_nli0Oi_o[6], ni001O);
	and(wire_nli0li_dataout, wire_nli0Oi_o[7], ni001O);
	and(wire_nli10i_dataout, wire_nli0ll_o[0], ni001O);
	and(wire_nli10l_dataout, wire_nli0ll_o[1], ni001O);
	and(wire_nli10O_dataout, wire_nli0ll_o[2], ni001O);
	and(wire_nli1ii_dataout, wire_nli0ll_o[3], ni001O);
	and(wire_nli1il_dataout, wire_nli0ll_o[4], ni001O);
	and(wire_nli1iO_dataout, wire_nli0ll_o[5], ni001O);
	and(wire_nli1li_dataout, wire_nli0ll_o[6], ni001O);
	and(wire_nli1ll_dataout, wire_nli0lO_o[0], ni001O);
	and(wire_nli1lO_dataout, wire_nli0lO_o[1], ni001O);
	and(wire_nli1Oi_dataout, wire_nli0lO_o[2], ni001O);
	and(wire_nli1Ol_dataout, wire_nli0lO_o[3], ni001O);
	and(wire_nli1OO_dataout, wire_nli0lO_o[4], ni001O);
	and(wire_nlii_dataout, niOOl, niiOli);
	and(wire_nlil_dataout, niOOO, niiOli);
	and(wire_nlil0O_dataout, wire_nllO1O_dataout, n1iOl);
	and(wire_nlilii_dataout, wire_nllO0i_dataout, n1iOl);
	and(wire_nlilil_dataout, niiOOi, n1iOO);
	and(wire_nlill_dataout, wire_nliOl_o[0], wire_n0iiO_o);
	and(wire_nlilli_dataout, wire_nlO10l_dataout, n1l1i);
	and(wire_nlilll_dataout, wire_nlO10O_dataout, n1l1i);
	and(wire_nlillO_dataout, wire_nlOi0O_dataout, n1l1l);
	and(wire_nlilO_dataout, wire_nliOl_o[1], wire_n0iiO_o);
	and(wire_nliO_dataout, nl11i, niiOli);
	and(wire_nliOi_dataout, wire_nliOl_o[2], wire_n0iiO_o);
	and(wire_nliOll_dataout, (~ niiOOi), n1ilO);
	assign		wire_nliOO_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[0] : wire_nll0l_dataout;
	and(wire_nll_dataout, rbisten_tx, (rbist_sel[0] & (~ rbist_sel[1])));
	assign		wire_nll0i_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[4] : wire_nlliO_dataout;
	and(wire_nll0l_dataout, niOii, ~(wire_n0iil_o));
	and(wire_nll0O_dataout, niOil, ~(wire_n0iil_o));
	and(wire_nll11i_dataout, wire_nlO1ll_dataout, n1l1i);
	assign		wire_nll1i_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[1] : wire_nll0O_dataout;
	assign		wire_nll1l_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[2] : wire_nllii_dataout;
	assign		wire_nll1O_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[3] : wire_nllil_dataout;
	and(wire_nll1Oi_dataout, wire_nlOlOO_dataout, n1l0l);
	and(wire_nlli_dataout, nl11l, niiOli);
	and(wire_nllii_dataout, niOiO, ~(wire_n0iil_o));
	and(wire_nllil_dataout, niOli, ~(wire_n0iil_o));
	and(wire_nlliO_dataout, niOll, ~(wire_n0iil_o));
	and(wire_nlll_dataout, nl11O, niiOli);
	and(wire_nlllil_dataout, ni0l0l, ~(ni0Oii));
	and(wire_nllliO_dataout, ni0l0l, ni0Oii);
	and(wire_nlllli_dataout, wire_nlllOl_dataout, ~(niiOOi));
	assign		wire_nlllll_dataout = (niiOOi === 1'b1) ? (~ ni0lii) : wire_nlllOO_dataout;
	and(wire_nllllO_dataout, wire_nllO1i_dataout, niiOOi);
	and(wire_nlllOi_dataout, wire_nllO1l_dataout, niiOOi);
	assign		wire_nlllOl_dataout = (ni0Oii === 1'b1) ? ni0l0l : ni0l0O;
	assign		wire_nlllOO_dataout = (ni0Oii === 1'b1) ? (~ ni0l0l) : (~ ni0l0O);
	and(wire_nllO_dataout, nl10i, niiOli);
	assign		wire_nllO0i_dataout = (niiOOi === 1'b1) ? ni0lil : ni0liO;
	and(wire_nllO0l_dataout, wire_nllOll_dataout, niiOOi);
	and(wire_nllO0O_dataout, wire_nllOlO_dataout, niiOOi);
	and(wire_nllO1i_dataout, ni0lii, ~(ni0Oii));
	and(wire_nllO1l_dataout, ni0lii, ni0Oii);
	assign		wire_nllO1O_dataout = (niiOOi === 1'b1) ? (~ ni0lil) : (~ ni0liO);
	and(wire_nllOii_dataout, wire_nllOOi_dataout, niiOOi);
	and(wire_nllOil_dataout, wire_nllOOl_dataout, niiOOi);
	and(wire_nllOiO_dataout, wire_nllOOO_dataout, niiOOi);
	and(wire_nllOli_dataout, ni0lli, niiOOi);
	and(wire_nllOll_dataout, wire_nlO11i_dataout, ~(ni0lli));
	and(wire_nllOlO_dataout, wire_nlO11l_dataout, ~(ni0lli));
	and(wire_nllOOi_dataout, wire_nlO11O_dataout, ~(ni0lli));
	and(wire_nllOOl_dataout, wire_nlO10i_dataout, ~(ni0lli));
	and(wire_nllOOO_dataout, (~ ni0lll), ~(ni0lli));
	and(wire_nlO_dataout, rbisten_tx, (((~ rbist_sel[0]) & (~ rbist_sel[1])) & (niiOll6 ^ niiOll5)));
	and(wire_nlO00i_dataout, wire_nlO0li_dataout, ~(ni0lOO));
	and(wire_nlO00l_dataout, ni0lOi, ~(ni0lOO));
	and(wire_nlO00O_dataout, wire_nlO0ll_dataout, ~(ni0lOi));
	and(wire_nlO01i_dataout, wire_nlO0ii_dataout, ~(ni0lOO));
	and(wire_nlO01l_dataout, wire_nlO0il_dataout, ~(ni0lOO));
	and(wire_nlO01O_dataout, wire_nlO0iO_dataout, ~(ni0lOO));
	and(wire_nlO0ii_dataout, wire_nlO0lO_dataout, ~(ni0lOi));
	and(wire_nlO0il_dataout, wire_nlO0Oi_dataout, ~(ni0lOi));
	and(wire_nlO0iO_dataout, wire_nlO0Ol_dataout, ~(ni0lOi));
	and(wire_nlO0li_dataout, (~ ni0lOl), ~(ni0lOi));
	and(wire_nlO0ll_dataout, wire_nlO0OO_dataout, ni0lOl);
	and(wire_nlO0lO_dataout, wire_nlOi1i_dataout, ni0lOl);
	and(wire_nlO0Oi_dataout, wire_nlOi1l_dataout, ni0lOl);
	and(wire_nlO0Ol_dataout, ni0Oii, ni0lOl);
	and(wire_nlO0OO_dataout, wire_nlOi1O_dataout, ~(ni0Oii));
	and(wire_nlO10i_dataout, ni0Oii, ni0lll);
	or(wire_nlO10l_dataout, (~ ni0llO), ~(niiOOi));
	and(wire_nlO10O_dataout, ni0llO, niiOOi);
	and(wire_nlO11i_dataout, wire_nlO0OO_dataout, ni0lll);
	and(wire_nlO11l_dataout, wire_nlOi1i_dataout, ni0lll);
	and(wire_nlO11O_dataout, wire_nlOi1l_dataout, ni0lll);
	and(wire_nlO1ii_dataout, wire_nlO1OO_dataout, ~(niiOOi));
	and(wire_nlO1il_dataout, wire_nlO01i_dataout, ~(niiOOi));
	and(wire_nlO1iO_dataout, wire_nlO01l_dataout, ~(niiOOi));
	and(wire_nlO1li_dataout, wire_nlO01O_dataout, ~(niiOOi));
	assign		wire_nlO1ll_dataout = (niiOOi === 1'b1) ? ni0llO : ni0lOO;
	and(wire_nlO1lO_dataout, wire_nlO00i_dataout, ~(niiOOi));
	and(wire_nlO1Oi_dataout, (~ ni0llO), niiOOi);
	and(wire_nlO1Ol_dataout, wire_nlO00l_dataout, ~(niiOOi));
	and(wire_nlO1OO_dataout, wire_nlO00O_dataout, ~(ni0lOO));
	and(wire_nlOi_dataout, nl10l, niiOli);
	and(wire_nlOi0i_dataout, ni0Oli, ~(ni0Oll));
	assign		wire_nlOi0O_dataout = (niiOOi === 1'b1) ? wire_nlOl1O_dataout : wire_nlOiiO_dataout;
	and(wire_nlOi1i_dataout, wire_nlOi0i_dataout, ~(ni0Oii));
	and(wire_nlOi1l_dataout, ni0Oll, ~(ni0Oii));
	and(wire_nlOi1O_dataout, (~ ni0Oli), ~(ni0Oll));
	assign		wire_nlOiii_dataout = (niiOOi === 1'b1) ? wire_nlOl0i_dataout : wire_nlOili_dataout;
	assign		wire_nlOiil_dataout = (niiOOi === 1'b1) ? wire_nlOl0l_dataout : wire_nlOill_dataout;
	assign		wire_nlOiiO_dataout = (ni0Oii === 1'b1) ? wire_nlOiOO_dataout : wire_nlOilO_dataout;
	assign		wire_nlOili_dataout = (ni0Oii === 1'b1) ? wire_nlOl1i_dataout : wire_nlOiOi_dataout;
	assign		wire_nlOill_dataout = (ni0Oii === 1'b1) ? wire_nlOl1l_dataout : wire_nlOiOl_dataout;
	and(wire_nlOilO_dataout, ni0O1i, ~(ni0O0i));
	or(wire_nlOiOi_dataout, ni0O1i, ni0O0i);
	and(wire_nlOiOl_dataout, (~ ni0O1i), ~(ni0O0i));
	and(wire_nlOiOO_dataout, ni0O1l, ~(ni0O0O));
	and(wire_nlOl_dataout, nl10O, niiOli);
	assign		wire_nlOl0i_dataout = (ni0Oii === 1'b1) ? wire_nlOlli_dataout : wire_nlOlii_dataout;
	assign		wire_nlOl0l_dataout = (ni0Oii === 1'b1) ? wire_nlOlll_dataout : wire_nlOlil_dataout;
	and(wire_nlOl0O_dataout, ni0O0i, ~(ni0O1O));
	or(wire_nlOl1i_dataout, ni0O1l, ni0O0O);
	and(wire_nlOl1l_dataout, (~ ni0O1l), ~(ni0O0O));
	assign		wire_nlOl1O_dataout = (ni0Oii === 1'b1) ? wire_nlOliO_dataout : wire_nlOl0O_dataout;
	or(wire_nlOlii_dataout, ni0O0i, ni0O1O);
	and(wire_nlOlil_dataout, (~ ni0O0i), ~(ni0O1O));
	and(wire_nlOliO_dataout, ni0O0O, ~(ni0O0l));
	or(wire_nlOlli_dataout, ni0O0O, ni0O0l);
	and(wire_nlOlll_dataout, (~ ni0O0O), ~(ni0O0l));
	and(wire_nlOllO_dataout, (~ ni0OiO), niiOOi);
	or(wire_nlOlOi_dataout, wire_nlOO1l_dataout, niiOOi);
	and(wire_nlOlOl_dataout, ni0Oii, ~(niiOOi));
	and(wire_nlOlOO_dataout, wire_nlOO1O_dataout, ~(niiOOi));
	and(wire_nlOO_dataout, nl1ii, niiOli);
	and(wire_nlOO0i_dataout, wire_nlOO0O_dataout, ~(ni0Oii));
	and(wire_nlOO0l_dataout, ni0Oil, ni0OiO);
	and(wire_nlOO0O_dataout, (~ ni0Oil), ni0OiO);
	and(wire_nlOO1i_dataout, wire_nlOO0i_dataout, ~(niiOOi));
	and(wire_nlOO1l_dataout, wire_nlOO0l_dataout, ~(ni0Oii));
	and(wire_nlOO1O_dataout, (~ ni0OiO), ~(ni0Oii));
	oper_add   n00Oi
	( 
	.a({n101i, n11OO, n11Ol, n11Oi, n11lO, n11ll, n11li, n11iO, n11il}),
	.b({{8{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n00Oi_o));
	defparam
		n00Oi.sgate_representation = 0,
		n00Oi.width_a = 9,
		n00Oi.width_b = 9,
		n00Oi.width_o = 9;
	oper_add   n01iO
	( 
	.a({n11ii, n110O, n110l, n110i}),
	.b({{3{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n01iO_o));
	defparam
		n01iO.sgate_representation = 0,
		n01iO.width_a = 4,
		n01iO.width_b = 4,
		n01iO.width_o = 4;
	oper_add   n1lOi
	( 
	.a({nlOOiO, nlOOil, nliliO}),
	.b({{2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1lOi_o));
	defparam
		n1lOi.sgate_representation = 0,
		n1lOi.width_a = 3,
		n1lOi.width_b = 3,
		n1lOi.width_o = 3;
	oper_add   n1Oll
	( 
	.a({nlOOOO, nlOOOl, nlOOOi, nlOOlO, nlOOll, nlOOli}),
	.b({{5{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1Oll_o));
	defparam
		n1Oll.sgate_representation = 0,
		n1Oll.width_a = 6,
		n1Oll.width_b = 6,
		n1Oll.width_o = 6;
	oper_add   n1OOO
	( 
	.a({n111O, n111l, n111i}),
	.b({{2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1OOO_o));
	defparam
		n1OOO.sgate_representation = 0,
		n1OOO.width_a = 3,
		n1OOO.width_b = 3,
		n1OOO.width_o = 3;
	oper_add   nli0ll
	( 
	.a({nl00Ol, nl00Oi, nl00lO, nl00ll, nl00li, nl00iO, nl00il}),
	.b({{6{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli0ll_o));
	defparam
		nli0ll.sgate_representation = 0,
		nli0ll.width_a = 7,
		nli0ll.width_b = 7,
		nli0ll.width_o = 7;
	oper_add   nli0lO
	( 
	.a({nl0i0O, nl0i0l, nl0i0i, nl0i1O, nl0i1l, nl0i1i, nl00OO}),
	.b({{6{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli0lO_o));
	defparam
		nli0lO.sgate_representation = 0,
		nli0lO.width_a = 7,
		nli0lO.width_b = 7,
		nli0lO.width_o = 7;
	oper_add   nli0Oi
	( 
	.a({nl0iOl, nl0iOi, nl0ilO, nl0ill, nl0ili, nl0iiO, nl0iil, nl0iii}),
	.b({{7{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli0Oi_o));
	defparam
		nli0Oi.sgate_representation = 0,
		nli0Oi.width_a = 8,
		nli0Oi.width_b = 8,
		nli0Oi.width_o = 8;
	oper_add   nliOl
	( 
	.a({((niilOO16 ^ niilOO15) & niO0O), niO0l, n0lOi}),
	.b({{2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nliOl_o));
	defparam
		nliOl.sgate_representation = 0,
		nliOl.width_a = 3,
		nliOl.width_b = 3,
		nliOl.width_o = 3;
	oper_add   nllli
	( 
	.a({niOll, niOli, niOiO, ((niiO1i14 ^ niiO1i13) & niOil), niOii}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nllli_o));
	defparam
		nllli.sgate_representation = 0,
		nllli.width_a = 5,
		nllli.width_b = 5,
		nllli.width_o = 5;
	oper_selector   n0iii
	( 
	.data({1'b0, wire_niiOl_dataout, (~ niiill)}),
	.o(wire_n0iii_o),
	.sel({nii10l, nl0iO, nl0il}));
	defparam
		n0iii.width_data = 3,
		n0iii.width_sel = 3;
	oper_selector   n0iil
	( 
	.data({1'b0, wire_niiOO_dataout, niiill}),
	.o(wire_n0iil_o),
	.sel({nii10l, nl0iO, nl0il}));
	defparam
		n0iil.width_data = 3,
		n0iil.width_sel = 3;
	oper_selector   n0iiO
	( 
	.data({1'b0, wire_nilOi_dataout, wire_nii1O_dataout, {2{(~ niiiil)}}}),
	.o(wire_n0iiO_o),
	.sel({ni0OOO, nli0O, nl01l, nl01i, nl1OO}));
	defparam
		n0iiO.width_data = 5,
		n0iiO.width_sel = 5;
	oper_selector   n0ilO
	( 
	.data({1'b0, niiOOi}),
	.o(wire_n0ilO_o),
	.sel({nii11i, (~ nii11i)}));
	defparam
		n0ilO.width_data = 2,
		n0ilO.width_sel = 2;
	oper_selector   n0iOl
	( 
	.data({1'b0, niiiil, (~ niiiil)}),
	.o(wire_n0iOl_o),
	.sel({nii11l, nl01i, nl1OO}));
	defparam
		n0iOl.width_data = 3,
		n0iOl.width_sel = 3;
	oper_selector   n0l1i
	( 
	.data({1'b0, wire_nii1l_dataout, (~ niiiil)}),
	.o(wire_n0l1i_o),
	.sel({nii11O, nl01l, nl01i}));
	defparam
		n0l1i.width_data = 3,
		n0l1i.width_sel = 3;
	oper_selector   n0l1O
	( 
	.data({1'b0, niiOOi, 1'b1, wire_nii1O_dataout}),
	.o(wire_n0l1O_o),
	.sel({nii10i, nl0ii, (((nl00O | nl00l) | nl00i) | nl01O), nl01l}));
	defparam
		n0l1O.width_data = 4,
		n0l1O.width_sel = 4;
	oper_selector   n0lii
	( 
	.data({1'b0, wire_niili_dataout, wire_nil1i_dataout}),
	.o(wire_n0lii_o),
	.sel({nii10l, nl0iO, nl0il}));
	defparam
		n0lii.width_data = 3,
		n0lii.width_sel = 3;
	oper_selector   n0lil
	( 
	.data({1'b0, wire_niill_dataout, wire_nil1l_dataout}),
	.o(wire_n0lil_o),
	.sel({nii10l, nl0iO, nl0il}));
	defparam
		n0lil.width_data = 3,
		n0lil.width_sel = 3;
	oper_selector   n0liO
	( 
	.data({1'b0, wire_niilO_dataout, wire_nil1O_dataout}),
	.o(wire_n0liO_o),
	.sel({nii10l, nl0iO, nl0il}));
	defparam
		n0liO.width_data = 3,
		n0liO.width_sel = 3;
	oper_selector   n0lli
	( 
	.data({1'b0, wire_niiOi_dataout, wire_nil0i_dataout}),
	.o(wire_n0lli_o),
	.sel({nii10l, nl0iO, nl0il}));
	defparam
		n0lli.width_data = 3,
		n0lli.width_sel = 3;
	oper_selector   n0lOl
	( 
	.data({1'b0, niiOOi, 1'b1}),
	.o(wire_n0lOl_o),
	.sel({nii10O, nl0ll, nl0li}));
	defparam
		n0lOl.width_data = 3,
		n0lOl.width_sel = 3;
	oper_selector   n0O0l
	( 
	.data({1'b0, niiOOi, 1'b1}),
	.o(wire_n0O0l_o),
	.sel({nii1il, nl0OO, nl0Ol}));
	defparam
		n0O0l.width_data = 3,
		n0O0l.width_sel = 3;
	oper_selector   n0O1l
	( 
	.data({1'b0, niiOOi, 1'b1}),
	.o(wire_n0O1l_o),
	.sel({nii1ii, nl0Oi, nl0lO}));
	defparam
		n0O1l.width_data = 3,
		n0O1l.width_sel = 3;
	oper_selector   n0Oil
	( 
	.data({1'b0, niiOOi, 1'b1}),
	.o(wire_n0Oil_o),
	.sel({nii1iO, nli1l, nli1i}));
	defparam
		n0Oil.width_data = 3,
		n0Oil.width_sel = 3;
	oper_selector   n0Oll
	( 
	.data({1'b0, niiOOi, 1'b1}),
	.o(wire_n0Oll_o),
	.sel({nii1li, nli0i, nli1O}));
	defparam
		n0Oll.width_data = 3,
		n0Oll.width_sel = 3;
	oper_selector   n0OOl
	( 
	.data({1'b0, niiOOi, wire_nilll_dataout, 1'b1, wire_niiOl_dataout, (~ niiill)}),
	.o(wire_n0OOl_o),
	.sel({nii1ll, nliil, nli0O, nli0l, nl0iO, nl0il}));
	defparam
		n0OOl.width_data = 6,
		n0OOl.width_sel = 6;
	oper_selector   ni00l
	( 
	.data({1'b0, niiOOi}),
	.o(wire_ni00l_o),
	.sel({nii00l, (~ nii00l)}));
	defparam
		ni00l.width_data = 2,
		ni00l.width_sel = 2;
	oper_selector   ni01i
	( 
	.data({1'b0, ((nii1OO44 ^ nii1OO43) & niiOOi)}),
	.o(wire_ni01i_o),
	.sel({nii01i, (~ nii01i)}));
	defparam
		ni01i.width_data = 2,
		ni01i.width_sel = 2;
	oper_selector   ni01O
	( 
	.data({1'b0, niiOOi}),
	.o(wire_ni01O_o),
	.sel({nii01l, (~ nii01l)}));
	defparam
		ni01O.width_data = 2,
		ni01O.width_sel = 2;
	oper_selector   ni0ii
	( 
	.data({1'b0, niiOOi}),
	.o(wire_ni0ii_o),
	.sel({nii0ii, ((nii00O40 ^ nii00O39) & (~ nii0ii))}));
	defparam
		ni0ii.width_data = 2,
		ni0ii.width_sel = 2;
	oper_selector   ni0iO
	( 
	.data({1'b0, niiOOi}),
	.o(wire_ni0iO_o),
	.sel({((nii0li36 ^ nii0li35) & nii0ll), (~ nii0ll)}));
	defparam
		ni0iO.width_data = 2,
		ni0iO.width_sel = 2;
	oper_selector   ni0ll
	( 
	.data({1'b0, niiOOi}),
	.o(wire_ni0ll_o),
	.sel({nii0Ol, (~ nii0Ol)}));
	defparam
		ni0ll.width_data = 2,
		ni0ll.width_sel = 2;
	oper_selector   ni0Oi
	( 
	.data({1'b0, ((nii0OO32 ^ nii0OO31) & wire_nilli_dataout), ((niii1i30 ^ niii1i29) & niiOOi), {7{niiOOi}}}),
	.o(wire_ni0Oi_o),
	.sel({((niii1l28 ^ niii1l27) & niii0l), nli0O, nli0i, nl0OO, nl0ll, nl0ii, nl00O, ((niii1O26 ^ niii1O25) & nl00l), ((niii0i24 ^ niii0i23) & nl00i), nl01l}));
	defparam
		ni0Oi.width_data = 10,
		ni0Oi.width_sel = 10;
	oper_selector   ni10i
	( 
	.data({niiilO, 1'b0, wire_nii0l_dataout, wire_nii1i_dataout}),
	.o(wire_ni10i_o),
	.sel({nlili, nii1Oi, nl01l, nl1OO}));
	defparam
		ni10i.width_data = 4,
		ni10i.width_sel = 4;
	oper_selector   ni11l
	( 
	.data({(~ niiilO), (~ niiOOi), wire_nilOi_dataout, 1'b0, wire_nii0i_dataout, wire_ni0OO_dataout}),
	.o(wire_ni11l_o),
	.sel({nlili, nliil, nli0O, nii1lO, nl01l, nl1OO}));
	defparam
		ni11l.width_data = 6,
		ni11l.width_sel = 6;
	oper_selector   ni1Ol
	( 
	.data({1'b0, niiOOi}),
	.o(wire_ni1Ol_o),
	.sel({nii1Ol, (~ nii1Ol)}));
	defparam
		ni1Ol.width_data = 2,
		ni1Ol.width_sel = 2;
	oper_selector   nil00l
	( 
	.data({1'b0, 1'b1, wire_niO00O_dataout}),
	.o(wire_nil00l_o),
	.sel({(nli11O | nl0O0l), ni1lOO, nl0OOi}));
	defparam
		nil00l.width_data = 3,
		nil00l.width_sel = 3;
	oper_selector   nil01O
	( 
	.data({1'b0, 1'b1, niiOOi, wire_niO00l_dataout}),
	.o(wire_nil01O_o),
	.sel({nli11O, ni1lOl, nl0OOl, nl0OOi}));
	defparam
		nil01O.width_data = 4,
		nil01O.width_sel = 4;
	oper_selector   nil0il
	( 
	.data({1'b0, 1'b1, wire_niO0ii_dataout}),
	.o(wire_nil0il_o),
	.sel({nli11O, ni1O1i, nl0OOi}));
	defparam
		nil0il.width_data = 3,
		nil0il.width_sel = 3;
	oper_selector   nil0li
	( 
	.data({1'b0, 1'b1, wire_niO0il_dataout}),
	.o(wire_nil0li_o),
	.sel({ni1O1O, ni1O1l, nl0OOi}));
	defparam
		nil0li.width_data = 3,
		nil0li.width_sel = 3;
	oper_selector   nil0Oi
	( 
	.data({1'b0, (~ niiOOi), wire_niO0iO_dataout, 1'b1}),
	.o(wire_nil0Oi_o),
	.sel({ni1O0l, nl0OOl, nl0OOi, ni1O0i}));
	defparam
		nil0Oi.width_data = 4,
		nil0Oi.width_sel = 4;
	oper_selector   nil1li
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nil1li_o),
	.sel({ni1lll, (~ ni1lll)}));
	defparam
		nil1li.width_data = 2,
		nil1li.width_sel = 2;
	oper_selector   nil1lO
	( 
	.data({1'b0, (~ niiOOi), wire_niO01O_dataout, 1'b1}),
	.o(wire_nil1lO_o),
	.sel({ni1llO, nl0OOl, nl0OOi, (nl0O0l | nl0O1O)}));
	defparam
		nil1lO.width_data = 4,
		nil1lO.width_sel = 4;
	oper_selector   nil1OO
	( 
	.data({1'b0, (~ niiOOi), wire_niO00i_dataout, 1'b1}),
	.o(wire_nil1OO_o),
	.sel({ni1lOi, nl0OOl, nl0OOi, (nl0O0l | nl0O0i)}));
	defparam
		nil1OO.width_data = 4,
		nil1OO.width_sel = 4;
	oper_selector   nili0i
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nili0i_o),
	.sel({ni1Oil, (~ ni1Oil)}));
	defparam
		nili0i.width_data = 2,
		nili0i.width_sel = 2;
	oper_selector   nili0O
	( 
	.data({1'b0, niiOOi, wire_niO0ll_dataout, niiOOi}),
	.o(wire_nili0O_o),
	.sel({ni1OiO, nl0OOl, nl0OOi, nl0O0O}));
	defparam
		nili0O.width_data = 4,
		nili0O.width_sel = 4;
	oper_selector   nili1i
	( 
	.data({1'b0, 1'b1, wire_niO0li_dataout}),
	.o(wire_nili1i_o),
	.sel({ni1Oii, ni1O0O, nl0OOi}));
	defparam
		nili1i.width_data = 3,
		nili1i.width_sel = 3;
	oper_selector   niliil
	( 
	.data({1'b0, niiOOi, wire_niO0lO_dataout, {5{niiOOi}}}),
	.o(wire_niliil_o),
	.sel({ni1Oli, nli11i, nl0OOi, nl0OlO, nl0Oli, nl0Oil, nl0O0O, nl0O0i}));
	defparam
		niliil.width_data = 8,
		niliil.width_sel = 8;
	oper_selector   nilili
	( 
	.data({1'b0, {2{niiOOi}}, wire_niO0Oi_dataout, {4{niiOOi}}}),
	.o(wire_nilili_o),
	.sel({ni1Oll, nli11i, nl0OOl, nl0OOi, nl0OlO, nl0Oli, nl0Oil, nl0O0i}));
	defparam
		nilili.width_data = 8,
		nilili.width_sel = 8;
	oper_selector   nililO
	( 
	.data({1'b0, {2{niiOOi}}, wire_niO0Ol_dataout, {5{niiOOi}}}),
	.o(wire_nililO_o),
	.sel({ni1OlO, nli11i, nl0OOl, nl0OOi, nl0OlO, nl0Oli, nl0Oil, nl0O0O, nl0O0i}));
	defparam
		nililO.width_data = 9,
		nililO.width_sel = 9;
	oper_selector   niliOl
	( 
	.data({1'b0, {2{niiOOi}}, wire_niO0OO_dataout, {4{niiOOi}}}),
	.o(wire_niliOl_o),
	.sel({ni1OOi, nli11i, nl0OOl, nl0OOi, nl0OlO, nl0Oli, nl0O0O, nl0O0i}));
	defparam
		niliOl.width_data = 8,
		niliOl.width_sel = 8;
	oper_selector   nill0O
	( 
	.data({wire_nl01iO_dataout, wire_nl11Ol_dataout, 1'b0, wire_niO10i_dataout, wire_niO11O_dataout}),
	.o(wire_nill0O_o),
	.sel({nli11O, nli11i, ni011i, nl0OOi, nl0O0i}));
	defparam
		nill0O.width_data = 5,
		nill0O.width_sel = 5;
	oper_selector   nill1i
	( 
	.data({1'b0, niiOOi, wire_niOi1i_dataout, {4{niiOOi}}}),
	.o(wire_nill1i_o),
	.sel({ni1OOl, nl0OOl, nl0OOi, nl0Oli, nl0Oil, nl0O0O, nl0O0i}));
	defparam
		nill1i.width_data = 7,
		nill1i.width_sel = 7;
	oper_selector   nill1O
	( 
	.data({1'b0, {2{niiOOi}}, wire_niOi1l_dataout, {3{niiOOi}}}),
	.o(wire_nill1O_o),
	.sel({ni1OOO, nli11i, nl0OOl, nl0OOi, nl0Oil, nl0O0O, nl0O0i}));
	defparam
		nill1O.width_data = 7,
		nill1O.width_sel = 7;
	oper_selector   nillil
	( 
	.data({wire_nl01li_dataout, wire_nl11OO_dataout, 1'b0, wire_niO10l_dataout, wire_niO11l_dataout, wire_nlO_dataout}),
	.o(wire_nillil_o),
	.sel({nli11O, nli11i, ni011l, nl0OOi, nl0O0O, nl0O0l}));
	defparam
		nillil.width_data = 6,
		nillil.width_sel = 6;
	oper_selector   nillli
	( 
	.data({wire_nl01ll_dataout, wire_nl101i_dataout, 1'b0, wire_niO10O_dataout, wire_niO11O_dataout}),
	.o(wire_nillli_o),
	.sel({nli11O, nli11i, ni011O, nl0OOi, nl0O0O}));
	defparam
		nillli.width_data = 5,
		nillli.width_sel = 5;
	oper_selector   nilllO
	( 
	.data({wire_nl01lO_dataout, wire_nl101l_dataout, 1'b0, wire_niO1ii_dataout, wire_niO11l_dataout, wire_nlO_dataout}),
	.o(wire_nilllO_o),
	.sel({nli11O, nli11i, ni010i, nl0OOi, nl0Oil, nl0Oii}));
	defparam
		nilllO.width_data = 6,
		nilllO.width_sel = 6;
	oper_selector   nillOl
	( 
	.data({wire_nl01Oi_dataout, wire_nl101O_dataout, 1'b0, wire_niO1il_dataout, wire_niO11O_dataout}),
	.o(wire_nillOl_o),
	.sel({nli11O, nli11i, ni010l, nl0OOi, nl0Oil}));
	defparam
		nillOl.width_data = 5,
		nillOl.width_sel = 5;
	oper_selector   nilO0l
	( 
	.data({wire_nl001i_dataout, wire_nl100O_dataout, 1'b0, wire_niO1ll_dataout, wire_niO11l_dataout, wire_nlO_dataout}),
	.o(wire_nilO0l_o),
	.sel({nli11O, nli11i, ni01il, nl0OOi, nl0OlO, nl0Oll}));
	defparam
		nilO0l.width_data = 6,
		nilO0l.width_sel = 6;
	oper_selector   nilO1i
	( 
	.data({wire_nl01Ol_dataout, wire_nl100i_dataout, 1'b0, wire_niO1iO_dataout, wire_niO11l_dataout, wire_nlO_dataout}),
	.o(wire_nilO1i_o),
	.sel({nli11O, nli11i, ni010O, nl0OOi, nl0Oli, nl0OiO}));
	defparam
		nilO1i.width_data = 6,
		nilO1i.width_sel = 6;
	oper_selector   nilO1O
	( 
	.data({wire_nl01OO_dataout, wire_nl100l_dataout, 1'b0, wire_niO1li_dataout, wire_niO11O_dataout}),
	.o(wire_nilO1O_o),
	.sel({nli11O, nli11i, ni01ii, nl0OOi, nl0Oli}));
	defparam
		nilO1O.width_data = 5,
		nilO1O.width_sel = 5;
	oper_selector   nilOii
	( 
	.data({wire_nl001l_dataout, wire_nl10ii_dataout, 1'b0, wire_niO1lO_dataout, wire_niO11O_dataout}),
	.o(wire_nilOii_o),
	.sel({nli11O, nli11i, ni01iO, nl0OOi, nl0OlO}));
	defparam
		nilOii.width_data = 5,
		nilOii.width_sel = 5;
	oper_selector   nilOiO
	( 
	.data({wire_nl001O_dataout, wire_nl10il_dataout, 1'b0, wire_niO1Oi_dataout}),
	.o(wire_nilOiO_o),
	.sel({nli11O, nli11i, ni01ll, nl0OOi}));
	defparam
		nilOiO.width_data = 4,
		nilOiO.width_sel = 4;
	oper_selector   nilOli
	( 
	.data({wire_nl000i_dataout, wire_nl10iO_dataout, wire_nlO_dataout, wire_niO1Ol_dataout, 1'b0}),
	.o(wire_nilOli_o),
	.sel({nli11O, nli11i, nl0OOl, nl0OOi, ni01li}));
	defparam
		nilOli.width_data = 5,
		nilOli.width_sel = 5;
	oper_selector   nilOlO
	( 
	.data({wire_nl000l_dataout, wire_nl10li_dataout, 1'b0, wire_niO1OO_dataout}),
	.o(wire_nilOlO_o),
	.sel({nli11O, nli11i, ni01ll, nl0OOi}));
	defparam
		nilOlO.width_data = 4,
		nilOlO.width_sel = 4;
	oper_selector   nilOOl
	( 
	.data({wire_nl000O_dataout, wire_nl10ll_dataout, 1'b0, wire_niO01i_dataout, wire_niO11l_dataout, wire_nlO_dataout}),
	.o(wire_nilOOl_o),
	.sel({nli11O, nli11i, ni01lO, nl0OOi, nl0O0i, nl0O1O}));
	defparam
		nilOOl.width_data = 6,
		nilOOl.width_sel = 6;
	oper_selector   niO11i
	( 
	.data({wire_nl00ii_dataout, wire_nl10lO_dataout, (~ wire_nlO_dataout), wire_niO01l_dataout, {10{(~ wire_nlO_dataout)}}}),
	.o(wire_niO11i_o),
	.sel({nli11O, nli11i, nl0OOl, nl0OOi, nl0OlO, nl0Oll, nl0Oli, nl0OiO, nl0Oil, nl0Oii, nl0O0O, nl0O0l, nl0O0i, nl0O1O}));
	defparam
		niO11i.width_data = 14,
		niO11i.width_sel = 14;
	oper_selector   nlilOi
	( 
	.data({1'b0, wire_nlOO1i_dataout, wire_nlllll_dataout, {2{(~ ni0l0l)}}}),
	.o(wire_nlilOi_o),
	.sel({ni000i, n1l0l, n1iii, n1i0O, n1i0l}));
	defparam
		nlilOi.width_data = 5,
		nlilOi.width_sel = 5;
	oper_selector   nliO0l
	( 
	.data({1'b0, wire_nlllli_dataout, (~ ni0l0l)}),
	.o(wire_nliO0l_o),
	.sel({ni00ii, n1iii, n1i0O}));
	defparam
		nliO0l.width_data = 3,
		nliO0l.width_sel = 3;
	oper_selector   nliO1i
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nliO1i_o),
	.sel({ni000l, (~ ni000l)}));
	defparam
		nliO1i.width_data = 2,
		nliO1i.width_sel = 2;
	oper_selector   nliO1O
	( 
	.data({1'b0, ni0l0l, (~ ni0l0l)}),
	.o(wire_nliO1O_o),
	.sel({ni000O, n1i0O, n1i0l}));
	defparam
		nliO1O.width_data = 3,
		nliO1O.width_sel = 3;
	oper_selector   nliOii
	( 
	.data({1'b0, niiOOi, 1'b1, wire_nlllll_dataout}),
	.o(wire_nliOii_o),
	.sel({ni00il, n1ilO, (((n1ill | n1ili) | n1iiO) | n1iil), n1iii}));
	defparam
		nliOii.width_data = 4,
		nliOii.width_sel = 4;
	oper_selector   nliOli
	( 
	.data({1'b0, wire_nlO1ii_dataout, wire_nllO0l_dataout}),
	.o(wire_nliOli_o),
	.sel({ni00iO, n1l1i, n1iOO}));
	defparam
		nliOli.width_data = 3,
		nliOli.width_sel = 3;
	oper_selector   nliOlO
	( 
	.data({1'b0, wire_nlO1il_dataout, wire_nllO0O_dataout}),
	.o(wire_nliOlO_o),
	.sel({ni00iO, n1l1i, n1iOO}));
	defparam
		nliOlO.width_data = 3,
		nliOlO.width_sel = 3;
	oper_selector   nliOOi
	( 
	.data({1'b0, wire_nlO1iO_dataout, wire_nllOii_dataout}),
	.o(wire_nliOOi_o),
	.sel({ni00iO, n1l1i, n1iOO}));
	defparam
		nliOOi.width_data = 3,
		nliOOi.width_sel = 3;
	oper_selector   nliOOl
	( 
	.data({1'b0, wire_nlO1li_dataout, wire_nllOil_dataout}),
	.o(wire_nliOOl_o),
	.sel({ni00iO, n1l1i, n1iOO}));
	defparam
		nliOOl.width_data = 3,
		nliOOl.width_sel = 3;
	oper_selector   nll00O
	( 
	.data({1'b0, 1'b1, (~ niiOOi)}),
	.o(wire_nll00O_o),
	.sel({ni0i0l, ni0i0i, n1iOi}));
	defparam
		nll00O.width_data = 3,
		nll00O.width_sel = 3;
	oper_selector   nll01i
	( 
	.data({ni0Oii, 1'b0, wire_nlllOi_dataout, wire_nllliO_dataout}),
	.o(wire_nll01i_o),
	.sel({n1liO, ni0i1i, n1iii, n1i0l}));
	defparam
		nll01i.width_data = 4,
		nll01i.width_sel = 4;
	oper_selector   nll01O
	( 
	.data({1'b0, 1'b1, (~ niiOOi)}),
	.o(wire_nll01O_o),
	.sel({ni0i1O, ni0i1l, n1iOi}));
	defparam
		nll01O.width_data = 3,
		nll01O.width_sel = 3;
	oper_selector   nll0iO
	( 
	.data({1'b0, 1'b1, niiOOi}),
	.o(wire_nll0iO_o),
	.sel({ni0iii, ni0i0O, n1iOi}));
	defparam
		nll0iO.width_data = 3,
		nll0iO.width_sel = 3;
	oper_selector   nll0lO
	( 
	.data({1'b0, 1'b1, (~ niiOOi)}),
	.o(wire_nll0lO_o),
	.sel({ni0iiO, ni0iil, n1iOi}));
	defparam
		nll0lO.width_data = 3,
		nll0lO.width_sel = 3;
	oper_selector   nll0OO
	( 
	.data({1'b0, 1'b1, niiOOi}),
	.o(wire_nll0OO_o),
	.sel({(((n1liO | n1l1O) | n1iOO) | n1iil), ni0ili, n1iOi}));
	defparam
		nll0OO.width_data = 3,
		nll0OO.width_sel = 3;
	oper_selector   nll10i
	( 
	.data({1'b0, wire_nlO1lO_dataout, wire_nllOiO_dataout, wire_nllO0i_dataout}),
	.o(wire_nll10i_o),
	.sel({ni00ll, n1l1i, n1iOO, n1iOl}));
	defparam
		nll10i.width_data = 4,
		nll10i.width_sel = 4;
	oper_selector   nll10O
	( 
	.data({1'b0, wire_nlOiii_dataout, wire_nlO1Oi_dataout, (~ niiOOi)}),
	.o(wire_nll10O_o),
	.sel({ni00lO, n1l1l, n1l1i, n1iOO}));
	defparam
		nll10O.width_data = 4,
		nll10O.width_sel = 4;
	oper_selector   nll11l
	( 
	.data({1'b0, 1'b1, wire_nllO1O_dataout}),
	.o(wire_nll11l_o),
	.sel({ni00li, n1iOi, n1iOl}));
	defparam
		nll11l.width_data = 3,
		nll11l.width_sel = 3;
	oper_selector   nll1il
	( 
	.data({1'b0, wire_nlOlOi_dataout, 1'b1, wire_nlOiil_dataout, wire_nlO1Ol_dataout, wire_nllOli_dataout}),
	.o(wire_nll1il_o),
	.sel({ni00Oi, n1l0l, (n1l0i | n1l1O), n1l1l, n1l1i, n1iOO}));
	defparam
		nll1il.width_data = 6,
		nll1il.width_sel = 6;
	oper_selector   nll1ll
	( 
	.data({1'b0, niiOOi, wire_nlOlOl_dataout}),
	.o(wire_nll1ll_o),
	.sel({ni00Ol, n1lii, n1l0l}));
	defparam
		nll1ll.width_data = 3,
		nll1ll.width_sel = 3;
	oper_selector   nll1Ol
	( 
	.data({(~ ni0Oii), (~ niiOOi), wire_nlOO1i_dataout, 1'b0, wire_nllllO_dataout, wire_nlllil_dataout}),
	.o(wire_nll1Ol_o),
	.sel({n1liO, n1lii, n1l0l, ni00OO, n1iii, n1i0l}));
	defparam
		nll1Ol.width_data = 6,
		nll1Ol.width_sel = 6;
	oper_selector   nlli0i
	( 
	.data({1'b0, 1'b1, niiOOi}),
	.o(wire_nlli0i_o),
	.sel({ni0ilO, ni0ill, n1iOi}));
	defparam
		nlli0i.width_data = 3,
		nlli0i.width_sel = 3;
	oper_selector   nlliil
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nlliil_o),
	.sel({ni0iOi, (~ ni0iOi)}));
	defparam
		nlliil.width_data = 2,
		nlliil.width_sel = 2;
	oper_selector   nllili
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nllili_o),
	.sel({ni0iOl, (~ ni0iOl)}));
	defparam
		nllili.width_data = 2,
		nllili.width_sel = 2;
	oper_selector   nllilO
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nllilO_o),
	.sel({ni0l1i, (~ ni0l1i)}));
	defparam
		nllilO.width_data = 2,
		nllilO.width_sel = 2;
	oper_selector   nlliOi
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nlliOi_o),
	.sel({ni0iOO, (~ ni0iOO)}));
	defparam
		nlliOi.width_data = 2,
		nlliOi.width_sel = 2;
	oper_selector   nlliOO
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nlliOO_o),
	.sel({ni0l1i, (~ ni0l1i)}));
	defparam
		nlliOO.width_data = 2,
		nlliOO.width_sel = 2;
	oper_selector   nlll0i
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nlll0i_o),
	.sel({ni0l1O, (~ ni0l1O)}));
	defparam
		nlll0i.width_data = 2,
		nlll0i.width_sel = 2;
	oper_selector   nlll0O
	( 
	.data({1'b0, wire_nlOllO_dataout, {9{niiOOi}}}),
	.o(wire_nlll0O_o),
	.sel({ni0l0i, n1l0l, n1l1i, n1iOO, n1iOi, n1iOl, n1ilO, n1ill, n1ili, n1iil, n1iii}));
	defparam
		nlll0O.width_data = 11,
		nlll0O.width_sel = 11;
	oper_selector   nlll1l
	( 
	.data({1'b0, niiOOi}),
	.o(wire_nlll1l_o),
	.sel({ni0l1l, (~ ni0l1l)}));
	defparam
		nlll1l.width_data = 2,
		nlll1l.width_sel = 2;
	assign
		bist_ctl_sg = {wire_ni1O_dataout, wire_ni1l_dataout},
		bist_data_sg = {wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout, wire_n0iO_dataout, wire_n0il_dataout, wire_n0ii_dataout, wire_n00O_dataout, wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout},
		ni000i = (((((((((((((n1liO | n1lii) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil),
		ni000l = ((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1iiO) | n1i0O) | n1i0l),
		ni000O = (((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii),
		ni001i = ((((((((~ nl0iOl) & (~ nl0iOi)) & (~ nl0ilO)) & (~ nl0ill)) & (~ nl0ili)) & nl0iiO) & nl0iil) & nl0iii),
		ni001O = (nli11i | nl0OOi),
		ni00ii = (((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1i0l),
		ni00il = (((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1i0O) | n1i0l),
		ni00iO = (((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni00li = (((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni00ll = ((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni00lO = ((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni00Oi = (((((((((((n1liO | n1lii) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni00Ol = (((((((((((((((n1liO | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni00OO = ((((((((((((n1l0i | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1i0O),
		ni010i = ((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni010l = (((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni010O = ((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni011i = (((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O1O),
		ni011l = ((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0i) | nl0O1O),
		ni011O = (((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0l) | nl0O0i) | nl0O1O),
		ni01ii = (((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni01il = ((((((((nl0OOl | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni01iO = (((((((((nl0OOl | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni01li = (((((((((nl0OlO | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni01ll = ((((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni01lO = ((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l),
		ni01Oi = (((((((nl0iOl & nl0iOi) & nl0ilO) & nl0ill) & nl0ili) & nl0iiO) & nl0iil) & nl0iii),
		ni01Ol = ((((((nl00Ol & nl00Oi) & nl00lO) & nl00ll) & nl00li) & nl00iO) & nl00il),
		ni01OO = ((((((((~ nl0iOl) & (~ nl0iOi)) & (~ nl0ilO)) & nl0ill) & (~ nl0ili)) & (~ nl0iiO)) & (~ nl0iil)) & (~ nl0iii)),
		ni0i0i = ((((((n1lii | n1l1O) | n1l1l) | n1iOO) | n1ill) | n1ili) | n1iil),
		ni0i0l = (((((((((n1liO | n1l0l) | n1l0i) | n1l1i) | n1iOl) | n1ilO) | n1iiO) | n1iii) | n1i0O) | n1i0l),
		ni0i0O = (((((((((((n1l0l | n1l0i) | n1l1l) | n1l1i) | n1iOl) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iii) | n1i0O) | n1i0l),
		ni0i1i = ((((((((((((((n1lii | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1i0O),
		ni0i1l = (((((((((n1lii | n1l0l) | n1l0i) | n1l1O) | n1iOO) | n1iOl) | n1ilO) | n1ill) | n1iiO) | n1iil),
		ni0i1O = ((((((n1liO | n1l1l) | n1l1i) | n1ili) | n1iii) | n1i0O) | n1i0l),
		ni0iii = ((((n1liO | n1lii) | n1l1O) | n1iOO) | n1iil),
		ni0iil = (((((((((((n1lii | n1l1O) | n1l1l) | n1iOO) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni0iiO = ((((n1liO | n1l0l) | n1l0i) | n1l1i) | n1iOl),
		ni0ili = ((((((((((((n1lii | n1l0l) | n1l0i) | n1l1l) | n1l1i) | n1iOl) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iii) | n1i0O) | n1i0l),
		ni0ill = (((((((n1lii | n1l0l) | n1l0i) | n1l1l) | n1l1i) | n1iOO) | n1iiO) | n1i0O),
		ni0ilO = ((((((((n1liO | n1l1O) | n1iOl) | n1ilO) | n1ill) | n1ili) | n1iil) | n1iii) | n1i0l),
		ni0iOi = (((((((((((n1liO | n1l0i) | n1l1O) | n1l1l) | n1iOO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni0iOl = (((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1iOO) | n1iOl) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni0iOO = ((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1iOO) | n1iOl) | n1iiO) | n1i0O) | n1i0l),
		ni0l0i = (((((((n1liO | n1lii) | n1l0i) | n1l1O) | n1l1l) | n1iiO) | n1i0O) | n1i0l),
		ni0l0l = ((nlOOiO & (~ nlOOil)) & nliliO),
		ni0l0O = ((nlOOiO & nlOOil) & (~ nliliO)),
		ni0l1i = ((((((n1liO | n1l0i) | n1l1i) | n1iOi) | n1iiO) | n1i0O) | n1i0l),
		ni0l1l = ((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1iiO) | n1i0O) | n1i0l),
		ni0l1O = ((((((((((n1liO | n1l0i) | n1iOl) | n1iOi) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l),
		ni0lii = (((~ nlOOiO) & nlOOil) & (~ nliliO)),
		ni0lil = ((((((~ nlOOOO) & nlOOOl) & (~ nlOOOi)) & (~ nlOOlO)) & nlOOll) & nlOOli),
		ni0liO = (((((nlOOOO & (~ nlOOOl)) & (~ nlOOOi)) & nlOOlO) & nlOOll) & nlOOli),
		ni0lli = (((~ n111O) & n111l) & n111i),
		ni0lll = ((n111O & n111l) & n111i),
		ni0llO = ((((~ n11ii) & (~ n110O)) & n110l) & (~ n110i)),
		ni0lOi = ((((~ n11ii) & n110O) & n110l) & n110i),
		ni0lOl = (((n11ii & n110O) & n110l) & n110i),
		ni0lOO = (((((~ n11ii) & (~ n110O)) & n110l) & n110i) | (((n11ii & (~ n110O)) & n110l) & n110i)),
		ni0O0i = (((((((((~ n101i) & n11OO) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)) & n11iO) & n11il),
		ni0O0l = (((((((((~ n101i) & (~ n11OO)) & n11Ol) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)) & (~ n11iO)) & (~ n11il)),
		ni0O0O = (((((((((~ n101i) & n11OO) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)) & n11iO) & (~ n11il)),
		ni0O1i = ((((((((n101i & (~ n11OO)) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & n11li) & n11iO) & n11il),
		ni0O1l = ((((((((n101i & (~ n11OO)) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & n11li) & n11iO) & (~ n11il)),
		ni0O1O = (((((((((~ n101i) & (~ n11OO)) & n11Ol) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)) & (~ n11iO)) & n11il),
		ni0Oii = ((~ rcxpat_chnl_sel[0]) & (~ rcxpat_chnl_sel[1])),
		ni0Oil = (((~ nlOOiO) & (~ nlOOil)) & nliliO),
		ni0OiO = (ni0Oll | ni0Oli),
		ni0Oli = ((~ rcxpat_chnl_sel[0]) & rcxpat_chnl_sel[1]),
		ni0Oll = (rcxpat_chnl_sel[0] & (~ rcxpat_chnl_sel[1])),
		ni0OlO = ((((n1lii | n1iiO) | n1iii) | n1i0O) | n1i0l),
		ni0OOi = ((((((n1liO | n1l0l) | n1l0i) | n1l1O) | n1ill) | n1ili) | n1i0l),
		ni0OOl = ((((((n1liO | n1l0l) | n1l1O) | n1l1l) | n1ili) | n1i0O) | n1i0l),
		ni0OOO = (((((((((((((((((((nlili | nliil) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O),
		ni1lll = ((((((nli11O | nl0OOi) | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O),
		ni1llO = (((((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0i),
		ni1lOi = (((((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O1O),
		ni1lOl = ((((((((((nli11i | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni1lOO = ((((((((((nli11i | nl0OOl) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0i) | nl0O1O),
		ni1O0i = ((((((nl0Oli | nl0OiO) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni1O0l = ((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oil),
		ni1O0O = (((((((nli11i | nl0OOl) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni1O1i = (((((((((((nli11i | nl0OOl) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni1O1l = (((((((nli11i | nl0OOl) | nl0Oll) | nl0OiO) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O),
		ni1O1O = ((((nli11O | nl0OlO) | nl0Oli) | nl0Oil) | nl0Oii),
		ni1Oii = ((((nli11O | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO),
		ni1Oil = (((((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0l) | nl0O1O),
		ni1OiO = ((((((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0l) | nl0O0i) | nl0O1O),
		ni1Oli = ((((((nli11O | nl0OOl) | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O),
		ni1Oll = ((((((nli11O | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O1O),
		ni1OlO = (((((nli11O | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O),
		ni1OOi = ((((((nli11O | nl0Oll) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0l) | nl0O1O),
		ni1OOl = (((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O),
		ni1OOO = (((((((nli11O | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O),
		nii00l = (((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0il) | nl01O) | nl01i) | nl1OO),
		nii01i = (((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli1O) | nli1i) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii01l = (((((((((((((nlili | nli0l) | nli1O) | nli1i) | nl0Ol) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl01O) | nl01i) | nl1OO) | (~ (nii01O42 ^ nii01O41))),
		nii0ii = (((((((((((((nlili | nli0l) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0lO) | nl0li) | nl0il) | nl01O) | nl01i) | nl1OO) | (~ (nii0il38 ^ nii0il37))),
		nii0ll = ((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0iO) | nl0il) | nl01O) | nl01i) | nl1OO) | (~ (nii0lO34 ^ nii0lO33))),
		nii0Ol = ((((((((((((((((nlili | nli0l) | nli1O) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0il) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii10i = (((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl01i) | nl1OO),
		nii10l = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii10O = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii11i = ((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl01O) | nl01i) | nl1OO),
		nii11l = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l),
		nii11O = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl1OO),
		nii1ii = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii1il = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii1iO = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii1li = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii1ll = ((((((((((((((((((nlili | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		nii1lO = ((((((((((((((((((nli0l | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01i),
		nii1Oi = ((((((((((((((((((((nliil | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01i),
		nii1Ol = (((((((((((((((nlili | nli0l) | nli1O) | nli1i) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0il) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO),
		niii0l = (((((((((((((((nlili | nliil) | nli0l) | nli1O) | nli1l) | nli1i) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0iO) | nl0il) | nl01O) | nl01i) | nl1OO) | (~ (niii0O22 ^ niii0O21))),
		niiiil = ((niO0O & (~ niO0l)) & n0lOi),
		niiiiO = ((niO0O & niO0l) & (~ n0lOi)),
		niiili = (((~ niO0O) & niO0l) & (~ n0lOi)),
		niiill = ((((niOll & niOli) & niOiO) & niOil) & (~ niOii)),
		niiilO = ((~ rcxpat_chnl_sel[0]) & (~ rcxpat_chnl_sel[1])),
		niiiOi = (((~ niO0O) & (~ niO0l)) & n0lOi),
		niiiOl = (niil1i | niiiOO),
		niiiOO = ((~ rcxpat_chnl_sel[0]) & rcxpat_chnl_sel[1]),
		niil0i = (((((((((nliil | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0ll) | nl0li),
		niil0l = (((((((((nlili | nliil) | nli1l) | nl0OO) | nl0Oi) | nl0li) | nl0il) | nl0ii) | nl00O) | nl00i),
		niil0O = (((((((((nlili | nli0O) | nli0l) | nli1O) | nli1l) | nli1i) | nl0Oi) | nl0lO) | nl0iO) | nl00l),
		niil1i = (rcxpat_chnl_sel[0] & (~ rcxpat_chnl_sel[1])),
		niil1l = ((((nliil | nl01O) | nl01l) | nl01i) | nl1OO),
		niil1O = (((((((nlili | nli0i) | nl0lO) | nl0ll) | nl0ii) | nl01l) | nl01i) | nl1OO),
		niilii = (((((nlili | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl00l),
		niilil = (((((((((((nlili | nli0O) | nli0l) | nli1O) | nli1i) | nl0Ol) | nl0lO) | nl0ll) | nl0il) | nl00l) | nl00i) | nl1OO),
		niiliO = (((((((((nlili | nli0i) | nli1l) | nl0Ol) | nl0Oi) | nl0lO) | nl0iO) | nl00l) | nl01l) | nl1OO),
		niilli = (((((((((nliil | nli0l) | nli0i) | nli1O) | nl0Ol) | nl0Oi) | nl0li) | nl0ii) | nl01O) | nl01l),
		niilll = 1'b1,
		niilOl = 1'b0,
		niiOil = (((~ rbist_sel[0]) & (~ rbist_sel[1])) & (niiO0O8 ^ niiO0O7)),
		niiOiO = ((rbist_sel[0] & (~ rbist_sel[1])) & (niiO0i10 ^ niiO0i9)),
		niiOli = (((~ rbist_sel[0]) & rbist_sel[1]) & (niiO1l12 ^ niiO1l11)),
		niiOOi = ((((rpmadwidth_tx & (~ rpma_doublewidth_tx)) & (nil11i2 ^ nil11i1)) & rdwidth_tx) | ((rpmadwidth_tx & rpma_doublewidth_tx) & (niiOOl4 ^ niiOOl3)));
endmodule //arriagx_hssi_tx_bist_gen
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 91 mux21 114 oper_decoder 1 oper_mux 23 oper_selector 20 
`timescale 1 ps / 1 ps
module  arriagx_hssi_tx_prbs_gen
	( 
	prbs_out,
	rpma_doublewidth_tx,
	rpmadwidth_tx,
	rprbs_en_tx,
	rprbs_sel,
	soft_reset,
	tx_clk) /* synthesis synthesis_clearbox=1 */;
	output   [19:0]  prbs_out;
	input   rpma_doublewidth_tx;
	input   rpmadwidth_tx;
	input   rprbs_en_tx;
	input   [2:0]  rprbs_sel;
	input   soft_reset;
	input   tx_clk;

	reg	n101l5;
	reg	n101l6;
	reg	n10ii3;
	reg	n10ii4;
	reg	n10lO1;
	reg	n10lO2;
	reg	n110i13;
	reg	n110i14;
	reg	n11il11;
	reg	n11il12;
	reg	n11ll10;
	reg	n11ll9;
	reg	n11Ol7;
	reg	n11Ol8;
	reg	nlO0lO43;
	reg	nlO0lO44;
	reg	nlO0Oi41;
	reg	nlO0Oi42;
	reg	nlO0Ol39;
	reg	nlO0Ol40;
	reg	nlO0OO37;
	reg	nlO0OO38;
	reg	nlOi1O35;
	reg	nlOi1O36;
	reg	nlOiii33;
	reg	nlOiii34;
	reg	nlOill31;
	reg	nlOill32;
	reg	nlOiOl29;
	reg	nlOiOl30;
	reg	nlOl0O25;
	reg	nlOl0O26;
	reg	nlOl1l27;
	reg	nlOl1l28;
	reg	nlOlll23;
	reg	nlOlll24;
	reg	nlOlOl21;
	reg	nlOlOl22;
	reg	nlOO0l19;
	reg	nlOO0l20;
	reg	nlOOil17;
	reg	nlOOil18;
	reg	nlOOOi15;
	reg	nlOOOi16;
	reg	n011i;
	reg	n011l;
	reg	n1lOi;
	reg	n1lOl;
	reg	n1lOO;
	reg	n1O0i;
	reg	n1O0l;
	reg	n1O0O;
	reg	n1O1i;
	reg	n1O1l;
	reg	n1O1O;
	reg	n1Oii;
	reg	n1Oil;
	reg	n1OiO;
	reg	n1Oli;
	reg	n1Oll;
	reg	n1OlO;
	reg	n1OOi;
	reg	n1OOl;
	reg	n1OOO;
	reg	nli;
	wire	wire_niO_CLRN;
	reg	n000i;
	reg	n000l;
	reg	n000O;
	reg	n001i;
	reg	n001l;
	reg	n001O;
	reg	n00ii;
	reg	n00il;
	reg	n00iO;
	reg	n00li;
	reg	n00ll;
	reg	n010i;
	reg	n010l;
	reg	n010O;
	reg	n011O;
	reg	n01ii;
	reg	n01il;
	reg	n01iO;
	reg	n01li;
	reg	n01ll;
	reg	n01lO;
	reg	n01Oi;
	reg	n01Ol;
	reg	n01OO;
	reg	ni;
	reg	nO;
	wire	wire_nl_CLRN;
	wire	wire_n00i_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00lO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n00Oi_dataout;
	wire	wire_n00Ol_dataout;
	wire	wire_n00OO_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n0i0i_dataout;
	wire	wire_n0i0l_dataout;
	wire	wire_n0i0O_dataout;
	wire	wire_n0i1i_dataout;
	wire	wire_n0i1l_dataout;
	wire	wire_n0i1O_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0iii_dataout;
	wire	wire_n0iil_dataout;
	wire	wire_n0iiO_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0ili_dataout;
	wire	wire_n0ill_dataout;
	wire	wire_n0ilO_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0iOi_dataout;
	wire	wire_n0iOl_dataout;
	wire	wire_n0iOO_dataout;
	wire	wire_n0l0i_dataout;
	wire	wire_n0l0l_dataout;
	wire	wire_n0l0O_dataout;
	wire	wire_n0l1i_dataout;
	wire	wire_n0l1l_dataout;
	wire	wire_n0l1O_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0lii_dataout;
	wire	wire_n0lil_dataout;
	wire	wire_n0liO_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lli_dataout;
	wire	wire_n0lll_dataout;
	wire	wire_n0llO_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0lOi_dataout;
	wire	wire_n0lOl_dataout;
	wire	wire_n0lOO_dataout;
	wire	wire_n0O0i_dataout;
	wire	wire_n0O0l_dataout;
	wire	wire_n0O0O_dataout;
	wire	wire_n0O1i_dataout;
	wire	wire_n0O1l_dataout;
	wire	wire_n0O1O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Oii_dataout;
	wire	wire_n0Oil_dataout;
	wire	wire_n0OiO_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0Oli_dataout;
	wire	wire_n0Oll_dataout;
	wire	wire_n0OlO_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n0OOi_dataout;
	wire	wire_n0OOl_dataout;
	wire	wire_n0OOO_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_ni00i_dataout;
	wire	wire_ni01i_dataout;
	wire	wire_ni01l_dataout;
	wire	wire_ni01O_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni10i_dataout;
	wire	wire_ni10l_dataout;
	wire	wire_ni10O_dataout;
	wire	wire_ni11i_dataout;
	wire	wire_ni11l_dataout;
	wire	wire_ni11O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1ii_dataout;
	wire	wire_ni1il_dataout;
	wire	wire_ni1iO_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1li_dataout;
	wire	wire_ni1ll_dataout;
	wire	wire_ni1lO_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_ni1Oi_dataout;
	wire	wire_ni1Ol_dataout;
	wire	wire_ni1OO_dataout;
	wire	wire_nlO0O_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOli_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOO_dataout;
	wire  [31:0]   wire_nil0l_o;
	wire  wire_nil0O_o;
	wire  wire_nilii_o;
	wire  wire_nilil_o;
	wire  wire_niliO_o;
	wire  wire_nilli_o;
	wire  wire_nilll_o;
	wire  wire_nillO_o;
	wire  wire_nilOi_o;
	wire  wire_nilOl_o;
	wire  wire_nilOO_o;
	wire  wire_niO0i_o;
	wire  wire_niO0l_o;
	wire  wire_niO0O_o;
	wire  wire_niO1i_o;
	wire  wire_niO1l_o;
	wire  wire_niO1O_o;
	wire  wire_niOii_o;
	wire  wire_niOil_o;
	wire  wire_niOiO_o;
	wire  wire_niOli_o;
	wire  wire_niOll_o;
	wire  wire_niOlO_o;
	wire  wire_niOOi_o;
	wire  wire_ni00l_o;
	wire  wire_ni00O_o;
	wire  wire_ni0ii_o;
	wire  wire_ni0il_o;
	wire  wire_ni0iO_o;
	wire  wire_ni0li_o;
	wire  wire_ni0ll_o;
	wire  wire_ni0lO_o;
	wire  wire_ni0Ol_o;
	wire  wire_ni0OO_o;
	wire  wire_nii0i_o;
	wire  wire_nii1i_o;
	wire  wire_nii1l_o;
	wire  wire_niiii_o;
	wire  wire_niiiO_o;
	wire  wire_niili_o;
	wire  wire_niill_o;
	wire  wire_niilO_o;
	wire  wire_nil1i_o;
	wire  wire_nil1l_o;
	wire  n100i;
	wire  n100l;
	wire  n100O;
	wire  n101i;
	wire  n101O;
	wire  n10li;
	wire  n110O;
	wire  n111i;
	wire  n111l;
	wire  n111O;
	wire  n11ii;
	wire  n11li;
	wire  n11Oi;
	wire  nlO00i;
	wire  nlO00l;
	wire  nlO00O;
	wire  nlO0ii;
	wire  nlO0il;
	wire  nlO0iO;
	wire  nlO0li;
	wire  nlO0ll;
	wire  nlOi0l;
	wire  nlOi0O;
	wire  nlOi1i;
	wire  nlOi1l;
	wire  nlOiiO;
	wire  nlOili;
	wire  nlOiOi;
	wire  nlOl0i;
	wire  nlOl0l;
	wire  nlOl1i;
	wire  nlOlil;
	wire  nlOliO;
	wire  nlOlli;
	wire  nlOlOi;
	wire  nlOO0i;
	wire  nlOO1i;
	wire  nlOO1l;
	wire  nlOO1O;
	wire  nlOOii;
	wire  nlOOli;
	wire  nlOOll;
	wire  nlOOlO;
	wire  nlOOOO;

	initial
		n101l5 = 0;
	always @ ( posedge tx_clk)
		  n101l5 <= n101l6;
	event n101l5_event;
	initial
		#1 ->n101l5_event;
	always @(n101l5_event)
		n101l5 <= {1{1'b1}};
	initial
		n101l6 = 0;
	always @ ( posedge tx_clk)
		  n101l6 <= n101l5;
	initial
		n10ii3 = 0;
	always @ ( posedge tx_clk)
		  n10ii3 <= n10ii4;
	event n10ii3_event;
	initial
		#1 ->n10ii3_event;
	always @(n10ii3_event)
		n10ii3 <= {1{1'b1}};
	initial
		n10ii4 = 0;
	always @ ( posedge tx_clk)
		  n10ii4 <= n10ii3;
	initial
		n10lO1 = 0;
	always @ ( posedge tx_clk)
		  n10lO1 <= n10lO2;
	event n10lO1_event;
	initial
		#1 ->n10lO1_event;
	always @(n10lO1_event)
		n10lO1 <= {1{1'b1}};
	initial
		n10lO2 = 0;
	always @ ( posedge tx_clk)
		  n10lO2 <= n10lO1;
	initial
		n110i13 = 0;
	always @ ( posedge tx_clk)
		  n110i13 <= n110i14;
	event n110i13_event;
	initial
		#1 ->n110i13_event;
	always @(n110i13_event)
		n110i13 <= {1{1'b1}};
	initial
		n110i14 = 0;
	always @ ( posedge tx_clk)
		  n110i14 <= n110i13;
	initial
		n11il11 = 0;
	always @ ( posedge tx_clk)
		  n11il11 <= n11il12;
	event n11il11_event;
	initial
		#1 ->n11il11_event;
	always @(n11il11_event)
		n11il11 <= {1{1'b1}};
	initial
		n11il12 = 0;
	always @ ( posedge tx_clk)
		  n11il12 <= n11il11;
	initial
		n11ll10 = 0;
	always @ ( posedge tx_clk)
		  n11ll10 <= n11ll9;
	initial
		n11ll9 = 0;
	always @ ( posedge tx_clk)
		  n11ll9 <= n11ll10;
	event n11ll9_event;
	initial
		#1 ->n11ll9_event;
	always @(n11ll9_event)
		n11ll9 <= {1{1'b1}};
	initial
		n11Ol7 = 0;
	always @ ( posedge tx_clk)
		  n11Ol7 <= n11Ol8;
	event n11Ol7_event;
	initial
		#1 ->n11Ol7_event;
	always @(n11Ol7_event)
		n11Ol7 <= {1{1'b1}};
	initial
		n11Ol8 = 0;
	always @ ( posedge tx_clk)
		  n11Ol8 <= n11Ol7;
	initial
		nlO0lO43 = 0;
	always @ ( posedge tx_clk)
		  nlO0lO43 <= nlO0lO44;
	event nlO0lO43_event;
	initial
		#1 ->nlO0lO43_event;
	always @(nlO0lO43_event)
		nlO0lO43 <= {1{1'b1}};
	initial
		nlO0lO44 = 0;
	always @ ( posedge tx_clk)
		  nlO0lO44 <= nlO0lO43;
	initial
		nlO0Oi41 = 0;
	always @ ( posedge tx_clk)
		  nlO0Oi41 <= nlO0Oi42;
	event nlO0Oi41_event;
	initial
		#1 ->nlO0Oi41_event;
	always @(nlO0Oi41_event)
		nlO0Oi41 <= {1{1'b1}};
	initial
		nlO0Oi42 = 0;
	always @ ( posedge tx_clk)
		  nlO0Oi42 <= nlO0Oi41;
	initial
		nlO0Ol39 = 0;
	always @ ( posedge tx_clk)
		  nlO0Ol39 <= nlO0Ol40;
	event nlO0Ol39_event;
	initial
		#1 ->nlO0Ol39_event;
	always @(nlO0Ol39_event)
		nlO0Ol39 <= {1{1'b1}};
	initial
		nlO0Ol40 = 0;
	always @ ( posedge tx_clk)
		  nlO0Ol40 <= nlO0Ol39;
	initial
		nlO0OO37 = 0;
	always @ ( posedge tx_clk)
		  nlO0OO37 <= nlO0OO38;
	event nlO0OO37_event;
	initial
		#1 ->nlO0OO37_event;
	always @(nlO0OO37_event)
		nlO0OO37 <= {1{1'b1}};
	initial
		nlO0OO38 = 0;
	always @ ( posedge tx_clk)
		  nlO0OO38 <= nlO0OO37;
	initial
		nlOi1O35 = 0;
	always @ ( posedge tx_clk)
		  nlOi1O35 <= nlOi1O36;
	event nlOi1O35_event;
	initial
		#1 ->nlOi1O35_event;
	always @(nlOi1O35_event)
		nlOi1O35 <= {1{1'b1}};
	initial
		nlOi1O36 = 0;
	always @ ( posedge tx_clk)
		  nlOi1O36 <= nlOi1O35;
	initial
		nlOiii33 = 0;
	always @ ( posedge tx_clk)
		  nlOiii33 <= nlOiii34;
	event nlOiii33_event;
	initial
		#1 ->nlOiii33_event;
	always @(nlOiii33_event)
		nlOiii33 <= {1{1'b1}};
	initial
		nlOiii34 = 0;
	always @ ( posedge tx_clk)
		  nlOiii34 <= nlOiii33;
	initial
		nlOill31 = 0;
	always @ ( posedge tx_clk)
		  nlOill31 <= nlOill32;
	event nlOill31_event;
	initial
		#1 ->nlOill31_event;
	always @(nlOill31_event)
		nlOill31 <= {1{1'b1}};
	initial
		nlOill32 = 0;
	always @ ( posedge tx_clk)
		  nlOill32 <= nlOill31;
	initial
		nlOiOl29 = 0;
	always @ ( posedge tx_clk)
		  nlOiOl29 <= nlOiOl30;
	event nlOiOl29_event;
	initial
		#1 ->nlOiOl29_event;
	always @(nlOiOl29_event)
		nlOiOl29 <= {1{1'b1}};
	initial
		nlOiOl30 = 0;
	always @ ( posedge tx_clk)
		  nlOiOl30 <= nlOiOl29;
	initial
		nlOl0O25 = 0;
	always @ ( posedge tx_clk)
		  nlOl0O25 <= nlOl0O26;
	event nlOl0O25_event;
	initial
		#1 ->nlOl0O25_event;
	always @(nlOl0O25_event)
		nlOl0O25 <= {1{1'b1}};
	initial
		nlOl0O26 = 0;
	always @ ( posedge tx_clk)
		  nlOl0O26 <= nlOl0O25;
	initial
		nlOl1l27 = 0;
	always @ ( posedge tx_clk)
		  nlOl1l27 <= nlOl1l28;
	event nlOl1l27_event;
	initial
		#1 ->nlOl1l27_event;
	always @(nlOl1l27_event)
		nlOl1l27 <= {1{1'b1}};
	initial
		nlOl1l28 = 0;
	always @ ( posedge tx_clk)
		  nlOl1l28 <= nlOl1l27;
	initial
		nlOlll23 = 0;
	always @ ( posedge tx_clk)
		  nlOlll23 <= nlOlll24;
	event nlOlll23_event;
	initial
		#1 ->nlOlll23_event;
	always @(nlOlll23_event)
		nlOlll23 <= {1{1'b1}};
	initial
		nlOlll24 = 0;
	always @ ( posedge tx_clk)
		  nlOlll24 <= nlOlll23;
	initial
		nlOlOl21 = 0;
	always @ ( posedge tx_clk)
		  nlOlOl21 <= nlOlOl22;
	event nlOlOl21_event;
	initial
		#1 ->nlOlOl21_event;
	always @(nlOlOl21_event)
		nlOlOl21 <= {1{1'b1}};
	initial
		nlOlOl22 = 0;
	always @ ( posedge tx_clk)
		  nlOlOl22 <= nlOlOl21;
	initial
		nlOO0l19 = 0;
	always @ ( posedge tx_clk)
		  nlOO0l19 <= nlOO0l20;
	event nlOO0l19_event;
	initial
		#1 ->nlOO0l19_event;
	always @(nlOO0l19_event)
		nlOO0l19 <= {1{1'b1}};
	initial
		nlOO0l20 = 0;
	always @ ( posedge tx_clk)
		  nlOO0l20 <= nlOO0l19;
	initial
		nlOOil17 = 0;
	always @ ( posedge tx_clk)
		  nlOOil17 <= nlOOil18;
	event nlOOil17_event;
	initial
		#1 ->nlOOil17_event;
	always @(nlOOil17_event)
		nlOOil17 <= {1{1'b1}};
	initial
		nlOOil18 = 0;
	always @ ( posedge tx_clk)
		  nlOOil18 <= nlOOil17;
	initial
		nlOOOi15 = 0;
	always @ ( posedge tx_clk)
		  nlOOOi15 <= nlOOOi16;
	event nlOOOi15_event;
	initial
		#1 ->nlOOOi15_event;
	always @(nlOOOi15_event)
		nlOOOi15 <= {1{1'b1}};
	initial
		nlOOOi16 = 0;
	always @ ( posedge tx_clk)
		  nlOOOi16 <= nlOOOi15;
	initial
	begin
		n011i = 0;
		n011l = 0;
		n1lOi = 0;
		n1lOl = 0;
		n1lOO = 0;
		n1O0i = 0;
		n1O0l = 0;
		n1O0O = 0;
		n1O1i = 0;
		n1O1l = 0;
		n1O1O = 0;
		n1Oii = 0;
		n1Oil = 0;
		n1OiO = 0;
		n1Oli = 0;
		n1Oll = 0;
		n1OlO = 0;
		n1OOi = 0;
		n1OOl = 0;
		n1OOO = 0;
		nli = 0;
	end
	always @ ( posedge tx_clk or  negedge wire_niO_CLRN)
	begin
		if (wire_niO_CLRN == 1'b0) 
		begin
			n011i <= 0;
			n011l <= 0;
			n1lOi <= 0;
			n1lOl <= 0;
			n1lOO <= 0;
			n1O0i <= 0;
			n1O0l <= 0;
			n1O0O <= 0;
			n1O1i <= 0;
			n1O1l <= 0;
			n1O1O <= 0;
			n1Oii <= 0;
			n1Oil <= 0;
			n1OiO <= 0;
			n1Oli <= 0;
			n1Oll <= 0;
			n1OlO <= 0;
			n1OOi <= 0;
			n1OOl <= 0;
			n1OOO <= 0;
			nli <= 0;
		end
		else if  (n100O == 1'b0) 
		begin
			n011i <= wire_n0OiO_dataout;
			n011l <= wire_n0Oli_dataout;
			n1lOi <= wire_n0l0O_dataout;
			n1lOl <= wire_n0lii_dataout;
			n1lOO <= wire_n0lil_dataout;
			n1O0i <= wire_n0llO_dataout;
			n1O0l <= wire_n0lOi_dataout;
			n1O0O <= wire_n0lOl_dataout;
			n1O1i <= wire_n0liO_dataout;
			n1O1l <= wire_n0lli_dataout;
			n1O1O <= wire_n0lll_dataout;
			n1Oii <= wire_n0lOO_dataout;
			n1Oil <= wire_n0O1i_dataout;
			n1OiO <= wire_n0O1l_dataout;
			n1Oli <= wire_n0O1O_dataout;
			n1Oll <= wire_n0O0i_dataout;
			n1OlO <= wire_n0O0l_dataout;
			n1OOi <= wire_n0O0O_dataout;
			n1OOl <= wire_n0Oii_dataout;
			n1OOO <= wire_n0Oil_dataout;
			nli <= wire_n0l0l_dataout;
		end
	end
	assign
		wire_niO_CLRN = ((n101l6 ^ n101l5) & (~ soft_reset));
	initial
	begin
		n000i = 0;
		n000l = 0;
		n000O = 0;
		n001i = 0;
		n001l = 0;
		n001O = 0;
		n00ii = 0;
		n00il = 0;
		n00iO = 0;
		n00li = 0;
		n00ll = 0;
		n010i = 0;
		n010l = 0;
		n010O = 0;
		n011O = 0;
		n01ii = 0;
		n01il = 0;
		n01iO = 0;
		n01li = 0;
		n01ll = 0;
		n01lO = 0;
		n01Oi = 0;
		n01Ol = 0;
		n01OO = 0;
		ni = 0;
		nO = 0;
	end
	always @ ( posedge tx_clk or  negedge wire_nl_CLRN)
	begin
		if (wire_nl_CLRN == 1'b0) 
		begin
			n000i <= 0;
			n000l <= 0;
			n000O <= 0;
			n001i <= 0;
			n001l <= 0;
			n001O <= 0;
			n00ii <= 0;
			n00il <= 0;
			n00iO <= 0;
			n00li <= 0;
			n00ll <= 0;
			n010i <= 0;
			n010l <= 0;
			n010O <= 0;
			n011O <= 0;
			n01ii <= 0;
			n01il <= 0;
			n01iO <= 0;
			n01li <= 0;
			n01ll <= 0;
			n01lO <= 0;
			n01Oi <= 0;
			n01Ol <= 0;
			n01OO <= 0;
			ni <= 0;
			nO <= 0;
		end
		else 
		begin
			n000i <= wire_n0iOi_dataout;
			n000l <= wire_n0iOl_dataout;
			n000O <= wire_n0iOO_dataout;
			n001i <= wire_n0ili_dataout;
			n001l <= wire_n0ill_dataout;
			n001O <= wire_n0ilO_dataout;
			n00ii <= wire_n0l1i_dataout;
			n00il <= wire_n0l1l_dataout;
			n00iO <= wire_n0l1O_dataout;
			n00li <= wire_n0l0i_dataout;
			n00ll <= ni;
			n010i <= wire_n00Oi_dataout;
			n010l <= wire_n00Ol_dataout;
			n010O <= wire_n00OO_dataout;
			n011O <= wire_n00lO_dataout;
			n01ii <= wire_n0i1i_dataout;
			n01il <= wire_n0i1l_dataout;
			n01iO <= wire_n0i1O_dataout;
			n01li <= wire_n0i0i_dataout;
			n01ll <= wire_n0i0l_dataout;
			n01lO <= wire_n0i0O_dataout;
			n01Oi <= wire_n0iii_dataout;
			n01Ol <= wire_n0iil_dataout;
			n01OO <= wire_n0iiO_dataout;
			ni <= nO;
			nO <= rprbs_en_tx;
		end
	end
	assign
		wire_nl_CLRN = ((n10lO2 ^ n10lO1) & (~ soft_reset));
	or(wire_n00i_dataout, n01il, nli);
	and(wire_n00l_dataout, n01iO, ~(nli));
	assign		wire_n00lO_dataout = (n100O === 1'b1) ? (~ n101O) : wire_n0Oll_dataout;
	or(wire_n00O_dataout, n01li, nli);
	assign		wire_n00Oi_dataout = (n100O === 1'b1) ? (~ n101O) : wire_n0OlO_dataout;
	assign		wire_n00Ol_dataout = (n100O === 1'b1) ? (~ n101O) : wire_n0OOi_dataout;
	assign		wire_n00OO_dataout = (n100O === 1'b1) ? (~ n101O) : wire_n0OOl_dataout;
	and(wire_n01i_dataout, n010l, ~(nli));
	and(wire_n01l_dataout, n010O, ~(nli));
	and(wire_n01O_dataout, n01ii, ~(nli));
	assign		wire_n0i0i_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni11O_dataout;
	assign		wire_n0i0l_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni10i_dataout;
	assign		wire_n0i0O_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni10l_dataout;
	assign		wire_n0i1i_dataout = (n100O === 1'b1) ? (~ n101O) : wire_n0OOO_dataout;
	assign		wire_n0i1l_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni11i_dataout;
	or(wire_n0i1O_dataout, wire_ni11l_dataout, n100O);
	and(wire_n0ii_dataout, n01ll, ~(nli));
	assign		wire_n0iii_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni10O_dataout;
	assign		wire_n0iil_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni1ii_dataout;
	or(wire_n0iiO_dataout, wire_ni1il_dataout, n100O);
	and(wire_n0il_dataout, n01lO, ~(nli));
	or(wire_n0ili_dataout, wire_ni1iO_dataout, n100O);
	assign		wire_n0ill_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni1li_dataout;
	assign		wire_n0ilO_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni1ll_dataout;
	and(wire_n0iO_dataout, n01Oi, ~(nli));
	assign		wire_n0iOi_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni1lO_dataout;
	assign		wire_n0iOl_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni1Oi_dataout;
	assign		wire_n0iOO_dataout = (n100O === 1'b1) ? (~ n100l) : wire_ni1Ol_dataout;
	assign		wire_n0l0i_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni01O_dataout;
	assign		wire_n0l0l_dataout = (n00ll === 1'b1) ? wire_ni00i_dataout : nli;
	assign		wire_n0l0O_dataout = (n00ll === 1'b1) ? wire_ni00l_o : n1lOi;
	assign		wire_n0l1i_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni1OO_dataout;
	assign		wire_n0l1l_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni01i_dataout;
	assign		wire_n0l1O_dataout = (n100O === 1'b1) ? (~ n101O) : wire_ni01l_dataout;
	and(wire_n0li_dataout, n01Ol, ~(nli));
	assign		wire_n0lii_dataout = (n00ll === 1'b1) ? wire_ni00O_o : n1lOl;
	assign		wire_n0lil_dataout = (n00ll === 1'b1) ? wire_ni0ii_o : n1lOO;
	assign		wire_n0liO_dataout = (n00ll === 1'b1) ? wire_ni0il_o : n1O1i;
	and(wire_n0ll_dataout, n01OO, ~(nli));
	assign		wire_n0lli_dataout = (n00ll === 1'b1) ? wire_ni0iO_o : n1O1l;
	assign		wire_n0lll_dataout = (n00ll === 1'b1) ? wire_ni0li_o : n1O1O;
	assign		wire_n0llO_dataout = (n00ll === 1'b1) ? wire_ni0ll_o : n1O0i;
	and(wire_n0lO_dataout, n001i, ~(nli));
	assign		wire_n0lOi_dataout = (n00ll === 1'b1) ? wire_ni0lO_o : n1O0l;
	assign		wire_n0lOl_dataout = (n00ll === 1'b1) ? wire_ni0Ol_o : n1O0O;
	assign		wire_n0lOO_dataout = (n00ll === 1'b1) ? wire_ni0OO_o : n1Oii;
	assign		wire_n0O0i_dataout = (n00ll === 1'b1) ? wire_niiii_o : n1Oll;
	assign		wire_n0O0l_dataout = (n00ll === 1'b1) ? wire_niiiO_o : n1OlO;
	assign		wire_n0O0O_dataout = (n00ll === 1'b1) ? wire_niili_o : n1OOi;
	assign		wire_n0O1i_dataout = (n00ll === 1'b1) ? wire_nii1i_o : n1Oil;
	assign		wire_n0O1l_dataout = (n00ll === 1'b1) ? wire_nii1l_o : n1OiO;
	assign		wire_n0O1O_dataout = (n00ll === 1'b1) ? wire_nii0i_o : n1Oli;
	and(wire_n0Oi_dataout, n001l, ~(nli));
	assign		wire_n0Oii_dataout = (n00ll === 1'b1) ? wire_niill_o : n1OOl;
	assign		wire_n0Oil_dataout = (n00ll === 1'b1) ? wire_niilO_o : n1OOO;
	assign		wire_n0OiO_dataout = (n00ll === 1'b1) ? wire_nil1i_o : n011i;
	and(wire_n0Ol_dataout, n001O, ~(nli));
	assign		wire_n0Oli_dataout = (n00ll === 1'b1) ? wire_nil1l_o : n011l;
	assign		wire_n0Oll_dataout = (n00ll === 1'b1) ? wire_nil0O_o : n011O;
	assign		wire_n0OlO_dataout = (n00ll === 1'b1) ? wire_nilii_o : n010i;
	and(wire_n0OO_dataout, n000i, ~(nli));
	assign		wire_n0OOi_dataout = (n00ll === 1'b1) ? wire_nilil_o : n010l;
	assign		wire_n0OOl_dataout = (n00ll === 1'b1) ? wire_niliO_o : n010O;
	assign		wire_n0OOO_dataout = (n00ll === 1'b1) ? wire_nilli_o : n01ii;
	and(wire_n10i_dataout, wire_n0lO_dataout, ~((~ nli)));
	and(wire_n10l_dataout, wire_n0Oi_dataout, ~((~ nli)));
	and(wire_n10O_dataout, wire_n0Ol_dataout, ~((~ nli)));
	and(wire_n11i_dataout, wire_n0iO_dataout, ~((~ nli)));
	and(wire_n11l_dataout, wire_n0li_dataout, ~((~ nli)));
	and(wire_n11O_dataout, wire_n0ll_dataout, ~((~ nli)));
	and(wire_n1ii_dataout, wire_n0OO_dataout, ~((~ nli)));
	and(wire_n1il_dataout, wire_ni1i_dataout, ~((~ nli)));
	and(wire_n1iO_dataout, wire_ni1l_dataout, ~((~ nli)));
	and(wire_n1li_dataout, wire_ni1O_dataout, ~((~ nli)));
	and(wire_n1ll_dataout, wire_ni0i_dataout, ~((~ nli)));
	and(wire_n1lO_dataout, wire_ni0l_dataout, ~((~ nli)));
	and(wire_n1Oi_dataout, wire_ni0O_dataout, ~((~ nli)));
	and(wire_n1Ol_dataout, n011O, ~(nli));
	and(wire_n1OO_dataout, n010i, ~(nli));
	assign		wire_ni00i_dataout = (wire_nil0l_o[11] === 1'b1) ? (~ nli) : nli;
	assign		wire_ni01i_dataout = (n00ll === 1'b1) ? wire_niOll_o : n00il;
	assign		wire_ni01l_dataout = (n00ll === 1'b1) ? wire_niOlO_o : n00iO;
	assign		wire_ni01O_dataout = (n00ll === 1'b1) ? wire_niOOi_o : n00li;
	and(wire_ni0i_dataout, n00il, ~(nli));
	and(wire_ni0l_dataout, n00iO, ~(nli));
	and(wire_ni0O_dataout, n00li, ~(nli));
	assign		wire_ni10i_dataout = (n00ll === 1'b1) ? wire_nilOl_o : n01ll;
	assign		wire_ni10l_dataout = (n00ll === 1'b1) ? wire_nilOO_o : n01lO;
	assign		wire_ni10O_dataout = (n00ll === 1'b1) ? wire_niO1i_o : n01Oi;
	assign		wire_ni11i_dataout = (n00ll === 1'b1) ? wire_nilll_o : n01il;
	assign		wire_ni11l_dataout = (n00ll === 1'b1) ? wire_nillO_o : n01iO;
	assign		wire_ni11O_dataout = (n00ll === 1'b1) ? wire_nilOi_o : n01li;
	and(wire_ni1i_dataout, n000l, ~(nli));
	assign		wire_ni1ii_dataout = (n00ll === 1'b1) ? wire_niO1l_o : n01Ol;
	assign		wire_ni1il_dataout = (n00ll === 1'b1) ? wire_niO1O_o : n01OO;
	assign		wire_ni1iO_dataout = (n00ll === 1'b1) ? wire_niO0i_o : n001i;
	and(wire_ni1l_dataout, n000O, ~(nli));
	assign		wire_ni1li_dataout = (n00ll === 1'b1) ? wire_niO0l_o : n001l;
	assign		wire_ni1ll_dataout = (n00ll === 1'b1) ? wire_niO0O_o : n001O;
	assign		wire_ni1lO_dataout = (n00ll === 1'b1) ? wire_niOii_o : n000i;
	and(wire_ni1O_dataout, n00ii, ~(nli));
	assign		wire_ni1Oi_dataout = (n00ll === 1'b1) ? wire_niOil_o : n000l;
	assign		wire_ni1Ol_dataout = (n00ll === 1'b1) ? wire_niOiO_o : n000O;
	assign		wire_ni1OO_dataout = (n00ll === 1'b1) ? wire_niOli_o : n00ii;
	or(wire_nlO0O_dataout, wire_n1Ol_dataout, (~ nli));
	or(wire_nlOii_dataout, wire_n1OO_dataout, (~ nli));
	or(wire_nlOil_dataout, wire_n01i_dataout, (~ nli));
	or(wire_nlOiO_dataout, wire_n01l_dataout, (~ nli));
	or(wire_nlOli_dataout, wire_n01O_dataout, (~ nli));
	and(wire_nlOll_dataout, wire_n00i_dataout, ~((~ nli)));
	or(wire_nlOlO_dataout, wire_n00l_dataout, (~ nli));
	and(wire_nlOOi_dataout, wire_n00O_dataout, ~((~ nli)));
	or(wire_nlOOl_dataout, wire_n0ii_dataout, (~ nli));
	or(wire_nlOOO_dataout, wire_n0il_dataout, (~ nli));
	oper_decoder   nil0l
	( 
	.i({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}),
	.o(wire_nil0l_o));
	defparam
		nil0l.width_i = 5,
		nil0l.width_o = 32;
	oper_mux   nil0O
	( 
	.data({{3{1'b0}}, {3{1'b1}}, ((n000i ^ n010O) ^ n00iO), nlOOlO, {5{1'b0}}, 1'b1, nlOi1i, (n01Oi ^ n01lO), {4{1'b0}}, wire_nlO0O_dataout, {2{1'b1}}, n11li, {6{1'b0}}, 1'b1, ((n11Oi ^ n010i) ^ n011O)}),
	.o(wire_nil0O_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nil0O.width_data = 32,
		nil0O.width_sel = 5;
	oper_mux   nilii
	( 
	.data({{3{1'b0}}, {2{1'b1}}, 1'b0, ((n000l ^ n01ii) ^ n00li), nlOOOO, {6{1'b0}}, nlOi1l, (n01Ol ^ n01Oi), {4{1'b0}}, wire_nlOii_dataout, 1'b1, 1'b0, n11ii, {7{1'b0}}, ((n101i ^ n010l) ^ n010i)}),
	.o(wire_nilii_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nilii.width_data = 32,
		nilii.width_sel = 5;
	oper_mux   nilil
	( 
	.data({{3{1'b0}}, {3{1'b1}}, (n01il ^ n011O), nlOO1O, {5{1'b0}}, 1'b1, nlOi0l, n111l, {4{1'b0}}, wire_nlOil_dataout, {2{1'b1}}, n110O, {6{1'b0}}, 1'b1, (((((n101i ^ n01il) ^ n010O) ^ n010l) ^ n010i) ^ n011O)}),
	.o(wire_nilil_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nilil.width_data = 32,
		nilil.width_sel = 5;
	oper_mux   niliO
	( 
	.data({{3{1'b0}}, {2{1'b1}}, 1'b0, (n01iO ^ n010i), nlOO0i, {6{1'b0}}, nlOi0O, n111O, {4{1'b0}}, wire_nlOiO_dataout, 1'b1, 1'b0, (n01iO ^ n010O), {7{1'b0}}, (((((n01li ^ n01il) ^ n01ii) ^ n010O) ^ n010l) ^ n011O)}),
	.o(wire_niliO_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niliO.width_data = 32,
		niliO.width_sel = 5;
	oper_mux   nilli
	( 
	.data({{3{1'b0}}, {3{1'b1}}, nlOi1i, nlOOii, {5{1'b0}}, 1'b1, nlOiiO, nlOOlO, {4{1'b0}}, wire_nlOli_dataout, {2{1'b1}}, (n01li ^ n01ii), {6{1'b0}}, 1'b1, ((n01ii ^ n010O) ^ n011O)}),
	.o(wire_nilli_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nilli.width_data = 32,
		nilli.width_sel = 5;
	oper_mux   nilll
	( 
	.data({{6{1'b0}}, nlOi1l, nlOOll, {6{1'b0}}, nlOili, nlOOOO, {4{1'b0}}, wire_nlOll_dataout, {2{1'b0}}, (n01ll ^ n01il), {7{1'b0}}, ((n01il ^ n01ii) ^ n010i)}),
	.o(wire_nilll_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nilll.width_data = 32,
		nilll.width_sel = 5;
	oper_mux   nillO
	( 
	.data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, nlOi0l, (nlOlli ^ n001i), {5{1'b0}}, 1'b1, nlOiOi, (nlOl0i ^ n01lO), {4{1'b0}}, wire_nlOlO_dataout, 1'b0, 1'b1, (n01lO ^ n01iO), {6{1'b0}}, 1'b1, (n11Oi ^ n010l)}),
	.o(wire_nillO_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nillO.width_data = 32,
		nillO.width_sel = 5;
	oper_mux   nilOi
	( 
	.data({{6{1'b0}}, nlOi0O, n111i, {6{1'b0}}, nlOl1i, (n01Ol ^ n01lO), {4{1'b0}}, wire_nlOOi_dataout, {2{1'b0}}, (n11li ^ n01li), {7{1'b0}}, (n101i ^ n010O)}),
	.o(wire_nilOi_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nilOi.width_data = 32,
		nilOi.width_sel = 5;
	oper_mux   nilOl
	( 
	.data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, nlOiiO, (n000i ^ n001l), {5{1'b0}}, 1'b1, nlOl0i, (n01OO ^ n01Oi), {4{1'b0}}, wire_nlOOl_dataout, 1'b0, 1'b1, (n11ii ^ n01ll), {8{1'b0}}}),
	.o(wire_nilOl_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nilOl.width_data = 32,
		nilOl.width_sel = 5;
	oper_mux   nilOO
	( 
	.data({{3{1'b0}}, 1'b1, {2{1'b0}}, nlOili, (n000l ^ n001O), {6{1'b0}}, nlOl0l, (n001i ^ n01Ol), {4{1'b0}}, wire_nlOOO_dataout, {2{1'b0}}, (n110O ^ n01lO), {8{1'b0}}}),
	.o(wire_nilOO_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		nilOO.width_data = 32,
		nilOO.width_sel = 5;
	oper_mux   niO0i
	( 
	.data({{4{1'b0}}, 1'b1, 1'b0, nlOl0l, ((n00ii ^ n001O) ^ n001l), {6{1'b0}}, nlOlOi, ((n001O ^ n01Ol) ^ n01Oi), {4{1'b0}}, wire_n10i_dataout, {11{1'b0}}}),
	.o(wire_niO0i_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niO0i.width_data = 32,
		niO0i.width_sel = 5;
	oper_mux   niO0l
	( 
	.data({{4{1'b0}}, {2{1'b1}}, nlOlil, ((nlOO1O ^ n001l) ^ n001i), {5{1'b0}}, 1'b1, nlOO1i, ((n111l ^ n01Oi) ^ n01lO), {4{1'b0}}, wire_n10l_dataout, {11{1'b0}}}),
	.o(wire_niO0l_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niO0l.width_data = 32,
		niO0l.width_sel = 5;
	oper_mux   niO0O
	( 
	.data({{3{1'b0}}, 1'b1, {2{1'b0}}, nlOliO, ((nlOO0i ^ n001O) ^ n001l), {6{1'b0}}, nlOO1l, ((n111O ^ n01Ol) ^ n01Oi), {4{1'b0}}, wire_n10O_dataout, {11{1'b0}}}),
	.o(wire_niO0O_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niO0O.width_data = 32,
		niO0O.width_sel = 5;
	oper_mux   niO1i
	( 
	.data({{4{1'b0}}, {2{1'b1}}, nlOiOi, (n000O ^ n000i), {5{1'b0}}, 1'b1, nlOlil, (n001l ^ n01OO), {4{1'b0}}, wire_n11i_dataout, {11{1'b0}}}),
	.o(wire_niO1i_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niO1i.width_data = 32,
		niO1i.width_sel = 5;
	oper_mux   niO1l
	( 
	.data({{4{1'b0}}, 1'b1, 1'b0, nlOl1i, (n00ii ^ n000l), {6{1'b0}}, nlOliO, n111i, {4{1'b0}}, wire_n11l_dataout, {11{1'b0}}}),
	.o(wire_niO1l_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niO1l.width_data = 32,
		niO1l.width_sel = 5;
	oper_mux   niO1O
	( 
	.data({{4{1'b0}}, {2{1'b1}}, nlOl0i, ((n000O ^ n001l) ^ n001i), {5{1'b0}}, 1'b1, nlOlli, ((n001l ^ n01Oi) ^ n01lO), {4{1'b0}}, wire_n11O_dataout, {11{1'b0}}}),
	.o(wire_niO1O_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niO1O.width_data = 32,
		niO1O.width_sel = 5;
	oper_mux   niOii
	( 
	.data({{5{1'b0}}, 1'b1, nlOlli, ((nlOOii ^ n000i) ^ n001O), {6{1'b0}}, n011O, {5{1'b0}}, wire_n1ii_dataout, {11{1'b0}}}),
	.o(wire_niOii_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niOii.width_data = 32,
		niOii.width_sel = 5;
	oper_mux   niOil
	( 
	.data({{3{1'b0}}, 1'b1, {2{1'b0}}, nlOlOi, (nlOOli ^ n000i), {6{1'b0}}, n010i, {5{1'b0}}, wire_n1il_dataout, {11{1'b0}}}),
	.o(wire_niOil_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niOil.width_data = 32,
		niOil.width_sel = 5;
	oper_mux   niOiO
	( 
	.data({{5{1'b0}}, 1'b1, nlOO1i, ((nlOOli ^ n001l) ^ n001i), {6{1'b0}}, n010l, {5{1'b0}}, wire_n1iO_dataout, {11{1'b0}}}),
	.o(wire_niOiO_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niOiO.width_data = 32,
		niOiO.width_sel = 5;
	oper_mux   niOli
	( 
	.data({{6{1'b0}}, nlOO1l, ((nlOOll ^ n001O) ^ n001i), {6{1'b0}}, n010O, {5{1'b0}}, wire_n1li_dataout, {11{1'b0}}}),
	.o(wire_niOli_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niOli.width_data = 32,
		niOli.width_sel = 5;
	oper_mux   niOll
	( 
	.data({{6{1'b0}}, n011O, {7{1'b0}}, n01ii, {5{1'b0}}, wire_n1ll_dataout, {11{1'b0}}}),
	.o(wire_niOll_o),
	.sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niOll.width_data = 32,
		niOll.width_sel = 5;
	oper_mux   niOlO
	( 
	.data({{6{1'b0}}, ((nlO0lO44 ^ nlO0lO43) & n010i), {7{1'b0}}, n01il, {5{1'b0}}, wire_n1lO_dataout, {11{1'b0}}}),
	.o(wire_niOlO_o),
	.sel({((nlO0Oi42 ^ nlO0Oi41) & rpma_doublewidth_tx), rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niOlO.width_data = 32,
		niOlO.width_sel = 5;
	oper_mux   niOOi
	( 
	.data({{6{1'b0}}, n010l, {7{1'b0}}, n01iO, {5{1'b0}}, ((nlO0Ol40 ^ nlO0Ol39) & wire_n1Oi_dataout), {11{1'b0}}}),
	.o(wire_niOOi_o),
	.sel({((nlO0OO38 ^ nlO0OO37) & rpma_doublewidth_tx), rpmadwidth_tx, rprbs_sel[2:0]}));
	defparam
		niOOi.width_data = 32,
		niOOi.width_sel = 5;
	oper_selector   ni00l
	( 
	.data({1'b0, n011O, n00li}),
	.o(wire_ni00l_o),
	.sel({nlO0iO, nlO0li, nlO00i}));
	defparam
		ni00l.width_data = 3,
		ni00l.width_sel = 3;
	oper_selector   ni00O
	( 
	.data({1'b0, n010i, n00iO}),
	.o(wire_ni00O_o),
	.sel({nlO0iO, nlO0li, nlO00i}));
	defparam
		ni00O.width_data = 3,
		ni00O.width_sel = 3;
	oper_selector   ni0ii
	( 
	.data({1'b0, n010l, n00il}),
	.o(wire_ni0ii_o),
	.sel({nlO0iO, nlO0li, nlO00i}));
	defparam
		ni0ii.width_data = 3,
		ni0ii.width_sel = 3;
	oper_selector   ni0il
	( 
	.data({1'b0, n010O, n00ii}),
	.o(wire_ni0il_o),
	.sel({nlO0iO, nlO0li, nlO00i}));
	defparam
		ni0il.width_data = 3,
		ni0il.width_sel = 3;
	oper_selector   ni0iO
	( 
	.data({1'b0, n01ii, n000O}),
	.o(wire_ni0iO_o),
	.sel({nlO0iO, nlO0li, nlO00i}));
	defparam
		ni0iO.width_data = 3,
		ni0iO.width_sel = 3;
	oper_selector   ni0li
	( 
	.data({1'b0, n01il, n000l}),
	.o(wire_ni0li_o),
	.sel({nlO0iO, nlO0li, nlO00i}));
	defparam
		ni0li.width_data = 3,
		ni0li.width_sel = 3;
	oper_selector   ni0ll
	( 
	.data({1'b0, n01iO, n000i}),
	.o(wire_ni0ll_o),
	.sel({nlO0iO, nlO0li, nlO00i}));
	defparam
		ni0ll.width_data = 3,
		ni0ll.width_sel = 3;
	oper_selector   ni0lO
	( 
	.data({1'b0, n01li, n001O}),
	.o(wire_ni0lO_o),
	.sel({nlO0iO, nlO0li, nlO00i}));
	defparam
		ni0lO.width_data = 3,
		ni0lO.width_sel = 3;
	oper_selector   ni0Ol
	( 
	.data({1'b0, n01ll, n001l, n000i}),
	.o(wire_ni0Ol_o),
	.sel({nlO0ll, nlO0il, wire_nil0l_o[25], nlO0ii}));
	defparam
		ni0Ol.width_data = 4,
		ni0Ol.width_sel = 4;
	oper_selector   ni0OO
	( 
	.data({1'b0, n01lO, n001i, n000l}),
	.o(wire_ni0OO_o),
	.sel({nlO0ll, nlO0il, wire_nil0l_o[25], nlO0ii}));
	defparam
		ni0OO.width_data = 4,
		ni0OO.width_sel = 4;
	oper_selector   nii0i
	( 
	.data({1'b0, n01OO, n01Oi}),
	.o(wire_nii0i_o),
	.sel({nlO0iO, nlO00O, ((wire_nil0l_o[25] | wire_nil0l_o[18]) | wire_nil0l_o[16])}));
	defparam
		nii0i.width_data = 3,
		nii0i.width_sel = 3;
	oper_selector   nii1i
	( 
	.data({1'b0, n01Oi, n01OO, n01ll, n001l}),
	.o(wire_nii1i_o),
	.sel({nlO0iO, nlO0il, wire_nil0l_o[25], nlO0ii, wire_nil0l_o[17]}));
	defparam
		nii1i.width_data = 5,
		nii1i.width_sel = 5;
	oper_selector   nii1l
	( 
	.data({1'b0, n01Ol, n01lO, n001i}),
	.o(wire_nii1l_o),
	.sel({nlO0iO, nlO00l, nlO0ii, wire_nil0l_o[17]}));
	defparam
		nii1l.width_data = 4,
		nii1l.width_sel = 4;
	oper_selector   niiii
	( 
	.data({1'b0, n001i, n01lO, n01Ol}),
	.o(wire_niiii_o),
	.sel({nlO0iO, nlO0il, wire_nil0l_o[25], ((wire_nil0l_o[18] | wire_nil0l_o[17]) | wire_nil0l_o[16])}));
	defparam
		niiii.width_data = 4,
		niiii.width_sel = 4;
	oper_selector   niiiO
	( 
	.data({1'b0, n001l, n01ll, n01OO, n01Oi}),
	.o(wire_niiiO_o),
	.sel({nlO0iO, nlO0il, wire_nil0l_o[25], nlO0ii, wire_nil0l_o[17]}));
	defparam
		niiiO.width_data = 5,
		niiiO.width_sel = 5;
	oper_selector   niili
	( 
	.data({1'b0, n001O, n01li, n001i, n01lO}),
	.o(wire_niili_o),
	.sel({nlO0iO, nlO0il, wire_nil0l_o[25], nlO0ii, wire_nil0l_o[17]}));
	defparam
		niili.width_data = 5,
		niili.width_sel = 5;
	oper_selector   niill
	( 
	.data({1'b0, n000i, n01iO, n001l, n01ll}),
	.o(wire_niill_o),
	.sel({nlO0iO, nlO0il, wire_nil0l_o[25], nlO0ii, wire_nil0l_o[17]}));
	defparam
		niill.width_data = 5,
		niill.width_sel = 5;
	oper_selector   niilO
	( 
	.data({1'b0, n000l, n01il, n001O, n01li}),
	.o(wire_niilO_o),
	.sel({nlO0iO, nlO0il, wire_nil0l_o[25], nlO0ii, wire_nil0l_o[17]}));
	defparam
		niilO.width_data = 5,
		niilO.width_sel = 5;
	oper_selector   nil1i
	( 
	.data({1'b0, n000O, n01ii}),
	.o(wire_nil1i_o),
	.sel({nlO0ll, nlO0li, wire_nil0l_o[25]}));
	defparam
		nil1i.width_data = 3,
		nil1i.width_sel = 3;
	oper_selector   nil1l
	( 
	.data({1'b0, n00ii, n010O}),
	.o(wire_nil1l_o),
	.sel({nlO0ll, nlO0li, wire_nil0l_o[25]}));
	defparam
		nil1l.width_data = 3,
		nil1l.width_sel = 3;
	assign
		n100i = ((((rpmadwidth_tx & rpma_doublewidth_tx) & (~ rprbs_sel[0])) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])),
		n100l = (((((~ rpmadwidth_tx) & rpma_doublewidth_tx) & (~ rprbs_sel[0])) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])),
		n100O = ((ni & (~ n00ll)) & (n10ii4 ^ n10ii3)),
		n101i = (n01li ^ n01iO),
		n101O = (n100l | n100i),
		n10li = 1'b1,
		n110O = (n01il ^ n010l),
		n111i = (n001O ^ n001i),
		n111l = (n01OO ^ n01Ol),
		n111O = ((n001i ^ n01OO) ^ (~ (n110i14 ^ n110i13))),
		n11ii = ((n01ii ^ n010i) ^ (~ (n11il12 ^ n11il11))),
		n11li = ((n010O ^ n011O) ^ (~ (n11ll10 ^ n11ll9))),
		n11Oi = ((n01iO ^ n01il) ^ (~ (n11Ol8 ^ n11Ol7))),
		nlO00i = (wire_nil0l_o[25] | wire_nil0l_o[17]),
		nlO00l = ((((((((((wire_nil0l_o[28] | wire_nil0l_o[27]) | wire_nil0l_o[26]) | wire_nil0l_o[25]) | wire_nil0l_o[24]) | wire_nil0l_o[11]) | wire_nil0l_o[10]) | wire_nil0l_o[9]) | wire_nil0l_o[8]) | wire_nil0l_o[1]) | wire_nil0l_o[0]),
		nlO00O = ((((((((((wire_nil0l_o[28] | wire_nil0l_o[27]) | wire_nil0l_o[26]) | wire_nil0l_o[24]) | wire_nil0l_o[17]) | wire_nil0l_o[11]) | wire_nil0l_o[10]) | wire_nil0l_o[9]) | wire_nil0l_o[8]) | wire_nil0l_o[1]) | wire_nil0l_o[0]),
		nlO0ii = (wire_nil0l_o[18] | wire_nil0l_o[16]),
		nlO0il = (((((((((wire_nil0l_o[28] | wire_nil0l_o[27]) | wire_nil0l_o[26]) | wire_nil0l_o[24]) | wire_nil0l_o[11]) | wire_nil0l_o[10]) | wire_nil0l_o[9]) | wire_nil0l_o[8]) | wire_nil0l_o[1]) | wire_nil0l_o[0]),
		nlO0iO = (((((((((((((((((wire_nil0l_o[31] | wire_nil0l_o[30]) | wire_nil0l_o[29]) | wire_nil0l_o[23]) | wire_nil0l_o[22]) | wire_nil0l_o[21]) | wire_nil0l_o[20]) | wire_nil0l_o[19]) | wire_nil0l_o[15]) | wire_nil0l_o[14]) | wire_nil0l_o[13]) | wire_nil0l_o[12]) | wire_nil0l_o[7]) | wire_nil0l_o[6]) | wire_nil0l_o[5]) | wire_nil0l_o[4]) | wire_nil0l_o[3]) | wire_nil0l_o[2]),
		nlO0li = (((((((((((wire_nil0l_o[28] | wire_nil0l_o[27]) | wire_nil0l_o[26]) | wire_nil0l_o[24]) | wire_nil0l_o[18]) | wire_nil0l_o[16]) | wire_nil0l_o[11]) | wire_nil0l_o[10]) | wire_nil0l_o[9]) | wire_nil0l_o[8]) | wire_nil0l_o[1]) | wire_nil0l_o[0]),
		nlO0ll = ((((((((((((((((((wire_nil0l_o[31] | wire_nil0l_o[30]) | wire_nil0l_o[29]) | wire_nil0l_o[23]) | wire_nil0l_o[22]) | wire_nil0l_o[21]) | wire_nil0l_o[20]) | wire_nil0l_o[19]) | wire_nil0l_o[17]) | wire_nil0l_o[15]) | wire_nil0l_o[14]) | wire_nil0l_o[13]) | wire_nil0l_o[12]) | wire_nil0l_o[7]) | wire_nil0l_o[6]) | wire_nil0l_o[5]) | wire_nil0l_o[4]) | wire_nil0l_o[3]) | wire_nil0l_o[2]),
		nlOi0l = (n01lO ^ n01ii),
		nlOi0O = ((n01Oi ^ n01il) ^ (~ (nlOiii34 ^ nlOiii33))),
		nlOi1i = (n01li ^ n010l),
		nlOi1l = ((n01ll ^ n010O) ^ (~ (nlOi1O36 ^ nlOi1O35))),
		nlOiiO = (n01Ol ^ n01iO),
		nlOili = ((n01OO ^ n01li) ^ (~ (nlOill32 ^ nlOill31))),
		nlOiOi = ((n001i ^ n01ll) ^ (~ (nlOiOl30 ^ nlOiOl29))),
		nlOl0i = (n001O ^ n01Oi),
		nlOl0l = ((n000i ^ n01Ol) ^ (~ (nlOl0O26 ^ nlOl0O25))),
		nlOl1i = ((n001l ^ n01lO) ^ (~ (nlOl1l28 ^ nlOl1l27))),
		nlOlil = (n000l ^ n01OO),
		nlOliO = (n000O ^ n001i),
		nlOlli = ((n00ii ^ n001l) ^ (~ (nlOlll24 ^ nlOlll23))),
		nlOlOi = ((n00il ^ n001O) ^ (~ (nlOlOl22 ^ nlOlOl21))),
		nlOO0i = ((n000l ^ n000i) ^ (~ (nlOO0l20 ^ nlOO0l19))),
		nlOO1i = (n00iO ^ n000i),
		nlOO1l = (n00li ^ n000l),
		nlOO1O = (n000i ^ n001O),
		nlOOii = ((n000O ^ n000l) ^ (~ (nlOOil18 ^ nlOOil17))),
		nlOOli = (nlOOll ^ n000l),
		nlOOll = (n00ii ^ n000O),
		nlOOlO = ((n001l ^ n001i) ^ (~ (nlOOOi16 ^ nlOOOi15))),
		nlOOOO = (n001O ^ n001l),
		prbs_out = {n011l, n011i, n1OOO, n1OOl, n1OOi, n1OlO, n1Oll, n1Oli, n1OiO, n1Oil, n1Oii, n1O0O, n1O0l, n1O0i, n1O1O, n1O1l, n1O1i, n1lOO, n1lOl, n1lOi};
endmodule //arriagx_hssi_tx_prbs_gen
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 120 mux21 122 oper_mux 110 
`timescale 1 ps / 1 ps
module  arriagx_hssi_tx_enc_chnl_top
	( 
	cascaded_8b10b_en,
	clk,
	d21_5_eq_n,
	d2_2_eq_n,
	disp_out_3b,
	doublewidth,
	dwidth,
	endec,
	enpolinv_tx,
	ge_xaui_sel,
	ib_force_disparity,
	k_det,
	prbs_en,
	pudr,
	r8b10b_enc_ibm_en,
	renbitrev_tx,
	rendec_data_sel_tx,
	renpolinv_tx,
	rensymswap_tx,
	rev_loop_data,
	rev_loopbk,
	rforce_disp,
	rrev_loopbk,
	rst,
	tx_ctl_pre_en,
	tx_ctl_tc,
	tx_ctl_ts,
	tx_data_9_pre_en,
	tx_data_9_tc,
	tx_data_pg,
	tx_data_pre_en,
	tx_data_tc,
	tx_data_ts,
	txd_extend_tc,
	txlp20b) /* synthesis synthesis_clearbox=1 */;
	input   cascaded_8b10b_en;
	input   clk;
	input   d21_5_eq_n;
	input   d2_2_eq_n;
	output   [1:0]  disp_out_3b;
	input   doublewidth;
	input   dwidth;
	input   endec;
	input   enpolinv_tx;
	input   ge_xaui_sel;
	input   ib_force_disparity;
	input   k_det;
	input   prbs_en;
	output   [19:0]  pudr;
	input   r8b10b_enc_ibm_en;
	input   renbitrev_tx;
	input   rendec_data_sel_tx;
	input   renpolinv_tx;
	input   rensymswap_tx;
	input   [19:0]  rev_loop_data;
	input   rev_loopbk;
	input   rforce_disp;
	input   rrev_loopbk;
	input   rst;
	output   [1:0]  tx_ctl_pre_en;
	input   [1:0]  tx_ctl_tc;
	input   tx_ctl_ts;
	output   [1:0]  tx_data_9_pre_en;
	input   [1:0]  tx_data_9_tc;
	input   [19:0]  tx_data_pg;
	output   [15:0]  tx_data_pre_en;
	input   [15:0]  tx_data_tc;
	input   [7:0]  tx_data_ts;
	input   [1:0]  txd_extend_tc;
	output   [19:0]  txlp20b;

	reg	nilO0l49;
	reg	nilO0l50;
	reg	nilO0O47;
	reg	nilO0O48;
	reg	nilOii45;
	reg	nilOii46;
	reg	nilOiO43;
	reg	nilOiO44;
	reg	nilOli41;
	reg	nilOli42;
	reg	nilOll39;
	reg	nilOll40;
	reg	nilOlO37;
	reg	nilOlO38;
	reg	nilOOi35;
	reg	nilOOi36;
	reg	nilOOl33;
	reg	nilOOl34;
	reg	nilOOO31;
	reg	nilOOO32;
	reg	niO00i5;
	reg	niO00i6;
	reg	niO01l7;
	reg	niO01l8;
	reg	niO0ii3;
	reg	niO0ii4;
	reg	niO0iO1;
	reg	niO0iO2;
	reg	niO10i23;
	reg	niO10i24;
	reg	niO10l21;
	reg	niO10l22;
	reg	niO10O19;
	reg	niO10O20;
	reg	niO11i29;
	reg	niO11i30;
	reg	niO11l27;
	reg	niO11l28;
	reg	niO11O25;
	reg	niO11O26;
	reg	niO1ii17;
	reg	niO1ii18;
	reg	niO1il15;
	reg	niO1il16;
	reg	niO1li13;
	reg	niO1li14;
	reg	niO1lO11;
	reg	niO1lO12;
	reg	niO1OO10;
	reg	niO1OO9;
	reg	n00OO;
	reg	n00Ol_clk_prev;
	wire	wire_n00Ol_PRN;
	wire	wire_n00Ol_ENA;
	reg	n0liO;
	reg	n0lli;
	reg	n0lll;
	reg	n0llO;
	reg	n0lOi;
	reg	n0lOO;
	reg	n0O1l;
	reg	n0O1O;
	reg	n0OiO;
	reg	n0Oll;
	reg	nii0i;
	reg	nii0l;
	reg	nii0O;
	reg	nii1l;
	reg	nii1O;
	reg	niiil;
	reg	niili;
	reg	niill;
	reg	nil0O;
	reg	nil1l;
	reg	nil0l_clk_prev;
	wire	wire_nil0l_CLRN;
	wire	wire_nil0l_PRN;
	reg	n00lO;
	reg	n00Oi;
	reg	n0i0i;
	reg	n0i0l;
	reg	n0i0O;
	reg	n0i1l;
	reg	n0i1O;
	reg	n0iii;
	reg	n0iil;
	reg	n0iiO;
	reg	n0ili;
	reg	n0ill;
	reg	n0ilO;
	reg	n0iOi;
	reg	n0iOl;
	reg	n0iOO;
	reg	n0l0i;
	reg	n0l0l;
	reg	n0l0O;
	reg	n0l1i;
	reg	n0l1l;
	reg	n0l1O;
	reg	n0lii;
	reg	n0lil;
	reg	n0lOl;
	reg	n0O0i;
	reg	n0O0l;
	reg	n0O0O;
	reg	n0O1i;
	reg	n0Oii;
	reg	n0Oil;
	reg	n0Oli;
	reg	n0OlO;
	reg	n0OOi;
	reg	n0OOl;
	reg	n0OOO;
	reg	ni0OO;
	reg	ni11i;
	reg	ni11l;
	reg	ni11O;
	reg	nii1i;
	reg	niiii;
	reg	niiiO;
	reg	niilO;
	reg	niiOi;
	reg	niiOl;
	reg	niiOO;
	reg	nil0i;
	reg	nil1i;
	reg	nil1O_clk_prev;
	wire	wire_nil1O_CLRN;
	wire	wire_nil1O_PRN;
	wire	wire_n00i_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n0i1i_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_ni00i_dataout;
	wire	wire_ni01O_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0iO_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0li_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1ii_dataout;
	wire	wire_ni1il_dataout;
	wire	wire_ni1iO_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1li_dataout;
	wire	wire_ni1ll_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_nii_dataout;
	wire	wire_niii_dataout;
	wire	wire_niil_dataout;
	wire	wire_niiO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nili_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0i0l_dataout;
	wire	wire_nl0i0O_dataout;
	wire	wire_nl0i1l_dataout;
	wire	wire_nl0ili_dataout;
	wire	wire_nl0ilO_dataout;
	wire	wire_nl0iOi_dataout;
	wire	wire_nl0iOl_dataout;
	wire	wire_nl0iOO_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0l1i_dataout;
	wire	wire_nl0lii_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl10iO_dataout;
	wire	wire_nl10li_dataout;
	wire	wire_nl10ll_dataout;
	wire	wire_nl10lO_dataout;
	wire	wire_nl10Oi_dataout;
	wire	wire_nl10Ol_dataout;
	wire	wire_nl11iO_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1lli_dataout;
	wire	wire_nl1lll_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nl1O1l_dataout;
	wire	wire_nl1O1O_dataout;
	wire	wire_nli_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlii0i_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nlil0i_dataout;
	wire	wire_nlil0l_dataout;
	wire	wire_nlil0O_dataout;
	wire	wire_nlilii_dataout;
	wire	wire_nlilil_dataout;
	wire	wire_nliliO_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nll10l_dataout;
	wire	wire_nll10O_dataout;
	wire	wire_nll1lO_dataout;
	wire	wire_nll1Oi_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nllllO_dataout;
	wire	wire_nlllOO_dataout;
	wire	wire_nllO0l_dataout;
	wire	wire_nllO1i_dataout;
	wire	wire_nllOii_dataout;
	wire	wire_nllOil_dataout;
	wire	wire_nllOiO_dataout;
	wire	wire_nllOli_dataout;
	wire	wire_nllOll_dataout;
	wire	wire_nlO11l_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOli_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOO_dataout;
	wire  wire_n000i_o;
	wire  wire_n000l_o;
	wire  wire_n000O_o;
	wire  wire_n001i_o;
	wire  wire_n001l_o;
	wire  wire_n001O_o;
	wire  wire_n00ii_o;
	wire  wire_n00il_o;
	wire  wire_n00iO_o;
	wire  wire_n00li_o;
	wire  wire_n00ll_o;
	wire  wire_n01ii_o;
	wire  wire_n01il_o;
	wire  wire_n01iO_o;
	wire  wire_n01li_o;
	wire  wire_n01ll_o;
	wire  wire_n01lO_o;
	wire  wire_n01Oi_o;
	wire  wire_n01Ol_o;
	wire  wire_n01OO_o;
	wire  wire_nilii_o;
	wire  wire_nilil_o;
	wire  wire_niliO_o;
	wire  wire_nilli_o;
	wire  wire_nilll_o;
	wire  wire_nillO_o;
	wire  wire_nilOi_o;
	wire  wire_nilOl_o;
	wire  wire_nilOO_o;
	wire  wire_niO0i_o;
	wire  wire_niO0l_o;
	wire  wire_niO0O_o;
	wire  wire_niO1i_o;
	wire  wire_niO1l_o;
	wire  wire_niO1O_o;
	wire  wire_niOii_o;
	wire  wire_niOil_o;
	wire  wire_niOiO_o;
	wire  wire_niOli_o;
	wire  wire_niOll_o;
	wire  wire_niOlO_o;
	wire  wire_niOOi_o;
	wire  wire_niOOl_o;
	wire  wire_niOOO_o;
	wire  wire_nl00i_o;
	wire  wire_nl00l_o;
	wire  wire_nl00O_o;
	wire  wire_nl01i_o;
	wire  wire_nl01l_o;
	wire  wire_nl01O_o;
	wire  wire_nl0ii_o;
	wire  wire_nl0il_o;
	wire  wire_nl0iO_o;
	wire  wire_nl0li_o;
	wire  wire_nl0ll_o;
	wire  wire_nl0lO_o;
	wire  wire_nl0Oi_o;
	wire  wire_nl0Ol_o;
	wire  wire_nl0OO_o;
	wire  wire_nl10i_o;
	wire  wire_nl10l_o;
	wire  wire_nl10O_o;
	wire  wire_nl11i_o;
	wire  wire_nl11l_o;
	wire  wire_nl11O_o;
	wire  wire_nl1ii_o;
	wire  wire_nl1il_o;
	wire  wire_nl1iO_o;
	wire  wire_nl1li_o;
	wire  wire_nl1ll_o;
	wire  wire_nl1lO_o;
	wire  wire_nl1Oi_o;
	wire  wire_nl1Ol_o;
	wire  wire_nl1OO_o;
	wire  wire_nli0i_o;
	wire  wire_nli0l_o;
	wire  wire_nli0O_o;
	wire  wire_nli1i_o;
	wire  wire_nli1l_o;
	wire  wire_nli1O_o;
	wire  wire_nliii_o;
	wire  wire_nliil_o;
	wire  wire_nliiO_o;
	wire  wire_nlili_o;
	wire  wire_nlill_o;
	wire  wire_nlilO_o;
	wire  wire_nliOi_o;
	wire  wire_nliOl_o;
	wire  wire_nliOO_o;
	wire  wire_nll0i_o;
	wire  wire_nll0l_o;
	wire  wire_nll0O_o;
	wire  wire_nll1i_o;
	wire  wire_nll1l_o;
	wire  wire_nll1O_o;
	wire  wire_nllii_o;
	wire  wire_nllil_o;
	wire  wire_nlliO_o;
	wire  wire_nllli_o;
	wire  wire_nllll_o;
	wire  wire_nlllO_o;
	wire  wire_nllOi_o;
	wire  wire_nllOl_o;
	wire  wire_nllOO_o;
	wire  wire_nlO0i_o;
	wire  wire_nlO0l_o;
	wire  wire_nlO0O_o;
	wire  wire_nlO1i_o;
	wire  wire_nlO1l_o;
	wire  wire_nlO1O_o;
	wire  nil00i;
	wire  nil00l;
	wire  nil00O;
	wire  nil01i;
	wire  nil01l;
	wire  nil01O;
	wire  nil0ii;
	wire  nil0il;
	wire  nil0iO;
	wire  nil0li;
	wire  nil0ll;
	wire  nil0lO;
	wire  nil0Oi;
	wire  nil0Ol;
	wire  nil0OO;
	wire  nil1ll;
	wire  nil1lO;
	wire  nil1Oi;
	wire  nil1Ol;
	wire  nil1OO;
	wire  nili0i;
	wire  nili0l;
	wire  nili0O;
	wire  nili1i;
	wire  nili1l;
	wire  nili1O;
	wire  niliii;
	wire  niliil;
	wire  niliiO;
	wire  nilili;
	wire  nilill;
	wire  nililO;
	wire  niliOi;
	wire  niliOl;
	wire  niliOO;
	wire  nill0i;
	wire  nill0l;
	wire  nill0O;
	wire  nill1i;
	wire  nill1l;
	wire  nill1O;
	wire  nillii;
	wire  nillil;
	wire  nilliO;
	wire  nillli;
	wire  nillll;
	wire  nilllO;
	wire  nillOi;
	wire  nillOl;
	wire  nillOO;
	wire  nilO0i;
	wire  nilO1i;
	wire  nilO1l;
	wire  nilO1O;
	wire  nilOil;
	wire  niO00O;
	wire  niO1iO;
	wire  niO1Ol;

	initial
		nilO0l49 = 0;
	always @ ( posedge clk)
		  nilO0l49 <= nilO0l50;
	event nilO0l49_event;
	initial
		#1 ->nilO0l49_event;
	always @(nilO0l49_event)
		nilO0l49 <= {1{1'b1}};
	initial
		nilO0l50 = 0;
	always @ ( posedge clk)
		  nilO0l50 <= nilO0l49;
	initial
		nilO0O47 = 0;
	always @ ( posedge clk)
		  nilO0O47 <= nilO0O48;
	event nilO0O47_event;
	initial
		#1 ->nilO0O47_event;
	always @(nilO0O47_event)
		nilO0O47 <= {1{1'b1}};
	initial
		nilO0O48 = 0;
	always @ ( posedge clk)
		  nilO0O48 <= nilO0O47;
	initial
		nilOii45 = 0;
	always @ ( posedge clk)
		  nilOii45 <= nilOii46;
	event nilOii45_event;
	initial
		#1 ->nilOii45_event;
	always @(nilOii45_event)
		nilOii45 <= {1{1'b1}};
	initial
		nilOii46 = 0;
	always @ ( posedge clk)
		  nilOii46 <= nilOii45;
	initial
		nilOiO43 = 0;
	always @ ( posedge clk)
		  nilOiO43 <= nilOiO44;
	event nilOiO43_event;
	initial
		#1 ->nilOiO43_event;
	always @(nilOiO43_event)
		nilOiO43 <= {1{1'b1}};
	initial
		nilOiO44 = 0;
	always @ ( posedge clk)
		  nilOiO44 <= nilOiO43;
	initial
		nilOli41 = 0;
	always @ ( posedge clk)
		  nilOli41 <= nilOli42;
	event nilOli41_event;
	initial
		#1 ->nilOli41_event;
	always @(nilOli41_event)
		nilOli41 <= {1{1'b1}};
	initial
		nilOli42 = 0;
	always @ ( posedge clk)
		  nilOli42 <= nilOli41;
	initial
		nilOll39 = 0;
	always @ ( posedge clk)
		  nilOll39 <= nilOll40;
	event nilOll39_event;
	initial
		#1 ->nilOll39_event;
	always @(nilOll39_event)
		nilOll39 <= {1{1'b1}};
	initial
		nilOll40 = 0;
	always @ ( posedge clk)
		  nilOll40 <= nilOll39;
	initial
		nilOlO37 = 0;
	always @ ( posedge clk)
		  nilOlO37 <= nilOlO38;
	event nilOlO37_event;
	initial
		#1 ->nilOlO37_event;
	always @(nilOlO37_event)
		nilOlO37 <= {1{1'b1}};
	initial
		nilOlO38 = 0;
	always @ ( posedge clk)
		  nilOlO38 <= nilOlO37;
	initial
		nilOOi35 = 0;
	always @ ( posedge clk)
		  nilOOi35 <= nilOOi36;
	event nilOOi35_event;
	initial
		#1 ->nilOOi35_event;
	always @(nilOOi35_event)
		nilOOi35 <= {1{1'b1}};
	initial
		nilOOi36 = 0;
	always @ ( posedge clk)
		  nilOOi36 <= nilOOi35;
	initial
		nilOOl33 = 0;
	always @ ( posedge clk)
		  nilOOl33 <= nilOOl34;
	event nilOOl33_event;
	initial
		#1 ->nilOOl33_event;
	always @(nilOOl33_event)
		nilOOl33 <= {1{1'b1}};
	initial
		nilOOl34 = 0;
	always @ ( posedge clk)
		  nilOOl34 <= nilOOl33;
	initial
		nilOOO31 = 0;
	always @ ( posedge clk)
		  nilOOO31 <= nilOOO32;
	event nilOOO31_event;
	initial
		#1 ->nilOOO31_event;
	always @(nilOOO31_event)
		nilOOO31 <= {1{1'b1}};
	initial
		nilOOO32 = 0;
	always @ ( posedge clk)
		  nilOOO32 <= nilOOO31;
	initial
		niO00i5 = 0;
	always @ ( posedge clk)
		  niO00i5 <= niO00i6;
	event niO00i5_event;
	initial
		#1 ->niO00i5_event;
	always @(niO00i5_event)
		niO00i5 <= {1{1'b1}};
	initial
		niO00i6 = 0;
	always @ ( posedge clk)
		  niO00i6 <= niO00i5;
	initial
		niO01l7 = 0;
	always @ ( posedge clk)
		  niO01l7 <= niO01l8;
	event niO01l7_event;
	initial
		#1 ->niO01l7_event;
	always @(niO01l7_event)
		niO01l7 <= {1{1'b1}};
	initial
		niO01l8 = 0;
	always @ ( posedge clk)
		  niO01l8 <= niO01l7;
	initial
		niO0ii3 = 0;
	always @ ( posedge clk)
		  niO0ii3 <= niO0ii4;
	event niO0ii3_event;
	initial
		#1 ->niO0ii3_event;
	always @(niO0ii3_event)
		niO0ii3 <= {1{1'b1}};
	initial
		niO0ii4 = 0;
	always @ ( posedge clk)
		  niO0ii4 <= niO0ii3;
	initial
		niO0iO1 = 0;
	always @ ( posedge clk)
		  niO0iO1 <= niO0iO2;
	event niO0iO1_event;
	initial
		#1 ->niO0iO1_event;
	always @(niO0iO1_event)
		niO0iO1 <= {1{1'b1}};
	initial
		niO0iO2 = 0;
	always @ ( posedge clk)
		  niO0iO2 <= niO0iO1;
	initial
		niO10i23 = 0;
	always @ ( posedge clk)
		  niO10i23 <= niO10i24;
	event niO10i23_event;
	initial
		#1 ->niO10i23_event;
	always @(niO10i23_event)
		niO10i23 <= {1{1'b1}};
	initial
		niO10i24 = 0;
	always @ ( posedge clk)
		  niO10i24 <= niO10i23;
	initial
		niO10l21 = 0;
	always @ ( posedge clk)
		  niO10l21 <= niO10l22;
	event niO10l21_event;
	initial
		#1 ->niO10l21_event;
	always @(niO10l21_event)
		niO10l21 <= {1{1'b1}};
	initial
		niO10l22 = 0;
	always @ ( posedge clk)
		  niO10l22 <= niO10l21;
	initial
		niO10O19 = 0;
	always @ ( posedge clk)
		  niO10O19 <= niO10O20;
	event niO10O19_event;
	initial
		#1 ->niO10O19_event;
	always @(niO10O19_event)
		niO10O19 <= {1{1'b1}};
	initial
		niO10O20 = 0;
	always @ ( posedge clk)
		  niO10O20 <= niO10O19;
	initial
		niO11i29 = 0;
	always @ ( posedge clk)
		  niO11i29 <= niO11i30;
	event niO11i29_event;
	initial
		#1 ->niO11i29_event;
	always @(niO11i29_event)
		niO11i29 <= {1{1'b1}};
	initial
		niO11i30 = 0;
	always @ ( posedge clk)
		  niO11i30 <= niO11i29;
	initial
		niO11l27 = 0;
	always @ ( posedge clk)
		  niO11l27 <= niO11l28;
	event niO11l27_event;
	initial
		#1 ->niO11l27_event;
	always @(niO11l27_event)
		niO11l27 <= {1{1'b1}};
	initial
		niO11l28 = 0;
	always @ ( posedge clk)
		  niO11l28 <= niO11l27;
	initial
		niO11O25 = 0;
	always @ ( posedge clk)
		  niO11O25 <= niO11O26;
	event niO11O25_event;
	initial
		#1 ->niO11O25_event;
	always @(niO11O25_event)
		niO11O25 <= {1{1'b1}};
	initial
		niO11O26 = 0;
	always @ ( posedge clk)
		  niO11O26 <= niO11O25;
	initial
		niO1ii17 = 0;
	always @ ( posedge clk)
		  niO1ii17 <= niO1ii18;
	event niO1ii17_event;
	initial
		#1 ->niO1ii17_event;
	always @(niO1ii17_event)
		niO1ii17 <= {1{1'b1}};
	initial
		niO1ii18 = 0;
	always @ ( posedge clk)
		  niO1ii18 <= niO1ii17;
	initial
		niO1il15 = 0;
	always @ ( posedge clk)
		  niO1il15 <= niO1il16;
	event niO1il15_event;
	initial
		#1 ->niO1il15_event;
	always @(niO1il15_event)
		niO1il15 <= {1{1'b1}};
	initial
		niO1il16 = 0;
	always @ ( posedge clk)
		  niO1il16 <= niO1il15;
	initial
		niO1li13 = 0;
	always @ ( posedge clk)
		  niO1li13 <= niO1li14;
	event niO1li13_event;
	initial
		#1 ->niO1li13_event;
	always @(niO1li13_event)
		niO1li13 <= {1{1'b1}};
	initial
		niO1li14 = 0;
	always @ ( posedge clk)
		  niO1li14 <= niO1li13;
	initial
		niO1lO11 = 0;
	always @ ( posedge clk)
		  niO1lO11 <= niO1lO12;
	event niO1lO11_event;
	initial
		#1 ->niO1lO11_event;
	always @(niO1lO11_event)
		niO1lO11 <= {1{1'b1}};
	initial
		niO1lO12 = 0;
	always @ ( posedge clk)
		  niO1lO12 <= niO1lO11;
	initial
		niO1OO10 = 0;
	always @ ( posedge clk)
		  niO1OO10 <= niO1OO9;
	initial
		niO1OO9 = 0;
	always @ ( posedge clk)
		  niO1OO9 <= niO1OO10;
	event niO1OO9_event;
	initial
		#1 ->niO1OO9_event;
	always @(niO1OO9_event)
		niO1OO9 <= {1{1'b1}};
	initial
	begin
		n00OO = 0;
	end
	always @ (clk or wire_n00Ol_PRN or rst)
	begin
		if (wire_n00Ol_PRN == 1'b0) 
		begin
			n00OO <= 1;
		end
		else if  (rst == 1'b1) 
		begin
			n00OO <= 0;
		end
		else if  (wire_n00Ol_ENA == 1'b1) 
		if (clk != n00Ol_clk_prev && clk == 1'b1) 
		begin
			n00OO <= nilOil;
		end
		n00Ol_clk_prev <= clk;
	end
	assign
		wire_n00Ol_ENA = ((ib_force_disparity & tx_data_9_tc[0]) & (~ n00OO)),
		wire_n00Ol_PRN = (nilO0l50 ^ nilO0l49);
	initial
	begin
		n0liO = 0;
		n0lli = 0;
		n0lll = 0;
		n0llO = 0;
		n0lOi = 0;
		n0lOO = 0;
		n0O1l = 0;
		n0O1O = 0;
		n0OiO = 0;
		n0Oll = 0;
		nii0i = 0;
		nii0l = 0;
		nii0O = 0;
		nii1l = 0;
		nii1O = 0;
		niiil = 0;
		niili = 0;
		niill = 0;
		nil0O = 0;
		nil1l = 0;
	end
	always @ (clk or wire_nil0l_PRN or wire_nil0l_CLRN)
	begin
		if (wire_nil0l_PRN == 1'b0) 
		begin
			n0liO <= 1;
			n0lli <= 1;
			n0lll <= 1;
			n0llO <= 1;
			n0lOi <= 1;
			n0lOO <= 1;
			n0O1l <= 1;
			n0O1O <= 1;
			n0OiO <= 1;
			n0Oll <= 1;
			nii0i <= 1;
			nii0l <= 1;
			nii0O <= 1;
			nii1l <= 1;
			nii1O <= 1;
			niiil <= 1;
			niili <= 1;
			niill <= 1;
			nil0O <= 1;
			nil1l <= 1;
		end
		else if  (wire_nil0l_CLRN == 1'b0) 
		begin
			n0liO <= 0;
			n0lli <= 0;
			n0lll <= 0;
			n0llO <= 0;
			n0lOi <= 0;
			n0lOO <= 0;
			n0O1l <= 0;
			n0O1O <= 0;
			n0OiO <= 0;
			n0Oll <= 0;
			nii0i <= 0;
			nii0l <= 0;
			nii0O <= 0;
			nii1l <= 0;
			nii1O <= 0;
			niiil <= 0;
			niili <= 0;
			niill <= 0;
			nil0O <= 0;
			nil1l <= 0;
		end
		else 
		if (clk != nil0l_clk_prev && clk == 1'b1) 
		begin
			n0liO <= nii1l;
			n0lli <= nii1O;
			n0lll <= nii0i;
			n0llO <= nii0l;
			n0lOi <= nii0O;
			n0lOO <= niiil;
			n0O1l <= niili;
			n0O1O <= niill;
			n0OiO <= nil1l;
			n0Oll <= nil0O;
			nii0i <= wire_nilll_o;
			nii0l <= wire_nillO_o;
			nii0O <= wire_nilOi_o;
			nii1l <= wire_niliO_o;
			nii1O <= wire_nilli_o;
			niiil <= wire_nilOO_o;
			niili <= wire_niO1l_o;
			niill <= wire_niO1O_o;
			nil0O <= wire_niOll_o;
			nil1l <= wire_niOiO_o;
		end
		nil0l_clk_prev <= clk;
	end
	assign
		wire_nil0l_CLRN = (nilOli42 ^ nilOli41),
		wire_nil0l_PRN = ((nilOiO44 ^ nilOiO43) & (~ rst));
	initial
	begin
		n00lO = 0;
		n00Oi = 0;
		n0i0i = 0;
		n0i0l = 0;
		n0i0O = 0;
		n0i1l = 0;
		n0i1O = 0;
		n0iii = 0;
		n0iil = 0;
		n0iiO = 0;
		n0ili = 0;
		n0ill = 0;
		n0ilO = 0;
		n0iOi = 0;
		n0iOl = 0;
		n0iOO = 0;
		n0l0i = 0;
		n0l0l = 0;
		n0l0O = 0;
		n0l1i = 0;
		n0l1l = 0;
		n0l1O = 0;
		n0lii = 0;
		n0lil = 0;
		n0lOl = 0;
		n0O0i = 0;
		n0O0l = 0;
		n0O0O = 0;
		n0O1i = 0;
		n0Oii = 0;
		n0Oil = 0;
		n0Oli = 0;
		n0OlO = 0;
		n0OOi = 0;
		n0OOl = 0;
		n0OOO = 0;
		ni0OO = 0;
		ni11i = 0;
		ni11l = 0;
		ni11O = 0;
		nii1i = 0;
		niiii = 0;
		niiiO = 0;
		niilO = 0;
		niiOi = 0;
		niiOl = 0;
		niiOO = 0;
		nil0i = 0;
		nil1i = 0;
	end
	always @ (clk or wire_nil1O_PRN or wire_nil1O_CLRN)
	begin
		if (wire_nil1O_PRN == 1'b0) 
		begin
			n00lO <= 1;
			n00Oi <= 1;
			n0i0i <= 1;
			n0i0l <= 1;
			n0i0O <= 1;
			n0i1l <= 1;
			n0i1O <= 1;
			n0iii <= 1;
			n0iil <= 1;
			n0iiO <= 1;
			n0ili <= 1;
			n0ill <= 1;
			n0ilO <= 1;
			n0iOi <= 1;
			n0iOl <= 1;
			n0iOO <= 1;
			n0l0i <= 1;
			n0l0l <= 1;
			n0l0O <= 1;
			n0l1i <= 1;
			n0l1l <= 1;
			n0l1O <= 1;
			n0lii <= 1;
			n0lil <= 1;
			n0lOl <= 1;
			n0O0i <= 1;
			n0O0l <= 1;
			n0O0O <= 1;
			n0O1i <= 1;
			n0Oii <= 1;
			n0Oil <= 1;
			n0Oli <= 1;
			n0OlO <= 1;
			n0OOi <= 1;
			n0OOl <= 1;
			n0OOO <= 1;
			ni0OO <= 1;
			ni11i <= 1;
			ni11l <= 1;
			ni11O <= 1;
			nii1i <= 1;
			niiii <= 1;
			niiiO <= 1;
			niilO <= 1;
			niiOi <= 1;
			niiOl <= 1;
			niiOO <= 1;
			nil0i <= 1;
			nil1i <= 1;
		end
		else if  (wire_nil1O_CLRN == 1'b0) 
		begin
			n00lO <= 0;
			n00Oi <= 0;
			n0i0i <= 0;
			n0i0l <= 0;
			n0i0O <= 0;
			n0i1l <= 0;
			n0i1O <= 0;
			n0iii <= 0;
			n0iil <= 0;
			n0iiO <= 0;
			n0ili <= 0;
			n0ill <= 0;
			n0ilO <= 0;
			n0iOi <= 0;
			n0iOl <= 0;
			n0iOO <= 0;
			n0l0i <= 0;
			n0l0l <= 0;
			n0l0O <= 0;
			n0l1i <= 0;
			n0l1l <= 0;
			n0l1O <= 0;
			n0lii <= 0;
			n0lil <= 0;
			n0lOl <= 0;
			n0O0i <= 0;
			n0O0l <= 0;
			n0O0O <= 0;
			n0O1i <= 0;
			n0Oii <= 0;
			n0Oil <= 0;
			n0Oli <= 0;
			n0OlO <= 0;
			n0OOi <= 0;
			n0OOl <= 0;
			n0OOO <= 0;
			ni0OO <= 0;
			ni11i <= 0;
			ni11l <= 0;
			ni11O <= 0;
			nii1i <= 0;
			niiii <= 0;
			niiiO <= 0;
			niilO <= 0;
			niiOi <= 0;
			niiOl <= 0;
			niiOO <= 0;
			nil0i <= 0;
			nil1i <= 0;
		end
		else 
		if (clk != nil1O_clk_prev && clk == 1'b1) 
		begin
			n00lO <= rev_loopbk;
			n00Oi <= wire_n0i1i_dataout;
			n0i0i <= tx_ctl_tc[0];
			n0i0l <= tx_ctl_tc[1];
			n0i0O <= tx_data_tc[0];
			n0i1l <= tx_data_9_tc[0];
			n0i1O <= tx_data_9_tc[1];
			n0iii <= tx_data_tc[1];
			n0iil <= tx_data_tc[2];
			n0iiO <= tx_data_tc[3];
			n0ili <= tx_data_tc[4];
			n0ill <= tx_data_tc[5];
			n0ilO <= tx_data_tc[6];
			n0iOi <= tx_data_tc[7];
			n0iOl <= tx_data_tc[8];
			n0iOO <= tx_data_tc[9];
			n0l0i <= tx_data_tc[13];
			n0l0l <= tx_data_tc[14];
			n0l0O <= tx_data_tc[15];
			n0l1i <= tx_data_tc[10];
			n0l1l <= tx_data_tc[11];
			n0l1O <= tx_data_tc[12];
			n0lii <= ni11O;
			n0lil <= nii1i;
			n0lOl <= niiii;
			n0O0i <= niilO;
			n0O0l <= niiOi;
			n0O0O <= niiOl;
			n0O1i <= niiiO;
			n0Oii <= niiOO;
			n0Oil <= nil1i;
			n0Oli <= nil0i;
			n0OlO <= n0OOi;
			n0OOi <= rensymswap_tx;
			n0OOl <= n0OOO;
			n0OOO <= renbitrev_tx;
			ni0OO <= n00lO;
			ni11i <= ni11l;
			ni11l <= (renpolinv_tx & enpolinv_tx);
			ni11O <= wire_nilii_o;
			nii1i <= wire_nilil_o;
			niiii <= wire_nilOl_o;
			niiiO <= wire_niO1i_o;
			niilO <= wire_niO0i_o;
			niiOi <= wire_niO0l_o;
			niiOl <= wire_niO0O_o;
			niiOO <= wire_niOii_o;
			nil0i <= wire_niOli_o;
			nil1i <= wire_niOil_o;
		end
		nil1O_clk_prev <= clk;
	end
	assign
		wire_nil1O_CLRN = ((nilOii46 ^ nilOii45) & (~ rst)),
		wire_nil1O_PRN = (nilO0O48 ^ nilO0O47);
	assign		wire_n00i_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[11] : wire_ni0l_dataout;
	assign		wire_n00l_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[12] : wire_ni0O_dataout;
	assign		wire_n00O_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[13] : wire_niii_dataout;
	assign		wire_n01i_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[8] : wire_ni1l_dataout;
	assign		wire_n01l_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[9] : wire_ni1O_dataout;
	assign		wire_n01O_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[10] : wire_ni0i_dataout;
	assign		wire_n0i1i_dataout = (cascaded_8b10b_en === 1'b1) ? wire_nllllO_dataout : wire_nl0i1l_dataout;
	assign		wire_n0ii_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[14] : wire_niil_dataout;
	assign		wire_n0il_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[15] : wire_niiO_dataout;
	and(wire_n0iO_dataout, wire_nili_dataout, ~(niO1Ol));
	and(wire_n0li_dataout, wire_nill_dataout, ~(niO1Ol));
	and(wire_n0ll_dataout, wire_nilO_dataout, ~(niO1Ol));
	and(wire_n0lO_dataout, wire_niOi_dataout, ~(niO1Ol));
	assign		wire_n0O_dataout = (rendec_data_sel_tx === 1'b1) ? tx_ctl_tc[0] : tx_ctl_ts;
	or(wire_n0Oi_dataout, wire_niOl_dataout, niO1Ol);
	and(wire_n0Ol_dataout, wire_niOO_dataout, ~(niO1Ol));
	or(wire_n0OO_dataout, wire_nl1i_dataout, niO1Ol);
	and(wire_n10i_dataout, tx_data_tc[12], rendec_data_sel_tx);
	and(wire_n10l_dataout, tx_data_tc[13], rendec_data_sel_tx);
	and(wire_n10O_dataout, tx_data_tc[14], rendec_data_sel_tx);
	and(wire_n11i_dataout, tx_data_tc[9], rendec_data_sel_tx);
	and(wire_n11l_dataout, tx_data_tc[10], rendec_data_sel_tx);
	and(wire_n11O_dataout, tx_data_tc[11], rendec_data_sel_tx);
	and(wire_n1ii_dataout, tx_data_tc[15], rendec_data_sel_tx);
	assign		wire_n1il_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[0] : wire_n0iO_dataout;
	assign		wire_n1iO_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[1] : wire_n0li_dataout;
	assign		wire_n1li_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[2] : wire_n0ll_dataout;
	assign		wire_n1ll_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[3] : wire_n0lO_dataout;
	assign		wire_n1lO_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[4] : wire_n0Oi_dataout;
	assign		wire_n1Oi_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[5] : wire_n0Ol_dataout;
	assign		wire_n1Ol_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[6] : wire_n0OO_dataout;
	assign		wire_n1OO_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[7] : wire_ni1i_dataout;
	and(wire_ni00i_dataout, wire_nl0i1l_dataout, ~(((rforce_disp & txd_extend_tc[1]) & tx_data_9_tc[1])));
	or(wire_ni01O_dataout, wire_ni00i_dataout, ((rforce_disp & (~ txd_extend_tc[1])) & tx_data_9_tc[1]));
	and(wire_ni0i_dataout, wire_nl0l_dataout, ~(niO1Ol));
	or(wire_ni0iO_dataout, wire_ni0li_dataout, ((rforce_disp & (~ txd_extend_tc[0])) & tx_data_9_tc[0]));
	and(wire_ni0l_dataout, wire_nl0O_dataout, ~(niO1Ol));
	and(wire_ni0li_dataout, n00Oi, ~(((rforce_disp & txd_extend_tc[0]) & tx_data_9_tc[0])));
	and(wire_ni0O_dataout, wire_nlii_dataout, ~(niO1Ol));
	and(wire_ni1i_dataout, wire_nl1l_dataout, ~(niO1Ol));
	assign		wire_ni1ii_dataout = (cascaded_8b10b_en === 1'b1) ? wire_ni0iO_dataout : wire_ni1iO_dataout;
	assign		wire_ni1il_dataout = (cascaded_8b10b_en === 1'b1) ? wire_ni01O_dataout : wire_nl0i1l_dataout;
	assign		wire_ni1iO_dataout = (ib_force_disparity === 1'b1) ? (((~ n00OO) & tx_data_9_tc[0]) | n00Oi) : wire_ni1li_dataout;
	and(wire_ni1l_dataout, wire_nl1O_dataout, ~(niO1Ol));
	or(wire_ni1li_dataout, wire_ni1ll_dataout, ((rforce_disp & (~ txd_extend_tc[0])) & tx_data_9_tc[0]));
	and(wire_ni1ll_dataout, n00Oi, ~(((rforce_disp & txd_extend_tc[0]) & tx_data_9_tc[0])));
	and(wire_ni1O_dataout, wire_nl0i_dataout, ~(niO1Ol));
	and(wire_nii_dataout, tx_ctl_tc[1], rendec_data_sel_tx);
	and(wire_niii_dataout, wire_nlil_dataout, ~(niO1Ol));
	and(wire_niil_dataout, wire_nliO_dataout, ~(niO1Ol));
	and(wire_niiO_dataout, wire_nlli_dataout, ~(niO1Ol));
	assign		wire_nil_dataout = (cascaded_8b10b_en === 1'b1) ? tx_ctl_tc[0] : wire_nli_dataout;
	or(wire_nili_dataout, wire_nlOii_dataout, niO1iO);
	and(wire_nill_dataout, wire_nlOil_dataout, ~(niO1iO));
	or(wire_nilO_dataout, wire_nlOiO_dataout, niO1iO);
	assign		wire_niO_dataout = (cascaded_8b10b_en === 1'b1) ? tx_ctl_tc[1] : wire_nll_dataout;
	and(wire_niOi_dataout, wire_nlOli_dataout, ~(niO1iO));
	and(wire_niOl_dataout, wire_nlOll_dataout, ~(niO1iO));
	and(wire_niOO_dataout, wire_nlOlO_dataout, ~(niO1iO));
	and(wire_nl0i_dataout, wire_n11i_dataout, ~(niO1iO));
	or(wire_nl0i0l_dataout, wire_nl0i0O_dataout, nili1O);
	and(wire_nl0i0O_dataout, (~ nili0O), ~(wire_n1OO_dataout));
	assign		wire_nl0i1l_dataout = ((nili1i | (wire_n1OO_dataout & nili0O)) === 1'b1) ? (~ wire_nl11iO_dataout) : wire_nl11iO_dataout;
	assign		wire_nl0ili_dataout = (nili1i === 1'b1) ? (~ wire_n1Ol_dataout) : wire_n1Ol_dataout;
	and(wire_nl0ilO_dataout, wire_n1Oi_dataout, ~(nili1O));
	assign		wire_nl0iOi_dataout = (nili0i === 1'b1) ? (~ wire_nl0ilO_dataout) : wire_nl0ilO_dataout;
	assign		wire_nl0iOl_dataout = (nili0i === 1'b1) ? (~ wire_nl0ili_dataout) : wire_nl0ili_dataout;
	assign		wire_nl0iOO_dataout = (nili0i === 1'b1) ? (~ wire_n1OO_dataout) : wire_n1OO_dataout;
	and(wire_nl0l_dataout, wire_n11l_dataout, ~(niO1iO));
	assign		wire_nl0l1i_dataout = (nili0i === 1'b1) ? (~ wire_nl0i0l_dataout) : wire_nl0i0l_dataout;
	assign		wire_nl0lii_dataout = (r8b10b_enc_ibm_en === 1'b1) ? niliii : wire_nil_dataout;
	and(wire_nl0O_dataout, wire_n11O_dataout, ~(niO1iO));
	assign		wire_nl10iO_dataout = (nil1OO === 1'b1) ? (~ wire_n1il_dataout) : wire_n1il_dataout;
	assign		wire_nl10li_dataout = (nil1OO === 1'b1) ? (~ wire_nl1O1l_dataout) : wire_nl1O1l_dataout;
	assign		wire_nl10ll_dataout = (nil1OO === 1'b1) ? (~ wire_nl1lll_dataout) : wire_nl1lll_dataout;
	assign		wire_nl10lO_dataout = (nil1OO === 1'b1) ? (~ wire_nl1lli_dataout) : wire_nl1lli_dataout;
	assign		wire_nl10Oi_dataout = (nil1OO === 1'b1) ? (~ nil00O) : nil00O;
	assign		wire_nl10Ol_dataout = (nil1OO === 1'b1) ? (~ nil01O) : nil01O;
	assign		wire_nl11iO_dataout = (((nil0il | ((wire_nl1O1O_dataout | nil0ll) | nil0li)) | nil01i) === 1'b1) ? (~ wire_ni1ii_dataout) : wire_ni1ii_dataout;
	or(wire_nl1i_dataout, wire_nlOOi_dataout, niO1iO);
	or(wire_nl1l_dataout, wire_nlOOl_dataout, niO1iO);
	assign		wire_nl1lli_dataout = (nil0li === 1'b1) ? (~ wire_n1ll_dataout) : wire_n1ll_dataout;
	assign		wire_nl1lll_dataout = (((wire_n1lO_dataout & (wire_n1ll_dataout & ((~ wire_n1li_dataout) & ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout))))) | nil0ll) === 1'b1) ? (~ wire_n1li_dataout) : wire_n1li_dataout;
	and(wire_nl1O_dataout, wire_nlOOO_dataout, ~(niO1iO));
	assign		wire_nl1O1l_dataout = (nil0lO === 1'b1) ? (~ wire_n1iO_dataout) : wire_n1iO_dataout;
	assign		wire_nl1O1O_dataout = (r8b10b_enc_ibm_en === 1'b1) ? niliii : wire_nil_dataout;
	and(wire_nli_dataout, wire_n0O_dataout, ~(niO00O));
	and(wire_nlii_dataout, wire_n10i_dataout, ~(niO1iO));
	assign		wire_nlii0i_dataout = (((nill0l | ((wire_nll1Oi_dataout | nillil) | nillii)) | niliOi) === 1'b1) ? (~ wire_ni1il_dataout) : wire_ni1il_dataout;
	and(wire_nlil_dataout, wire_n10l_dataout, ~(niO1iO));
	assign		wire_nlil0i_dataout = (nililO === 1'b1) ? (~ wire_n01i_dataout) : wire_n01i_dataout;
	assign		wire_nlil0l_dataout = (nililO === 1'b1) ? (~ wire_nll1lO_dataout) : wire_nll1lO_dataout;
	assign		wire_nlil0O_dataout = (nililO === 1'b1) ? (~ wire_nll10O_dataout) : wire_nll10O_dataout;
	assign		wire_nlilii_dataout = (nililO === 1'b1) ? (~ wire_nll10l_dataout) : wire_nll10l_dataout;
	assign		wire_nlilil_dataout = (nililO === 1'b1) ? (~ nill1O) : nill1O;
	assign		wire_nliliO_dataout = (nililO === 1'b1) ? (~ niliOO) : niliOO;
	and(wire_nliO_dataout, wire_n10O_dataout, ~(niO1iO));
	and(wire_nll_dataout, wire_nii_dataout, ~(niO00O));
	assign		wire_nll10l_dataout = (nillii === 1'b1) ? (~ wire_n00i_dataout) : wire_n00i_dataout;
	assign		wire_nll10O_dataout = (((wire_n00l_dataout & (wire_n00i_dataout & ((~ wire_n01O_dataout) & ((~ wire_n01l_dataout) & (~ wire_n01i_dataout))))) | nillil) === 1'b1) ? (~ wire_n01O_dataout) : wire_n01O_dataout;
	assign		wire_nll1lO_dataout = (nilliO === 1'b1) ? (~ wire_n01l_dataout) : wire_n01l_dataout;
	assign		wire_nll1Oi_dataout = (r8b10b_enc_ibm_en === 1'b1) ? nilO0i : wire_niO_dataout;
	and(wire_nlli_dataout, wire_n1ii_dataout, ~(niO1iO));
	assign		wire_nllllO_dataout = ((nillOi | (wire_n0il_dataout & nilO1O)) === 1'b1) ? (~ wire_nlii0i_dataout) : wire_nlii0i_dataout;
	or(wire_nlllOO_dataout, wire_nllO1i_dataout, nillOO);
	assign		wire_nllO0l_dataout = (nillOi === 1'b1) ? (~ wire_n0ii_dataout) : wire_n0ii_dataout;
	and(wire_nllO1i_dataout, (~ nilO1O), ~(wire_n0il_dataout));
	and(wire_nllOii_dataout, wire_n00O_dataout, ~(nillOO));
	assign		wire_nllOil_dataout = (nilO1i === 1'b1) ? (~ wire_nllOii_dataout) : wire_nllOii_dataout;
	assign		wire_nllOiO_dataout = (nilO1i === 1'b1) ? (~ wire_nllO0l_dataout) : wire_nllO0l_dataout;
	assign		wire_nllOli_dataout = (nilO1i === 1'b1) ? (~ wire_n0il_dataout) : wire_n0il_dataout;
	assign		wire_nllOll_dataout = (nilO1i === 1'b1) ? (~ wire_nlllOO_dataout) : wire_nlllOO_dataout;
	assign		wire_nlO11l_dataout = (r8b10b_enc_ibm_en === 1'b1) ? nilO0i : wire_niO_dataout;
	assign		wire_nlOii_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[0] : tx_data_ts[0];
	assign		wire_nlOil_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[1] : tx_data_ts[1];
	assign		wire_nlOiO_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[2] : tx_data_ts[2];
	assign		wire_nlOli_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[3] : tx_data_ts[3];
	assign		wire_nlOll_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[4] : tx_data_ts[4];
	assign		wire_nlOlO_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[5] : tx_data_ts[5];
	assign		wire_nlOOi_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[6] : tx_data_ts[6];
	assign		wire_nlOOl_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[7] : tx_data_ts[7];
	and(wire_nlOOO_dataout, tx_data_tc[8], rendec_data_sel_tx);
	oper_mux   n000i
	( 
	.data({{4{tx_data_pg[12]}}, rev_loop_data[12], wire_nlil0O_dataout, tx_data_pg[12], wire_nlil0O_dataout, {4{tx_data_pg[12]}}, rev_loop_data[12], tx_data_tc[10], tx_data_pg[12], tx_data_tc[10]}),
	.o(wire_n000i_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n000i.width_data = 16,
		n000i.width_sel = 4;
	oper_mux   n000l
	( 
	.data({{4{tx_data_pg[13]}}, rev_loop_data[13], wire_nlilii_dataout, tx_data_pg[13], wire_nlilii_dataout, {4{tx_data_pg[13]}}, rev_loop_data[13], tx_data_tc[11], tx_data_pg[13], tx_data_tc[11]}),
	.o(wire_n000l_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n000l.width_data = 16,
		n000l.width_sel = 4;
	oper_mux   n000O
	( 
	.data({{4{tx_data_pg[14]}}, rev_loop_data[14], wire_nlilil_dataout, tx_data_pg[14], wire_nlilil_dataout, {4{tx_data_pg[14]}}, rev_loop_data[14], tx_data_tc[12], tx_data_pg[14], tx_data_tc[12]}),
	.o(wire_n000O_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n000O.width_data = 16,
		n000O.width_sel = 4;
	oper_mux   n001i
	( 
	.data({{4{tx_data_pg[9]}}, rev_loop_data[9], wire_nl0l1i_dataout, tx_data_pg[9], wire_nl0l1i_dataout, {4{tx_data_pg[9]}}, rev_loop_data[9], tx_data_9_tc[0], tx_data_pg[9], tx_data_9_tc[0]}),
	.o(wire_n001i_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n001i.width_data = 16,
		n001i.width_sel = 4;
	oper_mux   n001l
	( 
	.data({{4{tx_data_pg[10]}}, rev_loop_data[10], wire_nlil0i_dataout, tx_data_pg[10], wire_nlil0i_dataout, {4{tx_data_pg[10]}}, rev_loop_data[10], tx_data_tc[8], tx_data_pg[10], tx_data_tc[8]}),
	.o(wire_n001l_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n001l.width_data = 16,
		n001l.width_sel = 4;
	oper_mux   n001O
	( 
	.data({{4{tx_data_pg[11]}}, rev_loop_data[11], wire_nlil0l_dataout, tx_data_pg[11], wire_nlil0l_dataout, {4{tx_data_pg[11]}}, rev_loop_data[11], tx_data_tc[9], tx_data_pg[11], tx_data_tc[9]}),
	.o(wire_n001O_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n001O.width_data = 16,
		n001O.width_sel = 4;
	oper_mux   n00ii
	( 
	.data({{4{tx_data_pg[15]}}, rev_loop_data[15], wire_nliliO_dataout, tx_data_pg[15], wire_nliliO_dataout, {4{tx_data_pg[15]}}, rev_loop_data[15], tx_data_tc[13], tx_data_pg[15], tx_data_tc[13]}),
	.o(wire_n00ii_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n00ii.width_data = 16,
		n00ii.width_sel = 4;
	oper_mux   n00il
	( 
	.data({{4{tx_data_pg[16]}}, rev_loop_data[16], wire_nllOil_dataout, tx_data_pg[16], wire_nllOil_dataout, {4{tx_data_pg[16]}}, rev_loop_data[16], tx_data_tc[14], tx_data_pg[16], tx_data_tc[14]}),
	.o(wire_n00il_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n00il.width_data = 16,
		n00il.width_sel = 4;
	oper_mux   n00iO
	( 
	.data({{4{tx_data_pg[17]}}, rev_loop_data[17], wire_nllOiO_dataout, tx_data_pg[17], wire_nllOiO_dataout, {4{tx_data_pg[17]}}, rev_loop_data[17], tx_data_tc[15], tx_data_pg[17], tx_data_tc[15]}),
	.o(wire_n00iO_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n00iO.width_data = 16,
		n00iO.width_sel = 4;
	oper_mux   n00li
	( 
	.data({{4{tx_data_pg[18]}}, rev_loop_data[18], wire_nllOli_dataout, tx_data_pg[18], wire_nllOli_dataout, {4{tx_data_pg[18]}}, rev_loop_data[18], tx_ctl_tc[1], tx_data_pg[18], tx_ctl_tc[1]}),
	.o(wire_n00li_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n00li.width_data = 16,
		n00li.width_sel = 4;
	oper_mux   n00ll
	( 
	.data({{4{tx_data_pg[19]}}, rev_loop_data[19], wire_nllOll_dataout, tx_data_pg[19], wire_nllOll_dataout, {4{tx_data_pg[19]}}, rev_loop_data[19], tx_data_9_tc[1], tx_data_pg[19], tx_data_9_tc[1]}),
	.o(wire_n00ll_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n00ll.width_data = 16,
		n00ll.width_sel = 4;
	oper_mux   n01ii
	( 
	.data({{4{tx_data_pg[0]}}, rev_loop_data[0], wire_nl10iO_dataout, tx_data_pg[0], wire_nl10iO_dataout, {4{tx_data_pg[0]}}, rev_loop_data[0], tx_data_tc[0], tx_data_pg[0], tx_data_tc[0]}),
	.o(wire_n01ii_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01ii.width_data = 16,
		n01ii.width_sel = 4;
	oper_mux   n01il
	( 
	.data({{4{tx_data_pg[1]}}, rev_loop_data[1], wire_nl10li_dataout, tx_data_pg[1], wire_nl10li_dataout, {4{tx_data_pg[1]}}, rev_loop_data[1], tx_data_tc[1], tx_data_pg[1], tx_data_tc[1]}),
	.o(wire_n01il_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01il.width_data = 16,
		n01il.width_sel = 4;
	oper_mux   n01iO
	( 
	.data({{4{tx_data_pg[2]}}, rev_loop_data[2], wire_nl10ll_dataout, tx_data_pg[2], wire_nl10ll_dataout, {4{tx_data_pg[2]}}, rev_loop_data[2], tx_data_tc[2], tx_data_pg[2], tx_data_tc[2]}),
	.o(wire_n01iO_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01iO.width_data = 16,
		n01iO.width_sel = 4;
	oper_mux   n01li
	( 
	.data({{4{tx_data_pg[3]}}, rev_loop_data[3], wire_nl10lO_dataout, tx_data_pg[3], wire_nl10lO_dataout, {4{tx_data_pg[3]}}, rev_loop_data[3], tx_data_tc[3], tx_data_pg[3], tx_data_tc[3]}),
	.o(wire_n01li_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01li.width_data = 16,
		n01li.width_sel = 4;
	oper_mux   n01ll
	( 
	.data({{4{tx_data_pg[4]}}, rev_loop_data[4], wire_nl10Oi_dataout, tx_data_pg[4], wire_nl10Oi_dataout, {4{tx_data_pg[4]}}, rev_loop_data[4], tx_data_tc[4], tx_data_pg[4], tx_data_tc[4]}),
	.o(wire_n01ll_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01ll.width_data = 16,
		n01ll.width_sel = 4;
	oper_mux   n01lO
	( 
	.data({{4{tx_data_pg[5]}}, rev_loop_data[5], wire_nl10Ol_dataout, tx_data_pg[5], wire_nl10Ol_dataout, {4{tx_data_pg[5]}}, rev_loop_data[5], tx_data_tc[5], tx_data_pg[5], tx_data_tc[5]}),
	.o(wire_n01lO_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01lO.width_data = 16,
		n01lO.width_sel = 4;
	oper_mux   n01Oi
	( 
	.data({{4{tx_data_pg[6]}}, rev_loop_data[6], wire_nl0iOi_dataout, tx_data_pg[6], wire_nl0iOi_dataout, {4{tx_data_pg[6]}}, rev_loop_data[6], tx_data_tc[6], tx_data_pg[6], tx_data_tc[6]}),
	.o(wire_n01Oi_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01Oi.width_data = 16,
		n01Oi.width_sel = 4;
	oper_mux   n01Ol
	( 
	.data({{4{tx_data_pg[7]}}, rev_loop_data[7], wire_nl0iOl_dataout, tx_data_pg[7], wire_nl0iOl_dataout, {4{tx_data_pg[7]}}, rev_loop_data[7], tx_data_tc[7], tx_data_pg[7], tx_data_tc[7]}),
	.o(wire_n01Ol_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01Ol.width_data = 16,
		n01Ol.width_sel = 4;
	oper_mux   n01OO
	( 
	.data({{4{tx_data_pg[8]}}, rev_loop_data[8], wire_nl0iOO_dataout, tx_data_pg[8], wire_nl0iOO_dataout, {4{tx_data_pg[8]}}, rev_loop_data[8], tx_ctl_tc[1], tx_data_pg[8], tx_ctl_tc[0]}),
	.o(wire_n01OO_o),
	.sel({endec, prbs_en, rrev_loopbk, ni0OO}));
	defparam
		n01OO.width_data = 16,
		n01OO.width_sel = 4;
	oper_mux   nilii
	( 
	.data({wire_niOlO_o, wire_nl01l_o, wire_nliii_o, wire_nlllO_o}),
	.o(wire_nilii_o),
	.sel({doublewidth, dwidth}));
	defparam
		nilii.width_data = 4,
		nilii.width_sel = 2;
	oper_mux   nilil
	( 
	.data({wire_niOOi_o, wire_nl01O_o, wire_nliil_o, wire_nllOi_o}),
	.o(wire_nilil_o),
	.sel({doublewidth, dwidth}));
	defparam
		nilil.width_data = 4,
		nilil.width_sel = 2;
	oper_mux   niliO
	( 
	.data({wire_niOOl_o, wire_nl00i_o, wire_nliiO_o, wire_nllOl_o}),
	.o(wire_niliO_o),
	.sel({doublewidth, dwidth}));
	defparam
		niliO.width_data = 4,
		niliO.width_sel = 2;
	oper_mux   nilli
	( 
	.data({wire_niOOO_o, wire_nl00l_o, wire_nlili_o, wire_nllOO_o}),
	.o(wire_nilli_o),
	.sel({doublewidth, dwidth}));
	defparam
		nilli.width_data = 4,
		nilli.width_sel = 2;
	oper_mux   nilll
	( 
	.data({wire_nl11i_o, wire_nl00O_o, wire_nlill_o, wire_nlO1i_o}),
	.o(wire_nilll_o),
	.sel({doublewidth, dwidth}));
	defparam
		nilll.width_data = 4,
		nilll.width_sel = 2;
	oper_mux   nillO
	( 
	.data({wire_nl11l_o, wire_nl0ii_o, wire_nlilO_o, wire_nlO1l_o}),
	.o(wire_nillO_o),
	.sel({doublewidth, dwidth}));
	defparam
		nillO.width_data = 4,
		nillO.width_sel = 2;
	oper_mux   nilOi
	( 
	.data({wire_nl11O_o, wire_nl0il_o, wire_nliOi_o, wire_nlO1O_o}),
	.o(wire_nilOi_o),
	.sel({doublewidth, dwidth}));
	defparam
		nilOi.width_data = 4,
		nilOi.width_sel = 2;
	oper_mux   nilOl
	( 
	.data({wire_nl10i_o, wire_nl0iO_o, wire_nliOl_o, wire_nlO0i_o}),
	.o(wire_nilOl_o),
	.sel({doublewidth, dwidth}));
	defparam
		nilOl.width_data = 4,
		nilOl.width_sel = 2;
	oper_mux   nilOO
	( 
	.data({wire_nl10l_o, wire_nl0li_o, wire_nliOO_o, wire_nlO0l_o}),
	.o(wire_nilOO_o),
	.sel({doublewidth, dwidth}));
	defparam
		nilOO.width_data = 4,
		nilOO.width_sel = 2;
	oper_mux   niO0i
	( 
	.data({wire_nl1iO_o, wire_nl0Ol_o, {2{wire_nll0i_o}}}),
	.o(wire_niO0i_o),
	.sel({doublewidth, dwidth}));
	defparam
		niO0i.width_data = 4,
		niO0i.width_sel = 2;
	oper_mux   niO0l
	( 
	.data({wire_nl1li_o, wire_nl0OO_o, {2{wire_nll0l_o}}}),
	.o(wire_niO0l_o),
	.sel({doublewidth, dwidth}));
	defparam
		niO0l.width_data = 4,
		niO0l.width_sel = 2;
	oper_mux   niO0O
	( 
	.data({wire_nl1ll_o, wire_nli1i_o, {2{wire_nll0O_o}}}),
	.o(wire_niO0O_o),
	.sel({doublewidth, dwidth}));
	defparam
		niO0O.width_data = 4,
		niO0O.width_sel = 2;
	oper_mux   niO1i
	( 
	.data({wire_nl10O_o, wire_nl0ll_o, wire_nll1i_o, wire_nlO0O_o}),
	.o(wire_niO1i_o),
	.sel({doublewidth, dwidth}));
	defparam
		niO1i.width_data = 4,
		niO1i.width_sel = 2;
	oper_mux   niO1l
	( 
	.data({wire_nl1ii_o, wire_nl0lO_o, {2{wire_nll1l_o}}}),
	.o(wire_niO1l_o),
	.sel({doublewidth, dwidth}));
	defparam
		niO1l.width_data = 4,
		niO1l.width_sel = 2;
	oper_mux   niO1O
	( 
	.data({wire_nl1il_o, wire_nl0Oi_o, {2{wire_nll1O_o}}}),
	.o(wire_niO1O_o),
	.sel({doublewidth, dwidth}));
	defparam
		niO1O.width_data = 4,
		niO1O.width_sel = 2;
	oper_mux   niOii
	( 
	.data({wire_nl1lO_o, wire_nli1l_o, {2{wire_nllii_o}}}),
	.o(wire_niOii_o),
	.sel({doublewidth, dwidth}));
	defparam
		niOii.width_data = 4,
		niOii.width_sel = 2;
	oper_mux   niOil
	( 
	.data({wire_nl1Oi_o, wire_nli1O_o, {2{wire_nllil_o}}}),
	.o(wire_niOil_o),
	.sel({doublewidth, dwidth}));
	defparam
		niOil.width_data = 4,
		niOil.width_sel = 2;
	oper_mux   niOiO
	( 
	.data({wire_nl1Ol_o, wire_nli0i_o, {2{wire_nlliO_o}}}),
	.o(wire_niOiO_o),
	.sel({doublewidth, dwidth}));
	defparam
		niOiO.width_data = 4,
		niOiO.width_sel = 2;
	oper_mux   niOli
	( 
	.data({wire_nl1OO_o, wire_nli0l_o, {2{wire_nllli_o}}}),
	.o(wire_niOli_o),
	.sel({doublewidth, dwidth}));
	defparam
		niOli.width_data = 4,
		niOli.width_sel = 2;
	oper_mux   niOll
	( 
	.data({wire_nl01i_o, wire_nli0O_o, {2{wire_nllll_o}}}),
	.o(wire_niOll_o),
	.sel({doublewidth, dwidth}));
	defparam
		niOll.width_data = 4,
		niOll.width_sel = 2;
	oper_mux   niOlO
	( 
	.data({(~ wire_n001i_o), (~ wire_n00ll_o), (~ wire_n001l_o), (~ wire_n01ii_o), wire_n001i_o, wire_n00ll_o, wire_n001l_o, wire_n01ii_o}),
	.o(wire_niOlO_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		niOlO.width_data = 8,
		niOlO.width_sel = 3;
	oper_mux   niOOi
	( 
	.data({(~ wire_n01OO_o), (~ wire_n00li_o), (~ wire_n001O_o), (~ wire_n01il_o), wire_n01OO_o, wire_n00li_o, wire_n001O_o, wire_n01il_o}),
	.o(wire_niOOi_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		niOOi.width_data = 8,
		niOOi.width_sel = 3;
	oper_mux   niOOl
	( 
	.data({(~ wire_n01Ol_o), (~ wire_n00iO_o), (~ wire_n000i_o), (~ wire_n01iO_o), wire_n01Ol_o, wire_n00iO_o, wire_n000i_o, wire_n01iO_o}),
	.o(wire_niOOl_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		niOOl.width_data = 8,
		niOOl.width_sel = 3;
	oper_mux   niOOO
	( 
	.data({(~ wire_n01Oi_o), (~ wire_n00il_o), (~ wire_n000l_o), (~ wire_n01li_o), wire_n01Oi_o, wire_n00il_o, wire_n000l_o, wire_n01li_o}),
	.o(wire_niOOO_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		niOOO.width_data = 8,
		niOOO.width_sel = 3;
	oper_mux   nl00i
	( 
	.data({(~ wire_n01lO_o), (~ wire_n00ii_o), (~ wire_n000i_o), (~ wire_n01iO_o), wire_n01lO_o, wire_n00ii_o, wire_n000i_o, wire_n01iO_o}),
	.o(wire_nl00i_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl00i.width_data = 8,
		nl00i.width_sel = 3;
	oper_mux   nl00l
	( 
	.data({(~ wire_n01ll_o), (~ wire_n000O_o), (~ wire_n000l_o), (~ wire_n01li_o), wire_n01ll_o, wire_n000O_o, wire_n000l_o, wire_n01li_o}),
	.o(wire_nl00l_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl00l.width_data = 8,
		nl00l.width_sel = 3;
	oper_mux   nl00O
	( 
	.data({(~ wire_n01li_o), (~ wire_n000l_o), (~ wire_n000O_o), (~ wire_n01ll_o), wire_n01li_o, wire_n000l_o, wire_n000O_o, wire_n01ll_o}),
	.o(wire_nl00O_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl00O.width_data = 8,
		nl00O.width_sel = 3;
	oper_mux   nl01i
	( 
	.data({(~ wire_n001l_o), (~ wire_n01ii_o), (~ wire_n001i_o), (~ wire_n00ll_o), wire_n001l_o, wire_n01ii_o, wire_n001i_o, wire_n00ll_o}),
	.o(wire_nl01i_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl01i.width_data = 8,
		nl01i.width_sel = 3;
	oper_mux   nl01l
	( 
	.data({(~ wire_n01Ol_o), (~ wire_n00iO_o), (~ wire_n001l_o), (~ wire_n01ii_o), wire_n01Ol_o, wire_n00iO_o, wire_n001l_o, wire_n01ii_o}),
	.o(wire_nl01l_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl01l.width_data = 8,
		nl01l.width_sel = 3;
	oper_mux   nl01O
	( 
	.data({(~ wire_n01Oi_o), (~ wire_n00il_o), (~ wire_n001O_o), (~ wire_n01il_o), wire_n01Oi_o, wire_n00il_o, wire_n001O_o, wire_n01il_o}),
	.o(wire_nl01O_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl01O.width_data = 8,
		nl01O.width_sel = 3;
	oper_mux   nl0ii
	( 
	.data({(~ wire_n01iO_o), (~ wire_n000i_o), (~ wire_n00ii_o), (~ wire_n01lO_o), wire_n01iO_o, wire_n000i_o, wire_n00ii_o, wire_n01lO_o}),
	.o(wire_nl0ii_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0ii.width_data = 8,
		nl0ii.width_sel = 3;
	oper_mux   nl0il
	( 
	.data({(~ wire_n01il_o), (~ wire_n001O_o), (~ wire_n00il_o), (~ wire_n01Oi_o), wire_n01il_o, wire_n001O_o, wire_n00il_o, wire_n01Oi_o}),
	.o(wire_nl0il_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0il.width_data = 8,
		nl0il.width_sel = 3;
	oper_mux   nl0iO
	( 
	.data({(~ wire_n01ii_o), (~ wire_n001l_o), (~ wire_n00iO_o), (~ wire_n01Ol_o), wire_n01ii_o, wire_n001l_o, wire_n00iO_o, wire_n01Ol_o}),
	.o(wire_nl0iO_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0iO.width_data = 8,
		nl0iO.width_sel = 3;
	oper_mux   nl0li
	( 
	.data({{4{(~ wire_n01OO_o)}}, {4{wire_n01OO_o}}}),
	.o(wire_nl0li_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0li.width_data = 8,
		nl0li.width_sel = 3;
	oper_mux   nl0ll
	( 
	.data({{4{(~ wire_n001i_o)}}, {4{wire_n001i_o}}}),
	.o(wire_nl0ll_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0ll.width_data = 8,
		nl0ll.width_sel = 3;
	oper_mux   nl0lO
	( 
	.data({(~ wire_n00iO_o), (~ wire_n01Ol_o), (~ wire_n01ii_o), (~ wire_n001l_o), wire_n00iO_o, wire_n01Ol_o, wire_n01ii_o, wire_n001l_o}),
	.o(wire_nl0lO_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0lO.width_data = 8,
		nl0lO.width_sel = 3;
	oper_mux   nl0Oi
	( 
	.data({(~ wire_n00il_o), (~ wire_n01Oi_o), (~ wire_n01il_o), (~ wire_n001O_o), wire_n00il_o, wire_n01Oi_o, wire_n01il_o, wire_n001O_o}),
	.o(wire_nl0Oi_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0Oi.width_data = 8,
		nl0Oi.width_sel = 3;
	oper_mux   nl0Ol
	( 
	.data({(~ wire_n00ii_o), (~ wire_n01lO_o), (~ wire_n01iO_o), (~ wire_n000i_o), wire_n00ii_o, wire_n01lO_o, wire_n01iO_o, wire_n000i_o}),
	.o(wire_nl0Ol_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0Ol.width_data = 8,
		nl0Ol.width_sel = 3;
	oper_mux   nl0OO
	( 
	.data({(~ wire_n000O_o), (~ wire_n01ll_o), (~ wire_n01li_o), (~ wire_n000l_o), wire_n000O_o, wire_n01ll_o, wire_n01li_o, wire_n000l_o}),
	.o(wire_nl0OO_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl0OO.width_data = 8,
		nl0OO.width_sel = 3;
	oper_mux   nl10i
	( 
	.data({(~ wire_n01iO_o), (~ wire_n000i_o), (~ wire_n00iO_o), (~ wire_n01Ol_o), wire_n01iO_o, wire_n000i_o, wire_n00iO_o, wire_n01Ol_o}),
	.o(wire_nl10i_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl10i.width_data = 8,
		nl10i.width_sel = 3;
	oper_mux   nl10l
	( 
	.data({(~ wire_n01il_o), (~ wire_n001O_o), (~ wire_n00li_o), (~ wire_n01OO_o), wire_n01il_o, wire_n001O_o, wire_n00li_o, wire_n01OO_o}),
	.o(wire_nl10l_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl10l.width_data = 8,
		nl10l.width_sel = 3;
	oper_mux   nl10O
	( 
	.data({(~ wire_n01ii_o), (~ wire_n001l_o), (~ wire_n00ll_o), (~ wire_n001i_o), wire_n01ii_o, wire_n001l_o, wire_n00ll_o, wire_n001i_o}),
	.o(wire_nl10O_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl10O.width_data = 8,
		nl10O.width_sel = 3;
	oper_mux   nl11i
	( 
	.data({(~ wire_n01lO_o), (~ wire_n00ii_o), (~ wire_n000O_o), (~ wire_n01ll_o), wire_n01lO_o, wire_n00ii_o, wire_n000O_o, wire_n01ll_o}),
	.o(wire_nl11i_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl11i.width_data = 8,
		nl11i.width_sel = 3;
	oper_mux   nl11l
	( 
	.data({(~ wire_n01ll_o), (~ wire_n000O_o), (~ wire_n00ii_o), (~ wire_n01lO_o), wire_n01ll_o, wire_n000O_o, wire_n00ii_o, wire_n01lO_o}),
	.o(wire_nl11l_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl11l.width_data = 8,
		nl11l.width_sel = 3;
	oper_mux   nl11O
	( 
	.data({(~ wire_n01li_o), (~ wire_n000l_o), (~ wire_n00il_o), (~ wire_n01Oi_o), wire_n01li_o, wire_n000l_o, wire_n00il_o, wire_n01Oi_o}),
	.o(wire_nl11O_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl11O.width_data = 8,
		nl11O.width_sel = 3;
	oper_mux   nl1ii
	( 
	.data({(~ wire_n00ll_o), (~ wire_n001i_o), (~ wire_n01ii_o), (~ wire_n001l_o), wire_n00ll_o, wire_n001i_o, wire_n01ii_o, wire_n001l_o}),
	.o(wire_nl1ii_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1ii.width_data = 8,
		nl1ii.width_sel = 3;
	oper_mux   nl1il
	( 
	.data({(~ wire_n00li_o), (~ wire_n01OO_o), (~ wire_n01il_o), (~ wire_n001O_o), wire_n00li_o, wire_n01OO_o, wire_n01il_o, wire_n001O_o}),
	.o(wire_nl1il_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1il.width_data = 8,
		nl1il.width_sel = 3;
	oper_mux   nl1iO
	( 
	.data({(~ wire_n00iO_o), (~ wire_n01Ol_o), (~ wire_n01iO_o), (~ wire_n000i_o), wire_n00iO_o, wire_n01Ol_o, wire_n01iO_o, wire_n000i_o}),
	.o(wire_nl1iO_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1iO.width_data = 8,
		nl1iO.width_sel = 3;
	oper_mux   nl1li
	( 
	.data({(~ wire_n00il_o), (~ wire_n01Oi_o), (~ wire_n01li_o), (~ wire_n000l_o), wire_n00il_o, wire_n01Oi_o, wire_n01li_o, wire_n000l_o}),
	.o(wire_nl1li_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1li.width_data = 8,
		nl1li.width_sel = 3;
	oper_mux   nl1ll
	( 
	.data({(~ wire_n00ii_o), (~ wire_n01lO_o), (~ wire_n01ll_o), (~ wire_n000O_o), wire_n00ii_o, wire_n01lO_o, wire_n01ll_o, wire_n000O_o}),
	.o(wire_nl1ll_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1ll.width_data = 8,
		nl1ll.width_sel = 3;
	oper_mux   nl1lO
	( 
	.data({(~ wire_n000O_o), (~ wire_n01ll_o), (~ wire_n01lO_o), (~ wire_n00ii_o), wire_n000O_o, wire_n01ll_o, wire_n01lO_o, wire_n00ii_o}),
	.o(wire_nl1lO_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1lO.width_data = 8,
		nl1lO.width_sel = 3;
	oper_mux   nl1Oi
	( 
	.data({(~ wire_n000l_o), (~ wire_n01li_o), (~ wire_n01Oi_o), (~ wire_n00il_o), wire_n000l_o, wire_n01li_o, wire_n01Oi_o, wire_n00il_o}),
	.o(wire_nl1Oi_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1Oi.width_data = 8,
		nl1Oi.width_sel = 3;
	oper_mux   nl1Ol
	( 
	.data({(~ wire_n000i_o), (~ wire_n01iO_o), (~ wire_n01Ol_o), (~ wire_n00iO_o), wire_n000i_o, wire_n01iO_o, wire_n01Ol_o, wire_n00iO_o}),
	.o(wire_nl1Ol_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1Ol.width_data = 8,
		nl1Ol.width_sel = 3;
	oper_mux   nl1OO
	( 
	.data({(~ wire_n001O_o), (~ wire_n01il_o), (~ wire_n01OO_o), (~ wire_n00li_o), wire_n001O_o, wire_n01il_o, wire_n01OO_o, wire_n00li_o}),
	.o(wire_nl1OO_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nl1OO.width_data = 8,
		nl1OO.width_sel = 3;
	oper_mux   nli0i
	( 
	.data({(~ wire_n001l_o), (~ wire_n01ii_o), (~ wire_n01Ol_o), (~ wire_n00iO_o), wire_n001l_o, wire_n01ii_o, wire_n01Ol_o, wire_n00iO_o}),
	.o(wire_nli0i_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nli0i.width_data = 8,
		nli0i.width_sel = 3;
	oper_mux   nli0l
	( 
	.data({{4{(~ wire_n00li_o)}}, {4{wire_n00li_o}}}),
	.o(wire_nli0l_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nli0l.width_data = 8,
		nli0l.width_sel = 3;
	oper_mux   nli0O
	( 
	.data({{4{(~ wire_n00ll_o)}}, {4{wire_n00ll_o}}}),
	.o(wire_nli0O_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nli0O.width_data = 8,
		nli0O.width_sel = 3;
	oper_mux   nli1i
	( 
	.data({(~ wire_n000l_o), (~ wire_n01li_o), (~ wire_n01ll_o), (~ wire_n000O_o), wire_n000l_o, wire_n01li_o, wire_n01ll_o, wire_n000O_o}),
	.o(wire_nli1i_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nli1i.width_data = 8,
		nli1i.width_sel = 3;
	oper_mux   nli1l
	( 
	.data({(~ wire_n000i_o), (~ wire_n01iO_o), (~ wire_n01lO_o), (~ wire_n00ii_o), wire_n000i_o, wire_n01iO_o, wire_n01lO_o, wire_n00ii_o}),
	.o(wire_nli1l_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nli1l.width_data = 8,
		nli1l.width_sel = 3;
	oper_mux   nli1O
	( 
	.data({(~ wire_n001O_o), (~ wire_n01il_o), (~ wire_n01Oi_o), (~ wire_n00il_o), wire_n001O_o, wire_n01il_o, wire_n01Oi_o, wire_n00il_o}),
	.o(wire_nli1O_o),
	.sel({ni11i, n0OOl, n0OlO}));
	defparam
		nli1O.width_data = 8,
		nli1O.width_sel = 3;
	oper_mux   nliii
	( 
	.data({(~ wire_n001i_o), (~ wire_n01ii_o), wire_n001i_o, wire_n01ii_o}),
	.o(wire_nliii_o),
	.sel({ni11i, n0OOl}));
	defparam
		nliii.width_data = 4,
		nliii.width_sel = 2;
	oper_mux   nliil
	( 
	.data({(~ wire_n01OO_o), (~ wire_n01il_o), wire_n01OO_o, wire_n01il_o}),
	.o(wire_nliil_o),
	.sel({ni11i, n0OOl}));
	defparam
		nliil.width_data = 4,
		nliil.width_sel = 2;
	oper_mux   nliiO
	( 
	.data({(~ wire_n01Ol_o), (~ wire_n01iO_o), wire_n01Ol_o, wire_n01iO_o}),
	.o(wire_nliiO_o),
	.sel({ni11i, n0OOl}));
	defparam
		nliiO.width_data = 4,
		nliiO.width_sel = 2;
	oper_mux   nlili
	( 
	.data({(~ wire_n01Oi_o), (~ wire_n01li_o), wire_n01Oi_o, wire_n01li_o}),
	.o(wire_nlili_o),
	.sel({ni11i, n0OOl}));
	defparam
		nlili.width_data = 4,
		nlili.width_sel = 2;
	oper_mux   nlill
	( 
	.data({(~ wire_n01lO_o), (~ wire_n01ll_o), wire_n01lO_o, wire_n01ll_o}),
	.o(wire_nlill_o),
	.sel({ni11i, n0OOl}));
	defparam
		nlill.width_data = 4,
		nlill.width_sel = 2;
	oper_mux   nlilO
	( 
	.data({(~ wire_n01ll_o), (~ wire_n01lO_o), wire_n01ll_o, wire_n01lO_o}),
	.o(wire_nlilO_o),
	.sel({ni11i, n0OOl}));
	defparam
		nlilO.width_data = 4,
		nlilO.width_sel = 2;
	oper_mux   nliOi
	( 
	.data({(~ wire_n01li_o), (~ wire_n01Oi_o), wire_n01li_o, wire_n01Oi_o}),
	.o(wire_nliOi_o),
	.sel({ni11i, n0OOl}));
	defparam
		nliOi.width_data = 4,
		nliOi.width_sel = 2;
	oper_mux   nliOl
	( 
	.data({(~ wire_n01iO_o), (~ wire_n01Ol_o), wire_n01iO_o, wire_n01Ol_o}),
	.o(wire_nliOl_o),
	.sel({ni11i, n0OOl}));
	defparam
		nliOl.width_data = 4,
		nliOl.width_sel = 2;
	oper_mux   nliOO
	( 
	.data({(~ wire_n01il_o), (~ wire_n01OO_o), wire_n01il_o, wire_n01OO_o}),
	.o(wire_nliOO_o),
	.sel({ni11i, n0OOl}));
	defparam
		nliOO.width_data = 4,
		nliOO.width_sel = 2;
	oper_mux   nll0i
	( 
	.data({{2{(~ wire_n000i_o)}}, {2{wire_n000i_o}}}),
	.o(wire_nll0i_o),
	.sel({ni11i, n0OOl}));
	defparam
		nll0i.width_data = 4,
		nll0i.width_sel = 2;
	oper_mux   nll0l
	( 
	.data({{2{(~ wire_n000l_o)}}, {2{wire_n000l_o}}}),
	.o(wire_nll0l_o),
	.sel({ni11i, n0OOl}));
	defparam
		nll0l.width_data = 4,
		nll0l.width_sel = 2;
	oper_mux   nll0O
	( 
	.data({{2{(~ wire_n000O_o)}}, {2{wire_n000O_o}}}),
	.o(wire_nll0O_o),
	.sel({ni11i, n0OOl}));
	defparam
		nll0O.width_data = 4,
		nll0O.width_sel = 2;
	oper_mux   nll1i
	( 
	.data({(~ wire_n01ii_o), (~ wire_n001i_o), wire_n01ii_o, wire_n001i_o}),
	.o(wire_nll1i_o),
	.sel({ni11i, n0OOl}));
	defparam
		nll1i.width_data = 4,
		nll1i.width_sel = 2;
	oper_mux   nll1l
	( 
	.data({{2{(~ wire_n001l_o)}}, {2{wire_n001l_o}}}),
	.o(wire_nll1l_o),
	.sel({ni11i, n0OOl}));
	defparam
		nll1l.width_data = 4,
		nll1l.width_sel = 2;
	oper_mux   nll1O
	( 
	.data({{2{(~ wire_n001O_o)}}, {2{wire_n001O_o}}}),
	.o(wire_nll1O_o),
	.sel({ni11i, n0OOl}));
	defparam
		nll1O.width_data = 4,
		nll1O.width_sel = 2;
	oper_mux   nllii
	( 
	.data({{2{(~ wire_n00ii_o)}}, {2{wire_n00ii_o}}}),
	.o(wire_nllii_o),
	.sel({ni11i, n0OOl}));
	defparam
		nllii.width_data = 4,
		nllii.width_sel = 2;
	oper_mux   nllil
	( 
	.data({{2{(~ wire_n00il_o)}}, {2{wire_n00il_o}}}),
	.o(wire_nllil_o),
	.sel({ni11i, n0OOl}));
	defparam
		nllil.width_data = 4,
		nllil.width_sel = 2;
	oper_mux   nlliO
	( 
	.data({((nilOll40 ^ nilOll39) & (~ wire_n00iO_o)), (~ wire_n00iO_o), wire_n00iO_o, ((nilOlO38 ^ nilOlO37) & wire_n00iO_o)}),
	.o(wire_nlliO_o),
	.sel({ni11i, n0OOl}));
	defparam
		nlliO.width_data = 4,
		nlliO.width_sel = 2;
	oper_mux   nllli
	( 
	.data({(~ wire_n00li_o), ((nilOOi36 ^ nilOOi35) & (~ wire_n00li_o)), {2{wire_n00li_o}}}),
	.o(wire_nllli_o),
	.sel({ni11i, n0OOl}));
	defparam
		nllli.width_data = 4,
		nllli.width_sel = 2;
	oper_mux   nllll
	( 
	.data({{2{(~ wire_n00ll_o)}}, {2{wire_n00ll_o}}}),
	.o(wire_nllll_o),
	.sel({ni11i, n0OOl}));
	defparam
		nllll.width_data = 4,
		nllll.width_sel = 2;
	oper_mux   nlllO
	( 
	.data({(~ wire_n01Ol_o), (~ wire_n01ii_o), wire_n01Ol_o, wire_n01ii_o}),
	.o(wire_nlllO_o),
	.sel({ni11i, n0OOl}));
	defparam
		nlllO.width_data = 4,
		nlllO.width_sel = 2;
	oper_mux   nllOi
	( 
	.data({(~ wire_n01Oi_o), ((nilOOl34 ^ nilOOl33) & (~ wire_n01il_o)), wire_n01Oi_o, wire_n01il_o}),
	.o(wire_nllOi_o),
	.sel({ni11i, n0OOl}));
	defparam
		nllOi.width_data = 4,
		nllOi.width_sel = 2;
	oper_mux   nllOl
	( 
	.data({(~ wire_n01lO_o), (~ wire_n01iO_o), wire_n01lO_o, wire_n01iO_o}),
	.o(wire_nllOl_o),
	.sel({ni11i, n0OOl}));
	defparam
		nllOl.width_data = 4,
		nllOl.width_sel = 2;
	oper_mux   nllOO
	( 
	.data({(~ wire_n01ll_o), (~ wire_n01li_o), wire_n01ll_o, ((nilOOO32 ^ nilOOO31) & wire_n01li_o)}),
	.o(wire_nllOO_o),
	.sel({ni11i, n0OOl}));
	defparam
		nllOO.width_data = 4,
		nllOO.width_sel = 2;
	oper_mux   nlO0i
	( 
	.data({(~ wire_n01ii_o), (~ wire_n01Ol_o), wire_n01ii_o, wire_n01Ol_o}),
	.o(wire_nlO0i_o),
	.sel({ni11i, ((niO10l22 ^ niO10l21) & n0OOl)}));
	defparam
		nlO0i.width_data = 4,
		nlO0i.width_sel = 2;
	oper_mux   nlO0l
	( 
	.data({((niO10O20 ^ niO10O19) & (~ wire_n01OO_o)), (~ wire_n01OO_o), {2{wire_n01OO_o}}}),
	.o(wire_nlO0l_o),
	.sel({((niO1ii18 ^ niO1ii17) & ni11i), n0OOl}));
	defparam
		nlO0l.width_data = 4,
		nlO0l.width_sel = 2;
	oper_mux   nlO0O
	( 
	.data({{2{(~ wire_n001i_o)}}, ((niO1il16 ^ niO1il15) & wire_n001i_o), wire_n001i_o}),
	.o(wire_nlO0O_o),
	.sel({ni11i, n0OOl}));
	defparam
		nlO0O.width_data = 4,
		nlO0O.width_sel = 2;
	oper_mux   nlO1i
	( 
	.data({((niO11i30 ^ niO11i29) & (~ wire_n01li_o)), (~ wire_n01ll_o), wire_n01li_o, wire_n01ll_o}),
	.o(wire_nlO1i_o),
	.sel({ni11i, n0OOl}));
	defparam
		nlO1i.width_data = 4,
		nlO1i.width_sel = 2;
	oper_mux   nlO1l
	( 
	.data({(~ wire_n01iO_o), ((niO11l28 ^ niO11l27) & (~ wire_n01lO_o)), ((niO11O26 ^ niO11O25) & wire_n01iO_o), wire_n01lO_o}),
	.o(wire_nlO1l_o),
	.sel({ni11i, n0OOl}));
	defparam
		nlO1l.width_data = 4,
		nlO1l.width_sel = 2;
	oper_mux   nlO1O
	( 
	.data({(~ wire_n01il_o), (~ wire_n01Oi_o), wire_n01il_o, wire_n01Oi_o}),
	.o(wire_nlO1O_o),
	.sel({((niO10i24 ^ niO10i23) & ni11i), n0OOl}));
	defparam
		nlO1O.width_data = 4,
		nlO1O.width_sel = 2;
	assign
		disp_out_3b = {wire_nllllO_dataout, wire_nl0i1l_dataout},
		nil00i = (((((~ wire_n1ll_dataout) & (wire_n1li_dataout & nil1ll)) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & nil1ll))) | (wire_n1ll_dataout & (wire_n1li_dataout & ((~ wire_n1iO_dataout) & wire_n1il_dataout)))) | (wire_n1ll_dataout & (wire_n1li_dataout & (wire_n1iO_dataout & (~ wire_n1il_dataout))))),
		nil00l = (((((((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & (wire_n1iO_dataout & wire_n1il_dataout))) | ((~ wire_n1ll_dataout) & (wire_n1li_dataout & nil1Ol))) | ((~ wire_n1ll_dataout) & (wire_n1li_dataout & nil1Oi))) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & nil1Ol))) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & nil1Oi))) | (wire_n1ll_dataout & (wire_n1li_dataout & ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout))))),
		nil00O = (nil0il | (wire_n1lO_dataout & nil0ii)),
		nil01i = (wire_n1lO_dataout & ((wire_n1ll_dataout & nil0iO) | nil00i)),
		nil01l = (wire_nl1O1O_dataout & nil00l),
		nil01O = ((((~ wire_n1lO_dataout) | wire_nl1O1O_dataout) & nil00l) | (wire_n1lO_dataout & (((~ nil00i) & (~ nil00l)) & nil0ii))),
		nil0ii = ((~ wire_n1ll_dataout) | (wire_n1li_dataout | (wire_n1iO_dataout | wire_n1il_dataout))),
		nil0il = ((~ wire_n1lO_dataout) & nil0iO),
		nil0iO = (((((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & ((~ wire_n1iO_dataout) & wire_n1il_dataout))) | ((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & (wire_n1iO_dataout & (~ wire_n1il_dataout))))) | ((~ wire_n1ll_dataout) & (wire_n1li_dataout & nil1lO))) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & nil1lO))),
		nil0li = (wire_n1ll_dataout & (wire_n1li_dataout & (wire_n1iO_dataout & wire_n1il_dataout))),
		nil0ll = ((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout)))),
		nil0lO = (nil0li | nil0ll),
		nil0Oi = ((((wire_n1lO_dataout & wire_n1ll_dataout) & wire_n1li_dataout) & (~ wire_n1iO_dataout)) & (~ wire_n1il_dataout)),
		nil0Ol = (wire_n1iO_dataout & wire_n1il_dataout),
		nil0OO = ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout)),
		nil1ll = (wire_n1iO_dataout & wire_n1il_dataout),
		nil1lO = ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout)),
		nil1Oi = (wire_n1iO_dataout & (~ wire_n1il_dataout)),
		nil1Ol = ((~ wire_n1iO_dataout) & wire_n1il_dataout),
		nil1OO = (((((((~ wire_n1ll_dataout) & (wire_n1li_dataout & (wire_n1iO_dataout & wire_n1il_dataout))) | (wire_n1lO_dataout & nil0ll)) | (wire_n1lO_dataout & nil0li)) | (wire_n1lO_dataout & nil00i)) | nil01l) ^ ((~ wire_ni1ii_dataout) & (nil01l | ((nil0lO | ((~ wire_n1lO_dataout) & (((~ wire_n1ll_dataout) & nil00i) | nil0iO))) | nil01i)))),
		nili0i = ((((~ wire_nl11iO_dataout) & (wire_nl0lii_dataout & (~ nili0O))) | nili0l) ^ ((~ wire_nl11iO_dataout) & nili0O)),
		nili0l = (wire_n1Ol_dataout & wire_n1Oi_dataout),
		nili0O = (nili0l | nili1l),
		nili1i = ((~ wire_n1OO_dataout) & nili1l),
		nili1l = ((~ wire_n1Ol_dataout) & (~ wire_n1Oi_dataout)),
		nili1O = (wire_n1OO_dataout & (wire_n1Ol_dataout & (wire_n1Oi_dataout & ((((~ wire_nl11iO_dataout) & ((wire_n1lO_dataout & (~ wire_n1ll_dataout)) & (((((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & ((~ wire_n1iO_dataout) & wire_n1il_dataout))) | ((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & (wire_n1iO_dataout & (~ wire_n1il_dataout))))) | ((~ wire_n1ll_dataout) & (wire_n1li_dataout & nil0OO))) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & nil0OO))))) | (wire_nl11iO_dataout & (((~ wire_n1lO_dataout) & wire_n1ll_dataout) & (((((~ wire_n1ll_dataout) & (wire_n1li_dataout & nil0Ol)) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & nil0Ol))) | (wire_n1ll_dataout & (wire_n1li_dataout & ((~ wire_n1iO_dataout) & wire_n1il_dataout)))) | (wire_n1ll_dataout & (wire_n1li_dataout & (wire_n1iO_dataout & (~ wire_n1il_dataout)))))))) | (wire_n1OO_dataout & (wire_n1Ol_dataout & (wire_nil_dataout & wire_n1Oi_dataout))))))),
		niliii = (wire_nil_dataout & nil0Oi),
		niliil = (wire_n01l_dataout & wire_n01i_dataout),
		niliiO = ((~ wire_n01l_dataout) & (~ wire_n01i_dataout)),
		nilili = (wire_n01l_dataout & (~ wire_n01i_dataout)),
		nilill = ((~ wire_n01l_dataout) & wire_n01i_dataout),
		nililO = (((((((~ wire_n00i_dataout) & (wire_n01O_dataout & (wire_n01l_dataout & wire_n01i_dataout))) | (wire_n00l_dataout & nillil)) | (wire_n00l_dataout & nillii)) | (wire_n00l_dataout & nill1i)) | niliOl) ^ ((~ wire_ni1il_dataout) & (niliOl | ((nilliO | ((~ wire_n00l_dataout) & (((~ wire_n00i_dataout) & nill1i) | nill0O))) | niliOi)))),
		niliOi = (wire_n00l_dataout & ((wire_n00i_dataout & nill0O) | nill1i)),
		niliOl = (wire_nll1Oi_dataout & nill1l),
		niliOO = ((((~ wire_n00l_dataout) | wire_nll1Oi_dataout) & nill1l) | (wire_n00l_dataout & (((~ nill1i) & (~ nill1l)) & nill0i))),
		nill0i = ((~ wire_n00i_dataout) | (wire_n01O_dataout | (wire_n01l_dataout | wire_n01i_dataout))),
		nill0l = ((~ wire_n00l_dataout) & nill0O),
		nill0O = (((((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & ((~ wire_n01l_dataout) & wire_n01i_dataout))) | ((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & (wire_n01l_dataout & (~ wire_n01i_dataout))))) | ((~ wire_n00i_dataout) & (wire_n01O_dataout & niliiO))) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & niliiO))),
		nill1i = (((((~ wire_n00i_dataout) & (wire_n01O_dataout & niliil)) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & niliil))) | (wire_n00i_dataout & (wire_n01O_dataout & ((~ wire_n01l_dataout) & wire_n01i_dataout)))) | (wire_n00i_dataout & (wire_n01O_dataout & (wire_n01l_dataout & (~ wire_n01i_dataout))))),
		nill1l = (((((((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & (wire_n01l_dataout & wire_n01i_dataout))) | ((~ wire_n00i_dataout) & (wire_n01O_dataout & nilill))) | ((~ wire_n00i_dataout) & (wire_n01O_dataout & nilili))) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & nilill))) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & nilili))) | (wire_n00i_dataout & (wire_n01O_dataout & ((~ wire_n01l_dataout) & (~ wire_n01i_dataout))))),
		nill1O = (nill0l | (wire_n00l_dataout & nill0i)),
		nillii = (wire_n00i_dataout & (wire_n01O_dataout & (wire_n01l_dataout & wire_n01i_dataout))),
		nillil = ((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & ((~ wire_n01l_dataout) & (~ wire_n01i_dataout)))),
		nilliO = (nillii | nillil),
		nillli = ((((wire_n00l_dataout & wire_n00i_dataout) & wire_n01O_dataout) & (~ wire_n01l_dataout)) & (~ wire_n01i_dataout)),
		nillll = (wire_n01l_dataout & wire_n01i_dataout),
		nilllO = ((~ wire_n01l_dataout) & (~ wire_n01i_dataout)),
		nillOi = ((~ wire_n0il_dataout) & nillOl),
		nillOl = ((~ wire_n0ii_dataout) & (~ wire_n00O_dataout)),
		nillOO = (wire_n0il_dataout & (wire_n0ii_dataout & (wire_n00O_dataout & ((((~ wire_nlii0i_dataout) & ((wire_n00l_dataout & (~ wire_n00i_dataout)) & (((((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & ((~ wire_n01l_dataout) & wire_n01i_dataout))) | ((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & (wire_n01l_dataout & (~ wire_n01i_dataout))))) | ((~ wire_n00i_dataout) & (wire_n01O_dataout & nilllO))) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & nilllO))))) | (wire_nlii0i_dataout & (((~ wire_n00l_dataout) & wire_n00i_dataout) & (((((~ wire_n00i_dataout) & (wire_n01O_dataout & nillll)) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & nillll))) | (wire_n00i_dataout & (wire_n01O_dataout & ((~ wire_n01l_dataout) & wire_n01i_dataout)))) | (wire_n00i_dataout & (wire_n01O_dataout & (wire_n01l_dataout & (~ wire_n01i_dataout)))))))) | (wire_n0il_dataout & (wire_n0ii_dataout & (wire_niO_dataout & wire_n00O_dataout))))))),
		nilO0i = (wire_niO_dataout & nillli),
		nilO1i = ((((~ wire_nlii0i_dataout) & (wire_nlO11l_dataout & (~ nilO1O))) | nilO1l) ^ ((~ wire_nlii0i_dataout) & nilO1O)),
		nilO1l = (wire_n0ii_dataout & wire_n00O_dataout),
		nilO1O = (nilO1l | nillOl),
		nilOil = 1'b1,
		niO00O = ((((((d21_5_eq_n & d2_2_eq_n) & (niO0iO2 ^ niO0iO1)) & ge_xaui_sel) & (~ tx_ctl_tc[0])) & (niO0ii4 ^ niO0ii3)) & k_det),
		niO1iO = (((((((d21_5_eq_n & d2_2_eq_n) & (niO1lO12 ^ niO1lO11)) & ge_xaui_sel) & (~ tx_ctl_tc[0])) & (niO1li14 ^ niO1li13)) & k_det) & (~ n00Oi)),
		niO1Ol = ((((((((d21_5_eq_n & d2_2_eq_n) & (niO00i6 ^ niO00i5)) & ge_xaui_sel) & (~ tx_ctl_tc[0])) & k_det) & (niO01l8 ^ niO01l7)) & n00Oi) & (niO1OO10 ^ niO1OO9)),
		pudr = {nil0O, nil0i, nil1l, nil1i, niiOO, niiOl, niiOi, niilO, niill, niili, niiiO, niiil, niiii, nii0O, nii0l, nii0i, nii1O, nii1l, nii1i, ni11O},
		tx_ctl_pre_en = {n0i0l, n0i0i},
		tx_data_9_pre_en = {n0i1O, n0i1l},
		tx_data_pre_en = {n0l0O, n0l0l, n0l0i, n0l1O, n0l1l, n0l1i, n0iOO, n0iOl, n0iOi, n0ilO, n0ill, n0ili, n0iiO, n0iil, n0iii, n0i0O},
		txlp20b = {n0Oll, n0Oli, n0OiO, n0Oil, n0Oii, n0O0O, n0O0l, n0O0i, n0O1O, n0O1l, n0O1i, n0lOO, n0lOl, n0lOi, n0llO, n0lll, n0lli, n0liO, n0lil, n0lii};
endmodule //arriagx_hssi_tx_enc_chnl_top
//synopsys translate_on
//VALID FILE

`timescale 1 ps/1 ps

module arriagx_hssi_tx_digi (txpcs_rst, scan_mode, txd, 
		pld_tx_clk, polinv_tx, rev_loop_data, wrenable_tx, rddisable_tx, 
		phfifourst_tx, txfifo_shared_sig_in_ch0, txfifo_shared_sig_in_q0_ch0, 
		txfifo_shared_sig_out, full_tx, empty_tx,
                tx_data_ts, tx_ctl_ts, refclk_pma, txpma_local_clk,
                tx_clk_out, tx_data_tc, tx_ctl_tc, pudr, 
                rd_enable_sync, refclk_b, txlp20b, tx_pipe_clk, encoder_testbus, tx_ctrl_testbus,
                tx_pipe_soft_reset, tx_pipe_electidle, rrev_loopbk, rev_loopbk, rbisten_tx, 
                rforce_disp, rib_force_disp, rforce_echar, rforce_kchar, rendec_tx, 
                rge_xaui_tx, 
                rdwidth_tx, rtxfifo_dis, rcascaded_8b10b_en_tx, 
                rprbsen_tx, rprbs_sel, rbist_sel, rcxpat_chnl_en, 
                renpolinv_tx, rphfifopldentx, rphfifoursttx,
                rfreerun_tx, rtxwrclksel, rtxrdclksel, renbitrev_tx, rensymswap_tx,
                r8b10b_enc_ibm_en, rtxfifo_lowlatency_en,
                rpmadwidth_tx, rpma_doublewidth_tx, rtx_pipe_enable,
                rindv_tx, rendec_data_sel_tx, rphfifo_master_sel_tx
              );

// Reset inputs
input          txpcs_rst;             // TX PCS resets

// Scan inputs
input          scan_mode;             // 1'b1 = scan mode active; 
                                      // 1'b0 = normal mode
// TX PCS channel inputs/outputs
input   [43:0] txd;                   // TXD data bus from PLD
input          pld_tx_clk;            // XGMII tx clock for this lane from PLD
input          polinv_tx;             // TX polarity inversion dynamic control signal
input   [7:0]  tx_data_ts;            // 8-bit tx data from 10G ethernet 
                                      // tx state machine (tx_sm)
input          tx_ctl_ts;             // 1-bit tx control from 10G ethernet tx state machine (tx_sm)
input          refclk_pma;            // Global parallel clock from TX PLL
input          txpma_local_clk;       // Individual TX PMA clock from TX PMA Extension
input          rev_loopbk;	      // Dynamic signal causes reverse loopback
input   [19:0] rev_loop_data;	      // 10 bit data from RX rate matching FIFO, reverse loopback
input          wrenable_tx;           // TX phase comp. FIFO write enable control signal
input          rddisable_tx;          // TX phase comp. FIFO read disable control signal
input          phfifourst_tx;	      // TX phase comp. FIFO user reset
input   [3:0]  txfifo_shared_sig_in_ch0;    // TX FIFO shared signal from channel 0
input   [3:0]  txfifo_shared_sig_in_q0_ch0; // TX FIFO shared signal from channel 0 of Quad 0

output  [3:0]  txfifo_shared_sig_out; // TX FIFO shared signal output
output         full_tx;               // TX Phase comp. FIFO full flag
output         empty_tx;              // TX Phase comp. FIFO empty flag
output         tx_clk_out;
output  [7:0]  tx_data_tc;            // 8-bit tx data from tx_ctrl to XAUI TX SM
output         tx_ctl_tc;             // TX control/TX data bit 8 from tx_ctrl to XAUI TX SM
output  [19:0] pudr;                  // TX PCS 20-bit code group bus to TX PMA
output         rd_enable_sync;
output         refclk_b;              
output [19:0]  txlp20b;               // tx 20-bit code group bus to RX PCS for loopback
output         tx_pipe_clk;           // TX PIPE interface clock
output [9:0]   encoder_testbus;       // Test bus from 8B10B encoder
output [9:0]   tx_ctrl_testbus;       // Test bus from TX FIFO
output         tx_pipe_soft_reset;    // TX PIPE soft reset from TX FIFO
output         tx_pipe_electidle;     // TxElecIdle output from TX FIFO

// TX PCS CRAMs
input          rrev_loopbk;	      // CRAM - Enable dynamic Reverse, PIPE mode
input          rbisten_tx;            // ENBIST CRAM
input 	       rforce_disp;	      // Acting with TXD[9, 19] forces current disparity to 1 or 0
input          rib_force_disp;        // Disparity force CRAM in IB mode
input          rforce_echar;          // Force /E/ char CRAM
input          rforce_kchar;          // Force /K/ char CRAM
input          rendec_tx;             // Enable 8B/10B encoder CRAM
input          rge_xaui_tx;           // GIGE Idle test enable CRAM
input          rdwidth_tx;            // TX parallel interface data width CRAM
input          rtxfifo_dis;           // TX FIFO disable CRAM
input          rcascaded_8b10b_en_tx; // Caascaded 8b/10b encoder enable CRAM
input          rprbsen_tx;            // PRBS generator enable CRAM
input   [2:0]  rprbs_sel;             // PRBS selection CRAM
input   [1:0]  rbist_sel;             // BIST selection CRAM
input   [1:0]  rcxpat_chnl_en;        // CRPAT or CJPAT selection CRAM
input          renpolinv_tx;          // TX Polarity inversion enable CRAM
input          rphfifopldentx;        // TX phase comp. FIFO PLD read/write enable CRAM
input          rphfifoursttx;         // TX phase comp. FIFO user reset enable CRAM
input          rfreerun_tx;           // TX_CLK out free running during TX PCS reset enable CRAM
input          rtxwrclksel;           // TX FIFO write clock selection CRAM
input          rtxrdclksel;           // TX FIFO read clock selection CRAM
input          renbitrev_tx;          // TX bit reversal enable CRAM
input          rensymswap_tx;         // TX symbol swap enable CRAM
input          r8b10b_enc_ibm_en;     // 8B10B Encoder fix enable CRAM
input          rtxfifo_lowlatency_en; // TX FIFO low latency enable CRAM
input          rpmadwidth_tx;         // TX PCS to TX PMA data width selection CRAM
input          rpma_doublewidth_tx;   // PCS/PMA double width (16/20) selection CRAM
input          rtx_pipe_enable;       // TX PIPE enable CRAM

// Common PCS CRAMs
input          rindv_tx;              // TX SM bypassing CRAM
input          rendec_data_sel_tx;    // TX 8B10B encoder data in selection CRAM
input          rphfifo_master_sel_tx; // TX Phase comp. FIFO pointers selection CRAM

// Wiring section
wire	       refclk_b;
wire           wr_clk_pos;
wire           fifo_rd_clk;
wire    [7:0]  tx_data_tc_high;       // high 8-bit tx data from tx_ctrl
wire    [7:0]  tx_data_tc;            // low 8-bit tx data from tx_ctrl
wire           tx_ctl_tc_high;        // high tx control/tx data bit 8 from tx_ctrl
wire           tx_ctl_tc;             // low tx control/tx data bit 8 from tx_ctrl
wire	       rd_enable_sync;
wire	[1:0]  tx_ctl_pre_en;  
wire    [15:0] tx_data_pre_en;
wire    [1:0]  tx_data_9_pre_en;
wire    [15:0] tx_data_sg;            // 16-bit data sequence generated by bist_gen.
wire    [1:0]  tx_control_sg;         // 2-bit control sequence generated by selftest_gen.
wire    [1:0]  tx_data_9_tc;          // tx data bit 9 from tx_ctrl
wire    [19:0]  tx_data_pg;           // 20-bit tx code group generated by prbs_gen
wire           soft_reset_int;
wire    [1:0]  k_det, d21_5_eq_n, d2_2_eq_n;
wire 	[1:0]  txd_extend_tc;         // Extend txd by 2 bits. Used to force disparity. This will go to the encoder. 
				      // THis is input from the PLD Fabric
wire    [1:0]  disp_out_3b;           // Disparity output from encoder for testbus
wire 	       wr_enable2;
wire    [2:0]  wptr_bin;
wire 	       rd_enable2;
wire    [2:0]  rptr_bin;

// Gated soft reset by scan_mode signal
//assign soft_reset_int = (scan_mode) ? 1'b0 : txpcs_rst;
assign soft_reset_int =  txpcs_rst;

// TX PIPE interface clock
assign tx_pipe_clk = wr_clk_pos;

// Encoder testbus
assign encoder_testbus = {disp_out_3b, pudr[7:0]};

// TX FIFO testbus
assign tx_ctrl_testbus = {1'b0, txfifo_shared_sig_out[0], wr_enable2, wptr_bin, rd_enable2, rptr_bin};

// Clock selection module
arriagx_hssi_tx_txclk_ctl txclk_ctl_1 (
                       .txrst(txpcs_rst), 
                       .pld_tx_clk(pld_tx_clk), 
                       .refclk_pma(refclk_pma), 
                       .txpma_local_clk(txpma_local_clk),
                       .tx_div2_sync_in_ch0(txfifo_shared_sig_in_ch0[3]),
                       .tx_div2_sync_in_q0_ch0(txfifo_shared_sig_in_q0_ch0[3]),
		       .rindv_tx(rindv_tx), 
                       .rtxrdclksel(rtxrdclksel), 
                       .rtxwrclksel(rtxwrclksel),
                       .rdwidth_tx(rdwidth_tx), 
                       .rfreerun_tx(rfreerun_tx),
                       .rphfifo_master_sel_tx(rphfifo_master_sel_tx),
                       .scan_mode (scan_mode),
		       .tx_clk_out(tx_clk_out), 
                       .tx_div2_sync_out(txfifo_shared_sig_out[3]), 
                       .wr_clk_pos(wr_clk_pos), 
                       .fifo_rd_clk(fifo_rd_clk),
                       .refclk_b(refclk_b) 
		      );
		     

// TX Phase compensation FIFO module
arriagx_hssi_tx_ctrl           tx_ctrl_1 (
                             .soft_reset (soft_reset_int),
                             .fifo_wr_clk (wr_clk_pos),
                             .fifo_rd_clk (fifo_rd_clk),
			     .refclk_b_in (refclk_b),
			     .scan_mode(scan_mode),
                             .indv (rindv_tx),
                             .rphfifo_master_sel_tx (rphfifo_master_sel_tx),
                             .p_rlpbk (1'b0),
                             .selftest_en (rbisten_tx),
                             .dwidth (rdwidth_tx),
                             .txfifo_dis (rtxfifo_dis),
                             .rtxfifo_urst_en(rphfifoursttx),
                             .txfifo_urst(phfifourst_tx),
                             .rtxfifo_lowlatency_en(rtxfifo_lowlatency_en),
                             .rtxphfifopldctl_en(rphfifopldentx),
                             .rtx_pipe_enable(rtx_pipe_enable),
                             .pld_we(wrenable_tx),
                             .pld_rd_dis(rddisable_tx),
                             .txd ({txd[42:33],txd[31:22],txd[20:11],txd[9:0]}),
			     .txd_extend ({txd[43],txd[32],txd[21],txd[10]}),               
			     .rforce_disp (rforce_disp),
                             .tx_data_sg ({16'h0000,tx_data_sg}),      
                             .tx_control_sg ({2'b00,tx_control_sg}),   
                             .rxd_lpbk (40'h0000000000),
                             .redund_ctl (4'h0),
                             .txd_redun (40'h0000000000),
                             .wr_enable_ch0(txfifo_shared_sig_in_ch0[2]),
                             .rd_enable_ch0(txfifo_shared_sig_in_ch0[1]),
                             .fifo_select_in_ch0(txfifo_shared_sig_in_ch0[0]),
                             .wr_enable_q0_ch0(txfifo_shared_sig_in_q0_ch0[2]),
                             .rd_enable_q0_ch0(txfifo_shared_sig_in_q0_ch0[1]),
                             .fifo_select_in_q0_ch0 (txfifo_shared_sig_in_q0_ch0[0]),
                             .rforce_kchar (rforce_kchar),
                             .rforce_echar (rforce_echar),
			     .txd_extend_tc (txd_extend_tc),               
                             .tx_data_tc ({tx_data_tc_high,tx_data_tc}),             
                             .tx_ctl_tc ({tx_ctl_tc_high,tx_ctl_tc}),             
                             .tx_data_9_tc (tx_data_9_tc),
                             .rd_enable_sync (rd_enable_sync),
                             .k_det (k_det),
                             .d21_5_eq_n (d21_5_eq_n),
			     .d2_2_eq_n (d2_2_eq_n),
			     .wr_enable_out(txfifo_shared_sig_out[2]),
			     .rd_enable_out(txfifo_shared_sig_out[1]),
                             .fifo_select_out (txfifo_shared_sig_out[0]),
                             .ph_fifo_full(full_tx),
                             .ph_fifo_empty(empty_tx),
                             .soft_reset_wclk1(tx_pipe_soft_reset),
                             .pipe_electric_idle(tx_pipe_electidle),
                             .wr_enable2(wr_enable2),
                             .wptr_bin(wptr_bin),
                             .rd_enable2(rd_enable2),
                             .rptr_bin(rptr_bin)
                            );           

// BIST generator module
arriagx_hssi_tx_bist_gen selftest_gen_1  (
                          .tx_clk(wr_clk_pos),
                          .soft_reset(tx_pipe_soft_reset),
                          .rbisten_tx(rbisten_tx),
                          .rpmadwidth_tx(rpmadwidth_tx),
                          .rpma_doublewidth_tx(rpma_doublewidth_tx),
                          .rdwidth_tx(rdwidth_tx),
                          .rbist_sel(rbist_sel),
                          .rcxpat_chnl_sel(rcxpat_chnl_en),
                          .bist_data_sg(tx_data_sg),
                          .bist_ctl_sg(tx_control_sg)
                         );

// PRBS generator module
arriagx_hssi_tx_prbs_gen prbs_gen_1      (
                          .tx_clk(refclk_b), 
                          .soft_reset(soft_reset_int), 
                          .rprbs_en_tx(rprbsen_tx), 
                          .rpmadwidth_tx(rpmadwidth_tx),
                          .rpma_doublewidth_tx(rpma_doublewidth_tx), 
                          .rprbs_sel(rprbs_sel),
                          .prbs_out(tx_data_pg)
                         );

// 8B-10B Encoder module
arriagx_hssi_tx_enc_chnl_top enc_chnl_top_1 (
                             .rst(soft_reset_int), 
                             .clk(refclk_b), 
                             .cascaded_8b10b_en(rcascaded_8b10b_en_tx),
                             .rendec_data_sel_tx(rendec_data_sel_tx), 
                             .rrev_loopbk(rrev_loopbk), 
                             .rev_loopbk(rev_loopbk),
                             .dwidth(rpmadwidth_tx),
                             .doublewidth(rpma_doublewidth_tx),
                             .endec(rendec_tx), 
                             .ge_xaui_sel(rge_xaui_tx), 
                             .rforce_disp(rforce_disp), 
                             .ib_force_disparity(rib_force_disp), 
                             .prbs_en(rprbsen_tx), 
                             .r8b10b_enc_ibm_en(r8b10b_enc_ibm_en),
                             .rev_loop_data(rev_loop_data),
                             .tx_ctl_ts(tx_ctl_ts),
                             .tx_ctl_tc({tx_ctl_tc_high,tx_ctl_tc}),
                             .tx_data_ts(tx_data_ts),
                             .txd_extend_tc(txd_extend_tc),
                             .tx_data_tc({tx_data_tc_high,tx_data_tc}), 
                             .tx_data_9_tc(tx_data_9_tc),
                             .tx_data_pg(tx_data_pg),
                             .k_det(k_det[0]),
                             .d21_5_eq_n(d21_5_eq_n[0]),
                             .d2_2_eq_n(d2_2_eq_n[0]),
                             .renpolinv_tx(renpolinv_tx),
                             .enpolinv_tx(polinv_tx),
                             .renbitrev_tx(renbitrev_tx),
                             .rensymswap_tx(rensymswap_tx),
                             .pudr(pudr), 
                             .txlp20b(txlp20b),
                             .tx_data_pre_en(tx_data_pre_en),
                             .tx_data_9_pre_en(tx_data_9_pre_en), 
                             .tx_ctl_pre_en(tx_ctl_pre_en),
                             .disp_out_3b(disp_out_3b)
                             );

endmodule

//****************************************************************************
// Description:
//    This is a flip-flop based implementation
//    Bit 15,14 are the underflow/overflow/insertion/deletion status bits
//    Bit 13 is the running Disparity polarity bits 
//    Bit 12 is the Disparity Error bit
//    Bit 11 is the Resync/Sync_status bit
//    Bit 10 is the Invalid Code bit
//    Bit 9 to 0 -- Encoded 10-bit data
//****************************************************************************

`timescale 1ps / 1ps

module arriagx_hssi_ram20x16_syn (
    data_in,
    clk,
    fifo_wr,
    rst_l, 
    fifo_re1,
    fifo_re2,
    data_out1,
    data_out2
    );

input 		clk;
input 		rst_l;
input 	[19:0]	fifo_wr;
input 	[19:0] 	fifo_re1;
input 	[19:0] 	fifo_re2;
input 	[15:0] 	data_in;
output 	[15:0] 	data_out1;
output 	[15:0] 	data_out2;

parameter read_access_time = 0;
parameter write_access_time = 0;
parameter ram_width = 16;

reg [ram_width-1:0] data_out1_i, data_out2_i;
reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, 
                    ram_array_d_3, ram_array_d_4, ram_array_d_5, 
                    ram_array_d_6, ram_array_d_7, ram_array_d_8, 
                    ram_array_d_9, ram_array_d_10, ram_array_d_11,
                    ram_array_d_12, ram_array_d_13, ram_array_d_14,
		    ram_array_d_15, ram_array_d_16, ram_array_d_17, 
		    ram_array_d_18, ram_array_d_19, 
 		    ram_array_q_0, ram_array_q_1, ram_array_q_2, 
                    ram_array_q_3, ram_array_q_4, ram_array_q_5, 
                    ram_array_q_6, ram_array_q_7, ram_array_q_8, 
                    ram_array_q_9, ram_array_q_10, ram_array_q_11,
                    ram_array_q_12, ram_array_q_13, ram_array_q_14,
		    ram_array_q_15, ram_array_q_16, ram_array_q_17, 
		    ram_array_q_18, ram_array_q_19; 
wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, data_reg_3,
		     data_reg_4, data_reg_5, data_reg_6, data_reg_7,
		     data_reg_8, data_reg_9, data_reg_10, data_reg_11, 
		     data_reg_12, data_reg_13, data_reg_14, data_reg_15, 
	             data_reg_16, data_reg_17, data_reg_18, data_reg_19;

wire 		we, re_l;

assign we = 1'b1;
assign re_l = 1'b0;

/* Modelling the read port */
/* Assuming address trigerred operation only */
//assignment
assign
    data_reg_0 = ( fifo_wr[0] == 1'b1 ) ? data_in : ram_array_q_0,
    data_reg_1 = ( fifo_wr[1] == 1'b1 ) ? data_in : ram_array_q_1,
    data_reg_2 = ( fifo_wr[2] == 1'b1 ) ? data_in : ram_array_q_2,
    data_reg_3 = ( fifo_wr[3] == 1'b1 ) ? data_in : ram_array_q_3,
    data_reg_4 = ( fifo_wr[4] == 1'b1 ) ? data_in : ram_array_q_4,
    data_reg_5 = ( fifo_wr[5] == 1'b1 ) ? data_in : ram_array_q_5,
    data_reg_6 = ( fifo_wr[6] == 1'b1 ) ? data_in : ram_array_q_6,
    data_reg_7 = ( fifo_wr[7] == 1'b1 ) ? data_in : ram_array_q_7,
    data_reg_8 = ( fifo_wr[8] == 1'b1 ) ? data_in : ram_array_q_8,
    data_reg_9 = ( fifo_wr[9] == 1'b1 ) ? data_in : ram_array_q_9,
    data_reg_10 = ( fifo_wr[10] == 1'b1 ) ? data_in : ram_array_q_10,
    data_reg_11 = ( fifo_wr[11] == 1'b1 ) ? data_in : ram_array_q_11,
    data_reg_12 = ( fifo_wr[12] == 1'b1 ) ? data_in : ram_array_q_12,
    data_reg_13 = ( fifo_wr[13] == 1'b1 ) ? data_in : ram_array_q_13,
    data_reg_14 = ( fifo_wr[14] == 1'b1 ) ? data_in : ram_array_q_14,
    data_reg_15 = ( fifo_wr[15] == 1'b1 ) ? data_in : ram_array_q_15,
    data_reg_16 = ( fifo_wr[16] == 1'b1 ) ? data_in : ram_array_q_16,
    data_reg_17 = ( fifo_wr[17] == 1'b1 ) ? data_in : ram_array_q_17,
    data_reg_18 = ( fifo_wr[18] == 1'b1 ) ? data_in : ram_array_q_18,
    data_reg_19 = ( fifo_wr[19] == 1'b1 ) ? data_in : ram_array_q_19;


assign #read_access_time data_out1 = re_l ? 15'b0 : data_out1_i;
assign #read_access_time data_out2 = re_l ? 15'b0 : data_out2_i;


always @(
    ram_array_q_0	or 
    ram_array_q_1	or 
    ram_array_q_2	or 
    ram_array_q_3	or 
    ram_array_q_4       or
    ram_array_q_5       or
    ram_array_q_6       or
    ram_array_q_7       or 
    ram_array_q_8       or
    ram_array_q_9       or
    ram_array_q_10      or
    ram_array_q_11      or 
    ram_array_q_12      or 
    ram_array_q_13      or 
    ram_array_q_14      or 
    ram_array_q_15      or 
    ram_array_q_16      or 
    ram_array_q_17      or 
    ram_array_q_18      or 
    ram_array_q_19      or 
    fifo_re1		or
    fifo_re2		)
begin
    case ( fifo_re1 )  // synopsys parallel_case full_case
    20'b00000000000000000001 : data_out1_i = ram_array_q_0;
    20'b00000000000000000010 : data_out1_i = ram_array_q_1;
    20'b00000000000000000100 : data_out1_i = ram_array_q_2;
    20'b00000000000000001000 : data_out1_i = ram_array_q_3;
    20'b00000000000000010000 : data_out1_i = ram_array_q_4;
    20'b00000000000000100000 : data_out1_i = ram_array_q_5;
    20'b00000000000001000000 : data_out1_i = ram_array_q_6;
    20'b00000000000010000000 : data_out1_i = ram_array_q_7;
    20'b00000000000100000000 : data_out1_i = ram_array_q_8;
    20'b00000000001000000000 : data_out1_i = ram_array_q_9;
    20'b00000000010000000000 : data_out1_i = ram_array_q_10;
    20'b00000000100000000000 : data_out1_i = ram_array_q_11;
    20'b00000001000000000000 : data_out1_i = ram_array_q_12;
    20'b00000010000000000000 : data_out1_i = ram_array_q_13;
    20'b00000100000000000000 : data_out1_i = ram_array_q_14;
    20'b00001000000000000000 : data_out1_i = ram_array_q_15;
    20'b00010000000000000000 : data_out1_i = ram_array_q_16;
    20'b00100000000000000000 : data_out1_i = ram_array_q_17;
    20'b01000000000000000000 : data_out1_i = ram_array_q_18;
    20'b10000000000000000000 : data_out1_i = ram_array_q_19;
    endcase

    case ( fifo_re2 )  // synopsys parallel_case full_case
    20'b00000000000000000001 : data_out2_i = ram_array_q_0;
    20'b00000000000000000010 : data_out2_i = ram_array_q_1;
    20'b00000000000000000100 : data_out2_i = ram_array_q_2;
    20'b00000000000000001000 : data_out2_i = ram_array_q_3;
    20'b00000000000000010000 : data_out2_i = ram_array_q_4;
    20'b00000000000000100000 : data_out2_i = ram_array_q_5;
    20'b00000000000001000000 : data_out2_i = ram_array_q_6;
    20'b00000000000010000000 : data_out2_i = ram_array_q_7;
    20'b00000000000100000000 : data_out2_i = ram_array_q_8;
    20'b00000000001000000000 : data_out2_i = ram_array_q_9;
    20'b00000000010000000000 : data_out2_i = ram_array_q_10;
    20'b00000000100000000000 : data_out2_i = ram_array_q_11;
    20'b00000001000000000000 : data_out2_i = ram_array_q_12;
    20'b00000010000000000000 : data_out2_i = ram_array_q_13;
    20'b00000100000000000000 : data_out2_i = ram_array_q_14;
    20'b00001000000000000000 : data_out2_i = ram_array_q_15;
    20'b00010000000000000000 : data_out2_i = ram_array_q_16;
    20'b00100000000000000000 : data_out2_i = ram_array_q_17;
    20'b01000000000000000000 : data_out2_i = ram_array_q_18;
    20'b10000000000000000000 : data_out2_i = ram_array_q_19;
    endcase
end


/* Modelling the write port */
always @(posedge clk or negedge rst_l) 
begin
    if(~rst_l) begin
	ram_array_q_0 <= #write_access_time 0;
	ram_array_q_1 <= #write_access_time 0;
	ram_array_q_2 <= #write_access_time 0; 
	ram_array_q_3 <= #write_access_time 0; 
        ram_array_q_4 <= #write_access_time 0;
        ram_array_q_5 <= #write_access_time 0;
        ram_array_q_6 <= #write_access_time 0;
        ram_array_q_7 <= #write_access_time 0; 
        ram_array_q_8 <= #write_access_time 0;
        ram_array_q_9 <= #write_access_time 0;
        ram_array_q_10 <= #write_access_time 0;
        ram_array_q_11 <= #write_access_time 0; 
        ram_array_q_12 <= #write_access_time 0; 
        ram_array_q_13 <= #write_access_time 0; 
        ram_array_q_14 <= #write_access_time 0; 
        ram_array_q_15 <= #write_access_time 0; 
        ram_array_q_16 <= #write_access_time 0; 
        ram_array_q_17 <= #write_access_time 0; 
        ram_array_q_18 <= #write_access_time 0; 
        ram_array_q_19 <= #write_access_time 0; 
    end
    else begin
	ram_array_q_0 <= #write_access_time ram_array_d_0;
	ram_array_q_1 <= #write_access_time ram_array_d_1;
	ram_array_q_2 <= #write_access_time ram_array_d_2;
	ram_array_q_3 <= #write_access_time ram_array_d_3;
        ram_array_q_4 <= #write_access_time ram_array_d_4;
        ram_array_q_5 <= #write_access_time ram_array_d_5;
        ram_array_q_6 <= #write_access_time ram_array_d_6;
        ram_array_q_7 <= #write_access_time ram_array_d_7;
        ram_array_q_8 <= #write_access_time ram_array_d_8;
        ram_array_q_9 <= #write_access_time ram_array_d_9;
        ram_array_q_10 <= #write_access_time ram_array_d_10;
        ram_array_q_11 <= #write_access_time ram_array_d_11;
        ram_array_q_12 <= #write_access_time ram_array_d_12;
        ram_array_q_13 <= #write_access_time ram_array_d_13;
        ram_array_q_14 <= #write_access_time ram_array_d_14;
        ram_array_q_15 <= #write_access_time ram_array_d_15;
        ram_array_q_16 <= #write_access_time ram_array_d_16;
        ram_array_q_17 <= #write_access_time ram_array_d_17;
        ram_array_q_18 <= #write_access_time ram_array_d_18;
        ram_array_q_19 <= #write_access_time ram_array_d_19;
    end
end
         
always @( 
    we 			or 
    data_reg_0 		or 
    data_reg_1 		or 
    data_reg_2		or 
    data_reg_3		or
    data_reg_4          or
    data_reg_5          or
    data_reg_6          or
    data_reg_7          or
    data_reg_8          or
    data_reg_9          or
    data_reg_10         or
    data_reg_11         or
    data_reg_12         or
    data_reg_13         or
    data_reg_14         or
    data_reg_15         or
    data_reg_16         or
    data_reg_17         or
    data_reg_18         or
    data_reg_19         or
    ram_array_q_0 	or 
    ram_array_q_1	or
    ram_array_q_2	or
    ram_array_q_3	or
    ram_array_q_4       or
    ram_array_q_5       or
    ram_array_q_6       or
    ram_array_q_7	or
    ram_array_q_8       or
    ram_array_q_9       or
    ram_array_q_10      or
    ram_array_q_11      or
    ram_array_q_12      or
    ram_array_q_13      or
    ram_array_q_14      or
    ram_array_q_15      or
    ram_array_q_16      or
    ram_array_q_17      or
    ram_array_q_18      or
    ram_array_q_19	)
begin
    if(we) begin
	ram_array_d_0 <= #write_access_time data_reg_0;
	ram_array_d_1 <= #write_access_time data_reg_1;
	ram_array_d_2 <= #write_access_time data_reg_2;
	ram_array_d_3 <= #write_access_time data_reg_3;
        ram_array_d_4 <= #write_access_time data_reg_4;
        ram_array_d_5 <= #write_access_time data_reg_5;
        ram_array_d_6 <= #write_access_time data_reg_6;
        ram_array_d_7 <= #write_access_time data_reg_7; 
        ram_array_d_8 <= #write_access_time data_reg_8;
        ram_array_d_9 <= #write_access_time data_reg_9;
        ram_array_d_10 <= #write_access_time data_reg_10;
        ram_array_d_11 <= #write_access_time data_reg_11; 
        ram_array_d_12 <= #write_access_time data_reg_12; 
        ram_array_d_13 <= #write_access_time data_reg_13; 
        ram_array_d_14 <= #write_access_time data_reg_14; 
        ram_array_d_15 <= #write_access_time data_reg_15; 
        ram_array_d_16 <= #write_access_time data_reg_16; 
        ram_array_d_17 <= #write_access_time data_reg_17; 
        ram_array_d_18 <= #write_access_time data_reg_18; 
        ram_array_d_19 <= #write_access_time data_reg_19; 
    end
    else begin
	ram_array_d_0 <= #write_access_time ram_array_q_0;
	ram_array_d_1 <= #write_access_time ram_array_q_1;
	ram_array_d_2 <= #write_access_time ram_array_q_2;
	ram_array_d_3 <= #write_access_time ram_array_q_3;
        ram_array_d_4 <= #write_access_time ram_array_q_4;
        ram_array_d_5 <= #write_access_time ram_array_q_5;
        ram_array_d_6 <= #write_access_time ram_array_q_6;
        ram_array_d_7 <= #write_access_time ram_array_q_7;
        ram_array_d_8 <= #write_access_time ram_array_q_8;
        ram_array_d_9 <= #write_access_time ram_array_q_9;
        ram_array_d_10 <= #write_access_time ram_array_q_10;
        ram_array_d_11 <= #write_access_time ram_array_q_11;
        ram_array_d_12 <= #write_access_time ram_array_q_12;
        ram_array_d_13 <= #write_access_time ram_array_q_13;
        ram_array_d_14 <= #write_access_time ram_array_q_14;
        ram_array_d_15 <= #write_access_time ram_array_q_15;
        ram_array_d_16 <= #write_access_time ram_array_q_16;
        ram_array_d_17 <= #write_access_time ram_array_q_17;
        ram_array_d_18 <= #write_access_time ram_array_q_18;
        ram_array_d_19 <= #write_access_time ram_array_q_19;
    end
end

endmodule

//************************************************************
// Description:
//
//    Started from ram16x13_syn.v and modified to have 
//    width of 14
//
//    Bit 13 is the running Disparity polarity bits 
//    Bit 12 is the Disparity Error bit
//    Bit 11 is the Resync/Sync_status bit
//    Bit 10 is the Invalid Code bit
//    Bit 9 to 0 -- Encoded 10-bit data
// **********************************************************


`timescale 1ps / 1ps

module arriagx_hssi_ram16x14_syn (
    clk,
    rst_l, 
    addr_wr,
    addr_rd1,
    addr_rd2,
    data_in,
    we,
    re_l,
    data_out1,
    data_out2
    );

input 		clk;
input 		rst_l;
input 	[15:0]	addr_wr;
input 	[15:0] 	addr_rd1;
input 	[15:0] 	addr_rd2;
input 	[13:0] 	data_in;
input 		we, re_l;
output 	[13:0] 	data_out1;
output 	[13:0] 	data_out2;

parameter read_access_time = 0;
parameter write_access_time = 0;
parameter ram_width = 14;

reg [ram_width-1:0] data_out1_i, data_out2_i;
reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, ram_array_d_3,
		    ram_array_d_4, ram_array_d_5, ram_array_d_6, ram_array_d_7,
		    ram_array_d_8, ram_array_d_9, ram_array_d_10, 
                    ram_array_d_11,
		    ram_array_d_12, ram_array_d_13, ram_array_d_14, 
                    ram_array_d_15,
		    ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3,
		    ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7,
		    ram_array_q_8, ram_array_q_9, ram_array_q_10, 
                    ram_array_q_11,
		    ram_array_q_12, ram_array_q_13, ram_array_q_14, 
                    ram_array_q_15;
wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, data_reg_3,
		     data_reg_4, data_reg_5, data_reg_6, data_reg_7,
		     data_reg_8, data_reg_9, data_reg_10, data_reg_11,
		     data_reg_12, data_reg_13, data_reg_14, data_reg_15;

 /* Modelling the read port */
 /* Assuming address trigerred operation only */
//assignment
assign
    data_reg_0 = ( addr_wr[0] == 1'b1 ) ? data_in : ram_array_q_0,
    data_reg_1 = ( addr_wr[1] == 1'b1 ) ? data_in : ram_array_q_1,
    data_reg_2 = ( addr_wr[2] == 1'b1 ) ? data_in : ram_array_q_2,
    data_reg_3 = ( addr_wr[3] == 1'b1 ) ? data_in : ram_array_q_3,
    data_reg_4 = ( addr_wr[4] == 1'b1 ) ? data_in : ram_array_q_4,
    data_reg_5 = ( addr_wr[5] == 1'b1 ) ? data_in : ram_array_q_5,
    data_reg_6 = ( addr_wr[6] == 1'b1 ) ? data_in : ram_array_q_6,
    data_reg_7 = ( addr_wr[7] == 1'b1 ) ? data_in : ram_array_q_7,
    data_reg_8 = ( addr_wr[8] == 1'b1 ) ? data_in : ram_array_q_8,
    data_reg_9 = ( addr_wr[9] == 1'b1 ) ? data_in : ram_array_q_9,
    data_reg_10 = ( addr_wr[10] == 1'b1 ) ? data_in : ram_array_q_10,
    data_reg_11 = ( addr_wr[11] == 1'b1 ) ? data_in : ram_array_q_11,
    data_reg_12 = ( addr_wr[12] == 1'b1 ) ? data_in : ram_array_q_12,
    data_reg_13 = ( addr_wr[13] == 1'b1 ) ? data_in : ram_array_q_13,
    data_reg_14 = ( addr_wr[14] == 1'b1 ) ? data_in : ram_array_q_14,
    data_reg_15 = ( addr_wr[15] == 1'b1 ) ? data_in : ram_array_q_15;


assign #read_access_time data_out1 = re_l ? 13'b0000000000000 : data_out1_i;
assign #read_access_time data_out2 = re_l ? 13'b0000000000000 : data_out2_i;


always @(
    ram_array_q_0	or 
    ram_array_q_1	or 
    ram_array_q_2	or 
    ram_array_q_3	or 
    ram_array_q_4       or
    ram_array_q_5       or
    ram_array_q_6       or
    ram_array_q_7       or 
    ram_array_q_8       or
    ram_array_q_9       or
    ram_array_q_10      or
    ram_array_q_11      or 
    ram_array_q_12      or
    ram_array_q_13      or
    ram_array_q_14      or
    ram_array_q_15      or 
    addr_rd1		or
    addr_rd2		)
begin
    case ( addr_rd1 )  // synopsys parallel_case full_case
    16'b0000000000000001 : data_out1_i = ram_array_q_0;
    16'b0000000000000010 : data_out1_i = ram_array_q_1;
    16'b0000000000000100 : data_out1_i = ram_array_q_2;
    16'b0000000000001000 : data_out1_i = ram_array_q_3;
    16'b0000000000010000 : data_out1_i = ram_array_q_4;
    16'b0000000000100000 : data_out1_i = ram_array_q_5;
    16'b0000000001000000 : data_out1_i = ram_array_q_6;
    16'b0000000010000000 : data_out1_i = ram_array_q_7;
    16'b0000000100000000 : data_out1_i = ram_array_q_8;
    16'b0000001000000000 : data_out1_i = ram_array_q_9;
    16'b0000010000000000 : data_out1_i = ram_array_q_10;
    16'b0000100000000000 : data_out1_i = ram_array_q_11;
    16'b0001000000000000 : data_out1_i = ram_array_q_12;
    16'b0010000000000000 : data_out1_i = ram_array_q_13;
    16'b0100000000000000 : data_out1_i = ram_array_q_14;
    16'b1000000000000000 : data_out1_i = ram_array_q_15;
    endcase

    case ( addr_rd2 )  // synopsys parallel_case full_case
    16'b0000000000000001 : data_out2_i = ram_array_q_0;
    16'b0000000000000010 : data_out2_i = ram_array_q_1;
    16'b0000000000000100 : data_out2_i = ram_array_q_2;
    16'b0000000000001000 : data_out2_i = ram_array_q_3;
    16'b0000000000010000 : data_out2_i = ram_array_q_4;
    16'b0000000000100000 : data_out2_i = ram_array_q_5;
    16'b0000000001000000 : data_out2_i = ram_array_q_6;
    16'b0000000010000000 : data_out2_i = ram_array_q_7;
    16'b0000000100000000 : data_out2_i = ram_array_q_8;
    16'b0000001000000000 : data_out2_i = ram_array_q_9;
    16'b0000010000000000 : data_out2_i = ram_array_q_10;
    16'b0000100000000000 : data_out2_i = ram_array_q_11;
    16'b0001000000000000 : data_out2_i = ram_array_q_12;
    16'b0010000000000000 : data_out2_i = ram_array_q_13;
    16'b0100000000000000 : data_out2_i = ram_array_q_14;
    16'b1000000000000000 : data_out2_i = ram_array_q_15;
    endcase

end


/* Modelling the write port */
always @(posedge clk or negedge rst_l) 
begin
    if(~rst_l) begin
	ram_array_q_0 <= #write_access_time 0;
	ram_array_q_1 <= #write_access_time 0;
	ram_array_q_2 <= #write_access_time 0; 
	ram_array_q_3 <= #write_access_time 0; 
        ram_array_q_4 <= #write_access_time 0;
        ram_array_q_5 <= #write_access_time 0;
        ram_array_q_6 <= #write_access_time 0;
        ram_array_q_7 <= #write_access_time 0; 
        ram_array_q_8 <= #write_access_time 0;
        ram_array_q_9 <= #write_access_time 0;
        ram_array_q_10 <= #write_access_time 0;
        ram_array_q_11 <= #write_access_time 0; 
        ram_array_q_12 <= #write_access_time 0;
        ram_array_q_13 <= #write_access_time 0;
        ram_array_q_14 <= #write_access_time 0;
        ram_array_q_15 <= #write_access_time 0; 
    end
    else begin
	ram_array_q_0 <= #write_access_time ram_array_d_0;
	ram_array_q_1 <= #write_access_time ram_array_d_1;
	ram_array_q_2 <= #write_access_time ram_array_d_2;
	ram_array_q_3 <= #write_access_time ram_array_d_3;
        ram_array_q_4 <= #write_access_time ram_array_d_4;
        ram_array_q_5 <= #write_access_time ram_array_d_5;
        ram_array_q_6 <= #write_access_time ram_array_d_6;
        ram_array_q_7 <= #write_access_time ram_array_d_7;
        ram_array_q_8 <= #write_access_time ram_array_d_8;
        ram_array_q_9 <= #write_access_time ram_array_d_9;
        ram_array_q_10 <= #write_access_time ram_array_d_10;
        ram_array_q_11 <= #write_access_time ram_array_d_11;
        ram_array_q_12 <= #write_access_time ram_array_d_12;
        ram_array_q_13 <= #write_access_time ram_array_d_13;
        ram_array_q_14 <= #write_access_time ram_array_d_14;
        ram_array_q_15 <= #write_access_time ram_array_d_15;
    end
end
         

always @( 
    we 			or 
    data_reg_0 		or 
    data_reg_1 		or 
    data_reg_2		or 
    data_reg_3		or
    data_reg_4          or
    data_reg_5          or
    data_reg_6          or
    data_reg_7          or
    data_reg_8          or
    data_reg_9          or
    data_reg_10         or
    data_reg_11         or
    data_reg_12         or
    data_reg_13         or
    data_reg_14         or
    data_reg_15         or
    ram_array_q_0 	or 
    ram_array_q_1	or
    ram_array_q_2	or
    ram_array_q_3	or
    ram_array_q_4       or
    ram_array_q_5       or
    ram_array_q_6       or
    ram_array_q_7	or
    ram_array_q_8       or
    ram_array_q_9       or
    ram_array_q_10      or
    ram_array_q_11	or
    ram_array_q_12      or
    ram_array_q_13      or
    ram_array_q_14      or
    ram_array_q_15	)
begin
    if(we) begin
	ram_array_d_0 <= #write_access_time data_reg_0;
	ram_array_d_1 <= #write_access_time data_reg_1;
	ram_array_d_2 <= #write_access_time data_reg_2;
	ram_array_d_3 <= #write_access_time data_reg_3;
        ram_array_d_4 <= #write_access_time data_reg_4;
        ram_array_d_5 <= #write_access_time data_reg_5;
        ram_array_d_6 <= #write_access_time data_reg_6;
        ram_array_d_7 <= #write_access_time data_reg_7; 
        ram_array_d_8 <= #write_access_time data_reg_8;
        ram_array_d_9 <= #write_access_time data_reg_9;
        ram_array_d_10 <= #write_access_time data_reg_10;
        ram_array_d_11 <= #write_access_time data_reg_11; 
        ram_array_d_12 <= #write_access_time data_reg_12;
        ram_array_d_13 <= #write_access_time data_reg_13;
        ram_array_d_14 <= #write_access_time data_reg_14;
        ram_array_d_15 <= #write_access_time data_reg_15; 
    end
    else begin
	ram_array_d_0 <= #write_access_time ram_array_q_0;
	ram_array_d_1 <= #write_access_time ram_array_q_1;
	ram_array_d_2 <= #write_access_time ram_array_q_2;
	ram_array_d_3 <= #write_access_time ram_array_q_3;
        ram_array_d_4 <= #write_access_time ram_array_q_4;
        ram_array_d_5 <= #write_access_time ram_array_q_5;
        ram_array_d_6 <= #write_access_time ram_array_q_6;
        ram_array_d_7 <= #write_access_time ram_array_q_7;
        ram_array_d_8 <= #write_access_time ram_array_q_8;
        ram_array_d_9 <= #write_access_time ram_array_q_9;
        ram_array_d_10 <= #write_access_time ram_array_q_10;
        ram_array_d_11 <= #write_access_time ram_array_q_11;
        ram_array_d_12 <= #write_access_time ram_array_q_12;
        ram_array_d_13 <= #write_access_time ram_array_q_13;
        ram_array_d_14 <= #write_access_time ram_array_q_14;
        ram_array_d_15 <= #write_access_time ram_array_q_15;

    end
end

endmodule

module arriagx_hssi_ram8x65_syn (
    rst_l, 
    clk,
    fifo_wr,
    data_in,
    fifo_re,
    data_out
    );

input 		rst_l;
input 		clk;
input 	[7:0]	fifo_wr;
input 	[64:0] 	data_in;
input 	[7:0] 	fifo_re;
output 	[64:0] 	data_out;

parameter read_access_time = 0;
parameter write_access_time = 0;
parameter ram_width = 65;

reg [ram_width-1:0] data_out_i;
reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, 
                    ram_array_d_3, ram_array_d_4, ram_array_d_5, 
                    ram_array_d_6, ram_array_d_7, 
 		    ram_array_q_0, ram_array_q_1, ram_array_q_2, 
                    ram_array_q_3, ram_array_q_4, ram_array_q_5, 
                    ram_array_q_6, ram_array_q_7;

wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, data_reg_3,
		     data_reg_4, data_reg_5, data_reg_6, data_reg_7;

wire 		we, re_l;

assign we = 1'b1;
assign re_l = 1'b0;

/* Modelling the read port */
/* Assuming address trigerred operation only */
//assignment
assign
    data_reg_0 = ( fifo_wr[0] == 1'b1 ) ? data_in : ram_array_q_0,
    data_reg_1 = ( fifo_wr[1] == 1'b1 ) ? data_in : ram_array_q_1,
    data_reg_2 = ( fifo_wr[2] == 1'b1 ) ? data_in : ram_array_q_2,
    data_reg_3 = ( fifo_wr[3] == 1'b1 ) ? data_in : ram_array_q_3,
    data_reg_4 = ( fifo_wr[4] == 1'b1 ) ? data_in : ram_array_q_4,
    data_reg_5 = ( fifo_wr[5] == 1'b1 ) ? data_in : ram_array_q_5,
    data_reg_6 = ( fifo_wr[6] == 1'b1 ) ? data_in : ram_array_q_6,
    data_reg_7 = ( fifo_wr[7] == 1'b1 ) ? data_in : ram_array_q_7;

assign  data_out = re_l ? 60'b0 : data_out_i;

always @(
    ram_array_q_0	or 
    ram_array_q_1	or 
    ram_array_q_2	or 
    ram_array_q_3	or 
    ram_array_q_4       or
    ram_array_q_5       or
    ram_array_q_6       or
    ram_array_q_7       or 
    fifo_re		
    )
begin
    case ( fifo_re )  // synopsys parallel_case full_case
    8'b00000001 : data_out_i = ram_array_q_0;
    8'b00000010 : data_out_i = ram_array_q_1;
    8'b00000100 : data_out_i = ram_array_q_2;
    8'b00001000 : data_out_i = ram_array_q_3;
    8'b00010000 : data_out_i = ram_array_q_4;
    8'b00100000 : data_out_i = ram_array_q_5;
    8'b01000000 : data_out_i = ram_array_q_6;
    8'b10000000 : data_out_i = ram_array_q_7;
    default     : data_out_i = ram_array_q_0;
    endcase

end


/* Modelling the write port */
always @(posedge clk or negedge rst_l) 
begin
    if(~rst_l) begin
	ram_array_q_0 <= #write_access_time 0;
	ram_array_q_1 <= #write_access_time 0;
	ram_array_q_2 <= #write_access_time 0; 
	ram_array_q_3 <= #write_access_time 0; 
        ram_array_q_4 <= #write_access_time 0;
        ram_array_q_5 <= #write_access_time 0;
        ram_array_q_6 <= #write_access_time 0;
        ram_array_q_7 <= #write_access_time 0; 
    end
    else begin
	ram_array_q_0 <= #write_access_time ram_array_d_0;
	ram_array_q_1 <= #write_access_time ram_array_d_1;
	ram_array_q_2 <= #write_access_time ram_array_d_2;
	ram_array_q_3 <= #write_access_time ram_array_d_3;
        ram_array_q_4 <= #write_access_time ram_array_d_4;
        ram_array_q_5 <= #write_access_time ram_array_d_5;
        ram_array_q_6 <= #write_access_time ram_array_d_6;
        ram_array_q_7 <= #write_access_time ram_array_d_7;
    end
end
         
always @( 
    we 			or 
    data_reg_0 		or 
    data_reg_1 		or 
    data_reg_2		or 
    data_reg_3		or
    data_reg_4          or
    data_reg_5          or
    data_reg_6          or
    data_reg_7          or
    ram_array_q_0 	or 
    ram_array_q_1	or
    ram_array_q_2	or
    ram_array_q_3	or
    ram_array_q_4       or
    ram_array_q_5       or
    ram_array_q_6       or
    ram_array_q_7	
       )
begin
    if(we) begin
	ram_array_d_0 <=  data_reg_0;
	ram_array_d_1 <=  data_reg_1;
	ram_array_d_2 <=  data_reg_2;
	ram_array_d_3 <=  data_reg_3;
        ram_array_d_4 <=  data_reg_4;
        ram_array_d_5 <=  data_reg_5;
        ram_array_d_6 <=  data_reg_6;
        ram_array_d_7 <=  data_reg_7; 
    end
    else begin
	ram_array_d_0 <=  ram_array_q_0;
	ram_array_d_1 <=  ram_array_q_1;
	ram_array_d_2 <=  ram_array_q_2;
	ram_array_d_3 <=  ram_array_q_3;
        ram_array_d_4 <=  ram_array_q_4;
        ram_array_d_5 <=  ram_array_q_5;
        ram_array_d_6 <=  ram_array_q_6;
        ram_array_d_7 <=  ram_array_q_7;
    end
end

endmodule
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 152 mux21 611 oper_add 8 oper_decoder 4 oper_mux 37 oper_selector 4 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_bist_ver
	( 
	bistdone,
	bisterr,
	clk_2,
	cur_state,
	err_ctl,
	err_data,
	prbs_done,
	prbs_err,
	rbist_clr_rx,
	rbist_sel,
	rbisten_rx,
	rcxpat_chnl_sel,
	rdwidth_rx,
	rpma_doublewidth_rx,
	rpmadwidth_rx,
	rxc,
	rxd,
	selftest_done,
	selftest_err,
	soft_reset,
	sync_status) /* synthesis synthesis_clearbox=1 */;
	output   bistdone;
	output   bisterr;
	input   clk_2;
	output   [4:0]  cur_state;
	output   [1:0]  err_ctl;
	output   [15:0]  err_data;
	input   prbs_done;
	input   prbs_err;
	input   rbist_clr_rx;
	input   [1:0]  rbist_sel;
	input   rbisten_rx;
	input   [1:0]  rcxpat_chnl_sel;
	input   rdwidth_rx;
	input   rpma_doublewidth_rx;
	input   rpmadwidth_rx;
	input   [3:0]  rxc;
	input   [63:0]  rxd;
	output   selftest_done;
	output   selftest_err;
	input   soft_reset;
	input   sync_status;

	reg	n0liiO49;
	reg	n0liiO50;
	reg	n0lili47;
	reg	n0lili48;
	reg	n0O00O25;
	reg	n0O00O26;
	reg	n0O10l45;
	reg	n0O10l46;
	reg	n0O10O43;
	reg	n0O10O44;
	reg	n0O1ii41;
	reg	n0O1ii42;
	reg	n0O1il39;
	reg	n0O1il40;
	reg	n0O1iO37;
	reg	n0O1iO38;
	reg	n0O1li35;
	reg	n0O1li36;
	reg	n0O1ll33;
	reg	n0O1ll34;
	reg	n0O1lO31;
	reg	n0O1lO32;
	reg	n0O1Oi29;
	reg	n0O1Oi30;
	reg	n0O1Ol27;
	reg	n0O1Ol28;
	reg	n0Oili23;
	reg	n0Oili24;
	reg	n0OiOi21;
	reg	n0OiOi22;
	reg	n0Ol0l19;
	reg	n0Ol0l20;
	reg	n0Olii17;
	reg	n0Olii18;
	reg	n0Olil15;
	reg	n0Olil16;
	reg	n0OliO13;
	reg	n0OliO14;
	reg	n0Olll11;
	reg	n0Olll12;
	reg	n0OlOi10;
	reg	n0OlOi9;
	reg	n0OlOO7;
	reg	n0OlOO8;
	reg	n0OOii5;
	reg	n0OOii6;
	reg	n0OOiO3;
	reg	n0OOiO4;
	reg	n0OOll1;
	reg	n0OOll2;
	reg	ni00i;
	reg	ni01l;
	reg	ni1O1O;
	reg	niiilO;
	reg	niiiOi;
	reg	niiiOl;
	reg	niiiOO;
	reg	niil0i;
	reg	niil0l;
	reg	niil0O;
	reg	niil1i;
	reg	niil1l;
	reg	niil1O;
	reg	niilii;
	reg	niilil;
	reg	niiliO;
	reg	niilli;
	reg	niilll;
	reg	niillO;
	reg	niilOi;
	reg	niilOl;
	reg	niiO0i;
	reg	niiO1O;
	reg	nll00O;
	reg	nll0ii;
	wire	wire_ni01O_CLRN;
	reg	n11ii;
	reg	ni00l;
	reg	ni00O;
	reg	ni01i;
	reg	ni0ii;
	reg	ni0il;
	reg	ni0iO;
	reg	ni0li;
	reg	ni0ll;
	reg	ni0lO;
	reg	ni0Oi;
	reg	ni0Ol;
	reg	nii1i;
	reg	niilOO;
	reg	niiO1i;
	reg	niiO1l;
	reg	niiOii;
	reg	niiOil;
	reg	niiOiO;
	reg	niiOli;
	reg	niiOll;
	reg	niiOlO;
	reg	niiOOi;
	reg	niiOOl;
	reg	niiOOO;
	reg	nil00i;
	reg	nil00l;
	reg	nil00O;
	reg	nil01i;
	reg	nil01l;
	reg	nil01O;
	reg	nil0ii;
	reg	nil10i;
	reg	nil10l;
	reg	nil10O;
	reg	nil11i;
	reg	nil11l;
	reg	nil11O;
	reg	nil1ii;
	reg	nil1il;
	reg	nil1iO;
	reg	nil1li;
	reg	nil1ll;
	reg	nil1lO;
	reg	nil1Oi;
	reg	nil1Ol;
	reg	nil1OO;
	reg	nl1Oii;
	reg	nll00l;
	reg	nll0il;
	reg	nll0iO;
	reg	nll0li;
	reg	nll0ll;
	reg	nll0lO;
	reg	nll0Oi;
	reg	nll0Ol;
	reg	nll0OO;
	reg	nlli0i;
	reg	nlli0l;
	reg	nlli0O;
	reg	nlli1i;
	reg	nlli1l;
	reg	nlli1O;
	reg	nlliii;
	reg	nlliil;
	reg	nlliiO;
	reg	nllili;
	reg	nllill;
	reg	nllilO;
	reg	nlliOi;
	reg	nlliOl;
	reg	nlliOO;
	reg	nlll0i;
	reg	nlll1i;
	reg	nlll1l;
	reg	nlll1O;
	reg	ni0OO_clk_prev;
	wire	wire_ni0OO_CLRN;
	wire	wire_ni0OO_PRN;
	reg	niiO0O;
	reg	niiO0l_clk_prev;
	wire	wire_niiO0l_CLRN;
	wire	wire_niiO0l_PRN;
	wire	wire_n000i_dataout;
	wire	wire_n000l_dataout;
	wire	wire_n000O_dataout;
	wire	wire_n001i_dataout;
	wire	wire_n001l_dataout;
	wire	wire_n001O_dataout;
	wire	wire_n00i_dataout;
	wire	wire_n00ii_dataout;
	wire	wire_n00il_dataout;
	wire	wire_n00iO_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00li_dataout;
	wire	wire_n00ll_dataout;
	wire	wire_n00lO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n00Oi_dataout;
	wire	wire_n00Ol_dataout;
	wire	wire_n00OO_dataout;
	wire	wire_n010i_dataout;
	wire	wire_n010l_dataout;
	wire	wire_n010O_dataout;
	wire	wire_n011i_dataout;
	wire	wire_n011l_dataout;
	wire	wire_n011O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01ii_dataout;
	wire	wire_n01il_dataout;
	wire	wire_n01iO_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01li_dataout;
	wire	wire_n01ll_dataout;
	wire	wire_n01lO_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n01Oi_dataout;
	wire	wire_n01Ol_dataout;
	wire	wire_n01OO_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0i0i_dataout;
	wire	wire_n0i0l_dataout;
	wire	wire_n0i0O_dataout;
	wire	wire_n0i1i_dataout;
	wire	wire_n0i1l_dataout;
	wire	wire_n0i1O_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0iii_dataout;
	wire	wire_n0iil_dataout;
	wire	wire_n0iiO_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0ili_dataout;
	wire	wire_n0ill_dataout;
	wire	wire_n0ilO_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0iOi_dataout;
	wire	wire_n0iOl_dataout;
	wire	wire_n0iOO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0l0i_dataout;
	wire	wire_n0l0l_dataout;
	wire	wire_n0l0O_dataout;
	wire	wire_n0l1i_dataout;
	wire	wire_n0l1l_dataout;
	wire	wire_n0l1O_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0lii_dataout;
	wire	wire_n0lil_dataout;
	wire	wire_n0liO_dataout;
	wire	wire_n0lli_dataout;
	wire	wire_n0lll_dataout;
	wire	wire_n0llO_dataout;
	wire	wire_n0lOi_dataout;
	wire	wire_n0lOl_dataout;
	wire	wire_n0lOO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0O0i_dataout;
	wire	wire_n0O0l_dataout;
	wire	wire_n0O0O_dataout;
	wire	wire_n0O1i_dataout;
	wire	wire_n0O1l_dataout;
	wire	wire_n0O1O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Oii_dataout;
	wire	wire_n0Oil_dataout;
	wire	wire_n0OiO_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0Oli_dataout;
	wire	wire_n0Oll_dataout;
	wire	wire_n0OlO_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n0OOi_dataout;
	wire	wire_n0OOl_dataout;
	wire	wire_n0OOO_dataout;
	wire	wire_n100O_dataout;
	wire	wire_n10ii_dataout;
	wire	wire_n10il_dataout;
	wire	wire_n10iO_dataout;
	wire	wire_n10li_dataout;
	wire	wire_n10ll_dataout;
	wire	wire_n10lO_dataout;
	wire	wire_n10Oi_dataout;
	wire	wire_n10Ol_dataout;
	wire	wire_n10OO_dataout;
	wire	wire_n1i0i_dataout;
	wire	wire_n1i0l_dataout;
	wire	wire_n1i0O_dataout;
	wire	wire_n1i1i_dataout;
	wire	wire_n1i1l_dataout;
	wire	wire_n1iii_dataout;
	wire	wire_n1iil_dataout;
	wire	wire_n1iiO_dataout;
	wire	wire_n1ili_dataout;
	wire	wire_n1ill_dataout;
	wire	wire_n1ilO_dataout;
	wire	wire_n1iOi_dataout;
	wire	wire_n1iOl_dataout;
	wire	wire_n1iOO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1l0i_dataout;
	wire	wire_n1l0l_dataout;
	wire	wire_n1l0O_dataout;
	wire	wire_n1l1i_dataout;
	wire	wire_n1l1l_dataout;
	wire	wire_n1l1O_dataout;
	wire	wire_n1lii_dataout;
	wire	wire_n1lil_dataout;
	wire	wire_n1liO_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lli_dataout;
	wire	wire_n1lll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1lOi_dataout;
	wire	wire_n1lOl_dataout;
	wire	wire_n1lOO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1O0i_dataout;
	wire	wire_n1O0l_dataout;
	wire	wire_n1O0O_dataout;
	wire	wire_n1O1i_dataout;
	wire	wire_n1O1l_dataout;
	wire	wire_n1O1O_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Oii_dataout;
	wire	wire_n1Oil_dataout;
	wire	wire_n1OiO_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1Oli_dataout;
	wire	wire_n1Oll_dataout;
	wire	wire_n1OlO_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_n1OOi_dataout;
	wire	wire_n1OOl_dataout;
	wire	wire_n1OOO_dataout;
	wire	wire_ni_dataout;
	wire	wire_ni000l_dataout;
	wire	wire_ni000O_dataout;
	wire	wire_ni001l_dataout;
	wire	wire_ni001O_dataout;
	wire	wire_ni00ii_dataout;
	wire	wire_ni00il_dataout;
	wire	wire_ni00iO_dataout;
	wire	wire_ni00li_dataout;
	wire	wire_ni00lO_dataout;
	wire	wire_ni00Oi_dataout;
	wire	wire_ni00OO_dataout;
	wire	wire_ni010i_dataout;
	wire	wire_ni010O_dataout;
	wire	wire_ni011i_dataout;
	wire	wire_ni011O_dataout;
	wire	wire_ni01ii_dataout;
	wire	wire_ni01il_dataout;
	wire	wire_ni01iO_dataout;
	wire	wire_ni01li_dataout;
	wire	wire_ni01ll_dataout;
	wire	wire_ni01lO_dataout;
	wire	wire_ni01Ol_dataout;
	wire	wire_ni01OO_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0i0i_dataout;
	wire	wire_ni0i0l_dataout;
	wire	wire_ni0i0O_dataout;
	wire	wire_ni0i1i_dataout;
	wire	wire_ni0i1O_dataout;
	wire	wire_ni0iii_dataout;
	wire	wire_ni0iil_dataout;
	wire	wire_ni0iiO_dataout;
	wire	wire_ni0ill_dataout;
	wire	wire_ni0ilO_dataout;
	wire	wire_ni0iOl_dataout;
	wire	wire_ni0iOO_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0l0i_dataout;
	wire	wire_ni0l0l_dataout;
	wire	wire_ni0l0O_dataout;
	wire	wire_ni0l1l_dataout;
	wire	wire_ni0l1O_dataout;
	wire	wire_ni0lii_dataout;
	wire	wire_ni0liO_dataout;
	wire	wire_ni0lli_dataout;
	wire	wire_ni0llO_dataout;
	wire	wire_ni0lOi_dataout;
	wire	wire_ni0lOl_dataout;
	wire	wire_ni0lOO_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni0O0i_dataout;
	wire	wire_ni0O0l_dataout;
	wire	wire_ni0O0O_dataout;
	wire	wire_ni0O1i_dataout;
	wire	wire_ni0O1l_dataout;
	wire	wire_ni0O1O_dataout;
	wire	wire_ni0Oii_dataout;
	wire	wire_ni0Oil_dataout;
	wire	wire_ni0OiO_dataout;
	wire	wire_ni0Oli_dataout;
	wire	wire_ni0OOi_dataout;
	wire	wire_ni0OOl_dataout;
	wire	wire_ni0OOO_dataout;
	wire	wire_ni10i_dataout;
	wire	wire_ni10l_dataout;
	wire	wire_ni10O_dataout;
	wire	wire_ni11i_dataout;
	wire	wire_ni11l_dataout;
	wire	wire_ni11O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1ii_dataout;
	wire	wire_ni1il_dataout;
	wire	wire_ni1iO_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1l0l_dataout;
	wire	wire_ni1l0O_dataout;
	wire	wire_ni1lii_dataout;
	wire	wire_ni1lil_dataout;
	wire	wire_ni1liO_dataout;
	wire	wire_ni1lli_dataout;
	wire	wire_ni1lll_dataout;
	wire	wire_ni1llO_dataout;
	wire	wire_ni1lOi_dataout;
	wire	wire_ni1lOl_dataout;
	wire	wire_ni1lOO_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_ni1O0i_dataout;
	wire	wire_ni1O0l_dataout;
	wire	wire_ni1O0O_dataout;
	wire	wire_ni1O1i_dataout;
	wire	wire_ni1Oii_dataout;
	wire	wire_ni1Oil_dataout;
	wire	wire_ni1OiO_dataout;
	wire	wire_ni1Oli_dataout;
	wire	wire_ni1Oll_dataout;
	wire	wire_ni1OOi_dataout;
	wire	wire_ni1OOl_dataout;
	wire	wire_ni1OOO_dataout;
	wire	wire_nii_dataout;
	wire	wire_nii00i_dataout;
	wire	wire_nii00l_dataout;
	wire	wire_nii00O_dataout;
	wire	wire_nii0i_dataout;
	wire	wire_nii0ii_dataout;
	wire	wire_nii0l_dataout;
	wire	wire_nii0ll_dataout;
	wire	wire_nii0O_dataout;
	wire	wire_nii0Oi_dataout;
	wire	wire_nii10i_dataout;
	wire	wire_nii10l_dataout;
	wire	wire_nii10O_dataout;
	wire	wire_nii11i_dataout;
	wire	wire_nii11l_dataout;
	wire	wire_nii11O_dataout;
	wire	wire_nii1ii_dataout;
	wire	wire_nii1il_dataout;
	wire	wire_nii1iO_dataout;
	wire	wire_nii1l_dataout;
	wire	wire_nii1li_dataout;
	wire	wire_nii1ll_dataout;
	wire	wire_nii1lO_dataout;
	wire	wire_nii1O_dataout;
	wire	wire_nii1Oi_dataout;
	wire	wire_niii_dataout;
	wire	wire_niiii_dataout;
	wire	wire_niiil_dataout;
	wire	wire_niiiO_dataout;
	wire	wire_niil_dataout;
	wire	wire_niili_dataout;
	wire	wire_niill_dataout;
	wire	wire_niilO_dataout;
	wire	wire_niiO_dataout;
	wire	wire_niiOi_dataout;
	wire	wire_nil_dataout;
	wire	wire_nil0il_dataout;
	wire	wire_nil0iO_dataout;
	wire	wire_nil0li_dataout;
	wire	wire_nil0ll_dataout;
	wire	wire_nil0lO_dataout;
	wire	wire_nil0Oi_dataout;
	wire	wire_nil0Ol_dataout;
	wire	wire_nil0OO_dataout;
	wire	wire_nili_dataout;
	wire	wire_nili0i_dataout;
	wire	wire_nili0l_dataout;
	wire	wire_nili0O_dataout;
	wire	wire_nili1i_dataout;
	wire	wire_nili1l_dataout;
	wire	wire_nili1O_dataout;
	wire	wire_niliii_dataout;
	wire	wire_niliil_dataout;
	wire	wire_niliiO_dataout;
	wire	wire_nilili_dataout;
	wire	wire_nilill_dataout;
	wire	wire_nililO_dataout;
	wire	wire_niliOi_dataout;
	wire	wire_niliOl_dataout;
	wire	wire_niliOO_dataout;
	wire	wire_nill_dataout;
	wire	wire_nill0i_dataout;
	wire	wire_nill0l_dataout;
	wire	wire_nill0O_dataout;
	wire	wire_nill1i_dataout;
	wire	wire_nill1l_dataout;
	wire	wire_nill1O_dataout;
	wire	wire_nillii_dataout;
	wire	wire_nillil_dataout;
	wire	wire_nilliO_dataout;
	wire	wire_nillli_dataout;
	wire	wire_nillll_dataout;
	wire	wire_nilllO_dataout;
	wire	wire_nillOi_dataout;
	wire	wire_nillOl_dataout;
	wire	wire_nillOO_dataout;
	wire	wire_nilO_dataout;
	wire	wire_nilO0i_dataout;
	wire	wire_nilO0l_dataout;
	wire	wire_nilO0O_dataout;
	wire	wire_nilO1i_dataout;
	wire	wire_nilO1l_dataout;
	wire	wire_nilO1O_dataout;
	wire	wire_nilOii_dataout;
	wire	wire_nilOil_dataout;
	wire	wire_nilOiO_dataout;
	wire	wire_nilOli_dataout;
	wire	wire_nilOll_dataout;
	wire	wire_nilOlO_dataout;
	wire	wire_nilOOi_dataout;
	wire	wire_nilOOl_dataout;
	wire	wire_nilOOO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niO00i_dataout;
	wire	wire_niO00l_dataout;
	wire	wire_niO00O_dataout;
	wire	wire_niO01i_dataout;
	wire	wire_niO01l_dataout;
	wire	wire_niO01O_dataout;
	wire	wire_niO0ii_dataout;
	wire	wire_niO0il_dataout;
	wire	wire_niO0iO_dataout;
	wire	wire_niO0li_dataout;
	wire	wire_niO0ll_dataout;
	wire	wire_niO0lO_dataout;
	wire	wire_niO0Oi_dataout;
	wire	wire_niO10i_dataout;
	wire	wire_niO10l_dataout;
	wire	wire_niO10O_dataout;
	wire	wire_niO11i_dataout;
	wire	wire_niO11l_dataout;
	wire	wire_niO11O_dataout;
	wire	wire_niO1ii_dataout;
	wire	wire_niO1il_dataout;
	wire	wire_niO1iO_dataout;
	wire	wire_niO1li_dataout;
	wire	wire_niO1ll_dataout;
	wire	wire_niO1lO_dataout;
	wire	wire_niO1Oi_dataout;
	wire	wire_niO1Ol_dataout;
	wire	wire_niO1OO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOi0i_dataout;
	wire	wire_niOi0l_dataout;
	wire	wire_niOi0O_dataout;
	wire	wire_niOi1l_dataout;
	wire	wire_niOi1O_dataout;
	wire	wire_niOiii_dataout;
	wire	wire_niOiil_dataout;
	wire	wire_niOiiO_dataout;
	wire	wire_niOili_dataout;
	wire	wire_niOill_dataout;
	wire	wire_niOilO_dataout;
	wire	wire_niOiOi_dataout;
	wire	wire_niOiOl_dataout;
	wire	wire_niOiOO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOl1i_dataout;
	wire	wire_niOl1l_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl000l_dataout;
	wire	wire_nl000O_dataout;
	wire	wire_nl001i_dataout;
	wire	wire_nl001l_dataout;
	wire	wire_nl001O_dataout;
	wire	wire_nl00ii_dataout;
	wire	wire_nl00il_dataout;
	wire	wire_nl00iO_dataout;
	wire	wire_nl00li_dataout;
	wire	wire_nl00ll_dataout;
	wire	wire_nl00lO_dataout;
	wire	wire_nl00Oi_dataout;
	wire	wire_nl00Ol_dataout;
	wire	wire_nl00OO_dataout;
	wire	wire_nl01il_dataout;
	wire	wire_nl01iO_dataout;
	wire	wire_nl01li_dataout;
	wire	wire_nl01ll_dataout;
	wire	wire_nl01lO_dataout;
	wire	wire_nl01Oi_dataout;
	wire	wire_nl01Ol_dataout;
	wire	wire_nl01OO_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0i0i_dataout;
	wire	wire_nl0i0l_dataout;
	wire	wire_nl0i0O_dataout;
	wire	wire_nl0i1i_dataout;
	wire	wire_nl0i1l_dataout;
	wire	wire_nl0i1O_dataout;
	wire	wire_nl0iii_dataout;
	wire	wire_nl0iil_dataout;
	wire	wire_nl0iiO_dataout;
	wire	wire_nl0ili_dataout;
	wire	wire_nl0ill_dataout;
	wire	wire_nl0ilO_dataout;
	wire	wire_nl0iOl_dataout;
	wire	wire_nl0iOO_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0l0i_dataout;
	wire	wire_nl0l0l_dataout;
	wire	wire_nl0l0O_dataout;
	wire	wire_nl0l1i_dataout;
	wire	wire_nl0l1l_dataout;
	wire	wire_nl0l1O_dataout;
	wire	wire_nl0lii_dataout;
	wire	wire_nl0lil_dataout;
	wire	wire_nl0liO_dataout;
	wire	wire_nl0lli_dataout;
	wire	wire_nl0lll_dataout;
	wire	wire_nl0llO_dataout;
	wire	wire_nl0lOi_dataout;
	wire	wire_nl0lOl_dataout;
	wire	wire_nl0lOO_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl0O0i_dataout;
	wire	wire_nl0O0l_dataout;
	wire	wire_nl0O0O_dataout;
	wire	wire_nl0O1i_dataout;
	wire	wire_nl0O1l_dataout;
	wire	wire_nl0O1O_dataout;
	wire	wire_nl0Oii_dataout;
	wire	wire_nl0Oil_dataout;
	wire	wire_nl0OiO_dataout;
	wire	wire_nl0Oli_dataout;
	wire	wire_nl0Oll_dataout;
	wire	wire_nl0OlO_dataout;
	wire	wire_nl0OOi_dataout;
	wire	wire_nl0OOl_dataout;
	wire	wire_nl0OOO_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nl1Oil_dataout;
	wire	wire_nl1OiO_dataout;
	wire	wire_nl1Oll_dataout;
	wire	wire_nl1OlO_dataout;
	wire	wire_nl1OOi_dataout;
	wire	wire_nl1OOl_dataout;
	wire	wire_nl1OOO_dataout;
	wire	wire_nli_dataout;
	wire	wire_nli00i_dataout;
	wire	wire_nli00l_dataout;
	wire	wire_nli00O_dataout;
	wire	wire_nli01i_dataout;
	wire	wire_nli01l_dataout;
	wire	wire_nli01O_dataout;
	wire	wire_nli0ii_dataout;
	wire	wire_nli0il_dataout;
	wire	wire_nli0iO_dataout;
	wire	wire_nli0li_dataout;
	wire	wire_nli0ll_dataout;
	wire	wire_nli0lO_dataout;
	wire	wire_nli0Oi_dataout;
	wire	wire_nli0Ol_dataout;
	wire	wire_nli0OO_dataout;
	wire	wire_nli10i_dataout;
	wire	wire_nli10l_dataout;
	wire	wire_nli10O_dataout;
	wire	wire_nli11i_dataout;
	wire	wire_nli11l_dataout;
	wire	wire_nli11O_dataout;
	wire	wire_nli1ii_dataout;
	wire	wire_nli1il_dataout;
	wire	wire_nli1iO_dataout;
	wire	wire_nli1li_dataout;
	wire	wire_nli1ll_dataout;
	wire	wire_nli1lO_dataout;
	wire	wire_nli1Oi_dataout;
	wire	wire_nli1Ol_dataout;
	wire	wire_nli1OO_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlii0i_dataout;
	wire	wire_nlii0l_dataout;
	wire	wire_nlii0O_dataout;
	wire	wire_nlii1i_dataout;
	wire	wire_nlii1l_dataout;
	wire	wire_nlii1O_dataout;
	wire	wire_nliiii_dataout;
	wire	wire_nliiil_dataout;
	wire	wire_nliiiO_dataout;
	wire	wire_nliill_dataout;
	wire	wire_nliilO_dataout;
	wire	wire_nliiOi_dataout;
	wire	wire_nliiOl_dataout;
	wire	wire_nliiOO_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nlil0i_dataout;
	wire	wire_nlil0l_dataout;
	wire	wire_nlil0O_dataout;
	wire	wire_nlil1i_dataout;
	wire	wire_nlil1l_dataout;
	wire	wire_nlil1O_dataout;
	wire	wire_nlilii_dataout;
	wire	wire_nlilil_dataout;
	wire	wire_nliliO_dataout;
	wire	wire_nlilli_dataout;
	wire	wire_nlilll_dataout;
	wire	wire_nlillO_dataout;
	wire	wire_nlilOi_dataout;
	wire	wire_nlilOl_dataout;
	wire	wire_nlilOO_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nliO0i_dataout;
	wire	wire_nliO0l_dataout;
	wire	wire_nliO0O_dataout;
	wire	wire_nliO1i_dataout;
	wire	wire_nliO1l_dataout;
	wire	wire_nliO1O_dataout;
	wire	wire_nliOii_dataout;
	wire	wire_nliOil_dataout;
	wire	wire_nliOiO_dataout;
	wire	wire_nliOli_dataout;
	wire	wire_nliOll_dataout;
	wire	wire_nliOlO_dataout;
	wire	wire_nliOOi_dataout;
	wire	wire_nliOOl_dataout;
	wire	wire_nliOOO_dataout;
	wire	wire_nll10i_dataout;
	wire	wire_nll10l_dataout;
	wire	wire_nll10O_dataout;
	wire	wire_nll11i_dataout;
	wire	wire_nll11O_dataout;
	wire	wire_nll1ii_dataout;
	wire	wire_nll1il_dataout;
	wire	wire_nll1iO_dataout;
	wire	wire_nll1li_dataout;
	wire	wire_nll1ll_dataout;
	wire	wire_nll1lO_dataout;
	wire	wire_nll1Oi_dataout;
	wire	wire_nll1Ol_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nlll0l_dataout;
	wire	wire_nlll0O_dataout;
	wire	wire_nlllii_dataout;
	wire	wire_nlllil_dataout;
	wire	wire_nllliO_dataout;
	wire	wire_nlllli_dataout;
	wire	wire_nlllll_dataout;
	wire	wire_nllllO_dataout;
	wire	wire_nlllOi_dataout;
	wire	wire_nlllOl_dataout;
	wire	wire_nlllOO_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nllO0l_dataout;
	wire	wire_nllO0O_dataout;
	wire	wire_nllO1i_dataout;
	wire	wire_nllO1l_dataout;
	wire	wire_nllO1O_dataout;
	wire	wire_nllOii_dataout;
	wire	wire_nllOiO_dataout;
	wire	wire_nllOli_dataout;
	wire	wire_nllOll_dataout;
	wire	wire_nllOlO_dataout;
	wire	wire_nllOOi_dataout;
	wire	wire_nllOOl_dataout;
	wire	wire_nllOOO_dataout;
	wire	wire_nlO00i_dataout;
	wire	wire_nlO00l_dataout;
	wire	wire_nlO01i_dataout;
	wire	wire_nlO01l_dataout;
	wire	wire_nlO01O_dataout;
	wire	wire_nlO10i_dataout;
	wire	wire_nlO10l_dataout;
	wire	wire_nlO10O_dataout;
	wire	wire_nlO11i_dataout;
	wire	wire_nlO11O_dataout;
	wire	wire_nlO1ii_dataout;
	wire	wire_nlO1il_dataout;
	wire	wire_nlO1iO_dataout;
	wire	wire_nlO1li_dataout;
	wire	wire_nlO1ll_dataout;
	wire	wire_nlO1lO_dataout;
	wire	wire_nlO1Oi_dataout;
	wire	wire_nlO1Ol_dataout;
	wire	wire_nlO1OO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nO_dataout;
	wire  [4:0]   wire_niiOl_o;
	wire  [6:0]   wire_niO0Ol_o;
	wire  [6:0]   wire_niO0OO_o;
	wire  [7:0]   wire_niOi1i_o;
	wire  [5:0]   wire_nllO0i_o;
	wire  [2:0]   wire_nllOil_o;
	wire  [8:0]   wire_nlO00O_o;
	wire  [3:0]   wire_nlO11l_o;
	wire  [31:0]   wire_n11ll_o;
	wire  [15:0]   wire_ni1ill_o;
	wire  [15:0]   wire_nii0Ol_o;
	wire  [15:0]   wire_nl1Oli_o;
	wire  wire_n100i_o;
	wire  wire_n100l_o;
	wire  wire_n101i_o;
	wire  wire_n101l_o;
	wire  wire_n101O_o;
	wire  wire_n11Ol_o;
	wire  wire_n11OO_o;
	wire  wire_ni1ilO_o;
	wire  wire_ni1iOi_o;
	wire  wire_ni1iOl_o;
	wire  wire_ni1iOO_o;
	wire  wire_ni1l0i_o;
	wire  wire_ni1l1i_o;
	wire  wire_ni1l1l_o;
	wire  wire_ni1l1O_o;
	wire  wire_nii0iO_o;
	wire  wire_nii0li_o;
	wire  wire_nii0lO_o;
	wire  wire_nii0OO_o;
	wire  wire_niii0i_o;
	wire  wire_niii0l_o;
	wire  wire_niii0O_o;
	wire  wire_niii1i_o;
	wire  wire_niii1l_o;
	wire  wire_niii1O_o;
	wire  wire_niiiii_o;
	wire  wire_niiiil_o;
	wire  wire_niiiiO_o;
	wire  wire_niiili_o;
	wire  wire_niiill_o;
	wire  wire_nl010i_o;
	wire  wire_nl010l_o;
	wire  wire_nl010O_o;
	wire  wire_nl011i_o;
	wire  wire_nl011l_o;
	wire  wire_nl011O_o;
	wire  wire_nl01ii_o;
	wire  wire_n11il_o;
	wire  wire_n11iO_o;
	wire  wire_n11lO_o;
	wire  wire_ni1iiO_o;
	wire  n0iOli;
	wire  n0iOll;
	wire  n0iOlO;
	wire  n0iOOi;
	wire  n0iOOl;
	wire  n0iOOO;
	wire  n0l00i;
	wire  n0l00l;
	wire  n0l00O;
	wire  n0l01i;
	wire  n0l01l;
	wire  n0l01O;
	wire  n0l0ii;
	wire  n0l0il;
	wire  n0l0iO;
	wire  n0l0li;
	wire  n0l0ll;
	wire  n0l0lO;
	wire  n0l0Oi;
	wire  n0l0Ol;
	wire  n0l0OO;
	wire  n0l10i;
	wire  n0l10l;
	wire  n0l10O;
	wire  n0l11i;
	wire  n0l11l;
	wire  n0l11O;
	wire  n0l1ii;
	wire  n0l1il;
	wire  n0l1iO;
	wire  n0l1li;
	wire  n0l1ll;
	wire  n0l1lO;
	wire  n0l1Oi;
	wire  n0l1Ol;
	wire  n0l1OO;
	wire  n0li0i;
	wire  n0li0l;
	wire  n0li0O;
	wire  n0li1i;
	wire  n0li1l;
	wire  n0li1O;
	wire  n0liii;
	wire  n0liil;
	wire  n0lill;
	wire  n0lilO;
	wire  n0liOi;
	wire  n0liOl;
	wire  n0liOO;
	wire  n0ll0i;
	wire  n0ll0l;
	wire  n0ll0O;
	wire  n0ll1i;
	wire  n0ll1l;
	wire  n0ll1O;
	wire  n0llii;
	wire  n0llil;
	wire  n0lliO;
	wire  n0llli;
	wire  n0llll;
	wire  n0lllO;
	wire  n0llOi;
	wire  n0llOl;
	wire  n0llOO;
	wire  n0lO0i;
	wire  n0lO0l;
	wire  n0lO0O;
	wire  n0lO1i;
	wire  n0lO1l;
	wire  n0lO1O;
	wire  n0lOii;
	wire  n0lOil;
	wire  n0lOiO;
	wire  n0lOli;
	wire  n0lOll;
	wire  n0lOlO;
	wire  n0lOOi;
	wire  n0lOOl;
	wire  n0lOOO;
	wire  n0O00i;
	wire  n0O00l;
	wire  n0O01i;
	wire  n0O01l;
	wire  n0O01O;
	wire  n0O0il;
	wire  n0O0iO;
	wire  n0O0li;
	wire  n0O0ll;
	wire  n0O0lO;
	wire  n0O0Oi;
	wire  n0O0Ol;
	wire  n0O0OO;
	wire  n0O10i;
	wire  n0O11i;
	wire  n0O11l;
	wire  n0O11O;
	wire  n0O1OO;
	wire  n0Oi0i;
	wire  n0Oi0l;
	wire  n0Oi0O;
	wire  n0Oi1i;
	wire  n0Oi1l;
	wire  n0Oi1O;
	wire  n0Oiii;
	wire  n0Oiil;
	wire  n0OiiO;
	wire  n0OilO;
	wire  n0OiOO;
	wire  n0Ol0i;
	wire  n0Ol0O;
	wire  n0Ol1i;
	wire  n0Ol1l;
	wire  n0Ol1O;
	wire  n0OO0i;
	wire  n0OO0l;
	wire  n0OO0O;
	wire  n0OO1l;
	wire  n0OO1O;

	initial
		n0liiO49 = 0;
	always @ ( posedge clk_2)
		  n0liiO49 <= n0liiO50;
	event n0liiO49_event;
	initial
		#1 ->n0liiO49_event;
	always @(n0liiO49_event)
		n0liiO49 <= {1{1'b1}};
	initial
		n0liiO50 = 0;
	always @ ( posedge clk_2)
		  n0liiO50 <= n0liiO49;
	initial
		n0lili47 = 0;
	always @ ( posedge clk_2)
		  n0lili47 <= n0lili48;
	event n0lili47_event;
	initial
		#1 ->n0lili47_event;
	always @(n0lili47_event)
		n0lili47 <= {1{1'b1}};
	initial
		n0lili48 = 0;
	always @ ( posedge clk_2)
		  n0lili48 <= n0lili47;
	initial
		n0O00O25 = 0;
	always @ ( posedge clk_2)
		  n0O00O25 <= n0O00O26;
	event n0O00O25_event;
	initial
		#1 ->n0O00O25_event;
	always @(n0O00O25_event)
		n0O00O25 <= {1{1'b1}};
	initial
		n0O00O26 = 0;
	always @ ( posedge clk_2)
		  n0O00O26 <= n0O00O25;
	initial
		n0O10l45 = 0;
	always @ ( posedge clk_2)
		  n0O10l45 <= n0O10l46;
	event n0O10l45_event;
	initial
		#1 ->n0O10l45_event;
	always @(n0O10l45_event)
		n0O10l45 <= {1{1'b1}};
	initial
		n0O10l46 = 0;
	always @ ( posedge clk_2)
		  n0O10l46 <= n0O10l45;
	initial
		n0O10O43 = 0;
	always @ ( posedge clk_2)
		  n0O10O43 <= n0O10O44;
	event n0O10O43_event;
	initial
		#1 ->n0O10O43_event;
	always @(n0O10O43_event)
		n0O10O43 <= {1{1'b1}};
	initial
		n0O10O44 = 0;
	always @ ( posedge clk_2)
		  n0O10O44 <= n0O10O43;
	initial
		n0O1ii41 = 0;
	always @ ( posedge clk_2)
		  n0O1ii41 <= n0O1ii42;
	event n0O1ii41_event;
	initial
		#1 ->n0O1ii41_event;
	always @(n0O1ii41_event)
		n0O1ii41 <= {1{1'b1}};
	initial
		n0O1ii42 = 0;
	always @ ( posedge clk_2)
		  n0O1ii42 <= n0O1ii41;
	initial
		n0O1il39 = 0;
	always @ ( posedge clk_2)
		  n0O1il39 <= n0O1il40;
	event n0O1il39_event;
	initial
		#1 ->n0O1il39_event;
	always @(n0O1il39_event)
		n0O1il39 <= {1{1'b1}};
	initial
		n0O1il40 = 0;
	always @ ( posedge clk_2)
		  n0O1il40 <= n0O1il39;
	initial
		n0O1iO37 = 0;
	always @ ( posedge clk_2)
		  n0O1iO37 <= n0O1iO38;
	event n0O1iO37_event;
	initial
		#1 ->n0O1iO37_event;
	always @(n0O1iO37_event)
		n0O1iO37 <= {1{1'b1}};
	initial
		n0O1iO38 = 0;
	always @ ( posedge clk_2)
		  n0O1iO38 <= n0O1iO37;
	initial
		n0O1li35 = 0;
	always @ ( posedge clk_2)
		  n0O1li35 <= n0O1li36;
	event n0O1li35_event;
	initial
		#1 ->n0O1li35_event;
	always @(n0O1li35_event)
		n0O1li35 <= {1{1'b1}};
	initial
		n0O1li36 = 0;
	always @ ( posedge clk_2)
		  n0O1li36 <= n0O1li35;
	initial
		n0O1ll33 = 0;
	always @ ( posedge clk_2)
		  n0O1ll33 <= n0O1ll34;
	event n0O1ll33_event;
	initial
		#1 ->n0O1ll33_event;
	always @(n0O1ll33_event)
		n0O1ll33 <= {1{1'b1}};
	initial
		n0O1ll34 = 0;
	always @ ( posedge clk_2)
		  n0O1ll34 <= n0O1ll33;
	initial
		n0O1lO31 = 0;
	always @ ( posedge clk_2)
		  n0O1lO31 <= n0O1lO32;
	event n0O1lO31_event;
	initial
		#1 ->n0O1lO31_event;
	always @(n0O1lO31_event)
		n0O1lO31 <= {1{1'b1}};
	initial
		n0O1lO32 = 0;
	always @ ( posedge clk_2)
		  n0O1lO32 <= n0O1lO31;
	initial
		n0O1Oi29 = 0;
	always @ ( posedge clk_2)
		  n0O1Oi29 <= n0O1Oi30;
	event n0O1Oi29_event;
	initial
		#1 ->n0O1Oi29_event;
	always @(n0O1Oi29_event)
		n0O1Oi29 <= {1{1'b1}};
	initial
		n0O1Oi30 = 0;
	always @ ( posedge clk_2)
		  n0O1Oi30 <= n0O1Oi29;
	initial
		n0O1Ol27 = 0;
	always @ ( posedge clk_2)
		  n0O1Ol27 <= n0O1Ol28;
	event n0O1Ol27_event;
	initial
		#1 ->n0O1Ol27_event;
	always @(n0O1Ol27_event)
		n0O1Ol27 <= {1{1'b1}};
	initial
		n0O1Ol28 = 0;
	always @ ( posedge clk_2)
		  n0O1Ol28 <= n0O1Ol27;
	initial
		n0Oili23 = 0;
	always @ ( posedge clk_2)
		  n0Oili23 <= n0Oili24;
	event n0Oili23_event;
	initial
		#1 ->n0Oili23_event;
	always @(n0Oili23_event)
		n0Oili23 <= {1{1'b1}};
	initial
		n0Oili24 = 0;
	always @ ( posedge clk_2)
		  n0Oili24 <= n0Oili23;
	initial
		n0OiOi21 = 0;
	always @ ( posedge clk_2)
		  n0OiOi21 <= n0OiOi22;
	event n0OiOi21_event;
	initial
		#1 ->n0OiOi21_event;
	always @(n0OiOi21_event)
		n0OiOi21 <= {1{1'b1}};
	initial
		n0OiOi22 = 0;
	always @ ( posedge clk_2)
		  n0OiOi22 <= n0OiOi21;
	initial
		n0Ol0l19 = 0;
	always @ ( posedge clk_2)
		  n0Ol0l19 <= n0Ol0l20;
	event n0Ol0l19_event;
	initial
		#1 ->n0Ol0l19_event;
	always @(n0Ol0l19_event)
		n0Ol0l19 <= {1{1'b1}};
	initial
		n0Ol0l20 = 0;
	always @ ( posedge clk_2)
		  n0Ol0l20 <= n0Ol0l19;
	initial
		n0Olii17 = 0;
	always @ ( posedge clk_2)
		  n0Olii17 <= n0Olii18;
	event n0Olii17_event;
	initial
		#1 ->n0Olii17_event;
	always @(n0Olii17_event)
		n0Olii17 <= {1{1'b1}};
	initial
		n0Olii18 = 0;
	always @ ( posedge clk_2)
		  n0Olii18 <= n0Olii17;
	initial
		n0Olil15 = 0;
	always @ ( posedge clk_2)
		  n0Olil15 <= n0Olil16;
	event n0Olil15_event;
	initial
		#1 ->n0Olil15_event;
	always @(n0Olil15_event)
		n0Olil15 <= {1{1'b1}};
	initial
		n0Olil16 = 0;
	always @ ( posedge clk_2)
		  n0Olil16 <= n0Olil15;
	initial
		n0OliO13 = 0;
	always @ ( posedge clk_2)
		  n0OliO13 <= n0OliO14;
	event n0OliO13_event;
	initial
		#1 ->n0OliO13_event;
	always @(n0OliO13_event)
		n0OliO13 <= {1{1'b1}};
	initial
		n0OliO14 = 0;
	always @ ( posedge clk_2)
		  n0OliO14 <= n0OliO13;
	initial
		n0Olll11 = 0;
	always @ ( posedge clk_2)
		  n0Olll11 <= n0Olll12;
	event n0Olll11_event;
	initial
		#1 ->n0Olll11_event;
	always @(n0Olll11_event)
		n0Olll11 <= {1{1'b1}};
	initial
		n0Olll12 = 0;
	always @ ( posedge clk_2)
		  n0Olll12 <= n0Olll11;
	initial
		n0OlOi10 = 0;
	always @ ( posedge clk_2)
		  n0OlOi10 <= n0OlOi9;
	initial
		n0OlOi9 = 0;
	always @ ( posedge clk_2)
		  n0OlOi9 <= n0OlOi10;
	event n0OlOi9_event;
	initial
		#1 ->n0OlOi9_event;
	always @(n0OlOi9_event)
		n0OlOi9 <= {1{1'b1}};
	initial
		n0OlOO7 = 0;
	always @ ( posedge clk_2)
		  n0OlOO7 <= n0OlOO8;
	event n0OlOO7_event;
	initial
		#1 ->n0OlOO7_event;
	always @(n0OlOO7_event)
		n0OlOO7 <= {1{1'b1}};
	initial
		n0OlOO8 = 0;
	always @ ( posedge clk_2)
		  n0OlOO8 <= n0OlOO7;
	initial
		n0OOii5 = 0;
	always @ ( posedge clk_2)
		  n0OOii5 <= n0OOii6;
	event n0OOii5_event;
	initial
		#1 ->n0OOii5_event;
	always @(n0OOii5_event)
		n0OOii5 <= {1{1'b1}};
	initial
		n0OOii6 = 0;
	always @ ( posedge clk_2)
		  n0OOii6 <= n0OOii5;
	initial
		n0OOiO3 = 0;
	always @ ( posedge clk_2)
		  n0OOiO3 <= n0OOiO4;
	event n0OOiO3_event;
	initial
		#1 ->n0OOiO3_event;
	always @(n0OOiO3_event)
		n0OOiO3 <= {1{1'b1}};
	initial
		n0OOiO4 = 0;
	always @ ( posedge clk_2)
		  n0OOiO4 <= n0OOiO3;
	initial
		n0OOll1 = 0;
	always @ ( posedge clk_2)
		  n0OOll1 <= n0OOll2;
	event n0OOll1_event;
	initial
		#1 ->n0OOll1_event;
	always @(n0OOll1_event)
		n0OOll1 <= {1{1'b1}};
	initial
		n0OOll2 = 0;
	always @ ( posedge clk_2)
		  n0OOll2 <= n0OOll1;
	initial
	begin
		ni00i = 0;
		ni01l = 0;
		ni1O1O = 0;
		niiilO = 0;
		niiiOi = 0;
		niiiOl = 0;
		niiiOO = 0;
		niil0i = 0;
		niil0l = 0;
		niil0O = 0;
		niil1i = 0;
		niil1l = 0;
		niil1O = 0;
		niilii = 0;
		niilil = 0;
		niiliO = 0;
		niilli = 0;
		niilll = 0;
		niillO = 0;
		niilOi = 0;
		niilOl = 0;
		niiO0i = 0;
		niiO1O = 0;
		nll00O = 0;
		nll0ii = 0;
	end
	always @ ( posedge clk_2 or  negedge wire_ni01O_CLRN)
	begin
		if (wire_ni01O_CLRN == 1'b0) 
		begin
			ni00i <= 0;
			ni01l <= 0;
			ni1O1O <= 0;
			niiilO <= 0;
			niiiOi <= 0;
			niiiOl <= 0;
			niiiOO <= 0;
			niil0i <= 0;
			niil0l <= 0;
			niil0O <= 0;
			niil1i <= 0;
			niil1l <= 0;
			niil1O <= 0;
			niilii <= 0;
			niilil <= 0;
			niiliO <= 0;
			niilli <= 0;
			niilll <= 0;
			niillO <= 0;
			niilOi <= 0;
			niilOl <= 0;
			niiO0i <= 0;
			niiO1O <= 0;
			nll00O <= 0;
			nll0ii <= 0;
		end
		else 
		begin
			ni00i <= wire_nii1O_dataout;
			ni01l <= wire_nii1l_dataout;
			ni1O1O <= wire_nil0il_dataout;
			niiilO <= wire_nil0iO_dataout;
			niiiOi <= wire_nil0li_dataout;
			niiiOl <= wire_nil0ll_dataout;
			niiiOO <= wire_nil0lO_dataout;
			niil0i <= wire_nili1i_dataout;
			niil0l <= wire_nili1l_dataout;
			niil0O <= wire_nili1O_dataout;
			niil1i <= wire_nil0Oi_dataout;
			niil1l <= wire_nil0Ol_dataout;
			niil1O <= wire_nil0OO_dataout;
			niilii <= wire_nili0i_dataout;
			niilil <= wire_nili0l_dataout;
			niiliO <= wire_nili0O_dataout;
			niilli <= wire_niliii_dataout;
			niilll <= wire_niliil_dataout;
			niillO <= wire_niliiO_dataout;
			niilOi <= wire_nilili_dataout;
			niilOl <= wire_nilill_dataout;
			niiO0i <= wire_niliOi_dataout;
			niiO1O <= wire_nililO_dataout;
			nll00O <= wire_nlll0l_dataout;
			nll0ii <= wire_nlll0O_dataout;
		end
	end
	assign
		wire_ni01O_CLRN = ((n0Ol0l20 ^ n0Ol0l19) & (~ soft_reset));
	initial
	begin
		n11ii = 0;
		ni00l = 0;
		ni00O = 0;
		ni01i = 0;
		ni0ii = 0;
		ni0il = 0;
		ni0iO = 0;
		ni0li = 0;
		ni0ll = 0;
		ni0lO = 0;
		ni0Oi = 0;
		ni0Ol = 0;
		nii1i = 0;
		niilOO = 0;
		niiO1i = 0;
		niiO1l = 0;
		niiOii = 0;
		niiOil = 0;
		niiOiO = 0;
		niiOli = 0;
		niiOll = 0;
		niiOlO = 0;
		niiOOi = 0;
		niiOOl = 0;
		niiOOO = 0;
		nil00i = 0;
		nil00l = 0;
		nil00O = 0;
		nil01i = 0;
		nil01l = 0;
		nil01O = 0;
		nil0ii = 0;
		nil10i = 0;
		nil10l = 0;
		nil10O = 0;
		nil11i = 0;
		nil11l = 0;
		nil11O = 0;
		nil1ii = 0;
		nil1il = 0;
		nil1iO = 0;
		nil1li = 0;
		nil1ll = 0;
		nil1lO = 0;
		nil1Oi = 0;
		nil1Ol = 0;
		nil1OO = 0;
		nl1Oii = 0;
		nll00l = 0;
		nll0il = 0;
		nll0iO = 0;
		nll0li = 0;
		nll0ll = 0;
		nll0lO = 0;
		nll0Oi = 0;
		nll0Ol = 0;
		nll0OO = 0;
		nlli0i = 0;
		nlli0l = 0;
		nlli0O = 0;
		nlli1i = 0;
		nlli1l = 0;
		nlli1O = 0;
		nlliii = 0;
		nlliil = 0;
		nlliiO = 0;
		nllili = 0;
		nllill = 0;
		nllilO = 0;
		nlliOi = 0;
		nlliOl = 0;
		nlliOO = 0;
		nlll0i = 0;
		nlll1i = 0;
		nlll1l = 0;
		nlll1O = 0;
	end
	always @ (clk_2 or wire_ni0OO_PRN or wire_ni0OO_CLRN)
	begin
		if (wire_ni0OO_PRN == 1'b0) 
		begin
			n11ii <= 1;
			ni00l <= 1;
			ni00O <= 1;
			ni01i <= 1;
			ni0ii <= 1;
			ni0il <= 1;
			ni0iO <= 1;
			ni0li <= 1;
			ni0ll <= 1;
			ni0lO <= 1;
			ni0Oi <= 1;
			ni0Ol <= 1;
			nii1i <= 1;
			niilOO <= 1;
			niiO1i <= 1;
			niiO1l <= 1;
			niiOii <= 1;
			niiOil <= 1;
			niiOiO <= 1;
			niiOli <= 1;
			niiOll <= 1;
			niiOlO <= 1;
			niiOOi <= 1;
			niiOOl <= 1;
			niiOOO <= 1;
			nil00i <= 1;
			nil00l <= 1;
			nil00O <= 1;
			nil01i <= 1;
			nil01l <= 1;
			nil01O <= 1;
			nil0ii <= 1;
			nil10i <= 1;
			nil10l <= 1;
			nil10O <= 1;
			nil11i <= 1;
			nil11l <= 1;
			nil11O <= 1;
			nil1ii <= 1;
			nil1il <= 1;
			nil1iO <= 1;
			nil1li <= 1;
			nil1ll <= 1;
			nil1lO <= 1;
			nil1Oi <= 1;
			nil1Ol <= 1;
			nil1OO <= 1;
			nl1Oii <= 1;
			nll00l <= 1;
			nll0il <= 1;
			nll0iO <= 1;
			nll0li <= 1;
			nll0ll <= 1;
			nll0lO <= 1;
			nll0Oi <= 1;
			nll0Ol <= 1;
			nll0OO <= 1;
			nlli0i <= 1;
			nlli0l <= 1;
			nlli0O <= 1;
			nlli1i <= 1;
			nlli1l <= 1;
			nlli1O <= 1;
			nlliii <= 1;
			nlliil <= 1;
			nlliiO <= 1;
			nllili <= 1;
			nllill <= 1;
			nllilO <= 1;
			nlliOi <= 1;
			nlliOl <= 1;
			nlliOO <= 1;
			nlll0i <= 1;
			nlll1i <= 1;
			nlll1l <= 1;
			nlll1O <= 1;
		end
		else if  (wire_ni0OO_CLRN == 1'b0) 
		begin
			n11ii <= 0;
			ni00l <= 0;
			ni00O <= 0;
			ni01i <= 0;
			ni0ii <= 0;
			ni0il <= 0;
			ni0iO <= 0;
			ni0li <= 0;
			ni0ll <= 0;
			ni0lO <= 0;
			ni0Oi <= 0;
			ni0Ol <= 0;
			nii1i <= 0;
			niilOO <= 0;
			niiO1i <= 0;
			niiO1l <= 0;
			niiOii <= 0;
			niiOil <= 0;
			niiOiO <= 0;
			niiOli <= 0;
			niiOll <= 0;
			niiOlO <= 0;
			niiOOi <= 0;
			niiOOl <= 0;
			niiOOO <= 0;
			nil00i <= 0;
			nil00l <= 0;
			nil00O <= 0;
			nil01i <= 0;
			nil01l <= 0;
			nil01O <= 0;
			nil0ii <= 0;
			nil10i <= 0;
			nil10l <= 0;
			nil10O <= 0;
			nil11i <= 0;
			nil11l <= 0;
			nil11O <= 0;
			nil1ii <= 0;
			nil1il <= 0;
			nil1iO <= 0;
			nil1li <= 0;
			nil1ll <= 0;
			nil1lO <= 0;
			nil1Oi <= 0;
			nil1Ol <= 0;
			nil1OO <= 0;
			nl1Oii <= 0;
			nll00l <= 0;
			nll0il <= 0;
			nll0iO <= 0;
			nll0li <= 0;
			nll0ll <= 0;
			nll0lO <= 0;
			nll0Oi <= 0;
			nll0Ol <= 0;
			nll0OO <= 0;
			nlli0i <= 0;
			nlli0l <= 0;
			nlli0O <= 0;
			nlli1i <= 0;
			nlli1l <= 0;
			nlli1O <= 0;
			nlliii <= 0;
			nlliil <= 0;
			nlliiO <= 0;
			nllili <= 0;
			nllill <= 0;
			nllilO <= 0;
			nlliOi <= 0;
			nlliOl <= 0;
			nlliOO <= 0;
			nlll0i <= 0;
			nlll1i <= 0;
			nlll1l <= 0;
			nlll1O <= 0;
		end
		else if  (rbist_clr_rx == 1'b0) 
		if (clk_2 != ni0OO_clk_prev && clk_2 == 1'b1) 
		begin
			n11ii <= ni01i;
			ni00l <= wire_n11lO_o;
			ni00O <= wire_nii0i_dataout;
			ni01i <= sync_status;
			ni0ii <= wire_nii0l_dataout;
			ni0il <= wire_nii0O_dataout;
			ni0iO <= wire_niiii_dataout;
			ni0li <= wire_niiil_dataout;
			ni0ll <= wire_n101i_o;
			ni0lO <= wire_n101l_o;
			ni0Oi <= wire_n101O_o;
			ni0Ol <= wire_n100i_o;
			nii1i <= wire_n100l_o;
			niilOO <= niiO1i;
			niiO1i <= sync_status;
			niiO1l <= wire_ni1iOi_o;
			niiOii <= wire_niO1Ol_dataout;
			niiOil <= wire_niO1OO_dataout;
			niiOiO <= wire_niO01i_dataout;
			niiOli <= wire_niO01l_dataout;
			niiOll <= wire_niO01O_dataout;
			niiOlO <= wire_niO00i_dataout;
			niiOOi <= wire_niO00l_dataout;
			niiOOl <= wire_niO10l_dataout;
			niiOOO <= wire_niO10O_dataout;
			nil00i <= wire_ni1l1i_o;
			nil00l <= wire_ni1l1l_o;
			nil00O <= wire_ni1l1O_o;
			nil01i <= nil00l;
			nil01l <= nil00O;
			nil01O <= nil0ii;
			nil0ii <= wire_ni1l0i_o;
			nil10i <= wire_niO1li_dataout;
			nil10l <= wire_niO1ll_dataout;
			nil10O <= wire_niO1lO_dataout;
			nil11i <= wire_niO1ii_dataout;
			nil11l <= wire_niO1il_dataout;
			nil11O <= wire_niO1iO_dataout;
			nil1ii <= wire_niO00O_dataout;
			nil1il <= wire_niO0ii_dataout;
			nil1iO <= wire_niO0il_dataout;
			nil1li <= wire_niO0iO_dataout;
			nil1ll <= wire_niO0li_dataout;
			nil1lO <= wire_niO0ll_dataout;
			nil1Oi <= wire_niO0lO_dataout;
			nil1Ol <= wire_niO0Oi_dataout;
			nil1OO <= nil00i;
			nl1Oii <= nll00l;
			nll00l <= sync_status;
			nll0il <= wire_nl011i_o;
			nll0iO <= wire_nlllii_dataout;
			nll0li <= wire_nlllil_dataout;
			nll0ll <= wire_nllliO_dataout;
			nll0lO <= wire_nlllli_dataout;
			nll0Oi <= wire_nlllll_dataout;
			nll0Ol <= wire_nllllO_dataout;
			nll0OO <= wire_nllO0l_dataout;
			nlli0i <= wire_nllOli_dataout;
			nlli0l <= wire_nllOll_dataout;
			nlli0O <= wire_nllOlO_dataout;
			nlli1i <= wire_nllO0O_dataout;
			nlli1l <= wire_nllOii_dataout;
			nlli1O <= wire_nllOiO_dataout;
			nlliii <= wire_nlO11O_dataout;
			nlliil <= wire_nlO10i_dataout;
			nlliiO <= wire_nlO10l_dataout;
			nllili <= wire_nlO10O_dataout;
			nllill <= wire_nlO1ii_dataout;
			nllilO <= wire_nlO1il_dataout;
			nlliOi <= wire_nlO1iO_dataout;
			nlliOl <= wire_nlO1li_dataout;
			nlliOO <= wire_nlO1ll_dataout;
			nlll0i <= wire_nl01ii_o;
			nlll1i <= wire_nl010i_o;
			nlll1l <= wire_nl010l_o;
			nlll1O <= wire_nl010O_o;
		end
		ni0OO_clk_prev <= clk_2;
	end
	assign
		wire_ni0OO_CLRN = ((n0Olil16 ^ n0Olil15) & (~ soft_reset)),
		wire_ni0OO_PRN = (n0Olii18 ^ n0Olii17);
	initial
	begin
		niiO0O = 0;
	end
	always @ (clk_2 or wire_niiO0l_PRN or wire_niiO0l_CLRN)
	begin
		if (wire_niiO0l_PRN == 1'b0) 
		begin
			niiO0O <= 1;
		end
		else if  (wire_niiO0l_CLRN == 1'b0) 
		begin
			niiO0O <= 0;
		end
		else if  (rbist_clr_rx == 1'b0) 
		if (clk_2 != niiO0l_clk_prev && clk_2 == 1'b1) 
		begin
			niiO0O <= wire_niO1Oi_dataout;
		end
		niiO0l_clk_prev <= clk_2;
	end
	assign
		wire_niiO0l_CLRN = (n0lili48 ^ n0lili47),
		wire_niiO0l_PRN = ((n0liiO50 ^ n0liiO49) & (~ soft_reset));
	or(wire_n000i_dataout, ni01l, (~ n0O0li));
	or(wire_n000l_dataout, ni00i, (~ n0O0li));
	or(wire_n000O_dataout, wire_n00lO_dataout, (~ n0O0li));
	or(wire_n001i_dataout, nii1i, n0Oiil);
	and(wire_n001l_dataout, wire_n00ll_dataout, ~((~ n0O0li)));
	and(wire_n001O_dataout, wire_n0i1l_dataout, ~((~ n0O0li)));
	assign		wire_n00i_dataout = (n0OO1O === 1'b1) ? nlll0i : wire_n0iO_dataout;
	and(wire_n00ii_dataout, wire_n00Oi_dataout, ~((~ n0O0li)));
	or(wire_n00il_dataout, wire_n00Ol_dataout, (~ n0O0li));
	and(wire_n00iO_dataout, wire_n00OO_dataout, ~((~ n0O0li)));
	and(wire_n00l_dataout, wire_n0li_dataout, ~(n0OO1O));
	or(wire_n00li_dataout, wire_n0i1i_dataout, (~ n0O0li));
	and(wire_n00ll_dataout, (~ n0O0ll), n0OO0l);
	or(wire_n00lO_dataout, wire_n1Oii_dataout, ~(n0OO0l));
	and(wire_n00O_dataout, ni0ll, n0OO0i);
	or(wire_n00Oi_dataout, wire_n1Oil_dataout, ~(n0OO0l));
	or(wire_n00Ol_dataout, wire_n1OiO_dataout, ~(n0OO0l));
	or(wire_n00OO_dataout, wire_n1Oli_dataout, ~(n0OO0l));
	and(wire_n010i_dataout, wire_n01iO_dataout, ~(n0Ol1i));
	and(wire_n010l_dataout, wire_n01li_dataout, ~(n0Ol1i));
	or(wire_n010O_dataout, wire_n01ll_dataout, n0Ol1i);
	or(wire_n011i_dataout, wire_n010O_dataout, n0Ol1O);
	or(wire_n011l_dataout, wire_n01ii_dataout, n0Ol1i);
	and(wire_n011O_dataout, wire_n01il_dataout, ~(n0Ol1i));
	assign		wire_n01i_dataout = (n0OO1O === 1'b1) ? nlll1i : wire_n00O_dataout;
	and(wire_n01ii_dataout, wire_n01lO_dataout, ~(n0OiOO));
	or(wire_n01il_dataout, wire_n01Oi_dataout, n0OiOO);
	and(wire_n01iO_dataout, wire_n01Ol_dataout, ~(n0OiOO));
	assign		wire_n01l_dataout = (n0OO1O === 1'b1) ? nlll1l : wire_n0ii_dataout;
	and(wire_n01li_dataout, wire_n01OO_dataout, ~(n0OiOO));
	or(wire_n01ll_dataout, wire_n001i_dataout, n0OiOO);
	or(wire_n01lO_dataout, ni0ll, n0Oiil);
	assign		wire_n01O_dataout = (n0OO1O === 1'b1) ? nlll1O : wire_n0il_dataout;
	or(wire_n01Oi_dataout, ni0lO, n0Oiil);
	and(wire_n01Ol_dataout, ni0Oi, ~(n0Oiil));
	and(wire_n01OO_dataout, ni0Ol, ~(n0Oiil));
	assign		wire_n0i_dataout = (n0OO0O === 1'b1) ? rxd[33] : rxd[17];
	or(wire_n0i0i_dataout, ni00i, (~ n0O0lO));
	or(wire_n0i0l_dataout, ni01l, (~ n0O0Oi));
	or(wire_n0i0O_dataout, ni00i, (~ n0O0Oi));
	and(wire_n0i1i_dataout, wire_n1Oll_dataout, n0OO0l);
	and(wire_n0i1l_dataout, n0O0ll, n0OO0l);
	or(wire_n0i1O_dataout, ni01l, (~ n0O0lO));
	and(wire_n0ii_dataout, ni0lO, n0OO0i);
	or(wire_n0iii_dataout, (~ n0OO0l), (~ n0O0Oi));
	and(wire_n0iil_dataout, n0OO0l, ~((~ n0O0Oi)));
	or(wire_n0iiO_dataout, ni01l, (~ n0O0Ol));
	and(wire_n0il_dataout, ni0Oi, n0OO0i);
	or(wire_n0ili_dataout, ni00i, (~ n0O0Ol));
	or(wire_n0ill_dataout, ni01l, (~ n0O0OO));
	or(wire_n0ilO_dataout, ni00i, (~ n0O0OO));
	and(wire_n0iO_dataout, ni0Ol, n0OO0i);
	or(wire_n0iOi_dataout, (~ n0OO0l), (~ n0O0OO));
	and(wire_n0iOl_dataout, (~ n0OO0l), ~((~ n0O0OO)));
	or(wire_n0iOO_dataout, n0OO0l, (~ n0O0OO));
	assign		wire_n0l_dataout = (n0OO0O === 1'b1) ? rxd[34] : rxd[18];
	or(wire_n0l0i_dataout, ni00i, (~ n0Oi1l));
	or(wire_n0l0l_dataout, (~ n0OO0l), (~ n0Oi1l));
	and(wire_n0l0O_dataout, n0OO0l, ~((~ n0Oi1l)));
	or(wire_n0l1i_dataout, ni01l, (~ n0Oi1i));
	or(wire_n0l1l_dataout, ni00i, (~ n0Oi1i));
	or(wire_n0l1O_dataout, ni01l, (~ n0Oi1l));
	and(wire_n0li_dataout, nii1i, n0OO0i);
	or(wire_n0lii_dataout, ni01l, (~ n0Oi1O));
	or(wire_n0lil_dataout, ni00i, (~ n0Oi1O));
	or(wire_n0liO_dataout, ni01l, (~ n0Oi0i));
	or(wire_n0lli_dataout, ni00i, (~ n0Oi0i));
	and(wire_n0lll_dataout, (~ n0OO0l), ~((~ n0Oi0i)));
	or(wire_n0llO_dataout, (~ n0OO0l), (~ n0Oi0i));
	and(wire_n0lOi_dataout, n0OO0l, ~((~ n0Oi0i)));
	or(wire_n0lOl_dataout, ni01l, (~ n0Oi0l));
	or(wire_n0lOO_dataout, ni00i, (~ n0Oi0l));
	assign		wire_n0O_dataout = (n0OO0O === 1'b1) ? rxd[35] : rxd[19];
	and(wire_n0O0i_dataout, n0OO0l, ~((~ n0Oi0O)));
	and(wire_n0O0l_dataout, ni0ll, ~((~ n0Oiil)));
	and(wire_n0O0O_dataout, ni0lO, ~((~ n0Oiil)));
	or(wire_n0O1i_dataout, ni01l, (~ n0Oi0O));
	or(wire_n0O1l_dataout, ni00i, (~ n0Oi0O));
	or(wire_n0O1O_dataout, (~ n0OO0l), (~ n0Oi0O));
	and(wire_n0Oi_dataout, ni1O1O, n0OO1l);
	or(wire_n0Oii_dataout, ni0Oi, (~ n0Oiil));
	and(wire_n0Oil_dataout, ni0Ol, ~((~ n0Oiil)));
	and(wire_n0OiO_dataout, nii1i, ~((~ n0Oiil)));
	and(wire_n0Ol_dataout, niiilO, n0OO1l);
	and(wire_n0Oli_dataout, wire_n0OOO_dataout, ~(n0Ol1l));
	assign		wire_n0Oll_dataout = (n0Ol1l === 1'b1) ? (~ n0OO0l) : wire_ni11i_dataout;
	assign		wire_n0OlO_dataout = (n0Ol1l === 1'b1) ? n0OO0l : wire_ni11l_dataout;
	and(wire_n0OO_dataout, niiiOi, n0OO1l);
	and(wire_n0OOi_dataout, wire_ni11O_dataout, ~(n0Ol1l));
	and(wire_n0OOl_dataout, wire_ni10i_dataout, ~(n0Ol1l));
	and(wire_n0OOO_dataout, wire_ni10l_dataout, ~(n0OiiO));
	and(wire_n100O_dataout, ni00i, ~((~ wire_ni_dataout)));
	and(wire_n10ii_dataout, ni01l, ~((~ wire_ni_dataout)));
	and(wire_n10il_dataout, ni0ll, ~((~ wire_ni_dataout)));
	and(wire_n10iO_dataout, ni0lO, ~((~ wire_ni_dataout)));
	and(wire_n10li_dataout, ni0Oi, ~((~ wire_ni_dataout)));
	and(wire_n10ll_dataout, ni0Ol, ~((~ wire_ni_dataout)));
	and(wire_n10lO_dataout, nii1i, ~((~ wire_ni_dataout)));
	or(wire_n10Oi_dataout, ni00l, ~(n0O1OO));
	or(wire_n10Ol_dataout, wire_n1i1l_dataout, n0O1OO);
	or(wire_n10OO_dataout, ni00i, n0O1OO);
	or(wire_n1i0i_dataout, ni00l, ~((~ n0O01l)));
	or(wire_n1i0l_dataout, wire_n1i1l_dataout, (~ n0O01l));
	or(wire_n1i0O_dataout, ni00i, (~ n0O01l));
	or(wire_n1i1i_dataout, ni00l, n0O1OO);
	or(wire_n1i1l_dataout, ni01l, ni00l);
	or(wire_n1iii_dataout, ni00l, (~ n0O01l));
	or(wire_n1iil_dataout, ni00l, ~((~ n0O01O)));
	or(wire_n1iiO_dataout, wire_n1i1l_dataout, (~ n0O01O));
	or(wire_n1ili_dataout, ni00i, (~ n0O01O));
	or(wire_n1ill_dataout, ni00l, (~ n0O01O));
	or(wire_n1ilO_dataout, ni00l, ~((~ n0O00i)));
	or(wire_n1iOi_dataout, wire_n1i1l_dataout, (~ n0O00i));
	or(wire_n1iOl_dataout, ni00i, (~ n0O00i));
	or(wire_n1iOO_dataout, ni00l, (~ n0O00i));
	assign		wire_n1l_dataout = (n0OO0O === 1'b1) ? rxc[2] : rxc[1];
	or(wire_n1l0i_dataout, (~ n0O0il), n0OO0l);
	or(wire_n1l0l_dataout, wire_n1lll_dataout, ~(n0OO0l));
	or(wire_n1l0O_dataout, ni01l, (~ n0O0il));
	assign		wire_n1l1i_dataout = (n0OO0l === 1'b1) ? wire_n1lil_dataout : ni00l;
	assign		wire_n1l1l_dataout = (n0OO0l === 1'b1) ? wire_n1liO_dataout : wire_n1l0O_dataout;
	assign		wire_n1l1O_dataout = (n0OO0l === 1'b1) ? wire_n1lli_dataout : wire_n1lii_dataout;
	or(wire_n1lii_dataout, ni00i, (~ n0O0il));
	or(wire_n1lil_dataout, ni00l, ~(n0O00l));
	or(wire_n1liO_dataout, wire_n1i1l_dataout, n0O00l);
	assign		wire_n1ll_dataout = (n0OO1l === 1'b1) ? nil00i : wire_n01i_dataout;
	or(wire_n1lli_dataout, ni00i, n0O00l);
	or(wire_n1lll_dataout, ni00l, n0O00l);
	assign		wire_n1lO_dataout = (n0OO1l === 1'b1) ? nil00l : wire_n01l_dataout;
	and(wire_n1lOi_dataout, (~ n0O0ll), ~((~ n0O0iO)));
	and(wire_n1lOl_dataout, n0O0ll, ~((~ n0O0iO)));
	or(wire_n1lOO_dataout, ni01l, (~ n0O0iO));
	assign		wire_n1O_dataout = (n0OO0O === 1'b1) ? rxd[32] : rxd[16];
	or(wire_n1O0i_dataout, wire_n1OiO_dataout, (~ n0O0iO));
	and(wire_n1O0l_dataout, wire_n1Oli_dataout, ~((~ n0O0iO)));
	or(wire_n1O0O_dataout, wire_n1Oll_dataout, (~ n0O0iO));
	or(wire_n1O1i_dataout, ni00i, (~ n0O0iO));
	or(wire_n1O1l_dataout, wire_n1Oii_dataout, (~ n0O0iO));
	and(wire_n1O1O_dataout, wire_n1Oil_dataout, ~((~ n0O0iO)));
	assign		wire_n1Oi_dataout = (n0OO1l === 1'b1) ? nil00O : wire_n01O_dataout;
	and(wire_n1Oii_dataout, wire_n1OlO_dataout, n0O0ll);
	and(wire_n1Oil_dataout, wire_n1OOi_dataout, n0O0ll);
	or(wire_n1OiO_dataout, wire_n1OOl_dataout, ~(n0O0ll));
	assign		wire_n1Ol_dataout = (n0OO1l === 1'b1) ? nil0ii : wire_n00i_dataout;
	and(wire_n1Oli_dataout, wire_n1OOO_dataout, n0O0ll);
	and(wire_n1Oll_dataout, wire_n011i_dataout, n0O0ll);
	and(wire_n1OlO_dataout, wire_n011l_dataout, ~(n0Ol1O));
	and(wire_n1OO_dataout, wire_n00l_dataout, ~(n0OO1l));
	and(wire_n1OOi_dataout, wire_n011O_dataout, ~(n0Ol1O));
	and(wire_n1OOl_dataout, wire_n010i_dataout, ~(n0Ol1O));
	and(wire_n1OOO_dataout, wire_n010l_dataout, ~(n0Ol1O));
	and(wire_ni_dataout, rbisten_rx, (((~ rbist_sel[0]) & rbist_sel[1]) & (n0OOiO4 ^ n0OOiO3)));
	assign		wire_ni000l_dataout = (n0OO0l === 1'b1) ? wire_ni00lO_dataout : wire_ni00iO_dataout;
	assign		wire_ni000O_dataout = (n0OO0l === 1'b1) ? wire_ni00Oi_dataout : wire_ni00li_dataout;
	or(wire_ni001l_dataout, niiO1O, n0l1il);
	or(wire_ni001O_dataout, niiO0i, n0l1il);
	or(wire_ni00ii_dataout, n0l1li, n0OO0l);
	assign		wire_ni00il_dataout = (n0OO0l === 1'b1) ? n0l1lO : n0l1li;
	or(wire_ni00iO_dataout, niiO1O, n0l1li);
	or(wire_ni00li_dataout, niiO0i, n0l1li);
	or(wire_ni00lO_dataout, niiO1O, n0l1lO);
	or(wire_ni00Oi_dataout, niiO0i, n0l1lO);
	or(wire_ni00OO_dataout, niiO1O, n0l1Ol);
	or(wire_ni010i_dataout, niiO0i, n0l11l);
	assign		wire_ni010O_dataout = (n0OO0l === 1'b1) ? wire_ni01Ol_dataout : wire_ni01ll_dataout;
	or(wire_ni011i_dataout, niiO1l, n0iOOO);
	or(wire_ni011O_dataout, niiO1O, n0l11l);
	assign		wire_ni01ii_dataout = (n0OO0l === 1'b1) ? wire_ni01OO_dataout : wire_ni01lO_dataout;
	or(wire_ni01il_dataout, n0l10i, n0OO0l);
	assign		wire_ni01iO_dataout = (n0OO0l === 1'b1) ? (~ n0l10O) : (~ n0l10i);
	assign		wire_ni01li_dataout = (n0OO0l === 1'b1) ? n0l10O : n0l10i;
	or(wire_ni01ll_dataout, niiO1O, n0l10i);
	or(wire_ni01lO_dataout, niiO0i, n0l10i);
	or(wire_ni01Ol_dataout, niiO1O, n0l10O);
	or(wire_ni01OO_dataout, niiO0i, n0l10O);
	and(wire_ni0i_dataout, niil1l, n0OO1l);
	assign		wire_ni0i0i_dataout = (n0OO0l === 1'b1) ? wire_ni0ilO_dataout : wire_ni0iiO_dataout;
	or(wire_ni0i0l_dataout, n0l01i, n0OO0l);
	assign		wire_ni0i0O_dataout = (n0OO0l === 1'b1) ? (~ n0l01O) : (~ n0l01i);
	or(wire_ni0i1i_dataout, niiO0i, n0l1Ol);
	assign		wire_ni0i1O_dataout = (n0OO0l === 1'b1) ? wire_ni0ill_dataout : wire_ni0iil_dataout;
	assign		wire_ni0iii_dataout = (n0OO0l === 1'b1) ? n0l01O : n0l01i;
	or(wire_ni0iil_dataout, niiO1O, n0l01i);
	or(wire_ni0iiO_dataout, niiO0i, n0l01i);
	or(wire_ni0ill_dataout, niiO1O, n0l01O);
	or(wire_ni0ilO_dataout, niiO0i, n0l01O);
	or(wire_ni0iOl_dataout, niiO1O, n0l00l);
	or(wire_ni0iOO_dataout, niiO0i, n0l00l);
	and(wire_ni0l_dataout, niil1O, n0OO1l);
	or(wire_ni0l0i_dataout, n0l0ii, n0OO0l);
	assign		wire_ni0l0l_dataout = (n0OO0l === 1'b1) ? n0l0li : n0l0ii;
	or(wire_ni0l0O_dataout, niiO1O, n0l0ii);
	assign		wire_ni0l1l_dataout = (n0OO0l === 1'b1) ? wire_ni0liO_dataout : wire_ni0l0O_dataout;
	assign		wire_ni0l1O_dataout = (n0OO0l === 1'b1) ? wire_ni0lli_dataout : wire_ni0lii_dataout;
	or(wire_ni0lii_dataout, niiO0i, n0l0ii);
	or(wire_ni0liO_dataout, niiO1O, n0l0li);
	or(wire_ni0lli_dataout, niiO0i, n0l0li);
	or(wire_ni0llO_dataout, niiO1O, n0li1i);
	or(wire_ni0lOi_dataout, niiO0i, n0li1i);
	or(wire_ni0lOl_dataout, wire_ni0O1O_dataout, n0li1i);
	and(wire_ni0lOO_dataout, wire_ni0O0i_dataout, ~(n0li1i));
	and(wire_ni0O_dataout, niil0i, n0OO1l);
	or(wire_ni0O0i_dataout, wire_ni0Oil_dataout, n0l0Ol);
	and(wire_ni0O0l_dataout, wire_ni0OiO_dataout, ~(n0l0Ol));
	and(wire_ni0O0O_dataout, wire_ni0Oli_dataout, ~(n0l0Ol));
	or(wire_ni0O1i_dataout, wire_ni0O0l_dataout, n0li1i);
	or(wire_ni0O1l_dataout, wire_ni0O0O_dataout, n0li1i);
	or(wire_ni0O1O_dataout, wire_ni0Oii_dataout, n0l0Ol);
	or(wire_ni0Oii_dataout, nil00i, n0l0Oi);
	or(wire_ni0Oil_dataout, nil00l, n0l0Oi);
	and(wire_ni0OiO_dataout, nil00O, ~(n0l0Oi));
	and(wire_ni0Oli_dataout, nil0ii, ~(n0l0Oi));
	or(wire_ni0OOi_dataout, wire_nii10l_dataout, n0liii);
	or(wire_ni0OOl_dataout, niiO1O, n0liii);
	or(wire_ni0OOO_dataout, niiO0i, n0liii);
	and(wire_ni10i_dataout, wire_ni1iO_dataout, ~(n0OiiO));
	assign		wire_ni10l_dataout = (n0Oiii === 1'b1) ? (~ n0OO0l) : ni0ll;
	assign		wire_ni10O_dataout = (n0Oiii === 1'b1) ? (~ n0OO0l) : ni0lO;
	assign		wire_ni11i_dataout = (n0OiiO === 1'b1) ? (~ n0OO0l) : wire_ni10O_dataout;
	assign		wire_ni11l_dataout = (n0OiiO === 1'b1) ? n0OO0l : wire_ni1ii_dataout;
	and(wire_ni11O_dataout, wire_ni1il_dataout, ~(n0OiiO));
	and(wire_ni1i_dataout, niiiOl, n0OO1l);
	assign		wire_ni1ii_dataout = (n0Oiii === 1'b1) ? n0OO0l : ni0Oi;
	and(wire_ni1il_dataout, ni0Ol, ~(n0Oiii));
	and(wire_ni1iO_dataout, nii1i, ~(n0Oiii));
	and(wire_ni1l_dataout, niiiOO, n0OO1l);
	and(wire_ni1l0l_dataout, niiO1l, ~((~ wire_nO_dataout)));
	and(wire_ni1l0O_dataout, niiO1O, ~((~ wire_nO_dataout)));
	and(wire_ni1lii_dataout, niiO0i, ~((~ wire_nO_dataout)));
	and(wire_ni1lil_dataout, nil00i, ~((~ wire_nO_dataout)));
	and(wire_ni1liO_dataout, nil00l, ~((~ wire_nO_dataout)));
	and(wire_ni1lli_dataout, nil00O, ~((~ wire_nO_dataout)));
	and(wire_ni1lll_dataout, nil0ii, ~((~ wire_nO_dataout)));
	or(wire_ni1llO_dataout, niiO1l, ~(n0iOll));
	or(wire_ni1lOi_dataout, niiO1O, n0iOll);
	or(wire_ni1lOl_dataout, wire_ni1O1i_dataout, n0iOll);
	or(wire_ni1lOO_dataout, niiO1l, n0iOll);
	and(wire_ni1O_dataout, niil1i, n0OO1l);
	assign		wire_ni1O0i_dataout = (n0OO0l === 1'b1) ? wire_ni1OOi_dataout : niiO1l;
	assign		wire_ni1O0l_dataout = (n0OO0l === 1'b1) ? n0iOOO : n0iOOi;
	assign		wire_ni1O0O_dataout = (n0OO0l === 1'b1) ? wire_ni1OOl_dataout : wire_ni1Oli_dataout;
	or(wire_ni1O1i_dataout, niiO0i, niiO1l);
	assign		wire_ni1Oii_dataout = (n0OO0l === 1'b1) ? wire_ni1OOO_dataout : wire_ni1Oll_dataout;
	or(wire_ni1Oil_dataout, n0iOOi, n0OO0l);
	or(wire_ni1OiO_dataout, wire_ni011i_dataout, ~(n0OO0l));
	or(wire_ni1Oli_dataout, niiO1O, n0iOOi);
	or(wire_ni1Oll_dataout, niiO0i, n0iOOi);
	or(wire_ni1OOi_dataout, niiO1l, ~(n0iOOO));
	or(wire_ni1OOl_dataout, niiO1O, n0iOOO);
	or(wire_ni1OOO_dataout, wire_ni1O1i_dataout, n0iOOO);
	assign		wire_nii_dataout = (n0OO0O === 1'b1) ? rxd[36] : rxd[20];
	or(wire_nii00i_dataout, nil00i, n0liil);
	and(wire_nii00l_dataout, nil00l, ~(n0liil));
	and(wire_nii00O_dataout, nil00O, ~(n0liil));
	assign		wire_nii0i_dataout = (wire_n11il_o === 1'b1) ? wire_niiOl_o[0] : wire_niiiO_dataout;
	and(wire_nii0ii_dataout, nil0ii, ~(n0liil));
	assign		wire_nii0l_dataout = (wire_n11il_o === 1'b1) ? wire_niiOl_o[1] : wire_niili_dataout;
	or(wire_nii0ll_dataout, wire_niOi0i_dataout, ~(wire_nii0Ol_o[2]));
	assign		wire_nii0O_dataout = (wire_n11il_o === 1'b1) ? wire_niiOl_o[2] : wire_niill_dataout;
	or(wire_nii0Oi_dataout, wire_niOi0O_dataout, ~(wire_nii0Ol_o[2]));
	or(wire_nii10i_dataout, wire_nii1iO_dataout, n0liii);
	and(wire_nii10l_dataout, (~ n0li1O), ~(n0li0l));
	and(wire_nii10O_dataout, wire_nii1li_dataout, ~(n0li0l));
	or(wire_nii11i_dataout, wire_nii10O_dataout, n0liii);
	and(wire_nii11l_dataout, wire_nii1ii_dataout, ~(n0liii));
	or(wire_nii11O_dataout, wire_nii1il_dataout, n0liii);
	or(wire_nii1ii_dataout, wire_nii1ll_dataout, n0li0l);
	and(wire_nii1il_dataout, wire_nii1lO_dataout, ~(n0li0l));
	and(wire_nii1iO_dataout, wire_nii1Oi_dataout, ~(n0li0l));
	and(wire_nii1l_dataout, wire_n11OO_o, ~(rbist_clr_rx));
	and(wire_nii1li_dataout, nil00i, ~(n0li1O));
	or(wire_nii1ll_dataout, nil00l, n0li1O);
	and(wire_nii1lO_dataout, nil00O, ~(n0li1O));
	and(wire_nii1O_dataout, wire_n11Ol_o, ~(rbist_clr_rx));
	and(wire_nii1Oi_dataout, nil0ii, ~(n0li1O));
	and(wire_niii_dataout, niil0l, n0OO1l);
	assign		wire_niiii_dataout = (wire_n11il_o === 1'b1) ? wire_niiOl_o[3] : wire_niilO_dataout;
	assign		wire_niiil_dataout = (wire_n11il_o === 1'b1) ? wire_niiOl_o[4] : wire_niiOi_dataout;
	and(wire_niiiO_dataout, ni00O, ~(wire_n11iO_o));
	and(wire_niil_dataout, niil0O, n0OO1l);
	and(wire_niili_dataout, ni0ii, ~(wire_n11iO_o));
	and(wire_niill_dataout, ni0il, ~(wire_n11iO_o));
	and(wire_niilO_dataout, ni0iO, ~(wire_n11iO_o));
	and(wire_niiO_dataout, niilii, n0OO1l);
	and(wire_niiOi_dataout, ni0li, ~(wire_n11iO_o));
	assign		wire_nil_dataout = (n0OO0O === 1'b1) ? rxd[37] : rxd[21];
	and(wire_nil0il_dataout, wire_niliOl_dataout, ~(rbist_clr_rx));
	and(wire_nil0iO_dataout, wire_niliOO_dataout, ~(rbist_clr_rx));
	and(wire_nil0li_dataout, wire_nill1i_dataout, ~(rbist_clr_rx));
	and(wire_nil0ll_dataout, wire_nill1l_dataout, ~(rbist_clr_rx));
	and(wire_nil0lO_dataout, wire_nill1O_dataout, ~(rbist_clr_rx));
	and(wire_nil0Oi_dataout, wire_nill0i_dataout, ~(rbist_clr_rx));
	and(wire_nil0Ol_dataout, wire_nill0l_dataout, ~(rbist_clr_rx));
	and(wire_nil0OO_dataout, wire_nill0O_dataout, ~(rbist_clr_rx));
	and(wire_nili_dataout, niilil, n0OO1l);
	and(wire_nili0i_dataout, wire_nillli_dataout, ~(rbist_clr_rx));
	and(wire_nili0l_dataout, wire_nillll_dataout, ~(rbist_clr_rx));
	and(wire_nili0O_dataout, wire_nilllO_dataout, ~(rbist_clr_rx));
	and(wire_nili1i_dataout, wire_nillii_dataout, ~(rbist_clr_rx));
	and(wire_nili1l_dataout, wire_nillil_dataout, ~(rbist_clr_rx));
	and(wire_nili1O_dataout, wire_nilliO_dataout, ~(rbist_clr_rx));
	and(wire_niliii_dataout, wire_nillOi_dataout, ~(rbist_clr_rx));
	and(wire_niliil_dataout, wire_nillOl_dataout, ~(rbist_clr_rx));
	and(wire_niliiO_dataout, wire_nillOO_dataout, ~(rbist_clr_rx));
	and(wire_nilili_dataout, wire_nilO1i_dataout, ~(rbist_clr_rx));
	and(wire_nilill_dataout, wire_ni1ilO_o, ~(rbist_clr_rx));
	and(wire_nililO_dataout, wire_ni1iOl_o, ~(rbist_clr_rx));
	and(wire_niliOi_dataout, wire_ni1iOO_o, ~(rbist_clr_rx));
	and(wire_niliOl_dataout, wire_nilO1l_dataout, ~((~ wire_nO_dataout)));
	and(wire_niliOO_dataout, wire_nilO1O_dataout, ~((~ wire_nO_dataout)));
	and(wire_nill_dataout, niiliO, n0OO1l);
	and(wire_nill0i_dataout, wire_nilOii_dataout, ~((~ wire_nO_dataout)));
	and(wire_nill0l_dataout, wire_nilOil_dataout, ~((~ wire_nO_dataout)));
	and(wire_nill0O_dataout, wire_nilOiO_dataout, ~((~ wire_nO_dataout)));
	and(wire_nill1i_dataout, wire_nilO0i_dataout, ~((~ wire_nO_dataout)));
	and(wire_nill1l_dataout, wire_nilO0l_dataout, ~((~ wire_nO_dataout)));
	and(wire_nill1O_dataout, wire_nilO0O_dataout, ~((~ wire_nO_dataout)));
	and(wire_nillii_dataout, wire_nilOli_dataout, ~((~ wire_nO_dataout)));
	and(wire_nillil_dataout, wire_nilOll_dataout, ~((~ wire_nO_dataout)));
	and(wire_nilliO_dataout, wire_nilOlO_dataout, ~((~ wire_nO_dataout)));
	and(wire_nillli_dataout, wire_nilOOi_dataout, ~((~ wire_nO_dataout)));
	and(wire_nillll_dataout, wire_nilOOl_dataout, ~((~ wire_nO_dataout)));
	and(wire_nilllO_dataout, wire_nilOOO_dataout, ~((~ wire_nO_dataout)));
	and(wire_nillOi_dataout, wire_niO11i_dataout, ~((~ wire_nO_dataout)));
	and(wire_nillOl_dataout, wire_niO11l_dataout, ~((~ wire_nO_dataout)));
	and(wire_nillOO_dataout, wire_niO11O_dataout, ~((~ wire_nO_dataout)));
	and(wire_nilO_dataout, niilli, n0OO1l);
	assign		wire_nilO0i_dataout = (niilOl === 1'b1) ? wire_nii0ll_dataout : niiiOi;
	assign		wire_nilO0l_dataout = (niilOl === 1'b1) ? wire_nii0lO_o : niiiOl;
	assign		wire_nilO0O_dataout = (niilOl === 1'b1) ? wire_nii0Oi_dataout : niiiOO;
	and(wire_nilO1i_dataout, wire_niO10i_dataout, ~((~ wire_nO_dataout)));
	assign		wire_nilO1l_dataout = (niilOl === 1'b1) ? wire_nii0iO_o : ni1O1O;
	assign		wire_nilO1O_dataout = (niilOl === 1'b1) ? wire_nii0li_o : niiilO;
	assign		wire_nilOii_dataout = (niilOl === 1'b1) ? wire_nii0OO_o : niil1i;
	assign		wire_nilOil_dataout = (niilOl === 1'b1) ? wire_niii1i_o : niil1l;
	assign		wire_nilOiO_dataout = (niilOl === 1'b1) ? wire_niii1l_o : niil1O;
	assign		wire_nilOli_dataout = (niilOl === 1'b1) ? wire_niii1O_o : niil0i;
	assign		wire_nilOll_dataout = (niilOl === 1'b1) ? wire_niii0i_o : niil0l;
	assign		wire_nilOlO_dataout = (niilOl === 1'b1) ? wire_niii0l_o : niil0O;
	assign		wire_nilOOi_dataout = (niilOl === 1'b1) ? wire_niii0O_o : niilii;
	assign		wire_nilOOl_dataout = (niilOl === 1'b1) ? wire_niiiii_o : niilil;
	assign		wire_nilOOO_dataout = (niilOl === 1'b1) ? wire_niiiil_o : niiliO;
	assign		wire_niO_dataout = (n0OO0O === 1'b1) ? rxd[38] : rxd[22];
	and(wire_niO00i_dataout, wire_niO0OO_o[5], wire_ni1iiO_o);
	and(wire_niO00l_dataout, wire_niO0OO_o[6], wire_ni1iiO_o);
	and(wire_niO00O_dataout, wire_niOi1i_o[0], wire_ni1iiO_o);
	and(wire_niO01i_dataout, wire_niO0OO_o[2], wire_ni1iiO_o);
	and(wire_niO01l_dataout, wire_niO0OO_o[3], wire_ni1iiO_o);
	and(wire_niO01O_dataout, wire_niO0OO_o[4], wire_ni1iiO_o);
	and(wire_niO0ii_dataout, wire_niOi1i_o[1], wire_ni1iiO_o);
	and(wire_niO0il_dataout, wire_niOi1i_o[2], wire_ni1iiO_o);
	and(wire_niO0iO_dataout, wire_niOi1i_o[3], wire_ni1iiO_o);
	and(wire_niO0li_dataout, wire_niOi1i_o[4], wire_ni1iiO_o);
	and(wire_niO0ll_dataout, wire_niOi1i_o[5], wire_ni1iiO_o);
	and(wire_niO0lO_dataout, wire_niOi1i_o[6], wire_ni1iiO_o);
	and(wire_niO0Oi_dataout, wire_niOi1i_o[7], wire_ni1iiO_o);
	assign		wire_niO10i_dataout = (niilOl === 1'b1) ? wire_niiill_o : niilOi;
	and(wire_niO10l_dataout, niiOOl, wire_ni1iiO_o);
	and(wire_niO10O_dataout, wire_niO0Ol_o[0], wire_ni1iiO_o);
	assign		wire_niO11i_dataout = (niilOl === 1'b1) ? wire_niiiiO_o : niilli;
	assign		wire_niO11l_dataout = (niilOl === 1'b1) ? wire_niiili_o : niilll;
	assign		wire_niO11O_dataout = (niilOl === 1'b1) ? (~ wire_nii0Ol_o[2]) : niillO;
	and(wire_niO1ii_dataout, wire_niO0Ol_o[1], wire_ni1iiO_o);
	and(wire_niO1il_dataout, wire_niO0Ol_o[2], wire_ni1iiO_o);
	and(wire_niO1iO_dataout, wire_niO0Ol_o[3], wire_ni1iiO_o);
	and(wire_niO1li_dataout, wire_niO0Ol_o[4], wire_ni1iiO_o);
	and(wire_niO1ll_dataout, wire_niO0Ol_o[5], wire_ni1iiO_o);
	and(wire_niO1lO_dataout, wire_niO0Ol_o[6], wire_ni1iiO_o);
	or(wire_niO1Oi_dataout, niiO0O, ~(wire_ni1iiO_o));
	and(wire_niO1Ol_dataout, wire_niO0OO_o[0], wire_ni1iiO_o);
	and(wire_niO1OO_dataout, wire_niO0OO_o[1], wire_ni1iiO_o);
	and(wire_niOi_dataout, niilll, n0OO1l);
	assign		wire_niOi0i_dataout = (n0OO0l === 1'b1) ? nil11i : nil1iO;
	assign		wire_niOi0l_dataout = (n0OO0l === 1'b1) ? nil11l : nil1li;
	assign		wire_niOi0O_dataout = (n0OO0l === 1'b1) ? nil11O : nil1ll;
	assign		wire_niOi1l_dataout = (n0OO0l === 1'b1) ? niiOOl : nil1ii;
	assign		wire_niOi1O_dataout = (n0OO0l === 1'b1) ? niiOOO : nil1il;
	assign		wire_niOiii_dataout = (n0OO0l === 1'b1) ? nil10i : nil1lO;
	assign		wire_niOiil_dataout = (n0OO0l === 1'b1) ? nil10l : nil1Oi;
	assign		wire_niOiiO_dataout = (n0OO0l === 1'b1) ? nil10O : nil1Ol;
	and(wire_niOili_dataout, niiO0O, n0OO0l);
	and(wire_niOill_dataout, niiOii, n0OO0l);
	and(wire_niOilO_dataout, niiOil, n0OO0l);
	and(wire_niOiOi_dataout, niiOiO, n0OO0l);
	and(wire_niOiOl_dataout, niiOli, n0OO0l);
	and(wire_niOiOO_dataout, niiOll, n0OO0l);
	and(wire_niOl_dataout, niillO, n0OO1l);
	and(wire_niOl1i_dataout, niiOlO, n0OO0l);
	and(wire_niOl1l_dataout, niiOOi, n0OO0l);
	and(wire_niOO_dataout, niilOi, n0OO1l);
	and(wire_nl_dataout, rbisten_rx, (rbist_sel[0] & (~ rbist_sel[1])));
	or(wire_nl000l_dataout, nll0il, ~((~ n0liOi)));
	or(wire_nl000O_dataout, wire_nl001O_dataout, (~ n0liOi));
	or(wire_nl001i_dataout, nll0ii, n0lill);
	or(wire_nl001l_dataout, nll0il, n0lill);
	or(wire_nl001O_dataout, nll00O, nll0il);
	or(wire_nl00ii_dataout, nll0ii, (~ n0liOi));
	or(wire_nl00il_dataout, nll0il, (~ n0liOi));
	or(wire_nl00iO_dataout, nll0il, ~((~ n0liOl)));
	or(wire_nl00li_dataout, wire_nl001O_dataout, (~ n0liOl));
	or(wire_nl00ll_dataout, nll0ii, (~ n0liOl));
	or(wire_nl00lO_dataout, nll0il, (~ n0liOl));
	or(wire_nl00Oi_dataout, nll0il, ~((~ n0liOO)));
	or(wire_nl00Ol_dataout, wire_nl001O_dataout, (~ n0liOO));
	or(wire_nl00OO_dataout, nll0ii, (~ n0liOO));
	and(wire_nl01il_dataout, nll0ii, ~((~ wire_nl_dataout)));
	and(wire_nl01iO_dataout, nll00O, ~((~ wire_nl_dataout)));
	and(wire_nl01li_dataout, nlll1i, ~((~ wire_nl_dataout)));
	and(wire_nl01ll_dataout, nlll1l, ~((~ wire_nl_dataout)));
	and(wire_nl01lO_dataout, nlll1O, ~((~ wire_nl_dataout)));
	and(wire_nl01Oi_dataout, nlll0i, ~((~ wire_nl_dataout)));
	or(wire_nl01Ol_dataout, nll0il, ~(n0lill));
	or(wire_nl01OO_dataout, wire_nl001O_dataout, n0lill);
	assign		wire_nl0i_dataout = (n0OO1O === 1'b1) ? nll00O : wire_nl0O_dataout;
	assign		wire_nl0i0i_dataout = (n0OO0l === 1'b1) ? wire_nl0ill_dataout : wire_nl0iil_dataout;
	or(wire_nl0i0l_dataout, (~ n0ll1l), n0OO0l);
	or(wire_nl0i0O_dataout, wire_nl0ilO_dataout, ~(n0OO0l));
	or(wire_nl0i1i_dataout, nll0il, (~ n0liOO));
	assign		wire_nl0i1l_dataout = (n0OO0l === 1'b1) ? wire_nl0iiO_dataout : nll0il;
	assign		wire_nl0i1O_dataout = (n0OO0l === 1'b1) ? wire_nl0ili_dataout : wire_nl0iii_dataout;
	or(wire_nl0iii_dataout, nll00O, (~ n0ll1l));
	or(wire_nl0iil_dataout, nll0ii, (~ n0ll1l));
	or(wire_nl0iiO_dataout, nll0il, ~(n0ll1i));
	or(wire_nl0ili_dataout, wire_nl001O_dataout, n0ll1i);
	or(wire_nl0ill_dataout, nll0ii, n0ll1i);
	or(wire_nl0ilO_dataout, nll0il, n0ll1i);
	and(wire_nl0iOl_dataout, wire_nl0l0O_dataout, ~((~ n0ll1O)));
	and(wire_nl0iOO_dataout, wire_nl0l0l_dataout, ~((~ n0ll1O)));
	and(wire_nl0l_dataout, ni00i, n0OO0i);
	or(wire_nl0l0i_dataout, wire_nl0l0O_dataout, (~ n0ll1O));
	assign		wire_nl0l0l_dataout = (n0OO0l === 1'b1) ? n0ll0i : n0ll0l;
	assign		wire_nl0l0O_dataout = (n0OO0l === 1'b1) ? (~ n0ll0i) : (~ n0ll0l);
	or(wire_nl0l1i_dataout, nll00O, (~ n0ll1O));
	or(wire_nl0l1l_dataout, nll0ii, (~ n0ll1O));
	or(wire_nl0l1O_dataout, wire_nl0l0l_dataout, (~ n0ll1O));
	or(wire_nl0lii_dataout, nll00O, (~ n0ll0O));
	or(wire_nl0lil_dataout, nll0ii, (~ n0ll0O));
	and(wire_nl0liO_dataout, n0OO0l, ~((~ n0llii)));
	or(wire_nl0lli_dataout, nll00O, (~ n0llii));
	or(wire_nl0lll_dataout, nll0ii, (~ n0llii));
	or(wire_nl0llO_dataout, wire_nl0O1i_dataout, (~ n0llii));
	or(wire_nl0lOi_dataout, wire_nl0O1l_dataout, (~ n0llii));
	or(wire_nl0lOl_dataout, wire_nl0O1O_dataout, (~ n0llii));
	or(wire_nl0lOO_dataout, wire_nl0O0i_dataout, (~ n0llii));
	and(wire_nl0O_dataout, ni01l, n0OO0i);
	and(wire_nl0O0i_dataout, wire_nl0Oil_dataout, n0OO0l);
	or(wire_nl0O0l_dataout, wire_nl0OiO_dataout, n0llil);
	and(wire_nl0O0O_dataout, wire_nl0Oli_dataout, ~(n0llil));
	and(wire_nl0O1i_dataout, wire_nl0O0l_dataout, n0OO0l);
	or(wire_nl0O1l_dataout, wire_nl0O0O_dataout, ~(n0OO0l));
	or(wire_nl0O1O_dataout, wire_nl0Oii_dataout, ~(n0OO0l));
	or(wire_nl0Oii_dataout, wire_nl0Oll_dataout, n0llil);
	and(wire_nl0Oil_dataout, wire_nl0OlO_dataout, ~(n0llil));
	or(wire_nl0OiO_dataout, wire_nl0OOi_dataout, ~(n0lliO));
	or(wire_nl0Oli_dataout, wire_nl0OOl_dataout, ~(n0lliO));
	or(wire_nl0Oll_dataout, wire_nl0OOO_dataout, ~(n0lliO));
	and(wire_nl0OlO_dataout, wire_nli11i_dataout, n0lliO);
	and(wire_nl0OOi_dataout, wire_nli11l_dataout, ~(n0O11i));
	or(wire_nl0OOl_dataout, wire_nli11O_dataout, n0O11i);
	and(wire_nl0OOO_dataout, wire_nli10i_dataout, ~(n0O11i));
	assign		wire_nl1i_dataout = (n0OO1l === 1'b1) ? niiO1O : wire_nl1O_dataout;
	assign		wire_nl1l_dataout = (n0OO1l === 1'b1) ? niiO0i : wire_nl0i_dataout;
	assign		wire_nl1O_dataout = (n0OO1O === 1'b1) ? nll0ii : wire_nl0l_dataout;
	and(wire_nl1Oil_dataout, wire_nliill_dataout, wire_nl1Oli_o[5]);
	and(wire_nl1OiO_dataout, n0llOO, wire_nl1Oli_o[5]);
	and(wire_nl1Oll_dataout, wire_nli1Ol_dataout, wire_nl1Oli_o[6]);
	and(wire_nl1OlO_dataout, wire_nli1OO_dataout, wire_nl1Oli_o[6]);
	and(wire_nl1OOi_dataout, wire_nl0liO_dataout, wire_nl1Oli_o[7]);
	and(wire_nl1OOl_dataout, wire_nl0iOl_dataout, wire_nl1Oli_o[8]);
	and(wire_nl1OOO_dataout, wire_nl0iOO_dataout, wire_nl1Oli_o[8]);
	assign		wire_nli_dataout = (n0OO0O === 1'b1) ? rxd[39] : rxd[23];
	or(wire_nli00i_dataout, wire_nli0li_dataout, (~ n0llli));
	or(wire_nli00l_dataout, wire_nli0ll_dataout, (~ n0llli));
	or(wire_nli00O_dataout, wire_nli0lO_dataout, (~ n0llli));
	or(wire_nli01i_dataout, nll00O, (~ n0llli));
	or(wire_nli01l_dataout, nll0ii, (~ n0llli));
	or(wire_nli01O_dataout, wire_nli0iO_dataout, (~ n0llli));
	or(wire_nli0ii_dataout, (~ n0llll), ~(n0OO0l));
	and(wire_nli0il_dataout, n0llll, n0OO0l);
	assign		wire_nli0iO_dataout = (n0OO0l === 1'b1) ? n0llll : wire_nli0Oi_dataout;
	assign		wire_nli0li_dataout = (n0OO0l === 1'b1) ? (~ n0llll) : wire_nli0Ol_dataout;
	assign		wire_nli0ll_dataout = (n0OO0l === 1'b1) ? (~ n0llll) : wire_nli0OO_dataout;
	assign		wire_nli0lO_dataout = (n0OO0l === 1'b1) ? n0llll : wire_nlii1i_dataout;
	or(wire_nli0Oi_dataout, wire_nlii1l_dataout, n0llOl);
	and(wire_nli0Ol_dataout, wire_nlii1O_dataout, ~(n0llOl));
	and(wire_nli0OO_dataout, wire_nlii0i_dataout, ~(n0llOl));
	and(wire_nli10i_dataout, wire_nli1il_dataout, ~(n0lOiO));
	or(wire_nli10l_dataout, wire_nli1iO_dataout, n0lOiO);
	and(wire_nli10O_dataout, wire_nli1li_dataout, ~(n0lOil));
	or(wire_nli11i_dataout, wire_nli10l_dataout, n0O11i);
	or(wire_nli11l_dataout, wire_nli10O_dataout, n0lOiO);
	or(wire_nli11O_dataout, wire_nli1ii_dataout, n0lOiO);
	and(wire_nli1ii_dataout, wire_nli1ll_dataout, ~(n0lOil));
	or(wire_nli1il_dataout, wire_nli1lO_dataout, n0lOil);
	or(wire_nli1iO_dataout, wire_nli1Oi_dataout, n0lOil);
	or(wire_nli1li_dataout, nlll1i, n0lOll);
	and(wire_nli1ll_dataout, nlll1l, ~(n0lOll));
	or(wire_nli1lO_dataout, nlll1O, n0lOll);
	or(wire_nli1Oi_dataout, nlll0i, n0lOll);
	and(wire_nli1Ol_dataout, wire_nli0ii_dataout, ~((~ n0llli)));
	and(wire_nli1OO_dataout, wire_nli0il_dataout, ~((~ n0llli)));
	and(wire_nlii_dataout, wire_n1l_dataout, n0OO0l);
	or(wire_nlii0i_dataout, wire_nliiil_dataout, n0lllO);
	and(wire_nlii0l_dataout, wire_nliiiO_dataout, ~(n0lllO));
	or(wire_nlii0O_dataout, wire_nl0OOi_dataout, ~(n0llOi));
	or(wire_nlii1i_dataout, wire_nlii0l_dataout, n0llOl);
	or(wire_nlii1l_dataout, wire_nlii0O_dataout, n0lllO);
	and(wire_nlii1O_dataout, wire_nliiii_dataout, ~(n0lllO));
	or(wire_nliiii_dataout, wire_nl0OOl_dataout, ~(n0llOi));
	or(wire_nliiil_dataout, wire_nl0OOO_dataout, ~(n0llOi));
	and(wire_nliiiO_dataout, wire_nli11i_dataout, n0llOi);
	and(wire_nliill_dataout, wire_nlil1i_dataout, ~((~ n0llOO)));
	or(wire_nliilO_dataout, nll00O, (~ n0llOO));
	or(wire_nliiOi_dataout, nll0ii, (~ n0llOO));
	or(wire_nliiOl_dataout, wire_nlil1l_dataout, (~ n0llOO));
	or(wire_nliiOO_dataout, wire_nlil1O_dataout, (~ n0llOO));
	and(wire_nlil_dataout, wire_n1O_dataout, n0OO0l);
	assign		wire_nlil0i_dataout = (n0OO0l === 1'b1) ? wire_nlilli_dataout : wire_nlilii_dataout;
	assign		wire_nlil0l_dataout = (n0OO0l === 1'b1) ? wire_nlilll_dataout : wire_nlilil_dataout;
	assign		wire_nlil0O_dataout = (n0OO0l === 1'b1) ? wire_nlillO_dataout : wire_nliliO_dataout;
	assign		wire_nlil1i_dataout = (n0O11i === 1'b1) ? wire_nlilOi_dataout : wire_nlil0i_dataout;
	assign		wire_nlil1l_dataout = (n0O11i === 1'b1) ? wire_nlilOl_dataout : wire_nlil0l_dataout;
	assign		wire_nlil1O_dataout = (n0O11i === 1'b1) ? wire_nlilOO_dataout : wire_nlil0O_dataout;
	and(wire_nlilii_dataout, n0lO1i, ~(n0lO1O));
	and(wire_nlilil_dataout, (~ n0lO1i), ~(n0lO1O));
	or(wire_nliliO_dataout, n0lO1i, n0lO1O);
	and(wire_nlilli_dataout, n0lO1O, ~(n0lO1l));
	and(wire_nlilll_dataout, (~ n0lO1O), ~(n0lO1l));
	or(wire_nlillO_dataout, n0lO1O, n0lO1l);
	assign		wire_nlilOi_dataout = (n0OO0l === 1'b1) ? wire_nliO0i_dataout : wire_nliO1i_dataout;
	assign		wire_nlilOl_dataout = (n0OO0l === 1'b1) ? wire_nliO0l_dataout : wire_nliO1l_dataout;
	assign		wire_nlilOO_dataout = (n0OO0l === 1'b1) ? wire_nliO0O_dataout : wire_nliO1O_dataout;
	and(wire_nliO_dataout, wire_n0i_dataout, n0OO0l);
	and(wire_nliO0i_dataout, n0lO0O, ~(n0lO0l));
	and(wire_nliO0l_dataout, (~ n0lO0O), ~(n0lO0l));
	or(wire_nliO0O_dataout, n0lO0O, n0lO0l);
	and(wire_nliO1i_dataout, n0lO0i, ~(n0lO0O));
	and(wire_nliO1l_dataout, (~ n0lO0i), ~(n0lO0O));
	or(wire_nliO1O_dataout, n0lO0i, n0lO0O);
	or(wire_nliOii_dataout, nll00O, (~ n0lOii));
	or(wire_nliOil_dataout, nll0ii, (~ n0lOii));
	and(wire_nliOiO_dataout, wire_nliOOi_dataout, ~(n0O11i));
	and(wire_nliOli_dataout, wire_nliOOl_dataout, ~(n0O11i));
	or(wire_nliOll_dataout, wire_nliOOO_dataout, n0O11i);
	and(wire_nliOlO_dataout, wire_nll11i_dataout, ~(n0O11i));
	or(wire_nliOOi_dataout, nlll1i, n0lOOl);
	and(wire_nliOOl_dataout, nlll1l, ~(n0lOOl));
	or(wire_nliOOO_dataout, nlll1O, n0lOOl);
	assign		wire_nll10i_dataout = (n0lOOO === 1'b1) ? (~ n0OO0l) : wire_nll1il_dataout;
	assign		wire_nll10l_dataout = (n0lOOO === 1'b1) ? n0OO0l : wire_nll1iO_dataout;
	and(wire_nll10O_dataout, wire_nll1li_dataout, ~(n0lOOO));
	and(wire_nll11i_dataout, nlll0i, ~(n0lOOl));
	and(wire_nll11O_dataout, wire_nll1ii_dataout, ~(n0lOOO));
	assign		wire_nll1ii_dataout = (n0lOlO === 1'b1) ? n0OO0l : wire_nll1ll_dataout;
	assign		wire_nll1il_dataout = (n0lOlO === 1'b1) ? (~ n0OO0l) : wire_nll1lO_dataout;
	assign		wire_nll1iO_dataout = (n0lOlO === 1'b1) ? n0OO0l : wire_nll1Oi_dataout;
	and(wire_nll1li_dataout, wire_nll1Ol_dataout, ~(n0lOlO));
	or(wire_nll1ll_dataout, nlll1i, n0lOli);
	assign		wire_nll1lO_dataout = (n0lOli === 1'b1) ? (~ n0OO0l) : nlll1l;
	assign		wire_nll1Oi_dataout = (n0lOli === 1'b1) ? n0OO0l : nlll1O;
	and(wire_nll1Ol_dataout, nlll0i, ~(n0lOli));
	and(wire_nlli_dataout, wire_n0l_dataout, n0OO0l);
	and(wire_nlll_dataout, wire_n0O_dataout, n0OO0l);
	and(wire_nlll0l_dataout, wire_nl011O_o, ~(rbist_clr_rx));
	and(wire_nlll0O_dataout, wire_nl011l_o, ~(rbist_clr_rx));
	assign		wire_nlllii_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[0] : wire_nlllOi_dataout;
	assign		wire_nlllil_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[1] : wire_nlllOl_dataout;
	assign		wire_nllliO_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[2] : wire_nlllOO_dataout;
	assign		wire_nlllli_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[3] : wire_nllO1i_dataout;
	assign		wire_nlllll_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[4] : wire_nllO1l_dataout;
	assign		wire_nllllO_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[5] : wire_nllO1O_dataout;
	and(wire_nlllOi_dataout, nll0iO, ~(wire_nl1OOO_dataout));
	and(wire_nlllOl_dataout, nll0li, ~(wire_nl1OOO_dataout));
	and(wire_nlllOO_dataout, nll0ll, ~(wire_nl1OOO_dataout));
	and(wire_nllO_dataout, wire_nii_dataout, n0OO0l);
	assign		wire_nllO0l_dataout = (wire_nl1OOi_dataout === 1'b1) ? wire_nllOil_o[0] : nll0OO;
	assign		wire_nllO0O_dataout = (wire_nl1OOi_dataout === 1'b1) ? wire_nllOil_o[1] : nlli1i;
	and(wire_nllO1i_dataout, nll0lO, ~(wire_nl1OOO_dataout));
	and(wire_nllO1l_dataout, nll0Oi, ~(wire_nl1OOO_dataout));
	and(wire_nllO1O_dataout, nll0Ol, ~(wire_nl1OOO_dataout));
	assign		wire_nllOii_dataout = (wire_nl1OOi_dataout === 1'b1) ? wire_nllOil_o[2] : nlli1l;
	and(wire_nllOiO_dataout, wire_nllOOi_dataout, ~(wire_nl1OlO_dataout));
	and(wire_nllOli_dataout, wire_nllOOl_dataout, ~(wire_nl1OlO_dataout));
	and(wire_nllOll_dataout, wire_nllOOO_dataout, ~(wire_nl1OlO_dataout));
	and(wire_nllOlO_dataout, wire_nlO11i_dataout, ~(wire_nl1OlO_dataout));
	assign		wire_nllOOi_dataout = (wire_nl1Oll_dataout === 1'b1) ? wire_nlO11l_o[0] : nlli1O;
	assign		wire_nllOOl_dataout = (wire_nl1Oll_dataout === 1'b1) ? wire_nlO11l_o[1] : nlli0i;
	assign		wire_nllOOO_dataout = (wire_nl1Oll_dataout === 1'b1) ? wire_nlO11l_o[2] : nlli0l;
	assign		wire_nlO00i_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[7] : nlliOl;
	assign		wire_nlO00l_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[8] : nlliOO;
	assign		wire_nlO01i_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[4] : nllill;
	assign		wire_nlO01l_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[5] : nllilO;
	assign		wire_nlO01O_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[6] : nlliOi;
	and(wire_nlO10i_dataout, wire_nlO1Oi_dataout, ~(wire_nl1Oil_dataout));
	and(wire_nlO10l_dataout, wire_nlO1Ol_dataout, ~(wire_nl1Oil_dataout));
	and(wire_nlO10O_dataout, wire_nlO1OO_dataout, ~(wire_nl1Oil_dataout));
	assign		wire_nlO11i_dataout = (wire_nl1Oll_dataout === 1'b1) ? wire_nlO11l_o[3] : nlli0O;
	and(wire_nlO11O_dataout, wire_nlO1lO_dataout, ~(wire_nl1Oil_dataout));
	and(wire_nlO1ii_dataout, wire_nlO01i_dataout, ~(wire_nl1Oil_dataout));
	and(wire_nlO1il_dataout, wire_nlO01l_dataout, ~(wire_nl1Oil_dataout));
	and(wire_nlO1iO_dataout, wire_nlO01O_dataout, ~(wire_nl1Oil_dataout));
	and(wire_nlO1li_dataout, wire_nlO00i_dataout, ~(wire_nl1Oil_dataout));
	and(wire_nlO1ll_dataout, wire_nlO00l_dataout, ~(wire_nl1Oil_dataout));
	assign		wire_nlO1lO_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[0] : nlliii;
	assign		wire_nlO1Oi_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[1] : nlliil;
	assign		wire_nlO1Ol_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[2] : nlliiO;
	assign		wire_nlO1OO_dataout = (wire_nl1OiO_dataout === 1'b1) ? wire_nlO00O_o[3] : nllili;
	and(wire_nlOi_dataout, wire_nil_dataout, n0OO0l);
	and(wire_nlOl_dataout, wire_niO_dataout, n0OO0l);
	and(wire_nlOO_dataout, wire_nli_dataout, n0OO0l);
	and(wire_nO_dataout, rbisten_rx, (((~ rbist_sel[0]) & (~ rbist_sel[1])) & (n0OOll2 ^ n0OOll1)));
	oper_add   niiOl
	( 
	.a({ni0li, ni0iO, ni0il, ni0ii, ni00O}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_niiOl_o));
	defparam
		niiOl.sgate_representation = 0,
		niiOl.width_a = 5,
		niiOl.width_b = 5,
		niiOl.width_o = 5;
	oper_add   niO0Ol
	( 
	.a({nil10O, nil10l, nil10i, nil11O, nil11l, nil11i, niiOOO}),
	.b({{6{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_niO0Ol_o));
	defparam
		niO0Ol.sgate_representation = 0,
		niO0Ol.width_a = 7,
		niO0Ol.width_b = 7,
		niO0Ol.width_o = 7;
	oper_add   niO0OO
	( 
	.a({niiOOi, niiOlO, niiOll, niiOli, niiOiO, niiOil, niiOii}),
	.b({{6{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_niO0OO_o));
	defparam
		niO0OO.sgate_representation = 0,
		niO0OO.width_a = 7,
		niO0OO.width_b = 7,
		niO0OO.width_o = 7;
	oper_add   niOi1i
	( 
	.a({nil1Ol, nil1Oi, nil1lO, nil1ll, nil1li, nil1iO, nil1il, nil1ii}),
	.b({{7{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_niOi1i_o));
	defparam
		niOi1i.sgate_representation = 0,
		niOi1i.width_a = 8,
		niOi1i.width_b = 8,
		niOi1i.width_o = 8;
	oper_add   nllO0i
	( 
	.a({nll0Ol, nll0Oi, nll0lO, nll0ll, nll0li, nll0iO}),
	.b({{5{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nllO0i_o));
	defparam
		nllO0i.sgate_representation = 0,
		nllO0i.width_a = 6,
		nllO0i.width_b = 6,
		nllO0i.width_o = 6;
	oper_add   nllOil
	( 
	.a({nlli1l, nlli1i, nll0OO}),
	.b({{2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nllOil_o));
	defparam
		nllOil.sgate_representation = 0,
		nllOil.width_a = 3,
		nllOil.width_b = 3,
		nllOil.width_o = 3;
	oper_add   nlO00O
	( 
	.a({nlliOO, nlliOl, nlliOi, nllilO, nllill, nllili, nlliiO, nlliil, nlliii}),
	.b({{8{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlO00O_o));
	defparam
		nlO00O.sgate_representation = 0,
		nlO00O.width_a = 9,
		nlO00O.width_b = 9,
		nlO00O.width_o = 9;
	oper_add   nlO11l
	( 
	.a({nlli0O, nlli0l, nlli0i, nlli1O}),
	.b({{3{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlO11l_o));
	defparam
		nlO11l.sgate_representation = 0,
		nlO11l.width_a = 4,
		nlO11l.width_b = 4,
		nlO11l.width_o = 4;
	oper_decoder   n11ll
	( 
	.i({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll}),
	.o(wire_n11ll_o));
	defparam
		n11ll.width_i = 5,
		n11ll.width_o = 32;
	oper_decoder   ni1ill
	( 
	.i({nil0ii, nil00O, nil00l, nil00i}),
	.o(wire_ni1ill_o));
	defparam
		ni1ill.width_i = 4,
		ni1ill.width_o = 16;
	oper_decoder   nii0Ol
	( 
	.i({nil01O, nil01l, nil01i, nil1OO}),
	.o(wire_nii0Ol_o));
	defparam
		nii0Ol.width_i = 4,
		nii0Ol.width_o = 16;
	oper_decoder   nl1Oli
	( 
	.i({nlll0i, nlll1O, nlll1l, nlll1i}),
	.o(wire_nl1Oli_o));
	defparam
		nl1Oli.width_i = 4,
		nl1Oli.width_o = 16;
	oper_mux   n100i
	( 
	.data({{10{1'b0}}, wire_n10ll_dataout, {5{1'b0}}, wire_n1O0l_dataout, wire_n00iO_dataout, n0O0lO, n0O0Oi, ((n0O1iO38 ^ n0O1iO37) & n0O0Ol), n0O0OO, n0Oi1i, n0Oi1l, n0Oi1O, wire_n0lOi_dataout, {3{1'b0}}, wire_n0Oil_dataout, wire_n0OOi_dataout, 1'b0}),
	.o(wire_n100i_o),
	.sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll}));
	defparam
		n100i.width_data = 32,
		n100i.width_sel = 5;
	oper_mux   n100l
	( 
	.data({{10{1'b0}}, wire_n10lO_dataout, ((n0O1li36 ^ n0O1li35) & wire_n1i1i_dataout), wire_n1iii_dataout, wire_n1ill_dataout, ((n0O1ll34 ^ n0O1ll33) & wire_n1iOO_dataout), wire_n1l0l_dataout, wire_n1O0O_dataout, wire_n00li_dataout, (~ n0O0lO), (~ n0O0Oi), (~ n0O0Ol), ((n0O1lO32 ^ n0O1lO31) & (~ n0O0OO)), ((n0O1Oi30 ^ n0O1Oi29) & (~ n0Oi1i)), (~ n0Oi1l), (~ n0Oi1O), (~ n0Oi0i), (~ n0Oi0l), (~ n0Oi0O), 1'b0, wire_n0OiO_dataout, wire_n0OOl_dataout, 1'b0}),
	.o(wire_n100l_o),
	.sel({((n0O1Ol28 ^ n0O1Ol27) & nii1i), ni0Ol, ni0Oi, ni0lO, ni0ll}));
	defparam
		n100l.width_data = 32,
		n100l.width_sel = 5;
	oper_mux   n101i
	( 
	.data({{10{1'b0}}, wire_n10il_dataout, {4{1'b1}}, wire_n1l0i_dataout, wire_n1O1l_dataout, wire_n000O_dataout, (~ n0O0lO), wire_n0iii_dataout, (~ n0O0Ol), wire_n0iOi_dataout, (~ n0Oi1i), wire_n0l0l_dataout, (~ n0Oi1O), wire_n0llO_dataout, (~ n0Oi0l), wire_n0O1O_dataout, 1'b0, wire_n0O0l_dataout, wire_n0Oli_dataout, (wire_ni_dataout & n11ii)}),
	.o(wire_n101i_o),
	.sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll}));
	defparam
		n101i.width_data = 32,
		n101i.width_sel = 5;
	oper_mux   n101l
	( 
	.data({{10{1'b0}}, wire_n10iO_dataout, {5{1'b0}}, wire_n1O1O_dataout, wire_n00ii_dataout, n0O0lO, wire_n0iil_dataout, 1'b0, wire_n0iOl_dataout, n0Oi1i, wire_n0l0O_dataout, 1'b0, wire_n0lll_dataout, n0Oi0l, wire_n0O0i_dataout, 1'b0, wire_n0O0O_dataout, wire_n0Oll_dataout, 1'b0}),
	.o(wire_n101l_o),
	.sel({nii1i, ni0Ol, ni0Oi, ((n0O10l46 ^ n0O10l45) & ni0lO), ni0ll}));
	defparam
		n101l.width_data = 32,
		n101l.width_sel = 5;
	oper_mux   n101O
	( 
	.data({{10{1'b0}}, ((n0O10O44 ^ n0O10O43) & wire_n10li_dataout), wire_n1i1i_dataout, wire_n1iii_dataout, ((n0O1ii42 ^ n0O1ii41) & wire_n1ill_dataout), wire_n1iOO_dataout, wire_n1l0l_dataout, wire_n1O0i_dataout, ((n0O1il40 ^ n0O1il39) & wire_n00il_dataout), {3{1'b1}}, wire_n0iOO_dataout, (~ n0Oi1i), (~ n0Oi1l), (~ n0Oi1O), wire_n0llO_dataout, {3{1'b1}}, wire_n0Oii_dataout, wire_n0OlO_dataout, 1'b0}),
	.o(wire_n101O_o),
	.sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll}));
	defparam
		n101O.width_data = 32,
		n101O.width_sel = 5;
	oper_mux   n11Ol
	( 
	.data({{10{ni00i}}, wire_n100O_dataout, wire_n10OO_dataout, wire_n1i0O_dataout, wire_n1ili_dataout, wire_n1iOl_dataout, wire_n1l1O_dataout, wire_n1O1i_dataout, wire_n000l_dataout, wire_n0i0i_dataout, wire_n0i0O_dataout, wire_n0ili_dataout, wire_n0ilO_dataout, wire_n0l1l_dataout, wire_n0l0i_dataout, wire_n0lil_dataout, wire_n0lli_dataout, wire_n0lOO_dataout, wire_n0O1l_dataout, {4{ni00i}}}),
	.o(wire_n11Ol_o),
	.sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll}));
	defparam
		n11Ol.width_data = 32,
		n11Ol.width_sel = 5;
	oper_mux   n11OO
	( 
	.data({{10{ni01l}}, wire_n10ii_dataout, wire_n10Ol_dataout, wire_n1i0l_dataout, wire_n1iiO_dataout, wire_n1iOi_dataout, wire_n1l1l_dataout, wire_n1lOO_dataout, wire_n000i_dataout, wire_n0i1O_dataout, wire_n0i0l_dataout, wire_n0iiO_dataout, wire_n0ill_dataout, wire_n0l1i_dataout, wire_n0l1O_dataout, wire_n0lii_dataout, wire_n0liO_dataout, wire_n0lOl_dataout, wire_n0O1i_dataout, {4{ni01l}}}),
	.o(wire_n11OO_o),
	.sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll}));
	defparam
		n11OO.width_data = 32,
		n11OO.width_sel = 5;
	oper_mux   ni1ilO
	( 
	.data({{3{1'b0}}, n0iOll, wire_ni1O0l_dataout, n0l11l, wire_ni01li_dataout, n0l1il, wire_ni00il_dataout, 1'b0, wire_ni0iii_dataout, n0l00l, wire_ni0l0l_dataout, n0li1i, n0liii, 1'b0}),
	.o(wire_ni1ilO_o),
	.sel({nil0ii, nil00O, nil00l, nil00i}));
	defparam
		ni1ilO.width_data = 16,
		ni1ilO.width_sel = 4;
	oper_mux   ni1iOi
	( 
	.data({{2{niiO1l}}, wire_ni1l0l_dataout, wire_ni1llO_dataout, wire_ni1O0i_dataout, {11{niiO1l}}}),
	.o(wire_ni1iOi_o),
	.sel({nil0ii, nil00O, nil00l, nil00i}));
	defparam
		ni1iOi.width_data = 16,
		ni1iOi.width_sel = 4;
	oper_mux   ni1iOl
	( 
	.data({{2{niiO1O}}, wire_ni1l0O_dataout, wire_ni1lOi_dataout, wire_ni1O0O_dataout, wire_ni011O_dataout, wire_ni010O_dataout, wire_ni001l_dataout, wire_ni000l_dataout, wire_ni00OO_dataout, wire_ni0i1O_dataout, wire_ni0iOl_dataout, wire_ni0l1l_dataout, wire_ni0llO_dataout, wire_ni0OOl_dataout, niiO1O}),
	.o(wire_ni1iOl_o),
	.sel({nil0ii, nil00O, nil00l, nil00i}));
	defparam
		ni1iOl.width_data = 16,
		ni1iOl.width_sel = 4;
	oper_mux   ni1iOO
	( 
	.data({{2{niiO0i}}, wire_ni1lii_dataout, wire_ni1lOl_dataout, wire_ni1Oii_dataout, wire_ni010i_dataout, wire_ni01ii_dataout, wire_ni001O_dataout, wire_ni000O_dataout, wire_ni0i1i_dataout, wire_ni0i0i_dataout, wire_ni0iOO_dataout, wire_ni0l1O_dataout, wire_ni0lOi_dataout, wire_ni0OOO_dataout, niiO0i}),
	.o(wire_ni1iOO_o),
	.sel({nil0ii, nil00O, nil00l, nil00i}));
	defparam
		ni1iOO.width_data = 16,
		ni1iOO.width_sel = 4;
	oper_mux   ni1l0i
	( 
	.data({{2{1'b0}}, wire_ni1lll_dataout, wire_ni1lOO_dataout, wire_ni1OiO_dataout, {4{1'b1}}, n0l1Ol, wire_ni0iii_dataout, n0l00l, wire_ni0l0l_dataout, wire_ni0O1l_dataout, wire_nii10i_dataout, wire_nii0ii_dataout}),
	.o(wire_ni1l0i_o),
	.sel({nil0ii, nil00O, nil00l, nil00i}));
	defparam
		ni1l0i.width_data = 16,
		ni1l0i.width_sel = 4;
	oper_mux   ni1l1i
	( 
	.data({{2{1'b0}}, wire_ni1lil_dataout, 1'b1, wire_ni1Oil_dataout, 1'b1, wire_ni01il_dataout, 1'b1, wire_ni00ii_dataout, 1'b1, wire_ni0i0l_dataout, 1'b1, wire_ni0l0i_dataout, wire_ni0lOl_dataout, wire_nii11i_dataout, wire_nii00i_dataout}),
	.o(wire_ni1l1i_o),
	.sel({nil0ii, nil00O, nil00l, nil00i}));
	defparam
		ni1l1i.width_data = 16,
		ni1l1i.width_sel = 4;
	oper_mux   ni1l1l
	( 
	.data({{2{1'b0}}, wire_ni1liO_dataout, {2{1'b0}}, (~ n0l11l), wire_ni01iO_dataout, {2{1'b0}}, (~ n0l1Ol), wire_ni0i0O_dataout, {2{1'b0}}, wire_ni0lOO_dataout, wire_nii11l_dataout, wire_nii00l_dataout}),
	.o(wire_ni1l1l_o),
	.sel({nil0ii, nil00O, nil00l, nil00i}));
	defparam
		ni1l1l.width_data = 16,
		ni1l1l.width_sel = 4;
	oper_mux   ni1l1O
	( 
	.data({{2{1'b0}}, wire_ni1lli_dataout, wire_ni1lOO_dataout, wire_ni1OiO_dataout, n0l11l, wire_ni01li_dataout, n0l1il, wire_ni00il_dataout, {4{1'b1}}, wire_ni0O1i_dataout, wire_nii11O_dataout, wire_nii00O_dataout}),
	.o(wire_ni1l1O_o),
	.sel({nil0ii, nil00O, nil00l, nil00i}));
	defparam
		ni1l1O.width_data = 16,
		ni1l1O.width_sel = 4;
	oper_mux   nii0iO
	( 
	.data({{4{1'b1}}, 1'b0, 1'b1, {7{1'b0}}, wire_niOi1l_dataout, {2{1'b1}}}),
	.o(wire_nii0iO_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		nii0iO.width_data = 16,
		nii0iO.width_sel = 4;
	oper_mux   nii0li
	( 
	.data({{3{1'b1}}, 1'b0, {2{1'b1}}, {7{1'b0}}, wire_niOi1O_dataout, {2{1'b1}}}),
	.o(wire_nii0li_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		nii0li.width_data = 16,
		nii0li.width_sel = 4;
	oper_mux   nii0lO
	( 
	.data({{5{1'b1}}, 1'b0, {7{1'b1}}, wire_niOi0l_dataout, {2{1'b1}}}),
	.o(wire_nii0lO_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		nii0lO.width_data = 16,
		nii0lO.width_sel = 4;
	oper_mux   nii0OO
	( 
	.data({{7{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, wire_niOiii_dataout, {2{1'b1}}}),
	.o(wire_nii0OO_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		nii0OO.width_data = 16,
		nii0OO.width_sel = 4;
	oper_mux   niii0i
	( 
	.data({{3{n0OO0l}}, {3{1'b0}}, n0OO0l, {6{1'b0}}, wire_niOill_dataout, {2{n0OO0l}}}),
	.o(wire_niii0i_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niii0i.width_data = 16,
		niii0i.width_sel = 4;
	oper_mux   niii0l
	( 
	.data({{3{n0OO0l}}, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, wire_niOilO_dataout, {2{n0OO0l}}}),
	.o(wire_niii0l_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niii0l.width_data = 16,
		niii0l.width_sel = 4;
	oper_mux   niii0O
	( 
	.data({{3{n0OO0l}}, 1'b0, n0OO0l, {3{1'b0}}, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, wire_niOiOi_dataout, {2{n0OO0l}}}),
	.o(wire_niii0O_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niii0O.width_data = 16,
		niii0O.width_sel = 4;
	oper_mux   niii1i
	( 
	.data({{8{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, wire_niOiil_dataout, {2{1'b1}}}),
	.o(wire_niii1i_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niii1i.width_data = 16,
		niii1i.width_sel = 4;
	oper_mux   niii1l
	( 
	.data({{9{1'b1}}, {4{1'b0}}, wire_niOiiO_dataout, {2{1'b1}}}),
	.o(wire_niii1l_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niii1l.width_data = 16,
		niii1l.width_sel = 4;
	oper_mux   niii1O
	( 
	.data({{3{n0OO0l}}, 1'b0, n0OO0l, 1'b0, n0OO0l, {6{1'b0}}, wire_niOili_dataout, {2{n0OO0l}}}),
	.o(wire_niii1O_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niii1O.width_data = 16,
		niii1O.width_sel = 4;
	oper_mux   niiiii
	( 
	.data({{3{n0OO0l}}, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, wire_niOiOl_dataout, {2{n0OO0l}}}),
	.o(wire_niiiii_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niiiii.width_data = 16,
		niiiii.width_sel = 4;
	oper_mux   niiiil
	( 
	.data({{3{n0OO0l}}, 1'b0, n0OO0l, 1'b0, n0OO0l, {3{1'b0}}, n0OO0l, 1'b0, n0OO0l, wire_niOiOO_dataout, {2{n0OO0l}}}),
	.o(wire_niiiil_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niiiil.width_data = 16,
		niiiil.width_sel = 4;
	oper_mux   niiiiO
	( 
	.data({{3{n0OO0l}}, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, {2{1'b0}}, wire_niOl1i_dataout, {2{n0OO0l}}}),
	.o(wire_niiiiO_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niiiiO.width_data = 16,
		niiiiO.width_sel = 4;
	oper_mux   niiili
	( 
	.data({{3{n0OO0l}}, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, {4{1'b0}}, wire_niOl1l_dataout, {2{n0OO0l}}}),
	.o(wire_niiili_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niiili.width_data = 16,
		niiili.width_sel = 4;
	oper_mux   niiill
	( 
	.data({{3{n0OO0l}}, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, n0OO0l, 1'b0, {2{n0OO0l}}}),
	.o(wire_niiill_o),
	.sel({nil01O, nil01l, nil01i, nil1OO}));
	defparam
		niiill.width_data = 16,
		niiill.width_sel = 4;
	oper_mux   nl010i
	( 
	.data({wire_nl01li_dataout, {4{1'b1}}, wire_nl0i0l_dataout, (~ n0ll0O), wire_nl0l1O_dataout, wire_nl0llO_dataout, wire_nli01O_dataout, wire_nliiOl_dataout, {2{1'b1}}, wire_nliOiO_dataout, wire_nll11O_dataout, (wire_nl_dataout & nl1Oii)}),
	.o(wire_nl010i_o),
	.sel({nlll0i, nlll1O, nlll1l, nlll1i}));
	defparam
		nl010i.width_data = 16,
		nl010i.width_sel = 4;
	oper_mux   nl010l
	( 
	.data({wire_nl01ll_dataout, wire_nl001l_dataout, wire_nl00il_dataout, wire_nl00lO_dataout, wire_nl0i1i_dataout, wire_nl0i0O_dataout, (~ n0ll0O), wire_nl0l1O_dataout, wire_nl0lOi_dataout, wire_nli00i_dataout, wire_nliiOO_dataout, (~ n0lOii), 1'b0, wire_nliOli_dataout, wire_nll10i_dataout, 1'b0}),
	.o(wire_nl010l_o),
	.sel({nlll0i, nlll1O, nlll1l, nlll1i}));
	defparam
		nl010l.width_data = 16,
		nl010l.width_sel = 4;
	oper_mux   nl010O
	( 
	.data({wire_nl01lO_dataout, wire_nl001l_dataout, wire_nl00il_dataout, wire_nl00lO_dataout, wire_nl0i1i_dataout, wire_nl0i0O_dataout, (~ n0ll0O), wire_nl0l1O_dataout, wire_nl0lOl_dataout, wire_nli00l_dataout, {3{1'b1}}, wire_nliOll_dataout, wire_nll10l_dataout, 1'b0}),
	.o(wire_nl010O_o),
	.sel({nlll0i, nlll1O, nlll1l, nlll1i}));
	defparam
		nl010O.width_data = 16,
		nl010O.width_sel = 4;
	oper_mux   nl011i
	( 
	.data({nll0il, wire_nl01Ol_dataout, wire_nl000l_dataout, wire_nl00iO_dataout, wire_nl00Oi_dataout, wire_nl0i1l_dataout, {10{nll0il}}}),
	.o(wire_nl011i_o),
	.sel({nlll0i, nlll1O, nlll1l, nlll1i}));
	defparam
		nl011i.width_data = 16,
		nl011i.width_sel = 4;
	oper_mux   nl011l
	( 
	.data({wire_nl01il_dataout, wire_nl001i_dataout, wire_nl00ii_dataout, wire_nl00ll_dataout, wire_nl00OO_dataout, wire_nl0i0i_dataout, wire_nl0lil_dataout, wire_nl0l1l_dataout, wire_nl0lll_dataout, wire_nli01l_dataout, wire_nliiOi_dataout, wire_nliOil_dataout, {4{nll0ii}}}),
	.o(wire_nl011l_o),
	.sel({nlll0i, nlll1O, nlll1l, nlll1i}));
	defparam
		nl011l.width_data = 16,
		nl011l.width_sel = 4;
	oper_mux   nl011O
	( 
	.data({wire_nl01iO_dataout, wire_nl01OO_dataout, wire_nl000O_dataout, wire_nl00li_dataout, wire_nl00Ol_dataout, wire_nl0i1O_dataout, wire_nl0lii_dataout, wire_nl0l1i_dataout, wire_nl0lli_dataout, wire_nli01i_dataout, wire_nliilO_dataout, wire_nliOii_dataout, {4{nll00O}}}),
	.o(wire_nl011O_o),
	.sel({nlll0i, nlll1O, nlll1l, nlll1i}));
	defparam
		nl011O.width_data = 16,
		nl011O.width_sel = 4;
	oper_mux   nl01ii
	( 
	.data({wire_nl01Oi_dataout, wire_nl001l_dataout, wire_nl00il_dataout, wire_nl00lO_dataout, wire_nl0i1i_dataout, wire_nl0i0O_dataout, 1'b1, wire_nl0l0i_dataout, wire_nl0lOO_dataout, wire_nli00O_dataout, (~ n0llOO), (~ n0lOii), 1'b0, wire_nliOlO_dataout, wire_nll10O_dataout, 1'b0}),
	.o(wire_nl01ii_o),
	.sel({nlll0i, nlll1O, nlll1l, nlll1i}));
	defparam
		nl01ii.width_data = 16,
		nl01ii.width_sel = 4;
	oper_selector   n11il
	( 
	.data({1'b0, wire_n1lOi_dataout, wire_n001l_dataout}),
	.o(wire_n11il_o),
	.sel({n0O11O, wire_n11ll_o[15:14]}));
	defparam
		n11il.width_data = 3,
		n11il.width_sel = 3;
	oper_selector   n11iO
	( 
	.data({1'b0, wire_n1lOl_dataout, wire_n001O_dataout}),
	.o(wire_n11iO_o),
	.sel({n0O11O, wire_n11ll_o[15:14]}));
	defparam
		n11iO.width_data = 3,
		n11iO.width_sel = 3;
	oper_selector   n11lO
	( 
	.data({ni00l, wire_n10Oi_dataout, wire_n1i0i_dataout, wire_n1iil_dataout, wire_n1ilO_dataout, wire_n1l1i_dataout}),
	.o(wire_n11lO_o),
	.sel({n0O10i, wire_n11ll_o[20:16]}));
	defparam
		n11lO.width_data = 6,
		n11lO.width_sel = 6;
	oper_selector   ni1iiO
	( 
	.data({1'b0, 1'b1, wire_ni0OOi_dataout}),
	.o(wire_ni1iiO_o),
	.sel({n0iOli, wire_ni1ill_o[2:1]}));
	defparam
		ni1iiO.width_data = 3,
		ni1iiO.width_sel = 3;
	assign
		bistdone = ((wire_nl1l_dataout | prbs_done) | (~ (n0OlOi10 ^ n0OlOi9))),
		bisterr = ((wire_nl1i_dataout | prbs_err) | (~ (n0OlOO8 ^ n0OlOO7))),
		cur_state = {wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout},
		err_ctl = {wire_niOO_dataout, wire_niOl_dataout},
		err_data = {wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout},
		n0iOli = (((((((((((((wire_ni1ill_o[15] | wire_ni1ill_o[14]) | wire_ni1ill_o[13]) | wire_ni1ill_o[12]) | wire_ni1ill_o[11]) | wire_ni1ill_o[10]) | wire_ni1ill_o[9]) | wire_ni1ill_o[8]) | wire_ni1ill_o[7]) | wire_ni1ill_o[6]) | wire_ni1ill_o[5]) | wire_ni1ill_o[4]) | wire_ni1ill_o[3]) | wire_ni1ill_o[0]),
		n0iOll = ((~ n0iOlO) | (~ n0l0il)),
		n0iOlO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0iOOi = ((~ n0iOOl) | (~ n0l0il)),
		n0iOOl = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0iOOO = ((~ n0l11i) | (~ n0l0ll)),
		n0l00i = ((((((((((((((((~ wire_nlOO_dataout) & wire_nlOl_dataout) & wire_nlOi_dataout) & wire_nllO_dataout) & wire_nlll_dataout) & wire_nlli_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])),
		n0l00l = ((~ n0l00O) | (~ n0l0il)),
		n0l00O = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & (~ rxd[6])) & (~ rxd[7])),
		n0l01i = ((~ n0l01l) | (~ n0l0il)),
		n0l01l = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])),
		n0l01O = ((~ n0l00i) | (~ n0l0ll)),
		n0l0ii = ((~ n0l0iO) | (~ n0l0il)),
		n0l0il = ((~ wire_nlii_dataout) & rxc[0]),
		n0l0iO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])),
		n0l0li = ((~ n0l0lO) | (~ n0l0ll)),
		n0l0ll = (wire_nlii_dataout & rxc[0]),
		n0l0lO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & wire_nlOi_dataout) & wire_nllO_dataout) & wire_nlll_dataout) & wire_nlli_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])),
		n0l0Oi = (((((((nil1Ol & nil1Oi) & nil1lO) & nil1ll) & nil1li) & nil1iO) & nil1il) & nil1ii),
		n0l0Ol = (n0OO0l & n0l0OO),
		n0l0OO = (((((((niiOOi & niiOlO) & niiOll) & niiOli) & niiOiO) & niiOil) & niiOii) & niiO0O),
		n0l10i = ((~ n0l10l) | (~ n0l0il)),
		n0l10l = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0l10O = ((~ n0l1ii) | (~ n0l0ll)),
		n0l11i = (((((((((((((((wire_nlOO_dataout & wire_nlOl_dataout) & wire_nlOi_dataout) & wire_nllO_dataout) & wire_nlll_dataout) & wire_nlli_dataout) & (~ wire_nliO_dataout)) & wire_nlil_dataout) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0l11l = ((~ n0l11O) | (~ n0l0il)),
		n0l11O = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0l1ii = (((((((((((((((wire_nlOO_dataout & wire_nlOl_dataout) & wire_nlOi_dataout) & wire_nllO_dataout) & (~ wire_nlll_dataout)) & wire_nlli_dataout) & wire_nliO_dataout) & wire_nlil_dataout) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0l1il = ((~ n0l1iO) | (~ n0l0il)),
		n0l1iO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & rxd[7]),
		n0l1li = ((~ n0l1ll) | (~ n0l0il)),
		n0l1ll = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & rxd[7]),
		n0l1lO = ((~ n0l1Oi) | (~ n0l0ll)),
		n0l1Oi = (((((((((((((((wire_nlOO_dataout & wire_nlOl_dataout) & (~ wire_nlOi_dataout)) & wire_nllO_dataout) & wire_nlll_dataout) & wire_nlli_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & rxd[7]),
		n0l1Ol = ((~ n0l1OO) | (~ n0l0il)),
		n0l1OO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & (~ rxd[7])),
		n0li0i = (((((((rxd[0] & rxd[1]) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0li0l = (n0OO0l & (wire_nlii_dataout & n0li0O)),
		n0li0O = (((((((wire_nlOO_dataout & wire_nlOl_dataout) & wire_nlOi_dataout) & wire_nllO_dataout) & wire_nlll_dataout) & (~ wire_nlli_dataout)) & wire_nliO_dataout) & wire_nlil_dataout),
		n0li1i = ((~ n0li1l) | (~ ((~ wire_nlii_dataout) & (~ rxc[0])))),
		n0li1l = ((((((((((((((((~ (rxd[0] ^ wire_niOi1l_dataout)) & (~ (rxd[1] ^ wire_niOi1O_dataout))) & (~ (rxd[2] ^ wire_niOi0i_dataout))) & (~ (rxd[3] ^ wire_niOi0l_dataout))) & (~ (rxd[4] ^ wire_niOi0O_dataout))) & (~ (rxd[5] ^ wire_niOiii_dataout))) & (~ (rxd[6] ^ wire_niOiil_dataout))) & (~ (rxd[7] ^ wire_niOiiO_dataout))) & (~ (wire_nlil_dataout ^ wire_niOili_dataout))) & (~ (wire_nliO_dataout ^ wire_niOill_dataout))) & (~ (wire_nlli_dataout ^ wire_niOilO_dataout))) & (~ (wire_nlll_dataout ^ wire_niOiOi_dataout))) & (~ (wire_nllO_dataout ^ wire_niOiOl_dataout))) & (~ (wire_nlOi_dataout ^ wire_niOiOO_dataout))) & (~ (wire_nlOl_dataout ^ wire_niOl1i_dataout))) & (~ (wire_nlOO_dataout ^ wire_niOl1l_dataout))),
		n0li1O = ((~ n0OO0l) & (rxc[0] & n0li0i)),
		n0liii = (((((((nil1Ol & nil1Oi) & nil1lO) & nil1ll) & nil1li) & nil1iO) & nil1il) & nil1ii),
		n0liil = (wire_nO_dataout & niilOO),
		n0lill = ((~ rxc[0]) | (~ n0lilO)),
		n0lilO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0liOi = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & (~ rxd[4])) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0liOl = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0liOO = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & rxd[7]) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0ll0i = ((((((~ nll0Ol) & nll0Oi) & (~ nll0lO)) & (~ nll0ll)) & nll0li) & nll0iO),
		n0ll0l = (((((nll0Ol & (~ nll0Oi)) & (~ nll0lO)) & nll0ll) & nll0li) & nll0iO),
		n0ll0O = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nllO_dataout)) & (~ wire_nlli_dataout)) & rxd[5]) & rxd[7]) & (~ ((~ n0OO0l) ^ rxd[0]))) & (~ ((~ n0OO0l) ^ rxd[1]))) & (~ (n0OO0l ^ rxd[2]))) & (~ ((~ n0OO0l) ^ rxd[3]))) & (~ (n0OO0l ^ rxd[4]))) & (~ (n0OO0l ^ rxd[6]))) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nliO_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0ll1i = ((~ n0ll1l) | (~ (wire_nlii_dataout & (~ rxc[0])))),
		n0ll1l = ((((((((((((((((~ wire_nliO_dataout) & rxd[0]) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0ll1O = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nlll_dataout)) & (~ wire_nliO_dataout)) & rxd[0]) & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0llii = ((((((((((((((((~ wire_nlll_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & (~ rxd[4])) & rxd[5]) & rxd[6]) & rxd[7]) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0llil = (((~ nlli1l) & nlli1i) & nll0OO),
		n0lliO = ((nlli1l & nlli1i) & nll0OO),
		n0llli = ((((((((((((((((~ wire_nllO_dataout) & (~ wire_nlli_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nliO_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0llll = ((((~ nlli0O) & (~ nlli0l)) & nlli0i) & (~ nlli1O)),
		n0lllO = ((((~ nlli0O) & nlli0l) & nlli0i) & nlli1O),
		n0llOi = (((nlli0O & nlli0l) & nlli0i) & nlli1O),
		n0llOl = (((((~ nlli0O) & (~ nlli0l)) & nlli0i) & nlli1O) | (((nlli0O & (~ nlli0l)) & nlli0i) & nlli1O)),
		n0llOO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlil_dataout)) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & (~ rxd[7])) & (~ (n0OO0l ^ wire_nliO_dataout))) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))),
		n0lO0i = ((((((((nlliOO & (~ nlliOl)) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & nlliiO) & nlliil) & (~ nlliii)),
		n0lO0l = (((((((((~ nlliOO) & (~ nlliOl)) & nlliOi) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & (~ nlliil)) & (~ nlliii)),
		n0lO0O = (((((((((~ nlliOO) & nlliOl) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & nlliil) & (~ nlliii)),
		n0lO1i = ((((((((nlliOO & (~ nlliOl)) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & nlliiO) & nlliil) & nlliii),
		n0lO1l = (((((((((~ nlliOO) & (~ nlliOl)) & nlliOi) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & (~ nlliil)) & nlliii),
		n0lO1O = (((((((((~ nlliOO) & nlliOl) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & nlliil) & nlliii),
		n0lOii = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & (~ rxd[4])) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])) & (~ (n0OO0l ^ wire_nliO_dataout))) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))),
		n0lOil = ((~ rcxpat_chnl_sel[0]) & rcxpat_chnl_sel[1]),
		n0lOiO = (rcxpat_chnl_sel[0] & (~ rcxpat_chnl_sel[1])),
		n0lOli = (n0lOOi & n0lOll),
		n0lOll = (rcxpat_chnl_sel[0] & rcxpat_chnl_sel[1]),
		n0lOlO = (n0lOOl & n0lOOi),
		n0lOOi = (((((((rxd[0] & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])),
		n0lOOl = (n0lOiO | n0lOil),
		n0lOOO = (rxc[0] & (n0O11l & n0O11i)),
		n0O00i = (((((((rxd[0] & (~ rxd[1])) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & (~ rxd[7])),
		n0O00l = (((~ n0O0il) | (~ (wire_nlii_dataout & (~ rxc[0])))) | (~ (n0O00O26 ^ n0O00O25))),
		n0O01i = (((((((rxd[0] & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0O01l = (((((((rxd[0] & (~ rxd[1])) & (~ rxd[2])) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])),
		n0O01O = (((((((rxd[0] & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & (~ rxd[4])) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])),
		n0O0il = ((((((((((((((((~ wire_nliO_dataout) & (~ rxd[0])) & (~ rxd[1])) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0O0iO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & (~ rxd[1])) & (~ rxd[2])) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])),
		n0O0li = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOi_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & rxd[0]) & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & (~ rxd[6])) & (~ rxd[7])) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))),
		n0O0ll = ((((ni0li & ni0iO) & ni0il) & ni0ii) & (~ ni00O)),
		n0O0lO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0O0Oi = ((((((((((((((((~ wire_nlli_dataout) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nliO_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOi_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0O0Ol = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])),
		n0O0OO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & (~ rxd[3])) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))),
		n0O10i = ((((((((((((((((((((((((((wire_n11ll_o[31] | wire_n11ll_o[30]) | wire_n11ll_o[29]) | wire_n11ll_o[28]) | wire_n11ll_o[27]) | wire_n11ll_o[26]) | wire_n11ll_o[25]) | wire_n11ll_o[24]) | wire_n11ll_o[23]) | wire_n11ll_o[22]) | wire_n11ll_o[21]) | wire_n11ll_o[15]) | wire_n11ll_o[14]) | wire_n11ll_o[13]) | wire_n11ll_o[12]) | wire_n11ll_o[11]) | wire_n11ll_o[10]) | wire_n11ll_o[9]) | wire_n11ll_o[8]) | wire_n11ll_o[7]) | wire_n11ll_o[6]) | wire_n11ll_o[5]) | wire_n11ll_o[4]) | wire_n11ll_o[3]) | wire_n11ll_o[2]) | wire_n11ll_o[1]) | wire_n11ll_o[0]),
		n0O11i = ((~ rcxpat_chnl_sel[0]) & (~ rcxpat_chnl_sel[1])),
		n0O11l = (((((((rxd[0] & rxd[1]) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0O11O = (((((((((((((((((((((((((((((wire_n11ll_o[31] | wire_n11ll_o[30]) | wire_n11ll_o[29]) | wire_n11ll_o[28]) | wire_n11ll_o[27]) | wire_n11ll_o[26]) | wire_n11ll_o[25]) | wire_n11ll_o[24]) | wire_n11ll_o[23]) | wire_n11ll_o[22]) | wire_n11ll_o[21]) | wire_n11ll_o[20]) | wire_n11ll_o[19]) | wire_n11ll_o[18]) | wire_n11ll_o[17]) | wire_n11ll_o[16]) | wire_n11ll_o[13]) | wire_n11ll_o[12]) | wire_n11ll_o[11]) | wire_n11ll_o[10]) | wire_n11ll_o[9]) | wire_n11ll_o[8]) | wire_n11ll_o[7]) | wire_n11ll_o[6]) | wire_n11ll_o[5]) | wire_n11ll_o[4]) | wire_n11ll_o[3]) | wire_n11ll_o[2]) | wire_n11ll_o[1]) | wire_n11ll_o[0]),
		n0O1OO = ((~ rxc[0]) | (~ n0O01i)),
		n0Oi0i = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & (~ rxd[3])) & (~ rxd[4])) & rxd[5]) & (~ rxd[6])) & (~ rxd[7])) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nliO_dataout))) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))),
		n0Oi0l = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & (~ rxd[3])) & rxd[4]) & (~ rxd[5])) & rxd[6]) & rxd[7]),
		n0Oi0O = ((((((((((((((((~ wire_nlOi_dataout) & (~ wire_nlll_dataout)) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nliO_dataout))) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nllO_dataout))) & (~ (n0OO0l ^ wire_nlOl_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0Oi1i = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & rxd[3]) & (~ rxd[4])) & (~ rxd[5])) & (~ rxd[6])) & rxd[7]),
		n0Oi1l = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & (~ rxd[4])) & rxd[5]) & rxd[6]) & (~ rxd[7])) & (~ (n0OO0l ^ wire_nlil_dataout))) & (~ (n0OO0l ^ wire_nliO_dataout))) & (~ (n0OO0l ^ wire_nlli_dataout))) & (~ (n0OO0l ^ wire_nlll_dataout))) & (~ (n0OO0l ^ wire_nlOO_dataout))),
		n0Oi1O = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & (~ rxd[3])) & (~ rxd[4])) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])),
		n0Oiii = (n0OilO & n0Oiil),
		n0Oiil = (rcxpat_chnl_sel[0] & rcxpat_chnl_sel[1]),
		n0OiiO = ((((n0Ol1i | n0OiOO) | (~ (n0OiOi22 ^ n0OiOi21))) & n0OilO) & (n0Oili24 ^ n0Oili23)),
		n0OilO = (((((((rxd[0] & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])),
		n0OiOO = ((~ rcxpat_chnl_sel[0]) & rcxpat_chnl_sel[1]),
		n0Ol0i = (((((((rxd[0] & rxd[1]) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]),
		n0Ol0O = 1'b1,
		n0Ol1i = (rcxpat_chnl_sel[0] & (~ rcxpat_chnl_sel[1])),
		n0Ol1l = (rxc[0] & (n0Ol0i & n0Ol1O)),
		n0Ol1O = ((~ rcxpat_chnl_sel[0]) & (~ rcxpat_chnl_sel[1])),
		n0OO0i = (((~ rbist_sel[0]) & rbist_sel[1]) & (n0OliO14 ^ n0OliO13)),
		n0OO0l = (n0OO0O | (rpmadwidth_rx & rpma_doublewidth_rx)),
		n0OO0O = (((rpmadwidth_rx & (~ rpma_doublewidth_rx)) & rdwidth_rx) & (n0OOii6 ^ n0OOii5)),
		n0OO1l = (((~ rbist_sel[0]) & (~ rbist_sel[1])) & (n0Olll12 ^ n0Olll11)),
		n0OO1O = (rbist_sel[0] & (~ rbist_sel[1])),
		selftest_done = wire_nl1l_dataout,
		selftest_err = wire_nl1i_dataout;
endmodule //arriagx_hssi_rx_bist_ver
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 507 mux21 1111 oper_add 22 oper_decoder 14 oper_less_than 20 oper_mux 14 arriagx_hssi_ram20x16_syn 2 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_comp_chnl_top
	( 
	align_status,
	align_status_sync,
	align_status_sync_0,
	align_status_sync_2,
	audi,
	audi_pre,
	clk_1,
	clk_2,
	cmpfifourst,
	comp_curr_st,
	cudi,
	cudi_valid,
	disable_fifo_rd,
	disable_fifo_rd_0,
	disable_fifo_rd_2,
	disable_fifo_wr,
	disable_fifo_wr_0,
	disable_fifo_wr_2,
	dskwclksel,
	fifo_cnt,
	fifo_rd_in_comp_0,
	fifo_rd_in_comp_2,
	fifo_rd_out_comp,
	hard_reset,
	is_lane0,
	ralempty,
	ralfull,
	rclkcmpinsertpad,
	rclkcmppos,
	rclkcmpsq1n,
	rclkcmpsq1p,
	rclkcmpsqmd,
	rcmpfifourst,
	rdenable,
	rdfifo_almost_empty,
	rdfifo_almost_full,
	rdfifo_empty,
	rdfifo_full,
	rdwidth_rx,
	rev_loop_data,
	rgenericfifo,
	rmatchen,
	rrx_pipe_enable,
	rskpsetbased,
	rtruebac2bac,
	rwa_6g_en,
	scan_mode,
	soft_reset,
	sudi,
	sudi_pre,
	sync_status,
	wrenable) /* synthesis synthesis_clearbox=1 */;
	input   align_status;
	output   align_status_sync;
	input   align_status_sync_0;
	input   align_status_sync_2;
	input   [13:0]  audi;
	input   [13:0]  audi_pre;
	input   clk_1;
	input   clk_2;
	input   cmpfifourst;
	output   [1:0]  comp_curr_st;
	output   [31:0]  cudi;
	output   cudi_valid;
	output   disable_fifo_rd;
	input   disable_fifo_rd_0;
	input   disable_fifo_rd_2;
	output   disable_fifo_wr;
	input   disable_fifo_wr_0;
	input   disable_fifo_wr_2;
	input   [1:0]  dskwclksel;
	output   [4:0]  fifo_cnt;
	input   fifo_rd_in_comp_0;
	input   fifo_rd_in_comp_2;
	output   fifo_rd_out_comp;
	input   hard_reset;
	input   is_lane0;
	input   [3:0]  ralempty;
	input   [3:0]  ralfull;
	input   rclkcmpinsertpad;
	input   rclkcmppos;
	input   [19:0]  rclkcmpsq1n;
	input   [19:0]  rclkcmpsq1p;
	input   rclkcmpsqmd;
	input   rcmpfifourst;
	input   rdenable;
	output   rdfifo_almost_empty;
	output   rdfifo_almost_full;
	output   rdfifo_empty;
	output   rdfifo_full;
	input   rdwidth_rx;
	output   [19:0]  rev_loop_data;
	input   rgenericfifo;
	input   rmatchen;
	input   rrx_pipe_enable;
	input   rskpsetbased;
	input   rtruebac2bac;
	input   rwa_6g_en;
	input   scan_mode;
	input   soft_reset;
	input   [27:0]  sudi;
	input   [13:0]  sudi_pre;
	input   sync_status;
	input   wrenable;

	reg	nlill0l55;
	reg	nlill0l56;
	reg	nliOliO53;
	reg	nliOliO54;
	reg	nliOlli51;
	reg	nliOlli52;
	reg	nll000l3;
	reg	nll000l4;
	reg	nll001O5;
	reg	nll001O6;
	reg	nll00li1;
	reg	nll00li2;
	reg	nll010l11;
	reg	nll010l12;
	reg	nll011l13;
	reg	nll011l14;
	reg	nll01ii10;
	reg	nll01ii9;
	reg	nll01li7;
	reg	nll01li8;
	reg	nll10il47;
	reg	nll10il48;
	reg	nll111O49;
	reg	nll111O50;
	reg	nll1i0O43;
	reg	nll1i0O44;
	reg	nll1i1l45;
	reg	nll1i1l46;
	reg	nll1ili41;
	reg	nll1ili42;
	reg	nll1ilO39;
	reg	nll1ilO40;
	reg	nll1iOl37;
	reg	nll1iOl38;
	reg	nll1l1l35;
	reg	nll1l1l36;
	reg	nll1liO33;
	reg	nll1liO34;
	reg	nll1lOi31;
	reg	nll1lOi32;
	reg	nll1lOl29;
	reg	nll1lOl30;
	reg	nll1lOO27;
	reg	nll1lOO28;
	reg	nll1O0O21;
	reg	nll1O0O22;
	reg	nll1O1i25;
	reg	nll1O1i26;
	reg	nll1O1O23;
	reg	nll1O1O24;
	reg	nll1Oil19;
	reg	nll1Oil20;
	reg	nll1Oli17;
	reg	nll1Oli18;
	reg	nll1OOi15;
	reg	nll1OOi16;
	reg	n0OiiO;
	reg	n0Oili;
	reg	n0Oill;
	reg	n0OilO;
	reg	n0OiOi;
	reg	n0OiOl;
	reg	n0OiOO;
	reg	n0Ol0i;
	reg	n0Ol0l;
	reg	n0Ol0O;
	reg	n0Ol1i;
	reg	n0Ol1l;
	reg	n0Ol1O;
	reg	n0Olii;
	reg	n0Olil;
	reg	n0OliO;
	reg	n0Olli;
	reg	n0Olll;
	reg	n0OllO;
	reg	n0OlOi;
	reg	ni11ll;
	reg	ni11Ol;
	reg	ni11Oi_clk_prev;
	wire	wire_ni11Oi_CLRN;
	wire	wire_ni11Oi_PRN;
	reg	n0i;
	reg	nil;
	reg	nii_clk_prev;
	wire	wire_nii_CLRN;
	reg	nii00O;
	reg	nii11i;
	reg	nlO0i1i;
	reg	nlO0l0l;
	reg	n1O;
	reg	nO;
	reg	nl_clk_prev;
	wire	wire_nl_CLRN;
	reg	n1i10l;
	reg	n1i10O;
	reg	n1i1ii;
	reg	niO0li;
	reg	nl0liO;
	reg	nl0lli;
	reg	nl0llO;
	reg	nlOllil;
	wire	wire_nl0lll_PRN;
	reg	n00lii;
	reg	n00lil;
	reg	n0OlOl;
	reg	n0OlOO;
	reg	n0OO0i;
	reg	n0OO0l;
	reg	n0OO0O;
	reg	n0OO1i;
	reg	n0OO1l;
	reg	n0OO1O;
	reg	n0OOii;
	reg	n0OOil;
	reg	n0OOiO;
	reg	n0OOli;
	reg	n0OOll;
	reg	n0OOlO;
	reg	n0OOOi;
	reg	n0OOOl;
	reg	n0OOOO;
	reg	n1000i;
	reg	n1000l;
	reg	n1000O;
	reg	n1001i;
	reg	n1001l;
	reg	n1001O;
	reg	n100ii;
	reg	n101Oi;
	reg	n101Ol;
	reg	n101OO;
	reg	n10i0i;
	reg	n10i0l;
	reg	n10i0O;
	reg	n10i1O;
	reg	n10iii;
	reg	n10iil;
	reg	n10ili;
	reg	n10ill;
	reg	n10ilO;
	reg	n10iOi;
	reg	n10liO;
	reg	n10O0i;
	reg	n10O0l;
	reg	n10O1O;
	reg	n11OiO;
	reg	n1ii0l;
	reg	n1l10i;
	reg	n1l10l;
	reg	n1l10O;
	reg	n1l11i;
	reg	n1l11l;
	reg	n1l11O;
	reg	n1l1ii;
	reg	n1O00O;
	reg	n1O0il;
	reg	n1O0iO;
	reg	n1O0li;
	reg	n1O0ll;
	reg	n1O0lO;
	reg	n1O0Oi;
	reg	n1O1Oi;
	reg	ni0O0O;
	reg	ni0Oii;
	reg	ni0Oil;
	reg	ni0OiO;
	reg	ni0Oli;
	reg	ni0Oll;
	reg	ni0OlO;
	reg	ni0OOi;
	reg	ni0OOl;
	reg	ni0OOO;
	reg	ni101i;
	reg	ni101l;
	reg	ni110i;
	reg	ni110l;
	reg	ni110O;
	reg	ni111i;
	reg	ni111l;
	reg	ni111O;
	reg	ni11ii;
	reg	ni11il;
	reg	ni11iO;
	reg	ni11li;
	reg	ni11lO;
	reg	ni11OO;
	reg	nii00i;
	reg	nii01i;
	reg	nii01l;
	reg	nii01O;
	reg	nii0ii;
	reg	nii0il;
	reg	nii0iO;
	reg	nii0li;
	reg	nii0ll;
	reg	nii0lO;
	reg	nii0Oi;
	reg	nii0Ol;
	reg	nii0OO;
	reg	nii10i;
	reg	nii10l;
	reg	nii10O;
	reg	nii11l;
	reg	nii11O;
	reg	nii1ii;
	reg	nii1il;
	reg	nii1iO;
	reg	nii1li;
	reg	nii1ll;
	reg	nii1lO;
	reg	nii1Oi;
	reg	nii1Ol;
	reg	nii1OO;
	reg	niii0i;
	reg	niii0l;
	reg	niii0O;
	reg	niii1i;
	reg	niii1l;
	reg	niii1O;
	reg	niiiii;
	reg	niiiil;
	reg	niiiiO;
	reg	niiili;
	reg	nl000i;
	reg	nl000l;
	reg	nl000O;
	reg	nl001i;
	reg	nl001l;
	reg	nl00ii;
	reg	nl011i;
	reg	nl011l;
	reg	nl011O;
	reg	nl01Ol;
	reg	nl01OO;
	reg	nl0i1l;
	reg	nl0iiO;
	reg	nl0ili;
	reg	nl0ill;
	reg	nl1l0l;
	reg	nl1OiO;
	reg	nl1Oli;
	reg	nl1Oll;
	reg	nl1OlO;
	reg	nl1OOi;
	reg	nl1OOl;
	reg	nl1OOO;
	reg	nliOlO;
	reg	nll00ll;
	reg	nll00lO;
	reg	nll10l;
	reg	nll11l;
	reg	nllO0OO;
	reg	nllOi0i;
	reg	nllOi0l;
	reg	nllOi0O;
	reg	nllOi1i;
	reg	nllOi1l;
	reg	nllOi1O;
	reg	nllOiii;
	reg	nllOiil;
	reg	nllOiiO;
	reg	nllOili;
	reg	nllOilO;
	reg	nllOiOO;
	reg	nllOl1i;
	reg	nllOl1l;
	reg	nlO000O;
	reg	nlO00ii;
	reg	nlO00il;
	reg	nlO00iO;
	reg	nlO00li;
	reg	nlO00ll;
	reg	nlO00lO;
	reg	nlO00Oi;
	reg	nlO00Ol;
	reg	nlO00OO;
	reg	nlO0i0i;
	reg	nlO0i0l;
	reg	nlO0i0O;
	reg	nlO0i1l;
	reg	nlO0i1O;
	reg	nlO0iii;
	reg	nlO0iil;
	reg	nlO0iiO;
	reg	nlO0ili;
	reg	nlO0ill;
	reg	nlO0ilO;
	reg	nlO0iOi;
	reg	nlO0iOl;
	reg	nlO0iOO;
	reg	nlO0l0i;
	reg	nlO0l0O;
	reg	nlO0l1i;
	reg	nlO0l1l;
	reg	nlO0l1O;
	reg	nlO0lii;
	reg	nlO0lil;
	reg	nlO0liO;
	reg	nlO0lli;
	reg	nlO0lll;
	reg	nlO0llO;
	reg	nlO0lOi;
	reg	nlO0lOl;
	reg	nlO0lOO;
	reg	nlO0O0i;
	reg	nlO0O0l;
	reg	nlO0O0O;
	reg	nlO0O1i;
	reg	nlO0O1l;
	reg	nlO0O1O;
	reg	nlO0Oii;
	reg	nlO0Oil;
	reg	nlO0OiO;
	wire	wire_nll10i_CLRN;
	reg	nlllOiO;
	reg	nlllOli;
	reg	nlllOll;
	reg	nlllOlO;
	reg	nlllOOi;
	reg	nlllOOl;
	reg	nlllOOO;
	reg	nllO00i;
	reg	nllO00l;
	reg	nllO00O;
	reg	nllO01i;
	reg	nllO01l;
	reg	nllO01O;
	reg	nllO0ii;
	reg	nllO0il;
	reg	nllO0iO;
	reg	nllO0li;
	reg	nllO0ll;
	reg	nllO0lO;
	reg	nllO0Oi;
	reg	nllO0Ol;
	reg	nllO10i;
	reg	nllO10l;
	reg	nllO10O;
	reg	nllO11i;
	reg	nllO11l;
	reg	nllO11O;
	reg	nllO1ii;
	reg	nllO1il;
	reg	nllO1iO;
	reg	nllO1li;
	reg	nllO1ll;
	reg	nllO1lO;
	reg	nllO1Oi;
	reg	nllO1Ol;
	reg	nllO1OO;
	reg	nllOill;
	reg	nllOiOl;
	reg	nllOiOi_clk_prev;
	wire	wire_nllOiOi_PRN;
	reg	n00liO;
	reg	n10iOl;
	reg	n10O0O;
	reg	n110il;
	reg	n110iO;
	reg	n11O0l;
	reg	n11O0O;
	reg	n11Oii;
	reg	n11Oil;
	reg	n1i11i;
	reg	n1i11l;
	reg	n1i1il;
	reg	n1i1iO;
	reg	n1i1li;
	reg	n1ii0i;
	reg	n1ii1i;
	reg	n1ii1l;
	reg	n1ii1O;
	reg	n1l0lO;
	reg	n1l0Oi;
	reg	n1l0Ol;
	reg	n1l0OO;
	reg	n1l1il;
	reg	n1li1i;
	reg	n1li1l;
	reg	n1O0Ol;
	reg	n1O1lO;
	reg	n1Olil;
	reg	n1Olll;
	reg	n1OllO;
	reg	n1OlOi;
	reg	n1OlOl;
	reg	n1OlOO;
	reg	niiill;
	reg	niO00i;
	reg	niO00l;
	reg	niO00O;
	reg	niO01i;
	reg	niO01l;
	reg	niO01O;
	reg	niO0ii;
	reg	niO0il;
	reg	niO0iO;
	reg	niO0ll;
	reg	niO0lO;
	reg	niO0Oi;
	reg	niO0Ol;
	reg	niO0OO;
	reg	niO1ll;
	reg	niO1lO;
	reg	niO1Oi;
	reg	niO1Ol;
	reg	niO1OO;
	reg	niOi0i;
	reg	niOi0l;
	reg	niOi0O;
	reg	niOi1i;
	reg	niOi1l;
	reg	niOi1O;
	reg	niOiii;
	reg	niOiil;
	reg	niOiiO;
	reg	niOili;
	reg	niOill;
	reg	niOilO;
	reg	niOiOi;
	reg	niOiOl;
	reg	niOiOO;
	reg	nl00il;
	reg	nl0ilO;
	reg	nl0l0l;
	reg	nl0l0O;
	reg	nl0lOi;
	reg	nl0lOl;
	reg	nl0lOO;
	reg	nl1iii;
	reg	nl1iil;
	reg	nl1l0i;
	reg	nl1l1i;
	reg	nl1l1l;
	reg	nl1l1O;
	reg	nli10O;
	reg	nli1ii;
	reg	nli1il;
	reg	nli1iO;
	reg	nli1li;
	reg	nliiiO;
	reg	nliili;
	reg	nliill;
	reg	nliilO;
	reg	nliiOi;
	reg	nliOll;
	reg	nll00i;
	reg	nll00l;
	reg	nll00Oi;
	reg	nll10O;
	reg	nll1Ol;
	reg	nll1OO;
	reg	nlO00i;
	reg	nlO00l;
	reg	nlO00O;
	reg	nlO01i;
	reg	nlO01l;
	reg	nlO01O;
	reg	nlO0ii;
	reg	nlO0il;
	reg	nlO0iO;
	reg	nlO0li;
	reg	nlO0ll;
	reg	nlO0lO;
	reg	nlO0Oi;
	reg	nlO0Ol;
	reg	nlO0Oli;
	reg	nlO0OO;
	reg	nlO1li;
	reg	nlO1ll;
	reg	nlO1lO;
	reg	nlO1Oi;
	reg	nlO1Ol;
	reg	nlO1OO;
	reg	nlOi0i;
	reg	nlOi0l;
	reg	nlOi0O;
	reg	nlOi1i;
	reg	nlOi1l;
	reg	nlOi1O;
	reg	nlOill;
	reg	nlOilO;
	reg	nlOliiO;
	reg	nlOlili;
	reg	nlOlill;
	reg	nlOlilO;
	reg	nlOliOi;
	reg	nlOliOl;
	reg	nlOliOO;
	reg	nlOll0i;
	reg	nlOll0l;
	reg	nlOll0O;
	reg	nlOll1i;
	reg	nlOll1l;
	reg	nlOll1O;
	reg	nlOllii;
	reg	nlOlliO;
	reg	nlOllli;
	reg	nlOllll;
	reg	nlOlllO;
	reg	nlOllOi;
	reg	nlOllOl;
	reg	nlOllOO;
	reg	nlOlO0i;
	reg	nlOlO0l;
	reg	nlOlO0O;
	reg	nlOlO1i;
	reg	nlOlO1l;
	reg	nlOlO1O;
	reg	nlOlOii;
	reg	nlOlOil;
	reg	nlOlOiO;
	reg	nlOlOli;
	reg	nlOlOll;
	reg	nlOlOlO;
	reg	nlOlOO;
	reg	nlOlOOi;
	reg	nlOO1l;
	wire	wire_nlOO1i_CLRN;
	wire	wire_n0000l_dataout;
	wire	wire_n0010i_dataout;
	wire	wire_n0010l_dataout;
	wire	wire_n0011i_dataout;
	wire	wire_n0011l_dataout;
	wire	wire_n0011O_dataout;
	wire	wire_n001lO_dataout;
	wire	wire_n00i_dataout;
	wire	wire_n00i0i_dataout;
	wire	wire_n00i0l_dataout;
	wire	wire_n00i0O_dataout;
	wire	wire_n00iii_dataout;
	wire	wire_n00iil_dataout;
	wire	wire_n00iiO_dataout;
	wire	wire_n00ili_dataout;
	wire	wire_n00ill_dataout;
	wire	wire_n00ilO_dataout;
	wire	wire_n00iOi_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00lli_dataout;
	wire	wire_n00lll_dataout;
	wire	wire_n00llO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n0100i_dataout;
	wire	wire_n0100l_dataout;
	wire	wire_n0100O_dataout;
	wire	wire_n0101i_dataout;
	wire	wire_n0101l_dataout;
	wire	wire_n0101O_dataout;
	wire	wire_n010ii_dataout;
	wire	wire_n010il_dataout;
	wire	wire_n010ll_dataout;
	wire	wire_n010lO_dataout;
	wire	wire_n010Oi_dataout;
	wire	wire_n010Ol_dataout;
	wire	wire_n0111O_dataout;
	wire	wire_n011li_dataout;
	wire	wire_n011ll_dataout;
	wire	wire_n011lO_dataout;
	wire	wire_n011Oi_dataout;
	wire	wire_n011Ol_dataout;
	wire	wire_n011OO_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01i0i_dataout;
	wire	wire_n01i0l_dataout;
	wire	wire_n01i0O_dataout;
	wire	wire_n01iii_dataout;
	wire	wire_n01iil_dataout;
	wire	wire_n01iiO_dataout;
	wire	wire_n01ili_dataout;
	wire	wire_n01ill_dataout;
	wire	wire_n01ilO_dataout;
	wire	wire_n01iOi_dataout;
	wire	wire_n01iOl_dataout;
	wire	wire_n01iOO_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01l0i_dataout;
	wire	wire_n01l0l_dataout;
	wire	wire_n01l0O_dataout;
	wire	wire_n01l1i_dataout;
	wire	wire_n01l1l_dataout;
	wire	wire_n01l1O_dataout;
	wire	wire_n01lii_dataout;
	wire	wire_n01lil_dataout;
	wire	wire_n01liO_dataout;
	wire	wire_n01lli_dataout;
	wire	wire_n01lll_dataout;
	wire	wire_n01llO_dataout;
	wire	wire_n01lOi_dataout;
	wire	wire_n01lOl_dataout;
	wire	wire_n01lOO_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n01O0i_dataout;
	wire	wire_n01O0l_dataout;
	wire	wire_n01O0O_dataout;
	wire	wire_n01O1i_dataout;
	wire	wire_n01O1l_dataout;
	wire	wire_n01O1O_dataout;
	wire	wire_n01Oii_dataout;
	wire	wire_n01Oil_dataout;
	wire	wire_n01OiO_dataout;
	wire	wire_n01Oli_dataout;
	wire	wire_n01Oll_dataout;
	wire	wire_n01OlO_dataout;
	wire	wire_n01OOi_dataout;
	wire	wire_n01OOl_dataout;
	wire	wire_n01OOO_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n100il_dataout;
	wire	wire_n100iO_dataout;
	wire	wire_n100li_dataout;
	wire	wire_n100ll_dataout;
	wire	wire_n100lO_dataout;
	wire	wire_n100Oi_dataout;
	wire	wire_n100Ol_dataout;
	wire	wire_n100OO_dataout;
	wire	wire_n1010i_dataout;
	wire	wire_n1011i_dataout;
	wire	wire_n1011l_dataout;
	wire	wire_n1011O_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10i1i_dataout;
	wire	wire_n10i1l_dataout;
	wire	wire_n10iOO_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10l0i_dataout;
	wire	wire_n10l1i_dataout;
	wire	wire_n10l1l_dataout;
	wire	wire_n10l1O_dataout;
	wire	wire_n10lli_dataout;
	wire	wire_n10lll_dataout;
	wire	wire_n10lOi_dataout;
	wire	wire_n10lOl_dataout;
	wire	wire_n10lOO_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n10Oii_dataout;
	wire	wire_n10Oil_dataout;
	wire	wire_n10OOi_dataout;
	wire	wire_n1100i_dataout;
	wire	wire_n1100l_dataout;
	wire	wire_n1100O_dataout;
	wire	wire_n1101i_dataout;
	wire	wire_n1101l_dataout;
	wire	wire_n1101O_dataout;
	wire	wire_n110ii_dataout;
	wire	wire_n110ll_dataout;
	wire	wire_n1111i_dataout;
	wire	wire_n1111l_dataout;
	wire	wire_n1111O_dataout;
	wire	wire_n111ii_dataout;
	wire	wire_n111il_dataout;
	wire	wire_n111iO_dataout;
	wire	wire_n111li_dataout;
	wire	wire_n111ll_dataout;
	wire	wire_n111Oi_dataout;
	wire	wire_n111Ol_dataout;
	wire	wire_n111OO_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n11Oli_dataout;
	wire	wire_n11Oll_dataout;
	wire	wire_n11OlO_dataout;
	wire	wire_n11OOi_dataout;
	wire	wire_n11OOl_dataout;
	wire	wire_n11OOO_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1i00l_dataout;
	wire	wire_n1i01i_dataout;
	wire	wire_n1i01l_dataout;
	wire	wire_n1i0iO_dataout;
	wire	wire_n1i0lO_dataout;
	wire	wire_n1i1ll_dataout;
	wire	wire_n1i1lO_dataout;
	wire	wire_n1i1Oi_dataout;
	wire	wire_n1i1Ol_dataout;
	wire	wire_n1i1OO_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1ii0O_dataout;
	wire	wire_n1iiii_dataout;
	wire	wire_n1iiil_dataout;
	wire	wire_n1iiiO_dataout;
	wire	wire_n1iili_dataout;
	wire	wire_n1iill_dataout;
	wire	wire_n1iilO_dataout;
	wire	wire_n1iiOi_dataout;
	wire	wire_n1iiOl_dataout;
	wire	wire_n1iiOO_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1il0i_dataout;
	wire	wire_n1il0l_dataout;
	wire	wire_n1il0O_dataout;
	wire	wire_n1il1l_dataout;
	wire	wire_n1il1O_dataout;
	wire	wire_n1illl_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1l00i_dataout;
	wire	wire_n1l00l_dataout;
	wire	wire_n1l00O_dataout;
	wire	wire_n1l01i_dataout;
	wire	wire_n1l01l_dataout;
	wire	wire_n1l01O_dataout;
	wire	wire_n1l0ii_dataout;
	wire	wire_n1l0il_dataout;
	wire	wire_n1l1iO_dataout;
	wire	wire_n1l1li_dataout;
	wire	wire_n1l1ll_dataout;
	wire	wire_n1l1lO_dataout;
	wire	wire_n1l1Oi_dataout;
	wire	wire_n1l1Ol_dataout;
	wire	wire_n1l1OO_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1li0i_dataout;
	wire	wire_n1li0l_dataout;
	wire	wire_n1li0O_dataout;
	wire	wire_n1li1O_dataout;
	wire	wire_n1liii_dataout;
	wire	wire_n1liil_dataout;
	wire	wire_n1liiO_dataout;
	wire	wire_n1lili_dataout;
	wire	wire_n1lill_dataout;
	wire	wire_n1lilO_dataout;
	wire	wire_n1liOi_dataout;
	wire	wire_n1liOl_dataout;
	wire	wire_n1liOO_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1ll0i_dataout;
	wire	wire_n1ll0l_dataout;
	wire	wire_n1ll0O_dataout;
	wire	wire_n1ll1i_dataout;
	wire	wire_n1ll1l_dataout;
	wire	wire_n1ll1O_dataout;
	wire	wire_n1llii_dataout;
	wire	wire_n1llil_dataout;
	wire	wire_n1lliO_dataout;
	wire	wire_n1llli_dataout;
	wire	wire_n1llll_dataout;
	wire	wire_n1lllO_dataout;
	wire	wire_n1llOi_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1O0ii_dataout;
	wire	wire_n1O0OO_dataout;
	wire	wire_n1O1Ol_dataout;
	wire	wire_n1O1OO_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Oi0i_dataout;
	wire	wire_n1Oi0l_dataout;
	wire	wire_n1Oi0O_dataout;
	wire	wire_n1Oi1i_dataout;
	wire	wire_n1Oi1l_dataout;
	wire	wire_n1Oi1O_dataout;
	wire	wire_n1Oiii_dataout;
	wire	wire_n1Oiil_dataout;
	wire	wire_n1OiiO_dataout;
	wire	wire_n1Oili_dataout;
	wire	wire_n1Oill_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1Ol0i_dataout;
	wire	wire_n1Ol0l_dataout;
	wire	wire_n1Ol1l_dataout;
	wire	wire_n1Ol1O_dataout;
	wire	wire_n1OliO_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_n1OO0l_dataout;
	wire	wire_n1OO1i_dataout;
	wire	wire_n1OO1O_dataout;
	wire	wire_n1OOiO_dataout;
	wire	wire_ni_dataout;
	wire	wire_ni000i_dataout;
	wire	wire_ni000l_dataout;
	wire	wire_ni000O_dataout;
	wire	wire_ni001i_dataout;
	wire	wire_ni001l_dataout;
	wire	wire_ni001O_dataout;
	wire	wire_ni00ii_dataout;
	wire	wire_ni00il_dataout;
	wire	wire_ni00iO_dataout;
	wire	wire_ni00li_dataout;
	wire	wire_ni00ll_dataout;
	wire	wire_ni00lO_dataout;
	wire	wire_ni00Oi_dataout;
	wire	wire_ni00Ol_dataout;
	wire	wire_ni00OO_dataout;
	wire	wire_ni010i_dataout;
	wire	wire_ni010l_dataout;
	wire	wire_ni010O_dataout;
	wire	wire_ni011i_dataout;
	wire	wire_ni011l_dataout;
	wire	wire_ni011O_dataout;
	wire	wire_ni01ii_dataout;
	wire	wire_ni01il_dataout;
	wire	wire_ni01iO_dataout;
	wire	wire_ni01li_dataout;
	wire	wire_ni01ll_dataout;
	wire	wire_ni01lO_dataout;
	wire	wire_ni01Oi_dataout;
	wire	wire_ni01Ol_dataout;
	wire	wire_ni01OO_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0i0i_dataout;
	wire	wire_ni0i0l_dataout;
	wire	wire_ni0i0O_dataout;
	wire	wire_ni0i1i_dataout;
	wire	wire_ni0i1l_dataout;
	wire	wire_ni0i1O_dataout;
	wire	wire_ni0iii_dataout;
	wire	wire_ni0iil_dataout;
	wire	wire_ni0iiO_dataout;
	wire	wire_ni0ili_dataout;
	wire	wire_ni0ill_dataout;
	wire	wire_ni0ilO_dataout;
	wire	wire_ni0iOi_dataout;
	wire	wire_ni0iOl_dataout;
	wire	wire_ni0iOO_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0l0i_dataout;
	wire	wire_ni0l0l_dataout;
	wire	wire_ni0l0O_dataout;
	wire	wire_ni0l1i_dataout;
	wire	wire_ni0l1l_dataout;
	wire	wire_ni0l1O_dataout;
	wire	wire_ni0lii_dataout;
	wire	wire_ni0lil_dataout;
	wire	wire_ni0liO_dataout;
	wire	wire_ni0lli_dataout;
	wire	wire_ni0lll_dataout;
	wire	wire_ni0llO_dataout;
	wire	wire_ni0lOi_dataout;
	wire	wire_ni0lOl_dataout;
	wire	wire_ni0lOO_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni0O0i_dataout;
	wire	wire_ni0O0l_dataout;
	wire	wire_ni100i_dataout;
	wire	wire_ni100l_dataout;
	wire	wire_ni100O_dataout;
	wire	wire_ni101O_dataout;
	wire	wire_ni10ii_dataout;
	wire	wire_ni10il_dataout;
	wire	wire_ni10iO_dataout;
	wire	wire_ni10li_dataout;
	wire	wire_ni10ll_dataout;
	wire	wire_ni10lO_dataout;
	wire	wire_ni10Oi_dataout;
	wire	wire_ni10Ol_dataout;
	wire	wire_ni10OO_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1i0i_dataout;
	wire	wire_ni1i0l_dataout;
	wire	wire_ni1i0O_dataout;
	wire	wire_ni1i1i_dataout;
	wire	wire_ni1i1l_dataout;
	wire	wire_ni1i1O_dataout;
	wire	wire_ni1iii_dataout;
	wire	wire_ni1iil_dataout;
	wire	wire_ni1iiO_dataout;
	wire	wire_ni1ili_dataout;
	wire	wire_ni1ill_dataout;
	wire	wire_ni1ilO_dataout;
	wire	wire_ni1iOi_dataout;
	wire	wire_ni1iOl_dataout;
	wire	wire_ni1iOO_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1l0i_dataout;
	wire	wire_ni1l0l_dataout;
	wire	wire_ni1l0O_dataout;
	wire	wire_ni1l1i_dataout;
	wire	wire_ni1l1l_dataout;
	wire	wire_ni1l1O_dataout;
	wire	wire_ni1lii_dataout;
	wire	wire_ni1lil_dataout;
	wire	wire_ni1liO_dataout;
	wire	wire_ni1lli_dataout;
	wire	wire_ni1lll_dataout;
	wire	wire_ni1llO_dataout;
	wire	wire_ni1lOi_dataout;
	wire	wire_ni1lOl_dataout;
	wire	wire_ni1lOO_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_ni1O0i_dataout;
	wire	wire_ni1O0l_dataout;
	wire	wire_ni1O0O_dataout;
	wire	wire_ni1O1i_dataout;
	wire	wire_ni1O1l_dataout;
	wire	wire_ni1O1O_dataout;
	wire	wire_ni1Oii_dataout;
	wire	wire_ni1Oil_dataout;
	wire	wire_ni1OiO_dataout;
	wire	wire_ni1Oli_dataout;
	wire	wire_ni1Oll_dataout;
	wire	wire_ni1OlO_dataout;
	wire	wire_ni1OOi_dataout;
	wire	wire_ni1OOl_dataout;
	wire	wire_ni1OOO_dataout;
	wire	wire_niii_dataout;
	wire	wire_niiilO_dataout;
	wire	wire_niiiOi_dataout;
	wire	wire_niiiOl_dataout;
	wire	wire_niiiOO_dataout;
	wire	wire_niil_dataout;
	wire	wire_niil0i_dataout;
	wire	wire_niil0l_dataout;
	wire	wire_niil0O_dataout;
	wire	wire_niil1i_dataout;
	wire	wire_niil1l_dataout;
	wire	wire_niil1O_dataout;
	wire	wire_niilii_dataout;
	wire	wire_niilil_dataout;
	wire	wire_niiliO_dataout;
	wire	wire_niilli_dataout;
	wire	wire_niilll_dataout;
	wire	wire_niillO_dataout;
	wire	wire_niilOi_dataout;
	wire	wire_niilOl_dataout;
	wire	wire_niilOO_dataout;
	wire	wire_niiO_dataout;
	wire	wire_niiO0i_dataout;
	wire	wire_niiO0l_dataout;
	wire	wire_niiO0O_dataout;
	wire	wire_niiO1i_dataout;
	wire	wire_niiO1l_dataout;
	wire	wire_niiO1O_dataout;
	wire	wire_niiOii_dataout;
	wire	wire_niiOil_dataout;
	wire	wire_niiOiO_dataout;
	wire	wire_niiOli_dataout;
	wire	wire_niiOll_dataout;
	wire	wire_niiOlO_dataout;
	wire	wire_niiOOi_dataout;
	wire	wire_niiOOl_dataout;
	wire	wire_niiOOO_dataout;
	wire	wire_nil00i_dataout;
	wire	wire_nil00l_dataout;
	wire	wire_nil00O_dataout;
	wire	wire_nil01i_dataout;
	wire	wire_nil01l_dataout;
	wire	wire_nil01O_dataout;
	wire	wire_nil0ii_dataout;
	wire	wire_nil0il_dataout;
	wire	wire_nil0iO_dataout;
	wire	wire_nil0li_dataout;
	wire	wire_nil0ll_dataout;
	wire	wire_nil0lO_dataout;
	wire	wire_nil0Oi_dataout;
	wire	wire_nil0Ol_dataout;
	wire	wire_nil0OO_dataout;
	wire	wire_nil10i_dataout;
	wire	wire_nil10l_dataout;
	wire	wire_nil10O_dataout;
	wire	wire_nil11i_dataout;
	wire	wire_nil11l_dataout;
	wire	wire_nil11O_dataout;
	wire	wire_nil1ii_dataout;
	wire	wire_nil1il_dataout;
	wire	wire_nil1iO_dataout;
	wire	wire_nil1li_dataout;
	wire	wire_nil1ll_dataout;
	wire	wire_nil1lO_dataout;
	wire	wire_nil1Oi_dataout;
	wire	wire_nil1Ol_dataout;
	wire	wire_nil1OO_dataout;
	wire	wire_nili_dataout;
	wire	wire_nili0i_dataout;
	wire	wire_nili0l_dataout;
	wire	wire_nili0O_dataout;
	wire	wire_nili1i_dataout;
	wire	wire_nili1l_dataout;
	wire	wire_nili1O_dataout;
	wire	wire_niliii_dataout;
	wire	wire_niliil_dataout;
	wire	wire_niliiO_dataout;
	wire	wire_nilili_dataout;
	wire	wire_nilill_dataout;
	wire	wire_nililO_dataout;
	wire	wire_niliOi_dataout;
	wire	wire_niliOl_dataout;
	wire	wire_niliOO_dataout;
	wire	wire_nill_dataout;
	wire	wire_nill0i_dataout;
	wire	wire_nill0l_dataout;
	wire	wire_nill0O_dataout;
	wire	wire_nill1i_dataout;
	wire	wire_nill1l_dataout;
	wire	wire_nill1O_dataout;
	wire	wire_nillii_dataout;
	wire	wire_nillil_dataout;
	wire	wire_nilliO_dataout;
	wire	wire_nilll_dataout;
	wire	wire_nillli_dataout;
	wire	wire_nillll_dataout;
	wire	wire_nilllO_dataout;
	wire	wire_nillO_dataout;
	wire	wire_nillOi_dataout;
	wire	wire_nillOl_dataout;
	wire	wire_nillOO_dataout;
	wire	wire_nilO_dataout;
	wire	wire_nilO0i_dataout;
	wire	wire_nilO0l_dataout;
	wire	wire_nilO0O_dataout;
	wire	wire_nilO1i_dataout;
	wire	wire_nilO1l_dataout;
	wire	wire_nilO1O_dataout;
	wire	wire_nilOi_dataout;
	wire	wire_nilOl_dataout;
	wire	wire_nilOO_dataout;
	wire	wire_nilOOO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niO0i_dataout;
	wire	wire_niO0l_dataout;
	wire	wire_niO0O_dataout;
	wire	wire_niO10i_dataout;
	wire	wire_niO11i_dataout;
	wire	wire_niO11l_dataout;
	wire	wire_niO11O_dataout;
	wire	wire_niO1i_dataout;
	wire	wire_niO1l_dataout;
	wire	wire_niO1O_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOii_dataout;
	wire	wire_niOil_dataout;
	wire	wire_niOiO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOl0i_dataout;
	wire	wire_niOl0l_dataout;
	wire	wire_niOl0O_dataout;
	wire	wire_niOl1i_dataout;
	wire	wire_niOl1l_dataout;
	wire	wire_niOl1O_dataout;
	wire	wire_niOli_dataout;
	wire	wire_niOlii_dataout;
	wire	wire_niOlil_dataout;
	wire	wire_niOliO_dataout;
	wire	wire_niOll_dataout;
	wire	wire_niOlli_dataout;
	wire	wire_niOlll_dataout;
	wire	wire_niOllO_dataout;
	wire	wire_niOlO_dataout;
	wire	wire_niOlOi_dataout;
	wire	wire_niOlOl_dataout;
	wire	wire_niOlOO_dataout;
	wire	wire_niOO_dataout;
	wire	wire_niOO0i_dataout;
	wire	wire_niOO0l_dataout;
	wire	wire_niOO0O_dataout;
	wire	wire_niOO1i_dataout;
	wire	wire_niOO1l_dataout;
	wire	wire_niOO1O_dataout;
	wire	wire_niOOi_dataout;
	wire	wire_niOOii_dataout;
	wire	wire_niOOil_dataout;
	wire	wire_niOOiO_dataout;
	wire	wire_niOOl_dataout;
	wire	wire_niOOli_dataout;
	wire	wire_niOOll_dataout;
	wire	wire_niOOlO_dataout;
	wire	wire_niOOO_dataout;
	wire	wire_niOOOi_dataout;
	wire	wire_niOOOl_dataout;
	wire	wire_niOOOO_dataout;
	wire	wire_nl00i_dataout;
	wire	wire_nl00iO_dataout;
	wire	wire_nl00l_dataout;
	wire	wire_nl00li_dataout;
	wire	wire_nl00ll_dataout;
	wire	wire_nl00lO_dataout;
	wire	wire_nl00O_dataout;
	wire	wire_nl00Oi_dataout;
	wire	wire_nl010i_dataout;
	wire	wire_nl010l_dataout;
	wire	wire_nl010O_dataout;
	wire	wire_nl01i_dataout;
	wire	wire_nl01ii_dataout;
	wire	wire_nl01il_dataout;
	wire	wire_nl01iO_dataout;
	wire	wire_nl01l_dataout;
	wire	wire_nl01li_dataout;
	wire	wire_nl01ll_dataout;
	wire	wire_nl01lO_dataout;
	wire	wire_nl01O_dataout;
	wire	wire_nl01Oi_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0i0i_dataout;
	wire	wire_nl0i0O_dataout;
	wire	wire_nl0i1O_dataout;
	wire	wire_nl0ii_dataout;
	wire	wire_nl0il_dataout;
	wire	wire_nl0iO_dataout;
	wire	wire_nl0iOi_dataout;
	wire	wire_nl0iOl_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0l1l_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0ll_dataout;
	wire	wire_nl0lO_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl0O0i_dataout;
	wire	wire_nl0O0l_dataout;
	wire	wire_nl0O0O_dataout;
	wire	wire_nl0O1i_dataout;
	wire	wire_nl0O1l_dataout;
	wire	wire_nl0O1O_dataout;
	wire	wire_nl0Oi_dataout;
	wire	wire_nl0Oii_dataout;
	wire	wire_nl0Ol_dataout;
	wire	wire_nl0Oli_dataout;
	wire	wire_nl0OO_dataout;
	wire	wire_nl0OOl_dataout;
	wire	wire_nl100i_dataout;
	wire	wire_nl100l_dataout;
	wire	wire_nl100O_dataout;
	wire	wire_nl101i_dataout;
	wire	wire_nl101l_dataout;
	wire	wire_nl101O_dataout;
	wire	wire_nl10i_dataout;
	wire	wire_nl10ii_dataout;
	wire	wire_nl10il_dataout;
	wire	wire_nl10iO_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl10li_dataout;
	wire	wire_nl10lO_dataout;
	wire	wire_nl10O_dataout;
	wire	wire_nl10Oi_dataout;
	wire	wire_nl10Ol_dataout;
	wire	wire_nl10OO_dataout;
	wire	wire_nl110i_dataout;
	wire	wire_nl110l_dataout;
	wire	wire_nl110O_dataout;
	wire	wire_nl111i_dataout;
	wire	wire_nl111l_dataout;
	wire	wire_nl111O_dataout;
	wire	wire_nl11i_dataout;
	wire	wire_nl11ii_dataout;
	wire	wire_nl11il_dataout;
	wire	wire_nl11iO_dataout;
	wire	wire_nl11l_dataout;
	wire	wire_nl11li_dataout;
	wire	wire_nl11ll_dataout;
	wire	wire_nl11lO_dataout;
	wire	wire_nl11O_dataout;
	wire	wire_nl11Oi_dataout;
	wire	wire_nl11Ol_dataout;
	wire	wire_nl11OO_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1i0i_dataout;
	wire	wire_nl1i0l_dataout;
	wire	wire_nl1i0O_dataout;
	wire	wire_nl1i1i_dataout;
	wire	wire_nl1i1l_dataout;
	wire	wire_nl1i1O_dataout;
	wire	wire_nl1ii_dataout;
	wire	wire_nl1il_dataout;
	wire	wire_nl1iO_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1l0O_dataout;
	wire	wire_nl1li_dataout;
	wire	wire_nl1lii_dataout;
	wire	wire_nl1lil_dataout;
	wire	wire_nl1liO_dataout;
	wire	wire_nl1ll_dataout;
	wire	wire_nl1lli_dataout;
	wire	wire_nl1lll_dataout;
	wire	wire_nl1llO_dataout;
	wire	wire_nl1lO_dataout;
	wire	wire_nl1lOi_dataout;
	wire	wire_nl1lOl_dataout;
	wire	wire_nl1lOO_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nl1Oi_dataout;
	wire	wire_nl1Ol_dataout;
	wire	wire_nl1OO_dataout;
	wire	wire_nli_dataout;
	wire	wire_nli00i_dataout;
	wire	wire_nli00l_dataout;
	wire	wire_nli01i_dataout;
	wire	wire_nli01l_dataout;
	wire	wire_nli01O_dataout;
	wire	wire_nli0i_dataout;
	wire	wire_nli0ii_dataout;
	wire	wire_nli0il_dataout;
	wire	wire_nli0iO_dataout;
	wire	wire_nli0l_dataout;
	wire	wire_nli0li_dataout;
	wire	wire_nli0ll_dataout;
	wire	wire_nli0O_dataout;
	wire	wire_nli11l_dataout;
	wire	wire_nli1i_dataout;
	wire	wire_nli1l_dataout;
	wire	wire_nli1ll_dataout;
	wire	wire_nli1lO_dataout;
	wire	wire_nli1O_dataout;
	wire	wire_nli1Oi_dataout;
	wire	wire_nli1Ol_dataout;
	wire	wire_nli1OO_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nliii_dataout;
	wire	wire_nliil_dataout;
	wire	wire_nliiO_dataout;
	wire	wire_nliiOl_dataout;
	wire	wire_nliiOO_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nlil0i_dataout;
	wire	wire_nlil0l_dataout;
	wire	wire_nlil0O_dataout;
	wire	wire_nlil1i_dataout;
	wire	wire_nlil1l_dataout;
	wire	wire_nlil1O_dataout;
	wire	wire_nlili_dataout;
	wire	wire_nlilii_dataout;
	wire	wire_nlilil_dataout;
	wire	wire_nliliO_dataout;
	wire	wire_nlill_dataout;
	wire	wire_nlilli_dataout;
	wire	wire_nlilll_dataout;
	wire	wire_nlillO_dataout;
	wire	wire_nlilO_dataout;
	wire	wire_nlilOi_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nliOi_dataout;
	wire	wire_nliOl_dataout;
	wire	wire_nliOO_dataout;
	wire	wire_nliOOi_dataout;
	wire	wire_nliOOl_dataout;
	wire	wire_nll_dataout;
	wire	wire_nll00O_dataout;
	wire	wire_nll00Ol_dataout;
	wire	wire_nll00OO_dataout;
	wire	wire_nll01i_dataout;
	wire	wire_nll01l_dataout;
	wire	wire_nll0i_dataout;
	wire	wire_nll0i1i_dataout;
	wire	wire_nll0l_dataout;
	wire	wire_nll0O_dataout;
	wire	wire_nll0Ol_dataout;
	wire	wire_nll0OO_dataout;
	wire	wire_nll11O_dataout;
	wire	wire_nll1i_dataout;
	wire	wire_nll1ii_dataout;
	wire	wire_nll1il_dataout;
	wire	wire_nll1iO_dataout;
	wire	wire_nll1l_dataout;
	wire	wire_nll1li_dataout;
	wire	wire_nll1O_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nllii_dataout;
	wire	wire_nlliiO_dataout;
	wire	wire_nllil_dataout;
	wire	wire_nllili_dataout;
	wire	wire_nllilO_dataout;
	wire	wire_nlliO_dataout;
	wire	wire_nlliOi_dataout;
	wire	wire_nlliOl_dataout;
	wire	wire_nlliOO_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nlll0i_dataout;
	wire	wire_nlll0l_dataout;
	wire	wire_nlll0O_dataout;
	wire	wire_nlll1i_dataout;
	wire	wire_nlll1l_dataout;
	wire	wire_nlll1O_dataout;
	wire	wire_nllli_dataout;
	wire	wire_nlllii_dataout;
	wire	wire_nlllil_dataout;
	wire	wire_nllliO_dataout;
	wire	wire_nllll_dataout;
	wire	wire_nlllli_dataout;
	wire	wire_nlllll_dataout;
	wire	wire_nllllO_dataout;
	wire	wire_nlllO_dataout;
	wire	wire_nlllOi_dataout;
	wire	wire_nlllOl_dataout;
	wire	wire_nlllOO_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nllO0i_dataout;
	wire	wire_nllO0l_dataout;
	wire	wire_nllO0O_dataout;
	wire	wire_nllO1i_dataout;
	wire	wire_nllO1l_dataout;
	wire	wire_nllO1O_dataout;
	wire	wire_nllOi_dataout;
	wire	wire_nllOii_dataout;
	wire	wire_nllOil_dataout;
	wire	wire_nllOiO_dataout;
	wire	wire_nllOl_dataout;
	wire	wire_nllOl0i_dataout;
	wire	wire_nllOl0l_dataout;
	wire	wire_nllOl0O_dataout;
	wire	wire_nllOl1O_dataout;
	wire	wire_nllOli_dataout;
	wire	wire_nllOlii_dataout;
	wire	wire_nllOlil_dataout;
	wire	wire_nllOliO_dataout;
	wire	wire_nllOll_dataout;
	wire	wire_nllOlli_dataout;
	wire	wire_nllOlll_dataout;
	wire	wire_nllOllO_dataout;
	wire	wire_nllOlO_dataout;
	wire	wire_nllOlOi_dataout;
	wire	wire_nllOlOl_dataout;
	wire	wire_nllOlOO_dataout;
	wire	wire_nllOO_dataout;
	wire	wire_nllOO0i_dataout;
	wire	wire_nllOO0l_dataout;
	wire	wire_nllOO0O_dataout;
	wire	wire_nllOO1i_dataout;
	wire	wire_nllOO1l_dataout;
	wire	wire_nllOO1O_dataout;
	wire	wire_nllOOi_dataout;
	wire	wire_nllOOii_dataout;
	wire	wire_nllOOil_dataout;
	wire	wire_nllOOiO_dataout;
	wire	wire_nllOOl_dataout;
	wire	wire_nllOOli_dataout;
	wire	wire_nllOOll_dataout;
	wire	wire_nllOOlO_dataout;
	wire	wire_nllOOOi_dataout;
	wire	wire_nllOOOl_dataout;
	wire	wire_nllOOOO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlO000i_dataout;
	wire	wire_nlO000l_dataout;
	wire	wire_nlO001i_dataout;
	wire	wire_nlO010i_dataout;
	wire	wire_nlO010l_dataout;
	wire	wire_nlO010O_dataout;
	wire	wire_nlO011i_dataout;
	wire	wire_nlO011l_dataout;
	wire	wire_nlO011O_dataout;
	wire	wire_nlO01ii_dataout;
	wire	wire_nlO01il_dataout;
	wire	wire_nlO01iO_dataout;
	wire	wire_nlO01li_dataout;
	wire	wire_nlO01ll_dataout;
	wire	wire_nlO01lO_dataout;
	wire	wire_nlO01Oi_dataout;
	wire	wire_nlO01Ol_dataout;
	wire	wire_nlO01OO_dataout;
	wire	wire_nlO0i_dataout;
	wire	wire_nlO0l_dataout;
	wire	wire_nlO0O_dataout;
	wire	wire_nlO0Oll_dataout;
	wire	wire_nlO0OlO_dataout;
	wire	wire_nlO0OOi_dataout;
	wire	wire_nlO0OOl_dataout;
	wire	wire_nlO0OOO_dataout;
	wire	wire_nlO100i_dataout;
	wire	wire_nlO100l_dataout;
	wire	wire_nlO100O_dataout;
	wire	wire_nlO101i_dataout;
	wire	wire_nlO101l_dataout;
	wire	wire_nlO101O_dataout;
	wire	wire_nlO10ii_dataout;
	wire	wire_nlO10il_dataout;
	wire	wire_nlO10iO_dataout;
	wire	wire_nlO10li_dataout;
	wire	wire_nlO10ll_dataout;
	wire	wire_nlO10lO_dataout;
	wire	wire_nlO10Oi_dataout;
	wire	wire_nlO10Ol_dataout;
	wire	wire_nlO10OO_dataout;
	wire	wire_nlO110i_dataout;
	wire	wire_nlO110l_dataout;
	wire	wire_nlO110O_dataout;
	wire	wire_nlO111i_dataout;
	wire	wire_nlO111l_dataout;
	wire	wire_nlO111O_dataout;
	wire	wire_nlO11ii_dataout;
	wire	wire_nlO11il_dataout;
	wire	wire_nlO11iO_dataout;
	wire	wire_nlO11li_dataout;
	wire	wire_nlO11ll_dataout;
	wire	wire_nlO11lO_dataout;
	wire	wire_nlO11Oi_dataout;
	wire	wire_nlO11Ol_dataout;
	wire	wire_nlO11OO_dataout;
	wire	wire_nlO1i_dataout;
	wire	wire_nlO1i0i_dataout;
	wire	wire_nlO1i0l_dataout;
	wire	wire_nlO1i0O_dataout;
	wire	wire_nlO1i1i_dataout;
	wire	wire_nlO1i1l_dataout;
	wire	wire_nlO1i1O_dataout;
	wire	wire_nlO1iii_dataout;
	wire	wire_nlO1iil_dataout;
	wire	wire_nlO1iiO_dataout;
	wire	wire_nlO1ili_dataout;
	wire	wire_nlO1ill_dataout;
	wire	wire_nlO1ilO_dataout;
	wire	wire_nlO1iOi_dataout;
	wire	wire_nlO1iOl_dataout;
	wire	wire_nlO1iOO_dataout;
	wire	wire_nlO1l_dataout;
	wire	wire_nlO1l0i_dataout;
	wire	wire_nlO1l0l_dataout;
	wire	wire_nlO1l0O_dataout;
	wire	wire_nlO1l1i_dataout;
	wire	wire_nlO1l1l_dataout;
	wire	wire_nlO1l1O_dataout;
	wire	wire_nlO1lii_dataout;
	wire	wire_nlO1lil_dataout;
	wire	wire_nlO1liO_dataout;
	wire	wire_nlO1lli_dataout;
	wire	wire_nlO1lll_dataout;
	wire	wire_nlO1llO_dataout;
	wire	wire_nlO1lOi_dataout;
	wire	wire_nlO1lOO_dataout;
	wire	wire_nlO1O_dataout;
	wire	wire_nlO1O0i_dataout;
	wire	wire_nlO1O0l_dataout;
	wire	wire_nlO1O0O_dataout;
	wire	wire_nlO1O1i_dataout;
	wire	wire_nlO1O1l_dataout;
	wire	wire_nlO1O1O_dataout;
	wire	wire_nlO1Oii_dataout;
	wire	wire_nlO1Oil_dataout;
	wire	wire_nlO1OiO_dataout;
	wire	wire_nlO1Oli_dataout;
	wire	wire_nlO1Oll_dataout;
	wire	wire_nlO1OlO_dataout;
	wire	wire_nlO1OOi_dataout;
	wire	wire_nlO1OOl_dataout;
	wire	wire_nlO1OOO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOi00i_dataout;
	wire	wire_nlOi00l_dataout;
	wire	wire_nlOi00O_dataout;
	wire	wire_nlOi01i_dataout;
	wire	wire_nlOi01l_dataout;
	wire	wire_nlOi01O_dataout;
	wire	wire_nlOi0ii_dataout;
	wire	wire_nlOi0il_dataout;
	wire	wire_nlOi0iO_dataout;
	wire	wire_nlOi0li_dataout;
	wire	wire_nlOi0ll_dataout;
	wire	wire_nlOi0lO_dataout;
	wire	wire_nlOi0Oi_dataout;
	wire	wire_nlOi0Ol_dataout;
	wire	wire_nlOi0OO_dataout;
	wire	wire_nlOi10i_dataout;
	wire	wire_nlOi10l_dataout;
	wire	wire_nlOi10O_dataout;
	wire	wire_nlOi11i_dataout;
	wire	wire_nlOi11l_dataout;
	wire	wire_nlOi11O_dataout;
	wire	wire_nlOi1ii_dataout;
	wire	wire_nlOi1il_dataout;
	wire	wire_nlOi1iO_dataout;
	wire	wire_nlOi1li_dataout;
	wire	wire_nlOi1ll_dataout;
	wire	wire_nlOi1lO_dataout;
	wire	wire_nlOi1Oi_dataout;
	wire	wire_nlOi1Ol_dataout;
	wire	wire_nlOi1OO_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOii0i_dataout;
	wire	wire_nlOii0l_dataout;
	wire	wire_nlOii0O_dataout;
	wire	wire_nlOii1i_dataout;
	wire	wire_nlOii1l_dataout;
	wire	wire_nlOii1O_dataout;
	wire	wire_nlOiiii_dataout;
	wire	wire_nlOiiil_dataout;
	wire	wire_nlOiiiO_dataout;
	wire	wire_nlOiili_dataout;
	wire	wire_nlOiill_dataout;
	wire	wire_nlOiilO_dataout;
	wire	wire_nlOiiOi_dataout;
	wire	wire_nlOiiOl_dataout;
	wire	wire_nlOiiOO_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOil0i_dataout;
	wire	wire_nlOil0l_dataout;
	wire	wire_nlOil0O_dataout;
	wire	wire_nlOil1i_dataout;
	wire	wire_nlOil1l_dataout;
	wire	wire_nlOil1O_dataout;
	wire	wire_nlOilii_dataout;
	wire	wire_nlOilil_dataout;
	wire	wire_nlOiliO_dataout;
	wire	wire_nlOilli_dataout;
	wire	wire_nlOilll_dataout;
	wire	wire_nlOillO_dataout;
	wire	wire_nlOilOi_dataout;
	wire	wire_nlOilOl_dataout;
	wire	wire_nlOilOO_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOiO0i_dataout;
	wire	wire_nlOiO0l_dataout;
	wire	wire_nlOiO0O_dataout;
	wire	wire_nlOiO1i_dataout;
	wire	wire_nlOiO1l_dataout;
	wire	wire_nlOiO1O_dataout;
	wire	wire_nlOiOii_dataout;
	wire	wire_nlOiOil_dataout;
	wire	wire_nlOiOiO_dataout;
	wire	wire_nlOiOli_dataout;
	wire	wire_nlOiOll_dataout;
	wire	wire_nlOiOlO_dataout;
	wire	wire_nlOiOOi_dataout;
	wire	wire_nlOiOOl_dataout;
	wire	wire_nlOiOOO_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOl00i_dataout;
	wire	wire_nlOl00l_dataout;
	wire	wire_nlOl01i_dataout;
	wire	wire_nlOl01l_dataout;
	wire	wire_nlOl01O_dataout;
	wire	wire_nlOl0i_dataout;
	wire	wire_nlOl0l_dataout;
	wire	wire_nlOl0O_dataout;
	wire	wire_nlOl0Ol_dataout;
	wire	wire_nlOl0OO_dataout;
	wire	wire_nlOl10i_dataout;
	wire	wire_nlOl10l_dataout;
	wire	wire_nlOl10O_dataout;
	wire	wire_nlOl11i_dataout;
	wire	wire_nlOl11l_dataout;
	wire	wire_nlOl11O_dataout;
	wire	wire_nlOl1ii_dataout;
	wire	wire_nlOl1il_dataout;
	wire	wire_nlOl1iO_dataout;
	wire	wire_nlOl1l_dataout;
	wire	wire_nlOl1li_dataout;
	wire	wire_nlOl1ll_dataout;
	wire	wire_nlOl1lO_dataout;
	wire	wire_nlOl1O_dataout;
	wire	wire_nlOl1Oi_dataout;
	wire	wire_nlOl1Ol_dataout;
	wire	wire_nlOl1OO_dataout;
	wire	wire_nlOli_dataout;
	wire	wire_nlOli1i_dataout;
	wire	wire_nlOli1l_dataout;
	wire	wire_nlOli1O_dataout;
	wire	wire_nlOlii_dataout;
	wire	wire_nlOlil_dataout;
	wire	wire_nlOliO_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlli_dataout;
	wire	wire_nlOlll_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOlOi_dataout;
	wire	wire_nlOlOOl_dataout;
	wire	wire_nlOlOOO_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOO00i_dataout;
	wire	wire_nlOO00l_dataout;
	wire	wire_nlOO00O_dataout;
	wire	wire_nlOO01i_dataout;
	wire	wire_nlOO01l_dataout;
	wire	wire_nlOO01O_dataout;
	wire	wire_nlOO0ii_dataout;
	wire	wire_nlOO0il_dataout;
	wire	wire_nlOO0iO_dataout;
	wire	wire_nlOO0li_dataout;
	wire	wire_nlOO0ll_dataout;
	wire	wire_nlOO0lO_dataout;
	wire	wire_nlOO0Oi_dataout;
	wire	wire_nlOO0Ol_dataout;
	wire	wire_nlOO0OO_dataout;
	wire	wire_nlOO10i_dataout;
	wire	wire_nlOO10l_dataout;
	wire	wire_nlOO10O_dataout;
	wire	wire_nlOO11i_dataout;
	wire	wire_nlOO11l_dataout;
	wire	wire_nlOO11O_dataout;
	wire	wire_nlOO1ii_dataout;
	wire	wire_nlOO1il_dataout;
	wire	wire_nlOO1iO_dataout;
	wire	wire_nlOO1li_dataout;
	wire	wire_nlOO1ll_dataout;
	wire	wire_nlOO1lO_dataout;
	wire	wire_nlOO1Oi_dataout;
	wire	wire_nlOO1Ol_dataout;
	wire	wire_nlOO1OO_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOi0i_dataout;
	wire	wire_nlOOi0l_dataout;
	wire	wire_nlOOi0O_dataout;
	wire	wire_nlOOi1i_dataout;
	wire	wire_nlOOi1l_dataout;
	wire	wire_nlOOi1O_dataout;
	wire	wire_nlOOiii_dataout;
	wire	wire_nlOOiil_dataout;
	wire	wire_nlOOiiO_dataout;
	wire	wire_nlOOili_dataout;
	wire	wire_nlOOill_dataout;
	wire	wire_nlOOilO_dataout;
	wire	wire_nlOOiOi_dataout;
	wire	wire_nlOOiOl_dataout;
	wire	wire_nlOOiOO_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOl0i_dataout;
	wire	wire_nlOOl0l_dataout;
	wire	wire_nlOOl0O_dataout;
	wire	wire_nlOOl1i_dataout;
	wire	wire_nlOOl1l_dataout;
	wire	wire_nlOOl1O_dataout;
	wire	wire_nlOOlii_dataout;
	wire	wire_nlOOlil_dataout;
	wire	wire_nlOOliO_dataout;
	wire	wire_nlOOlli_dataout;
	wire	wire_nlOOlll_dataout;
	wire	wire_nlOOllO_dataout;
	wire	wire_nlOOlOi_dataout;
	wire	wire_nlOOlOl_dataout;
	wire	wire_nlOOlOO_dataout;
	wire	wire_nlOOO_dataout;
	wire	wire_nlOOO0i_dataout;
	wire	wire_nlOOO0l_dataout;
	wire	wire_nlOOO0O_dataout;
	wire	wire_nlOOO1i_dataout;
	wire	wire_nlOOO1l_dataout;
	wire	wire_nlOOO1O_dataout;
	wire	wire_nlOOOii_dataout;
	wire	wire_nlOOOil_dataout;
	wire	wire_nlOOOiO_dataout;
	wire	wire_nlOOOli_dataout;
	wire	wire_nlOOOll_dataout;
	wire	wire_nlOOOlO_dataout;
	wire	wire_nlOOOOi_dataout;
	wire	wire_nlOOOOl_dataout;
	wire	wire_nlOOOOO_dataout;
	wire  [5:0]   wire_n1110i_o;
	wire  [4:0]   wire_n111lO_o;
	wire  [5:0]   wire_n1i0ll_o;
	wire  [2:0]   wire_n1i0Ol_o;
	wire  [5:0]   wire_n1ilii_o;
	wire  [5:0]   wire_n1ilil_o;
	wire  [5:0]   wire_n1iliO_o;
	wire  [5:0]   wire_n1llOl_o;
	wire  [4:0]   wire_n1llOO_o;
	wire  [3:0]   wire_n1lO0O_o;
	wire  [4:0]   wire_n1lOil_o;
	wire  [2:0]   wire_n1OilO_o;
	wire  [4:0]   wire_niO10l_o;
	wire  [4:0]   wire_nl10ll_o;
	wire  [5:0]   wire_nli0lO_o;
	wire  [5:0]   wire_nli0Oi_o;
	wire  [5:0]   wire_nli0Ol_o;
	wire  [2:0]   wire_nli10i_o;
	wire  [5:0]   wire_nli11i_o;
	wire  [5:0]   wire_nlilOl_o;
	wire  [4:0]   wire_nlilOO_o;
	wire  [4:0]   wire_nlOli0i_o;
	wire  [31:0]   wire_n1010O_o;
	wire  [7:0]   wire_n101il_o;
	wire  [15:0]   wire_n101ll_o;
	wire  [7:0]   wire_n101lO_o;
	wire  [15:0]   wire_nilOil_o;
	wire  [15:0]   wire_nilOli_o;
	wire  [31:0]   wire_nilOOl_o;
	wire  [7:0]   wire_nl1O0i_o;
	wire  [31:0]   wire_nl1O1l_o;
	wire  [15:0]   wire_nl1Oii_o;
	wire  [7:0]   wire_nl1Oil_o;
	wire  [15:0]   wire_nlOl0ii_o;
	wire  [15:0]   wire_nlOl0iO_o;
	wire  [31:0]   wire_nlOl0Oi_o;
	wire  wire_n11l0l_o;
	wire  wire_n11lil_o;
	wire  wire_n11O0i_o;
	wire  wire_n1i0li_o;
	wire  wire_n1i0Oi_o;
	wire  wire_n1i0OO_o;
	wire  wire_n1illi_o;
	wire  wire_n1iOOO_o;
	wire  wire_n1l0ll_o;
	wire  wire_n1O00i_o;
	wire  wire_n1O00l_o;
	wire  wire_nl0OOO_o;
	wire  wire_nl1iOO_o;
	wire  wire_nli0OO_o;
	wire  wire_nli10l_o;
	wire  wire_nli11O_o;
	wire  wire_nlii0l_o;
	wire  wire_nliiil_o;
	wire  wire_nliOOO_o;
	wire  wire_nll11i_o;
	wire  wire_n000iO_o;
	wire  wire_n000li_o;
	wire  wire_n000ll_o;
	wire  wire_n000lO_o;
	wire  wire_n000Oi_o;
	wire  wire_n000Ol_o;
	wire  wire_n000OO_o;
	wire  wire_n00i1i_o;
	wire  wire_n00i1l_o;
	wire  wire_n00i1O_o;
	wire  wire_nlOiOi_o;
	wire  wire_nlOiOl_o;
	wire  wire_nlOiOO_o;
	wire  wire_nlOl1i_o;
	wire  [15:0]   wire_nlOiiO_data_out1;
	wire  [15:0]   wire_nlOiiO_data_out2;
	wire  [15:0]   wire_nlOili_data_out1;
	wire  [15:0]   wire_nlOili_data_out2;
	wire  nlill0i;
	wire  nlill0O;
	wire  nlill1O;
	wire  nlillii;
	wire  nlillil;
	wire  nlilliO;
	wire  nlillli;
	wire  nlillll;
	wire  nlilllO;
	wire  nlillOi;
	wire  nlillOl;
	wire  nlillOO;
	wire  nlilO0i;
	wire  nlilO0l;
	wire  nlilO0O;
	wire  nlilO1i;
	wire  nlilO1l;
	wire  nlilO1O;
	wire  nlilOii;
	wire  nlilOil;
	wire  nlilOiO;
	wire  nlilOli;
	wire  nlilOll;
	wire  nlilOlO;
	wire  nlilOOi;
	wire  nlilOOl;
	wire  nlilOOO;
	wire  nliO00i;
	wire  nliO00l;
	wire  nliO00O;
	wire  nliO01i;
	wire  nliO01l;
	wire  nliO01O;
	wire  nliO0ii;
	wire  nliO0il;
	wire  nliO0iO;
	wire  nliO0li;
	wire  nliO0ll;
	wire  nliO0lO;
	wire  nliO0Oi;
	wire  nliO0Ol;
	wire  nliO0OO;
	wire  nliO10i;
	wire  nliO10l;
	wire  nliO10O;
	wire  nliO11i;
	wire  nliO11l;
	wire  nliO11O;
	wire  nliO1ii;
	wire  nliO1il;
	wire  nliO1iO;
	wire  nliO1li;
	wire  nliO1ll;
	wire  nliO1lO;
	wire  nliO1Oi;
	wire  nliO1Ol;
	wire  nliO1OO;
	wire  nliOi0i;
	wire  nliOi0l;
	wire  nliOi0O;
	wire  nliOi1i;
	wire  nliOi1l;
	wire  nliOi1O;
	wire  nliOiii;
	wire  nliOiil;
	wire  nliOiiO;
	wire  nliOili;
	wire  nliOill;
	wire  nliOilO;
	wire  nliOiOi;
	wire  nliOiOl;
	wire  nliOiOO;
	wire  nliOl0i;
	wire  nliOl0l;
	wire  nliOl0O;
	wire  nliOl1i;
	wire  nliOl1l;
	wire  nliOl1O;
	wire  nliOlii;
	wire  nliOlil;
	wire  nliOlll;
	wire  nliOllO;
	wire  nliOlOi;
	wire  nliOlOl;
	wire  nliOlOO;
	wire  nliOO0i;
	wire  nliOO0l;
	wire  nliOO0O;
	wire  nliOO1i;
	wire  nliOO1l;
	wire  nliOO1O;
	wire  nliOOii;
	wire  nliOOil;
	wire  nliOOiO;
	wire  nliOOli;
	wire  nliOOll;
	wire  nliOOlO;
	wire  nliOOOi;
	wire  nliOOOl;
	wire  nliOOOO;
	wire  nll000O;
	wire  nll001i;
	wire  nll001l;
	wire  nll00iO;
	wire  nll010i;
	wire  nll011i;
	wire  nll01iO;
	wire  nll01lO;
	wire  nll01Oi;
	wire  nll01Ol;
	wire  nll01OO;
	wire  nll100i;
	wire  nll100l;
	wire  nll100O;
	wire  nll101i;
	wire  nll101l;
	wire  nll101O;
	wire  nll10ii;
	wire  nll10iO;
	wire  nll10li;
	wire  nll10ll;
	wire  nll10lO;
	wire  nll10Oi;
	wire  nll10Ol;
	wire  nll10OO;
	wire  nll110i;
	wire  nll110l;
	wire  nll110O;
	wire  nll111i;
	wire  nll111l;
	wire  nll11ii;
	wire  nll11il;
	wire  nll11iO;
	wire  nll11li;
	wire  nll11ll;
	wire  nll11lO;
	wire  nll11Oi;
	wire  nll11Ol;
	wire  nll11OO;
	wire  nll1i0i;
	wire  nll1i0l;
	wire  nll1i1i;
	wire  nll1iil;
	wire  nll1iiO;
	wire  nll1l0i;
	wire  nll1l0l;
	wire  nll1l0O;
	wire  nll1l1i;
	wire  nll1lii;
	wire  nll1lil;
	wire  nll1lll;
	wire  nll1llO;
	wire  nll1O0i;
	wire  nll1O0l;
	wire  nll1O1l;
	wire  nll1OlO;
	wire  nll1OOO;

	initial
		nlill0l55 = 0;
	always @ ( posedge clk_2)
		  nlill0l55 <= nlill0l56;
	event nlill0l55_event;
	initial
		#1 ->nlill0l55_event;
	always @(nlill0l55_event)
		nlill0l55 <= {1{1'b1}};
	initial
		nlill0l56 = 0;
	always @ ( posedge clk_2)
		  nlill0l56 <= nlill0l55;
	initial
		nliOliO53 = 0;
	always @ ( posedge clk_2)
		  nliOliO53 <= nliOliO54;
	event nliOliO53_event;
	initial
		#1 ->nliOliO53_event;
	always @(nliOliO53_event)
		nliOliO53 <= {1{1'b1}};
	initial
		nliOliO54 = 0;
	always @ ( posedge clk_2)
		  nliOliO54 <= nliOliO53;
	initial
		nliOlli51 = 0;
	always @ ( posedge clk_2)
		  nliOlli51 <= nliOlli52;
	event nliOlli51_event;
	initial
		#1 ->nliOlli51_event;
	always @(nliOlli51_event)
		nliOlli51 <= {1{1'b1}};
	initial
		nliOlli52 = 0;
	always @ ( posedge clk_2)
		  nliOlli52 <= nliOlli51;
	initial
		nll000l3 = 0;
	always @ ( posedge clk_2)
		  nll000l3 <= nll000l4;
	event nll000l3_event;
	initial
		#1 ->nll000l3_event;
	always @(nll000l3_event)
		nll000l3 <= {1{1'b1}};
	initial
		nll000l4 = 0;
	always @ ( posedge clk_2)
		  nll000l4 <= nll000l3;
	initial
		nll001O5 = 0;
	always @ ( posedge clk_2)
		  nll001O5 <= nll001O6;
	event nll001O5_event;
	initial
		#1 ->nll001O5_event;
	always @(nll001O5_event)
		nll001O5 <= {1{1'b1}};
	initial
		nll001O6 = 0;
	always @ ( posedge clk_2)
		  nll001O6 <= nll001O5;
	initial
		nll00li1 = 0;
	always @ ( posedge clk_2)
		  nll00li1 <= nll00li2;
	event nll00li1_event;
	initial
		#1 ->nll00li1_event;
	always @(nll00li1_event)
		nll00li1 <= {1{1'b1}};
	initial
		nll00li2 = 0;
	always @ ( posedge clk_2)
		  nll00li2 <= nll00li1;
	initial
		nll010l11 = 0;
	always @ ( posedge clk_2)
		  nll010l11 <= nll010l12;
	event nll010l11_event;
	initial
		#1 ->nll010l11_event;
	always @(nll010l11_event)
		nll010l11 <= {1{1'b1}};
	initial
		nll010l12 = 0;
	always @ ( posedge clk_2)
		  nll010l12 <= nll010l11;
	initial
		nll011l13 = 0;
	always @ ( posedge clk_2)
		  nll011l13 <= nll011l14;
	event nll011l13_event;
	initial
		#1 ->nll011l13_event;
	always @(nll011l13_event)
		nll011l13 <= {1{1'b1}};
	initial
		nll011l14 = 0;
	always @ ( posedge clk_2)
		  nll011l14 <= nll011l13;
	initial
		nll01ii10 = 0;
	always @ ( posedge clk_2)
		  nll01ii10 <= nll01ii9;
	initial
		nll01ii9 = 0;
	always @ ( posedge clk_2)
		  nll01ii9 <= nll01ii10;
	event nll01ii9_event;
	initial
		#1 ->nll01ii9_event;
	always @(nll01ii9_event)
		nll01ii9 <= {1{1'b1}};
	initial
		nll01li7 = 0;
	always @ ( posedge clk_2)
		  nll01li7 <= nll01li8;
	event nll01li7_event;
	initial
		#1 ->nll01li7_event;
	always @(nll01li7_event)
		nll01li7 <= {1{1'b1}};
	initial
		nll01li8 = 0;
	always @ ( posedge clk_2)
		  nll01li8 <= nll01li7;
	initial
		nll10il47 = 0;
	always @ ( posedge clk_2)
		  nll10il47 <= nll10il48;
	event nll10il47_event;
	initial
		#1 ->nll10il47_event;
	always @(nll10il47_event)
		nll10il47 <= {1{1'b1}};
	initial
		nll10il48 = 0;
	always @ ( posedge clk_2)
		  nll10il48 <= nll10il47;
	initial
		nll111O49 = 0;
	always @ ( posedge clk_2)
		  nll111O49 <= nll111O50;
	event nll111O49_event;
	initial
		#1 ->nll111O49_event;
	always @(nll111O49_event)
		nll111O49 <= {1{1'b1}};
	initial
		nll111O50 = 0;
	always @ ( posedge clk_2)
		  nll111O50 <= nll111O49;
	initial
		nll1i0O43 = 0;
	always @ ( posedge clk_2)
		  nll1i0O43 <= nll1i0O44;
	event nll1i0O43_event;
	initial
		#1 ->nll1i0O43_event;
	always @(nll1i0O43_event)
		nll1i0O43 <= {1{1'b1}};
	initial
		nll1i0O44 = 0;
	always @ ( posedge clk_2)
		  nll1i0O44 <= nll1i0O43;
	initial
		nll1i1l45 = 0;
	always @ ( posedge clk_2)
		  nll1i1l45 <= nll1i1l46;
	event nll1i1l45_event;
	initial
		#1 ->nll1i1l45_event;
	always @(nll1i1l45_event)
		nll1i1l45 <= {1{1'b1}};
	initial
		nll1i1l46 = 0;
	always @ ( posedge clk_2)
		  nll1i1l46 <= nll1i1l45;
	initial
		nll1ili41 = 0;
	always @ ( posedge clk_2)
		  nll1ili41 <= nll1ili42;
	event nll1ili41_event;
	initial
		#1 ->nll1ili41_event;
	always @(nll1ili41_event)
		nll1ili41 <= {1{1'b1}};
	initial
		nll1ili42 = 0;
	always @ ( posedge clk_2)
		  nll1ili42 <= nll1ili41;
	initial
		nll1ilO39 = 0;
	always @ ( posedge clk_2)
		  nll1ilO39 <= nll1ilO40;
	event nll1ilO39_event;
	initial
		#1 ->nll1ilO39_event;
	always @(nll1ilO39_event)
		nll1ilO39 <= {1{1'b1}};
	initial
		nll1ilO40 = 0;
	always @ ( posedge clk_2)
		  nll1ilO40 <= nll1ilO39;
	initial
		nll1iOl37 = 0;
	always @ ( posedge clk_2)
		  nll1iOl37 <= nll1iOl38;
	event nll1iOl37_event;
	initial
		#1 ->nll1iOl37_event;
	always @(nll1iOl37_event)
		nll1iOl37 <= {1{1'b1}};
	initial
		nll1iOl38 = 0;
	always @ ( posedge clk_2)
		  nll1iOl38 <= nll1iOl37;
	initial
		nll1l1l35 = 0;
	always @ ( posedge clk_2)
		  nll1l1l35 <= nll1l1l36;
	event nll1l1l35_event;
	initial
		#1 ->nll1l1l35_event;
	always @(nll1l1l35_event)
		nll1l1l35 <= {1{1'b1}};
	initial
		nll1l1l36 = 0;
	always @ ( posedge clk_2)
		  nll1l1l36 <= nll1l1l35;
	initial
		nll1liO33 = 0;
	always @ ( posedge clk_2)
		  nll1liO33 <= nll1liO34;
	event nll1liO33_event;
	initial
		#1 ->nll1liO33_event;
	always @(nll1liO33_event)
		nll1liO33 <= {1{1'b1}};
	initial
		nll1liO34 = 0;
	always @ ( posedge clk_2)
		  nll1liO34 <= nll1liO33;
	initial
		nll1lOi31 = 0;
	always @ ( posedge clk_2)
		  nll1lOi31 <= nll1lOi32;
	event nll1lOi31_event;
	initial
		#1 ->nll1lOi31_event;
	always @(nll1lOi31_event)
		nll1lOi31 <= {1{1'b1}};
	initial
		nll1lOi32 = 0;
	always @ ( posedge clk_2)
		  nll1lOi32 <= nll1lOi31;
	initial
		nll1lOl29 = 0;
	always @ ( posedge clk_2)
		  nll1lOl29 <= nll1lOl30;
	event nll1lOl29_event;
	initial
		#1 ->nll1lOl29_event;
	always @(nll1lOl29_event)
		nll1lOl29 <= {1{1'b1}};
	initial
		nll1lOl30 = 0;
	always @ ( posedge clk_2)
		  nll1lOl30 <= nll1lOl29;
	initial
		nll1lOO27 = 0;
	always @ ( posedge clk_2)
		  nll1lOO27 <= nll1lOO28;
	event nll1lOO27_event;
	initial
		#1 ->nll1lOO27_event;
	always @(nll1lOO27_event)
		nll1lOO27 <= {1{1'b1}};
	initial
		nll1lOO28 = 0;
	always @ ( posedge clk_2)
		  nll1lOO28 <= nll1lOO27;
	initial
		nll1O0O21 = 0;
	always @ ( posedge clk_2)
		  nll1O0O21 <= nll1O0O22;
	event nll1O0O21_event;
	initial
		#1 ->nll1O0O21_event;
	always @(nll1O0O21_event)
		nll1O0O21 <= {1{1'b1}};
	initial
		nll1O0O22 = 0;
	always @ ( posedge clk_2)
		  nll1O0O22 <= nll1O0O21;
	initial
		nll1O1i25 = 0;
	always @ ( posedge clk_2)
		  nll1O1i25 <= nll1O1i26;
	event nll1O1i25_event;
	initial
		#1 ->nll1O1i25_event;
	always @(nll1O1i25_event)
		nll1O1i25 <= {1{1'b1}};
	initial
		nll1O1i26 = 0;
	always @ ( posedge clk_2)
		  nll1O1i26 <= nll1O1i25;
	initial
		nll1O1O23 = 0;
	always @ ( posedge clk_2)
		  nll1O1O23 <= nll1O1O24;
	event nll1O1O23_event;
	initial
		#1 ->nll1O1O23_event;
	always @(nll1O1O23_event)
		nll1O1O23 <= {1{1'b1}};
	initial
		nll1O1O24 = 0;
	always @ ( posedge clk_2)
		  nll1O1O24 <= nll1O1O23;
	initial
		nll1Oil19 = 0;
	always @ ( posedge clk_2)
		  nll1Oil19 <= nll1Oil20;
	event nll1Oil19_event;
	initial
		#1 ->nll1Oil19_event;
	always @(nll1Oil19_event)
		nll1Oil19 <= {1{1'b1}};
	initial
		nll1Oil20 = 0;
	always @ ( posedge clk_2)
		  nll1Oil20 <= nll1Oil19;
	initial
		nll1Oli17 = 0;
	always @ ( posedge clk_2)
		  nll1Oli17 <= nll1Oli18;
	event nll1Oli17_event;
	initial
		#1 ->nll1Oli17_event;
	always @(nll1Oli17_event)
		nll1Oli17 <= {1{1'b1}};
	initial
		nll1Oli18 = 0;
	always @ ( posedge clk_2)
		  nll1Oli18 <= nll1Oli17;
	initial
		nll1OOi15 = 0;
	always @ ( posedge clk_2)
		  nll1OOi15 <= nll1OOi16;
	event nll1OOi15_event;
	initial
		#1 ->nll1OOi15_event;
	always @(nll1OOi15_event)
		nll1OOi15 <= {1{1'b1}};
	initial
		nll1OOi16 = 0;
	always @ ( posedge clk_2)
		  nll1OOi16 <= nll1OOi15;
	initial
	begin
		n0OiiO = 0;
		n0Oili = 0;
		n0Oill = 0;
		n0OilO = 0;
		n0OiOi = 0;
		n0OiOl = 0;
		n0OiOO = 0;
		n0Ol0i = 0;
		n0Ol0l = 0;
		n0Ol0O = 0;
		n0Ol1i = 0;
		n0Ol1l = 0;
		n0Ol1O = 0;
		n0Olii = 0;
		n0Olil = 0;
		n0OliO = 0;
		n0Olli = 0;
		n0Olll = 0;
		n0OllO = 0;
		n0OlOi = 0;
		ni11ll = 0;
		ni11Ol = 0;
	end
	always @ (clk_2 or wire_ni11Oi_PRN or wire_ni11Oi_CLRN)
	begin
		if (wire_ni11Oi_PRN == 1'b0) 
		begin
			n0OiiO <= 1;
			n0Oili <= 1;
			n0Oill <= 1;
			n0OilO <= 1;
			n0OiOi <= 1;
			n0OiOl <= 1;
			n0OiOO <= 1;
			n0Ol0i <= 1;
			n0Ol0l <= 1;
			n0Ol0O <= 1;
			n0Ol1i <= 1;
			n0Ol1l <= 1;
			n0Ol1O <= 1;
			n0Olii <= 1;
			n0Olil <= 1;
			n0OliO <= 1;
			n0Olli <= 1;
			n0Olll <= 1;
			n0OllO <= 1;
			n0OlOi <= 1;
			ni11ll <= 1;
			ni11Ol <= 1;
		end
		else if  (wire_ni11Oi_CLRN == 1'b0) 
		begin
			n0OiiO <= 0;
			n0Oili <= 0;
			n0Oill <= 0;
			n0OilO <= 0;
			n0OiOi <= 0;
			n0OiOl <= 0;
			n0OiOO <= 0;
			n0Ol0i <= 0;
			n0Ol0l <= 0;
			n0Ol0O <= 0;
			n0Ol1i <= 0;
			n0Ol1l <= 0;
			n0Ol1O <= 0;
			n0Olii <= 0;
			n0Olil <= 0;
			n0OliO <= 0;
			n0Olli <= 0;
			n0Olll <= 0;
			n0OllO <= 0;
			n0OlOi <= 0;
			ni11ll <= 0;
			ni11Ol <= 0;
		end
		else if  (nl0ill == 1'b0) 
		if (clk_2 != ni11Oi_clk_prev && clk_2 == 1'b1) 
		begin
			n0OiiO <= wire_ni1l0i_dataout;
			n0Oili <= wire_ni1l0l_dataout;
			n0Oill <= wire_ni1l0O_dataout;
			n0OilO <= wire_ni1lii_dataout;
			n0OiOi <= wire_ni1lil_dataout;
			n0OiOl <= wire_ni1liO_dataout;
			n0OiOO <= wire_ni1lli_dataout;
			n0Ol0i <= wire_ni1l1O_dataout;
			n0Ol0l <= wire_ni1lOl_dataout;
			n0Ol0O <= wire_ni1lOO_dataout;
			n0Ol1i <= wire_ni1lll_dataout;
			n0Ol1l <= wire_ni1llO_dataout;
			n0Ol1O <= wire_ni1lOi_dataout;
			n0Olii <= wire_ni1O1i_dataout;
			n0Olil <= wire_ni1O1l_dataout;
			n0OliO <= wire_ni1O1O_dataout;
			n0Olli <= wire_ni1O0i_dataout;
			n0Olll <= wire_ni1O0l_dataout;
			n0OllO <= wire_ni1O0O_dataout;
			n0OlOi <= wire_ni1Oii_dataout;
			ni11ll <= wire_ni000l_dataout;
			ni11Ol <= wire_ni00ii_dataout;
		end
		ni11Oi_clk_prev <= clk_2;
	end
	assign
		wire_ni11Oi_CLRN = ((nliOlli52 ^ nliOlli51) & (~ nll00iO)),
		wire_ni11Oi_PRN = (nliOliO54 ^ nliOliO53);
	initial
	begin
		n0i = 0;
		nil = 0;
	end
	always @ (clk_2 or hard_reset or wire_nii_CLRN)
	begin
		if (hard_reset == 1'b1) 
		begin
			n0i <= 1;
			nil <= 1;
		end
		else if  (wire_nii_CLRN == 1'b0) 
		begin
			n0i <= 0;
			nil <= 0;
		end
		else 
		if (clk_2 != nii_clk_prev && clk_2 == 1'b1) 
		begin
			n0i <= wire_niO_dataout;
			nil <= n0i;
		end
		nii_clk_prev <= clk_2;
	end
	assign
		wire_nii_CLRN = (nll000l4 ^ nll000l3);
	initial
	begin
		nii00O = 0;
		nii11i = 0;
		nlO0i1i = 0;
		nlO0l0l = 0;
	end
	always @ ( posedge clk_2 or  posedge nll00iO)
	begin
		if (nll00iO == 1'b1) 
		begin
			nii00O <= 1;
			nii11i <= 1;
			nlO0i1i <= 1;
			nlO0l0l <= 1;
		end
		else 
		begin
			nii00O <= wire_niiOlO_dataout;
			nii11i <= wire_niilil_dataout;
			nlO0i1i <= wire_nlOi1ii_dataout;
			nlO0l0l <= wire_nlOi0ll_dataout;
		end
	end
	initial
	begin
		n1O = 0;
		nO = 0;
	end
	always @ (clk_1 or nll00iO or wire_nl_CLRN)
	begin
		if (nll00iO == 1'b1) 
		begin
			n1O <= 1;
			nO <= 1;
		end
		else if  (wire_nl_CLRN == 1'b0) 
		begin
			n1O <= 0;
			nO <= 0;
		end
		else 
		if (clk_1 != nl_clk_prev && clk_1 == 1'b1) 
		begin
			n1O <= nll001l;
			nO <= n1O;
		end
		nl_clk_prev <= clk_1;
	end
	assign
		wire_nl_CLRN = (nll00li2 ^ nll00li1);
	initial
	begin
		n1i10l = 0;
		n1i10O = 0;
		n1i1ii = 0;
		niO0li = 0;
		nl0liO = 0;
		nl0lli = 0;
		nl0llO = 0;
		nlOllil = 0;
	end
	always @ ( posedge clk_1 or  negedge wire_nl0lll_PRN)
	begin
		if (wire_nl0lll_PRN == 1'b0) 
		begin
			n1i10l <= 1;
			n1i10O <= 1;
			n1i1ii <= 1;
			niO0li <= 1;
			nl0liO <= 1;
			nl0lli <= 1;
			nl0llO <= 1;
			nlOllil <= 1;
		end
		else 
		begin
			n1i10l <= wire_n1i1lO_dataout;
			n1i10O <= wire_n1i1Oi_dataout;
			n1i1ii <= wire_n1i1Ol_dataout;
			niO0li <= wire_niOl0O_dataout;
			nl0liO <= wire_nl0O1l_dataout;
			nl0lli <= wire_nl0O1O_dataout;
			nl0llO <= wire_nl0O0i_dataout;
			nlOllil <= wire_nlOO10i_dataout;
		end
	end
	assign
		wire_nl0lll_PRN = ((nll111O50 ^ nll111O49) & (~ wire_n1l_dataout));
	initial
	begin
		n00lii = 0;
		n00lil = 0;
		n0OlOl = 0;
		n0OlOO = 0;
		n0OO0i = 0;
		n0OO0l = 0;
		n0OO0O = 0;
		n0OO1i = 0;
		n0OO1l = 0;
		n0OO1O = 0;
		n0OOii = 0;
		n0OOil = 0;
		n0OOiO = 0;
		n0OOli = 0;
		n0OOll = 0;
		n0OOlO = 0;
		n0OOOi = 0;
		n0OOOl = 0;
		n0OOOO = 0;
		n1000i = 0;
		n1000l = 0;
		n1000O = 0;
		n1001i = 0;
		n1001l = 0;
		n1001O = 0;
		n100ii = 0;
		n101Oi = 0;
		n101Ol = 0;
		n101OO = 0;
		n10i0i = 0;
		n10i0l = 0;
		n10i0O = 0;
		n10i1O = 0;
		n10iii = 0;
		n10iil = 0;
		n10ili = 0;
		n10ill = 0;
		n10ilO = 0;
		n10iOi = 0;
		n10liO = 0;
		n10O0i = 0;
		n10O0l = 0;
		n10O1O = 0;
		n11OiO = 0;
		n1ii0l = 0;
		n1l10i = 0;
		n1l10l = 0;
		n1l10O = 0;
		n1l11i = 0;
		n1l11l = 0;
		n1l11O = 0;
		n1l1ii = 0;
		n1O00O = 0;
		n1O0il = 0;
		n1O0iO = 0;
		n1O0li = 0;
		n1O0ll = 0;
		n1O0lO = 0;
		n1O0Oi = 0;
		n1O1Oi = 0;
		ni0O0O = 0;
		ni0Oii = 0;
		ni0Oil = 0;
		ni0OiO = 0;
		ni0Oli = 0;
		ni0Oll = 0;
		ni0OlO = 0;
		ni0OOi = 0;
		ni0OOl = 0;
		ni0OOO = 0;
		ni101i = 0;
		ni101l = 0;
		ni110i = 0;
		ni110l = 0;
		ni110O = 0;
		ni111i = 0;
		ni111l = 0;
		ni111O = 0;
		ni11ii = 0;
		ni11il = 0;
		ni11iO = 0;
		ni11li = 0;
		ni11lO = 0;
		ni11OO = 0;
		nii00i = 0;
		nii01i = 0;
		nii01l = 0;
		nii01O = 0;
		nii0ii = 0;
		nii0il = 0;
		nii0iO = 0;
		nii0li = 0;
		nii0ll = 0;
		nii0lO = 0;
		nii0Oi = 0;
		nii0Ol = 0;
		nii0OO = 0;
		nii10i = 0;
		nii10l = 0;
		nii10O = 0;
		nii11l = 0;
		nii11O = 0;
		nii1ii = 0;
		nii1il = 0;
		nii1iO = 0;
		nii1li = 0;
		nii1ll = 0;
		nii1lO = 0;
		nii1Oi = 0;
		nii1Ol = 0;
		nii1OO = 0;
		niii0i = 0;
		niii0l = 0;
		niii0O = 0;
		niii1i = 0;
		niii1l = 0;
		niii1O = 0;
		niiiii = 0;
		niiiil = 0;
		niiiiO = 0;
		niiili = 0;
		nl000i = 0;
		nl000l = 0;
		nl000O = 0;
		nl001i = 0;
		nl001l = 0;
		nl00ii = 0;
		nl011i = 0;
		nl011l = 0;
		nl011O = 0;
		nl01Ol = 0;
		nl01OO = 0;
		nl0i1l = 0;
		nl0iiO = 0;
		nl0ili = 0;
		nl0ill = 0;
		nl1l0l = 0;
		nl1OiO = 0;
		nl1Oli = 0;
		nl1Oll = 0;
		nl1OlO = 0;
		nl1OOi = 0;
		nl1OOl = 0;
		nl1OOO = 0;
		nliOlO = 0;
		nll00ll = 0;
		nll00lO = 0;
		nll10l = 0;
		nll11l = 0;
		nllO0OO = 0;
		nllOi0i = 0;
		nllOi0l = 0;
		nllOi0O = 0;
		nllOi1i = 0;
		nllOi1l = 0;
		nllOi1O = 0;
		nllOiii = 0;
		nllOiil = 0;
		nllOiiO = 0;
		nllOili = 0;
		nllOilO = 0;
		nllOiOO = 0;
		nllOl1i = 0;
		nllOl1l = 0;
		nlO000O = 0;
		nlO00ii = 0;
		nlO00il = 0;
		nlO00iO = 0;
		nlO00li = 0;
		nlO00ll = 0;
		nlO00lO = 0;
		nlO00Oi = 0;
		nlO00Ol = 0;
		nlO00OO = 0;
		nlO0i0i = 0;
		nlO0i0l = 0;
		nlO0i0O = 0;
		nlO0i1l = 0;
		nlO0i1O = 0;
		nlO0iii = 0;
		nlO0iil = 0;
		nlO0iiO = 0;
		nlO0ili = 0;
		nlO0ill = 0;
		nlO0ilO = 0;
		nlO0iOi = 0;
		nlO0iOl = 0;
		nlO0iOO = 0;
		nlO0l0i = 0;
		nlO0l0O = 0;
		nlO0l1i = 0;
		nlO0l1l = 0;
		nlO0l1O = 0;
		nlO0lii = 0;
		nlO0lil = 0;
		nlO0liO = 0;
		nlO0lli = 0;
		nlO0lll = 0;
		nlO0llO = 0;
		nlO0lOi = 0;
		nlO0lOl = 0;
		nlO0lOO = 0;
		nlO0O0i = 0;
		nlO0O0l = 0;
		nlO0O0O = 0;
		nlO0O1i = 0;
		nlO0O1l = 0;
		nlO0O1O = 0;
		nlO0Oii = 0;
		nlO0Oil = 0;
		nlO0OiO = 0;
	end
	always @ ( posedge clk_2 or  negedge wire_nll10i_CLRN)
	begin
		if (wire_nll10i_CLRN == 1'b0) 
		begin
			n00lii <= 0;
			n00lil <= 0;
			n0OlOl <= 0;
			n0OlOO <= 0;
			n0OO0i <= 0;
			n0OO0l <= 0;
			n0OO0O <= 0;
			n0OO1i <= 0;
			n0OO1l <= 0;
			n0OO1O <= 0;
			n0OOii <= 0;
			n0OOil <= 0;
			n0OOiO <= 0;
			n0OOli <= 0;
			n0OOll <= 0;
			n0OOlO <= 0;
			n0OOOi <= 0;
			n0OOOl <= 0;
			n0OOOO <= 0;
			n1000i <= 0;
			n1000l <= 0;
			n1000O <= 0;
			n1001i <= 0;
			n1001l <= 0;
			n1001O <= 0;
			n100ii <= 0;
			n101Oi <= 0;
			n101Ol <= 0;
			n101OO <= 0;
			n10i0i <= 0;
			n10i0l <= 0;
			n10i0O <= 0;
			n10i1O <= 0;
			n10iii <= 0;
			n10iil <= 0;
			n10ili <= 0;
			n10ill <= 0;
			n10ilO <= 0;
			n10iOi <= 0;
			n10liO <= 0;
			n10O0i <= 0;
			n10O0l <= 0;
			n10O1O <= 0;
			n11OiO <= 0;
			n1ii0l <= 0;
			n1l10i <= 0;
			n1l10l <= 0;
			n1l10O <= 0;
			n1l11i <= 0;
			n1l11l <= 0;
			n1l11O <= 0;
			n1l1ii <= 0;
			n1O00O <= 0;
			n1O0il <= 0;
			n1O0iO <= 0;
			n1O0li <= 0;
			n1O0ll <= 0;
			n1O0lO <= 0;
			n1O0Oi <= 0;
			n1O1Oi <= 0;
			ni0O0O <= 0;
			ni0Oii <= 0;
			ni0Oil <= 0;
			ni0OiO <= 0;
			ni0Oli <= 0;
			ni0Oll <= 0;
			ni0OlO <= 0;
			ni0OOi <= 0;
			ni0OOl <= 0;
			ni0OOO <= 0;
			ni101i <= 0;
			ni101l <= 0;
			ni110i <= 0;
			ni110l <= 0;
			ni110O <= 0;
			ni111i <= 0;
			ni111l <= 0;
			ni111O <= 0;
			ni11ii <= 0;
			ni11il <= 0;
			ni11iO <= 0;
			ni11li <= 0;
			ni11lO <= 0;
			ni11OO <= 0;
			nii00i <= 0;
			nii01i <= 0;
			nii01l <= 0;
			nii01O <= 0;
			nii0ii <= 0;
			nii0il <= 0;
			nii0iO <= 0;
			nii0li <= 0;
			nii0ll <= 0;
			nii0lO <= 0;
			nii0Oi <= 0;
			nii0Ol <= 0;
			nii0OO <= 0;
			nii10i <= 0;
			nii10l <= 0;
			nii10O <= 0;
			nii11l <= 0;
			nii11O <= 0;
			nii1ii <= 0;
			nii1il <= 0;
			nii1iO <= 0;
			nii1li <= 0;
			nii1ll <= 0;
			nii1lO <= 0;
			nii1Oi <= 0;
			nii1Ol <= 0;
			nii1OO <= 0;
			niii0i <= 0;
			niii0l <= 0;
			niii0O <= 0;
			niii1i <= 0;
			niii1l <= 0;
			niii1O <= 0;
			niiiii <= 0;
			niiiil <= 0;
			niiiiO <= 0;
			niiili <= 0;
			nl000i <= 0;
			nl000l <= 0;
			nl000O <= 0;
			nl001i <= 0;
			nl001l <= 0;
			nl00ii <= 0;
			nl011i <= 0;
			nl011l <= 0;
			nl011O <= 0;
			nl01Ol <= 0;
			nl01OO <= 0;
			nl0i1l <= 0;
			nl0iiO <= 0;
			nl0ili <= 0;
			nl0ill <= 0;
			nl1l0l <= 0;
			nl1OiO <= 0;
			nl1Oli <= 0;
			nl1Oll <= 0;
			nl1OlO <= 0;
			nl1OOi <= 0;
			nl1OOl <= 0;
			nl1OOO <= 0;
			nliOlO <= 0;
			nll00ll <= 0;
			nll00lO <= 0;
			nll10l <= 0;
			nll11l <= 0;
			nllO0OO <= 0;
			nllOi0i <= 0;
			nllOi0l <= 0;
			nllOi0O <= 0;
			nllOi1i <= 0;
			nllOi1l <= 0;
			nllOi1O <= 0;
			nllOiii <= 0;
			nllOiil <= 0;
			nllOiiO <= 0;
			nllOili <= 0;
			nllOilO <= 0;
			nllOiOO <= 0;
			nllOl1i <= 0;
			nllOl1l <= 0;
			nlO000O <= 0;
			nlO00ii <= 0;
			nlO00il <= 0;
			nlO00iO <= 0;
			nlO00li <= 0;
			nlO00ll <= 0;
			nlO00lO <= 0;
			nlO00Oi <= 0;
			nlO00Ol <= 0;
			nlO00OO <= 0;
			nlO0i0i <= 0;
			nlO0i0l <= 0;
			nlO0i0O <= 0;
			nlO0i1l <= 0;
			nlO0i1O <= 0;
			nlO0iii <= 0;
			nlO0iil <= 0;
			nlO0iiO <= 0;
			nlO0ili <= 0;
			nlO0ill <= 0;
			nlO0ilO <= 0;
			nlO0iOi <= 0;
			nlO0iOl <= 0;
			nlO0iOO <= 0;
			nlO0l0i <= 0;
			nlO0l0O <= 0;
			nlO0l1i <= 0;
			nlO0l1l <= 0;
			nlO0l1O <= 0;
			nlO0lii <= 0;
			nlO0lil <= 0;
			nlO0liO <= 0;
			nlO0lli <= 0;
			nlO0lll <= 0;
			nlO0llO <= 0;
			nlO0lOi <= 0;
			nlO0lOl <= 0;
			nlO0lOO <= 0;
			nlO0O0i <= 0;
			nlO0O0l <= 0;
			nlO0O0O <= 0;
			nlO0O1i <= 0;
			nlO0O1l <= 0;
			nlO0O1O <= 0;
			nlO0Oii <= 0;
			nlO0Oil <= 0;
			nlO0OiO <= 0;
		end
		else 
		begin
			n00lii <= wire_n00lli_dataout;
			n00lil <= wire_n00lll_dataout;
			n0OlOl <= wire_ni101O_dataout;
			n0OlOO <= wire_ni100i_dataout;
			n0OO0i <= wire_ni10il_dataout;
			n0OO0l <= wire_ni10iO_dataout;
			n0OO0O <= wire_ni10li_dataout;
			n0OO1i <= wire_ni100l_dataout;
			n0OO1l <= wire_ni100O_dataout;
			n0OO1O <= wire_ni10ii_dataout;
			n0OOii <= wire_ni10ll_dataout;
			n0OOil <= wire_ni10lO_dataout;
			n0OOiO <= wire_ni10Oi_dataout;
			n0OOli <= wire_ni10Ol_dataout;
			n0OOll <= wire_ni10OO_dataout;
			n0OOlO <= wire_ni1i1i_dataout;
			n0OOOi <= wire_ni1i1l_dataout;
			n0OOOl <= wire_ni1i1O_dataout;
			n0OOOO <= wire_ni1i0i_dataout;
			n1000i <= wire_n100OO_dataout;
			n1000l <= wire_n10i1i_dataout;
			n1000O <= wire_n10i1l_dataout;
			n1001i <= wire_n100lO_dataout;
			n1001l <= wire_n100Oi_dataout;
			n1001O <= wire_n100Ol_dataout;
			n100ii <= n10i1O;
			n101Oi <= wire_n100iO_dataout;
			n101Ol <= wire_n100li_dataout;
			n101OO <= wire_n100ll_dataout;
			n10i0i <= n10i0l;
			n10i0l <= sync_status;
			n10i0O <= n10iii;
			n10i1O <= (rgenericfifo & rdenable);
			n10iii <= align_status;
			n10iil <= wire_n10iOO_dataout;
			n10ili <= wire_n10l1i_dataout;
			n10ill <= wire_n10l1l_dataout;
			n10ilO <= wire_n10l1O_dataout;
			n10iOi <= wire_n10l0i_dataout;
			n10liO <= n10O1O;
			n10O0i <= wire_n10Oii_dataout;
			n10O0l <= wire_n10Oil_dataout;
			n10O1O <= n10O0l;
			n11OiO <= wire_n100il_dataout;
			n1ii0l <= wire_n1l1iO_dataout;
			n1l10i <= wire_n1l1Oi_dataout;
			n1l10l <= wire_n1l1Ol_dataout;
			n1l10O <= wire_n1l1OO_dataout;
			n1l11i <= wire_n1l1li_dataout;
			n1l11l <= wire_n1l1ll_dataout;
			n1l11O <= wire_n1l1lO_dataout;
			n1l1ii <= wire_n1l01i_dataout;
			n1O00O <= wire_n1Ol1O_dataout;
			n1O0il <= wire_n1Ol0l_dataout;
			n1O0iO <= wire_n1Ol0i_dataout;
			n1O0li <= wire_n1O0OO_dataout;
			n1O0ll <= wire_n1Oi1i_dataout;
			n1O0lO <= wire_n1Oi1l_dataout;
			n1O0Oi <= wire_n1Ol1l_dataout;
			n1O1Oi <= wire_n1O0ii_dataout;
			ni0O0O <= wire_niiiOi_dataout;
			ni0Oii <= wire_niiiOl_dataout;
			ni0Oil <= wire_niiiOO_dataout;
			ni0OiO <= wire_niil1i_dataout;
			ni0Oli <= wire_niil1l_dataout;
			ni0Oll <= wire_niil1O_dataout;
			ni0OlO <= wire_niil0i_dataout;
			ni0OOi <= wire_niil0l_dataout;
			ni0OOl <= wire_niil0O_dataout;
			ni0OOO <= wire_niilii_dataout;
			ni101i <= wire_ni1l1l_dataout;
			ni101l <= wire_niiilO_dataout;
			ni110i <= wire_ni1iil_dataout;
			ni110l <= wire_ni1iiO_dataout;
			ni110O <= wire_ni1ili_dataout;
			ni111i <= wire_ni1i0l_dataout;
			ni111l <= wire_ni1i0O_dataout;
			ni111O <= wire_ni1iii_dataout;
			ni11ii <= wire_ni1ill_dataout;
			ni11il <= wire_ni1ilO_dataout;
			ni11iO <= wire_ni1iOi_dataout;
			ni11li <= wire_ni1iOl_dataout;
			ni11lO <= wire_ni1iOO_dataout;
			ni11OO <= wire_ni1l1i_dataout;
			nii00i <= wire_niiOll_dataout;
			nii01i <= wire_niiOil_dataout;
			nii01l <= wire_niiOiO_dataout;
			nii01O <= wire_niiOli_dataout;
			nii0ii <= wire_niiOOi_dataout;
			nii0il <= wire_niiOOl_dataout;
			nii0iO <= wire_niiOOO_dataout;
			nii0li <= wire_nil11i_dataout;
			nii0ll <= wire_nil11l_dataout;
			nii0lO <= wire_nil11O_dataout;
			nii0Oi <= wire_nil10i_dataout;
			nii0Ol <= wire_nil10l_dataout;
			nii0OO <= wire_nil10O_dataout;
			nii10i <= wire_niilll_dataout;
			nii10l <= wire_niillO_dataout;
			nii10O <= wire_niilOi_dataout;
			nii11l <= wire_niiliO_dataout;
			nii11O <= wire_niilli_dataout;
			nii1ii <= wire_niilOl_dataout;
			nii1il <= wire_niilOO_dataout;
			nii1iO <= wire_niiO1i_dataout;
			nii1li <= wire_niiO1l_dataout;
			nii1ll <= wire_niiO1O_dataout;
			nii1lO <= wire_niiO0i_dataout;
			nii1Oi <= wire_niiO0l_dataout;
			nii1Ol <= wire_niiO0O_dataout;
			nii1OO <= wire_niiOii_dataout;
			niii0i <= wire_nil1li_dataout;
			niii0l <= wire_nil1ll_dataout;
			niii0O <= wire_nil1lO_dataout;
			niii1i <= wire_nil1ii_dataout;
			niii1l <= wire_nil1il_dataout;
			niii1O <= wire_nil1iO_dataout;
			niiiii <= wire_nil1Oi_dataout;
			niiiil <= wire_nil1Ol_dataout;
			niiiiO <= wire_nil1OO_dataout;
			niiili <= wire_nil01i_dataout;
			nl000i <= wire_nl00li_dataout;
			nl000l <= wire_nl00ll_dataout;
			nl000O <= wire_nl00lO_dataout;
			nl001i <= sync_status;
			nl001l <= wire_nl00iO_dataout;
			nl00ii <= wire_nl00Oi_dataout;
			nl011i <= wire_nl01lO_dataout;
			nl011l <= wire_nl01Oi_dataout;
			nl011O <= nl01Ol;
			nl01Ol <= (rgenericfifo & rdenable);
			nl01OO <= nl001i;
			nl0i1l <= nl0iiO;
			nl0iiO <= nl0ill;
			nl0ili <= wire_nl0iOi_dataout;
			nl0ill <= wire_nl0iOl_dataout;
			nl1l0l <= wire_nl010i_dataout;
			nl1OiO <= wire_nl010l_dataout;
			nl1Oli <= wire_nl010O_dataout;
			nl1Oll <= wire_nl01ii_dataout;
			nl1OlO <= wire_nl01il_dataout;
			nl1OOi <= wire_nl01iO_dataout;
			nl1OOl <= wire_nl01li_dataout;
			nl1OOO <= wire_nl01ll_dataout;
			nliOlO <= wire_nll11O_dataout;
			nll00ll <= wire_nll00Ol_dataout;
			nll00lO <= wire_nll00OO_dataout;
			nll10l <= wire_nll1ii_dataout;
			nll11l <= wire_nll1il_dataout;
			nllO0OO <= wire_nllOl1O_dataout;
			nllOi0i <= wire_nllOlii_dataout;
			nllOi0l <= wire_nllOlil_dataout;
			nllOi0O <= wire_nllOliO_dataout;
			nllOi1i <= wire_nllOl0i_dataout;
			nllOi1l <= wire_nllOl0l_dataout;
			nllOi1O <= wire_nllOl0O_dataout;
			nllOiii <= wire_nllOlli_dataout;
			nllOiil <= wire_nllOlll_dataout;
			nllOiiO <= wire_nllOllO_dataout;
			nllOili <= wire_nllOlOi_dataout;
			nllOilO <= wire_nllOlOl_dataout;
			nllOiOO <= wire_nllOlOO_dataout;
			nllOl1i <= wire_nllOO1i_dataout;
			nllOl1l <= wire_nlO0Oll_dataout;
			nlO000O <= wire_nlO0OlO_dataout;
			nlO00ii <= wire_nlO0OOi_dataout;
			nlO00il <= wire_nlO0OOl_dataout;
			nlO00iO <= wire_nlO0OOO_dataout;
			nlO00li <= wire_nlOi11i_dataout;
			nlO00ll <= wire_nlOi11l_dataout;
			nlO00lO <= wire_nlOi11O_dataout;
			nlO00Oi <= wire_nlOi10i_dataout;
			nlO00Ol <= wire_nlOi10l_dataout;
			nlO00OO <= wire_nlOi10O_dataout;
			nlO0i0i <= wire_nlOi1li_dataout;
			nlO0i0l <= wire_nlOi1ll_dataout;
			nlO0i0O <= wire_nlOi1lO_dataout;
			nlO0i1l <= wire_nlOi1il_dataout;
			nlO0i1O <= wire_nlOi1iO_dataout;
			nlO0iii <= wire_nlOi1Oi_dataout;
			nlO0iil <= wire_nlOi1Ol_dataout;
			nlO0iiO <= wire_nlOi1OO_dataout;
			nlO0ili <= wire_nlOi01i_dataout;
			nlO0ill <= wire_nlOi01l_dataout;
			nlO0ilO <= wire_nlOi01O_dataout;
			nlO0iOi <= wire_nlOi00i_dataout;
			nlO0iOl <= wire_nlOi00l_dataout;
			nlO0iOO <= wire_nlOi00O_dataout;
			nlO0l0i <= wire_nlOi0li_dataout;
			nlO0l0O <= wire_nlOi0lO_dataout;
			nlO0l1i <= wire_nlOi0ii_dataout;
			nlO0l1l <= wire_nlOi0il_dataout;
			nlO0l1O <= wire_nlOi0iO_dataout;
			nlO0lii <= wire_nlOi0Oi_dataout;
			nlO0lil <= wire_nlOi0Ol_dataout;
			nlO0liO <= wire_nlOi0OO_dataout;
			nlO0lli <= wire_nlOii1i_dataout;
			nlO0lll <= wire_nlOii1l_dataout;
			nlO0llO <= wire_nlOii1O_dataout;
			nlO0lOi <= wire_nlOii0i_dataout;
			nlO0lOl <= wire_nlOii0l_dataout;
			nlO0lOO <= wire_nlOii0O_dataout;
			nlO0O0i <= wire_nlOiili_dataout;
			nlO0O0l <= wire_nlOiill_dataout;
			nlO0O0O <= wire_nlOiilO_dataout;
			nlO0O1i <= wire_nlOiiii_dataout;
			nlO0O1l <= wire_nlOiiil_dataout;
			nlO0O1O <= wire_nlOiiiO_dataout;
			nlO0Oii <= wire_nlOiiOi_dataout;
			nlO0Oil <= wire_nlOiiOl_dataout;
			nlO0OiO <= wire_nlOiiOO_dataout;
		end
	end
	assign
		wire_nll10i_CLRN = ((nll10il48 ^ nll10il47) & (~ nll00iO));
	initial
	begin
		nlllOiO = 0;
		nlllOli = 0;
		nlllOll = 0;
		nlllOlO = 0;
		nlllOOi = 0;
		nlllOOl = 0;
		nlllOOO = 0;
		nllO00i = 0;
		nllO00l = 0;
		nllO00O = 0;
		nllO01i = 0;
		nllO01l = 0;
		nllO01O = 0;
		nllO0ii = 0;
		nllO0il = 0;
		nllO0iO = 0;
		nllO0li = 0;
		nllO0ll = 0;
		nllO0lO = 0;
		nllO0Oi = 0;
		nllO0Ol = 0;
		nllO10i = 0;
		nllO10l = 0;
		nllO10O = 0;
		nllO11i = 0;
		nllO11l = 0;
		nllO11O = 0;
		nllO1ii = 0;
		nllO1il = 0;
		nllO1iO = 0;
		nllO1li = 0;
		nllO1ll = 0;
		nllO1lO = 0;
		nllO1Oi = 0;
		nllO1Ol = 0;
		nllO1OO = 0;
		nllOill = 0;
		nllOiOl = 0;
	end
	always @ (clk_2 or wire_nllOiOi_PRN or nll00iO)
	begin
		if (wire_nllOiOi_PRN == 1'b0) 
		begin
			nlllOiO <= 1;
			nlllOli <= 1;
			nlllOll <= 1;
			nlllOlO <= 1;
			nlllOOi <= 1;
			nlllOOl <= 1;
			nlllOOO <= 1;
			nllO00i <= 1;
			nllO00l <= 1;
			nllO00O <= 1;
			nllO01i <= 1;
			nllO01l <= 1;
			nllO01O <= 1;
			nllO0ii <= 1;
			nllO0il <= 1;
			nllO0iO <= 1;
			nllO0li <= 1;
			nllO0ll <= 1;
			nllO0lO <= 1;
			nllO0Oi <= 1;
			nllO0Ol <= 1;
			nllO10i <= 1;
			nllO10l <= 1;
			nllO10O <= 1;
			nllO11i <= 1;
			nllO11l <= 1;
			nllO11O <= 1;
			nllO1ii <= 1;
			nllO1il <= 1;
			nllO1iO <= 1;
			nllO1li <= 1;
			nllO1ll <= 1;
			nllO1lO <= 1;
			nllO1Oi <= 1;
			nllO1Ol <= 1;
			nllO1OO <= 1;
			nllOill <= 1;
			nllOiOl <= 1;
		end
		else if  (nll00iO == 1'b1) 
		begin
			nlllOiO <= 0;
			nlllOli <= 0;
			nlllOll <= 0;
			nlllOlO <= 0;
			nlllOOi <= 0;
			nlllOOl <= 0;
			nlllOOO <= 0;
			nllO00i <= 0;
			nllO00l <= 0;
			nllO00O <= 0;
			nllO01i <= 0;
			nllO01l <= 0;
			nllO01O <= 0;
			nllO0ii <= 0;
			nllO0il <= 0;
			nllO0iO <= 0;
			nllO0li <= 0;
			nllO0ll <= 0;
			nllO0lO <= 0;
			nllO0Oi <= 0;
			nllO0Ol <= 0;
			nllO10i <= 0;
			nllO10l <= 0;
			nllO10O <= 0;
			nllO11i <= 0;
			nllO11l <= 0;
			nllO11O <= 0;
			nllO1ii <= 0;
			nllO1il <= 0;
			nllO1iO <= 0;
			nllO1li <= 0;
			nllO1ll <= 0;
			nllO1lO <= 0;
			nllO1Oi <= 0;
			nllO1Ol <= 0;
			nllO1OO <= 0;
			nllOill <= 0;
			nllOiOl <= 0;
		end
		else if  (nlilO1O == 1'b0) 
		if (clk_2 != nllOiOi_clk_prev && clk_2 == 1'b1) 
		begin
			nlllOiO <= wire_nllOOOO_dataout;
			nlllOli <= wire_nlO111i_dataout;
			nlllOll <= wire_nlO111l_dataout;
			nlllOlO <= wire_nlO111O_dataout;
			nlllOOi <= wire_nlO110i_dataout;
			nlllOOl <= wire_nlO110l_dataout;
			nlllOOO <= wire_nlO110O_dataout;
			nllO00i <= wire_nllOO1O_dataout;
			nllO00l <= wire_nllOO0i_dataout;
			nllO00O <= wire_nllOO0l_dataout;
			nllO01i <= wire_nlO100O_dataout;
			nllO01l <= wire_nlO10ii_dataout;
			nllO01O <= wire_nllOO1l_dataout;
			nllO0ii <= wire_nllOO0O_dataout;
			nllO0il <= wire_nllOOii_dataout;
			nllO0iO <= wire_nllOOil_dataout;
			nllO0li <= wire_nllOOiO_dataout;
			nllO0ll <= wire_nllOOli_dataout;
			nllO0lO <= wire_nllOOll_dataout;
			nllO0Oi <= wire_nllOOlO_dataout;
			nllO0Ol <= wire_nllOOOi_dataout;
			nllO10i <= wire_nlO11li_dataout;
			nllO10l <= wire_nlO11ll_dataout;
			nllO10O <= wire_nllOOOl_dataout;
			nllO11i <= wire_nlO11ii_dataout;
			nllO11l <= wire_nlO11il_dataout;
			nllO11O <= wire_nlO11iO_dataout;
			nllO1ii <= wire_nlO11lO_dataout;
			nllO1il <= wire_nlO11Oi_dataout;
			nllO1iO <= wire_nlO11Ol_dataout;
			nllO1li <= wire_nlO11OO_dataout;
			nllO1ll <= wire_nlO101i_dataout;
			nllO1lO <= wire_nlO101l_dataout;
			nllO1Oi <= wire_nlO101O_dataout;
			nllO1Ol <= wire_nlO100i_dataout;
			nllO1OO <= wire_nlO100l_dataout;
			nllOill <= wire_nlO1i0i_dataout;
			nllOiOl <= wire_nlO1i0O_dataout;
		end
		nllOiOi_clk_prev <= clk_2;
	end
	assign
		wire_nllOiOi_PRN = (nlill0l56 ^ nlill0l55);
	initial
	begin
		n00liO = 0;
		n10iOl = 0;
		n10O0O = 0;
		n110il = 0;
		n110iO = 0;
		n11O0l = 0;
		n11O0O = 0;
		n11Oii = 0;
		n11Oil = 0;
		n1i11i = 0;
		n1i11l = 0;
		n1i1il = 0;
		n1i1iO = 0;
		n1i1li = 0;
		n1ii0i = 0;
		n1ii1i = 0;
		n1ii1l = 0;
		n1ii1O = 0;
		n1l0lO = 0;
		n1l0Oi = 0;
		n1l0Ol = 0;
		n1l0OO = 0;
		n1l1il = 0;
		n1li1i = 0;
		n1li1l = 0;
		n1O0Ol = 0;
		n1O1lO = 0;
		n1Olil = 0;
		n1Olll = 0;
		n1OllO = 0;
		n1OlOi = 0;
		n1OlOl = 0;
		n1OlOO = 0;
		niiill = 0;
		niO00i = 0;
		niO00l = 0;
		niO00O = 0;
		niO01i = 0;
		niO01l = 0;
		niO01O = 0;
		niO0ii = 0;
		niO0il = 0;
		niO0iO = 0;
		niO0ll = 0;
		niO0lO = 0;
		niO0Oi = 0;
		niO0Ol = 0;
		niO0OO = 0;
		niO1ll = 0;
		niO1lO = 0;
		niO1Oi = 0;
		niO1Ol = 0;
		niO1OO = 0;
		niOi0i = 0;
		niOi0l = 0;
		niOi0O = 0;
		niOi1i = 0;
		niOi1l = 0;
		niOi1O = 0;
		niOiii = 0;
		niOiil = 0;
		niOiiO = 0;
		niOili = 0;
		niOill = 0;
		niOilO = 0;
		niOiOi = 0;
		niOiOl = 0;
		niOiOO = 0;
		nl00il = 0;
		nl0ilO = 0;
		nl0l0l = 0;
		nl0l0O = 0;
		nl0lOi = 0;
		nl0lOl = 0;
		nl0lOO = 0;
		nl1iii = 0;
		nl1iil = 0;
		nl1l0i = 0;
		nl1l1i = 0;
		nl1l1l = 0;
		nl1l1O = 0;
		nli10O = 0;
		nli1ii = 0;
		nli1il = 0;
		nli1iO = 0;
		nli1li = 0;
		nliiiO = 0;
		nliili = 0;
		nliill = 0;
		nliilO = 0;
		nliiOi = 0;
		nliOll = 0;
		nll00i = 0;
		nll00l = 0;
		nll00Oi = 0;
		nll10O = 0;
		nll1Ol = 0;
		nll1OO = 0;
		nlO00i = 0;
		nlO00l = 0;
		nlO00O = 0;
		nlO01i = 0;
		nlO01l = 0;
		nlO01O = 0;
		nlO0ii = 0;
		nlO0il = 0;
		nlO0iO = 0;
		nlO0li = 0;
		nlO0ll = 0;
		nlO0lO = 0;
		nlO0Oi = 0;
		nlO0Ol = 0;
		nlO0Oli = 0;
		nlO0OO = 0;
		nlO1li = 0;
		nlO1ll = 0;
		nlO1lO = 0;
		nlO1Oi = 0;
		nlO1Ol = 0;
		nlO1OO = 0;
		nlOi0i = 0;
		nlOi0l = 0;
		nlOi0O = 0;
		nlOi1i = 0;
		nlOi1l = 0;
		nlOi1O = 0;
		nlOill = 0;
		nlOilO = 0;
		nlOliiO = 0;
		nlOlili = 0;
		nlOlill = 0;
		nlOlilO = 0;
		nlOliOi = 0;
		nlOliOl = 0;
		nlOliOO = 0;
		nlOll0i = 0;
		nlOll0l = 0;
		nlOll0O = 0;
		nlOll1i = 0;
		nlOll1l = 0;
		nlOll1O = 0;
		nlOllii = 0;
		nlOlliO = 0;
		nlOllli = 0;
		nlOllll = 0;
		nlOlllO = 0;
		nlOllOi = 0;
		nlOllOl = 0;
		nlOllOO = 0;
		nlOlO0i = 0;
		nlOlO0l = 0;
		nlOlO0O = 0;
		nlOlO1i = 0;
		nlOlO1l = 0;
		nlOlO1O = 0;
		nlOlOii = 0;
		nlOlOil = 0;
		nlOlOiO = 0;
		nlOlOli = 0;
		nlOlOll = 0;
		nlOlOlO = 0;
		nlOlOO = 0;
		nlOlOOi = 0;
		nlOO1l = 0;
	end
	always @ ( posedge clk_1 or  negedge wire_nlOO1i_CLRN)
	begin
		if (wire_nlOO1i_CLRN == 1'b0) 
		begin
			n00liO <= 0;
			n10iOl <= 0;
			n10O0O <= 0;
			n110il <= 0;
			n110iO <= 0;
			n11O0l <= 0;
			n11O0O <= 0;
			n11Oii <= 0;
			n11Oil <= 0;
			n1i11i <= 0;
			n1i11l <= 0;
			n1i1il <= 0;
			n1i1iO <= 0;
			n1i1li <= 0;
			n1ii0i <= 0;
			n1ii1i <= 0;
			n1ii1l <= 0;
			n1ii1O <= 0;
			n1l0lO <= 0;
			n1l0Oi <= 0;
			n1l0Ol <= 0;
			n1l0OO <= 0;
			n1l1il <= 0;
			n1li1i <= 0;
			n1li1l <= 0;
			n1O0Ol <= 0;
			n1O1lO <= 0;
			n1Olil <= 0;
			n1Olll <= 0;
			n1OllO <= 0;
			n1OlOi <= 0;
			n1OlOl <= 0;
			n1OlOO <= 0;
			niiill <= 0;
			niO00i <= 0;
			niO00l <= 0;
			niO00O <= 0;
			niO01i <= 0;
			niO01l <= 0;
			niO01O <= 0;
			niO0ii <= 0;
			niO0il <= 0;
			niO0iO <= 0;
			niO0ll <= 0;
			niO0lO <= 0;
			niO0Oi <= 0;
			niO0Ol <= 0;
			niO0OO <= 0;
			niO1ll <= 0;
			niO1lO <= 0;
			niO1Oi <= 0;
			niO1Ol <= 0;
			niO1OO <= 0;
			niOi0i <= 0;
			niOi0l <= 0;
			niOi0O <= 0;
			niOi1i <= 0;
			niOi1l <= 0;
			niOi1O <= 0;
			niOiii <= 0;
			niOiil <= 0;
			niOiiO <= 0;
			niOili <= 0;
			niOill <= 0;
			niOilO <= 0;
			niOiOi <= 0;
			niOiOl <= 0;
			niOiOO <= 0;
			nl00il <= 0;
			nl0ilO <= 0;
			nl0l0l <= 0;
			nl0l0O <= 0;
			nl0lOi <= 0;
			nl0lOl <= 0;
			nl0lOO <= 0;
			nl1iii <= 0;
			nl1iil <= 0;
			nl1l0i <= 0;
			nl1l1i <= 0;
			nl1l1l <= 0;
			nl1l1O <= 0;
			nli10O <= 0;
			nli1ii <= 0;
			nli1il <= 0;
			nli1iO <= 0;
			nli1li <= 0;
			nliiiO <= 0;
			nliili <= 0;
			nliill <= 0;
			nliilO <= 0;
			nliiOi <= 0;
			nliOll <= 0;
			nll00i <= 0;
			nll00l <= 0;
			nll00Oi <= 0;
			nll10O <= 0;
			nll1Ol <= 0;
			nll1OO <= 0;
			nlO00i <= 0;
			nlO00l <= 0;
			nlO00O <= 0;
			nlO01i <= 0;
			nlO01l <= 0;
			nlO01O <= 0;
			nlO0ii <= 0;
			nlO0il <= 0;
			nlO0iO <= 0;
			nlO0li <= 0;
			nlO0ll <= 0;
			nlO0lO <= 0;
			nlO0Oi <= 0;
			nlO0Ol <= 0;
			nlO0Oli <= 0;
			nlO0OO <= 0;
			nlO1li <= 0;
			nlO1ll <= 0;
			nlO1lO <= 0;
			nlO1Oi <= 0;
			nlO1Ol <= 0;
			nlO1OO <= 0;
			nlOi0i <= 0;
			nlOi0l <= 0;
			nlOi0O <= 0;
			nlOi1i <= 0;
			nlOi1l <= 0;
			nlOi1O <= 0;
			nlOill <= 0;
			nlOilO <= 0;
			nlOliiO <= 0;
			nlOlili <= 0;
			nlOlill <= 0;
			nlOlilO <= 0;
			nlOliOi <= 0;
			nlOliOl <= 0;
			nlOliOO <= 0;
			nlOll0i <= 0;
			nlOll0l <= 0;
			nlOll0O <= 0;
			nlOll1i <= 0;
			nlOll1l <= 0;
			nlOll1O <= 0;
			nlOllii <= 0;
			nlOlliO <= 0;
			nlOllli <= 0;
			nlOllll <= 0;
			nlOlllO <= 0;
			nlOllOi <= 0;
			nlOllOl <= 0;
			nlOllOO <= 0;
			nlOlO0i <= 0;
			nlOlO0l <= 0;
			nlOlO0O <= 0;
			nlOlO1i <= 0;
			nlOlO1l <= 0;
			nlOlO1O <= 0;
			nlOlOii <= 0;
			nlOlOil <= 0;
			nlOlOiO <= 0;
			nlOlOli <= 0;
			nlOlOll <= 0;
			nlOlOlO <= 0;
			nlOlOO <= 0;
			nlOlOOi <= 0;
			nlOO1l <= 0;
		end
		else 
		begin
			n00liO <= wire_n00llO_dataout;
			n10iOl <= wire_n10lli_dataout;
			n10O0O <= n1i11i;
			n110il <= (rgenericfifo & wrenable);
			n110iO <= wire_n11Oli_dataout;
			n11O0l <= wire_n11Oll_dataout;
			n11O0O <= wire_n11OlO_dataout;
			n11Oii <= wire_n11OOi_dataout;
			n11Oil <= wire_n11OOl_dataout;
			n1i11i <= nliO0li;
			n1i11l <= wire_n1i1ll_dataout;
			n1i1il <= wire_n1i1OO_dataout;
			n1i1iO <= wire_n1i01i_dataout;
			n1i1li <= wire_n1ii0O_dataout;
			n1ii0i <= wire_n1iili_dataout;
			n1ii1i <= wire_n1iiii_dataout;
			n1ii1l <= wire_n1iiil_dataout;
			n1ii1O <= wire_n1iiiO_dataout;
			n1l0lO <= wire_n1li0i_dataout;
			n1l0Oi <= wire_n1li0l_dataout;
			n1l0Ol <= wire_n1li0O_dataout;
			n1l0OO <= wire_n1liii_dataout;
			n1l1il <= wire_n1li1O_dataout;
			n1li1i <= wire_n1liil_dataout;
			n1li1l <= wire_n1O1Ol_dataout;
			n1O0Ol <= wire_n1OliO_dataout;
			n1O1lO <= wire_n1O1OO_dataout;
			n1Olil <= (rclkcmpsqmd & (wire_n01i0i_dataout & (((nliOi1O | n1OlOl) | n1OlOi) | n1OllO)));
			n1Olll <= wire_n1OO1i_dataout;
			n1OllO <= wire_n1OO1O_dataout;
			n1OlOi <= wire_n1OO0l_dataout;
			n1OlOl <= wire_n1OOiO_dataout;
			n1OlOO <= wire_n0111O_dataout;
			niiill <= wire_niOl1i_dataout;
			niO00i <= wire_nl1i1i_dataout;
			niO00l <= wire_nl1i1l_dataout;
			niO00O <= wire_nl1i1O_dataout;
			niO01i <= wire_nl10Oi_dataout;
			niO01l <= wire_nl10Ol_dataout;
			niO01O <= wire_nl10OO_dataout;
			niO0ii <= wire_nl1i0i_dataout;
			niO0il <= wire_nl1i0l_dataout;
			niO0iO <= wire_nl1i0O_dataout;
			niO0ll <= wire_niOlii_dataout;
			niO0lO <= wire_niOlil_dataout;
			niO0Oi <= wire_niOliO_dataout;
			niO0Ol <= wire_niOlli_dataout;
			niO0OO <= wire_niOlll_dataout;
			niO1ll <= wire_niOl1l_dataout;
			niO1lO <= wire_niOl1O_dataout;
			niO1Oi <= wire_niOl0i_dataout;
			niO1Ol <= wire_niOl0l_dataout;
			niO1OO <= wire_nl10lO_dataout;
			niOi0i <= wire_niOlOO_dataout;
			niOi0l <= wire_niOO1i_dataout;
			niOi0O <= wire_niOO1l_dataout;
			niOi1i <= wire_niOllO_dataout;
			niOi1l <= wire_niOlOi_dataout;
			niOi1O <= wire_niOlOl_dataout;
			niOiii <= wire_niOO1O_dataout;
			niOiil <= wire_niOO0i_dataout;
			niOiiO <= wire_niOO0l_dataout;
			niOili <= wire_niOO0O_dataout;
			niOill <= wire_niOOii_dataout;
			niOilO <= wire_niOOil_dataout;
			niOiOi <= wire_niOOiO_dataout;
			niOiOl <= wire_niOOli_dataout;
			niOiOO <= nl1iii;
			nl00il <= wire_nl0i1O_dataout;
			nl0ilO <= nl0l0l;
			nl0l0l <= nll100l;
			nl0l0O <= wire_nl0O1i_dataout;
			nl0lOi <= wire_nl0O0l_dataout;
			nl0lOl <= wire_nl0O0O_dataout;
			nl0lOO <= wire_nli1ll_dataout;
			nl1iii <= (rgenericfifo & wrenable);
			nl1iil <= wire_nl1l0O_dataout;
			nl1l0i <= wire_nl1lli_dataout;
			nl1l1i <= wire_nl1lii_dataout;
			nl1l1l <= wire_nl1lil_dataout;
			nl1l1O <= wire_nl1liO_dataout;
			nli10O <= wire_nli1lO_dataout;
			nli1ii <= wire_nli1Oi_dataout;
			nli1il <= wire_nli1Ol_dataout;
			nli1iO <= wire_nli1OO_dataout;
			nli1li <= wire_nliiOl_dataout;
			nliiiO <= wire_nliiOO_dataout;
			nliili <= wire_nlil1i_dataout;
			nliill <= wire_nlil1l_dataout;
			nliilO <= wire_nlil1O_dataout;
			nliiOi <= wire_nliOOi_dataout;
			nliOll <= wire_nliOOl_dataout;
			nll00i <= wire_nll0Ol_dataout;
			nll00l <= sudi[0];
			nll00Oi <= wire_nll0i1i_dataout;
			nll10O <= wire_nll01i_dataout;
			nll1Ol <= wire_nll01l_dataout;
			nll1OO <= wire_nll00O_dataout;
			nlO00i <= sudi[10];
			nlO00l <= sudi[11];
			nlO00O <= sudi[12];
			nlO01i <= sudi[7];
			nlO01l <= sudi[8];
			nlO01O <= sudi[9];
			nlO0ii <= sudi[13];
			nlO0il <= sudi[14];
			nlO0iO <= sudi[15];
			nlO0li <= sudi[16];
			nlO0ll <= sudi[17];
			nlO0lO <= sudi[18];
			nlO0Oi <= sudi[19];
			nlO0Ol <= sudi[20];
			nlO0Oli <= wire_nlOlOOl_dataout;
			nlO0OO <= sudi[21];
			nlO1li <= sudi[1];
			nlO1ll <= sudi[2];
			nlO1lO <= sudi[3];
			nlO1Oi <= sudi[4];
			nlO1Ol <= sudi[5];
			nlO1OO <= sudi[6];
			nlOi0i <= sudi[25];
			nlOi0l <= sudi[26];
			nlOi0O <= sudi[27];
			nlOi1i <= sudi[22];
			nlOi1l <= sudi[23];
			nlOi1O <= sudi[24];
			nlOill <= wire_nlOiOl_o;
			nlOilO <= wire_nlOiOO_o;
			nlOliiO <= wire_nlOlOOO_dataout;
			nlOlili <= wire_nlOO11i_dataout;
			nlOlill <= wire_nlOO11l_dataout;
			nlOlilO <= wire_nlOO11O_dataout;
			nlOliOi <= wire_n111Oi_dataout;
			nlOliOl <= wire_n111Ol_dataout;
			nlOliOO <= wire_n111OO_dataout;
			nlOll0i <= wire_n1100i_dataout;
			nlOll0l <= wire_n1100l_dataout;
			nlOll0O <= wire_n1100O_dataout;
			nlOll1i <= wire_n1101i_dataout;
			nlOll1l <= wire_n1101l_dataout;
			nlOll1O <= wire_n1101O_dataout;
			nlOllii <= wire_n110ii_dataout;
			nlOlliO <= wire_nlOO10l_dataout;
			nlOllli <= wire_nlOO10O_dataout;
			nlOllll <= wire_nlOO1ii_dataout;
			nlOlllO <= wire_nlOO1il_dataout;
			nlOllOi <= wire_nlOO1iO_dataout;
			nlOllOl <= wire_nlOO1li_dataout;
			nlOllOO <= wire_nlOO1ll_dataout;
			nlOlO0i <= wire_nlOO1OO_dataout;
			nlOlO0l <= wire_nlOO01i_dataout;
			nlOlO0O <= wire_nlOO01l_dataout;
			nlOlO1i <= wire_nlOO1lO_dataout;
			nlOlO1l <= wire_nlOO1Oi_dataout;
			nlOlO1O <= wire_nlOO1Ol_dataout;
			nlOlOii <= wire_nlOO01O_dataout;
			nlOlOil <= wire_nlOO00i_dataout;
			nlOlOiO <= wire_nlOO00l_dataout;
			nlOlOli <= wire_nlOO00O_dataout;
			nlOlOll <= wire_nlOO0ii_dataout;
			nlOlOlO <= wire_nlOO0il_dataout;
			nlOlOO <= wire_nlOl1i_o;
			nlOlOOi <= n110il;
			nlOO1l <= wire_nlOiOi_o;
		end
	end
	assign
		wire_nlOO1i_CLRN = ((nll1O1O24 ^ nll1O1O23) & (~ wire_n1l_dataout));
	assign		wire_n0000l_dataout = (rskpsetbased === 1'b1) ? (nliOl1i | nliOiOO) : (nliOl1O | nliOl1l);
	assign		wire_n0010i_dataout = (dskwclksel[1] === 1'b1) ? audi[11] : sudi[11];
	assign		wire_n0010l_dataout = (dskwclksel[1] === 1'b1) ? audi[13] : sudi[13];
	assign		wire_n0011i_dataout = (dskwclksel[1] === 1'b1) ? audi[7] : sudi[7];
	assign		wire_n0011l_dataout = (dskwclksel[1] === 1'b1) ? audi[8] : sudi[8];
	assign		wire_n0011O_dataout = (dskwclksel[1] === 1'b1) ? audi[9] : sudi[9];
	or(wire_n001lO_dataout, (rskpsetbased & (nliOiOl | nliOiOi)), ((~ rskpsetbased) & (((~ rclkcmppos) & nliOilO) | nliOill)));
	assign		wire_n00i_dataout = (rwa_6g_en === 1'b1) ? niiiiO : nlO0Oil;
	assign		wire_n00i0i_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[10] : rclkcmpsq1p[0];
	assign		wire_n00i0l_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[11] : rclkcmpsq1p[1];
	assign		wire_n00i0O_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[12] : rclkcmpsq1p[2];
	assign		wire_n00iii_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[13] : rclkcmpsq1p[3];
	assign		wire_n00iil_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[14] : rclkcmpsq1p[4];
	assign		wire_n00iiO_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[15] : rclkcmpsq1p[5];
	assign		wire_n00ili_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[16] : rclkcmpsq1p[6];
	assign		wire_n00ill_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[17] : rclkcmpsq1p[7];
	assign		wire_n00ilO_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[18] : rclkcmpsq1p[8];
	assign		wire_n00iOi_dataout = (nliOl0O === 1'b1) ? rclkcmpsq1p[19] : rclkcmpsq1p[9];
	assign		wire_n00l_dataout = (rwa_6g_en === 1'b1) ? niiili : nlO0OiO;
	and(wire_n00lli_dataout, n00lil, ~((~ nll11Oi)));
	and(wire_n00lll_dataout, n00liO, ~((~ nll11Oi)));
	and(wire_n00llO_dataout, wire_nliiil_o, (rgenericfifo | wire_nllili_dataout));
	assign		wire_n00O_dataout = (rwa_6g_en === 1'b1) ? wire_nli10l_o : wire_n1i0OO_o;
	assign		wire_n0100i_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[9] : sudi_pre[9];
	assign		wire_n0100l_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[10] : sudi_pre[10];
	assign		wire_n0100O_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[12] : sudi_pre[12];
	assign		wire_n0101i_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[6] : sudi_pre[6];
	assign		wire_n0101l_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[7] : sudi_pre[7];
	assign		wire_n0101O_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[8] : sudi_pre[8];
	assign		wire_n010ii_dataout = (dskwclksel[1] === 1'b1) ? audi[10] : sudi[10];
	assign		wire_n010il_dataout = (dskwclksel[1] === 1'b1) ? audi[12] : sudi[12];
	and(wire_n010ll_dataout, wire_n010lO_dataout, ~(nliOiii));
	assign		wire_n010lO_dataout = (nliOi0l === 1'b1) ? align_status_sync_0 : wire_n010Oi_dataout;
	assign		wire_n010Oi_dataout = (nliOi0i === 1'b1) ? align_status_sync_2 : wire_n010Ol_dataout;
	assign		wire_n010Ol_dataout = (dskwclksel[1] === 1'b1) ? n10i0O : n10i0i;
	and(wire_n0111O_dataout, nll1OlO, (wire_n01i0i_dataout & ((~ nliOl0O) | ((~ wire_n010il_dataout) & ((~ wire_n010ii_dataout) & n1O0Ol)))));
	assign		wire_n011li_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[0] : sudi_pre[0];
	assign		wire_n011ll_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[1] : sudi_pre[1];
	assign		wire_n011lO_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[2] : sudi_pre[2];
	assign		wire_n011Oi_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[3] : sudi_pre[3];
	assign		wire_n011Ol_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[4] : sudi_pre[4];
	assign		wire_n011OO_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[5] : sudi_pre[5];
	assign		wire_n01i_dataout = (rwa_6g_en === 1'b1) ? niii0O : nlO0O0l;
	and(wire_n01i0i_dataout, wire_n01i0l_dataout, ~(nliOiii));
	assign		wire_n01i0l_dataout = (dskwclksel[1] === 1'b1) ? align_status : sync_status;
	assign		wire_n01i0O_dataout = (nliOili === 1'b1) ? n10iil : wire_n01i0l_dataout;
	assign		wire_n01iii_dataout = (nliOiil === 1'b1) ? nllO0OO : wire_n01lil_dataout;
	assign		wire_n01iil_dataout = (nliOiil === 1'b1) ? nllOi1i : wire_n01liO_dataout;
	assign		wire_n01iiO_dataout = (nliOiil === 1'b1) ? nllOi1l : wire_n01lli_dataout;
	assign		wire_n01ili_dataout = (nliOiil === 1'b1) ? nllOi1O : wire_n01lll_dataout;
	assign		wire_n01ill_dataout = (nliOiil === 1'b1) ? nllOi0i : wire_n01llO_dataout;
	assign		wire_n01ilO_dataout = (nliOiil === 1'b1) ? nllOi0l : wire_n01lOi_dataout;
	assign		wire_n01iOi_dataout = (nliOiil === 1'b1) ? nllOi0O : wire_n01lOl_dataout;
	assign		wire_n01iOl_dataout = (nliOiil === 1'b1) ? nllOiii : wire_n01lOO_dataout;
	assign		wire_n01iOO_dataout = (nliOiil === 1'b1) ? nllOiil : wire_n01O1i_dataout;
	assign		wire_n01l_dataout = (rwa_6g_en === 1'b1) ? niiiii : nlO0O0O;
	assign		wire_n01l0i_dataout = (nliOiil === 1'b1) ? nllOilO : wire_n01O0l_dataout;
	assign		wire_n01l0l_dataout = (nliOiil === 1'b1) ? nllOiOl : wire_n01O0O_dataout;
	and(wire_n01l0O_dataout, wire_n01Oii_dataout, ~(nliOiil));
	assign		wire_n01l1i_dataout = (nliOiil === 1'b1) ? nllOiiO : wire_n01O1l_dataout;
	assign		wire_n01l1l_dataout = (nliOiil === 1'b1) ? nllOili : wire_n01O1O_dataout;
	assign		wire_n01l1O_dataout = (nliOiil === 1'b1) ? nllOill : wire_n01O0i_dataout;
	or(wire_n01lii_dataout, wire_n01Oil_dataout, nliOiil);
	assign		wire_n01lil_dataout = (nliOili === 1'b1) ? nllO0OO : wire_n01OiO_dataout;
	assign		wire_n01liO_dataout = (nliOili === 1'b1) ? nllOi1i : wire_n01Oli_dataout;
	assign		wire_n01lli_dataout = (nliOili === 1'b1) ? nllOi1l : wire_n01Oll_dataout;
	assign		wire_n01lll_dataout = (nliOili === 1'b1) ? nllOi1O : wire_n01OlO_dataout;
	assign		wire_n01llO_dataout = (nliOili === 1'b1) ? nllOi0i : wire_n01OOi_dataout;
	assign		wire_n01lOi_dataout = (nliOili === 1'b1) ? nllOi0l : wire_n01OOl_dataout;
	assign		wire_n01lOl_dataout = (nliOili === 1'b1) ? nllOi0O : wire_n01OOO_dataout;
	assign		wire_n01lOO_dataout = (nliOili === 1'b1) ? nllOiii : wire_n0011i_dataout;
	assign		wire_n01O_dataout = (rwa_6g_en === 1'b1) ? niiiil : nlO0Oii;
	assign		wire_n01O0i_dataout = (nliOili === 1'b1) ? nllOill : wire_n0010i_dataout;
	assign		wire_n01O0l_dataout = (nliOili === 1'b1) ? nllOilO : wire_n010il_dataout;
	assign		wire_n01O0O_dataout = (nliOili === 1'b1) ? nllOiOl : wire_n0010l_dataout;
	assign		wire_n01O1i_dataout = (nliOili === 1'b1) ? nllOiil : wire_n0011l_dataout;
	assign		wire_n01O1l_dataout = (nliOili === 1'b1) ? nllOiiO : wire_n0011O_dataout;
	assign		wire_n01O1O_dataout = (nliOili === 1'b1) ? nllOili : wire_n010ii_dataout;
	and(wire_n01Oii_dataout, nllOiOO, nliOili);
	and(wire_n01Oil_dataout, nllOl1i, nliOili);
	assign		wire_n01OiO_dataout = (dskwclksel[1] === 1'b1) ? audi[0] : sudi[0];
	assign		wire_n01Oli_dataout = (dskwclksel[1] === 1'b1) ? audi[1] : sudi[1];
	assign		wire_n01Oll_dataout = (dskwclksel[1] === 1'b1) ? audi[2] : sudi[2];
	assign		wire_n01OlO_dataout = (dskwclksel[1] === 1'b1) ? audi[3] : sudi[3];
	assign		wire_n01OOi_dataout = (dskwclksel[1] === 1'b1) ? audi[4] : sudi[4];
	assign		wire_n01OOl_dataout = (dskwclksel[1] === 1'b1) ? audi[5] : sudi[5];
	assign		wire_n01OOO_dataout = (dskwclksel[1] === 1'b1) ? audi[6] : sudi[6];
	assign		wire_n0ii_dataout = (rwa_6g_en === 1'b1) ? wire_nliOOO_o : wire_n1O00i_o;
	assign		wire_n0il_dataout = (rwa_6g_en === 1'b1) ? wire_nll11i_o : wire_n1O00l_o;
	assign		wire_n0iO_dataout = (rwa_6g_en === 1'b1) ? ((((nll01Oi | nll01lO) | (~ (nll01li8 ^ nll01li7))) | nll01iO) | (~ (nll01ii10 ^ nll01ii9))) : ((nll001i | nll01OO) | nll01Ol);
	assign		wire_n0li_dataout = (rwa_6g_en === 1'b1) ? wire_nlliOi_dataout : wire_n01iii_dataout;
	assign		wire_n0ll_dataout = (rwa_6g_en === 1'b1) ? wire_nlliOl_dataout : wire_n01iil_dataout;
	assign		wire_n0lO_dataout = (rwa_6g_en === 1'b1) ? wire_nlliOO_dataout : wire_n01iiO_dataout;
	and(wire_n0O_dataout, nil, ~(scan_mode));
	assign		wire_n0Oi_dataout = (rwa_6g_en === 1'b1) ? wire_nlll1i_dataout : wire_n01ili_dataout;
	assign		wire_n0Ol_dataout = (rwa_6g_en === 1'b1) ? wire_nlll1l_dataout : wire_n01ill_dataout;
	assign		wire_n0OO_dataout = (rwa_6g_en === 1'b1) ? wire_nlll1O_dataout : wire_n01ilO_dataout;
	and(wire_n100il_dataout, n1001l, ~(nliO1Oi));
	and(wire_n100iO_dataout, n1001O, ~(nliO1Oi));
	and(wire_n100li_dataout, n1000i, ~(nliO1Oi));
	and(wire_n100ll_dataout, n1000l, ~(nliO1Oi));
	and(wire_n100lO_dataout, n1000O, ~(nliO1Oi));
	and(wire_n100Oi_dataout, n110iO, ~(nliO1Oi));
	and(wire_n100Ol_dataout, n11O0l, ~(nliO1Oi));
	and(wire_n100OO_dataout, n11O0O, ~(nliO1Oi));
	assign		wire_n1010i_dataout = (nliO10O === 1'b1) ? n11Oil : wire_n101lO_o[4];
	assign		wire_n1011i_dataout = (nliO10O === 1'b1) ? n11O0l : (wire_n101il_o[2] | wire_n101il_o[1]);
	assign		wire_n1011l_dataout = (nliO10O === 1'b1) ? n11O0O : (wire_n101lO_o[2] | wire_n101lO_o[1]);
	assign		wire_n1011O_dataout = (nliO10O === 1'b1) ? n11Oii : nlilOll;
	assign		wire_n10i_dataout = (rwa_6g_en === 1'b1) ? nii0iO : nlO0lil;
	and(wire_n10i1i_dataout, n11Oii, ~(nliO1Oi));
	and(wire_n10i1l_dataout, n11Oil, ~(nliO1Oi));
	and(wire_n10iOO_dataout, (((~ rgenericfifo) & n10ilO) | nlilOlO), ~(nliO1Oi));
	assign		wire_n10l_dataout = (rwa_6g_en === 1'b1) ? nii0li : nlO0liO;
	and(wire_n10l0i_dataout, ((~ rgenericfifo) & n10iOl), ~(nliO1Oi));
	and(wire_n10l1i_dataout, n10ill, ~(nliO1Oi));
	and(wire_n10l1l_dataout, nlOill, ~(nliO1Oi));
	and(wire_n10l1O_dataout, n10iOi, ~(nliO1Oi));
	and(wire_n10lli_dataout, wire_n10lll_dataout, wire_n01i0i_dataout);
	or(wire_n10lll_dataout, n10iOl, ((~ n10iOl) & nlilOOi));
	assign		wire_n10lOi_dataout = (nliOi0l === 1'b1) ? fifo_rd_in_comp_0 : wire_n10lOl_dataout;
	assign		wire_n10lOl_dataout = (nliOi0i === 1'b1) ? fifo_rd_in_comp_2 : n10ilO;
	assign		wire_n10lOO_dataout = (rdwidth_rx === 1'b1) ? (nlilOOl | n10liO) : nlilOOl;
	assign		wire_n10O_dataout = (rwa_6g_en === 1'b1) ? nii0ll : nlO0lli;
	and(wire_n10Oii_dataout, nll00ll, ~(nliO1Oi));
	and(wire_n10Oil_dataout, (((n10ilO & nll00ll) & (~ n10O0i)) & (rskpsetbased | nlilOOO)), ~(nliO1Oi));
	assign		wire_n10OOi_dataout = (rdwidth_rx === 1'b1) ? (nliO11i | n10O0O) : nliO11i;
	and(wire_n1100i_dataout, nlO000O, ~(nliO0il));
	and(wire_n1100l_dataout, nlO00ii, ~(nliO0il));
	and(wire_n1100O_dataout, nlO00il, ~(nliO0il));
	and(wire_n1101i_dataout, nlOll0O, ~(nliO0il));
	and(wire_n1101l_dataout, nlOllii, ~(nliO0il));
	and(wire_n1101O_dataout, nllOl1l, ~(nliO0il));
	and(wire_n110ii_dataout, nlO00iO, ~(nliO0il));
	assign		wire_n110ll_dataout = (nll010i === 1'b1) ? disable_fifo_rd_0 : nll1O0l;
	and(wire_n1111i_dataout, wire_n1110i_o[3], ~(nlillOi));
	and(wire_n1111l_dataout, wire_n1110i_o[4], ~(nlillOi));
	or(wire_n1111O_dataout, wire_n1110i_o[5], nlillOi);
	and(wire_n111ii_dataout, wire_n111lO_o[0], ~(nlillOO));
	and(wire_n111il_dataout, wire_n111lO_o[1], ~(nlillOO));
	and(wire_n111iO_dataout, wire_n111lO_o[2], ~(nlillOO));
	and(wire_n111li_dataout, wire_n111lO_o[3], ~(nlillOO));
	and(wire_n111ll_dataout, wire_n111lO_o[4], ~(nlillOO));
	and(wire_n111Oi_dataout, nlOll1O, ~(nliO0il));
	and(wire_n111Ol_dataout, nlOll0i, ~(nliO0il));
	and(wire_n111OO_dataout, nlOll0l, ~(nliO0il));
	assign		wire_n11i_dataout = (rwa_6g_en === 1'b1) ? nii00O : nlO0l0l;
	assign		wire_n11l_dataout = (rwa_6g_en === 1'b1) ? nii0ii : nlO0l0O;
	assign		wire_n11O_dataout = (rwa_6g_en === 1'b1) ? nii0il : nlO0lii;
	and(wire_n11Oli_dataout, wire_n11OOO_dataout, ~(nliO0il));
	and(wire_n11Oll_dataout, wire_n1011i_dataout, ~(nliO0il));
	and(wire_n11OlO_dataout, wire_n1011l_dataout, ~(nliO0il));
	and(wire_n11OOi_dataout, wire_n1011O_dataout, ~(nliO0il));
	and(wire_n11OOl_dataout, wire_n1010i_dataout, ~(nliO0il));
	assign		wire_n11OOO_dataout = (nliO10O === 1'b1) ? n110iO : nlilOli;
	assign		wire_n1i_dataout = (rwa_6g_en === 1'b1) ? nli1iO : n1ii0i;
	assign		wire_n1i00l_dataout = (rdwidth_rx === 1'b1) ? (nliO10l | n1i11l) : nliO10l;
	and(wire_n1i01i_dataout, wire_n1i00l_dataout, ~(nliO0il));
	assign		wire_n1i01l_dataout = (rdwidth_rx === 1'b1) ? (nliO10i | n1i10l) : nliO10i;
	assign		wire_n1i0iO_dataout = (((((~ ralempty[0]) & (~ ralempty[1])) & (~ ralempty[2])) & (~ ralempty[3])) === 1'b1) ? wire_n1O00l_o : wire_n1i0li_o;
	assign		wire_n1i0lO_dataout = (((((~ ralfull[0]) & (~ ralfull[1])) & (~ ralfull[2])) & (~ ralfull[3])) === 1'b1) ? wire_n1O00i_o : wire_n1i0Oi_o;
	and(wire_n1i1ll_dataout, n1i1il, ~(nliO0il));
	or(wire_n1i1lO_dataout, n1i10O, nliO0il);
	or(wire_n1i1Oi_dataout, wire_n1i0iO_dataout, nliO0il);
	or(wire_n1i1Ol_dataout, wire_n1i01l_dataout, nliO0il);
	and(wire_n1i1OO_dataout, wire_n1i0lO_dataout, ~(nliO0il));
	assign		wire_n1ii_dataout = (rwa_6g_en === 1'b1) ? nii0lO : nlO0lll;
	and(wire_n1ii0O_dataout, wire_n1iill_dataout, ~(nliO0il));
	and(wire_n1iiii_dataout, wire_n1iilO_dataout, ~(nliO0il));
	and(wire_n1iiil_dataout, wire_n1iiOi_dataout, ~(nliO0il));
	and(wire_n1iiiO_dataout, wire_n1iiOl_dataout, ~(nliO0il));
	and(wire_n1iili_dataout, wire_n1iiOO_dataout, ~(nliO0il));
	assign		wire_n1iill_dataout = (nliO10O === 1'b1) ? n1i1li : wire_n1il1l_dataout;
	assign		wire_n1iilO_dataout = (nliO10O === 1'b1) ? n1ii1i : wire_n1il1O_dataout;
	assign		wire_n1iiOi_dataout = (nliO10O === 1'b1) ? n1ii1l : wire_n1il0i_dataout;
	assign		wire_n1iiOl_dataout = (nliO10O === 1'b1) ? n1ii1O : wire_n1il0l_dataout;
	assign		wire_n1iiOO_dataout = (nliO10O === 1'b1) ? n1ii0i : wire_n1il0O_dataout;
	assign		wire_n1il_dataout = (rwa_6g_en === 1'b1) ? nii0Oi : nlO0llO;
	assign		wire_n1il0i_dataout = (wire_n1illi_o === 1'b1) ? wire_n1iliO_o[3] : wire_n1ilii_o[3];
	assign		wire_n1il0l_dataout = (wire_n1illi_o === 1'b1) ? wire_n1iliO_o[4] : wire_n1ilii_o[4];
	assign		wire_n1il0O_dataout = (wire_n1illi_o === 1'b1) ? wire_n1iliO_o[5] : wire_n1ilii_o[5];
	assign		wire_n1il1l_dataout = (wire_n1illi_o === 1'b1) ? wire_n1iliO_o[1] : wire_n1ilii_o[1];
	assign		wire_n1il1O_dataout = (wire_n1illi_o === 1'b1) ? wire_n1iliO_o[2] : wire_n1ilii_o[2];
	assign		wire_n1illl_dataout = (nll010i === 1'b1) ? disable_fifo_wr_0 : nll1O0i;
	assign		wire_n1iO_dataout = (rwa_6g_en === 1'b1) ? nii0Ol : nlO0lOi;
	and(wire_n1l_dataout, nO, ~(scan_mode));
	and(wire_n1l00i_dataout, n1l11l, ~(wire_n110ll_dataout));
	and(wire_n1l00l_dataout, n1l11O, ~(wire_n110ll_dataout));
	and(wire_n1l00O_dataout, n1l10i, ~(wire_n110ll_dataout));
	and(wire_n1l01i_dataout, wire_n1l0il_dataout, ~(nliO1Oi));
	and(wire_n1l01l_dataout, n1ii0l, ~(wire_n110ll_dataout));
	and(wire_n1l01O_dataout, n1l11i, ~(wire_n110ll_dataout));
	and(wire_n1l0ii_dataout, n1l10l, ~(wire_n110ll_dataout));
	and(wire_n1l0il_dataout, n1l10O, ~(wire_n110ll_dataout));
	and(wire_n1l1iO_dataout, wire_n110ll_dataout, ~(nliO1Oi));
	and(wire_n1l1li_dataout, wire_n1l01l_dataout, ~(nliO1Oi));
	and(wire_n1l1ll_dataout, wire_n1l01O_dataout, ~(nliO1Oi));
	and(wire_n1l1lO_dataout, wire_n1l00i_dataout, ~(nliO1Oi));
	and(wire_n1l1Oi_dataout, wire_n1l00l_dataout, ~(nliO1Oi));
	and(wire_n1l1Ol_dataout, wire_n1l00O_dataout, ~(nliO1Oi));
	and(wire_n1l1OO_dataout, wire_n1l0ii_dataout, ~(nliO1Oi));
	assign		wire_n1li_dataout = (rwa_6g_en === 1'b1) ? nii0OO : nlO0lOl;
	and(wire_n1li0i_dataout, wire_n1liiO_dataout, ~(nliO0il));
	and(wire_n1li0l_dataout, wire_n1lili_dataout, ~(nliO0il));
	and(wire_n1li0O_dataout, wire_n1lill_dataout, ~(nliO0il));
	and(wire_n1li1O_dataout, nll1OOO, ~(nliO0il));
	and(wire_n1liii_dataout, wire_n1lilO_dataout, ~(nliO0il));
	and(wire_n1liil_dataout, wire_n1liOi_dataout, ~(nliO0il));
	assign		wire_n1liiO_dataout = (nliO00i === 1'b1) ? wire_n1lOil_o[0] : wire_n1liOl_dataout;
	assign		wire_n1lili_dataout = (nliO00i === 1'b1) ? wire_n1lOil_o[1] : wire_n1liOO_dataout;
	assign		wire_n1lill_dataout = (nliO00i === 1'b1) ? wire_n1lOil_o[2] : wire_n1ll1i_dataout;
	assign		wire_n1lilO_dataout = (nliO00i === 1'b1) ? wire_n1lOil_o[3] : wire_n1ll1l_dataout;
	assign		wire_n1liOi_dataout = (nliO00i === 1'b1) ? wire_n1lOil_o[4] : wire_n1ll1O_dataout;
	assign		wire_n1liOl_dataout = (nliO01l === 1'b1) ? n1l0lO : wire_n1ll0i_dataout;
	assign		wire_n1liOO_dataout = (nliO01l === 1'b1) ? wire_n1lO0O_o[0] : wire_n1ll0l_dataout;
	assign		wire_n1ll_dataout = (rwa_6g_en === 1'b1) ? niii1i : nlO0lOO;
	assign		wire_n1ll0i_dataout = (nliO01i === 1'b1) ? wire_n1llOO_o[0] : wire_n1lliO_dataout;
	assign		wire_n1ll0l_dataout = (nliO01i === 1'b1) ? wire_n1llOO_o[1] : wire_n1llli_dataout;
	assign		wire_n1ll0O_dataout = (nliO01i === 1'b1) ? wire_n1llOO_o[2] : wire_n1llll_dataout;
	assign		wire_n1ll1i_dataout = (nliO01l === 1'b1) ? wire_n1lO0O_o[1] : wire_n1ll0O_dataout;
	assign		wire_n1ll1l_dataout = (nliO01l === 1'b1) ? wire_n1lO0O_o[2] : wire_n1llii_dataout;
	assign		wire_n1ll1O_dataout = (nliO01l === 1'b1) ? wire_n1lO0O_o[3] : wire_n1llil_dataout;
	assign		wire_n1llii_dataout = (nliO01i === 1'b1) ? wire_n1llOO_o[3] : wire_n1lllO_dataout;
	assign		wire_n1llil_dataout = (nliO01i === 1'b1) ? wire_n1llOO_o[4] : wire_n1llOi_dataout;
	assign		wire_n1lliO_dataout = ((~ nliO1OO) === 1'b1) ? wire_n1llOl_o[1] : n1l0lO;
	assign		wire_n1llli_dataout = ((~ nliO1OO) === 1'b1) ? wire_n1llOl_o[2] : n1l0Oi;
	assign		wire_n1llll_dataout = ((~ nliO1OO) === 1'b1) ? wire_n1llOl_o[3] : n1l0Ol;
	assign		wire_n1lllO_dataout = ((~ nliO1OO) === 1'b1) ? wire_n1llOl_o[4] : n1l0OO;
	assign		wire_n1llOi_dataout = ((~ nliO1OO) === 1'b1) ? wire_n1llOl_o[5] : n1li1i;
	assign		wire_n1lO_dataout = (rwa_6g_en === 1'b1) ? niii1l : nlO0O1i;
	and(wire_n1O0ii_dataout, wire_n001lO_dataout, wire_n010ll_dataout);
	and(wire_n1O0OO_dataout, wire_n1Oi1O_dataout, wire_n010ll_dataout);
	and(wire_n1O1Ol_dataout, nliO0iO, ~(nliO0il));
	and(wire_n1O1OO_dataout, nliO0iO, ~(nliO0il));
	assign		wire_n1Oi_dataout = (rwa_6g_en === 1'b1) ? niii1O : nlO0O1l;
	and(wire_n1Oi0i_dataout, wire_n1Oiii_dataout, ~(nliO0Ol));
	and(wire_n1Oi0l_dataout, wire_n1Oiil_dataout, ~(nliO0Ol));
	assign		wire_n1Oi0O_dataout = (nliO0lO === 1'b1) ? wire_n1OilO_o[0] : wire_n1OiiO_dataout;
	and(wire_n1Oi1i_dataout, wire_n1Oi0i_dataout, wire_n010ll_dataout);
	and(wire_n1Oi1l_dataout, wire_n1Oi0l_dataout, wire_n010ll_dataout);
	or(wire_n1Oi1O_dataout, wire_n1Oi0O_dataout, nliO0Ol);
	assign		wire_n1Oiii_dataout = (nliO0lO === 1'b1) ? wire_n1OilO_o[1] : wire_n1Oili_dataout;
	assign		wire_n1Oiil_dataout = (nliO0lO === 1'b1) ? wire_n1OilO_o[2] : wire_n1Oill_dataout;
	and(wire_n1OiiO_dataout, wire_n1OilO_o[0], nliO0ll);
	and(wire_n1Oili_dataout, wire_n1OilO_o[1], nliO0ll);
	and(wire_n1Oill_dataout, wire_n1OilO_o[2], nliO0ll);
	assign		wire_n1Ol_dataout = (rwa_6g_en === 1'b1) ? niii0i : nlO0O1O;
	and(wire_n1Ol0i_dataout, (rclkcmpsqmd & ((~ n1O0iO) & wire_n110ll_dataout)), wire_n010ll_dataout);
	and(wire_n1Ol0l_dataout, wire_n110ll_dataout, wire_n010ll_dataout);
	and(wire_n1Ol1l_dataout, wire_n0000l_dataout, wire_n010ll_dataout);
	and(wire_n1Ol1O_dataout, n1O0iO, wire_n010ll_dataout);
	and(wire_n1OliO_dataout, (((~ rclkcmppos) & nliOi1i) | nliO0OO), (nliOl0O & wire_n01i0i_dataout));
	assign		wire_n1OO_dataout = (rwa_6g_en === 1'b1) ? niii0l : nlO0O0i;
	and(wire_n1OO0l_dataout, nliOi1l, (wire_n01i0i_dataout & n1OlOl));
	and(wire_n1OO1i_dataout, nliOi1l, (wire_n01i0i_dataout & n1OllO));
	and(wire_n1OO1O_dataout, nliOi1l, (wire_n01i0i_dataout & n1OlOi));
	and(wire_n1OOiO_dataout, nll1OlO, (wire_n01i0i_dataout & (((~ rclkcmpsqmd) & nliOi1O) | n1Olil)));
	assign		wire_ni_dataout = (rwa_6g_en === 1'b1) ? nl0lOl : n1i1iO;
	assign		wire_ni000i_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[10] : wire_ni0l0i_dataout;
	assign		wire_ni000l_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[11] : ni11ll;
	assign		wire_ni000O_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[12] : wire_ni0l0l_dataout;
	assign		wire_ni001i_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[7] : wire_ni0l1i_dataout;
	assign		wire_ni001l_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[8] : wire_ni0l1l_dataout;
	assign		wire_ni001O_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[9] : wire_ni0l1O_dataout;
	assign		wire_ni00ii_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[13] : ni11Ol;
	and(wire_ni00il_dataout, wire_nlOili_data_out1[14], nliOllO);
	or(wire_ni00iO_dataout, wire_nlOili_data_out1[15], ~(nliOllO));
	assign		wire_ni00li_dataout = (nliOlll === 1'b1) ? n0OlOl : wire_ni0l0O_dataout;
	assign		wire_ni00ll_dataout = (nliOlll === 1'b1) ? n0OlOO : wire_ni0lii_dataout;
	assign		wire_ni00lO_dataout = (nliOlll === 1'b1) ? n0OO1i : wire_ni0lil_dataout;
	assign		wire_ni00Oi_dataout = (nliOlll === 1'b1) ? n0OO1l : wire_ni0liO_dataout;
	assign		wire_ni00Ol_dataout = (nliOlll === 1'b1) ? n0OO1O : wire_ni0lli_dataout;
	assign		wire_ni00OO_dataout = (nliOlll === 1'b1) ? n0OO0i : wire_ni0lll_dataout;
	assign		wire_ni010i_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[11] : wire_ni0i0O_dataout;
	assign		wire_ni010l_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[12] : wire_ni0iii_dataout;
	assign		wire_ni010O_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[13] : wire_ni0iil_dataout;
	assign		wire_ni011i_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[8] : wire_ni0i1O_dataout;
	assign		wire_ni011l_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[9] : wire_ni0i0i_dataout;
	assign		wire_ni011O_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[10] : wire_ni0i0l_dataout;
	and(wire_ni01ii_dataout, wire_nlOiiO_data_out1[14], nliOllO);
	or(wire_ni01il_dataout, wire_nlOiiO_data_out1[15], ~(nliOllO));
	assign		wire_ni01iO_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[0] : wire_ni0iiO_dataout;
	assign		wire_ni01li_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[1] : wire_ni0ili_dataout;
	assign		wire_ni01ll_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[2] : wire_ni0ill_dataout;
	assign		wire_ni01lO_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[3] : wire_ni0ilO_dataout;
	assign		wire_ni01Oi_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[4] : wire_ni0iOi_dataout;
	assign		wire_ni01Ol_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[5] : wire_ni0iOl_dataout;
	assign		wire_ni01OO_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out1[6] : wire_ni0iOO_dataout;
	assign		wire_ni0i_dataout = (rwa_6g_en === 1'b1) ? wire_nlllii_dataout : wire_n01l1i_dataout;
	assign		wire_ni0i0i_dataout = (nliOlll === 1'b1) ? n0OOil : wire_ni0lOO_dataout;
	and(wire_ni0i0l_dataout, n0OOiO, nliOlll);
	assign		wire_ni0i0O_dataout = (nliOlll === 1'b1) ? n0OOli : ni11ll;
	assign		wire_ni0i1i_dataout = (nliOlll === 1'b1) ? n0OO0l : wire_ni0llO_dataout;
	assign		wire_ni0i1l_dataout = (nliOlll === 1'b1) ? n0OO0O : wire_ni0lOi_dataout;
	assign		wire_ni0i1O_dataout = (nliOlll === 1'b1) ? n0OOii : wire_ni0lOl_dataout;
	and(wire_ni0iii_dataout, n0OOll, nliOlll);
	assign		wire_ni0iil_dataout = (nliOlll === 1'b1) ? n0OOlO : ni11Ol;
	assign		wire_ni0iiO_dataout = (nliOlll === 1'b1) ? n0OOOO : wire_ni0l0O_dataout;
	assign		wire_ni0ili_dataout = (nliOlll === 1'b1) ? ni111i : wire_ni0lii_dataout;
	assign		wire_ni0ill_dataout = (nliOlll === 1'b1) ? ni111l : wire_ni0lil_dataout;
	assign		wire_ni0ilO_dataout = (nliOlll === 1'b1) ? ni111O : wire_ni0liO_dataout;
	assign		wire_ni0iOi_dataout = (nliOlll === 1'b1) ? ni110i : wire_ni0lli_dataout;
	assign		wire_ni0iOl_dataout = (nliOlll === 1'b1) ? ni110l : wire_ni0lll_dataout;
	assign		wire_ni0iOO_dataout = (nliOlll === 1'b1) ? ni110O : wire_ni0llO_dataout;
	assign		wire_ni0l_dataout = (rwa_6g_en === 1'b1) ? wire_nlllil_dataout : wire_n01l1l_dataout;
	and(wire_ni0l0i_dataout, ni11li, nliOlll);
	and(wire_ni0l0l_dataout, ni11lO, nliOlll);
	assign		wire_ni0l0O_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[10] : rclkcmpsq1n[10];
	assign		wire_ni0l1i_dataout = (nliOlll === 1'b1) ? ni11ii : wire_ni0lOi_dataout;
	assign		wire_ni0l1l_dataout = (nliOlll === 1'b1) ? ni11il : wire_ni0lOl_dataout;
	assign		wire_ni0l1O_dataout = (nliOlll === 1'b1) ? ni11iO : wire_ni0lOO_dataout;
	assign		wire_ni0lii_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[11] : rclkcmpsq1n[11];
	assign		wire_ni0lil_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[12] : rclkcmpsq1n[12];
	assign		wire_ni0liO_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[13] : rclkcmpsq1n[13];
	assign		wire_ni0lli_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[14] : rclkcmpsq1n[14];
	assign		wire_ni0lll_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[15] : rclkcmpsq1n[15];
	assign		wire_ni0llO_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[16] : rclkcmpsq1n[16];
	assign		wire_ni0lOi_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[17] : rclkcmpsq1n[17];
	assign		wire_ni0lOl_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[18] : rclkcmpsq1n[18];
	assign		wire_ni0lOO_dataout = (ni11Ol === 1'b1) ? rclkcmpsq1p[19] : rclkcmpsq1n[19];
	assign		wire_ni0O_dataout = (rwa_6g_en === 1'b1) ? wire_nllliO_dataout : wire_n01l1O_dataout;
	assign		wire_ni0O0i_dataout = (rclkcmpinsertpad === 1'b1) ? (~ ni11Ol) : ni11Ol;
	assign		wire_ni0O0l_dataout = (rclkcmpinsertpad === 1'b1) ? ni11Ol : (~ ni11Ol);
	assign		wire_ni100i_dataout = (nl0ill === 1'b1) ? (~ ni11Ol) : wire_ni1OiO_dataout;
	assign		wire_ni100l_dataout = (nl0ill === 1'b1) ? (~ ni11Ol) : wire_ni1Oli_dataout;
	assign		wire_ni100O_dataout = (nl0ill === 1'b1) ? wire_ni0O0l_dataout : wire_ni1Oll_dataout;
	assign		wire_ni101O_dataout = (nl0ill === 1'b1) ? wire_ni0O0i_dataout : wire_ni1Oil_dataout;
	assign		wire_ni10ii_dataout = (nl0ill === 1'b1) ? (~ ni11Ol) : wire_ni1OlO_dataout;
	assign		wire_ni10il_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni1OOi_dataout;
	assign		wire_ni10iO_dataout = (nl0ill === 1'b1) ? (~ ni11Ol) : wire_ni1OOl_dataout;
	assign		wire_ni10li_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni1OOO_dataout;
	assign		wire_ni10ll_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni011i_dataout;
	assign		wire_ni10lO_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni011l_dataout;
	and(wire_ni10Oi_dataout, wire_ni011O_dataout, ~(nl0ill));
	assign		wire_ni10Ol_dataout = (nl0ill === 1'b1) ? ni11ll : wire_ni010i_dataout;
	and(wire_ni10OO_dataout, wire_ni010l_dataout, ~(nl0ill));
	assign		wire_ni1i_dataout = (rwa_6g_en === 1'b1) ? wire_nlll0i_dataout : wire_n01iOi_dataout;
	assign		wire_ni1i0i_dataout = (nl0ill === 1'b1) ? wire_ni0O0i_dataout : wire_ni01iO_dataout;
	assign		wire_ni1i0l_dataout = (nl0ill === 1'b1) ? (~ ni11Ol) : wire_ni01li_dataout;
	assign		wire_ni1i0O_dataout = (nl0ill === 1'b1) ? (~ ni11Ol) : wire_ni01ll_dataout;
	assign		wire_ni1i1i_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni010O_dataout;
	and(wire_ni1i1l_dataout, wire_ni01ii_dataout, ~(nl0ill));
	or(wire_ni1i1O_dataout, wire_ni01il_dataout, nl0ill);
	assign		wire_ni1iii_dataout = (nl0ill === 1'b1) ? wire_ni0O0l_dataout : wire_ni01lO_dataout;
	assign		wire_ni1iil_dataout = (nl0ill === 1'b1) ? (~ ni11Ol) : wire_ni01Oi_dataout;
	assign		wire_ni1iiO_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni01Ol_dataout;
	assign		wire_ni1ili_dataout = (nl0ill === 1'b1) ? (~ ni11Ol) : wire_ni01OO_dataout;
	assign		wire_ni1ill_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni001i_dataout;
	assign		wire_ni1ilO_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni001l_dataout;
	assign		wire_ni1iOi_dataout = (nl0ill === 1'b1) ? ni11Ol : wire_ni001O_dataout;
	and(wire_ni1iOl_dataout, wire_ni000i_dataout, ~(nl0ill));
	and(wire_ni1iOO_dataout, wire_ni000O_dataout, ~(nl0ill));
	assign		wire_ni1l_dataout = (rwa_6g_en === 1'b1) ? wire_nlll0l_dataout : wire_n01iOl_dataout;
	assign		wire_ni1l0i_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[1] : n0OiiO;
	assign		wire_ni1l0l_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[2] : n0Oili;
	assign		wire_ni1l0O_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[3] : n0Oill;
	and(wire_ni1l1i_dataout, wire_ni00il_dataout, ~(nl0ill));
	or(wire_ni1l1l_dataout, wire_ni00iO_dataout, nl0ill);
	assign		wire_ni1l1O_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[0] : n0Ol0i;
	assign		wire_ni1lii_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[4] : n0OilO;
	assign		wire_ni1lil_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[5] : n0OiOi;
	assign		wire_ni1liO_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[6] : n0OiOl;
	assign		wire_ni1lli_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[7] : n0OiOO;
	assign		wire_ni1lll_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[8] : n0Ol1i;
	assign		wire_ni1llO_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out2[9] : n0Ol1l;
	assign		wire_ni1lOi_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[0] : n0Ol1O;
	assign		wire_ni1lOl_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[1] : n0Ol0l;
	assign		wire_ni1lOO_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[2] : n0Ol0O;
	assign		wire_ni1O_dataout = (rwa_6g_en === 1'b1) ? wire_nlll0O_dataout : wire_n01iOO_dataout;
	assign		wire_ni1O0i_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[6] : n0Olli;
	assign		wire_ni1O0l_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[7] : n0Olll;
	assign		wire_ni1O0O_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[8] : n0OllO;
	assign		wire_ni1O1i_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[3] : n0Olii;
	assign		wire_ni1O1l_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[4] : n0Olil;
	assign		wire_ni1O1O_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[5] : n0OliO;
	assign		wire_ni1Oii_dataout = (nliOllO === 1'b1) ? wire_nlOili_data_out2[9] : n0OlOi;
	assign		wire_ni1Oil_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[0] : wire_ni00li_dataout;
	assign		wire_ni1OiO_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[1] : wire_ni00ll_dataout;
	assign		wire_ni1Oli_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[2] : wire_ni00lO_dataout;
	assign		wire_ni1Oll_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[3] : wire_ni00Oi_dataout;
	assign		wire_ni1OlO_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[4] : wire_ni00Ol_dataout;
	assign		wire_ni1OOi_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[5] : wire_ni00OO_dataout;
	assign		wire_ni1OOl_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[6] : wire_ni0i1i_dataout;
	assign		wire_ni1OOO_dataout = (nliOllO === 1'b1) ? wire_nlOiiO_data_out1[7] : wire_ni0i1l_dataout;
	assign		wire_niii_dataout = (rwa_6g_en === 1'b1) ? wire_nlllli_dataout : wire_n01l0i_dataout;
	and(wire_niiilO_dataout, wire_nil01l_dataout, ~(nliOOOl));
	and(wire_niiiOi_dataout, wire_nil01O_dataout, ~(nliOOOl));
	and(wire_niiiOl_dataout, wire_nil00i_dataout, ~(nliOOOl));
	and(wire_niiiOO_dataout, wire_nil00l_dataout, ~(nliOOOl));
	assign		wire_niil_dataout = (rwa_6g_en === 1'b1) ? wire_nlllll_dataout : wire_n01l0l_dataout;
	and(wire_niil0i_dataout, wire_nil0iO_dataout, ~(nliOOOl));
	and(wire_niil0l_dataout, wire_nil0li_dataout, ~(nliOOOl));
	and(wire_niil0O_dataout, wire_nil0ll_dataout, ~(nliOOOl));
	and(wire_niil1i_dataout, wire_nil00O_dataout, ~(nliOOOl));
	and(wire_niil1l_dataout, wire_nil0ii_dataout, ~(nliOOOl));
	and(wire_niil1O_dataout, wire_nil0il_dataout, ~(nliOOOl));
	and(wire_niilii_dataout, wire_nil0lO_dataout, ~(nliOOOl));
	or(wire_niilil_dataout, wire_nil0Oi_dataout, nliOOOl);
	and(wire_niiliO_dataout, wire_nil0Ol_dataout, ~(nliOOOl));
	and(wire_niilli_dataout, wire_nil0OO_dataout, ~(nliOOOl));
	and(wire_niilll_dataout, wire_nili1i_dataout, ~(nliOOOl));
	and(wire_niillO_dataout, wire_nili1l_dataout, ~(nliOOOl));
	and(wire_niilOi_dataout, wire_nili1O_dataout, ~(nliOOOl));
	and(wire_niilOl_dataout, wire_nili0i_dataout, ~(nliOOOl));
	and(wire_niilOO_dataout, wire_nili0l_dataout, ~(nliOOOl));
	assign		wire_niiO_dataout = (rwa_6g_en === 1'b1) ? wire_nllllO_dataout : wire_n01l0O_dataout;
	and(wire_niiO0i_dataout, wire_niliiO_dataout, ~(nliOOOl));
	and(wire_niiO0l_dataout, wire_nilili_dataout, ~(nliOOOl));
	and(wire_niiO0O_dataout, wire_nilill_dataout, ~(nliOOOl));
	and(wire_niiO1i_dataout, wire_nili0O_dataout, ~(nliOOOl));
	and(wire_niiO1l_dataout, wire_niliii_dataout, ~(nliOOOl));
	and(wire_niiO1O_dataout, wire_niliil_dataout, ~(nliOOOl));
	and(wire_niiOii_dataout, wire_nililO_dataout, ~(nliOOOl));
	and(wire_niiOil_dataout, wire_niliOi_dataout, ~(nliOOOl));
	and(wire_niiOiO_dataout, wire_niliOl_dataout, ~(nliOOOl));
	and(wire_niiOli_dataout, wire_niliOO_dataout, ~(nliOOOl));
	and(wire_niiOll_dataout, wire_nill1i_dataout, ~(nliOOOl));
	or(wire_niiOlO_dataout, wire_nill1l_dataout, nliOOOl);
	and(wire_niiOOi_dataout, wire_nill1O_dataout, ~(nliOOOl));
	and(wire_niiOOl_dataout, wire_nill0i_dataout, ~(nliOOOl));
	and(wire_niiOOO_dataout, wire_nill0l_dataout, ~(nliOOOl));
	assign		wire_nil00i_dataout = (nliOO1l === 1'b1) ? nliOlOl : ni0Oii;
	assign		wire_nil00l_dataout = (nliOO1l === 1'b1) ? nliOlOO : ni0Oil;
	assign		wire_nil00O_dataout = (nliOO1l === 1'b1) ? (((wire_nilOOl_o[18] | wire_nilOOl_o[17]) | wire_nilOOl_o[16]) | wire_nilOOl_o[15]) : ni0OiO;
	and(wire_nil01i_dataout, wire_nilO0O_dataout, ~(nliOOOl));
	assign		wire_nil01l_dataout = (nliOO1l === 1'b1) ? nliOlOi : ni101l;
	assign		wire_nil01O_dataout = (nliOO1l === 1'b1) ? (((wire_nilOli_o[4] | wire_nilOli_o[3]) | wire_nilOli_o[2]) | wire_nilOli_o[1]) : ni0O0O;
	assign		wire_nil0ii_dataout = (nliOO1l === 1'b1) ? wire_nilOOO_dataout : ni0Oli;
	assign		wire_nil0il_dataout = (nliOO1l === 1'b1) ? wire_niO11i_dataout : ni0Oll;
	assign		wire_nil0iO_dataout = (nliOO1l === 1'b1) ? wire_niO11l_dataout : ni0OlO;
	assign		wire_nil0li_dataout = (nliOO1l === 1'b1) ? wire_niO11O_dataout : ni0OOi;
	assign		wire_nil0ll_dataout = (nliOO1l === 1'b1) ? wire_niO10i_dataout : ni0OOl;
	assign		wire_nil0lO_dataout = (nliOO1l === 1'b1) ? nii00i : ni0OOO;
	assign		wire_nil0Oi_dataout = (nliOO1l === 1'b1) ? ni0OOO : nii11i;
	assign		wire_nil0Ol_dataout = (nliOO1l === 1'b1) ? nii11i : nii11l;
	assign		wire_nil0OO_dataout = (nliOO1l === 1'b1) ? nii11l : nii11O;
	and(wire_nil10i_dataout, wire_nilliO_dataout, ~(nliOOOl));
	and(wire_nil10l_dataout, wire_nillli_dataout, ~(nliOOOl));
	and(wire_nil10O_dataout, wire_nillll_dataout, ~(nliOOOl));
	and(wire_nil11i_dataout, wire_nill0O_dataout, ~(nliOOOl));
	and(wire_nil11l_dataout, wire_nillii_dataout, ~(nliOOOl));
	and(wire_nil11O_dataout, wire_nillil_dataout, ~(nliOOOl));
	and(wire_nil1ii_dataout, wire_nilllO_dataout, ~(nliOOOl));
	and(wire_nil1il_dataout, wire_nillOi_dataout, ~(nliOOOl));
	and(wire_nil1iO_dataout, wire_nillOl_dataout, ~(nliOOOl));
	and(wire_nil1li_dataout, wire_nillOO_dataout, ~(nliOOOl));
	and(wire_nil1ll_dataout, wire_nilO1i_dataout, ~(nliOOOl));
	and(wire_nil1lO_dataout, wire_nilO1l_dataout, ~(nliOOOl));
	and(wire_nil1Oi_dataout, wire_nilO1O_dataout, ~(nliOOOl));
	and(wire_nil1Ol_dataout, wire_nilO0i_dataout, ~(nliOOOl));
	and(wire_nil1OO_dataout, wire_nilO0l_dataout, ~(nliOOOl));
	assign		wire_nili_dataout = (rwa_6g_en === 1'b1) ? wire_nlllOi_dataout : wire_n01lii_dataout;
	assign		wire_nili0i_dataout = (nliOO1l === 1'b1) ? nii10O : nii1ii;
	assign		wire_nili0l_dataout = (nliOO1l === 1'b1) ? nii1ii : nii1il;
	assign		wire_nili0O_dataout = (nliOO1l === 1'b1) ? nii1il : nii1iO;
	assign		wire_nili1i_dataout = (nliOO1l === 1'b1) ? nii11O : nii10i;
	assign		wire_nili1l_dataout = (nliOO1l === 1'b1) ? nii10i : nii10l;
	assign		wire_nili1O_dataout = (nliOO1l === 1'b1) ? nii10l : nii10O;
	assign		wire_niliii_dataout = (nliOO1l === 1'b1) ? nii1iO : nii1li;
	assign		wire_niliil_dataout = (nliOO1l === 1'b1) ? nii1li : nii1ll;
	assign		wire_niliiO_dataout = (nliOO1l === 1'b1) ? nii1ll : nii1lO;
	assign		wire_nilili_dataout = (nliOO1l === 1'b1) ? nii1lO : nii1Oi;
	assign		wire_nilill_dataout = (nliOO1l === 1'b1) ? nii1Oi : nii1Ol;
	assign		wire_nililO_dataout = (nliOO1l === 1'b1) ? nii1Ol : nii1OO;
	assign		wire_niliOi_dataout = (nliOO1l === 1'b1) ? nii1OO : nii01i;
	assign		wire_niliOl_dataout = (nliOO1l === 1'b1) ? nii01i : nii01l;
	assign		wire_niliOO_dataout = (nliOO1l === 1'b1) ? nii01l : nii01O;
	and(wire_nill_dataout, wire_nlllOl_dataout, rwa_6g_en);
	assign		wire_nill0i_dataout = (nliOO1l === 1'b1) ? nii0ii : nii0il;
	assign		wire_nill0l_dataout = (nliOO1l === 1'b1) ? nii0il : nii0iO;
	assign		wire_nill0O_dataout = (nliOO1l === 1'b1) ? nii0iO : nii0li;
	assign		wire_nill1i_dataout = (nliOO1l === 1'b1) ? nii01O : nii00i;
	assign		wire_nill1l_dataout = (nliOO1l === 1'b1) ? niiili : nii00O;
	assign		wire_nill1O_dataout = (nliOO1l === 1'b1) ? nii00O : nii0ii;
	assign		wire_nillii_dataout = (nliOO1l === 1'b1) ? nii0li : nii0ll;
	assign		wire_nillil_dataout = (nliOO1l === 1'b1) ? nii0ll : nii0lO;
	assign		wire_nilliO_dataout = (nliOO1l === 1'b1) ? nii0lO : nii0Oi;
	assign		wire_nilll_dataout = (rwa_6g_en === 1'b1) ? wire_nllilO_dataout : wire_n01i0O_dataout;
	assign		wire_nillli_dataout = (nliOO1l === 1'b1) ? nii0Oi : nii0Ol;
	assign		wire_nillll_dataout = (nliOO1l === 1'b1) ? nii0Ol : nii0OO;
	assign		wire_nilllO_dataout = (nliOO1l === 1'b1) ? nii0OO : niii1i;
	assign		wire_nillO_dataout = (rwa_6g_en === 1'b1) ? wire_nlliOi_dataout : wire_n01iii_dataout;
	assign		wire_nillOi_dataout = (nliOO1l === 1'b1) ? niii1i : niii1l;
	assign		wire_nillOl_dataout = (nliOO1l === 1'b1) ? niii1l : niii1O;
	assign		wire_nillOO_dataout = (nliOO1l === 1'b1) ? niii1O : niii0i;
	and(wire_nilO_dataout, wire_nlllOO_dataout, rwa_6g_en);
	assign		wire_nilO0i_dataout = (nliOO1l === 1'b1) ? niiiii : niiiil;
	assign		wire_nilO0l_dataout = (nliOO1l === 1'b1) ? niiiil : niiiiO;
	assign		wire_nilO0O_dataout = (nliOO1l === 1'b1) ? niiiiO : niiili;
	assign		wire_nilO1i_dataout = (nliOO1l === 1'b1) ? niii0i : niii0l;
	assign		wire_nilO1l_dataout = (nliOO1l === 1'b1) ? niii0l : niii0O;
	assign		wire_nilO1O_dataout = (nliOO1l === 1'b1) ? niii0O : niiiii;
	assign		wire_nilOi_dataout = (rwa_6g_en === 1'b1) ? wire_nlliOl_dataout : wire_n01iil_dataout;
	assign		wire_nilOl_dataout = (rwa_6g_en === 1'b1) ? wire_nlliOO_dataout : wire_n01iiO_dataout;
	assign		wire_nilOO_dataout = (rwa_6g_en === 1'b1) ? wire_nlll1i_dataout : wire_n01ili_dataout;
	and(wire_nilOOO_dataout, wire_niO10l_o[0], ~(nliOO1i));
	and(wire_niO_dataout, cmpfifourst, rcmpfifourst);
	assign		wire_niO0i_dataout = (rwa_6g_en === 1'b1) ? wire_nlll0l_dataout : wire_n01iOl_dataout;
	assign		wire_niO0l_dataout = (rwa_6g_en === 1'b1) ? wire_nlll0O_dataout : wire_n01iOO_dataout;
	assign		wire_niO0O_dataout = (rwa_6g_en === 1'b1) ? wire_nlllii_dataout : wire_n01l1i_dataout;
	and(wire_niO10i_dataout, wire_niO10l_o[4], ~(nliOO1i));
	and(wire_niO11i_dataout, wire_niO10l_o[1], ~(nliOO1i));
	and(wire_niO11l_dataout, wire_niO10l_o[2], ~(nliOO1i));
	and(wire_niO11O_dataout, wire_niO10l_o[3], ~(nliOO1i));
	assign		wire_niO1i_dataout = (rwa_6g_en === 1'b1) ? wire_nlll1l_dataout : wire_n01ill_dataout;
	assign		wire_niO1l_dataout = (rwa_6g_en === 1'b1) ? wire_nlll1O_dataout : wire_n01ilO_dataout;
	assign		wire_niO1O_dataout = (rwa_6g_en === 1'b1) ? wire_nlll0i_dataout : wire_n01iOi_dataout;
	and(wire_niOi_dataout, wire_nllO1i_dataout, rwa_6g_en);
	and(wire_niOii_dataout, wire_nlllOl_dataout, rwa_6g_en);
	and(wire_niOil_dataout, wire_nlllOO_dataout, rwa_6g_en);
	and(wire_niOiO_dataout, wire_nllO1i_dataout, rwa_6g_en);
	and(wire_niOl_dataout, wire_nllO1l_dataout, rwa_6g_en);
	and(wire_niOl0i_dataout, wire_niOOOl_dataout, ~(nll100i));
	and(wire_niOl0l_dataout, wire_niOOOO_dataout, ~(nll100i));
	or(wire_niOl0O_dataout, wire_nl111i_dataout, nll100i);
	and(wire_niOl1i_dataout, wire_niOOll_dataout, ~(nll100i));
	and(wire_niOl1l_dataout, wire_niOOlO_dataout, ~(nll100i));
	and(wire_niOl1O_dataout, wire_niOOOi_dataout, ~(nll100i));
	and(wire_niOli_dataout, wire_nllO1l_dataout, rwa_6g_en);
	and(wire_niOlii_dataout, wire_nl111l_dataout, ~(nll100i));
	and(wire_niOlil_dataout, wire_nl111O_dataout, ~(nll100i));
	and(wire_niOliO_dataout, wire_nl110i_dataout, ~(nll100i));
	and(wire_niOll_dataout, wire_nllO1O_dataout, rwa_6g_en);
	and(wire_niOlli_dataout, wire_nl110l_dataout, ~(nll100i));
	and(wire_niOlll_dataout, wire_nl110O_dataout, ~(nll100i));
	and(wire_niOllO_dataout, wire_nl11ii_dataout, ~(nll100i));
	and(wire_niOlO_dataout, wire_nllO0i_dataout, rwa_6g_en);
	and(wire_niOlOi_dataout, wire_nl11il_dataout, ~(nll100i));
	and(wire_niOlOl_dataout, wire_nl11iO_dataout, ~(nll100i));
	and(wire_niOlOO_dataout, wire_nl11li_dataout, ~(nll100i));
	and(wire_niOO_dataout, wire_nllO1O_dataout, rwa_6g_en);
	and(wire_niOO0i_dataout, wire_nl11Ol_dataout, ~(nll100i));
	and(wire_niOO0l_dataout, wire_nl11OO_dataout, ~(nll100i));
	and(wire_niOO0O_dataout, wire_nl101i_dataout, ~(nll100i));
	and(wire_niOO1i_dataout, wire_nl11ll_dataout, ~(nll100i));
	and(wire_niOO1l_dataout, wire_nl11lO_dataout, ~(nll100i));
	and(wire_niOO1O_dataout, wire_nl11Oi_dataout, ~(nll100i));
	and(wire_niOOi_dataout, wire_nllO0l_dataout, rwa_6g_en);
	and(wire_niOOii_dataout, wire_nl101l_dataout, ~(nll100i));
	and(wire_niOOil_dataout, wire_nl101O_dataout, ~(nll100i));
	and(wire_niOOiO_dataout, wire_nl100i_dataout, ~(nll100i));
	and(wire_niOOl_dataout, wire_nllO0O_dataout, rwa_6g_en);
	and(wire_niOOli_dataout, wire_nl100l_dataout, ~(nll100i));
	assign		wire_niOOll_dataout = (nll101l === 1'b1) ? wire_nl100O_dataout : niiill;
	assign		wire_niOOlO_dataout = (nll101l === 1'b1) ? wire_nl10ii_dataout : niO1ll;
	and(wire_niOOO_dataout, wire_nllOii_dataout, rwa_6g_en);
	assign		wire_niOOOi_dataout = (nll101l === 1'b1) ? wire_nl10il_dataout : niO1lO;
	assign		wire_niOOOl_dataout = (nll101l === 1'b1) ? wire_nl10iO_dataout : niO1Oi;
	assign		wire_niOOOO_dataout = (nll101l === 1'b1) ? wire_nl10li_dataout : niO1Ol;
	and(wire_nl00i_dataout, nlO0iO, rwa_6g_en);
	and(wire_nl00iO_dataout, (((~ rgenericfifo) & nl000O) | nliOOll), ~(nliOOOl));
	and(wire_nl00l_dataout, nlO0li, rwa_6g_en);
	and(wire_nl00li_dataout, nl000l, ~(nliOOOl));
	and(wire_nl00ll_dataout, nlOill, ~(nliOOOl));
	and(wire_nl00lO_dataout, nl00ii, ~(nliOOOl));
	and(wire_nl00O_dataout, nlO0ll, rwa_6g_en);
	and(wire_nl00Oi_dataout, ((~ rgenericfifo) & nl00il), ~(nliOOOl));
	and(wire_nl010i_dataout, nl1OOi, ~(nliOOOl));
	and(wire_nl010l_dataout, nl1OOl, ~(nliOOOl));
	and(wire_nl010O_dataout, nl1OOO, ~(nliOOOl));
	assign		wire_nl01i_dataout = (rwa_6g_en === 1'b1) ? ((nll011i | nliiOi) | (~ (nll1O0O22 ^ nll1O0O21))) : (((nll1OOO | n1li1l) | (~ (nll1OOi16 ^ nll1OOi15))) | ((n1O0Ol & (((((~ wire_n0100O_dataout) & ((~ wire_n0100l_dataout) & (rrx_pipe_enable & nll1OlO))) & (nll1Oli18 ^ nll1Oli17)) & nlOO1l) & (nll1Oil20 ^ nll1Oil19))) & wire_n1iOOO_o));
	and(wire_nl01ii_dataout, nl011i, ~(nliOOOl));
	and(wire_nl01il_dataout, nl011l, ~(nliOOOl));
	and(wire_nl01iO_dataout, nl1iil, ~(nliOOOl));
	assign		wire_nl01l_dataout = (rwa_6g_en === 1'b1) ? nliOll : n1O1lO;
	and(wire_nl01li_dataout, nl1l1i, ~(nliOOOl));
	and(wire_nl01ll_dataout, nl1l1l, ~(nliOOOl));
	and(wire_nl01lO_dataout, nl1l1O, ~(nliOOOl));
	and(wire_nl01O_dataout, nlO0il, rwa_6g_en);
	and(wire_nl01Oi_dataout, nl1l0i, ~(nliOOOl));
	and(wire_nl0i_dataout, wire_nllOii_dataout, rwa_6g_en);
	or(wire_nl0i0i_dataout, nl00il, ((~ nl00il) & nliOOlO));
	assign		wire_nl0i0O_dataout = (rdwidth_rx === 1'b1) ? (nliOOOi | nl0i1l) : nliOOOi;
	and(wire_nl0i1O_dataout, wire_nl0i0i_dataout, wire_nllili_dataout);
	and(wire_nl0ii_dataout, nlO0lO, rwa_6g_en);
	and(wire_nl0il_dataout, nlO0Oi, rwa_6g_en);
	and(wire_nl0iO_dataout, nlO0Ol, rwa_6g_en);
	and(wire_nl0iOi_dataout, n00lii, ~(nliOOOl));
	and(wire_nl0iOl_dataout, ((nl000O & n00lii) & (~ nl0ili)), ~(nliOOOl));
	and(wire_nl0l_dataout, wire_nllOil_dataout, rwa_6g_en);
	assign		wire_nl0l1l_dataout = (rdwidth_rx === 1'b1) ? (nliOOOO | nl0ilO) : nliOOOO;
	and(wire_nl0li_dataout, nlO0OO, rwa_6g_en);
	and(wire_nl0ll_dataout, nlOi1i, rwa_6g_en);
	and(wire_nl0lO_dataout, nlOi1l, rwa_6g_en);
	and(wire_nl0O_dataout, wire_nllOiO_dataout, rwa_6g_en);
	or(wire_nl0O0i_dataout, wire_nl0Oii_dataout, nll100i);
	and(wire_nl0O0l_dataout, wire_nli11l_dataout, ~(nll100i));
	and(wire_nl0O0O_dataout, wire_nl0Oli_dataout, ~(nll100i));
	and(wire_nl0O1i_dataout, nl0lOi, ~(nll100i));
	or(wire_nl0O1l_dataout, nl0lli, nll100i);
	or(wire_nl0O1O_dataout, wire_nl0OOl_dataout, nll100i);
	and(wire_nl0Oi_dataout, nlOi1O, rwa_6g_en);
	assign		wire_nl0Oii_dataout = (rdwidth_rx === 1'b1) ? (nll110i | nl0liO) : nll110i;
	and(wire_nl0Ol_dataout, nlOi0i, rwa_6g_en);
	assign		wire_nl0Oli_dataout = (rdwidth_rx === 1'b1) ? (nll110l | nl0l0O) : nll110l;
	and(wire_nl0OO_dataout, nlOi0l, rwa_6g_en);
	assign		wire_nl0OOl_dataout = (((((~ ralempty[0]) & (~ ralempty[1])) & (~ ralempty[2])) & (~ ralempty[3])) === 1'b1) ? wire_nll11i_o : wire_nl0OOO_o;
	assign		wire_nl100i_dataout = (nll101l === 1'b1) ? niOilO : niOiOi;
	assign		wire_nl100l_dataout = (nll101l === 1'b1) ? niOiOi : niOiOl;
	and(wire_nl100O_dataout, wire_nl10ll_o[0], ~(nliOO1O));
	assign		wire_nl101i_dataout = (nll101l === 1'b1) ? niOiiO : niOili;
	assign		wire_nl101l_dataout = (nll101l === 1'b1) ? niOili : niOill;
	assign		wire_nl101O_dataout = (nll101l === 1'b1) ? niOill : niOilO;
	assign		wire_nl10i_dataout = (rwa_6g_en === 1'b1) ? nlO1ll : wire_n01Oll_dataout;
	and(wire_nl10ii_dataout, wire_nl10ll_o[1], ~(nliOO1O));
	and(wire_nl10il_dataout, wire_nl10ll_o[2], ~(nliOO1O));
	and(wire_nl10iO_dataout, wire_nl10ll_o[3], ~(nliOO1O));
	assign		wire_nl10l_dataout = (rwa_6g_en === 1'b1) ? nlO1lO : wire_n01OlO_dataout;
	and(wire_nl10li_dataout, wire_nl10ll_o[4], ~(nliOO1O));
	and(wire_nl10lO_dataout, niO00l, ~(nll100i));
	assign		wire_nl10O_dataout = (rwa_6g_en === 1'b1) ? nlO1Oi : wire_n01OOi_dataout;
	and(wire_nl10Oi_dataout, niO00O, ~(nll100i));
	and(wire_nl10Ol_dataout, niO0ii, ~(nll100i));
	and(wire_nl10OO_dataout, niO0il, ~(nll100i));
	assign		wire_nl110i_dataout = (nll101l === 1'b1) ? niO0lO : niO0Oi;
	assign		wire_nl110l_dataout = (nll101l === 1'b1) ? niO0Oi : niO0Ol;
	assign		wire_nl110O_dataout = (nll101l === 1'b1) ? niO0Ol : niO0OO;
	assign		wire_nl111i_dataout = (nll101l === 1'b1) ? niOiOl : niO0li;
	assign		wire_nl111l_dataout = (nll101l === 1'b1) ? niO0li : niO0ll;
	assign		wire_nl111O_dataout = (nll101l === 1'b1) ? niO0ll : niO0lO;
	and(wire_nl11i_dataout, wire_nllOil_dataout, rwa_6g_en);
	assign		wire_nl11ii_dataout = (nll101l === 1'b1) ? niO0OO : niOi1i;
	assign		wire_nl11il_dataout = (nll101l === 1'b1) ? niOi1i : niOi1l;
	assign		wire_nl11iO_dataout = (nll101l === 1'b1) ? niOi1l : niOi1O;
	assign		wire_nl11l_dataout = (rwa_6g_en === 1'b1) ? nll00l : wire_n01OiO_dataout;
	assign		wire_nl11li_dataout = (nll101l === 1'b1) ? niOi1O : niOi0i;
	assign		wire_nl11ll_dataout = (nll101l === 1'b1) ? niOi0i : niOi0l;
	assign		wire_nl11lO_dataout = (nll101l === 1'b1) ? niOi0l : niOi0O;
	assign		wire_nl11O_dataout = (rwa_6g_en === 1'b1) ? nlO1li : wire_n01Oli_dataout;
	assign		wire_nl11Oi_dataout = (nll101l === 1'b1) ? niOi0O : niOiii;
	assign		wire_nl11Ol_dataout = (nll101l === 1'b1) ? niOiii : niOiil;
	assign		wire_nl11OO_dataout = (nll101l === 1'b1) ? niOiil : niOiiO;
	and(wire_nl1i_dataout, wire_nllO0i_dataout, rwa_6g_en);
	and(wire_nl1i0i_dataout, ni0Oii, ~(nll100i));
	and(wire_nl1i0l_dataout, ni0Oil, ~(nll100i));
	and(wire_nl1i0O_dataout, ni0OiO, ~(nll100i));
	and(wire_nl1i1i_dataout, niO0iO, ~(nll100i));
	and(wire_nl1i1l_dataout, ni101l, ~(nll100i));
	and(wire_nl1i1O_dataout, ni0O0O, ~(nll100i));
	assign		wire_nl1ii_dataout = (rwa_6g_en === 1'b1) ? nlO1Ol : wire_n01OOl_dataout;
	assign		wire_nl1il_dataout = (rwa_6g_en === 1'b1) ? nlO1OO : wire_n01OOO_dataout;
	assign		wire_nl1iO_dataout = (rwa_6g_en === 1'b1) ? nlO01i : wire_n0011i_dataout;
	and(wire_nl1l_dataout, wire_nllO0l_dataout, rwa_6g_en);
	and(wire_nl1l0O_dataout, wire_nl1lll_dataout, ~(nll100i));
	assign		wire_nl1li_dataout = (rwa_6g_en === 1'b1) ? nlO01l : wire_n0011l_dataout;
	and(wire_nl1lii_dataout, wire_nl1llO_dataout, ~(nll100i));
	and(wire_nl1lil_dataout, wire_nl1lOi_dataout, ~(nll100i));
	and(wire_nl1liO_dataout, wire_nl1lOl_dataout, ~(nll100i));
	assign		wire_nl1ll_dataout = (rwa_6g_en === 1'b1) ? nlO01O : wire_n0011O_dataout;
	and(wire_nl1lli_dataout, wire_nl1lOO_dataout, ~(nll100i));
	assign		wire_nl1lll_dataout = (nll110O === 1'b1) ? nl1iil : nliOOiO;
	assign		wire_nl1llO_dataout = (nll110O === 1'b1) ? nl1l1i : (wire_nl1O0i_o[2] | wire_nl1O0i_o[1]);
	assign		wire_nl1lO_dataout = (rwa_6g_en === 1'b1) ? nlO00i : wire_n010ii_dataout;
	assign		wire_nl1lOi_dataout = (nll110O === 1'b1) ? nl1l1l : (wire_nl1Oil_o[2] | wire_nl1Oil_o[1]);
	assign		wire_nl1lOl_dataout = (nll110O === 1'b1) ? nl1l1O : nliOOli;
	assign		wire_nl1lOO_dataout = (nll110O === 1'b1) ? nl1l0i : wire_nl1Oil_o[4];
	and(wire_nl1O_dataout, wire_nllO0O_dataout, rwa_6g_en);
	assign		wire_nl1Oi_dataout = (rwa_6g_en === 1'b1) ? nlO00l : wire_n0010i_dataout;
	assign		wire_nl1Ol_dataout = (rwa_6g_en === 1'b1) ? nlO00O : wire_n010il_dataout;
	assign		wire_nl1OO_dataout = (rwa_6g_en === 1'b1) ? nlO0ii : wire_n0010l_dataout;
	assign		wire_nli_dataout = (rwa_6g_en === 1'b1) ? wire_nl0i0O_dataout : wire_n10lOO_dataout;
	assign		wire_nli00i_dataout = (nll110O === 1'b1) ? nli1il : wire_nli0li_dataout;
	assign		wire_nli00l_dataout = (nll110O === 1'b1) ? nli1iO : wire_nli0ll_dataout;
	assign		wire_nli01i_dataout = (nll110O === 1'b1) ? nl0lOO : wire_nli0ii_dataout;
	assign		wire_nli01l_dataout = (nll110O === 1'b1) ? nli10O : wire_nli0il_dataout;
	assign		wire_nli01O_dataout = (nll110O === 1'b1) ? nli1ii : wire_nli0iO_dataout;
	assign		wire_nli0i_dataout = (rwa_6g_en === 1'b1) ? wire_nllili_dataout : wire_n01i0i_dataout;
	assign		wire_nli0ii_dataout = (wire_nli0OO_o === 1'b1) ? wire_nli0Ol_o[1] : wire_nli0lO_o[1];
	assign		wire_nli0il_dataout = (wire_nli0OO_o === 1'b1) ? wire_nli0Ol_o[2] : wire_nli0lO_o[2];
	assign		wire_nli0iO_dataout = (wire_nli0OO_o === 1'b1) ? wire_nli0Ol_o[3] : wire_nli0lO_o[3];
	assign		wire_nli0l_dataout = (rwa_6g_en === 1'b1) ? (rmatchen & (~ rgenericfifo)) : ((~ rgenericfifo) & (((((~ dskwclksel[1]) & rmatchen) & (nll010l12 ^ nll010l11)) | (is_lane0 & nll010i)) | (~ (nll011l14 ^ nll011l13))));
	assign		wire_nli0li_dataout = (wire_nli0OO_o === 1'b1) ? wire_nli0Ol_o[4] : wire_nli0lO_o[4];
	assign		wire_nli0ll_dataout = (wire_nli0OO_o === 1'b1) ? wire_nli0Ol_o[5] : wire_nli0lO_o[5];
	assign		wire_nli0O_dataout = (rwa_6g_en === 1'b1) ? niO0li : nlOllil;
	assign		wire_nli11l_dataout = (((((~ ralfull[0]) & (~ ralfull[1])) & (~ ralfull[2])) & (~ ralfull[3])) === 1'b1) ? wire_nliOOO_o : wire_nli11O_o;
	and(wire_nli1i_dataout, nlOi0O, rwa_6g_en);
	and(wire_nli1l_dataout, (nll011i | nliiOi), rwa_6g_en);
	and(wire_nli1ll_dataout, wire_nli01i_dataout, ~(nll100i));
	and(wire_nli1lO_dataout, wire_nli01l_dataout, ~(nll100i));
	and(wire_nli1O_dataout, nliOll, rwa_6g_en);
	and(wire_nli1Oi_dataout, wire_nli01O_dataout, ~(nll100i));
	and(wire_nli1Ol_dataout, wire_nli00i_dataout, ~(nll100i));
	and(wire_nli1OO_dataout, wire_nli00l_dataout, ~(nll100i));
	and(wire_nlii_dataout, wire_nllOli_dataout, rwa_6g_en);
	assign		wire_nliii_dataout = (rwa_6g_en === 1'b1) ? niO0ll : nlOlliO;
	assign		wire_nliil_dataout = (rwa_6g_en === 1'b1) ? niO0lO : nlOllli;
	assign		wire_nliiO_dataout = (rwa_6g_en === 1'b1) ? niO0Oi : nlOllll;
	and(wire_nliiOl_dataout, wire_nlil0i_dataout, ~(nll100i));
	and(wire_nliiOO_dataout, wire_nlil0l_dataout, ~(nll100i));
	and(wire_nlil_dataout, wire_nllOll_dataout, rwa_6g_en);
	assign		wire_nlil0i_dataout = (nll11OO === 1'b1) ? wire_nlilOO_o[0] : wire_nliliO_dataout;
	assign		wire_nlil0l_dataout = (nll11OO === 1'b1) ? wire_nlilOO_o[1] : wire_nlilli_dataout;
	assign		wire_nlil0O_dataout = (nll11OO === 1'b1) ? wire_nlilOO_o[2] : wire_nlilll_dataout;
	and(wire_nlil1i_dataout, wire_nlil0O_dataout, ~(nll100i));
	and(wire_nlil1l_dataout, wire_nlilii_dataout, ~(nll100i));
	and(wire_nlil1O_dataout, wire_nlilil_dataout, ~(nll100i));
	assign		wire_nlili_dataout = (rwa_6g_en === 1'b1) ? niO0Ol : nlOlllO;
	assign		wire_nlilii_dataout = (nll11OO === 1'b1) ? wire_nlilOO_o[3] : wire_nlillO_dataout;
	assign		wire_nlilil_dataout = (nll11OO === 1'b1) ? wire_nlilOO_o[4] : wire_nlilOi_dataout;
	assign		wire_nliliO_dataout = ((~ nll11Ol) === 1'b1) ? wire_nlilOl_o[1] : nli1li;
	assign		wire_nlill_dataout = (rwa_6g_en === 1'b1) ? niO0OO : nlOllOi;
	assign		wire_nlilli_dataout = ((~ nll11Ol) === 1'b1) ? wire_nlilOl_o[2] : nliiiO;
	assign		wire_nlilll_dataout = ((~ nll11Ol) === 1'b1) ? wire_nlilOl_o[3] : nliili;
	assign		wire_nlillO_dataout = ((~ nll11Ol) === 1'b1) ? wire_nlilOl_o[4] : nliill;
	assign		wire_nlilO_dataout = (rwa_6g_en === 1'b1) ? niOi1i : nlOllOl;
	assign		wire_nlilOi_dataout = ((~ nll11Ol) === 1'b1) ? wire_nlilOl_o[5] : nliilO;
	and(wire_nliO_dataout, wire_nllOlO_dataout, rwa_6g_en);
	assign		wire_nliOi_dataout = (rwa_6g_en === 1'b1) ? niOi1l : nlOllOO;
	assign		wire_nliOl_dataout = (rwa_6g_en === 1'b1) ? niOi1O : nlOlO1i;
	assign		wire_nliOO_dataout = (rwa_6g_en === 1'b1) ? niOi0i : nlOlO1l;
	and(wire_nliOOi_dataout, nll100l, ~(nll100i));
	and(wire_nliOOl_dataout, nll100l, ~(nll100i));
	assign		wire_nll_dataout = (rwa_6g_en === 1'b1) ? nl0llO : n1i1ii;
	or(wire_nll00O_dataout, (nll1lil & ((nll1l0l & (wire_nllili_dataout & nll10O)) & (nll1ili42 ^ nll1ili41))), (rtruebac2bac & (nll1lil & (nll1l0l & (wire_nllili_dataout & nll1OO)))));
	and(wire_nll00Ol_dataout, nll00lO, ~((~ nliO1Ol)));
	and(wire_nll00OO_dataout, nll00Oi, ~((~ nliO1Ol)));
	and(wire_nll01i_dataout, (nll1l0l & ((nll1i0l | nll1i0i) | (~ (nll1i1l46 ^ nll1i1l45)))), wire_nllili_dataout);
	and(wire_nll01l_dataout, ((nll1iiO | nll1iil) | (~ (nll1i0O44 ^ nll1i0O43))), wire_nllili_dataout);
	assign		wire_nll0i_dataout = (rwa_6g_en === 1'b1) ? niOiil : nlOlO0O;
	and(wire_nll0i1i_dataout, wire_n1l0ll_o, (rgenericfifo | wire_n01i0i_dataout));
	assign		wire_nll0l_dataout = (rwa_6g_en === 1'b1) ? niOiiO : nlOlOii;
	assign		wire_nll0O_dataout = (rwa_6g_en === 1'b1) ? niOili : nlOlOil;
	or(wire_nll0Ol_dataout, wire_nll0OO_dataout, ((rtruebac2bac & ((nll1l0l & (nll1lil & (wire_nllili_dataout & nll00i))) & (nll1iOl38 ^ nll1iOl37))) & (nll1ilO40 ^ nll1ilO39)));
	and(wire_nll0OO_dataout, (nll1lil & nll1l0l), (wire_nllili_dataout & nll1Ol));
	and(wire_nll11O_dataout, (nll10ii | nll100O), wire_nlliiO_dataout);
	assign		wire_nll1i_dataout = (rwa_6g_en === 1'b1) ? niOi0l : nlOlO1O;
	and(wire_nll1ii_dataout, wire_nll1iO_dataout, wire_nlliiO_dataout);
	and(wire_nll1il_dataout, nll10iO, wire_nlliiO_dataout);
	assign		wire_nll1iO_dataout = (nliOlO === 1'b1) ? (nll10ll | nll10li) : wire_nll1li_dataout;
	assign		wire_nll1l_dataout = (rwa_6g_en === 1'b1) ? niOi0O : nlOlO0i;
	or(wire_nll1li_dataout, (rtruebac2bac & (nll10l & (~ nll1i1i))), ((nll10OO | nll10Ol) & (nll10Oi | nll10lO)));
	assign		wire_nll1O_dataout = (rwa_6g_en === 1'b1) ? niOiii : nlOlO0l;
	and(wire_nlli_dataout, wire_nllOOi_dataout, rwa_6g_en);
	assign		wire_nllii_dataout = (rwa_6g_en === 1'b1) ? niOill : nlOlOiO;
	and(wire_nlliiO_dataout, nl01OO, ~(nll1l1i));
	assign		wire_nllil_dataout = (rwa_6g_en === 1'b1) ? niOilO : nlOlOli;
	and(wire_nllili_dataout, sync_status, ~(nll1l1i));
	assign		wire_nllilO_dataout = (nll1l0i === 1'b1) ? nl001l : sync_status;
	assign		wire_nlliO_dataout = (rwa_6g_en === 1'b1) ? niOiOi : nlOlOll;
	assign		wire_nlliOi_dataout = (nll1l0i === 1'b1) ? n0OlOl : sudi[0];
	assign		wire_nlliOl_dataout = (nll1l0i === 1'b1) ? n0OlOO : sudi[1];
	assign		wire_nlliOO_dataout = (nll1l0i === 1'b1) ? n0OO1i : sudi[2];
	and(wire_nlll_dataout, wire_nllOOl_dataout, rwa_6g_en);
	assign		wire_nlll0i_dataout = (nll1l0i === 1'b1) ? n0OO0l : sudi[6];
	assign		wire_nlll0l_dataout = (nll1l0i === 1'b1) ? n0OO0O : sudi[7];
	assign		wire_nlll0O_dataout = (nll1l0i === 1'b1) ? n0OOii : sudi[8];
	assign		wire_nlll1i_dataout = (nll1l0i === 1'b1) ? n0OO1l : sudi[3];
	assign		wire_nlll1l_dataout = (nll1l0i === 1'b1) ? n0OO1O : sudi[4];
	assign		wire_nlll1O_dataout = (nll1l0i === 1'b1) ? n0OO0i : sudi[5];
	assign		wire_nllli_dataout = (rwa_6g_en === 1'b1) ? niOiOl : nlOlOlO;
	assign		wire_nlllii_dataout = (nll1l0i === 1'b1) ? n0OOil : sudi[9];
	assign		wire_nlllil_dataout = (nll1l0i === 1'b1) ? n0OOiO : sudi[10];
	assign		wire_nllliO_dataout = (nll1l0i === 1'b1) ? n0OOli : sudi[11];
	assign		wire_nllll_dataout = (rwa_6g_en === 1'b1) ? ni0OOO : nlO00OO;
	assign		wire_nlllli_dataout = (nll1l0i === 1'b1) ? n0OOll : sudi[12];
	assign		wire_nlllll_dataout = (nll1l0i === 1'b1) ? n0OOlO : sudi[13];
	and(wire_nllllO_dataout, n0OOOi, nll1l0i);
	assign		wire_nlllO_dataout = (rwa_6g_en === 1'b1) ? nii11i : nlO0i1i;
	and(wire_nlllOi_dataout, n0OOOl, nll1l0i);
	assign		wire_nlllOl_dataout = (nll1l0i === 1'b1) ? n0OOOO : sudi[14];
	assign		wire_nlllOO_dataout = (nll1l0i === 1'b1) ? ni111i : sudi[15];
	assign		wire_nllO_dataout = (rwa_6g_en === 1'b1) ? nl0lOO : n1i1li;
	assign		wire_nllO0i_dataout = (nll1l0i === 1'b1) ? ni110l : sudi[19];
	assign		wire_nllO0l_dataout = (nll1l0i === 1'b1) ? ni110O : sudi[20];
	assign		wire_nllO0O_dataout = (nll1l0i === 1'b1) ? ni11ii : sudi[21];
	assign		wire_nllO1i_dataout = (nll1l0i === 1'b1) ? ni111l : sudi[16];
	assign		wire_nllO1l_dataout = (nll1l0i === 1'b1) ? ni111O : sudi[17];
	assign		wire_nllO1O_dataout = (nll1l0i === 1'b1) ? ni110i : sudi[18];
	assign		wire_nllOi_dataout = (rwa_6g_en === 1'b1) ? nii11l : nlO0i1l;
	assign		wire_nllOii_dataout = (nll1l0i === 1'b1) ? ni11il : sudi[22];
	assign		wire_nllOil_dataout = (nll1l0i === 1'b1) ? ni11iO : sudi[23];
	assign		wire_nllOiO_dataout = (nll1l0i === 1'b1) ? ni11li : sudi[24];
	assign		wire_nllOl_dataout = (rwa_6g_en === 1'b1) ? nii11O : nlO0i1O;
	assign		wire_nllOl0i_dataout = (nlilO1O === 1'b1) ? (~ nllOiOl) : wire_nlO10iO_dataout;
	assign		wire_nllOl0l_dataout = (nlilO1O === 1'b1) ? (~ nllOiOl) : wire_nlO10li_dataout;
	assign		wire_nllOl0O_dataout = (nlilO1O === 1'b1) ? wire_nlO000l_dataout : wire_nlO10ll_dataout;
	assign		wire_nllOl1O_dataout = (nlilO1O === 1'b1) ? wire_nlO000i_dataout : wire_nlO10il_dataout;
	assign		wire_nllOli_dataout = (nll1l0i === 1'b1) ? ni11ll : sudi[25];
	assign		wire_nllOlii_dataout = (nlilO1O === 1'b1) ? (~ nllOiOl) : wire_nlO10lO_dataout;
	assign		wire_nllOlil_dataout = (nlilO1O === 1'b1) ? nllOiOl : wire_nlO10Oi_dataout;
	assign		wire_nllOliO_dataout = (nlilO1O === 1'b1) ? (~ nllOiOl) : wire_nlO10Ol_dataout;
	assign		wire_nllOll_dataout = (nll1l0i === 1'b1) ? ni11lO : sudi[26];
	assign		wire_nllOlli_dataout = (nlilO1O === 1'b1) ? nllOiOl : wire_nlO10OO_dataout;
	assign		wire_nllOlll_dataout = (nlilO1O === 1'b1) ? nllOiOl : wire_nlO1i1i_dataout;
	assign		wire_nllOllO_dataout = (nlilO1O === 1'b1) ? nllOiOl : wire_nlO1i1l_dataout;
	assign		wire_nllOlO_dataout = (nll1l0i === 1'b1) ? ni11Ol : sudi[27];
	and(wire_nllOlOi_dataout, wire_nlO1i1O_dataout, ~(nlilO1O));
	and(wire_nllOlOl_dataout, wire_nlO1i0l_dataout, ~(nlilO1O));
	and(wire_nllOlOO_dataout, wire_nlO1iii_dataout, ~(nlilO1O));
	assign		wire_nllOO_dataout = (rwa_6g_en === 1'b1) ? nii10i : nlO0i0i;
	assign		wire_nllOO0i_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[2] : nllO00l;
	assign		wire_nllOO0l_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[3] : nllO00O;
	assign		wire_nllOO0O_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[4] : nllO0ii;
	or(wire_nllOO1i_dataout, wire_nlO1iil_dataout, nlilO1O);
	assign		wire_nllOO1l_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[0] : nllO01O;
	assign		wire_nllOO1O_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[1] : nllO00i;
	and(wire_nllOOi_dataout, ni11OO, nll1l0i);
	assign		wire_nllOOii_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[5] : nllO0il;
	assign		wire_nllOOil_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[6] : nllO0iO;
	assign		wire_nllOOiO_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[7] : nllO0li;
	and(wire_nllOOl_dataout, ni101i, nll1l0i);
	assign		wire_nllOOli_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[8] : nllO0ll;
	assign		wire_nllOOll_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[9] : nllO0lO;
	assign		wire_nllOOlO_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[11] : nllO0Oi;
	assign		wire_nllOOOi_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out2[13] : nllO0Ol;
	assign		wire_nllOOOl_dataout = (nlillii === 1'b1) ? nllO10l : nllO10O;
	assign		wire_nllOOOO_dataout = (nlillii === 1'b1) ? nllO1ii : nlllOiO;
	assign		wire_nlO_dataout = (rwa_6g_en === 1'b1) ? wire_nl0l1l_dataout : wire_n10OOi_dataout;
	assign		wire_nlO000i_dataout = (rclkcmpinsertpad === 1'b1) ? (~ nllOiOl) : nllOiOl;
	assign		wire_nlO000l_dataout = (rclkcmpinsertpad === 1'b1) ? nllOiOl : (~ nllOiOl);
	or(wire_nlO001i_dataout, nllOl1i, wire_n110ll_dataout);
	assign		wire_nlO010i_dataout = (wire_n110ll_dataout === 1'b1) ? nlllOll : nllOi1O;
	assign		wire_nlO010l_dataout = (wire_n110ll_dataout === 1'b1) ? nlllOlO : nllOi0i;
	assign		wire_nlO010O_dataout = (wire_n110ll_dataout === 1'b1) ? nlllOOi : nllOi0l;
	assign		wire_nlO011i_dataout = (wire_n110ll_dataout === 1'b1) ? nllO10O : nllO0OO;
	assign		wire_nlO011l_dataout = (wire_n110ll_dataout === 1'b1) ? nlllOiO : nllOi1i;
	assign		wire_nlO011O_dataout = (wire_n110ll_dataout === 1'b1) ? nlllOli : nllOi1l;
	assign		wire_nlO01ii_dataout = (wire_n110ll_dataout === 1'b1) ? nlllOOl : nllOi0O;
	assign		wire_nlO01il_dataout = (wire_n110ll_dataout === 1'b1) ? nlllOOO : nllOiii;
	assign		wire_nlO01iO_dataout = (wire_n110ll_dataout === 1'b1) ? nllO11i : nllOiil;
	assign		wire_nlO01li_dataout = (wire_n110ll_dataout === 1'b1) ? nllO11l : nllOiiO;
	and(wire_nlO01ll_dataout, nllOili, ~(wire_n110ll_dataout));
	assign		wire_nlO01lO_dataout = (wire_n110ll_dataout === 1'b1) ? nllO11O : nllOill;
	and(wire_nlO01Oi_dataout, nllOilO, ~(wire_n110ll_dataout));
	assign		wire_nlO01Ol_dataout = (wire_n110ll_dataout === 1'b1) ? nllO10i : nllOiOl;
	and(wire_nlO01OO_dataout, nllOiOO, ~(wire_n110ll_dataout));
	assign		wire_nlO0i_dataout = (rwa_6g_en === 1'b1) ? nii1il : nlO0iil;
	assign		wire_nlO0l_dataout = (rwa_6g_en === 1'b1) ? nii1iO : nlO0iiO;
	assign		wire_nlO0O_dataout = (rwa_6g_en === 1'b1) ? nii1li : nlO0ili;
	and(wire_nlO0Oll_dataout, wire_nlOil1i_dataout, ~(nliO1Oi));
	and(wire_nlO0OlO_dataout, wire_nlOil1l_dataout, ~(nliO1Oi));
	and(wire_nlO0OOi_dataout, wire_nlOil1O_dataout, ~(nliO1Oi));
	and(wire_nlO0OOl_dataout, wire_nlOil0i_dataout, ~(nliO1Oi));
	and(wire_nlO0OOO_dataout, wire_nlOil0l_dataout, ~(nliO1Oi));
	assign		wire_nlO100i_dataout = (nlillii === 1'b1) ? nllO0ll : nllO1Ol;
	assign		wire_nlO100l_dataout = (nlillii === 1'b1) ? nllO0lO : nllO1OO;
	assign		wire_nlO100O_dataout = (nlillii === 1'b1) ? nllO0Oi : nllO01i;
	assign		wire_nlO101i_dataout = (nlillii === 1'b1) ? nllO0il : nllO1ll;
	assign		wire_nlO101l_dataout = (nlillii === 1'b1) ? nllO0iO : nllO1lO;
	assign		wire_nlO101O_dataout = (nlillii === 1'b1) ? nllO0li : nllO1Oi;
	assign		wire_nlO10ii_dataout = (nlillii === 1'b1) ? nllO0Ol : nllO01l;
	assign		wire_nlO10il_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[0] : wire_nlO1iiO_dataout;
	assign		wire_nlO10iO_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[1] : wire_nlO1ili_dataout;
	assign		wire_nlO10li_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[2] : wire_nlO1ill_dataout;
	assign		wire_nlO10ll_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[3] : wire_nlO1ilO_dataout;
	assign		wire_nlO10lO_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[4] : wire_nlO1iOi_dataout;
	assign		wire_nlO10Oi_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[5] : wire_nlO1iOl_dataout;
	assign		wire_nlO10Ol_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[6] : wire_nlO1iOO_dataout;
	assign		wire_nlO10OO_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[7] : wire_nlO1l1i_dataout;
	assign		wire_nlO110i_dataout = (nlillii === 1'b1) ? nllO1ll : nlllOOi;
	assign		wire_nlO110l_dataout = (nlillii === 1'b1) ? nllO1lO : nlllOOl;
	assign		wire_nlO110O_dataout = (nlillii === 1'b1) ? nllO1Oi : nlllOOO;
	assign		wire_nlO111i_dataout = (nlillii === 1'b1) ? nllO1il : nlllOli;
	assign		wire_nlO111l_dataout = (nlillii === 1'b1) ? nllO1iO : nlllOll;
	assign		wire_nlO111O_dataout = (nlillii === 1'b1) ? nllO1li : nlllOlO;
	assign		wire_nlO11ii_dataout = (nlillii === 1'b1) ? nllO1Ol : nllO11i;
	assign		wire_nlO11il_dataout = (nlillii === 1'b1) ? nllO1OO : nllO11l;
	assign		wire_nlO11iO_dataout = (nlillii === 1'b1) ? nllO01i : nllO11O;
	assign		wire_nlO11li_dataout = (nlillii === 1'b1) ? nllO01l : nllO10i;
	assign		wire_nlO11ll_dataout = (nlillii === 1'b1) ? nllO01O : nllO10l;
	assign		wire_nlO11lO_dataout = (nlillii === 1'b1) ? nllO00i : nllO1ii;
	assign		wire_nlO11Oi_dataout = (nlillii === 1'b1) ? nllO00l : nllO1il;
	assign		wire_nlO11Ol_dataout = (nlillii === 1'b1) ? nllO00O : nllO1iO;
	assign		wire_nlO11OO_dataout = (nlillii === 1'b1) ? nllO0ii : nllO1li;
	assign		wire_nlO1i_dataout = (rwa_6g_en === 1'b1) ? nii10l : nlO0i0l;
	assign		wire_nlO1i0i_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[11] : wire_nlO1l0l_dataout;
	assign		wire_nlO1i0l_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[12] : wire_nlO1l0O_dataout;
	assign		wire_nlO1i0O_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[13] : wire_nlO1lii_dataout;
	assign		wire_nlO1i1i_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[8] : wire_nlO1l1l_dataout;
	assign		wire_nlO1i1l_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[9] : wire_nlO1l1O_dataout;
	assign		wire_nlO1i1O_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[10] : wire_nlO1l0i_dataout;
	assign		wire_nlO1iii_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[14] : wire_nlO1lil_dataout;
	assign		wire_nlO1iil_dataout = (nlillii === 1'b1) ? wire_nlOiiO_data_out1[15] : wire_nlO1liO_dataout;
	assign		wire_nlO1iiO_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1lOO_dataout : nllO0OO;
	assign		wire_nlO1ili_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1O1i_dataout : nllOi1i;
	assign		wire_nlO1ill_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1O1l_dataout : nllOi1l;
	assign		wire_nlO1ilO_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1O1O_dataout : nllOi1O;
	assign		wire_nlO1iOi_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1O0i_dataout : nllOi0i;
	assign		wire_nlO1iOl_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1O0l_dataout : nllOi0l;
	assign		wire_nlO1iOO_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1O0O_dataout : nllOi0O;
	assign		wire_nlO1l_dataout = (rwa_6g_en === 1'b1) ? nii10O : nlO0i0O;
	assign		wire_nlO1l0i_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1Oli_dataout : wire_nlO1lli_dataout;
	assign		wire_nlO1l0l_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1Oll_dataout : nllOill;
	assign		wire_nlO1l0O_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1OlO_dataout : wire_nlO1lll_dataout;
	assign		wire_nlO1l1i_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1Oii_dataout : nllOiii;
	assign		wire_nlO1l1l_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1Oil_dataout : nllOiil;
	assign		wire_nlO1l1O_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1OiO_dataout : nllOiiO;
	assign		wire_nlO1lii_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1OOi_dataout : nllOiOl;
	and(wire_nlO1lil_dataout, wire_nlO1OOl_dataout, rclkcmpsqmd);
	assign		wire_nlO1liO_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlO1OOO_dataout : (~ rrx_pipe_enable);
	and(wire_nlO1lli_dataout, wire_nlO1llO_dataout, ~(rrx_pipe_enable));
	and(wire_nlO1lll_dataout, wire_nlO1lOi_dataout, ~(rrx_pipe_enable));
	and(wire_nlO1llO_dataout, nllOili, nlill0O);
	and(wire_nlO1lOi_dataout, nllOilO, nlill0O);
	assign		wire_nlO1lOO_dataout = (n1O0iO === 1'b1) ? nllO10l : wire_nlO011i_dataout;
	assign		wire_nlO1O_dataout = (rwa_6g_en === 1'b1) ? nii1ii : nlO0iii;
	assign		wire_nlO1O0i_dataout = (n1O0iO === 1'b1) ? nllO1li : wire_nlO010l_dataout;
	assign		wire_nlO1O0l_dataout = (n1O0iO === 1'b1) ? nllO1ll : wire_nlO010O_dataout;
	assign		wire_nlO1O0O_dataout = (n1O0iO === 1'b1) ? nllO1lO : wire_nlO01ii_dataout;
	assign		wire_nlO1O1i_dataout = (n1O0iO === 1'b1) ? nllO1ii : wire_nlO011l_dataout;
	assign		wire_nlO1O1l_dataout = (n1O0iO === 1'b1) ? nllO1il : wire_nlO011O_dataout;
	assign		wire_nlO1O1O_dataout = (n1O0iO === 1'b1) ? nllO1iO : wire_nlO010i_dataout;
	assign		wire_nlO1Oii_dataout = (n1O0iO === 1'b1) ? nllO1Oi : wire_nlO01il_dataout;
	assign		wire_nlO1Oil_dataout = (n1O0iO === 1'b1) ? nllO1Ol : wire_nlO01iO_dataout;
	assign		wire_nlO1OiO_dataout = (n1O0iO === 1'b1) ? nllO1OO : wire_nlO01li_dataout;
	and(wire_nlO1Oli_dataout, wire_nlO01ll_dataout, ~(n1O0iO));
	assign		wire_nlO1Oll_dataout = (n1O0iO === 1'b1) ? nllO01i : wire_nlO01lO_dataout;
	and(wire_nlO1OlO_dataout, wire_nlO01Oi_dataout, ~(n1O0iO));
	assign		wire_nlO1OOi_dataout = (n1O0iO === 1'b1) ? nllO01l : wire_nlO01Ol_dataout;
	and(wire_nlO1OOl_dataout, wire_nlO01OO_dataout, ~(n1O0iO));
	or(wire_nlO1OOO_dataout, wire_nlO001i_dataout, n1O0iO);
	assign		wire_nlOi_dataout = (rwa_6g_en === 1'b1) ? nli10O : n1ii1i;
	and(wire_nlOi00i_dataout, wire_nlOiOiO_dataout, ~(nliO1Oi));
	and(wire_nlOi00l_dataout, wire_nlOiOli_dataout, ~(nliO1Oi));
	and(wire_nlOi00O_dataout, wire_nlOiOll_dataout, ~(nliO1Oi));
	and(wire_nlOi01i_dataout, wire_nlOiO0O_dataout, ~(nliO1Oi));
	and(wire_nlOi01l_dataout, wire_nlOiOii_dataout, ~(nliO1Oi));
	and(wire_nlOi01O_dataout, wire_nlOiOil_dataout, ~(nliO1Oi));
	and(wire_nlOi0ii_dataout, wire_nlOiOlO_dataout, ~(nliO1Oi));
	and(wire_nlOi0il_dataout, wire_nlOiOOi_dataout, ~(nliO1Oi));
	and(wire_nlOi0iO_dataout, wire_nlOiOOl_dataout, ~(nliO1Oi));
	and(wire_nlOi0li_dataout, wire_nlOiOOO_dataout, ~(nliO1Oi));
	or(wire_nlOi0ll_dataout, wire_nlOl11i_dataout, nliO1Oi);
	and(wire_nlOi0lO_dataout, wire_nlOl11l_dataout, ~(nliO1Oi));
	and(wire_nlOi0Oi_dataout, wire_nlOl11O_dataout, ~(nliO1Oi));
	and(wire_nlOi0Ol_dataout, wire_nlOl10i_dataout, ~(nliO1Oi));
	and(wire_nlOi0OO_dataout, wire_nlOl10l_dataout, ~(nliO1Oi));
	and(wire_nlOi10i_dataout, wire_nlOiliO_dataout, ~(nliO1Oi));
	and(wire_nlOi10l_dataout, wire_nlOilli_dataout, ~(nliO1Oi));
	and(wire_nlOi10O_dataout, wire_nlOilll_dataout, ~(nliO1Oi));
	and(wire_nlOi11i_dataout, wire_nlOil0O_dataout, ~(nliO1Oi));
	and(wire_nlOi11l_dataout, wire_nlOilii_dataout, ~(nliO1Oi));
	and(wire_nlOi11O_dataout, wire_nlOilil_dataout, ~(nliO1Oi));
	or(wire_nlOi1ii_dataout, wire_nlOillO_dataout, nliO1Oi);
	and(wire_nlOi1il_dataout, wire_nlOilOi_dataout, ~(nliO1Oi));
	and(wire_nlOi1iO_dataout, wire_nlOilOl_dataout, ~(nliO1Oi));
	and(wire_nlOi1li_dataout, wire_nlOilOO_dataout, ~(nliO1Oi));
	and(wire_nlOi1ll_dataout, wire_nlOiO1i_dataout, ~(nliO1Oi));
	and(wire_nlOi1lO_dataout, wire_nlOiO1l_dataout, ~(nliO1Oi));
	and(wire_nlOi1Oi_dataout, wire_nlOiO1O_dataout, ~(nliO1Oi));
	and(wire_nlOi1Ol_dataout, wire_nlOiO0i_dataout, ~(nliO1Oi));
	and(wire_nlOi1OO_dataout, wire_nlOiO0l_dataout, ~(nliO1Oi));
	assign		wire_nlOii_dataout = (rwa_6g_en === 1'b1) ? nii1ll : nlO0ill;
	and(wire_nlOii0i_dataout, wire_nlOl1iO_dataout, ~(nliO1Oi));
	and(wire_nlOii0l_dataout, wire_nlOl1li_dataout, ~(nliO1Oi));
	and(wire_nlOii0O_dataout, wire_nlOl1ll_dataout, ~(nliO1Oi));
	and(wire_nlOii1i_dataout, wire_nlOl10O_dataout, ~(nliO1Oi));
	and(wire_nlOii1l_dataout, wire_nlOl1ii_dataout, ~(nliO1Oi));
	and(wire_nlOii1O_dataout, wire_nlOl1il_dataout, ~(nliO1Oi));
	and(wire_nlOiiii_dataout, wire_nlOl1lO_dataout, ~(nliO1Oi));
	and(wire_nlOiiil_dataout, wire_nlOl1Oi_dataout, ~(nliO1Oi));
	and(wire_nlOiiiO_dataout, wire_nlOl1Ol_dataout, ~(nliO1Oi));
	and(wire_nlOiili_dataout, wire_nlOl1OO_dataout, ~(nliO1Oi));
	and(wire_nlOiill_dataout, wire_nlOl01i_dataout, ~(nliO1Oi));
	and(wire_nlOiilO_dataout, wire_nlOl01l_dataout, ~(nliO1Oi));
	and(wire_nlOiiOi_dataout, wire_nlOl01O_dataout, ~(nliO1Oi));
	and(wire_nlOiiOl_dataout, wire_nlOl00i_dataout, ~(nliO1Oi));
	and(wire_nlOiiOO_dataout, wire_nlOl00l_dataout, ~(nliO1Oi));
	assign		wire_nlOil_dataout = (rwa_6g_en === 1'b1) ? nii1lO : nlO0ilO;
	assign		wire_nlOil0i_dataout = (nlilllO === 1'b1) ? nlillli : nlO00il;
	assign		wire_nlOil0l_dataout = (nlilllO === 1'b1) ? (((wire_nlOl0Oi_o[18] | wire_nlOl0Oi_o[17]) | wire_nlOl0Oi_o[16]) | wire_nlOl0Oi_o[15]) : nlO00iO;
	assign		wire_nlOil0O_dataout = (nlilllO === 1'b1) ? wire_nlOl0Ol_dataout : nlO00li;
	assign		wire_nlOil1i_dataout = (nlilllO === 1'b1) ? nlillil : nllOl1l;
	assign		wire_nlOil1l_dataout = (nlilllO === 1'b1) ? (((wire_nlOl0iO_o[4] | wire_nlOl0iO_o[3]) | wire_nlOl0iO_o[2]) | wire_nlOl0iO_o[1]) : nlO000O;
	assign		wire_nlOil1O_dataout = (nlilllO === 1'b1) ? nlilliO : nlO00ii;
	assign		wire_nlOilii_dataout = (nlilllO === 1'b1) ? wire_nlOl0OO_dataout : nlO00ll;
	assign		wire_nlOilil_dataout = (nlilllO === 1'b1) ? wire_nlOli1i_dataout : nlO00lO;
	assign		wire_nlOiliO_dataout = (nlilllO === 1'b1) ? wire_nlOli1l_dataout : nlO00Oi;
	assign		wire_nlOilli_dataout = (nlilllO === 1'b1) ? wire_nlOli1O_dataout : nlO00Ol;
	assign		wire_nlOilll_dataout = (nlilllO === 1'b1) ? nlO0l0i : nlO00OO;
	assign		wire_nlOillO_dataout = (nlilllO === 1'b1) ? nlO00OO : nlO0i1i;
	assign		wire_nlOilOi_dataout = (nlilllO === 1'b1) ? nlO0i1i : nlO0i1l;
	assign		wire_nlOilOl_dataout = (nlilllO === 1'b1) ? nlO0i1l : nlO0i1O;
	assign		wire_nlOilOO_dataout = (nlilllO === 1'b1) ? nlO0i1O : nlO0i0i;
	assign		wire_nlOiO_dataout = (rwa_6g_en === 1'b1) ? nii1Oi : nlO0iOi;
	assign		wire_nlOiO0i_dataout = (nlilllO === 1'b1) ? nlO0iii : nlO0iil;
	assign		wire_nlOiO0l_dataout = (nlilllO === 1'b1) ? nlO0iil : nlO0iiO;
	assign		wire_nlOiO0O_dataout = (nlilllO === 1'b1) ? nlO0iiO : nlO0ili;
	assign		wire_nlOiO1i_dataout = (nlilllO === 1'b1) ? nlO0i0i : nlO0i0l;
	assign		wire_nlOiO1l_dataout = (nlilllO === 1'b1) ? nlO0i0l : nlO0i0O;
	assign		wire_nlOiO1O_dataout = (nlilllO === 1'b1) ? nlO0i0O : nlO0iii;
	assign		wire_nlOiOii_dataout = (nlilllO === 1'b1) ? nlO0ili : nlO0ill;
	assign		wire_nlOiOil_dataout = (nlilllO === 1'b1) ? nlO0ill : nlO0ilO;
	assign		wire_nlOiOiO_dataout = (nlilllO === 1'b1) ? nlO0ilO : nlO0iOi;
	assign		wire_nlOiOli_dataout = (nlilllO === 1'b1) ? nlO0iOi : nlO0iOl;
	assign		wire_nlOiOll_dataout = (nlilllO === 1'b1) ? nlO0iOl : nlO0iOO;
	assign		wire_nlOiOlO_dataout = (nlilllO === 1'b1) ? nlO0iOO : nlO0l1i;
	assign		wire_nlOiOOi_dataout = (nlilllO === 1'b1) ? nlO0l1i : nlO0l1l;
	assign		wire_nlOiOOl_dataout = (nlilllO === 1'b1) ? nlO0l1l : nlO0l1O;
	assign		wire_nlOiOOO_dataout = (nlilllO === 1'b1) ? nlO0l1O : nlO0l0i;
	assign		wire_nlOl_dataout = (rwa_6g_en === 1'b1) ? nli1ii : n1ii1l;
	assign		wire_nlOl00i_dataout = (nlilllO === 1'b1) ? nlO0Oii : nlO0Oil;
	assign		wire_nlOl00l_dataout = (nlilllO === 1'b1) ? nlO0Oil : nlO0OiO;
	assign		wire_nlOl01i_dataout = (nlilllO === 1'b1) ? nlO0O0i : nlO0O0l;
	assign		wire_nlOl01l_dataout = (nlilllO === 1'b1) ? nlO0O0l : nlO0O0O;
	assign		wire_nlOl01O_dataout = (nlilllO === 1'b1) ? nlO0O0O : nlO0Oii;
	and(wire_nlOl0i_dataout, wire_nlOl0O_dataout, ~((~ wire_nli0i_dataout)));
	and(wire_nlOl0l_dataout, nlOill, ~(wire_n0iO_dataout));
	and(wire_nlOl0O_dataout, nlOO1l, ~(wire_n0iO_dataout));
	and(wire_nlOl0Ol_dataout, wire_nlOli0i_o[0], ~(nlillll));
	and(wire_nlOl0OO_dataout, wire_nlOli0i_o[1], ~(nlillll));
	assign		wire_nlOl10i_dataout = (nlilllO === 1'b1) ? nlO0lii : nlO0lil;
	assign		wire_nlOl10l_dataout = (nlilllO === 1'b1) ? nlO0lil : nlO0liO;
	assign		wire_nlOl10O_dataout = (nlilllO === 1'b1) ? nlO0liO : nlO0lli;
	assign		wire_nlOl11i_dataout = (nlilllO === 1'b1) ? nlO0OiO : nlO0l0l;
	assign		wire_nlOl11l_dataout = (nlilllO === 1'b1) ? nlO0l0l : nlO0l0O;
	assign		wire_nlOl11O_dataout = (nlilllO === 1'b1) ? nlO0l0O : nlO0lii;
	assign		wire_nlOl1ii_dataout = (nlilllO === 1'b1) ? nlO0lli : nlO0lll;
	assign		wire_nlOl1il_dataout = (nlilllO === 1'b1) ? nlO0lll : nlO0llO;
	assign		wire_nlOl1iO_dataout = (nlilllO === 1'b1) ? nlO0llO : nlO0lOi;
	and(wire_nlOl1l_dataout, wire_n0iO_dataout, ~((~ wire_nli0i_dataout)));
	assign		wire_nlOl1li_dataout = (nlilllO === 1'b1) ? nlO0lOi : nlO0lOl;
	assign		wire_nlOl1ll_dataout = (nlilllO === 1'b1) ? nlO0lOl : nlO0lOO;
	assign		wire_nlOl1lO_dataout = (nlilllO === 1'b1) ? nlO0lOO : nlO0O1i;
	and(wire_nlOl1O_dataout, wire_nlOl0l_dataout, ~((~ wire_nli0i_dataout)));
	assign		wire_nlOl1Oi_dataout = (nlilllO === 1'b1) ? nlO0O1i : nlO0O1l;
	assign		wire_nlOl1Ol_dataout = (nlilllO === 1'b1) ? nlO0O1l : nlO0O1O;
	assign		wire_nlOl1OO_dataout = (nlilllO === 1'b1) ? nlO0O1O : nlO0O0i;
	assign		wire_nlOli_dataout = (rwa_6g_en === 1'b1) ? nii1Ol : nlO0iOl;
	and(wire_nlOli1i_dataout, wire_nlOli0i_o[2], ~(nlillll));
	and(wire_nlOli1l_dataout, wire_nlOli0i_o[3], ~(nlillll));
	and(wire_nlOli1O_dataout, wire_nlOli0i_o[4], ~(nlillll));
	assign		wire_nlOlii_dataout = ((~ wire_nli0i_dataout) === 1'b1) ? nlOO1l : wire_nlOlli_dataout;
	assign		wire_nlOlil_dataout = ((~ wire_nli0i_dataout) === 1'b1) ? nlOill : wire_nlOlll_dataout;
	and(wire_nlOliO_dataout, (~ nll1O1l), ~((~ wire_nli0i_dataout)));
	assign		wire_nlOll_dataout = (rwa_6g_en === 1'b1) ? nii1OO : nlO0iOO;
	assign		wire_nlOlli_dataout = (nll1O1l === 1'b1) ? wire_n0ii_dataout : nlOO1l;
	assign		wire_nlOlll_dataout = (nll1O1l === 1'b1) ? wire_n0il_dataout : nlOill;
	assign		wire_nlOlO_dataout = (rwa_6g_en === 1'b1) ? nii01i : nlO0l1i;
	and(wire_nlOlOi_dataout, wire_n00O_dataout, wire_nli0i_dataout);
	and(wire_nlOlOOl_dataout, wire_nlOO0iO_dataout, ~(nliO0il));
	and(wire_nlOlOOO_dataout, wire_nlOO0li_dataout, ~(nliO0il));
	assign		wire_nlOO_dataout = (rwa_6g_en === 1'b1) ? nli1il : n1ii1O;
	and(wire_nlOO00i_dataout, wire_nlOOiOl_dataout, ~(nliO0il));
	and(wire_nlOO00l_dataout, wire_nlOOiOO_dataout, ~(nliO0il));
	and(wire_nlOO00O_dataout, wire_nlOOl1i_dataout, ~(nliO0il));
	and(wire_nlOO01i_dataout, wire_nlOOill_dataout, ~(nliO0il));
	and(wire_nlOO01l_dataout, wire_nlOOilO_dataout, ~(nliO0il));
	and(wire_nlOO01O_dataout, wire_nlOOiOi_dataout, ~(nliO0il));
	and(wire_nlOO0ii_dataout, wire_nlOOl1l_dataout, ~(nliO0il));
	and(wire_nlOO0il_dataout, wire_nlOOl1O_dataout, ~(nliO0il));
	assign		wire_nlOO0iO_dataout = (nliO00O === 1'b1) ? wire_n111ii_dataout : wire_nlOOl0i_dataout;
	assign		wire_nlOO0li_dataout = (nliO00O === 1'b1) ? wire_n111il_dataout : wire_nlOOl0l_dataout;
	assign		wire_nlOO0ll_dataout = (nliO00O === 1'b1) ? wire_n111iO_dataout : wire_nlOOl0O_dataout;
	assign		wire_nlOO0lO_dataout = (nliO00O === 1'b1) ? wire_n111li_dataout : wire_nlOOlii_dataout;
	assign		wire_nlOO0Oi_dataout = (nliO00O === 1'b1) ? wire_n111ll_dataout : wire_nlOOlil_dataout;
	assign		wire_nlOO0Ol_dataout = (nliO00O === 1'b1) ? nlOlOlO : wire_nlOOliO_dataout;
	assign		wire_nlOO0OO_dataout = (nliO00O === 1'b1) ? nlOllil : wire_nlOOlli_dataout;
	or(wire_nlOO10i_dataout, wire_nlOO0Ol_dataout, nliO0il);
	and(wire_nlOO10l_dataout, wire_nlOO0OO_dataout, ~(nliO0il));
	and(wire_nlOO10O_dataout, wire_nlOOi1i_dataout, ~(nliO0il));
	and(wire_nlOO11i_dataout, wire_nlOO0ll_dataout, ~(nliO0il));
	and(wire_nlOO11l_dataout, wire_nlOO0lO_dataout, ~(nliO0il));
	and(wire_nlOO11O_dataout, wire_nlOO0Oi_dataout, ~(nliO0il));
	and(wire_nlOO1ii_dataout, wire_nlOOi1l_dataout, ~(nliO0il));
	and(wire_nlOO1il_dataout, wire_nlOOi1O_dataout, ~(nliO0il));
	and(wire_nlOO1iO_dataout, wire_nlOOi0i_dataout, ~(nliO0il));
	and(wire_nlOO1li_dataout, wire_nlOOi0l_dataout, ~(nliO0il));
	and(wire_nlOO1ll_dataout, wire_nlOOi0O_dataout, ~(nliO0il));
	and(wire_nlOO1lO_dataout, wire_nlOOiii_dataout, ~(nliO0il));
	and(wire_nlOO1Oi_dataout, wire_nlOOiil_dataout, ~(nliO0il));
	and(wire_nlOO1Ol_dataout, wire_nlOOiiO_dataout, ~(nliO0il));
	and(wire_nlOO1OO_dataout, wire_nlOOili_dataout, ~(nliO0il));
	assign		wire_nlOOi_dataout = (rwa_6g_en === 1'b1) ? nii01l : nlO0l1l;
	assign		wire_nlOOi0i_dataout = (nliO00O === 1'b1) ? nlOlllO : wire_nlOOlOl_dataout;
	assign		wire_nlOOi0l_dataout = (nliO00O === 1'b1) ? nlOllOi : wire_nlOOlOO_dataout;
	assign		wire_nlOOi0O_dataout = (nliO00O === 1'b1) ? nlOllOl : wire_nlOOO1i_dataout;
	assign		wire_nlOOi1i_dataout = (nliO00O === 1'b1) ? nlOlliO : wire_nlOOlll_dataout;
	assign		wire_nlOOi1l_dataout = (nliO00O === 1'b1) ? nlOllli : wire_nlOOllO_dataout;
	assign		wire_nlOOi1O_dataout = (nliO00O === 1'b1) ? nlOllll : wire_nlOOlOi_dataout;
	assign		wire_nlOOiii_dataout = (nliO00O === 1'b1) ? nlOllOO : wire_nlOOO1l_dataout;
	assign		wire_nlOOiil_dataout = (nliO00O === 1'b1) ? nlOlO1i : wire_nlOOO1O_dataout;
	assign		wire_nlOOiiO_dataout = (nliO00O === 1'b1) ? nlOlO1l : wire_nlOOO0i_dataout;
	assign		wire_nlOOili_dataout = (nliO00O === 1'b1) ? nlOlO1O : wire_nlOOO0l_dataout;
	assign		wire_nlOOill_dataout = (nliO00O === 1'b1) ? nlOlO0i : wire_nlOOO0O_dataout;
	assign		wire_nlOOilO_dataout = (nliO00O === 1'b1) ? nlOlO0l : wire_nlOOOii_dataout;
	assign		wire_nlOOiOi_dataout = (nliO00O === 1'b1) ? nlOlO0O : wire_nlOOOil_dataout;
	assign		wire_nlOOiOl_dataout = (nliO00O === 1'b1) ? nlOlOii : wire_nlOOOiO_dataout;
	assign		wire_nlOOiOO_dataout = (nliO00O === 1'b1) ? nlOlOil : wire_nlOOOli_dataout;
	assign		wire_nlOOl_dataout = (rwa_6g_en === 1'b1) ? nii01O : nlO0l1O;
	assign		wire_nlOOl0i_dataout = (nlillOl === 1'b1) ? wire_nlOOOOl_dataout : nlO0Oli;
	assign		wire_nlOOl0l_dataout = (nlillOl === 1'b1) ? wire_nlOOOOO_dataout : nlOliiO;
	assign		wire_nlOOl0O_dataout = (nlillOl === 1'b1) ? wire_n1111i_dataout : nlOlili;
	assign		wire_nlOOl1i_dataout = (nliO00O === 1'b1) ? nlOlOiO : wire_nlOOOll_dataout;
	assign		wire_nlOOl1l_dataout = (nliO00O === 1'b1) ? nlOlOli : wire_nlOOOlO_dataout;
	assign		wire_nlOOl1O_dataout = (nliO00O === 1'b1) ? nlOlOll : wire_nlOOOOi_dataout;
	assign		wire_nlOOlii_dataout = (nlillOl === 1'b1) ? wire_n1111l_dataout : nlOlill;
	assign		wire_nlOOlil_dataout = (nlillOl === 1'b1) ? wire_n1111O_dataout : nlOlilO;
	assign		wire_nlOOliO_dataout = (nlillOl === 1'b1) ? nlOlliO : nlOllil;
	assign		wire_nlOOlli_dataout = (nlillOl === 1'b1) ? nlOllli : nlOlliO;
	assign		wire_nlOOlll_dataout = (nlillOl === 1'b1) ? nlOllll : nlOllli;
	assign		wire_nlOOllO_dataout = (nlillOl === 1'b1) ? nlOlllO : nlOllll;
	assign		wire_nlOOlOi_dataout = (nlillOl === 1'b1) ? nlOllOi : nlOlllO;
	assign		wire_nlOOlOl_dataout = (nlillOl === 1'b1) ? nlOllOl : nlOllOi;
	assign		wire_nlOOlOO_dataout = (nlillOl === 1'b1) ? nlOllOO : nlOllOl;
	assign		wire_nlOOO_dataout = (rwa_6g_en === 1'b1) ? nii00i : nlO0l0i;
	assign		wire_nlOOO0i_dataout = (nlillOl === 1'b1) ? nlOlO0i : nlOlO1O;
	assign		wire_nlOOO0l_dataout = (nlillOl === 1'b1) ? nlOlO0l : nlOlO0i;
	assign		wire_nlOOO0O_dataout = (nlillOl === 1'b1) ? nlOlO0O : nlOlO0l;
	assign		wire_nlOOO1i_dataout = (nlillOl === 1'b1) ? nlOlO1i : nlOllOO;
	assign		wire_nlOOO1l_dataout = (nlillOl === 1'b1) ? nlOlO1l : nlOlO1i;
	assign		wire_nlOOO1O_dataout = (nlillOl === 1'b1) ? nlOlO1O : nlOlO1l;
	assign		wire_nlOOOii_dataout = (nlillOl === 1'b1) ? nlOlOii : nlOlO0O;
	assign		wire_nlOOOil_dataout = (nlillOl === 1'b1) ? nlOlOil : nlOlOii;
	assign		wire_nlOOOiO_dataout = (nlillOl === 1'b1) ? nlOlOiO : nlOlOil;
	assign		wire_nlOOOli_dataout = (nlillOl === 1'b1) ? nlOlOli : nlOlOiO;
	assign		wire_nlOOOll_dataout = (nlillOl === 1'b1) ? nlOlOll : nlOlOli;
	assign		wire_nlOOOlO_dataout = (nlillOl === 1'b1) ? nlOlOlO : nlOlOll;
	assign		wire_nlOOOOi_dataout = (nlillOl === 1'b1) ? nlOllil : nlOlOlO;
	or(wire_nlOOOOl_dataout, wire_n1110i_o[1], nlillOi);
	or(wire_nlOOOOO_dataout, wire_n1110i_o[2], nlillOi);
	oper_add   n1110i
	( 
	.a({nlOlilO, nlOlill, nlOlili, nlOliiO, nlO0Oli, 1'b1}),
	.b({{4{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1110i_o));
	defparam
		n1110i.sgate_representation = 0,
		n1110i.width_a = 6,
		n1110i.width_b = 6,
		n1110i.width_o = 6;
	oper_add   n111lO
	( 
	.a({nlOlilO, nlOlill, nlOlili, nlOliiO, nlO0Oli}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n111lO_o));
	defparam
		n111lO.sgate_representation = 0,
		n111lO.width_a = 5,
		n111lO.width_b = 5,
		n111lO.width_o = 5;
	oper_add   n1i0ll
	( 
	.a({1'b0, (~ ralempty[3]), (~ ralempty[2]), (~ ralempty[1]), (~ ralempty[0]), 1'b1}),
	.b({{5{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1i0ll_o));
	defparam
		n1i0ll.sgate_representation = 0,
		n1i0ll.width_a = 6,
		n1i0ll.width_b = 6,
		n1i0ll.width_o = 6;
	oper_add   n1i0Ol
	( 
	.a({1'b0, ralfull[3:2]}),
	.b({{2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1i0Ol_o));
	defparam
		n1i0Ol.sgate_representation = 0,
		n1i0Ol.width_a = 3,
		n1i0Ol.width_b = 3,
		n1i0Ol.width_o = 3;
	oper_add   n1ilii
	( 
	.a({(~ wire_n1ilil_o[5]), (~ wire_n1ilil_o[4]), (~ wire_n1ilil_o[3]), (~ wire_n1ilil_o[2]), (~ wire_n1ilil_o[1]), 1'b1}),
	.b({1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1ilii_o));
	defparam
		n1ilii.sgate_representation = 0,
		n1ilii.width_a = 6,
		n1ilii.width_b = 6,
		n1ilii.width_o = 6;
	oper_add   n1ilil
	( 
	.a({nlOll1l, nliO1il, nliO1iO, nliO1li, nliO1ll, 1'b1}),
	.b({(~ nlOlilO), (~ nlOlill), (~ nlOlili), (~ nlOliiO), (~ nlO0Oli), 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1ilil_o));
	defparam
		n1ilil.sgate_representation = 0,
		n1ilil.width_a = 6,
		n1ilil.width_b = 6,
		n1ilil.width_o = 6;
	oper_add   n1iliO
	( 
	.a({nlOlilO, nlOlill, nlOlili, nlOliiO, nlO0Oli, 1'b1}),
	.b({(~ nlOll1l), (~ nliO1il), (~ nliO1iO), (~ nliO1li), (~ nliO1ll), 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1iliO_o));
	defparam
		n1iliO.sgate_representation = 0,
		n1iliO.width_a = 6,
		n1iliO.width_b = 6,
		n1iliO.width_o = 6;
	oper_add   n1llOl
	( 
	.a({n1li1i, n1l0OO, n1l0Ol, n1l0Oi, n1l0lO, 1'b1}),
	.b({{4{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1llOl_o));
	defparam
		n1llOl.sgate_representation = 0,
		n1llOl.width_a = 6,
		n1llOl.width_b = 6,
		n1llOl.width_o = 6;
	oper_add   n1llOO
	( 
	.a({n1li1i, n1l0OO, n1l0Ol, n1l0Oi, n1l0lO}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1llOO_o));
	defparam
		n1llOO.sgate_representation = 0,
		n1llOO.width_a = 5,
		n1llOO.width_b = 5,
		n1llOO.width_o = 5;
	oper_add   n1lO0O
	( 
	.a({n1li1i, n1l0OO, n1l0Ol, n1l0Oi}),
	.b({{3{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1lO0O_o));
	defparam
		n1lO0O.sgate_representation = 0,
		n1lO0O.width_a = 4,
		n1lO0O.width_b = 4,
		n1lO0O.width_o = 4;
	oper_add   n1lOil
	( 
	.a({n1li1i, n1l0OO, n1l0Ol, n1l0Oi, n1l0lO}),
	.b({{3{1'b0}}, {2{1'b1}}}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1lOil_o));
	defparam
		n1lOil.sgate_representation = 0,
		n1lOil.width_a = 5,
		n1lOil.width_b = 5,
		n1lOil.width_o = 5;
	oper_add   n1OilO
	( 
	.a({n1O0lO, n1O0ll, n1O0li}),
	.b({{2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n1OilO_o));
	defparam
		n1OilO.sgate_representation = 0,
		n1OilO.width_a = 3,
		n1OilO.width_b = 3,
		n1OilO.width_o = 3;
	oper_add   niO10l
	( 
	.a({ni0OOl, ni0OOi, ni0OlO, ni0Oll, ni0Oli}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_niO10l_o));
	defparam
		niO10l.sgate_representation = 0,
		niO10l.width_a = 5,
		niO10l.width_b = 5,
		niO10l.width_o = 5;
	oper_add   nl10ll
	( 
	.a({niO1Ol, niO1Oi, niO1lO, niO1ll, niiill}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nl10ll_o));
	defparam
		nl10ll.sgate_representation = 0,
		nl10ll.width_a = 5,
		nl10ll.width_b = 5,
		nl10ll.width_o = 5;
	oper_add   nli0lO
	( 
	.a({(~ wire_nli0Oi_o[5]), (~ wire_nli0Oi_o[4]), (~ wire_nli0Oi_o[3]), (~ wire_nli0Oi_o[2]), (~ wire_nli0Oi_o[1]), 1'b1}),
	.b({1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli0lO_o));
	defparam
		nli0lO.sgate_representation = 0,
		nli0lO.width_a = 6,
		nli0lO.width_b = 6,
		nli0lO.width_o = 6;
	oper_add   nli0Oi
	( 
	.a({niO00i, nll11il, nll11iO, nll11li, nll11ll, 1'b1}),
	.b({(~ niO1Ol), (~ niO1Oi), (~ niO1lO), (~ niO1ll), (~ niiill), 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli0Oi_o));
	defparam
		nli0Oi.sgate_representation = 0,
		nli0Oi.width_a = 6,
		nli0Oi.width_b = 6,
		nli0Oi.width_o = 6;
	oper_add   nli0Ol
	( 
	.a({niO1Ol, niO1Oi, niO1lO, niO1ll, niiill, 1'b1}),
	.b({(~ niO00i), (~ nll11il), (~ nll11iO), (~ nll11li), (~ nll11ll), 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli0Ol_o));
	defparam
		nli0Ol.sgate_representation = 0,
		nli0Ol.width_a = 6,
		nli0Ol.width_b = 6,
		nli0Ol.width_o = 6;
	oper_add   nli10i
	( 
	.a({1'b0, ralfull[3:2]}),
	.b({{2{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli10i_o));
	defparam
		nli10i.sgate_representation = 0,
		nli10i.width_a = 3,
		nli10i.width_b = 3,
		nli10i.width_o = 3;
	oper_add   nli11i
	( 
	.a({1'b0, (~ ralempty[3]), (~ ralempty[2]), (~ ralempty[1]), (~ ralempty[0]), 1'b1}),
	.b({{5{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli11i_o));
	defparam
		nli11i.sgate_representation = 0,
		nli11i.width_a = 6,
		nli11i.width_b = 6,
		nli11i.width_o = 6;
	oper_add   nlilOl
	( 
	.a({nliilO, nliill, nliili, nliiiO, nli1li, 1'b1}),
	.b({{4{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlilOl_o));
	defparam
		nlilOl.sgate_representation = 0,
		nlilOl.width_a = 6,
		nlilOl.width_b = 6,
		nlilOl.width_o = 6;
	oper_add   nlilOO
	( 
	.a({nliilO, nliill, nliili, nliiiO, nli1li}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlilOO_o));
	defparam
		nlilOO.sgate_representation = 0,
		nlilOO.width_a = 5,
		nlilOO.width_b = 5,
		nlilOO.width_o = 5;
	oper_add   nlOli0i
	( 
	.a({nlO00Ol, nlO00Oi, nlO00lO, nlO00ll, nlO00li}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlOli0i_o));
	defparam
		nlOli0i.sgate_representation = 0,
		nlOli0i.width_a = 5,
		nlOli0i.width_b = 5,
		nlOli0i.width_o = 5;
	oper_decoder   n1010O
	( 
	.i({wire_n1il0O_dataout, wire_n1il0l_dataout, wire_n1il0i_dataout, wire_n1il1O_dataout, wire_n1il1l_dataout}),
	.o(wire_n1010O_o));
	defparam
		n1010O.width_i = 5,
		n1010O.width_o = 32;
	oper_decoder   n101il
	( 
	.i({wire_n1il0O_dataout, wire_n1il0i_dataout, wire_n1il1O_dataout}),
	.o(wire_n101il_o));
	defparam
		n101il.width_i = 3,
		n101il.width_o = 8;
	oper_decoder   n101ll
	( 
	.i({wire_n1il0O_dataout, wire_n1il0l_dataout, wire_n1il0i_dataout, wire_n1il1O_dataout}),
	.o(wire_n101ll_o));
	defparam
		n101ll.width_i = 4,
		n101ll.width_o = 16;
	oper_decoder   n101lO
	( 
	.i({wire_n1il0O_dataout, wire_n1il0l_dataout, wire_n1il0i_dataout}),
	.o(wire_n101lO_o));
	defparam
		n101lO.width_i = 3,
		n101lO.width_o = 8;
	oper_decoder   nilOil
	( 
	.i({ni0OOl, ni0OOi, ni0OlO, ni0Oll}),
	.o(wire_nilOil_o));
	defparam
		nilOil.width_i = 4,
		nilOil.width_o = 16;
	oper_decoder   nilOli
	( 
	.i({ni0OOl, ni0OlO, ni0Oll, ni0Oli}),
	.o(wire_nilOli_o));
	defparam
		nilOli.width_i = 4,
		nilOli.width_o = 16;
	oper_decoder   nilOOl
	( 
	.i({ni0OOl, ni0OOi, ni0OlO, ni0Oll, ni0Oli}),
	.o(wire_nilOOl_o));
	defparam
		nilOOl.width_i = 5,
		nilOOl.width_o = 32;
	oper_decoder   nl1O0i
	( 
	.i({wire_nli0ll_dataout, wire_nli0iO_dataout, wire_nli0il_dataout}),
	.o(wire_nl1O0i_o));
	defparam
		nl1O0i.width_i = 3,
		nl1O0i.width_o = 8;
	oper_decoder   nl1O1l
	( 
	.i({wire_nli0ll_dataout, wire_nli0li_dataout, wire_nli0iO_dataout, wire_nli0il_dataout, wire_nli0ii_dataout}),
	.o(wire_nl1O1l_o));
	defparam
		nl1O1l.width_i = 5,
		nl1O1l.width_o = 32;
	oper_decoder   nl1Oii
	( 
	.i({wire_nli0ll_dataout, wire_nli0li_dataout, wire_nli0iO_dataout, wire_nli0il_dataout}),
	.o(wire_nl1Oii_o));
	defparam
		nl1Oii.width_i = 4,
		nl1Oii.width_o = 16;
	oper_decoder   nl1Oil
	( 
	.i({wire_nli0ll_dataout, wire_nli0li_dataout, wire_nli0iO_dataout}),
	.o(wire_nl1Oil_o));
	defparam
		nl1Oil.width_i = 3,
		nl1Oil.width_o = 8;
	oper_decoder   nlOl0ii
	( 
	.i({nlO00Ol, nlO00Oi, nlO00lO, nlO00ll}),
	.o(wire_nlOl0ii_o));
	defparam
		nlOl0ii.width_i = 4,
		nlOl0ii.width_o = 16;
	oper_decoder   nlOl0iO
	( 
	.i({nlO00Ol, nlO00lO, nlO00ll, nlO00li}),
	.o(wire_nlOl0iO_o));
	defparam
		nlOl0iO.width_i = 4,
		nlOl0iO.width_o = 16;
	oper_decoder   nlOl0Oi
	( 
	.i({nlO00Ol, nlO00Oi, nlO00lO, nlO00ll, nlO00li}),
	.o(wire_nlOl0Oi_o));
	defparam
		nlOl0Oi.width_i = 5,
		nlOl0Oi.width_o = 32;
	oper_less_than   n11l0l
	( 
	.a({n1O0lO, n1O0ll, n1O0li}),
	.b({1'b1, 1'b0, 1'b1}),
	.cin(1'b0),
	.o(wire_n11l0l_o));
	defparam
		n11l0l.sgate_representation = 0,
		n11l0l.width_a = 3,
		n11l0l.width_b = 3;
	oper_less_than   n11lil
	( 
	.a({3{1'b0}}),
	.b({n1O0lO, n1O0ll, n1O0li}),
	.cin(1'b0),
	.o(wire_n11lil_o));
	defparam
		n11lil.sgate_representation = 0,
		n11lil.width_a = 3,
		n11lil.width_b = 3;
	oper_less_than   n11O0i
	( 
	.a({1'b0, 1'b1, 1'b0, {2{1'b1}}}),
	.b({n1001i, nlilO0O, nlilOii, nlilOil, nlilOiO}),
	.cin(1'b1),
	.o(wire_n11O0i_o));
	defparam
		n11O0i.sgate_representation = 0,
		n11O0i.width_a = 5,
		n11O0i.width_b = 5;
	oper_less_than   n1i0li
	( 
	.a({n1ii0i, n1ii1O, n1ii1l, n1ii1i, n1i1li}),
	.b({wire_n1i0ll_o[5:1]}),
	.cin(1'b0),
	.o(wire_n1i0li_o));
	defparam
		n1i0li.sgate_representation = 0,
		n1i0li.width_a = 5,
		n1i0li.width_b = 5;
	oper_less_than   n1i0Oi
	( 
	.a({wire_n1i0Ol_o[2:0], ralfull[1:0]}),
	.b({n1ii0i, n1ii1O, n1ii1l, n1ii1i, n1i1li}),
	.cin(1'b0),
	.o(wire_n1i0Oi_o));
	defparam
		n1i0Oi.sgate_representation = 0,
		n1i0Oi.width_a = 5,
		n1i0Oi.width_b = 5;
	oper_less_than   n1i0OO
	( 
	.a({5{1'b0}}),
	.b({nlOll1l, nliO1il, nliO1iO, nliO1li, nliO1ll}),
	.cin(1'b0),
	.o(wire_n1i0OO_o));
	defparam
		n1i0OO.sgate_representation = 0,
		n1i0OO.width_a = 5,
		n1i0OO.width_b = 5;
	oper_less_than   n1illi
	( 
	.a({nlOll1l, nliO1il, nliO1iO, nliO1li, nliO1ll}),
	.b({nlOlilO, nlOlill, nlOlili, nlOliiO, nlO0Oli}),
	.cin(1'b1),
	.o(wire_n1illi_o));
	defparam
		n1illi.sgate_representation = 0,
		n1illi.width_a = 5,
		n1illi.width_b = 5;
	oper_less_than   n1iOOO
	( 
	.a({1'b0, {2{1'b1}}, 1'b0, 1'b1}),
	.b({wire_n1il0O_dataout, wire_n1il0l_dataout, wire_n1il0i_dataout, wire_n1il1O_dataout, wire_n1il1l_dataout}),
	.cin(1'b0),
	.o(wire_n1iOOO_o));
	defparam
		n1iOOO.sgate_representation = 0,
		n1iOOO.width_a = 5,
		n1iOOO.width_b = 5;
	oper_less_than   n1l0ll
	( 
	.a({n1ii0i, n1ii1O, n1ii1l, n1ii1i, n1i1li}),
	.b({{2{1'b0}}, 1'b1, 1'b0, 1'b1}),
	.cin(1'b0),
	.o(wire_n1l0ll_o));
	defparam
		n1l0ll.sgate_representation = 0,
		n1l0ll.width_a = 5,
		n1l0ll.width_b = 5;
	oper_less_than   n1O00i
	( 
	.a({1'b0, {2{1'b1}}, 1'b0, 1'b1}),
	.b({n1ii0i, n1ii1O, n1ii1l, n1ii1i, n1i1li}),
	.cin(1'b0),
	.o(wire_n1O00i_o));
	defparam
		n1O00i.sgate_representation = 0,
		n1O00i.width_a = 5,
		n1O00i.width_b = 5;
	oper_less_than   n1O00l
	( 
	.a({n1ii0i, n1ii1O, n1ii1l, n1ii1i, n1i1li}),
	.b({1'b0, 1'b1, 1'b0, {2{1'b1}}}),
	.cin(1'b0),
	.o(wire_n1O00l_o));
	defparam
		n1O00l.sgate_representation = 0,
		n1O00l.width_a = 5,
		n1O00l.width_b = 5;
	oper_less_than   nl0OOO
	( 
	.a({nli1iO, nli1il, nli1ii, nli10O, nl0lOO}),
	.b({wire_nli11i_o[5:1]}),
	.cin(1'b0),
	.o(wire_nl0OOO_o));
	defparam
		nl0OOO.sgate_representation = 0,
		nl0OOO.width_a = 5,
		nl0OOO.width_b = 5;
	oper_less_than   nl1iOO
	( 
	.a({1'b0, 1'b1, 1'b0, {2{1'b1}}}),
	.b({nl1OlO, nliOO0l, nliOO0O, nliOOii, nliOOil}),
	.cin(1'b1),
	.o(wire_nl1iOO_o));
	defparam
		nl1iOO.sgate_representation = 0,
		nl1iOO.width_a = 5,
		nl1iOO.width_b = 5;
	oper_less_than   nli0OO
	( 
	.a({niO00i, nll11il, nll11iO, nll11li, nll11ll}),
	.b({niO1Ol, niO1Oi, niO1lO, niO1ll, niiill}),
	.cin(1'b1),
	.o(wire_nli0OO_o));
	defparam
		nli0OO.sgate_representation = 0,
		nli0OO.width_a = 5,
		nli0OO.width_b = 5;
	oper_less_than   nli10l
	( 
	.a({5{1'b0}}),
	.b({niO00i, nll11il, nll11iO, nll11li, nll11ll}),
	.cin(1'b0),
	.o(wire_nli10l_o));
	defparam
		nli10l.sgate_representation = 0,
		nli10l.width_a = 5,
		nli10l.width_b = 5;
	oper_less_than   nli11O
	( 
	.a({wire_nli10i_o[2:0], ralfull[1:0]}),
	.b({nli1iO, nli1il, nli1ii, nli10O, nl0lOO}),
	.cin(1'b0),
	.o(wire_nli11O_o));
	defparam
		nli11O.sgate_representation = 0,
		nli11O.width_a = 5,
		nli11O.width_b = 5;
	oper_less_than   nlii0l
	( 
	.a({1'b0, {2{1'b1}}, 1'b0, 1'b1}),
	.b({wire_nli0ll_dataout, wire_nli0li_dataout, wire_nli0iO_dataout, wire_nli0il_dataout, wire_nli0ii_dataout}),
	.cin(1'b0),
	.o(wire_nlii0l_o));
	defparam
		nlii0l.sgate_representation = 0,
		nlii0l.width_a = 5,
		nlii0l.width_b = 5;
	oper_less_than   nliiil
	( 
	.a({nli1iO, nli1il, nli1ii, nli10O, nl0lOO}),
	.b({{2{1'b0}}, 1'b1, 1'b0, 1'b1}),
	.cin(1'b0),
	.o(wire_nliiil_o));
	defparam
		nliiil.sgate_representation = 0,
		nliiil.width_a = 5,
		nliiil.width_b = 5;
	oper_less_than   nliOOO
	( 
	.a({1'b0, {2{1'b1}}, 1'b0, 1'b1}),
	.b({nli1iO, nli1il, nli1ii, nli10O, nl0lOO}),
	.cin(1'b0),
	.o(wire_nliOOO_o));
	defparam
		nliOOO.sgate_representation = 0,
		nliOOO.width_a = 5,
		nliOOO.width_b = 5;
	oper_less_than   nll11i
	( 
	.a({nli1iO, nli1il, nli1ii, nli10O, nl0lOO}),
	.b({1'b0, 1'b1, 1'b0, {2{1'b1}}}),
	.cin(1'b0),
	.o(wire_nll11i_o));
	defparam
		nll11i.sgate_representation = 0,
		nll11i.width_a = 5,
		nll11i.width_b = 5;
	oper_mux   n000iO
	( 
	.data({{3{rclkcmpsq1n[0]}}, rclkcmpsq1n[10], rclkcmpsq1p[10], rclkcmpsq1n[10], rclkcmpsq1p[0], rclkcmpsq1n[0]}),
	.o(wire_n000iO_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n000iO.width_data = 8,
		n000iO.width_sel = 3;
	oper_mux   n000li
	( 
	.data({{3{rclkcmpsq1n[1]}}, rclkcmpsq1n[11], rclkcmpsq1p[11], rclkcmpsq1n[11], rclkcmpsq1p[1], rclkcmpsq1n[1]}),
	.o(wire_n000li_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n000li.width_data = 8,
		n000li.width_sel = 3;
	oper_mux   n000ll
	( 
	.data({{3{rclkcmpsq1n[2]}}, rclkcmpsq1n[12], rclkcmpsq1p[12], rclkcmpsq1n[12], rclkcmpsq1p[2], rclkcmpsq1n[2]}),
	.o(wire_n000ll_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n000ll.width_data = 8,
		n000ll.width_sel = 3;
	oper_mux   n000lO
	( 
	.data({{3{rclkcmpsq1n[3]}}, rclkcmpsq1n[13], rclkcmpsq1p[13], rclkcmpsq1n[13], rclkcmpsq1p[3], rclkcmpsq1n[3]}),
	.o(wire_n000lO_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n000lO.width_data = 8,
		n000lO.width_sel = 3;
	oper_mux   n000Oi
	( 
	.data({{3{rclkcmpsq1n[4]}}, rclkcmpsq1n[14], rclkcmpsq1p[14], rclkcmpsq1n[14], rclkcmpsq1p[4], rclkcmpsq1n[4]}),
	.o(wire_n000Oi_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n000Oi.width_data = 8,
		n000Oi.width_sel = 3;
	oper_mux   n000Ol
	( 
	.data({{3{rclkcmpsq1n[5]}}, rclkcmpsq1n[15], rclkcmpsq1p[15], rclkcmpsq1n[15], rclkcmpsq1p[5], rclkcmpsq1n[5]}),
	.o(wire_n000Ol_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n000Ol.width_data = 8,
		n000Ol.width_sel = 3;
	oper_mux   n000OO
	( 
	.data({{3{rclkcmpsq1n[6]}}, rclkcmpsq1n[16], rclkcmpsq1p[16], rclkcmpsq1n[16], rclkcmpsq1p[6], rclkcmpsq1n[6]}),
	.o(wire_n000OO_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n000OO.width_data = 8,
		n000OO.width_sel = 3;
	oper_mux   n00i1i
	( 
	.data({{3{rclkcmpsq1n[7]}}, rclkcmpsq1n[17], rclkcmpsq1p[17], rclkcmpsq1n[17], rclkcmpsq1p[7], rclkcmpsq1n[7]}),
	.o(wire_n00i1i_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n00i1i.width_data = 8,
		n00i1i.width_sel = 3;
	oper_mux   n00i1l
	( 
	.data({{3{rclkcmpsq1n[8]}}, rclkcmpsq1n[18], rclkcmpsq1p[18], rclkcmpsq1n[18], rclkcmpsq1p[8], rclkcmpsq1n[8]}),
	.o(wire_n00i1l_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n00i1l.width_data = 8,
		n00i1l.width_sel = 3;
	oper_mux   n00i1O
	( 
	.data({{3{rclkcmpsq1n[9]}}, rclkcmpsq1n[19], rclkcmpsq1p[19], rclkcmpsq1n[19], rclkcmpsq1p[9], rclkcmpsq1n[9]}),
	.o(wire_n00i1O_o),
	.sel({rskpsetbased, rclkcmpsqmd, rclkcmppos}));
	defparam
		n00i1O.width_data = 8,
		n00i1O.width_sel = 3;
	oper_mux   nlOiOi
	( 
	.data({wire_nlOlii_dataout, ((nll1lOi32 ^ nll1lOi31) & wire_nlOl0i_dataout), {2{nlOO1l}}}),
	.o(wire_nlOiOi_o),
	.sel({nlOlOO, nlOilO}));
	defparam
		nlOiOi.width_data = 4,
		nlOiOi.width_sel = 2;
	oper_mux   nlOiOl
	( 
	.data({wire_nlOlil_dataout, wire_nlOl1O_dataout, ((nll1lOl30 ^ nll1lOl29) & nlOill), ((nll1lOO28 ^ nll1lOO27) & nlOill)}),
	.o(wire_nlOiOl_o),
	.sel({nlOlOO, nlOilO}));
	defparam
		nlOiOl.width_data = 4,
		nlOiOl.width_sel = 2;
	oper_mux   nlOiOO
	( 
	.data({wire_nlOliO_dataout, wire_nlOl1l_dataout, wire_nli0i_dataout, (wire_nli0l_dataout & wire_nli0i_dataout)}),
	.o(wire_nlOiOO_o),
	.sel({((nll1O1i26 ^ nll1O1i25) & nlOlOO), nlOilO}));
	defparam
		nlOiOO.width_data = 4,
		nlOiOO.width_sel = 2;
	oper_mux   nlOl1i
	( 
	.data({{2{wire_nli0i_dataout}}, wire_nlOlOi_dataout, 1'b0}),
	.o(wire_nlOl1i_o),
	.sel({nlOlOO, nlOilO}));
	defparam
		nlOl1i.width_data = 4,
		nlOl1i.width_sel = 2;
	arriagx_hssi_ram20x16_syn   nlOiiO
	( 
	.clk(clk_1),
	.data_in({wire_nl01l_dataout, wire_nl01i_dataout, wire_nl1OO_dataout, wire_nl1Ol_dataout, wire_nl1Oi_dataout, wire_nl1lO_dataout, wire_nl1ll_dataout, wire_nl1li_dataout, wire_nl1iO_dataout, wire_nl1il_dataout, wire_nl1ii_dataout, wire_nl10O_dataout, wire_nl10l_dataout, wire_nl10i_dataout, wire_nl11O_dataout, wire_nl11l_dataout}),
	.data_out1(wire_nlOiiO_data_out1),
	.data_out2(wire_nlOiiO_data_out2),
	.fifo_re1({wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout, wire_n1li_dataout, wire_n1iO_dataout, wire_n1il_dataout, wire_n1ii_dataout, wire_n10O_dataout, wire_n10l_dataout, wire_n10i_dataout, wire_n11O_dataout, wire_n11l_dataout, wire_n11i_dataout}),
	.fifo_re2({wire_nlOOO_dataout, wire_nlOOl_dataout, wire_nlOOi_dataout, wire_nlOlO_dataout, wire_nlOll_dataout, wire_nlOli_dataout, wire_nlOiO_dataout, wire_nlOil_dataout, wire_nlOii_dataout, wire_nlO0O_dataout, wire_nlO0l_dataout, wire_nlO0i_dataout, wire_nlO1O_dataout, wire_nlO1l_dataout, wire_nlO1i_dataout, wire_nllOO_dataout, wire_nllOl_dataout, wire_nllOi_dataout, wire_nlllO_dataout, wire_nllll_dataout}),
	.fifo_wr({wire_nllli_dataout, wire_nlliO_dataout, wire_nllil_dataout, wire_nllii_dataout, wire_nll0O_dataout, wire_nll0l_dataout, wire_nll0i_dataout, wire_nll1O_dataout, wire_nll1l_dataout, wire_nll1i_dataout, wire_nliOO_dataout, wire_nliOl_dataout, wire_nliOi_dataout, wire_nlilO_dataout, wire_nlill_dataout, wire_nlili_dataout, wire_nliiO_dataout, wire_nliil_dataout, wire_nliii_dataout, wire_nli0O_dataout}),
	.rst_l((~ wire_n1l_dataout)));
	defparam
		nlOiiO.ram_width = 16,
		nlOiiO.read_access_time = 0,
		nlOiiO.write_access_time = 0;
	arriagx_hssi_ram20x16_syn   nlOili
	( 
	.clk(clk_1),
	.data_in({wire_nli1O_dataout, wire_nli1l_dataout, wire_nli1i_dataout, wire_nl0OO_dataout, wire_nl0Ol_dataout, wire_nl0Oi_dataout, wire_nl0lO_dataout, wire_nl0ll_dataout, wire_nl0li_dataout, wire_nl0iO_dataout, wire_nl0il_dataout, wire_nl0ii_dataout, wire_nl00O_dataout, wire_nl00l_dataout, wire_nl00i_dataout, wire_nl01O_dataout}),
	.data_out1(wire_nlOili_data_out1),
	.data_out2(wire_nlOili_data_out2),
	.fifo_re1({wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout, wire_n1li_dataout, wire_n1iO_dataout, wire_n1il_dataout, wire_n1ii_dataout, wire_n10O_dataout, wire_n10l_dataout, wire_n10i_dataout, wire_n11O_dataout, wire_n11l_dataout, wire_n11i_dataout}),
	.fifo_re2({wire_nlOOO_dataout, wire_nlOOl_dataout, wire_nlOOi_dataout, wire_nlOlO_dataout, wire_nlOll_dataout, wire_nlOli_dataout, wire_nlOiO_dataout, wire_nlOil_dataout, wire_nlOii_dataout, wire_nlO0O_dataout, wire_nlO0l_dataout, wire_nlO0i_dataout, wire_nlO1O_dataout, wire_nlO1l_dataout, wire_nlO1i_dataout, wire_nllOO_dataout, wire_nllOl_dataout, wire_nllOi_dataout, wire_nlllO_dataout, wire_nllll_dataout}),
	.fifo_wr({wire_nllli_dataout, wire_nlliO_dataout, wire_nllil_dataout, wire_nllii_dataout, wire_nll0O_dataout, wire_nll0l_dataout, wire_nll0i_dataout, wire_nll1O_dataout, wire_nll1l_dataout, wire_nll1i_dataout, wire_nliOO_dataout, wire_nliOl_dataout, wire_nliOi_dataout, wire_nlilO_dataout, wire_nlill_dataout, wire_nlili_dataout, wire_nliiO_dataout, wire_nliil_dataout, wire_nliii_dataout, wire_nli0O_dataout}),
	.rst_l((~ wire_n1l_dataout)));
	defparam
		nlOili.ram_width = 16,
		nlOili.read_access_time = 0,
		nlOili.write_access_time = 0;
	assign
		align_status_sync = n10i0O,
		comp_curr_st = {nlOlOO, nlOilO},
		cudi = {wire_nlll_dataout, wire_nlli_dataout, wire_nliO_dataout, wire_nlil_dataout, wire_nlii_dataout, wire_nl0O_dataout, wire_nl0l_dataout, wire_nl0i_dataout, wire_nl1O_dataout, wire_nl1l_dataout, wire_nl1i_dataout, wire_niOO_dataout, wire_niOl_dataout, wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout},
		cudi_valid = wire_nilll_dataout,
		disable_fifo_rd = nll1O0l,
		disable_fifo_wr = nll1O0i,
		fifo_cnt = {wire_n1i_dataout, wire_nlOO_dataout, wire_nlOl_dataout, wire_nlOi_dataout, wire_nllO_dataout},
		fifo_rd_out_comp = n10ilO,
		nlill0i = (nlOll1i ^ nlOliOl),
		nlill0O = (rgenericfifo & (~ n100ii)),
		nlill1O = (n101OO ^ n101Oi),
		nlillii = (n100ii | ((~ rgenericfifo) & (~ wire_n110ll_dataout))),
		nlillil = ((((wire_nlOl0ii_o[8] | wire_nlOl0ii_o[6]) | wire_nlOl0ii_o[4]) | wire_nlOl0ii_o[2]) | wire_nlOl0ii_o[0]),
		nlilliO = (((((((wire_nlOl0Oi_o[10] | wire_nlOl0Oi_o[9]) | wire_nlOl0Oi_o[8]) | wire_nlOl0Oi_o[7]) | wire_nlOl0Oi_o[6]) | wire_nlOl0Oi_o[5]) | wire_nlOl0Oi_o[4]) | wire_nlOl0Oi_o[3]),
		nlillli = (((((((((wire_nlOl0Oi_o[16] | wire_nlOl0Oi_o[15]) | wire_nlOl0Oi_o[14]) | wire_nlOl0Oi_o[13]) | wire_nlOl0Oi_o[12]) | wire_nlOl0Oi_o[11]) | wire_nlOl0Oi_o[10]) | wire_nlOl0Oi_o[9]) | wire_nlOl0Oi_o[8]) | wire_nlOl0Oi_o[7]),
		nlillll = ((((nlO00Ol & (~ nlO00Oi)) & (~ nlO00lO)) & nlO00ll) & nlO00li),
		nlilllO = (((~ rgenericfifo) & (wire_n10lOi_dataout & (~ wire_n110ll_dataout))) | nlilOlO),
		nlillOi = (((((~ nlOlilO) & (~ nlOlill)) & (~ nlOlili)) & (~ nlOliiO)) & (~ nlO0Oli)),
		nlillOl = ((~ rgenericfifo) & nliO01O),
		nlillOO = ((((nlOlilO & (~ nlOlill)) & (~ nlOlili)) & nlOliiO) & nlO0Oli),
		nlilO0i = (((~ rclkcmpsqmd) & (~ nliOiiO)) & (rtruebac2bac | ((~ rtruebac2bac) & (~ n1O0il)))),
		nlilO0l = (((((~ n1001i) & nlilO0O) & (~ nlilOii)) & nlilOil) & (~ nlilOiO)),
		nlilO0O = ((~ n1001i) & n101OO),
		nlilO1i = ((((((((((~ (rclkcmpsq1n[0] ^ nllO10O)) & (~ (rclkcmpsq1n[1] ^ nlllOiO))) & (~ (rclkcmpsq1n[2] ^ nlllOli))) & (~ (rclkcmpsq1n[3] ^ nlllOll))) & (~ (rclkcmpsq1n[4] ^ nlllOlO))) & (~ (rclkcmpsq1n[5] ^ nlllOOi))) & (~ (rclkcmpsq1n[6] ^ nlllOOl))) & (~ (rclkcmpsq1n[7] ^ nlllOOO))) & (~ (rclkcmpsq1n[8] ^ nllO11i))) & (~ (rclkcmpsq1n[9] ^ nllO11l))),
		nlilO1l = ((((((((((~ (rclkcmpsq1p[0] ^ nllO10O)) & (~ (rclkcmpsq1p[1] ^ nlllOiO))) & (~ (rclkcmpsq1p[2] ^ nlllOli))) & (~ (rclkcmpsq1p[3] ^ nlllOll))) & (~ (rclkcmpsq1p[4] ^ nlllOlO))) & (~ (rclkcmpsq1p[5] ^ nlllOOi))) & (~ (rclkcmpsq1p[6] ^ nlllOOl))) & (~ (rclkcmpsq1p[7] ^ nlllOOO))) & (~ (rclkcmpsq1p[8] ^ nllO11i))) & (~ (rclkcmpsq1p[9] ^ nllO11l))),
		nlilO1O = (rskpsetbased & n10O0l),
		nlilOii = ((~ n1001i) & (n101OO ^ n101Ol)),
		nlilOil = (n1001i ^ (n101Ol ^ nlill1O)),
		nlilOiO = (n1001i ^ (nlill1O ^ (n101Ol ^ n11OiO))),
		nlilOli = (((((((((wire_n1010O_o[18] | wire_n1010O_o[17]) | wire_n1010O_o[14]) | wire_n1010O_o[13]) | wire_n1010O_o[10]) | wire_n1010O_o[9]) | wire_n1010O_o[6]) | wire_n1010O_o[5]) | wire_n1010O_o[2]) | wire_n1010O_o[1]),
		nlilOll = ((((wire_n101ll_o[8] | wire_n101ll_o[7]) | wire_n101ll_o[6]) | wire_n101ll_o[5]) | wire_n101ll_o[4]),
		nlilOlO = (rgenericfifo & n100ii),
		nlilOOi = (((((~ n1ii0i) & (~ n1ii1O)) & n1ii1l) & n1ii1i) & n1i1li),
		nlilOOl = (n10O0l | n10O1O),
		nlilOOO = ((((((((~ n1l1ii) & (~ n1l10O)) & (~ n1l10l)) & (~ n1l10i)) & (~ n1l11O)) & (~ n1l11l)) & (~ n1l11i)) & (~ n1ii0l)),
		nliO00i = (nliO0ii & (rclkcmpsqmd & ((nll1OOO | n1l1il) & wire_n1illl_dataout))),
		nliO00l = ((((n1li1i | n1l0OO) | n1l0Ol) | n1l0Oi) | n1l0lO),
		nliO00O = (((~ rgenericfifo) & (~ wire_n1illl_dataout)) | (rgenericfifo & nlOlOOi)),
		nliO01i = (nliO0ii & ((~ rclkcmpsqmd) & (((~ rgenericfifo) & wire_n1illl_dataout) | (rgenericfifo & (~ nlOlOOi))))),
		nliO01l = (nliO0ii & nliO01O),
		nliO01O = (rclkcmpsqmd & wire_n1illl_dataout),
		nliO0ii = ((~ rskpsetbased) | (~ nliO0li)),
		nliO0il = ((~ rgenericfifo) & (~ wire_n01i0i_dataout)),
		nliO0iO = ((rskpsetbased | ((~ rskpsetbased) & (~ wire_n1illl_dataout))) & nliO0li),
		nliO0li = ((~ nliO1lO) & nliO1ii),
		nliO0ll = ((wire_n0000l_dataout & (~ (((~ n1O0lO) & (~ n1O0ll)) & (~ n1O0li)))) & wire_n11l0l_o),
		nliO0lO = (wire_n11l0l_o & nliO0Oi),
		nliO0Oi = (((~ wire_n0000l_dataout) & ((n10ili & ((~ rrx_pipe_enable) & nlilO0i)) & wire_n11lil_o)) & wire_n11l0l_o),
		nliO0Ol = (wire_n0000l_dataout & wire_n001lO_dataout),
		nliO0OO = ((((((((((~ (rclkcmpsq1p[0] ^ wire_n011li_dataout)) & (~ (rclkcmpsq1p[1] ^ wire_n011ll_dataout))) & (~ (rclkcmpsq1p[2] ^ wire_n011lO_dataout))) & (~ (rclkcmpsq1p[3] ^ wire_n011Oi_dataout))) & (~ (rclkcmpsq1p[4] ^ wire_n011Ol_dataout))) & (~ (rclkcmpsq1p[5] ^ wire_n011OO_dataout))) & (~ (rclkcmpsq1p[6] ^ wire_n0101i_dataout))) & (~ (rclkcmpsq1p[7] ^ wire_n0101l_dataout))) & (~ (rclkcmpsq1p[8] ^ wire_n0101O_dataout))) & (~ (rclkcmpsq1p[9] ^ wire_n0100i_dataout))),
		nliO10i = (wire_n1i0iO_dataout | n1i10O),
		nliO10l = (wire_n1i0lO_dataout | n1i1il),
		nliO10O = (wire_n1illl_dataout & nliO1ii),
		nliO11i = (nliO0li | n1i11i),
		nliO11l = ((((n1ii0i & (~ n1ii1O)) & (~ n1ii1l)) & n1ii1i) & n1i1li),
		nliO11O = (((((~ wire_n1il0O_dataout) & (~ wire_n1il0l_dataout)) & (~ wire_n1il0i_dataout)) & (~ wire_n1il1O_dataout)) & (~ wire_n1il1l_dataout)),
		nliO1ii = (nliO11O & nliO11l),
		nliO1il = ((~ nlOll1l) & nlOll1i),
		nliO1iO = ((~ nlOll1l) & (nlOll1i ^ nlOliOO)),
		nliO1li = (nlOll1l ^ (nlOliOO ^ nlill0i)),
		nliO1ll = (nlOll1l ^ (nlill0i ^ (nlOliOO ^ nlOliOi))),
		nliO1lO = (((wire_n1iOOO_o & (nliOi1O & nlOO1l)) & (~ (rskpsetbased & (~ rrx_pipe_enable)))) | (wire_n1iOOO_o & (((rskpsetbased & (rtruebac2bac & (n1OlOl | (n1OlOi | (n1OllO | n1Olll))))) | ((~ rrx_pipe_enable) & (rskpsetbased & ((~ rtruebac2bac) & n1OlOl)))) & nlOO1l))),
		nliO1Oi = ((~ rgenericfifo) & (~ wire_n010ll_dataout)),
		nliO1Ol = (rgenericfifo | wire_n010ll_dataout),
		nliO1OO = (((((~ n1li1i) & (~ n1l0OO)) & (~ n1l0Ol)) & (~ n1l0Oi)) & (~ n1l0lO)),
		nliOi0i = (dskwclksel[0] & nliOi0O),
		nliOi0l = ((~ dskwclksel[0]) & nliOi0O),
		nliOi0O = ((~ is_lane0) & nll010i),
		nliOi1i = ((((((((((~ (rclkcmpsq1n[0] ^ wire_n011li_dataout)) & (~ (rclkcmpsq1n[1] ^ wire_n011ll_dataout))) & (~ (rclkcmpsq1n[2] ^ wire_n011lO_dataout))) & (~ (rclkcmpsq1n[3] ^ wire_n011Oi_dataout))) & (~ (rclkcmpsq1n[4] ^ wire_n011Ol_dataout))) & (~ (rclkcmpsq1n[5] ^ wire_n011OO_dataout))) & (~ (rclkcmpsq1n[6] ^ wire_n0101i_dataout))) & (~ (rclkcmpsq1n[7] ^ wire_n0101l_dataout))) & (~ (rclkcmpsq1n[8] ^ wire_n0101O_dataout))) & (~ (rclkcmpsq1n[9] ^ wire_n0100i_dataout))),
		nliOi1l = (nll1OlO & ((~ rclkcmpsqmd) | n1Olil)),
		nliOi1O = ((~ wire_n010il_dataout) & ((~ wire_n010ii_dataout) & n1OlOO)),
		nliOiii = ((~ rmatchen) | rgenericfifo),
		nliOiil = (((wire_n0000l_dataout & (wire_n001lO_dataout & (rrx_pipe_enable & nliOili))) & (~ nliOiiO)) & n10ili),
		nliOiiO = (wire_n11O0i_o | (n1O0il & nlilO0l)),
		nliOili = (rmatchen | rgenericfifo),
		nliOill = ((((((((((~ (rclkcmpsq1p[0] ^ nllO01O)) & (~ (rclkcmpsq1p[1] ^ nllO00i))) & (~ (rclkcmpsq1p[2] ^ nllO00l))) & (~ (rclkcmpsq1p[3] ^ nllO00O))) & (~ (rclkcmpsq1p[4] ^ nllO0ii))) & (~ (rclkcmpsq1p[5] ^ nllO0il))) & (~ (rclkcmpsq1p[6] ^ nllO0iO))) & (~ (rclkcmpsq1p[7] ^ nllO0li))) & (~ (rclkcmpsq1p[8] ^ nllO0ll))) & (~ (rclkcmpsq1p[9] ^ nllO0lO))),
		nliOilO = ((((((((((~ (rclkcmpsq1n[0] ^ nllO01O)) & (~ (rclkcmpsq1n[1] ^ nllO00i))) & (~ (rclkcmpsq1n[2] ^ nllO00l))) & (~ (rclkcmpsq1n[3] ^ nllO00O))) & (~ (rclkcmpsq1n[4] ^ nllO0ii))) & (~ (rclkcmpsq1n[5] ^ nllO0il))) & (~ (rclkcmpsq1n[6] ^ nllO0iO))) & (~ (rclkcmpsq1n[7] ^ nllO0li))) & (~ (rclkcmpsq1n[8] ^ nllO0ll))) & (~ (rclkcmpsq1n[9] ^ nllO0lO))),
		nliOiOi = ((((((((((~ (rclkcmpsq1n[0] ^ nllO10l)) & (~ (rclkcmpsq1n[1] ^ nllO1ii))) & (~ (rclkcmpsq1n[2] ^ nllO1il))) & (~ (rclkcmpsq1n[3] ^ nllO1iO))) & (~ (rclkcmpsq1n[4] ^ nllO1li))) & (~ (rclkcmpsq1n[5] ^ nllO1ll))) & (~ (rclkcmpsq1n[6] ^ nllO1lO))) & (~ (rclkcmpsq1n[7] ^ nllO1Oi))) & (~ (rclkcmpsq1n[8] ^ nllO1Ol))) & (~ (rclkcmpsq1n[9] ^ nllO1OO))),
		nliOiOl = ((((((((((~ (rclkcmpsq1p[0] ^ nllO10l)) & (~ (rclkcmpsq1p[1] ^ nllO1ii))) & (~ (rclkcmpsq1p[2] ^ nllO1il))) & (~ (rclkcmpsq1p[3] ^ nllO1iO))) & (~ (rclkcmpsq1p[4] ^ nllO1li))) & (~ (rclkcmpsq1p[5] ^ nllO1ll))) & (~ (rclkcmpsq1p[6] ^ nllO1lO))) & (~ (rclkcmpsq1p[7] ^ nllO1Oi))) & (~ (rclkcmpsq1p[8] ^ nllO1Ol))) & (~ (rclkcmpsq1p[9] ^ nllO1OO))),
		nliOiOO = ((((((((((~ (wire_n000iO_o ^ nllO01O)) & (~ (wire_n000li_o ^ nllO00i))) & (~ (wire_n000ll_o ^ nllO00l))) & (~ (wire_n000lO_o ^ nllO00O))) & (~ (wire_n000Oi_o ^ nllO0ii))) & (~ (wire_n000Ol_o ^ nllO0il))) & (~ (wire_n000OO_o ^ nllO0iO))) & (~ (wire_n00i1i_o ^ nllO0li))) & (~ (wire_n00i1l_o ^ nllO0ll))) & (~ (wire_n00i1O_o ^ nllO0lO))),
		nliOl0i = ((((((((((~ (wire_n000iO_o ^ wire_n011li_dataout)) & (~ (wire_n000li_o ^ wire_n011ll_dataout))) & (~ (wire_n000ll_o ^ wire_n011lO_dataout))) & (~ (wire_n000lO_o ^ wire_n011Oi_dataout))) & (~ (wire_n000Oi_o ^ wire_n011Ol_dataout))) & (~ (wire_n000Ol_o ^ wire_n011OO_dataout))) & (~ (wire_n000OO_o ^ wire_n0101i_dataout))) & (~ (wire_n00i1i_o ^ wire_n0101l_dataout))) & (~ (wire_n00i1l_o ^ wire_n0101O_dataout))) & (~ (wire_n00i1O_o ^ wire_n0100i_dataout))),
		nliOl0l = ((((((((((~ (wire_n00i0i_dataout ^ wire_n011li_dataout)) & (~ (wire_n00i0l_dataout ^ wire_n011ll_dataout))) & (~ (wire_n00i0O_dataout ^ wire_n011lO_dataout))) & (~ (wire_n00iii_dataout ^ wire_n011Oi_dataout))) & (~ (wire_n00iil_dataout ^ wire_n011Ol_dataout))) & (~ (wire_n00iiO_dataout ^ wire_n011OO_dataout))) & (~ (wire_n00ili_dataout ^ wire_n0101i_dataout))) & (~ (wire_n00ill_dataout ^ wire_n0101l_dataout))) & (~ (wire_n00ilO_dataout ^ wire_n0101O_dataout))) & (~ (wire_n00iOi_dataout ^ wire_n0100i_dataout))),
		nliOl0O = (rskpsetbased | rclkcmpsqmd),
		nliOl1i = ((((((((((~ (wire_n00i0i_dataout ^ nllO01O)) & (~ (wire_n00i0l_dataout ^ nllO00i))) & (~ (wire_n00i0O_dataout ^ nllO00l))) & (~ (wire_n00iii_dataout ^ nllO00O))) & (~ (wire_n00iil_dataout ^ nllO0ii))) & (~ (wire_n00iiO_dataout ^ nllO0il))) & (~ (wire_n00ili_dataout ^ nllO0iO))) & (~ (wire_n00ill_dataout ^ nllO0li))) & (~ (wire_n00ilO_dataout ^ nllO0ll))) & (~ (wire_n00iOi_dataout ^ nllO0lO))),
		nliOl1l = ((((((((((~ (wire_n000iO_o ^ nllO10l)) & (~ (wire_n000li_o ^ nllO1ii))) & (~ (wire_n000ll_o ^ nllO1il))) & (~ (wire_n000lO_o ^ nllO1iO))) & (~ (wire_n000Oi_o ^ nllO1li))) & (~ (wire_n000Ol_o ^ nllO1ll))) & (~ (wire_n000OO_o ^ nllO1lO))) & (~ (wire_n00i1i_o ^ nllO1Oi))) & (~ (wire_n00i1l_o ^ nllO1Ol))) & (~ (wire_n00i1O_o ^ nllO1OO))),
		nliOl1O = ((((((((((~ (wire_n00i0i_dataout ^ nllO10l)) & (~ (wire_n00i0l_dataout ^ nllO1ii))) & (~ (wire_n00i0O_dataout ^ nllO1il))) & (~ (wire_n00iii_dataout ^ nllO1iO))) & (~ (wire_n00iil_dataout ^ nllO1li))) & (~ (wire_n00iiO_dataout ^ nllO1ll))) & (~ (wire_n00ili_dataout ^ nllO1lO))) & (~ (wire_n00ill_dataout ^ nllO1Oi))) & (~ (wire_n00ilO_dataout ^ nllO1Ol))) & (~ (wire_n00iOi_dataout ^ nllO1OO))),
		nliOlii = (nl1Oll ^ nl1OiO),
		nliOlil = (niO01O ^ niO01i),
		nliOlll = (rgenericfifo & (~ nl011O)),
		nliOllO = (nl011O | ((~ rgenericfifo) & (~ nll10iO))),
		nliOlOi = ((((wire_nilOil_o[8] | wire_nilOil_o[6]) | wire_nilOil_o[4]) | wire_nilOil_o[2]) | wire_nilOil_o[0]),
		nliOlOl = (((((((wire_nilOOl_o[10] | wire_nilOOl_o[9]) | wire_nilOOl_o[8]) | wire_nilOOl_o[7]) | wire_nilOOl_o[6]) | wire_nilOOl_o[5]) | wire_nilOOl_o[4]) | wire_nilOOl_o[3]),
		nliOlOO = (((((((((wire_nilOOl_o[16] | wire_nilOOl_o[15]) | wire_nilOOl_o[14]) | wire_nilOOl_o[13]) | wire_nilOOl_o[12]) | wire_nilOOl_o[11]) | wire_nilOOl_o[10]) | wire_nilOOl_o[9]) | wire_nilOOl_o[8]) | wire_nilOOl_o[7]),
		nliOO0i = (((((~ nl1OlO) & nliOO0l) & (~ nliOO0O)) & nliOOii) & (~ nliOOil)),
		nliOO0l = ((~ nl1OlO) & nl1Oll),
		nliOO0O = ((~ nl1OlO) & (nl1Oll ^ nl1Oli)),
		nliOO1i = ((((ni0OOl & (~ ni0OOi)) & (~ ni0OlO)) & ni0Oll) & ni0Oli),
		nliOO1l = (((~ rgenericfifo) & (nl000O & (~ nll10iO))) | nliOOll),
		nliOO1O = ((((niO1Ol & (~ niO1Oi)) & (~ niO1lO)) & niO1ll) & niiill),
		nliOOii = (nl1OlO ^ (nl1Oli ^ nliOlii)),
		nliOOil = (nl1OlO ^ (nliOlii ^ (nl1Oli ^ nl1l0l))),
		nliOOiO = (((((((((wire_nl1O1l_o[18] | wire_nl1O1l_o[17]) | wire_nl1O1l_o[14]) | wire_nl1O1l_o[13]) | wire_nl1O1l_o[10]) | wire_nl1O1l_o[9]) | wire_nl1O1l_o[6]) | wire_nl1O1l_o[5]) | wire_nl1O1l_o[2]) | wire_nl1O1l_o[1]),
		nliOOli = ((((wire_nl1Oii_o[8] | wire_nl1Oii_o[7]) | wire_nl1Oii_o[6]) | wire_nl1Oii_o[5]) | wire_nl1Oii_o[4]),
		nliOOll = (rgenericfifo & nl011O),
		nliOOlO = (((((~ nli1iO) & (~ nli1il)) & nli1ii) & nli10O) & nl0lOO),
		nliOOOi = (nl0ill | nl0iiO),
		nliOOOl = ((~ rgenericfifo) & (~ wire_nlliiO_dataout)),
		nliOOOO = (nll100l | nl0l0l),
		nll000O = 1'b1,
		nll001i = (((((~ n1ii0i) & n1ii1O) & n1ii1l) & (~ n1ii1i)) & n1i1li),
		nll001l = 1'b0,
		nll00iO = ((wire_n0O_dataout | soft_reset) | (~ (nll001O6 ^ nll001O5))),
		nll010i = (dskwclksel[1] & rmatchen),
		nll011i = ((nll101l & (~ nll100l)) & nll101i),
		nll01iO = (((((~ nli1iO) & nli1il) & (~ nli1ii)) & nli10O) & nl0lOO),
		nll01lO = (((((~ nli1iO) & nli1il) & nli1ii) & (~ nli10O)) & (~ nl0lOO)),
		nll01Oi = (((((~ nli1iO) & nli1il) & nli1ii) & (~ nli10O)) & nl0lOO),
		nll01Ol = (((((~ n1ii0i) & n1ii1O) & (~ n1ii1l)) & n1ii1i) & n1i1li),
		nll01OO = (((((~ n1ii0i) & n1ii1O) & n1ii1l) & (~ n1ii1i)) & (~ n1i1li)),
		nll100i = ((~ rgenericfifo) & (~ wire_nllili_dataout)),
		nll100l = ((~ nll11lO) & nll11ii),
		nll100O = ((((((((((~ (rclkcmpsq1n[0] ^ wire_nlOili_data_out2[0])) & (~ (rclkcmpsq1n[1] ^ wire_nlOili_data_out2[1]))) & (~ (rclkcmpsq1n[2] ^ wire_nlOili_data_out2[2]))) & (~ (rclkcmpsq1n[3] ^ wire_nlOili_data_out2[3]))) & (~ (rclkcmpsq1n[4] ^ wire_nlOili_data_out2[4]))) & (~ (rclkcmpsq1n[5] ^ wire_nlOili_data_out2[5]))) & (~ (rclkcmpsq1n[6] ^ wire_nlOili_data_out2[6]))) & (~ (rclkcmpsq1n[7] ^ wire_nlOili_data_out2[7]))) & (~ (rclkcmpsq1n[8] ^ wire_nlOili_data_out2[8]))) & (~ (rclkcmpsq1n[9] ^ wire_nlOili_data_out2[9]))),
		nll101i = ((((nliilO | nliill) | nliili) | nliiiO) | nli1li),
		nll101l = (((~ rgenericfifo) & (~ nll101O)) | (rgenericfifo & niOiOO)),
		nll101O = (nll11lO | nll100l),
		nll10ii = ((((((((((~ (rclkcmpsq1p[0] ^ wire_nlOili_data_out2[0])) & (~ (rclkcmpsq1p[1] ^ wire_nlOili_data_out2[1]))) & (~ (rclkcmpsq1p[2] ^ wire_nlOili_data_out2[2]))) & (~ (rclkcmpsq1p[3] ^ wire_nlOili_data_out2[3]))) & (~ (rclkcmpsq1p[4] ^ wire_nlOili_data_out2[4]))) & (~ (rclkcmpsq1p[5] ^ wire_nlOili_data_out2[5]))) & (~ (rclkcmpsq1p[6] ^ wire_nlOili_data_out2[6]))) & (~ (rclkcmpsq1p[7] ^ wire_nlOili_data_out2[7]))) & (~ (rclkcmpsq1p[8] ^ wire_nlOili_data_out2[8]))) & (~ (rclkcmpsq1p[9] ^ wire_nlOili_data_out2[9]))),
		nll10iO = (nl0ill | (nll10l & (nl000i & (~ nll1i1i)))),
		nll10li = ((((((((((~ (rclkcmpsq1n[10] ^ wire_nlOiiO_data_out2[0])) & (~ (rclkcmpsq1n[11] ^ wire_nlOiiO_data_out2[1]))) & (~ (rclkcmpsq1n[12] ^ wire_nlOiiO_data_out2[2]))) & (~ (rclkcmpsq1n[13] ^ wire_nlOiiO_data_out2[3]))) & (~ (rclkcmpsq1n[14] ^ wire_nlOiiO_data_out2[4]))) & (~ (rclkcmpsq1n[15] ^ wire_nlOiiO_data_out2[5]))) & (~ (rclkcmpsq1n[16] ^ wire_nlOiiO_data_out2[6]))) & (~ (rclkcmpsq1n[17] ^ wire_nlOiiO_data_out2[7]))) & (~ (rclkcmpsq1n[18] ^ wire_nlOiiO_data_out2[8]))) & (~ (rclkcmpsq1n[19] ^ wire_nlOiiO_data_out2[9]))),
		nll10ll = ((((((((((~ (rclkcmpsq1p[10] ^ wire_nlOiiO_data_out2[0])) & (~ (rclkcmpsq1p[11] ^ wire_nlOiiO_data_out2[1]))) & (~ (rclkcmpsq1p[12] ^ wire_nlOiiO_data_out2[2]))) & (~ (rclkcmpsq1p[13] ^ wire_nlOiiO_data_out2[3]))) & (~ (rclkcmpsq1p[14] ^ wire_nlOiiO_data_out2[4]))) & (~ (rclkcmpsq1p[15] ^ wire_nlOiiO_data_out2[5]))) & (~ (rclkcmpsq1p[16] ^ wire_nlOiiO_data_out2[6]))) & (~ (rclkcmpsq1p[17] ^ wire_nlOiiO_data_out2[7]))) & (~ (rclkcmpsq1p[18] ^ wire_nlOiiO_data_out2[8]))) & (~ (rclkcmpsq1p[19] ^ wire_nlOiiO_data_out2[9]))),
		nll10lO = ((((((((((~ (rclkcmpsq1n[0] ^ n0Ol0i)) & (~ (rclkcmpsq1n[1] ^ n0OiiO))) & (~ (rclkcmpsq1n[2] ^ n0Oili))) & (~ (rclkcmpsq1n[3] ^ n0Oill))) & (~ (rclkcmpsq1n[4] ^ n0OilO))) & (~ (rclkcmpsq1n[5] ^ n0OiOi))) & (~ (rclkcmpsq1n[6] ^ n0OiOl))) & (~ (rclkcmpsq1n[7] ^ n0OiOO))) & (~ (rclkcmpsq1n[8] ^ n0Ol1i))) & (~ (rclkcmpsq1n[9] ^ n0Ol1l))),
		nll10Oi = ((((((((((~ (rclkcmpsq1p[0] ^ n0Ol0i)) & (~ (rclkcmpsq1p[1] ^ n0OiiO))) & (~ (rclkcmpsq1p[2] ^ n0Oili))) & (~ (rclkcmpsq1p[3] ^ n0Oill))) & (~ (rclkcmpsq1p[4] ^ n0OilO))) & (~ (rclkcmpsq1p[5] ^ n0OiOi))) & (~ (rclkcmpsq1p[6] ^ n0OiOl))) & (~ (rclkcmpsq1p[7] ^ n0OiOO))) & (~ (rclkcmpsq1p[8] ^ n0Ol1i))) & (~ (rclkcmpsq1p[9] ^ n0Ol1l))),
		nll10Ol = ((((((((((~ (rclkcmpsq1n[10] ^ n0Ol1O)) & (~ (rclkcmpsq1n[11] ^ n0Ol0l))) & (~ (rclkcmpsq1n[12] ^ n0Ol0O))) & (~ (rclkcmpsq1n[13] ^ n0Olii))) & (~ (rclkcmpsq1n[14] ^ n0Olil))) & (~ (rclkcmpsq1n[15] ^ n0OliO))) & (~ (rclkcmpsq1n[16] ^ n0Olli))) & (~ (rclkcmpsq1n[17] ^ n0Olll))) & (~ (rclkcmpsq1n[18] ^ n0OllO))) & (~ (rclkcmpsq1n[19] ^ n0OlOi))),
		nll10OO = ((((((((((~ (rclkcmpsq1p[10] ^ n0Ol1O)) & (~ (rclkcmpsq1p[11] ^ n0Ol0l))) & (~ (rclkcmpsq1p[12] ^ n0Ol0O))) & (~ (rclkcmpsq1p[13] ^ n0Olii))) & (~ (rclkcmpsq1p[14] ^ n0Olil))) & (~ (rclkcmpsq1p[15] ^ n0OliO))) & (~ (rclkcmpsq1p[16] ^ n0Olli))) & (~ (rclkcmpsq1p[17] ^ n0Olll))) & (~ (rclkcmpsq1p[18] ^ n0OllO))) & (~ (rclkcmpsq1p[19] ^ n0OlOi))),
		nll110i = (wire_nl0OOl_dataout | nl0lli),
		nll110l = (wire_nli11l_dataout | nl0lOi),
		nll110O = (nll101O & nll11ii),
		nll111i = ((((nli1iO & (~ nli1il)) & (~ nli1ii)) & nli10O) & nl0lOO),
		nll111l = (((((~ wire_nli0ll_dataout) & (~ wire_nli0li_dataout)) & (~ wire_nli0iO_dataout)) & (~ wire_nli0il_dataout)) & (~ wire_nli0ii_dataout)),
		nll11ii = (nll111l & nll111i),
		nll11il = ((~ niO00i) & niO01O),
		nll11iO = ((~ niO00i) & (niO01O ^ niO01l)),
		nll11li = (niO00i ^ (niO01l ^ nliOlil)),
		nll11ll = (niO00i ^ (nliOlil ^ (niO01l ^ niO1OO))),
		nll11lO = (wire_nlii0l_o & ((nll00i | nll1OO) & nlOO1l)),
		nll11Oi = (rgenericfifo | wire_nlliiO_dataout),
		nll11Ol = (((((~ nliilO) & (~ nliill)) & (~ nliili)) & (~ nliiiO)) & (~ nli1li)),
		nll11OO = ((((~ rgenericfifo) & nll101O) | (rgenericfifo & (~ niOiOO))) & (~ nll100l)),
		nll1i0i = ((((((((((~ (sudi[0] ^ rclkcmpsq1n[0])) & (~ (sudi[1] ^ rclkcmpsq1n[1]))) & (~ (sudi[2] ^ rclkcmpsq1n[2]))) & (~ (sudi[3] ^ rclkcmpsq1n[3]))) & (~ (sudi[4] ^ rclkcmpsq1n[4]))) & (~ (sudi[5] ^ rclkcmpsq1n[5]))) & (~ (sudi[6] ^ rclkcmpsq1n[6]))) & (~ (sudi[7] ^ rclkcmpsq1n[7]))) & (~ (sudi[8] ^ rclkcmpsq1n[8]))) & (~ (sudi[9] ^ rclkcmpsq1n[9]))),
		nll1i0l = ((((((((((~ (sudi[0] ^ rclkcmpsq1p[0])) & (~ (sudi[1] ^ rclkcmpsq1p[1]))) & (~ (sudi[2] ^ rclkcmpsq1p[2]))) & (~ (sudi[3] ^ rclkcmpsq1p[3]))) & (~ (sudi[4] ^ rclkcmpsq1p[4]))) & (~ (sudi[5] ^ rclkcmpsq1p[5]))) & (~ (sudi[6] ^ rclkcmpsq1p[6]))) & (~ (sudi[7] ^ rclkcmpsq1p[7]))) & (~ (sudi[8] ^ rclkcmpsq1p[8]))) & (~ (sudi[9] ^ rclkcmpsq1p[9]))),
		nll1i1i = (wire_nl1iOO_o | (nll11l & nliOO0i)),
		nll1iil = ((((((((((~ (sudi[14] ^ rclkcmpsq1n[0])) & (~ (sudi[15] ^ rclkcmpsq1n[1]))) & (~ (sudi[16] ^ rclkcmpsq1n[2]))) & (~ (sudi[17] ^ rclkcmpsq1n[3]))) & (~ (sudi[18] ^ rclkcmpsq1n[4]))) & (~ (sudi[19] ^ rclkcmpsq1n[5]))) & (~ (sudi[20] ^ rclkcmpsq1n[6]))) & (~ (sudi[21] ^ rclkcmpsq1n[7]))) & (~ (sudi[22] ^ rclkcmpsq1n[8]))) & (~ (sudi[23] ^ rclkcmpsq1n[9]))),
		nll1iiO = ((((((((((~ (sudi[14] ^ rclkcmpsq1p[0])) & (~ (sudi[15] ^ rclkcmpsq1p[1]))) & (~ (sudi[16] ^ rclkcmpsq1p[2]))) & (~ (sudi[17] ^ rclkcmpsq1p[3]))) & (~ (sudi[18] ^ rclkcmpsq1p[4]))) & (~ (sudi[19] ^ rclkcmpsq1p[5]))) & (~ (sudi[20] ^ rclkcmpsq1p[6]))) & (~ (sudi[21] ^ rclkcmpsq1p[7]))) & (~ (sudi[22] ^ rclkcmpsq1p[8]))) & (~ (sudi[23] ^ rclkcmpsq1p[9]))),
		nll1l0i = (rmatchen | rgenericfifo),
		nll1l0l = (nll1lii | nll1l0O),
		nll1l0O = ((((((((((~ (sudi[14] ^ rclkcmpsq1n[10])) & (~ (sudi[15] ^ rclkcmpsq1n[11]))) & (~ (sudi[16] ^ rclkcmpsq1n[12]))) & (~ (sudi[17] ^ rclkcmpsq1n[13]))) & (~ (sudi[18] ^ rclkcmpsq1n[14]))) & (~ (sudi[19] ^ rclkcmpsq1n[15]))) & (~ (sudi[20] ^ rclkcmpsq1n[16]))) & (~ (sudi[21] ^ rclkcmpsq1n[17]))) & (~ (sudi[22] ^ rclkcmpsq1n[18]))) & (~ (sudi[23] ^ rclkcmpsq1n[19]))),
		nll1l1i = (((~ rmatchen) | rgenericfifo) | (~ (nll1l1l36 ^ nll1l1l35))),
		nll1lii = ((((((((((~ (sudi[14] ^ rclkcmpsq1p[10])) & (~ (sudi[15] ^ rclkcmpsq1p[11]))) & (~ (sudi[16] ^ rclkcmpsq1p[12]))) & (~ (sudi[17] ^ rclkcmpsq1p[13]))) & (~ (sudi[18] ^ rclkcmpsq1p[14]))) & (~ (sudi[19] ^ rclkcmpsq1p[15]))) & (~ (sudi[20] ^ rclkcmpsq1p[16]))) & (~ (sudi[21] ^ rclkcmpsq1p[17]))) & (~ (sudi[22] ^ rclkcmpsq1p[18]))) & (~ (sudi[23] ^ rclkcmpsq1p[19]))),
		nll1lil = ((nll1llO | nll1lll) | (~ (nll1liO34 ^ nll1liO33))),
		nll1lll = ((((((((((~ (sudi[0] ^ rclkcmpsq1n[10])) & (~ (sudi[1] ^ rclkcmpsq1n[11]))) & (~ (sudi[2] ^ rclkcmpsq1n[12]))) & (~ (sudi[3] ^ rclkcmpsq1n[13]))) & (~ (sudi[4] ^ rclkcmpsq1n[14]))) & (~ (sudi[5] ^ rclkcmpsq1n[15]))) & (~ (sudi[6] ^ rclkcmpsq1n[16]))) & (~ (sudi[7] ^ rclkcmpsq1n[17]))) & (~ (sudi[8] ^ rclkcmpsq1n[18]))) & (~ (sudi[9] ^ rclkcmpsq1n[19]))),
		nll1llO = ((((((((((~ (sudi[0] ^ rclkcmpsq1p[10])) & (~ (sudi[1] ^ rclkcmpsq1p[11]))) & (~ (sudi[2] ^ rclkcmpsq1p[12]))) & (~ (sudi[3] ^ rclkcmpsq1p[13]))) & (~ (sudi[4] ^ rclkcmpsq1p[14]))) & (~ (sudi[5] ^ rclkcmpsq1p[15]))) & (~ (sudi[6] ^ rclkcmpsq1p[16]))) & (~ (sudi[7] ^ rclkcmpsq1p[17]))) & (~ (sudi[8] ^ rclkcmpsq1p[18]))) & (~ (sudi[9] ^ rclkcmpsq1p[19]))),
		nll1O0i = ((rskpsetbased & nliO0li) | nliO1lO),
		nll1O0l = ((wire_n0000l_dataout & (n10ili & ((~ rskpsetbased) & nlilO0i))) | ((n1O0iO | ((n10ili & ((rclkcmpsqmd & (~ nliOiiO)) & (rtruebac2bac | ((~ rtruebac2bac) & (~ n1O00O))))) & ((nliOl1O & nlilO1l) | (nliOl1l & nlilO1i)))) | (nliO0Oi | ((n1O0Oi & (n1O1Oi & (n10ili & (rrx_pipe_enable & ((~ rclkcmpsqmd) & ((~ rtruebac2bac) & (~ nliOiiO))))))) | nlilO1O)))),
		nll1O1l = (wire_n0il_dataout | wire_n0ii_dataout),
		nll1OlO = (nliOl0l | nliOl0i),
		nll1OOO = ((((~ rrx_pipe_enable) & nliO0ii) & nliO00O) & nliO00l),
		rdfifo_almost_empty = wire_nll_dataout,
		rdfifo_almost_full = wire_ni_dataout,
		rdfifo_empty = wire_nli_dataout,
		rdfifo_full = wire_nlO_dataout,
		rev_loop_data = {wire_nl11i_dataout, wire_niOOO_dataout, wire_niOOl_dataout, wire_niOOi_dataout, wire_niOlO_dataout, wire_niOll_dataout, wire_niOli_dataout, wire_niOiO_dataout, wire_niOil_dataout, wire_niOii_dataout, wire_niO0O_dataout, wire_niO0l_dataout, wire_niO0i_dataout, wire_niO1O_dataout, wire_niO1l_dataout, wire_niO1i_dataout, wire_nilOO_dataout, wire_nilOl_dataout, wire_nilOi_dataout, wire_nillO_dataout};
endmodule //arriagx_hssi_rx_comp_chnl_top
//synopsys translate_on
//VALID FILE

`timescale 1 ps / 1 ps
module arriagx_hssi_rx_byte_des (
    soft_reset,
    clk_2,
    rx_we_out,
    rdwidth,
    rx_wr_clk,
    soft_reset_wclk1,
    bo_en,
    bo_3g_en,
	rx_data_int,
    sync_resync_d,
    disp_err_d,
    pattern_det_d,
    ovr_undflow_d,
    disp_val_d,

    byte_des_fifo_data_in,
    byte_des_bo_3g_start
);

input           soft_reset;
input           clk_2;
input           rx_we_out;
input           rdwidth;
input           rx_wr_clk;
input           soft_reset_wclk1;

input           bo_en;
input           bo_3g_en;
	
input    [19:0] rx_data_int;
input    [1:0]  sync_resync_d;
input    [1:0]  disp_err_d;
input    [1:0]  pattern_det_d;
input    [3:0]  ovr_undflow_d;
input    [1:0]  disp_val_d;

output [63:0] byte_des_fifo_data_in;
output [1:0]  byte_des_bo_3g_start;

reg    [63:0] fifo_data_in;
reg    [1:0]  bo_3g_start;

reg    [31:0] data_lt_0_sync;
reg    [31:0] data_lt_0;
reg    [31:0] data_lt_1;

reg           bo_3g_en_lt_0_sync;
reg           bo_3g_en_lt_0;
reg           bo_3g_en_lt_1;

assign byte_des_fifo_data_in = fifo_data_in;
assign byte_des_bo_3g_start  = bo_3g_start;

always @(posedge soft_reset or posedge clk_2)
begin
   if (soft_reset)
      begin
         data_lt_1            <= 32'h00000000;
         data_lt_0            <= 32'h00000000;
         data_lt_0_sync       <= 32'h00000000;
         bo_3g_en_lt_1        <= 1'b0;
         bo_3g_en_lt_0        <= 1'b0;
         bo_3g_en_lt_0_sync   <= 1'b0;
      end
   else
      begin
         if (rdwidth && !rx_we_out)
            begin
               data_lt_1[7:0]  <= #1  rx_data_int[7:0];
               data_lt_1[8]    <= #1  rx_data_int[8];
               data_lt_1[9]    <= #1  rx_data_int[9];
               data_lt_1[10]   <= #1  sync_resync_d[0];
               data_lt_1[11]   <= #1  disp_err_d[0];
               data_lt_1[12]   <= #1  pattern_det_d[0];
               data_lt_1[13]   <= #1  ovr_undflow_d[0];
               data_lt_1[14]   <= #1  ovr_undflow_d[1];
               data_lt_1[15]   <= #1  disp_val_d[0];
               data_lt_1[23:16]<= #1  rx_data_int[17:10];
               data_lt_1[24]   <= #1  rx_data_int[18];
               data_lt_1[25]   <= #1  rx_data_int[19];
               data_lt_1[26]   <= #1  sync_resync_d[1];
               data_lt_1[27]   <= #1  disp_err_d[1];
               data_lt_1[28]   <= #1  pattern_det_d[1];
               data_lt_1[29]   <= #1  ovr_undflow_d[2];
               data_lt_1[30]   <= #1  ovr_undflow_d[3];
               data_lt_1[31]   <= #1  disp_val_d[1];
               bo_3g_en_lt_1   <= #1  bo_en | bo_3g_en;
            end

         if (rdwidth & rx_we_out)
            begin
               data_lt_0[7:0]  <= #1  rx_data_int[7:0];
               data_lt_0[8]    <= #1  rx_data_int[8];
               data_lt_0[9]    <= #1  rx_data_int[9];
               data_lt_0[10]   <= #1  sync_resync_d[0];
               data_lt_0[11]   <= #1  disp_err_d[0];
               data_lt_0[12]   <= #1  pattern_det_d[0];
               data_lt_0[13]   <= #1  ovr_undflow_d[0];
               data_lt_0[14]   <= #1  ovr_undflow_d[1];
               data_lt_0[15]   <= #1  disp_val_d[0];
               data_lt_0[23:16]<= #1  rx_data_int[17:10];
               data_lt_0[24]   <= #1  rx_data_int[18];
               data_lt_0[25]   <= #1  rx_data_int[19];
               data_lt_0[26]   <= #1  sync_resync_d[1];
               data_lt_0[27]   <= #1  disp_err_d[1];
               data_lt_0[28]   <= #1  pattern_det_d[1];
               data_lt_0[29]   <= #1  ovr_undflow_d[2];
               data_lt_0[30]   <= #1  ovr_undflow_d[3];
               data_lt_0[31]   <= #1  disp_val_d[1];
               bo_3g_en_lt_0   <= #1  bo_en | bo_3g_en;
            end

         if (!rdwidth)
            begin
               data_lt_0_sync[7:0]  <=  rx_data_int[7:0];
               data_lt_0_sync[8]    <=  rx_data_int[8];
               data_lt_0_sync[9]    <=  rx_data_int[9];
               data_lt_0_sync[10]   <=  sync_resync_d[0];
               data_lt_0_sync[11]   <=  disp_err_d[0];
               data_lt_0_sync[12]   <=  pattern_det_d[0];
               data_lt_0_sync[13]   <=  ovr_undflow_d[0];
               data_lt_0_sync[14]   <=  ovr_undflow_d[1];
               data_lt_0_sync[15]   <=  disp_val_d[0];
               data_lt_0_sync[23:16]<=  rx_data_int[17:10];
               data_lt_0_sync[24]   <=  rx_data_int[18];
               data_lt_0_sync[25]   <=  rx_data_int[19];
               data_lt_0_sync[26]   <=  sync_resync_d[1];
               data_lt_0_sync[27]   <=  disp_err_d[1];
               data_lt_0_sync[28]   <=  pattern_det_d[1];
               data_lt_0_sync[29]   <=  ovr_undflow_d[2];
               data_lt_0_sync[30]   <=  ovr_undflow_d[3];
               data_lt_0_sync[31]   <=  disp_val_d[1];
               bo_3g_en_lt_0_sync   <=  bo_en | bo_3g_en;
            end
         else 
            begin
               data_lt_0_sync     <= #1 data_lt_0;
               bo_3g_en_lt_0_sync <= #1 bo_3g_en_lt_0;
            end

      end
end

// write enable, fifo data in
always @(posedge rx_wr_clk or posedge soft_reset_wclk1)
begin
	if (soft_reset_wclk1)
	begin
		fifo_data_in <= 64'h0000000000000000;
		bo_3g_start <= 2'h0;
	end
	else
	begin
		// add one unit delay to help VCS to order the sampling 
		// sequence between clk_2 and rx_wr_clk
		fifo_data_in <= #1 {data_lt_1, data_lt_0_sync};	
		bo_3g_start  <= #1 {bo_3g_en_lt_1, bo_3g_en_lt_0_sync};	
	end
end

endmodule
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 364 mux21 1224 oper_decoder 7 oper_mux 200 oper_selector 2 arriagx_hssi_ram8x65_syn 1 arriagx_hssi_rx_byte_des 1 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_ctrl
	( 
	bytord_valid_out,
	bytordplden,
	clk_2,
	dec_data_valid,
	dec_data_valid_pre,
	disp_err_delay,
	disp_val_delay,
	endec_rx,
	indv_rx,
	invalid_code_delay,
	ovr_undflow,
	ph_fifo_empty,
	ph_fifo_full,
	pld_re,
	pld_wr_dis,
	rautoinsdis,
	rbytord_2sym_en,
	rbytorden,
	rbytordpadval,
	rbytordpat,
	rbytordplden,
	rclkcmpinsertpad,
	rd_enable2,
	rd_enable_ch0,
	rd_enable_out,
	rd_enable_q0_ch0,
	rdwidth,
	rendec_data_sel_rx,
	rinvalid_code_err_only,
	rphfifo_master_sel_rx,
	rpmadatawidth,
	rptr_bin,
	rrxfifo_dis,
	rrxfifo_lowlatency_en,
	rrxfifo_urst_en,
	rrxphfifopldctl_en,
	rsync_comp_pat,
	rsync_comp_porn,
	rsync_comp_size,
	rsync_sm_dis,
	running_disp,
	rwa_6g_en,
	rx_control_dt,
	rx_control_rs,
	rx_data_dt,
	rx_data_rs,
	rx_rd_clk,
	rx_we_in_ch0,
	rx_we_in_q0_ch0,
	rx_we_out,
	rx_wr_clk,
	rxc,
	rxd,
	rxd_19,
	rxd_9,
	rxd_lpbk,
	rxfifo_urst,
	scan_mode,
	signal_detect_out,
	signal_detect_sync_st,
	soft_reset,
	soft_reset_rclk1,
	sync_resync_delay,
	sync_resync_pre,
	tenb_data,
	wptr_bin,
	wr_enable2,
	wr_enable_ch0,
	wr_enable_out,
	wr_enable_q0_ch0) /* synthesis synthesis_clearbox=1 */;
	output   bytord_valid_out;
	input   bytordplden;
	input   clk_2;
	input   [1:0]  dec_data_valid;
	input   [1:0]  dec_data_valid_pre;
	input   [1:0]  disp_err_delay;
	input   [1:0]  disp_val_delay;
	input   endec_rx;
	input   indv_rx;
	input   [1:0]  invalid_code_delay;
	input   [3:0]  ovr_undflow;
	output   ph_fifo_empty;
	output   ph_fifo_full;
	input   pld_re;
	input   pld_wr_dis;
	input   rautoinsdis;
	input   rbytord_2sym_en;
	input   [1:0]  rbytorden;
	input   [9:0]  rbytordpadval;
	input   [9:0]  rbytordpat;
	input   rbytordplden;
	input   rclkcmpinsertpad;
	output   rd_enable2;
	input   rd_enable_ch0;
	output   rd_enable_out;
	input   rd_enable_q0_ch0;
	input   rdwidth;
	input   rendec_data_sel_rx;
	input   rinvalid_code_err_only;
	input   rphfifo_master_sel_rx;
	input   rpmadatawidth;
	output   [2:0]  rptr_bin;
	input   rrxfifo_dis;
	input   rrxfifo_lowlatency_en;
	input   rrxfifo_urst_en;
	input   rrxphfifopldctl_en;
	input   [39:0]  rsync_comp_pat;
	input   rsync_comp_porn;
	input   [2:0]  rsync_comp_size;
	input   rsync_sm_dis;
	output   [1:0]  running_disp;
	input   rwa_6g_en;
	input   [1:0]  rx_control_dt;
	input   rx_control_rs;
	input   [15:0]  rx_data_dt;
	input   [7:0]  rx_data_rs;
	input   rx_rd_clk;
	input   rx_we_in_ch0;
	input   rx_we_in_q0_ch0;
	output   rx_we_out;
	input   rx_wr_clk;
	output   [3:0]  rxc;
	output   [63:0]  rxd;
	output   [1:0]  rxd_19;
	output   [1:0]  rxd_9;
	output   [39:0]  rxd_lpbk;
	input   rxfifo_urst;
	input   scan_mode;
	output   signal_detect_out;
	input   signal_detect_sync_st;
	input   soft_reset;
	output   soft_reset_rclk1;
	input   [1:0]  sync_resync_delay;
	input   [1:0]  sync_resync_pre;
	input   [19:0]  tenb_data;
	output   [2:0]  wptr_bin;
	output   wr_enable2;
	input   wr_enable_ch0;
	output   wr_enable_out;
	input   wr_enable_q0_ch0;

	reg	nl0000i61;
	reg	nl0000i62;
	reg	nl0000l59;
	reg	nl0000l60;
	reg	nl0000O57;
	reg	nl0000O58;
	reg	nl000il55;
	reg	nl000il56;
	reg	nl000iO53;
	reg	nl000iO54;
	reg	nl000Ol51;
	reg	nl000Ol52;
	reg	nl000OO49;
	reg	nl000OO50;
	reg	nl0i01O41;
	reg	nl0i01O42;
	reg	nl0i1ii47;
	reg	nl0i1ii48;
	reg	nl0i1il45;
	reg	nl0i1il46;
	reg	nl0i1iO43;
	reg	nl0i1iO44;
	reg	nl0illi39;
	reg	nl0illi40;
	reg	nl0ilOi37;
	reg	nl0ilOi38;
	reg	nl0iO0i33;
	reg	nl0iO0i34;
	reg	nl0iO1i35;
	reg	nl0iO1i36;
	reg	nl0iOii31;
	reg	nl0iOii32;
	reg	nl0iOil29;
	reg	nl0iOil30;
	reg	nl0iOlO27;
	reg	nl0iOlO28;
	reg	nl0l00i5;
	reg	nl0l00i6;
	reg	nl0l01i11;
	reg	nl0l01i12;
	reg	nl0l01l10;
	reg	nl0l01l9;
	reg	nl0l01O7;
	reg	nl0l01O8;
	reg	nl0l0ii3;
	reg	nl0l0ii4;
	reg	nl0l0li1;
	reg	nl0l0li2;
	reg	nl0l10i23;
	reg	nl0l10i24;
	reg	nl0l10O21;
	reg	nl0l10O22;
	reg	nl0l11i25;
	reg	nl0l11i26;
	reg	nl0l1il19;
	reg	nl0l1il20;
	reg	nl0l1iO17;
	reg	nl0l1iO18;
	reg	nl0l1ll15;
	reg	nl0l1ll16;
	reg	nl0l1Oi13;
	reg	nl0l1Oi14;
	reg	n110i;
	reg	n111i;
	reg	n111O_clk_prev;
	wire	wire_n111O_CLRN;
	wire	wire_n111O_PRN;
	reg	n11OOl;
	reg	n11OOi_clk_prev;
	wire	wire_n11OOi_CLRN;
	wire	wire_n11OOi_PRN;
	reg	n100i;
	reg	n100l;
	reg	n100O;
	reg	n1010O;
	reg	n101i;
	reg	n101l;
	reg	n101O;
	reg	n10ii;
	reg	n10il;
	reg	n10iO;
	reg	n10li;
	reg	n10ll;
	reg	n10lO;
	reg	n10Oi;
	reg	n10Ol;
	reg	n10OO;
	reg	n110l;
	reg	n110O;
	reg	n11ii;
	reg	n11il;
	reg	n11iO;
	reg	n11li;
	reg	n11ll;
	reg	n11lO;
	reg	n11Oi;
	reg	n11Ol;
	reg	n11Oll;
	reg	n11OlO;
	reg	n11OO;
	reg	n1i0i;
	reg	n1i0l;
	reg	n1i0O;
	reg	n1i1i;
	reg	n1i1l;
	reg	n1i1O;
	reg	n1iii;
	reg	n1iil;
	reg	n1iiO;
	reg	n1ili;
	reg	n1ill;
	reg	n1ilO;
	reg	n1iOi;
	reg	n1iOl;
	reg	n1iOO;
	reg	n1l1i;
	reg	n1l1O;
	wire	wire_n1l1l_CLRN;
	reg	nl0OlOi;
	reg	nl0OllO_clk_prev;
	wire	wire_nl0OllO_CLRN;
	wire	wire_nl0OllO_PRN;
	wire	wire_nl0OllO_ENA;
	reg	nl0OO0l;
	reg	nl0OOOi;
	reg	nli101i;
	reg	nli10li;
	reg	nli11ii;
	wire	wire_nli10iO_PRN;
	reg	nli10Oi;
	reg	nli10lO_clk_prev;
	wire	wire_nli10lO_CLRN;
	wire	wire_nli10lO_PRN;
	reg	nl0llOi;
	reg	nl0lOil;
	reg	nl0lOiO;
	reg	nl0lOli;
	reg	nl0lOll;
	reg	nl0lOlO;
	reg	nl0lOOi;
	reg	nl0lOOl;
	reg	nl0lOOO;
	reg	nl0O00i;
	reg	nl0O00l;
	reg	nl0O00O;
	reg	nl0O01i;
	reg	nl0O01l;
	reg	nl0O01O;
	reg	nl0O0ii;
	reg	nl0O0il;
	reg	nl0O0iO;
	reg	nl0O0li;
	reg	nl0O0ll;
	reg	nl0O0lO;
	reg	nl0O0Oi;
	reg	nl0O0Ol;
	reg	nl0O0OO;
	reg	nl0O10i;
	reg	nl0O10l;
	reg	nl0O10O;
	reg	nl0O11i;
	reg	nl0O11l;
	reg	nl0O11O;
	reg	nl0O1ii;
	reg	nl0O1il;
	reg	nl0O1iO;
	reg	nl0O1li;
	reg	nl0O1ll;
	reg	nl0O1lO;
	reg	nl0O1Oi;
	reg	nl0O1Ol;
	reg	nl0O1OO;
	reg	nl0Oi0i;
	reg	nl0Oi0l;
	reg	nl0Oi0O;
	reg	nl0Oi1i;
	reg	nl0Oi1l;
	reg	nl0Oi1O;
	reg	nl0Oiii;
	reg	nl0Oiil;
	reg	nl0OiiO;
	reg	nl0Oili;
	reg	nl0Oill;
	reg	nl0OilO;
	reg	nl0OiOi;
	reg	nl0OiOl;
	reg	nl0OiOO;
	reg	nl0Ol0i;
	reg	nl0Ol0l;
	reg	nl0Ol0O;
	reg	nl0Ol1i;
	reg	nl0Ol1l;
	reg	nl0Ol1O;
	reg	nl0Olii;
	reg	nl0Olil;
	reg	nl0OliO;
	reg	nl0Olli;
	reg	nl0Olll;
	reg	nl0OlOl;
	reg	nl0OlOO;
	reg	nl0OO0i;
	reg	nl0OO0O;
	reg	nl0OO1i;
	reg	nl0OO1l;
	reg	nl0OO1O;
	reg	nl0OOii;
	reg	nl0OOil;
	reg	nl0OOiO;
	reg	nl0OOli;
	reg	nl0OOll;
	reg	nl0OOlO;
	reg	nl0OOOl;
	reg	nl0OOOO;
	reg	nli100i;
	reg	nli100l;
	reg	nli100O;
	reg	nli101l;
	reg	nli101O;
	reg	nli10ii;
	reg	nli10il;
	reg	nli10ll;
	reg	nli110i;
	reg	nli110l;
	reg	nli110O;
	reg	nli111i;
	reg	nli111l;
	reg	nli111O;
	reg	nli11il;
	reg	nli11iO;
	reg	nli11li;
	reg	nli11ll;
	reg	nli11lO;
	reg	nli11Oi;
	reg	nli11Ol;
	reg	nli11OO;
	reg	nlO0ll;
	reg	nlOl0l;
	reg	nlOl0O;
	reg	nlOlil;
	reg	n11OOO;
	reg	nli1lli;
	reg	nli1lll;
	reg	nli1llO;
	reg	nli1lOi;
	reg	nli1lOl;
	reg	nli1lOO;
	reg	nli1O1i;
	reg	nliliO;
	reg	nlilli;
	reg	nlilll;
	reg	nlillO;
	reg	nlilOi;
	reg	nlilOl;
	reg	nlilOO;
	reg	nliO0i;
	reg	nliO0l;
	reg	nliO0O;
	reg	nliO1i;
	reg	nliO1l;
	reg	nliO1O;
	reg	nliOii;
	reg	nliOil;
	reg	nliOiO;
	reg	nliOli;
	reg	nliOll;
	reg	nliOlO;
	reg	nliOOi;
	reg	nliOOl;
	reg	nliOOO;
	reg	nll00i;
	reg	nll00l;
	reg	nll00O;
	reg	nll01i;
	reg	nll01l;
	reg	nll01O;
	reg	nll0ii;
	reg	nll0il;
	reg	nll0iO;
	reg	nll0li;
	reg	nll0ll;
	reg	nll0lO;
	reg	nll0Oi;
	reg	nll0Ol;
	reg	nll0OO;
	reg	nll10i;
	reg	nll10l;
	reg	nll10O;
	reg	nll11i;
	reg	nll11l;
	reg	nll11O;
	reg	nll1ii;
	reg	nll1il;
	reg	nll1iO;
	reg	nll1li;
	reg	nll1ll;
	reg	nll1lO;
	reg	nll1Oi;
	reg	nll1Ol;
	reg	nll1OO;
	reg	nlli0i;
	reg	nlli0l;
	reg	nlli0O;
	reg	nlli1i;
	reg	nlli1l;
	reg	nlli1O;
	reg	nlliii;
	reg	nlliil;
	reg	nlliiO;
	reg	nllili;
	reg	nllill;
	reg	nllilO;
	reg	nlliOi;
	reg	nlliOl;
	reg	nlliOO;
	reg	nlll0i;
	reg	nlll0l;
	reg	nlll0O;
	reg	nlll1i;
	reg	nlll1l;
	reg	nlll1O;
	reg	nlllii;
	reg	nlllil;
	reg	nllliO;
	reg	nlllli;
	reg	nlllll;
	reg	nllllO;
	reg	nlllOi;
	reg	nlllOl;
	reg	nlllOO;
	reg	nllO0i;
	reg	nllO0l;
	reg	nllO0O;
	reg	nllO1i;
	reg	nllO1l;
	reg	nllO1O;
	reg	nllOii;
	reg	nllOil;
	reg	nllOiO;
	reg	nllOli;
	reg	nllOll;
	reg	nllOlO;
	reg	nllOOi;
	reg	nllOOl;
	reg	nllOOO;
	reg	nlO00i;
	reg	nlO00l;
	reg	nlO00O;
	reg	nlO01i;
	reg	nlO01l;
	reg	nlO01O;
	reg	nlO0ii;
	reg	nlO0il;
	reg	nlO0iO;
	reg	nlO0li;
	reg	nlO10i;
	reg	nlO10l;
	reg	nlO10O;
	reg	nlO11i;
	reg	nlO11l;
	reg	nlO11O;
	reg	nlO1ii;
	reg	nlO1il;
	reg	nlO1iO;
	reg	nlO1li;
	reg	nlO1ll;
	reg	nlO1lO;
	reg	nlO1Oi;
	reg	nlO1Ol;
	reg	nlO1OO;
	reg	nlOliO;
	reg	nlOlOl;
	reg	nlOlOO;
	reg	nlOO0i;
	reg	nlOO0O;
	reg	nlOO1i;
	reg	nlOO1l;
	reg	nlOO1O;
	reg	nlOOii;
	reg	nlOOOO;
	reg	nlOOOl_clk_prev;
	wire	wire_nlOOOl_CLRN;
	wire	wire_n0000i_dataout;
	wire	wire_n0000l_dataout;
	wire	wire_n0000O_dataout;
	wire	wire_n0001i_dataout;
	wire	wire_n0001l_dataout;
	wire	wire_n0001O_dataout;
	wire	wire_n000i_dataout;
	wire	wire_n000ii_dataout;
	wire	wire_n000il_dataout;
	wire	wire_n000iO_dataout;
	wire	wire_n000l_dataout;
	wire	wire_n000li_dataout;
	wire	wire_n000ll_dataout;
	wire	wire_n000lO_dataout;
	wire	wire_n000O_dataout;
	wire	wire_n000Oi_dataout;
	wire	wire_n000Ol_dataout;
	wire	wire_n000OO_dataout;
	wire	wire_n0010i_dataout;
	wire	wire_n0010l_dataout;
	wire	wire_n0010O_dataout;
	wire	wire_n0011i_dataout;
	wire	wire_n0011l_dataout;
	wire	wire_n0011O_dataout;
	wire	wire_n001i_dataout;
	wire	wire_n001ii_dataout;
	wire	wire_n001il_dataout;
	wire	wire_n001iO_dataout;
	wire	wire_n001l_dataout;
	wire	wire_n001li_dataout;
	wire	wire_n001ll_dataout;
	wire	wire_n001lO_dataout;
	wire	wire_n001O_dataout;
	wire	wire_n001Oi_dataout;
	wire	wire_n001Ol_dataout;
	wire	wire_n001OO_dataout;
	wire	wire_n00i_dataout;
	wire	wire_n00i0i_dataout;
	wire	wire_n00i0l_dataout;
	wire	wire_n00i0O_dataout;
	wire	wire_n00i1i_dataout;
	wire	wire_n00i1l_dataout;
	wire	wire_n00i1O_dataout;
	wire	wire_n00ii_dataout;
	wire	wire_n00iii_dataout;
	wire	wire_n00iil_dataout;
	wire	wire_n00iiO_dataout;
	wire	wire_n00il_dataout;
	wire	wire_n00ili_dataout;
	wire	wire_n00ill_dataout;
	wire	wire_n00ilO_dataout;
	wire	wire_n00iO_dataout;
	wire	wire_n00iOi_dataout;
	wire	wire_n00iOl_dataout;
	wire	wire_n00iOO_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00l0i_dataout;
	wire	wire_n00l0l_dataout;
	wire	wire_n00l0O_dataout;
	wire	wire_n00l1i_dataout;
	wire	wire_n00l1l_dataout;
	wire	wire_n00l1O_dataout;
	wire	wire_n00li_dataout;
	wire	wire_n00lii_dataout;
	wire	wire_n00lil_dataout;
	wire	wire_n00liO_dataout;
	wire	wire_n00ll_dataout;
	wire	wire_n00lli_dataout;
	wire	wire_n00lll_dataout;
	wire	wire_n00llO_dataout;
	wire	wire_n00lO_dataout;
	wire	wire_n00lOi_dataout;
	wire	wire_n00lOl_dataout;
	wire	wire_n00lOO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n00O0i_dataout;
	wire	wire_n00O0l_dataout;
	wire	wire_n00O0O_dataout;
	wire	wire_n00O1i_dataout;
	wire	wire_n00O1l_dataout;
	wire	wire_n00O1O_dataout;
	wire	wire_n00Oi_dataout;
	wire	wire_n00Oii_dataout;
	wire	wire_n00Oil_dataout;
	wire	wire_n00OiO_dataout;
	wire	wire_n00Oli_dataout;
	wire	wire_n00Oll_dataout;
	wire	wire_n00OlO_dataout;
	wire	wire_n00OO_dataout;
	wire	wire_n00OOi_dataout;
	wire	wire_n00OOl_dataout;
	wire	wire_n00OOO_dataout;
	wire	wire_n0100i_dataout;
	wire	wire_n0100l_dataout;
	wire	wire_n0100O_dataout;
	wire	wire_n0101i_dataout;
	wire	wire_n0101l_dataout;
	wire	wire_n0101O_dataout;
	wire	wire_n010i_dataout;
	wire	wire_n010ii_dataout;
	wire	wire_n010il_dataout;
	wire	wire_n010iO_dataout;
	wire	wire_n010l_dataout;
	wire	wire_n010li_dataout;
	wire	wire_n010ll_dataout;
	wire	wire_n010lO_dataout;
	wire	wire_n010O_dataout;
	wire	wire_n010Oi_dataout;
	wire	wire_n010Ol_dataout;
	wire	wire_n010OO_dataout;
	wire	wire_n0110i_dataout;
	wire	wire_n0110l_dataout;
	wire	wire_n0110O_dataout;
	wire	wire_n0111i_dataout;
	wire	wire_n0111l_dataout;
	wire	wire_n0111O_dataout;
	wire	wire_n011i_dataout;
	wire	wire_n011ii_dataout;
	wire	wire_n011il_dataout;
	wire	wire_n011iO_dataout;
	wire	wire_n011l_dataout;
	wire	wire_n011li_dataout;
	wire	wire_n011ll_dataout;
	wire	wire_n011lO_dataout;
	wire	wire_n011O_dataout;
	wire	wire_n011Oi_dataout;
	wire	wire_n011Ol_dataout;
	wire	wire_n011OO_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01i0i_dataout;
	wire	wire_n01i0l_dataout;
	wire	wire_n01i0O_dataout;
	wire	wire_n01i1i_dataout;
	wire	wire_n01i1l_dataout;
	wire	wire_n01i1O_dataout;
	wire	wire_n01ii_dataout;
	wire	wire_n01iii_dataout;
	wire	wire_n01iil_dataout;
	wire	wire_n01iiO_dataout;
	wire	wire_n01il_dataout;
	wire	wire_n01ili_dataout;
	wire	wire_n01ill_dataout;
	wire	wire_n01ilO_dataout;
	wire	wire_n01iO_dataout;
	wire	wire_n01iOi_dataout;
	wire	wire_n01iOl_dataout;
	wire	wire_n01iOO_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01l0i_dataout;
	wire	wire_n01l0l_dataout;
	wire	wire_n01l0O_dataout;
	wire	wire_n01l1i_dataout;
	wire	wire_n01l1l_dataout;
	wire	wire_n01l1O_dataout;
	wire	wire_n01li_dataout;
	wire	wire_n01lii_dataout;
	wire	wire_n01lil_dataout;
	wire	wire_n01liO_dataout;
	wire	wire_n01ll_dataout;
	wire	wire_n01lli_dataout;
	wire	wire_n01lll_dataout;
	wire	wire_n01llO_dataout;
	wire	wire_n01lO_dataout;
	wire	wire_n01lOi_dataout;
	wire	wire_n01lOl_dataout;
	wire	wire_n01lOO_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n01O0i_dataout;
	wire	wire_n01O0l_dataout;
	wire	wire_n01O0O_dataout;
	wire	wire_n01O1i_dataout;
	wire	wire_n01O1l_dataout;
	wire	wire_n01O1O_dataout;
	wire	wire_n01Oi_dataout;
	wire	wire_n01Oii_dataout;
	wire	wire_n01Oil_dataout;
	wire	wire_n01OiO_dataout;
	wire	wire_n01Ol_dataout;
	wire	wire_n01Oli_dataout;
	wire	wire_n01Oll_dataout;
	wire	wire_n01OlO_dataout;
	wire	wire_n01OO_dataout;
	wire	wire_n01OOi_dataout;
	wire	wire_n01OOl_dataout;
	wire	wire_n01OOO_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0i00i_dataout;
	wire	wire_n0i00l_dataout;
	wire	wire_n0i00O_dataout;
	wire	wire_n0i01i_dataout;
	wire	wire_n0i01l_dataout;
	wire	wire_n0i01O_dataout;
	wire	wire_n0i0i_dataout;
	wire	wire_n0i0ii_dataout;
	wire	wire_n0i0il_dataout;
	wire	wire_n0i0iO_dataout;
	wire	wire_n0i0l_dataout;
	wire	wire_n0i0li_dataout;
	wire	wire_n0i0ll_dataout;
	wire	wire_n0i0lO_dataout;
	wire	wire_n0i0O_dataout;
	wire	wire_n0i0Oi_dataout;
	wire	wire_n0i0Ol_dataout;
	wire	wire_n0i0OO_dataout;
	wire	wire_n0i10i_dataout;
	wire	wire_n0i10l_dataout;
	wire	wire_n0i10O_dataout;
	wire	wire_n0i11i_dataout;
	wire	wire_n0i11l_dataout;
	wire	wire_n0i11O_dataout;
	wire	wire_n0i1ii_dataout;
	wire	wire_n0i1il_dataout;
	wire	wire_n0i1iO_dataout;
	wire	wire_n0i1l_dataout;
	wire	wire_n0i1li_dataout;
	wire	wire_n0i1ll_dataout;
	wire	wire_n0i1lO_dataout;
	wire	wire_n0i1O_dataout;
	wire	wire_n0i1Oi_dataout;
	wire	wire_n0i1Ol_dataout;
	wire	wire_n0i1OO_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0ii0i_dataout;
	wire	wire_n0ii0l_dataout;
	wire	wire_n0ii0O_dataout;
	wire	wire_n0ii1i_dataout;
	wire	wire_n0ii1l_dataout;
	wire	wire_n0ii1O_dataout;
	wire	wire_n0iii_dataout;
	wire	wire_n0iiii_dataout;
	wire	wire_n0iiil_dataout;
	wire	wire_n0iiiO_dataout;
	wire	wire_n0iil_dataout;
	wire	wire_n0iili_dataout;
	wire	wire_n0iill_dataout;
	wire	wire_n0iilO_dataout;
	wire	wire_n0iiO_dataout;
	wire	wire_n0iiOi_dataout;
	wire	wire_n0iiOl_dataout;
	wire	wire_n0iiOO_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0il0i_dataout;
	wire	wire_n0il0l_dataout;
	wire	wire_n0il0O_dataout;
	wire	wire_n0il1i_dataout;
	wire	wire_n0il1l_dataout;
	wire	wire_n0il1O_dataout;
	wire	wire_n0ili_dataout;
	wire	wire_n0ilii_dataout;
	wire	wire_n0ilil_dataout;
	wire	wire_n0iliO_dataout;
	wire	wire_n0ill_dataout;
	wire	wire_n0illi_dataout;
	wire	wire_n0illl_dataout;
	wire	wire_n0illO_dataout;
	wire	wire_n0ilO_dataout;
	wire	wire_n0ilOi_dataout;
	wire	wire_n0ilOl_dataout;
	wire	wire_n0ilOO_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0iO0i_dataout;
	wire	wire_n0iO0l_dataout;
	wire	wire_n0iO0O_dataout;
	wire	wire_n0iO1i_dataout;
	wire	wire_n0iO1l_dataout;
	wire	wire_n0iO1O_dataout;
	wire	wire_n0iOi_dataout;
	wire	wire_n0iOii_dataout;
	wire	wire_n0iOil_dataout;
	wire	wire_n0iOiO_dataout;
	wire	wire_n0iOl_dataout;
	wire	wire_n0iOli_dataout;
	wire	wire_n0iOll_dataout;
	wire	wire_n0iOlO_dataout;
	wire	wire_n0iOO_dataout;
	wire	wire_n0iOOi_dataout;
	wire	wire_n0iOOl_dataout;
	wire	wire_n0iOOO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0l00i_dataout;
	wire	wire_n0l00l_dataout;
	wire	wire_n0l00O_dataout;
	wire	wire_n0l01i_dataout;
	wire	wire_n0l01l_dataout;
	wire	wire_n0l01O_dataout;
	wire	wire_n0l0i_dataout;
	wire	wire_n0l0ii_dataout;
	wire	wire_n0l0il_dataout;
	wire	wire_n0l0iO_dataout;
	wire	wire_n0l0l_dataout;
	wire	wire_n0l0li_dataout;
	wire	wire_n0l0ll_dataout;
	wire	wire_n0l0lO_dataout;
	wire	wire_n0l0O_dataout;
	wire	wire_n0l0Oi_dataout;
	wire	wire_n0l0Ol_dataout;
	wire	wire_n0l0OO_dataout;
	wire	wire_n0l10i_dataout;
	wire	wire_n0l10l_dataout;
	wire	wire_n0l10O_dataout;
	wire	wire_n0l11i_dataout;
	wire	wire_n0l11l_dataout;
	wire	wire_n0l11O_dataout;
	wire	wire_n0l1i_dataout;
	wire	wire_n0l1ii_dataout;
	wire	wire_n0l1il_dataout;
	wire	wire_n0l1iO_dataout;
	wire	wire_n0l1l_dataout;
	wire	wire_n0l1li_dataout;
	wire	wire_n0l1ll_dataout;
	wire	wire_n0l1lO_dataout;
	wire	wire_n0l1O_dataout;
	wire	wire_n0l1Oi_dataout;
	wire	wire_n0l1Ol_dataout;
	wire	wire_n0l1OO_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0li0i_dataout;
	wire	wire_n0li0l_dataout;
	wire	wire_n0li0O_dataout;
	wire	wire_n0li1i_dataout;
	wire	wire_n0li1l_dataout;
	wire	wire_n0li1O_dataout;
	wire	wire_n0lii_dataout;
	wire	wire_n0liii_dataout;
	wire	wire_n0liil_dataout;
	wire	wire_n0liiO_dataout;
	wire	wire_n0lil_dataout;
	wire	wire_n0lili_dataout;
	wire	wire_n0lill_dataout;
	wire	wire_n0lilO_dataout;
	wire	wire_n0liO_dataout;
	wire	wire_n0liOi_dataout;
	wire	wire_n0liOl_dataout;
	wire	wire_n0liOO_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0ll0i_dataout;
	wire	wire_n0ll0l_dataout;
	wire	wire_n0ll0O_dataout;
	wire	wire_n0ll1i_dataout;
	wire	wire_n0ll1l_dataout;
	wire	wire_n0ll1O_dataout;
	wire	wire_n0lli_dataout;
	wire	wire_n0llii_dataout;
	wire	wire_n0llil_dataout;
	wire	wire_n0lliO_dataout;
	wire	wire_n0lll_dataout;
	wire	wire_n0llli_dataout;
	wire	wire_n0llll_dataout;
	wire	wire_n0lllO_dataout;
	wire	wire_n0llO_dataout;
	wire	wire_n0llOi_dataout;
	wire	wire_n0llOl_dataout;
	wire	wire_n0llOO_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0lO0i_dataout;
	wire	wire_n0lO0l_dataout;
	wire	wire_n0lO0O_dataout;
	wire	wire_n0lO1i_dataout;
	wire	wire_n0lO1l_dataout;
	wire	wire_n0lO1O_dataout;
	wire	wire_n0lOi_dataout;
	wire	wire_n0lOii_dataout;
	wire	wire_n0lOil_dataout;
	wire	wire_n0lOiO_dataout;
	wire	wire_n0lOl_dataout;
	wire	wire_n0lOli_dataout;
	wire	wire_n0lOll_dataout;
	wire	wire_n0lOlO_dataout;
	wire	wire_n0lOO_dataout;
	wire	wire_n0lOOi_dataout;
	wire	wire_n0lOOl_dataout;
	wire	wire_n0lOOO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0O00i_dataout;
	wire	wire_n0O00l_dataout;
	wire	wire_n0O00O_dataout;
	wire	wire_n0O01i_dataout;
	wire	wire_n0O01l_dataout;
	wire	wire_n0O01O_dataout;
	wire	wire_n0O0ii_dataout;
	wire	wire_n0O0il_dataout;
	wire	wire_n0O0iO_dataout;
	wire	wire_n0O0l_dataout;
	wire	wire_n0O0li_dataout;
	wire	wire_n0O0ll_dataout;
	wire	wire_n0O0lO_dataout;
	wire	wire_n0O0O_dataout;
	wire	wire_n0O0Oi_dataout;
	wire	wire_n0O0Ol_dataout;
	wire	wire_n0O0OO_dataout;
	wire	wire_n0O10i_dataout;
	wire	wire_n0O10l_dataout;
	wire	wire_n0O10O_dataout;
	wire	wire_n0O11i_dataout;
	wire	wire_n0O11l_dataout;
	wire	wire_n0O11O_dataout;
	wire	wire_n0O1i_dataout;
	wire	wire_n0O1ii_dataout;
	wire	wire_n0O1il_dataout;
	wire	wire_n0O1iO_dataout;
	wire	wire_n0O1l_dataout;
	wire	wire_n0O1li_dataout;
	wire	wire_n0O1ll_dataout;
	wire	wire_n0O1lO_dataout;
	wire	wire_n0O1Oi_dataout;
	wire	wire_n0O1Ol_dataout;
	wire	wire_n0O1OO_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Oi0i_dataout;
	wire	wire_n0Oi0l_dataout;
	wire	wire_n0Oi0O_dataout;
	wire	wire_n0Oi1i_dataout;
	wire	wire_n0Oi1l_dataout;
	wire	wire_n0Oi1O_dataout;
	wire	wire_n0Oii_dataout;
	wire	wire_n0Oiii_dataout;
	wire	wire_n0Oiil_dataout;
	wire	wire_n0OiiO_dataout;
	wire	wire_n0Oil_dataout;
	wire	wire_n0Oili_dataout;
	wire	wire_n0Oill_dataout;
	wire	wire_n0OilO_dataout;
	wire	wire_n0OiO_dataout;
	wire	wire_n0OiOi_dataout;
	wire	wire_n0OiOl_dataout;
	wire	wire_n0OiOO_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0Ol0i_dataout;
	wire	wire_n0Ol0l_dataout;
	wire	wire_n0Ol0O_dataout;
	wire	wire_n0Ol1i_dataout;
	wire	wire_n0Ol1l_dataout;
	wire	wire_n0Ol1O_dataout;
	wire	wire_n0Oli_dataout;
	wire	wire_n0Olii_dataout;
	wire	wire_n0Olil_dataout;
	wire	wire_n0OliO_dataout;
	wire	wire_n0Oll_dataout;
	wire	wire_n0Olli_dataout;
	wire	wire_n0Olll_dataout;
	wire	wire_n0OllO_dataout;
	wire	wire_n0OlO_dataout;
	wire	wire_n0OlOi_dataout;
	wire	wire_n0OlOl_dataout;
	wire	wire_n0OlOO_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n0OO0i_dataout;
	wire	wire_n0OO0l_dataout;
	wire	wire_n0OO0O_dataout;
	wire	wire_n0OO1i_dataout;
	wire	wire_n0OO1l_dataout;
	wire	wire_n0OO1O_dataout;
	wire	wire_n0OOi_dataout;
	wire	wire_n0OOii_dataout;
	wire	wire_n0OOil_dataout;
	wire	wire_n0OOiO_dataout;
	wire	wire_n0OOl_dataout;
	wire	wire_n0OOli_dataout;
	wire	wire_n0OOll_dataout;
	wire	wire_n0OOlO_dataout;
	wire	wire_n0OOO_dataout;
	wire	wire_n0OOOi_dataout;
	wire	wire_n0OOOl_dataout;
	wire	wire_n0OOOO_dataout;
	wire	wire_n1010i_dataout;
	wire	wire_n1010l_dataout;
	wire	wire_n1011i_dataout;
	wire	wire_n1011l_dataout;
	wire	wire_n1011O_dataout;
	wire	wire_n101ii_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n10OOi_dataout;
	wire	wire_n10OOl_dataout;
	wire	wire_n10OOO_dataout;
	wire	wire_n111l_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1i00i_dataout;
	wire	wire_n1i00l_dataout;
	wire	wire_n1i00O_dataout;
	wire	wire_n1i01i_dataout;
	wire	wire_n1i01l_dataout;
	wire	wire_n1i01O_dataout;
	wire	wire_n1i0ii_dataout;
	wire	wire_n1i0il_dataout;
	wire	wire_n1i0iO_dataout;
	wire	wire_n1i0li_dataout;
	wire	wire_n1i0ll_dataout;
	wire	wire_n1i0lO_dataout;
	wire	wire_n1i0Oi_dataout;
	wire	wire_n1i0Ol_dataout;
	wire	wire_n1i0OO_dataout;
	wire	wire_n1i10i_dataout;
	wire	wire_n1i10l_dataout;
	wire	wire_n1i10O_dataout;
	wire	wire_n1i11i_dataout;
	wire	wire_n1i11l_dataout;
	wire	wire_n1i11O_dataout;
	wire	wire_n1i1ii_dataout;
	wire	wire_n1i1il_dataout;
	wire	wire_n1i1iO_dataout;
	wire	wire_n1i1li_dataout;
	wire	wire_n1i1ll_dataout;
	wire	wire_n1i1lO_dataout;
	wire	wire_n1i1Oi_dataout;
	wire	wire_n1i1Ol_dataout;
	wire	wire_n1i1OO_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1ii0i_dataout;
	wire	wire_n1ii0l_dataout;
	wire	wire_n1ii0O_dataout;
	wire	wire_n1ii1i_dataout;
	wire	wire_n1ii1l_dataout;
	wire	wire_n1ii1O_dataout;
	wire	wire_n1iiii_dataout;
	wire	wire_n1iiil_dataout;
	wire	wire_n1iiiO_dataout;
	wire	wire_n1iili_dataout;
	wire	wire_n1iill_dataout;
	wire	wire_n1iilO_dataout;
	wire	wire_n1iiOi_dataout;
	wire	wire_n1iiOl_dataout;
	wire	wire_n1iiOO_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1il0i_dataout;
	wire	wire_n1il0l_dataout;
	wire	wire_n1il0O_dataout;
	wire	wire_n1il1i_dataout;
	wire	wire_n1il1l_dataout;
	wire	wire_n1il1O_dataout;
	wire	wire_n1ilii_dataout;
	wire	wire_n1ilil_dataout;
	wire	wire_n1iliO_dataout;
	wire	wire_n1illi_dataout;
	wire	wire_n1illl_dataout;
	wire	wire_n1illO_dataout;
	wire	wire_n1ilOi_dataout;
	wire	wire_n1ilOl_dataout;
	wire	wire_n1ilOO_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1iO0i_dataout;
	wire	wire_n1iO0l_dataout;
	wire	wire_n1iO0O_dataout;
	wire	wire_n1iO1i_dataout;
	wire	wire_n1iO1l_dataout;
	wire	wire_n1iO1O_dataout;
	wire	wire_n1iOii_dataout;
	wire	wire_n1iOil_dataout;
	wire	wire_n1iOiO_dataout;
	wire	wire_n1iOli_dataout;
	wire	wire_n1iOll_dataout;
	wire	wire_n1iOlO_dataout;
	wire	wire_n1iOOi_dataout;
	wire	wire_n1iOOl_dataout;
	wire	wire_n1iOOO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1l00i_dataout;
	wire	wire_n1l00l_dataout;
	wire	wire_n1l00O_dataout;
	wire	wire_n1l01i_dataout;
	wire	wire_n1l01l_dataout;
	wire	wire_n1l01O_dataout;
	wire	wire_n1l0ii_dataout;
	wire	wire_n1l0il_dataout;
	wire	wire_n1l0iO_dataout;
	wire	wire_n1l0li_dataout;
	wire	wire_n1l0ll_dataout;
	wire	wire_n1l0lO_dataout;
	wire	wire_n1l0Oi_dataout;
	wire	wire_n1l0Ol_dataout;
	wire	wire_n1l0OO_dataout;
	wire	wire_n1l10i_dataout;
	wire	wire_n1l10l_dataout;
	wire	wire_n1l10O_dataout;
	wire	wire_n1l11i_dataout;
	wire	wire_n1l11l_dataout;
	wire	wire_n1l11O_dataout;
	wire	wire_n1l1ii_dataout;
	wire	wire_n1l1il_dataout;
	wire	wire_n1l1iO_dataout;
	wire	wire_n1l1li_dataout;
	wire	wire_n1l1ll_dataout;
	wire	wire_n1l1lO_dataout;
	wire	wire_n1l1Oi_dataout;
	wire	wire_n1l1Ol_dataout;
	wire	wire_n1l1OO_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1li0i_dataout;
	wire	wire_n1li0l_dataout;
	wire	wire_n1li0O_dataout;
	wire	wire_n1li1i_dataout;
	wire	wire_n1li1l_dataout;
	wire	wire_n1li1O_dataout;
	wire	wire_n1liii_dataout;
	wire	wire_n1liil_dataout;
	wire	wire_n1liiO_dataout;
	wire	wire_n1lili_dataout;
	wire	wire_n1lill_dataout;
	wire	wire_n1lilO_dataout;
	wire	wire_n1liOi_dataout;
	wire	wire_n1liOl_dataout;
	wire	wire_n1liOO_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1ll0i_dataout;
	wire	wire_n1ll0l_dataout;
	wire	wire_n1ll1i_dataout;
	wire	wire_n1ll1l_dataout;
	wire	wire_n1ll1O_dataout;
	wire	wire_n1llii_dataout;
	wire	wire_n1llil_dataout;
	wire	wire_n1lliO_dataout;
	wire	wire_n1llli_dataout;
	wire	wire_n1llll_dataout;
	wire	wire_n1lllO_dataout;
	wire	wire_n1llOi_dataout;
	wire	wire_n1llOl_dataout;
	wire	wire_n1llOO_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1lO0i_dataout;
	wire	wire_n1lO0l_dataout;
	wire	wire_n1lO0O_dataout;
	wire	wire_n1lO1i_dataout;
	wire	wire_n1lO1l_dataout;
	wire	wire_n1lO1O_dataout;
	wire	wire_n1lOii_dataout;
	wire	wire_n1lOil_dataout;
	wire	wire_n1lOiO_dataout;
	wire	wire_n1lOli_dataout;
	wire	wire_n1lOll_dataout;
	wire	wire_n1lOlO_dataout;
	wire	wire_n1lOOi_dataout;
	wire	wire_n1lOOl_dataout;
	wire	wire_n1lOOO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1O00i_dataout;
	wire	wire_n1O00l_dataout;
	wire	wire_n1O00O_dataout;
	wire	wire_n1O01i_dataout;
	wire	wire_n1O01l_dataout;
	wire	wire_n1O01O_dataout;
	wire	wire_n1O0ii_dataout;
	wire	wire_n1O0il_dataout;
	wire	wire_n1O0iO_dataout;
	wire	wire_n1O0l_dataout;
	wire	wire_n1O0ll_dataout;
	wire	wire_n1O0lO_dataout;
	wire	wire_n1O0O_dataout;
	wire	wire_n1O0Oi_dataout;
	wire	wire_n1O0Ol_dataout;
	wire	wire_n1O0OO_dataout;
	wire	wire_n1O10i_dataout;
	wire	wire_n1O10l_dataout;
	wire	wire_n1O10O_dataout;
	wire	wire_n1O11i_dataout;
	wire	wire_n1O11l_dataout;
	wire	wire_n1O11O_dataout;
	wire	wire_n1O1ii_dataout;
	wire	wire_n1O1il_dataout;
	wire	wire_n1O1iO_dataout;
	wire	wire_n1O1li_dataout;
	wire	wire_n1O1ll_dataout;
	wire	wire_n1O1lO_dataout;
	wire	wire_n1O1Oi_dataout;
	wire	wire_n1O1Ol_dataout;
	wire	wire_n1O1OO_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Oi0i_dataout;
	wire	wire_n1Oi0l_dataout;
	wire	wire_n1Oi0O_dataout;
	wire	wire_n1Oi1i_dataout;
	wire	wire_n1Oi1l_dataout;
	wire	wire_n1Oi1O_dataout;
	wire	wire_n1Oii_dataout;
	wire	wire_n1Oiii_dataout;
	wire	wire_n1Oiil_dataout;
	wire	wire_n1OiiO_dataout;
	wire	wire_n1Oil_dataout;
	wire	wire_n1Oili_dataout;
	wire	wire_n1Oill_dataout;
	wire	wire_n1OilO_dataout;
	wire	wire_n1OiOi_dataout;
	wire	wire_n1OiOl_dataout;
	wire	wire_n1OiOO_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1Ol0i_dataout;
	wire	wire_n1Ol0l_dataout;
	wire	wire_n1Ol0O_dataout;
	wire	wire_n1Ol1i_dataout;
	wire	wire_n1Ol1l_dataout;
	wire	wire_n1Ol1O_dataout;
	wire	wire_n1Olii_dataout;
	wire	wire_n1Olil_dataout;
	wire	wire_n1OliO_dataout;
	wire	wire_n1Oll_dataout;
	wire	wire_n1Olli_dataout;
	wire	wire_n1Olll_dataout;
	wire	wire_n1OllO_dataout;
	wire	wire_n1OlO_dataout;
	wire	wire_n1OlOi_dataout;
	wire	wire_n1OlOl_dataout;
	wire	wire_n1OlOO_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_n1OO0i_dataout;
	wire	wire_n1OO0l_dataout;
	wire	wire_n1OO0O_dataout;
	wire	wire_n1OO1i_dataout;
	wire	wire_n1OO1l_dataout;
	wire	wire_n1OO1O_dataout;
	wire	wire_n1OOi_dataout;
	wire	wire_n1OOii_dataout;
	wire	wire_n1OOil_dataout;
	wire	wire_n1OOiO_dataout;
	wire	wire_n1OOl_dataout;
	wire	wire_n1OOli_dataout;
	wire	wire_n1OOll_dataout;
	wire	wire_n1OOlO_dataout;
	wire	wire_n1OOO_dataout;
	wire	wire_n1OOOi_dataout;
	wire	wire_n1OOOl_dataout;
	wire	wire_n1OOOO_dataout;
	wire	wire_ni000i_dataout;
	wire	wire_ni000l_dataout;
	wire	wire_ni000O_dataout;
	wire	wire_ni001i_dataout;
	wire	wire_ni001l_dataout;
	wire	wire_ni001O_dataout;
	wire	wire_ni00i_dataout;
	wire	wire_ni00ii_dataout;
	wire	wire_ni00il_dataout;
	wire	wire_ni00iO_dataout;
	wire	wire_ni00l_dataout;
	wire	wire_ni00li_dataout;
	wire	wire_ni00ll_dataout;
	wire	wire_ni00lO_dataout;
	wire	wire_ni00O_dataout;
	wire	wire_ni00Oi_dataout;
	wire	wire_ni00Ol_dataout;
	wire	wire_ni00OO_dataout;
	wire	wire_ni010i_dataout;
	wire	wire_ni010l_dataout;
	wire	wire_ni010O_dataout;
	wire	wire_ni011i_dataout;
	wire	wire_ni011l_dataout;
	wire	wire_ni011O_dataout;
	wire	wire_ni01i_dataout;
	wire	wire_ni01ii_dataout;
	wire	wire_ni01il_dataout;
	wire	wire_ni01iO_dataout;
	wire	wire_ni01l_dataout;
	wire	wire_ni01li_dataout;
	wire	wire_ni01ll_dataout;
	wire	wire_ni01lO_dataout;
	wire	wire_ni01O_dataout;
	wire	wire_ni01Oi_dataout;
	wire	wire_ni01Ol_dataout;
	wire	wire_ni01OO_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0i0i_dataout;
	wire	wire_ni0i0l_dataout;
	wire	wire_ni0i0O_dataout;
	wire	wire_ni0i1i_dataout;
	wire	wire_ni0i1l_dataout;
	wire	wire_ni0i1O_dataout;
	wire	wire_ni0ii_dataout;
	wire	wire_ni0iii_dataout;
	wire	wire_ni0iil_dataout;
	wire	wire_ni0iiO_dataout;
	wire	wire_ni0ili_dataout;
	wire	wire_ni0ill_dataout;
	wire	wire_ni0ilO_dataout;
	wire	wire_ni0iO_dataout;
	wire	wire_ni0iOi_dataout;
	wire	wire_ni0iOl_dataout;
	wire	wire_ni0iOO_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0l0i_dataout;
	wire	wire_ni0l0l_dataout;
	wire	wire_ni0l0O_dataout;
	wire	wire_ni0l1i_dataout;
	wire	wire_ni0l1l_dataout;
	wire	wire_ni0l1O_dataout;
	wire	wire_ni0li_dataout;
	wire	wire_ni0lii_dataout;
	wire	wire_ni0lil_dataout;
	wire	wire_ni0liO_dataout;
	wire	wire_ni0ll_dataout;
	wire	wire_ni0lli_dataout;
	wire	wire_ni0lll_dataout;
	wire	wire_ni0llO_dataout;
	wire	wire_ni0lO_dataout;
	wire	wire_ni0lOi_dataout;
	wire	wire_ni0lOl_dataout;
	wire	wire_ni0lOO_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni0O0i_dataout;
	wire	wire_ni0O0l_dataout;
	wire	wire_ni0O0O_dataout;
	wire	wire_ni0O1i_dataout;
	wire	wire_ni0O1l_dataout;
	wire	wire_ni0O1O_dataout;
	wire	wire_ni0Oi_dataout;
	wire	wire_ni0Oii_dataout;
	wire	wire_ni0Oil_dataout;
	wire	wire_ni0OiO_dataout;
	wire	wire_ni0Ol_dataout;
	wire	wire_ni0Oli_dataout;
	wire	wire_ni0Oll_dataout;
	wire	wire_ni0OlO_dataout;
	wire	wire_ni0OO_dataout;
	wire	wire_ni0OOi_dataout;
	wire	wire_ni0OOl_dataout;
	wire	wire_ni0OOO_dataout;
	wire	wire_ni100i_dataout;
	wire	wire_ni100l_dataout;
	wire	wire_ni100O_dataout;
	wire	wire_ni101i_dataout;
	wire	wire_ni101l_dataout;
	wire	wire_ni101O_dataout;
	wire	wire_ni10i_dataout;
	wire	wire_ni10ii_dataout;
	wire	wire_ni10il_dataout;
	wire	wire_ni10iO_dataout;
	wire	wire_ni10l_dataout;
	wire	wire_ni10li_dataout;
	wire	wire_ni10ll_dataout;
	wire	wire_ni10lO_dataout;
	wire	wire_ni10O_dataout;
	wire	wire_ni10Oi_dataout;
	wire	wire_ni10Ol_dataout;
	wire	wire_ni10OO_dataout;
	wire	wire_ni110i_dataout;
	wire	wire_ni110l_dataout;
	wire	wire_ni110O_dataout;
	wire	wire_ni111i_dataout;
	wire	wire_ni111l_dataout;
	wire	wire_ni111O_dataout;
	wire	wire_ni11i_dataout;
	wire	wire_ni11ii_dataout;
	wire	wire_ni11il_dataout;
	wire	wire_ni11iO_dataout;
	wire	wire_ni11l_dataout;
	wire	wire_ni11li_dataout;
	wire	wire_ni11ll_dataout;
	wire	wire_ni11lO_dataout;
	wire	wire_ni11O_dataout;
	wire	wire_ni11Oi_dataout;
	wire	wire_ni11Ol_dataout;
	wire	wire_ni11OO_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1i0i_dataout;
	wire	wire_ni1i0l_dataout;
	wire	wire_ni1i0O_dataout;
	wire	wire_ni1i1i_dataout;
	wire	wire_ni1i1l_dataout;
	wire	wire_ni1i1O_dataout;
	wire	wire_ni1ii_dataout;
	wire	wire_ni1iii_dataout;
	wire	wire_ni1iil_dataout;
	wire	wire_ni1iiO_dataout;
	wire	wire_ni1il_dataout;
	wire	wire_ni1ili_dataout;
	wire	wire_ni1ill_dataout;
	wire	wire_ni1ilO_dataout;
	wire	wire_ni1iOi_dataout;
	wire	wire_ni1iOl_dataout;
	wire	wire_ni1iOO_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1l0i_dataout;
	wire	wire_ni1l0l_dataout;
	wire	wire_ni1l0O_dataout;
	wire	wire_ni1l1i_dataout;
	wire	wire_ni1l1l_dataout;
	wire	wire_ni1l1O_dataout;
	wire	wire_ni1lii_dataout;
	wire	wire_ni1lil_dataout;
	wire	wire_ni1liO_dataout;
	wire	wire_ni1lli_dataout;
	wire	wire_ni1lll_dataout;
	wire	wire_ni1llO_dataout;
	wire	wire_ni1lOi_dataout;
	wire	wire_ni1lOl_dataout;
	wire	wire_ni1lOO_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_ni1O0i_dataout;
	wire	wire_ni1O0l_dataout;
	wire	wire_ni1O0O_dataout;
	wire	wire_ni1O1i_dataout;
	wire	wire_ni1O1l_dataout;
	wire	wire_ni1O1O_dataout;
	wire	wire_ni1Oi_dataout;
	wire	wire_ni1Oii_dataout;
	wire	wire_ni1Oil_dataout;
	wire	wire_ni1OiO_dataout;
	wire	wire_ni1Ol_dataout;
	wire	wire_ni1Oli_dataout;
	wire	wire_ni1Oll_dataout;
	wire	wire_ni1OlO_dataout;
	wire	wire_ni1OO_dataout;
	wire	wire_ni1OOi_dataout;
	wire	wire_ni1OOl_dataout;
	wire	wire_ni1OOO_dataout;
	wire	wire_nii_dataout;
	wire	wire_nii01i_dataout;
	wire	wire_nii01l_dataout;
	wire	wire_nii0i_dataout;
	wire	wire_nii0l_dataout;
	wire	wire_nii0O_dataout;
	wire	wire_nii10i_dataout;
	wire	wire_nii10l_dataout;
	wire	wire_nii10O_dataout;
	wire	wire_nii11i_dataout;
	wire	wire_nii11l_dataout;
	wire	wire_nii11O_dataout;
	wire	wire_nii1i_dataout;
	wire	wire_nii1ii_dataout;
	wire	wire_nii1il_dataout;
	wire	wire_nii1iO_dataout;
	wire	wire_nii1l_dataout;
	wire	wire_nii1li_dataout;
	wire	wire_nii1ll_dataout;
	wire	wire_nii1lO_dataout;
	wire	wire_nii1O_dataout;
	wire	wire_nii1Oi_dataout;
	wire	wire_nii1Ol_dataout;
	wire	wire_nii1OO_dataout;
	wire	wire_niii_dataout;
	wire	wire_niiii_dataout;
	wire	wire_niiil_dataout;
	wire	wire_niiiO_dataout;
	wire	wire_niil_dataout;
	wire	wire_niili_dataout;
	wire	wire_niill_dataout;
	wire	wire_niilO_dataout;
	wire	wire_niiO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nil00i_dataout;
	wire	wire_nil00l_dataout;
	wire	wire_nil00O_dataout;
	wire	wire_nil01i_dataout;
	wire	wire_nil01l_dataout;
	wire	wire_nil01O_dataout;
	wire	wire_nil0i_dataout;
	wire	wire_nil0ii_dataout;
	wire	wire_nil0iO_dataout;
	wire	wire_nil0l_dataout;
	wire	wire_nil0li_dataout;
	wire	wire_nil0ll_dataout;
	wire	wire_nil0lO_dataout;
	wire	wire_nil0O_dataout;
	wire	wire_nil0Oi_dataout;
	wire	wire_nil0Ol_dataout;
	wire	wire_nil0OO_dataout;
	wire	wire_nil1ii_dataout;
	wire	wire_nil1il_dataout;
	wire	wire_nil1iO_dataout;
	wire	wire_nil1l_dataout;
	wire	wire_nil1li_dataout;
	wire	wire_nil1ll_dataout;
	wire	wire_nil1lO_dataout;
	wire	wire_nil1O_dataout;
	wire	wire_nil1Oi_dataout;
	wire	wire_nil1Ol_dataout;
	wire	wire_nil1OO_dataout;
	wire	wire_nili_dataout;
	wire	wire_nili0l_dataout;
	wire	wire_nili0O_dataout;
	wire	wire_nili1i_dataout;
	wire	wire_nili1l_dataout;
	wire	wire_nili1O_dataout;
	wire	wire_nilii_dataout;
	wire	wire_niliii_dataout;
	wire	wire_niliil_dataout;
	wire	wire_niliiO_dataout;
	wire	wire_nilil_dataout;
	wire	wire_nililO_dataout;
	wire	wire_niliO_dataout;
	wire	wire_niliOi_dataout;
	wire	wire_niliOl_dataout;
	wire	wire_niliOO_dataout;
	wire	wire_nill_dataout;
	wire	wire_nill0i_dataout;
	wire	wire_nill0l_dataout;
	wire	wire_nill0O_dataout;
	wire	wire_nill1i_dataout;
	wire	wire_nill1l_dataout;
	wire	wire_nill1O_dataout;
	wire	wire_nilli_dataout;
	wire	wire_nillil_dataout;
	wire	wire_nilliO_dataout;
	wire	wire_nilll_dataout;
	wire	wire_nillli_dataout;
	wire	wire_nillll_dataout;
	wire	wire_nilllO_dataout;
	wire	wire_nillOO_dataout;
	wire	wire_nilO_dataout;
	wire	wire_nilO0i_dataout;
	wire	wire_nilO0l_dataout;
	wire	wire_nilO0O_dataout;
	wire	wire_nilO1i_dataout;
	wire	wire_nilO1l_dataout;
	wire	wire_nilO1O_dataout;
	wire	wire_nilOii_dataout;
	wire	wire_nilOil_dataout;
	wire	wire_nilOiO_dataout;
	wire	wire_nilOli_dataout;
	wire	wire_nilOll_dataout;
	wire	wire_nilOlO_dataout;
	wire	wire_nilOOi_dataout;
	wire	wire_nilOOl_dataout;
	wire	wire_nilOOO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niO00i_dataout;
	wire	wire_niO00l_dataout;
	wire	wire_niO00O_dataout;
	wire	wire_niO01i_dataout;
	wire	wire_niO01l_dataout;
	wire	wire_niO01O_dataout;
	wire	wire_niO0ii_dataout;
	wire	wire_niO0il_dataout;
	wire	wire_niO0iO_dataout;
	wire	wire_niO0li_dataout;
	wire	wire_niO0ll_dataout;
	wire	wire_niO0lO_dataout;
	wire	wire_niO0Oi_dataout;
	wire	wire_niO0Ol_dataout;
	wire	wire_niO0OO_dataout;
	wire	wire_niO10i_dataout;
	wire	wire_niO10l_dataout;
	wire	wire_niO10O_dataout;
	wire	wire_niO11i_dataout;
	wire	wire_niO11l_dataout;
	wire	wire_niO11O_dataout;
	wire	wire_niO1ii_dataout;
	wire	wire_niO1il_dataout;
	wire	wire_niO1iO_dataout;
	wire	wire_niO1li_dataout;
	wire	wire_niO1ll_dataout;
	wire	wire_niO1lO_dataout;
	wire	wire_niO1Oi_dataout;
	wire	wire_niO1Ol_dataout;
	wire	wire_niO1OO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOi0i_dataout;
	wire	wire_niOi0l_dataout;
	wire	wire_niOi0O_dataout;
	wire	wire_niOi1i_dataout;
	wire	wire_niOi1l_dataout;
	wire	wire_niOi1O_dataout;
	wire	wire_niOiii_dataout;
	wire	wire_niOiil_dataout;
	wire	wire_niOiiO_dataout;
	wire	wire_niOili_dataout;
	wire	wire_niOill_dataout;
	wire	wire_niOilO_dataout;
	wire	wire_niOiOi_dataout;
	wire	wire_niOiOl_dataout;
	wire	wire_niOiOO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOl1i_dataout;
	wire	wire_niOl1l_dataout;
	wire	wire_niOl1O_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl000i_dataout;
	wire	wire_nl00il_dataout;
	wire	wire_nl00iO_dataout;
	wire	wire_nl00lO_dataout;
	wire	wire_nl00OO_dataout;
	wire	wire_nl010i_dataout;
	wire	wire_nl010O_dataout;
	wire	wire_nl011i_dataout;
	wire	wire_nl011l_dataout;
	wire	wire_nl011O_dataout;
	wire	wire_nl01ii_dataout;
	wire	wire_nl01il_dataout;
	wire	wire_nl01iO_dataout;
	wire	wire_nl01li_dataout;
	wire	wire_nl01ll_dataout;
	wire	wire_nl01lO_dataout;
	wire	wire_nl01Oi_dataout;
	wire	wire_nl01Ol_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0i0l_dataout;
	wire	wire_nl0i1l_dataout;
	wire	wire_nl0i1O_dataout;
	wire	wire_nl0iiO_dataout;
	wire	wire_nl0ili_dataout;
	wire	wire_nl0iOi_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0l0i_dataout;
	wire	wire_nl0l0O_dataout;
	wire	wire_nl0l1i_dataout;
	wire	wire_nl0l1O_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl0O0l_dataout;
	wire	wire_nl0O1i_dataout;
	wire	wire_nl0Oll_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1iil_dataout;
	wire	wire_nl1iiO_dataout;
	wire	wire_nl1ili_dataout;
	wire	wire_nl1ill_dataout;
	wire	wire_nl1ilO_dataout;
	wire	wire_nl1iOi_dataout;
	wire	wire_nl1iOl_dataout;
	wire	wire_nl1iOO_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1l0i_dataout;
	wire	wire_nl1l0l_dataout;
	wire	wire_nl1l0O_dataout;
	wire	wire_nl1l1i_dataout;
	wire	wire_nl1l1l_dataout;
	wire	wire_nl1l1O_dataout;
	wire	wire_nl1lii_dataout;
	wire	wire_nl1lil_dataout;
	wire	wire_nl1liO_dataout;
	wire	wire_nl1lli_dataout;
	wire	wire_nl1lll_dataout;
	wire	wire_nl1llO_dataout;
	wire	wire_nl1lOi_dataout;
	wire	wire_nl1lOl_dataout;
	wire	wire_nl1lOO_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nl1O0l_dataout;
	wire	wire_nl1O0O_dataout;
	wire	wire_nl1O1i_dataout;
	wire	wire_nl1O1l_dataout;
	wire	wire_nl1O1O_dataout;
	wire	wire_nl1Oii_dataout;
	wire	wire_nl1Oil_dataout;
	wire	wire_nl1OiO_dataout;
	wire	wire_nl1Oli_dataout;
	wire	wire_nl1Oll_dataout;
	wire	wire_nl1OlO_dataout;
	wire	wire_nl1OOi_dataout;
	wire	wire_nl1OOl_dataout;
	wire	wire_nl1OOO_dataout;
	wire	wire_nli_dataout;
	wire	wire_nli01O_dataout;
	wire	wire_nli0ii_dataout;
	wire	wire_nli0ll_dataout;
	wire	wire_nli0lO_dataout;
	wire	wire_nli10Ol_dataout;
	wire	wire_nli10OO_dataout;
	wire	wire_nli11i_dataout;
	wire	wire_nli11l_dataout;
	wire	wire_nli1i0i_dataout;
	wire	wire_nli1i1O_dataout;
	wire	wire_nli1iii_dataout;
	wire	wire_nli1iil_dataout;
	wire	wire_nli1iiO_dataout;
	wire	wire_nli1il_dataout;
	wire	wire_nli1ili_dataout;
	wire	wire_nli1ill_dataout;
	wire	wire_nli1ilO_dataout;
	wire	wire_nli1iOi_dataout;
	wire	wire_nli1iOl_dataout;
	wire	wire_nli1iOO_dataout;
	wire	wire_nli1l0i_dataout;
	wire	wire_nli1l0l_dataout;
	wire	wire_nli1l0O_dataout;
	wire	wire_nli1l1i_dataout;
	wire	wire_nli1l1l_dataout;
	wire	wire_nli1l1O_dataout;
	wire	wire_nli1lii_dataout;
	wire	wire_nli1O0i_dataout;
	wire	wire_nli1O0l_dataout;
	wire	wire_nli1O0O_dataout;
	wire	wire_nli1O1l_dataout;
	wire	wire_nli1O1O_dataout;
	wire	wire_nli1Oii_dataout;
	wire	wire_nli1Oil_dataout;
	wire	wire_nli1OiO_dataout;
	wire	wire_nli1OO_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlii1i_dataout;
	wire	wire_nliiil_dataout;
	wire	wire_nliill_dataout;
	wire	wire_nliiOO_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nlil0i_dataout;
	wire	wire_nlil0l_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nll0l_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nlO0lO_dataout;
	wire	wire_nlO0Oi_dataout;
	wire	wire_nlO0OO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOi0i_dataout;
	wire	wire_nlOi0l_dataout;
	wire	wire_nlOi0O_dataout;
	wire	wire_nlOi1i_dataout;
	wire	wire_nlOiii_dataout;
	wire	wire_nlOiil_dataout;
	wire	wire_nlOiiO_dataout;
	wire	wire_nlOili_dataout;
	wire	wire_nlOill_dataout;
	wire	wire_nlOilO_dataout;
	wire	wire_nlOiOi_dataout;
	wire	wire_nlOiOl_dataout;
	wire	wire_nlOiOO_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOl1i_dataout;
	wire	wire_nlOl1l_dataout;
	wire	wire_nlOlli_dataout;
	wire	wire_nlOlll_dataout;
	wire	wire_nlOllO_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOil_dataout;
	wire	wire_nlOOiO_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOli_dataout;
	wire	wire_nlOOO_dataout;
	wire	wire_nlOOOi_dataout;
	wire  [3:0]   wire_nil0il_o;
	wire  [7:0]   wire_nilill_o;
	wire  [15:0]   wire_nillOl_o;
	wire  [255:0]   wire_nl0lO1O_o;
	wire  [255:0]   wire_nl0lOii_o;
	wire  [63:0]   wire_nl10i_o;
	wire  [63:0]   wire_nll0i_o;
	wire  wire_n1000i_o;
	wire  wire_n1000l_o;
	wire  wire_n1000O_o;
	wire  wire_n1001i_o;
	wire  wire_n1001l_o;
	wire  wire_n1001O_o;
	wire  wire_n100ii_o;
	wire  wire_n100il_o;
	wire  wire_n100iO_o;
	wire  wire_n100li_o;
	wire  wire_n100ll_o;
	wire  wire_n100lO_o;
	wire  wire_n100Oi_o;
	wire  wire_n100Ol_o;
	wire  wire_n100OO_o;
	wire  wire_n101iO_o;
	wire  wire_n101li_o;
	wire  wire_n101ll_o;
	wire  wire_n101lO_o;
	wire  wire_n101Oi_o;
	wire  wire_n101Ol_o;
	wire  wire_n101OO_o;
	wire  wire_n10i0i_o;
	wire  wire_n10i0l_o;
	wire  wire_n10i0O_o;
	wire  wire_n10i1i_o;
	wire  wire_n10i1l_o;
	wire  wire_n10i1O_o;
	wire  wire_n10iii_o;
	wire  wire_n10iil_o;
	wire  wire_n10iiO_o;
	wire  wire_n10ili_o;
	wire  wire_n10ill_o;
	wire  wire_n10ilO_o;
	wire  wire_n10iOi_o;
	wire  wire_n10iOl_o;
	wire  wire_n10iOO_o;
	wire  wire_n10l0i_o;
	wire  wire_n10l0l_o;
	wire  wire_n10l0O_o;
	wire  wire_n10l1i_o;
	wire  wire_n10l1l_o;
	wire  wire_n10l1O_o;
	wire  wire_n10lii_o;
	wire  wire_n10lil_o;
	wire  wire_n10liO_o;
	wire  wire_n10lli_o;
	wire  wire_n10lll_o;
	wire  wire_n10llO_o;
	wire  wire_n10lOi_o;
	wire  wire_n10lOl_o;
	wire  wire_n10lOO_o;
	wire  wire_n10O0i_o;
	wire  wire_n10O0l_o;
	wire  wire_n10O0O_o;
	wire  wire_n10O1i_o;
	wire  wire_n10O1l_o;
	wire  wire_n10O1O_o;
	wire  wire_n10Oii_o;
	wire  wire_n10Oil_o;
	wire  wire_n10OiO_o;
	wire  wire_n10Oli_o;
	wire  wire_n10Oll_o;
	wire  wire_n10OlO_o;
	wire  wire_nii00i_o;
	wire  wire_nii00l_o;
	wire  wire_nii00O_o;
	wire  wire_nii01O_o;
	wire  wire_nii0ii_o;
	wire  wire_nii0il_o;
	wire  wire_nii0iO_o;
	wire  wire_nii0li_o;
	wire  wire_nii0ll_o;
	wire  wire_nii0lO_o;
	wire  wire_nii0Oi_o;
	wire  wire_nii0Ol_o;
	wire  wire_nii0OO_o;
	wire  wire_niii0i_o;
	wire  wire_niii0l_o;
	wire  wire_niii0O_o;
	wire  wire_niii1i_o;
	wire  wire_niii1l_o;
	wire  wire_niii1O_o;
	wire  wire_niiiii_o;
	wire  wire_niiiil_o;
	wire  wire_niiiiO_o;
	wire  wire_niiili_o;
	wire  wire_niiill_o;
	wire  wire_niiilO_o;
	wire  wire_niiiOi_o;
	wire  wire_niiiOl_o;
	wire  wire_niiiOO_o;
	wire  wire_niil0i_o;
	wire  wire_niil0l_o;
	wire  wire_niil0O_o;
	wire  wire_niil1i_o;
	wire  wire_niil1l_o;
	wire  wire_niil1O_o;
	wire  wire_niilii_o;
	wire  wire_niilil_o;
	wire  wire_niiliO_o;
	wire  wire_niilli_o;
	wire  wire_niilll_o;
	wire  wire_niillO_o;
	wire  wire_niilOi_o;
	wire  wire_niilOl_o;
	wire  wire_niilOO_o;
	wire  wire_niiO0i_o;
	wire  wire_niiO0l_o;
	wire  wire_niiO0O_o;
	wire  wire_niiO1i_o;
	wire  wire_niiO1l_o;
	wire  wire_niiO1O_o;
	wire  wire_niiOii_o;
	wire  wire_niiOil_o;
	wire  wire_niiOiO_o;
	wire  wire_niiOli_o;
	wire  wire_niiOll_o;
	wire  wire_niiOlO_o;
	wire  wire_niiOOi_o;
	wire  wire_niiOOl_o;
	wire  wire_niiOOO_o;
	wire  wire_nil10i_o;
	wire  wire_nil10l_o;
	wire  wire_nil10O_o;
	wire  wire_nil11i_o;
	wire  wire_nil11l_o;
	wire  wire_nil11O_o;
	wire  wire_nili0i_o;
	wire  wire_nillii_o;
	wire  wire_niOl0i_o;
	wire  wire_niOl0l_o;
	wire  wire_niOl0O_o;
	wire  wire_niOlii_o;
	wire  wire_niOlil_o;
	wire  wire_niOliO_o;
	wire  wire_niOlli_o;
	wire  wire_niOlll_o;
	wire  wire_niOllO_o;
	wire  wire_niOlOi_o;
	wire  wire_niOlOl_o;
	wire  wire_niOlOO_o;
	wire  wire_niOO0i_o;
	wire  wire_niOO0l_o;
	wire  wire_niOO0O_o;
	wire  wire_niOO1i_o;
	wire  wire_niOO1l_o;
	wire  wire_niOO1O_o;
	wire  wire_niOOii_o;
	wire  wire_niOOil_o;
	wire  wire_niOOiO_o;
	wire  wire_niOOli_o;
	wire  wire_niOOll_o;
	wire  wire_niOOlO_o;
	wire  wire_niOOOi_o;
	wire  wire_niOOOl_o;
	wire  wire_niOOOO_o;
	wire  wire_nl001i_o;
	wire  wire_nl001l_o;
	wire  wire_nl001O_o;
	wire  wire_nl010l_o;
	wire  wire_nl01OO_o;
	wire  wire_nl100i_o;
	wire  wire_nl100l_o;
	wire  wire_nl100O_o;
	wire  wire_nl101i_o;
	wire  wire_nl101l_o;
	wire  wire_nl101O_o;
	wire  wire_nl10ii_o;
	wire  wire_nl10il_o;
	wire  wire_nl10iO_o;
	wire  wire_nl10li_o;
	wire  wire_nl10ll_o;
	wire  wire_nl10lO_o;
	wire  wire_nl10Oi_o;
	wire  wire_nl10Ol_o;
	wire  wire_nl10OO_o;
	wire  wire_nl110i_o;
	wire  wire_nl110l_o;
	wire  wire_nl110O_o;
	wire  wire_nl111i_o;
	wire  wire_nl111l_o;
	wire  wire_nl111O_o;
	wire  wire_nl11ii_o;
	wire  wire_nl11il_o;
	wire  wire_nl11iO_o;
	wire  wire_nl11li_o;
	wire  wire_nl11ll_o;
	wire  wire_nl11lO_o;
	wire  wire_nl11Oi_o;
	wire  wire_nl11Ol_o;
	wire  wire_nl11OO_o;
	wire  wire_nl1i0i_o;
	wire  wire_nl1i0l_o;
	wire  wire_nl1i0O_o;
	wire  wire_nl1i1i_o;
	wire  wire_nl1i1l_o;
	wire  wire_nl1i1O_o;
	wire  wire_nl1iii_o;
	wire  wire_nl1O0i_o;
	wire  wire_niOil_o;
	wire  wire_nliil_o;
	wire  [64:0]   wire_nl0l0OO_data_out;
	wire  [1:0]   wire_nl0l0Ol_byte_des_bo_3g_start;
	wire  [63:0]   wire_nl0l0Ol_byte_des_fifo_data_in;
	wire  nl000ii;
	wire  nl000li;
	wire  nl000ll;
	wire  nl000lO;
	wire  nl000Oi;
	wire  nl00i0i;
	wire  nl00i0l;
	wire  nl00i0O;
	wire  nl00i1i;
	wire  nl00i1l;
	wire  nl00i1O;
	wire  nl00iii;
	wire  nl00iil;
	wire  nl00iiO;
	wire  nl00ili;
	wire  nl00ill;
	wire  nl00ilO;
	wire  nl00iOi;
	wire  nl00iOl;
	wire  nl00iOO;
	wire  nl00l0i;
	wire  nl00l0l;
	wire  nl00l0O;
	wire  nl00l1i;
	wire  nl00l1l;
	wire  nl00l1O;
	wire  nl00lii;
	wire  nl00lil;
	wire  nl00liO;
	wire  nl00lli;
	wire  nl00lll;
	wire  nl00llO;
	wire  nl00lOi;
	wire  nl00lOl;
	wire  nl00lOO;
	wire  nl00O0i;
	wire  nl00O0l;
	wire  nl00O0O;
	wire  nl00O1i;
	wire  nl00O1l;
	wire  nl00O1O;
	wire  nl00Oii;
	wire  nl00Oil;
	wire  nl00OiO;
	wire  nl00Oli;
	wire  nl00Oll;
	wire  nl00OlO;
	wire  nl00OOi;
	wire  nl00OOl;
	wire  nl00OOO;
	wire  nl0i00i;
	wire  nl0i00l;
	wire  nl0i00O;
	wire  nl0i01i;
	wire  nl0i01l;
	wire  nl0i0ii;
	wire  nl0i0il;
	wire  nl0i0iO;
	wire  nl0i0li;
	wire  nl0i0ll;
	wire  nl0i0lO;
	wire  nl0i0Oi;
	wire  nl0i0Ol;
	wire  nl0i0OO;
	wire  nl0i10i;
	wire  nl0i10l;
	wire  nl0i10O;
	wire  nl0i11i;
	wire  nl0i11l;
	wire  nl0i11O;
	wire  nl0i1li;
	wire  nl0i1ll;
	wire  nl0i1lO;
	wire  nl0i1Oi;
	wire  nl0i1Ol;
	wire  nl0i1OO;
	wire  nl0ii0i;
	wire  nl0ii0l;
	wire  nl0ii0O;
	wire  nl0ii1i;
	wire  nl0ii1l;
	wire  nl0ii1O;
	wire  nl0iiii;
	wire  nl0iiil;
	wire  nl0iiiO;
	wire  nl0iili;
	wire  nl0iill;
	wire  nl0iilO;
	wire  nl0iiOi;
	wire  nl0iiOl;
	wire  nl0iiOO;
	wire  nl0il0i;
	wire  nl0il0l;
	wire  nl0il0O;
	wire  nl0il1i;
	wire  nl0il1l;
	wire  nl0il1O;
	wire  nl0ilii;
	wire  nl0ilil;
	wire  nl0iliO;
	wire  nl0illO;
	wire  nl0ilOO;
	wire  nl0iO0O;
	wire  nl0iO1O;
	wire  nl0iOli;
	wire  nl0iOll;
	wire  nl0iOOl;
	wire  nl0iOOO;
	wire  nl0l00O;
	wire  nl0l0iO;
	wire  nl0l11l;
	wire  nl0l11O;
	wire  nl0l1OO;

	initial
		nl0000i61 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0000i61 <= nl0000i62;
	event nl0000i61_event;
	initial
		#1 ->nl0000i61_event;
	always @(nl0000i61_event)
		nl0000i61 <= {1{1'b1}};
	initial
		nl0000i62 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0000i62 <= nl0000i61;
	initial
		nl0000l59 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0000l59 <= nl0000l60;
	event nl0000l59_event;
	initial
		#1 ->nl0000l59_event;
	always @(nl0000l59_event)
		nl0000l59 <= {1{1'b1}};
	initial
		nl0000l60 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0000l60 <= nl0000l59;
	initial
		nl0000O57 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0000O57 <= nl0000O58;
	event nl0000O57_event;
	initial
		#1 ->nl0000O57_event;
	always @(nl0000O57_event)
		nl0000O57 <= {1{1'b1}};
	initial
		nl0000O58 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0000O58 <= nl0000O57;
	initial
		nl000il55 = 0;
	always @ ( posedge rx_wr_clk)
		  nl000il55 <= nl000il56;
	event nl000il55_event;
	initial
		#1 ->nl000il55_event;
	always @(nl000il55_event)
		nl000il55 <= {1{1'b1}};
	initial
		nl000il56 = 0;
	always @ ( posedge rx_wr_clk)
		  nl000il56 <= nl000il55;
	initial
		nl000iO53 = 0;
	always @ ( posedge rx_wr_clk)
		  nl000iO53 <= nl000iO54;
	event nl000iO53_event;
	initial
		#1 ->nl000iO53_event;
	always @(nl000iO53_event)
		nl000iO53 <= {1{1'b1}};
	initial
		nl000iO54 = 0;
	always @ ( posedge rx_wr_clk)
		  nl000iO54 <= nl000iO53;
	initial
		nl000Ol51 = 0;
	always @ ( posedge rx_wr_clk)
		  nl000Ol51 <= nl000Ol52;
	event nl000Ol51_event;
	initial
		#1 ->nl000Ol51_event;
	always @(nl000Ol51_event)
		nl000Ol51 <= {1{1'b1}};
	initial
		nl000Ol52 = 0;
	always @ ( posedge rx_wr_clk)
		  nl000Ol52 <= nl000Ol51;
	initial
		nl000OO49 = 0;
	always @ ( posedge rx_wr_clk)
		  nl000OO49 <= nl000OO50;
	event nl000OO49_event;
	initial
		#1 ->nl000OO49_event;
	always @(nl000OO49_event)
		nl000OO49 <= {1{1'b1}};
	initial
		nl000OO50 = 0;
	always @ ( posedge rx_wr_clk)
		  nl000OO50 <= nl000OO49;
	initial
		nl0i01O41 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0i01O41 <= nl0i01O42;
	event nl0i01O41_event;
	initial
		#1 ->nl0i01O41_event;
	always @(nl0i01O41_event)
		nl0i01O41 <= {1{1'b1}};
	initial
		nl0i01O42 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0i01O42 <= nl0i01O41;
	initial
		nl0i1ii47 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0i1ii47 <= nl0i1ii48;
	event nl0i1ii47_event;
	initial
		#1 ->nl0i1ii47_event;
	always @(nl0i1ii47_event)
		nl0i1ii47 <= {1{1'b1}};
	initial
		nl0i1ii48 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0i1ii48 <= nl0i1ii47;
	initial
		nl0i1il45 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0i1il45 <= nl0i1il46;
	event nl0i1il45_event;
	initial
		#1 ->nl0i1il45_event;
	always @(nl0i1il45_event)
		nl0i1il45 <= {1{1'b1}};
	initial
		nl0i1il46 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0i1il46 <= nl0i1il45;
	initial
		nl0i1iO43 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0i1iO43 <= nl0i1iO44;
	event nl0i1iO43_event;
	initial
		#1 ->nl0i1iO43_event;
	always @(nl0i1iO43_event)
		nl0i1iO43 <= {1{1'b1}};
	initial
		nl0i1iO44 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0i1iO44 <= nl0i1iO43;
	initial
		nl0illi39 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0illi39 <= nl0illi40;
	event nl0illi39_event;
	initial
		#1 ->nl0illi39_event;
	always @(nl0illi39_event)
		nl0illi39 <= {1{1'b1}};
	initial
		nl0illi40 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0illi40 <= nl0illi39;
	initial
		nl0ilOi37 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0ilOi37 <= nl0ilOi38;
	event nl0ilOi37_event;
	initial
		#1 ->nl0ilOi37_event;
	always @(nl0ilOi37_event)
		nl0ilOi37 <= {1{1'b1}};
	initial
		nl0ilOi38 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0ilOi38 <= nl0ilOi37;
	initial
		nl0iO0i33 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iO0i33 <= nl0iO0i34;
	event nl0iO0i33_event;
	initial
		#1 ->nl0iO0i33_event;
	always @(nl0iO0i33_event)
		nl0iO0i33 <= {1{1'b1}};
	initial
		nl0iO0i34 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iO0i34 <= nl0iO0i33;
	initial
		nl0iO1i35 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iO1i35 <= nl0iO1i36;
	event nl0iO1i35_event;
	initial
		#1 ->nl0iO1i35_event;
	always @(nl0iO1i35_event)
		nl0iO1i35 <= {1{1'b1}};
	initial
		nl0iO1i36 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iO1i36 <= nl0iO1i35;
	initial
		nl0iOii31 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iOii31 <= nl0iOii32;
	event nl0iOii31_event;
	initial
		#1 ->nl0iOii31_event;
	always @(nl0iOii31_event)
		nl0iOii31 <= {1{1'b1}};
	initial
		nl0iOii32 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iOii32 <= nl0iOii31;
	initial
		nl0iOil29 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iOil29 <= nl0iOil30;
	event nl0iOil29_event;
	initial
		#1 ->nl0iOil29_event;
	always @(nl0iOil29_event)
		nl0iOil29 <= {1{1'b1}};
	initial
		nl0iOil30 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iOil30 <= nl0iOil29;
	initial
		nl0iOlO27 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iOlO27 <= nl0iOlO28;
	event nl0iOlO27_event;
	initial
		#1 ->nl0iOlO27_event;
	always @(nl0iOlO27_event)
		nl0iOlO27 <= {1{1'b1}};
	initial
		nl0iOlO28 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0iOlO28 <= nl0iOlO27;
	initial
		nl0l00i5 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l00i5 <= nl0l00i6;
	event nl0l00i5_event;
	initial
		#1 ->nl0l00i5_event;
	always @(nl0l00i5_event)
		nl0l00i5 <= {1{1'b1}};
	initial
		nl0l00i6 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l00i6 <= nl0l00i5;
	initial
		nl0l01i11 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l01i11 <= nl0l01i12;
	event nl0l01i11_event;
	initial
		#1 ->nl0l01i11_event;
	always @(nl0l01i11_event)
		nl0l01i11 <= {1{1'b1}};
	initial
		nl0l01i12 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l01i12 <= nl0l01i11;
	initial
		nl0l01l10 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l01l10 <= nl0l01l9;
	initial
		nl0l01l9 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l01l9 <= nl0l01l10;
	event nl0l01l9_event;
	initial
		#1 ->nl0l01l9_event;
	always @(nl0l01l9_event)
		nl0l01l9 <= {1{1'b1}};
	initial
		nl0l01O7 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l01O7 <= nl0l01O8;
	event nl0l01O7_event;
	initial
		#1 ->nl0l01O7_event;
	always @(nl0l01O7_event)
		nl0l01O7 <= {1{1'b1}};
	initial
		nl0l01O8 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l01O8 <= nl0l01O7;
	initial
		nl0l0ii3 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l0ii3 <= nl0l0ii4;
	event nl0l0ii3_event;
	initial
		#1 ->nl0l0ii3_event;
	always @(nl0l0ii3_event)
		nl0l0ii3 <= {1{1'b1}};
	initial
		nl0l0ii4 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l0ii4 <= nl0l0ii3;
	initial
		nl0l0li1 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l0li1 <= nl0l0li2;
	event nl0l0li1_event;
	initial
		#1 ->nl0l0li1_event;
	always @(nl0l0li1_event)
		nl0l0li1 <= {1{1'b1}};
	initial
		nl0l0li2 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l0li2 <= nl0l0li1;
	initial
		nl0l10i23 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l10i23 <= nl0l10i24;
	event nl0l10i23_event;
	initial
		#1 ->nl0l10i23_event;
	always @(nl0l10i23_event)
		nl0l10i23 <= {1{1'b1}};
	initial
		nl0l10i24 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l10i24 <= nl0l10i23;
	initial
		nl0l10O21 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l10O21 <= nl0l10O22;
	event nl0l10O21_event;
	initial
		#1 ->nl0l10O21_event;
	always @(nl0l10O21_event)
		nl0l10O21 <= {1{1'b1}};
	initial
		nl0l10O22 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l10O22 <= nl0l10O21;
	initial
		nl0l11i25 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l11i25 <= nl0l11i26;
	event nl0l11i25_event;
	initial
		#1 ->nl0l11i25_event;
	always @(nl0l11i25_event)
		nl0l11i25 <= {1{1'b1}};
	initial
		nl0l11i26 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l11i26 <= nl0l11i25;
	initial
		nl0l1il19 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l1il19 <= nl0l1il20;
	event nl0l1il19_event;
	initial
		#1 ->nl0l1il19_event;
	always @(nl0l1il19_event)
		nl0l1il19 <= {1{1'b1}};
	initial
		nl0l1il20 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l1il20 <= nl0l1il19;
	initial
		nl0l1iO17 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l1iO17 <= nl0l1iO18;
	event nl0l1iO17_event;
	initial
		#1 ->nl0l1iO17_event;
	always @(nl0l1iO17_event)
		nl0l1iO17 <= {1{1'b1}};
	initial
		nl0l1iO18 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l1iO18 <= nl0l1iO17;
	initial
		nl0l1ll15 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l1ll15 <= nl0l1ll16;
	event nl0l1ll15_event;
	initial
		#1 ->nl0l1ll15_event;
	always @(nl0l1ll15_event)
		nl0l1ll15 <= {1{1'b1}};
	initial
		nl0l1ll16 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l1ll16 <= nl0l1ll15;
	initial
		nl0l1Oi13 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l1Oi13 <= nl0l1Oi14;
	event nl0l1Oi13_event;
	initial
		#1 ->nl0l1Oi13_event;
	always @(nl0l1Oi13_event)
		nl0l1Oi13 <= {1{1'b1}};
	initial
		nl0l1Oi14 = 0;
	always @ ( posedge rx_wr_clk)
		  nl0l1Oi14 <= nl0l1Oi13;
	initial
	begin
		n110i = 0;
		n111i = 0;
	end
	always @ (rx_wr_clk or wire_n111O_PRN or wire_n111O_CLRN)
	begin
		if (wire_n111O_PRN == 1'b0) 
		begin
			n110i <= 1;
			n111i <= 1;
		end
		else if  (wire_n111O_CLRN == 1'b0) 
		begin
			n110i <= 0;
			n111i <= 0;
		end
		else 
		if (rx_wr_clk != n111O_clk_prev && rx_wr_clk == 1'b1) 
		begin
			n110i <= nl0i1li;
			n111i <= n110i;
		end
		n111O_clk_prev <= rx_wr_clk;
	end
	assign
		wire_n111O_CLRN = (nl0i1iO44 ^ nl0i1iO43),
		wire_n111O_PRN = ((nl0i1il46 ^ nl0i1il45) & (~ nl0l0iO));
	initial
	begin
		n11OOl = 0;
	end
	always @ (clk_2 or wire_n11OOi_PRN or wire_n11OOi_CLRN)
	begin
		if (wire_n11OOi_PRN == 1'b0) 
		begin
			n11OOl <= 1;
		end
		else if  (wire_n11OOi_CLRN == 1'b0) 
		begin
			n11OOl <= 0;
		end
		else 
		if (clk_2 != n11OOi_clk_prev && clk_2 == 1'b1) 
		begin
			n11OOl <= wire_n1011i_dataout;
		end
		n11OOi_clk_prev <= clk_2;
	end
	assign
		wire_n11OOi_CLRN = (nl000OO50 ^ nl000OO49),
		wire_n11OOi_PRN = ((nl000Ol52 ^ nl000Ol51) & (~ soft_reset));
	initial
	begin
		n100i = 0;
		n100l = 0;
		n100O = 0;
		n1010O = 0;
		n101i = 0;
		n101l = 0;
		n101O = 0;
		n10ii = 0;
		n10il = 0;
		n10iO = 0;
		n10li = 0;
		n10ll = 0;
		n10lO = 0;
		n10Oi = 0;
		n10Ol = 0;
		n10OO = 0;
		n110l = 0;
		n110O = 0;
		n11ii = 0;
		n11il = 0;
		n11iO = 0;
		n11li = 0;
		n11ll = 0;
		n11lO = 0;
		n11Oi = 0;
		n11Ol = 0;
		n11Oll = 0;
		n11OlO = 0;
		n11OO = 0;
		n1i0i = 0;
		n1i0l = 0;
		n1i0O = 0;
		n1i1i = 0;
		n1i1l = 0;
		n1i1O = 0;
		n1iii = 0;
		n1iil = 0;
		n1iiO = 0;
		n1ili = 0;
		n1ill = 0;
		n1ilO = 0;
		n1iOi = 0;
		n1iOl = 0;
		n1iOO = 0;
		n1l1i = 0;
		n1l1O = 0;
	end
	always @ ( posedge clk_2 or  negedge wire_n1l1l_CLRN)
	begin
		if (wire_n1l1l_CLRN == 1'b0) 
		begin
			n100i <= 0;
			n100l <= 0;
			n100O <= 0;
			n1010O <= 0;
			n101i <= 0;
			n101l <= 0;
			n101O <= 0;
			n10ii <= 0;
			n10il <= 0;
			n10iO <= 0;
			n10li <= 0;
			n10ll <= 0;
			n10lO <= 0;
			n10Oi <= 0;
			n10Ol <= 0;
			n10OO <= 0;
			n110l <= 0;
			n110O <= 0;
			n11ii <= 0;
			n11il <= 0;
			n11iO <= 0;
			n11li <= 0;
			n11ll <= 0;
			n11lO <= 0;
			n11Oi <= 0;
			n11Ol <= 0;
			n11Oll <= 0;
			n11OlO <= 0;
			n11OO <= 0;
			n1i0i <= 0;
			n1i0l <= 0;
			n1i0O <= 0;
			n1i1i <= 0;
			n1i1l <= 0;
			n1i1O <= 0;
			n1iii <= 0;
			n1iil <= 0;
			n1iiO <= 0;
			n1ili <= 0;
			n1ill <= 0;
			n1ilO <= 0;
			n1iOi <= 0;
			n1iOl <= 0;
			n1iOO <= 0;
			n1l1i <= 0;
			n1l1O <= 0;
		end
		else 
		begin
			n100i <= nl0il1O;
			n100l <= nl0iiii;
			n100O <= nl0iill;
			n1010O <= wire_n1010i_dataout;
			n101i <= (((((nl0i1Oi | nl0i1lO) & rsync_comp_porn) & (nl0ilil | nl0iliO)) | nl0i1ll) & n101l);
			n101l <= nl0iiOO;
			n101O <= (((((nl0i01i | nl0i1OO) & rsync_comp_porn) & (nl0iOli | nl0l00O)) | nl0i1Ol) & n100i);
			n10ii <= nl0iiOO;
			n10il <= nl0il1O;
			n10iO <= n10ll;
			n10li <= n10lO;
			n10ll <= wire_nliil_o;
			n10lO <= wire_niOil_o;
			n10Oi <= (n10OO & nl0l00O);
			n10Ol <= (n1i1i & nl0iiOi);
			n10OO <= (n1i1l & nl0iOll);
			n110l <= dec_data_valid[0];
			n110O <= dec_data_valid[1];
			n11ii <= wire_n1O0l_dataout;
			n11il <= n11lO;
			n11iO <= n11Oi;
			n11li <= n11Ol;
			n11ll <= n11OO;
			n11lO <= ovr_undflow[0];
			n11Oi <= ovr_undflow[1];
			n11Ol <= ovr_undflow[2];
			n11Oll <= n11OlO;
			n11OlO <= nl0i01l;
			n11OO <= ovr_undflow[3];
			n1i0i <= n1i0O;
			n1i0l <= n1iii;
			n1i0O <= disp_val_delay[0];
			n1i1i <= (n1i1O & nl0il0i);
			n1i1l <= nl0iOll;
			n1i1O <= nl0il0i;
			n1iii <= disp_val_delay[1];
			n1iil <= n1ili;
			n1iiO <= n1ill;
			n1ili <= disp_err_delay[0];
			n1ill <= disp_err_delay[1];
			n1ilO <= n1iOl;
			n1iOi <= n1iOO;
			n1iOl <= sync_resync_delay[0];
			n1iOO <= sync_resync_delay[1];
			n1l1i <= signal_detect_sync_st;
			n1l1O <= n1l1i;
		end
	end
	assign
		wire_n1l1l_CLRN = ((nl0i01O42 ^ nl0i01O41) & (~ soft_reset));
	initial
	begin
		nl0OlOi = 0;
	end
	always @ (rx_rd_clk or wire_nl0OllO_PRN or wire_nl0OllO_CLRN)
	begin
		if (wire_nl0OllO_PRN == 1'b0) 
		begin
			nl0OlOi <= 1;
		end
		else if  (wire_nl0OllO_CLRN == 1'b0) 
		begin
			nl0OlOi <= 0;
		end
		else if  (wire_nl0OllO_ENA == 1'b1) 
		if (rx_rd_clk != nl0OllO_clk_prev && rx_rd_clk == 1'b1) 
		begin
			nl0OlOi <= nl0i1li;
		end
		nl0OllO_clk_prev <= rx_rd_clk;
	end
	assign
		wire_nl0OllO_ENA = (nlO0ll & nl0OlOi),
		wire_nl0OllO_CLRN = (nl0000l60 ^ nl0000l59),
		wire_nl0OllO_PRN = ((nl0000i62 ^ nl0000i61) & (~ wire_nlOOOi_dataout));
	initial
	begin
		nl0OO0l = 0;
		nl0OOOi = 0;
		nli101i = 0;
		nli10li = 0;
		nli11ii = 0;
	end
	always @ ( posedge rx_rd_clk or  negedge wire_nli10iO_PRN)
	begin
		if (wire_nli10iO_PRN == 1'b0) 
		begin
			nl0OO0l <= 1;
			nl0OOOi <= 1;
			nli101i <= 1;
			nli10li <= 1;
			nli11ii <= 1;
		end
		else 
		begin
			nl0OO0l <= nl0OOOi;
			nl0OOOi <= nli110O;
			nli101i <= nli10li;
			nli10li <= wire_nl0lOii_o[2];
			nli11ii <= wire_nli1ilO_dataout;
		end
	end
	assign
		wire_nli10iO_PRN = ((nl0000O58 ^ nl0000O57) & (~ wire_nlOOOi_dataout));
	initial
	begin
		nli10Oi = 0;
	end
	always @ (rx_wr_clk or wire_nli10lO_PRN or wire_nli10lO_CLRN)
	begin
		if (wire_nli10lO_PRN == 1'b0) 
		begin
			nli10Oi <= 1;
		end
		else if  (wire_nli10lO_CLRN == 1'b0) 
		begin
			nli10Oi <= 0;
		end
		else 
		if (rx_wr_clk != nli10lO_clk_prev && rx_wr_clk == 1'b1) 
		begin
			nli10Oi <= wire_nli1O1l_dataout;
		end
		nli10lO_clk_prev <= rx_wr_clk;
	end
	assign
		wire_nli10lO_CLRN = (nl000iO54 ^ nl000iO53),
		wire_nli10lO_PRN = ((nl000il56 ^ nl000il55) & (~ wire_n111l_dataout));
	initial
	begin
		nl0llOi = 0;
		nl0lOil = 0;
		nl0lOiO = 0;
		nl0lOli = 0;
		nl0lOll = 0;
		nl0lOlO = 0;
		nl0lOOi = 0;
		nl0lOOl = 0;
		nl0lOOO = 0;
		nl0O00i = 0;
		nl0O00l = 0;
		nl0O00O = 0;
		nl0O01i = 0;
		nl0O01l = 0;
		nl0O01O = 0;
		nl0O0ii = 0;
		nl0O0il = 0;
		nl0O0iO = 0;
		nl0O0li = 0;
		nl0O0ll = 0;
		nl0O0lO = 0;
		nl0O0Oi = 0;
		nl0O0Ol = 0;
		nl0O0OO = 0;
		nl0O10i = 0;
		nl0O10l = 0;
		nl0O10O = 0;
		nl0O11i = 0;
		nl0O11l = 0;
		nl0O11O = 0;
		nl0O1ii = 0;
		nl0O1il = 0;
		nl0O1iO = 0;
		nl0O1li = 0;
		nl0O1ll = 0;
		nl0O1lO = 0;
		nl0O1Oi = 0;
		nl0O1Ol = 0;
		nl0O1OO = 0;
		nl0Oi0i = 0;
		nl0Oi0l = 0;
		nl0Oi0O = 0;
		nl0Oi1i = 0;
		nl0Oi1l = 0;
		nl0Oi1O = 0;
		nl0Oiii = 0;
		nl0Oiil = 0;
		nl0OiiO = 0;
		nl0Oili = 0;
		nl0Oill = 0;
		nl0OilO = 0;
		nl0OiOi = 0;
		nl0OiOl = 0;
		nl0OiOO = 0;
		nl0Ol0i = 0;
		nl0Ol0l = 0;
		nl0Ol0O = 0;
		nl0Ol1i = 0;
		nl0Ol1l = 0;
		nl0Ol1O = 0;
		nl0Olii = 0;
		nl0Olil = 0;
		nl0OliO = 0;
		nl0Olli = 0;
		nl0Olll = 0;
		nl0OlOl = 0;
		nl0OlOO = 0;
		nl0OO0i = 0;
		nl0OO0O = 0;
		nl0OO1i = 0;
		nl0OO1l = 0;
		nl0OO1O = 0;
		nl0OOii = 0;
		nl0OOil = 0;
		nl0OOiO = 0;
		nl0OOli = 0;
		nl0OOll = 0;
		nl0OOlO = 0;
		nl0OOOl = 0;
		nl0OOOO = 0;
		nli100i = 0;
		nli100l = 0;
		nli100O = 0;
		nli101l = 0;
		nli101O = 0;
		nli10ii = 0;
		nli10il = 0;
		nli10ll = 0;
		nli110i = 0;
		nli110l = 0;
		nli110O = 0;
		nli111i = 0;
		nli111l = 0;
		nli111O = 0;
		nli11il = 0;
		nli11iO = 0;
		nli11li = 0;
		nli11ll = 0;
		nli11lO = 0;
		nli11Oi = 0;
		nli11Ol = 0;
		nli11OO = 0;
		nlO0ll = 0;
		nlOl0l = 0;
		nlOl0O = 0;
		nlOlil = 0;
	end
	always @ ( posedge rx_rd_clk or  posedge wire_nlOOOi_dataout)
	begin
		if (wire_nlOOOi_dataout == 1'b1) 
		begin
			nl0llOi <= 0;
			nl0lOil <= 0;
			nl0lOiO <= 0;
			nl0lOli <= 0;
			nl0lOll <= 0;
			nl0lOlO <= 0;
			nl0lOOi <= 0;
			nl0lOOl <= 0;
			nl0lOOO <= 0;
			nl0O00i <= 0;
			nl0O00l <= 0;
			nl0O00O <= 0;
			nl0O01i <= 0;
			nl0O01l <= 0;
			nl0O01O <= 0;
			nl0O0ii <= 0;
			nl0O0il <= 0;
			nl0O0iO <= 0;
			nl0O0li <= 0;
			nl0O0ll <= 0;
			nl0O0lO <= 0;
			nl0O0Oi <= 0;
			nl0O0Ol <= 0;
			nl0O0OO <= 0;
			nl0O10i <= 0;
			nl0O10l <= 0;
			nl0O10O <= 0;
			nl0O11i <= 0;
			nl0O11l <= 0;
			nl0O11O <= 0;
			nl0O1ii <= 0;
			nl0O1il <= 0;
			nl0O1iO <= 0;
			nl0O1li <= 0;
			nl0O1ll <= 0;
			nl0O1lO <= 0;
			nl0O1Oi <= 0;
			nl0O1Ol <= 0;
			nl0O1OO <= 0;
			nl0Oi0i <= 0;
			nl0Oi0l <= 0;
			nl0Oi0O <= 0;
			nl0Oi1i <= 0;
			nl0Oi1l <= 0;
			nl0Oi1O <= 0;
			nl0Oiii <= 0;
			nl0Oiil <= 0;
			nl0OiiO <= 0;
			nl0Oili <= 0;
			nl0Oill <= 0;
			nl0OilO <= 0;
			nl0OiOi <= 0;
			nl0OiOl <= 0;
			nl0OiOO <= 0;
			nl0Ol0i <= 0;
			nl0Ol0l <= 0;
			nl0Ol0O <= 0;
			nl0Ol1i <= 0;
			nl0Ol1l <= 0;
			nl0Ol1O <= 0;
			nl0Olii <= 0;
			nl0Olil <= 0;
			nl0OliO <= 0;
			nl0Olli <= 0;
			nl0Olll <= 0;
			nl0OlOl <= 0;
			nl0OlOO <= 0;
			nl0OO0i <= 0;
			nl0OO0O <= 0;
			nl0OO1i <= 0;
			nl0OO1l <= 0;
			nl0OO1O <= 0;
			nl0OOii <= 0;
			nl0OOil <= 0;
			nl0OOiO <= 0;
			nl0OOli <= 0;
			nl0OOll <= 0;
			nl0OOlO <= 0;
			nl0OOOl <= 0;
			nl0OOOO <= 0;
			nli100i <= 0;
			nli100l <= 0;
			nli100O <= 0;
			nli101l <= 0;
			nli101O <= 0;
			nli10ii <= 0;
			nli10il <= 0;
			nli10ll <= 0;
			nli110i <= 0;
			nli110l <= 0;
			nli110O <= 0;
			nli111i <= 0;
			nli111l <= 0;
			nli111O <= 0;
			nli11il <= 0;
			nli11iO <= 0;
			nli11li <= 0;
			nli11ll <= 0;
			nli11lO <= 0;
			nli11Oi <= 0;
			nli11Ol <= 0;
			nli11OO <= 0;
			nlO0ll <= 0;
			nlOl0l <= 0;
			nlOl0O <= 0;
			nlOlil <= 0;
		end
		else 
		begin
			nl0llOi <= wire_nl0l0OO_data_out[0];
			nl0lOil <= wire_nl0l0OO_data_out[1];
			nl0lOiO <= wire_nl0l0OO_data_out[2];
			nl0lOli <= wire_nl0l0OO_data_out[3];
			nl0lOll <= wire_nl0l0OO_data_out[4];
			nl0lOlO <= wire_nl0l0OO_data_out[5];
			nl0lOOi <= wire_nl0l0OO_data_out[6];
			nl0lOOl <= wire_nl0l0OO_data_out[7];
			nl0lOOO <= wire_nl0l0OO_data_out[8];
			nl0O00i <= wire_nl0l0OO_data_out[27];
			nl0O00l <= wire_nl0l0OO_data_out[28];
			nl0O00O <= wire_nl0l0OO_data_out[29];
			nl0O01i <= wire_nl0l0OO_data_out[24];
			nl0O01l <= wire_nl0l0OO_data_out[25];
			nl0O01O <= wire_nl0l0OO_data_out[26];
			nl0O0ii <= wire_nl0l0OO_data_out[30];
			nl0O0il <= wire_nl0l0OO_data_out[31];
			nl0O0iO <= wire_nl0l0OO_data_out[32];
			nl0O0li <= wire_nl0l0OO_data_out[33];
			nl0O0ll <= wire_nl0l0OO_data_out[34];
			nl0O0lO <= wire_nl0l0OO_data_out[35];
			nl0O0Oi <= wire_nl0l0OO_data_out[36];
			nl0O0Ol <= wire_nl0l0OO_data_out[37];
			nl0O0OO <= wire_nl0l0OO_data_out[38];
			nl0O10i <= wire_nl0l0OO_data_out[12];
			nl0O10l <= wire_nl0l0OO_data_out[13];
			nl0O10O <= wire_nl0l0OO_data_out[14];
			nl0O11i <= wire_nl0l0OO_data_out[9];
			nl0O11l <= wire_nl0l0OO_data_out[10];
			nl0O11O <= wire_nl0l0OO_data_out[11];
			nl0O1ii <= wire_nl0l0OO_data_out[15];
			nl0O1il <= wire_nl0l0OO_data_out[16];
			nl0O1iO <= wire_nl0l0OO_data_out[17];
			nl0O1li <= wire_nl0l0OO_data_out[18];
			nl0O1ll <= wire_nl0l0OO_data_out[19];
			nl0O1lO <= wire_nl0l0OO_data_out[20];
			nl0O1Oi <= wire_nl0l0OO_data_out[21];
			nl0O1Ol <= wire_nl0l0OO_data_out[22];
			nl0O1OO <= wire_nl0l0OO_data_out[23];
			nl0Oi0i <= wire_nl0l0OO_data_out[42];
			nl0Oi0l <= wire_nl0l0OO_data_out[43];
			nl0Oi0O <= wire_nl0l0OO_data_out[44];
			nl0Oi1i <= wire_nl0l0OO_data_out[39];
			nl0Oi1l <= wire_nl0l0OO_data_out[40];
			nl0Oi1O <= wire_nl0l0OO_data_out[41];
			nl0Oiii <= wire_nl0l0OO_data_out[45];
			nl0Oiil <= wire_nl0l0OO_data_out[46];
			nl0OiiO <= wire_nl0l0OO_data_out[47];
			nl0Oili <= wire_nl0l0OO_data_out[48];
			nl0Oill <= wire_nl0l0OO_data_out[49];
			nl0OilO <= wire_nl0l0OO_data_out[50];
			nl0OiOi <= wire_nl0l0OO_data_out[51];
			nl0OiOl <= wire_nl0l0OO_data_out[52];
			nl0OiOO <= wire_nl0l0OO_data_out[53];
			nl0Ol0i <= wire_nl0l0OO_data_out[57];
			nl0Ol0l <= wire_nl0l0OO_data_out[58];
			nl0Ol0O <= wire_nl0l0OO_data_out[59];
			nl0Ol1i <= wire_nl0l0OO_data_out[54];
			nl0Ol1l <= wire_nl0l0OO_data_out[55];
			nl0Ol1O <= wire_nl0l0OO_data_out[56];
			nl0Olii <= wire_nl0l0OO_data_out[60];
			nl0Olil <= wire_nl0l0OO_data_out[61];
			nl0OliO <= wire_nl0l0OO_data_out[62];
			nl0Olli <= wire_nl0l0OO_data_out[63];
			nl0Olll <= wire_nl0l0OO_data_out[64];
			nl0OlOl <= wire_nli10Ol_dataout;
			nl0OlOO <= wire_nli1i1O_dataout;
			nl0OO0i <= nl0OOlO;
			nl0OO0O <= nl0OOOl;
			nl0OO1i <= nl0OOiO;
			nl0OO1l <= nl0OOli;
			nl0OO1O <= nl0OOll;
			nl0OOii <= nl0OOOO;
			nl0OOil <= nli111i;
			nl0OOiO <= nli111l;
			nl0OOli <= nli111O;
			nl0OOll <= nli110i;
			nl0OOlO <= nli110l;
			nl0OOOl <= nli11ii;
			nl0OOOO <= nli11il;
			nli100i <= wire_nl0lOii_o[16];
			nli100l <= wire_nl0lOii_o[64];
			nli100O <= wire_nl0lOii_o[128];
			nli101l <= nli10ll;
			nli101O <= wire_nl0lOii_o[32];
			nli10ii <= wire_nl0lOii_o[4];
			nli10il <= wire_nl0lOii_o[8];
			nli10ll <= (~ nl000ii);
			nli110i <= wire_nli1iiO_dataout;
			nli110l <= wire_nli1ili_dataout;
			nli110O <= wire_nli1ill_dataout;
			nli111i <= nli11iO;
			nli111l <= wire_nli1iii_dataout;
			nli111O <= wire_nli1iil_dataout;
			nli11il <= wire_nli1iOi_dataout;
			nli11iO <= wire_nli1iOl_dataout;
			nli11li <= nli101O;
			nli11ll <= nli100i;
			nli11lO <= nli100l;
			nli11Oi <= nli100O;
			nli11Ol <= nli10ii;
			nli11OO <= nli10il;
			nlO0ll <= wire_nlOlli_dataout;
			nlOl0l <= wire_nlOllO_dataout;
			nlOl0O <= nlOlil;
			nlOlil <= nl0i01l;
		end
	end
	initial
	begin
		n11OOO = 0;
		nli1lli = 0;
		nli1lll = 0;
		nli1llO = 0;
		nli1lOi = 0;
		nli1lOl = 0;
		nli1lOO = 0;
		nli1O1i = 0;
		nliliO = 0;
		nlilli = 0;
		nlilll = 0;
		nlillO = 0;
		nlilOi = 0;
		nlilOl = 0;
		nlilOO = 0;
		nliO0i = 0;
		nliO0l = 0;
		nliO0O = 0;
		nliO1i = 0;
		nliO1l = 0;
		nliO1O = 0;
		nliOii = 0;
		nliOil = 0;
		nliOiO = 0;
		nliOli = 0;
		nliOll = 0;
		nliOlO = 0;
		nliOOi = 0;
		nliOOl = 0;
		nliOOO = 0;
		nll00i = 0;
		nll00l = 0;
		nll00O = 0;
		nll01i = 0;
		nll01l = 0;
		nll01O = 0;
		nll0ii = 0;
		nll0il = 0;
		nll0iO = 0;
		nll0li = 0;
		nll0ll = 0;
		nll0lO = 0;
		nll0Oi = 0;
		nll0Ol = 0;
		nll0OO = 0;
		nll10i = 0;
		nll10l = 0;
		nll10O = 0;
		nll11i = 0;
		nll11l = 0;
		nll11O = 0;
		nll1ii = 0;
		nll1il = 0;
		nll1iO = 0;
		nll1li = 0;
		nll1ll = 0;
		nll1lO = 0;
		nll1Oi = 0;
		nll1Ol = 0;
		nll1OO = 0;
		nlli0i = 0;
		nlli0l = 0;
		nlli0O = 0;
		nlli1i = 0;
		nlli1l = 0;
		nlli1O = 0;
		nlliii = 0;
		nlliil = 0;
		nlliiO = 0;
		nllili = 0;
		nllill = 0;
		nllilO = 0;
		nlliOi = 0;
		nlliOl = 0;
		nlliOO = 0;
		nlll0i = 0;
		nlll0l = 0;
		nlll0O = 0;
		nlll1i = 0;
		nlll1l = 0;
		nlll1O = 0;
		nlllii = 0;
		nlllil = 0;
		nllliO = 0;
		nlllli = 0;
		nlllll = 0;
		nllllO = 0;
		nlllOi = 0;
		nlllOl = 0;
		nlllOO = 0;
		nllO0i = 0;
		nllO0l = 0;
		nllO0O = 0;
		nllO1i = 0;
		nllO1l = 0;
		nllO1O = 0;
		nllOii = 0;
		nllOil = 0;
		nllOiO = 0;
		nllOli = 0;
		nllOll = 0;
		nllOlO = 0;
		nllOOi = 0;
		nllOOl = 0;
		nllOOO = 0;
		nlO00i = 0;
		nlO00l = 0;
		nlO00O = 0;
		nlO01i = 0;
		nlO01l = 0;
		nlO01O = 0;
		nlO0ii = 0;
		nlO0il = 0;
		nlO0iO = 0;
		nlO0li = 0;
		nlO10i = 0;
		nlO10l = 0;
		nlO10O = 0;
		nlO11i = 0;
		nlO11l = 0;
		nlO11O = 0;
		nlO1ii = 0;
		nlO1il = 0;
		nlO1iO = 0;
		nlO1li = 0;
		nlO1ll = 0;
		nlO1lO = 0;
		nlO1Oi = 0;
		nlO1Ol = 0;
		nlO1OO = 0;
		nlOliO = 0;
		nlOlOl = 0;
		nlOlOO = 0;
		nlOO0i = 0;
		nlOO0O = 0;
		nlOO1i = 0;
		nlOO1l = 0;
		nlOO1O = 0;
	end
	always @ ( posedge rx_wr_clk or  posedge wire_n111l_dataout)
	begin
		if (wire_n111l_dataout == 1'b1) 
		begin
			n11OOO <= 0;
			nli1lli <= 0;
			nli1lll <= 0;
			nli1llO <= 0;
			nli1lOi <= 0;
			nli1lOl <= 0;
			nli1lOO <= 0;
			nli1O1i <= 0;
			nliliO <= 0;
			nlilli <= 0;
			nlilll <= 0;
			nlillO <= 0;
			nlilOi <= 0;
			nlilOl <= 0;
			nlilOO <= 0;
			nliO0i <= 0;
			nliO0l <= 0;
			nliO0O <= 0;
			nliO1i <= 0;
			nliO1l <= 0;
			nliO1O <= 0;
			nliOii <= 0;
			nliOil <= 0;
			nliOiO <= 0;
			nliOli <= 0;
			nliOll <= 0;
			nliOlO <= 0;
			nliOOi <= 0;
			nliOOl <= 0;
			nliOOO <= 0;
			nll00i <= 0;
			nll00l <= 0;
			nll00O <= 0;
			nll01i <= 0;
			nll01l <= 0;
			nll01O <= 0;
			nll0ii <= 0;
			nll0il <= 0;
			nll0iO <= 0;
			nll0li <= 0;
			nll0ll <= 0;
			nll0lO <= 0;
			nll0Oi <= 0;
			nll0Ol <= 0;
			nll0OO <= 0;
			nll10i <= 0;
			nll10l <= 0;
			nll10O <= 0;
			nll11i <= 0;
			nll11l <= 0;
			nll11O <= 0;
			nll1ii <= 0;
			nll1il <= 0;
			nll1iO <= 0;
			nll1li <= 0;
			nll1ll <= 0;
			nll1lO <= 0;
			nll1Oi <= 0;
			nll1Ol <= 0;
			nll1OO <= 0;
			nlli0i <= 0;
			nlli0l <= 0;
			nlli0O <= 0;
			nlli1i <= 0;
			nlli1l <= 0;
			nlli1O <= 0;
			nlliii <= 0;
			nlliil <= 0;
			nlliiO <= 0;
			nllili <= 0;
			nllill <= 0;
			nllilO <= 0;
			nlliOi <= 0;
			nlliOl <= 0;
			nlliOO <= 0;
			nlll0i <= 0;
			nlll0l <= 0;
			nlll0O <= 0;
			nlll1i <= 0;
			nlll1l <= 0;
			nlll1O <= 0;
			nlllii <= 0;
			nlllil <= 0;
			nllliO <= 0;
			nlllli <= 0;
			nlllll <= 0;
			nllllO <= 0;
			nlllOi <= 0;
			nlllOl <= 0;
			nlllOO <= 0;
			nllO0i <= 0;
			nllO0l <= 0;
			nllO0O <= 0;
			nllO1i <= 0;
			nllO1l <= 0;
			nllO1O <= 0;
			nllOii <= 0;
			nllOil <= 0;
			nllOiO <= 0;
			nllOli <= 0;
			nllOll <= 0;
			nllOlO <= 0;
			nllOOi <= 0;
			nllOOl <= 0;
			nllOOO <= 0;
			nlO00i <= 0;
			nlO00l <= 0;
			nlO00O <= 0;
			nlO01i <= 0;
			nlO01l <= 0;
			nlO01O <= 0;
			nlO0ii <= 0;
			nlO0il <= 0;
			nlO0iO <= 0;
			nlO0li <= 0;
			nlO10i <= 0;
			nlO10l <= 0;
			nlO10O <= 0;
			nlO11i <= 0;
			nlO11l <= 0;
			nlO11O <= 0;
			nlO1ii <= 0;
			nlO1il <= 0;
			nlO1iO <= 0;
			nlO1li <= 0;
			nlO1ll <= 0;
			nlO1lO <= 0;
			nlO1Oi <= 0;
			nlO1Ol <= 0;
			nlO1OO <= 0;
			nlOliO <= 0;
			nlOlOl <= 0;
			nlOlOO <= 0;
			nlOO0i <= 0;
			nlOO0O <= 0;
			nlOO1i <= 0;
			nlOO1l <= 0;
			nlOO1O <= 0;
		end
		else 
		begin
			n11OOO <= wire_nlOi0i_dataout;
			nli1lli <= wire_nli1O1O_dataout;
			nli1lll <= wire_nli1O0i_dataout;
			nli1llO <= wire_nli1O0l_dataout;
			nli1lOi <= wire_nli1O0O_dataout;
			nli1lOl <= wire_nli1Oii_dataout;
			nli1lOO <= wire_nli1Oil_dataout;
			nli1O1i <= wire_nli1OiO_dataout;
			nliliO <= wire_nlOi0l_dataout;
			nlilli <= wire_nlOi0O_dataout;
			nlilll <= wire_nlOiii_dataout;
			nlillO <= wire_nlO0lO_dataout;
			nlilOi <= nlll1l;
			nlilOl <= nlll1O;
			nlilOO <= nlll0i;
			nliO0i <= nlllil;
			nliO0l <= nllliO;
			nliO0O <= nlllli;
			nliO1i <= nlll0l;
			nliO1l <= nlll0O;
			nliO1O <= nlllii;
			nliOii <= nlllll;
			nliOil <= nllllO;
			nliOiO <= nlllOi;
			nliOli <= nlllOl;
			nliOll <= nlllOO;
			nliOlO <= nllO1i;
			nliOOi <= nllO1l;
			nliOOl <= nllO1O;
			nliOOO <= nllO0i;
			nll00i <= nlO1il;
			nll00l <= nlO1iO;
			nll00O <= nlO1li;
			nll01i <= nlO10l;
			nll01l <= nlO10O;
			nll01O <= nlO1ii;
			nll0ii <= nlO1ll;
			nll0il <= nlO1lO;
			nll0iO <= nlO1Oi;
			nll0li <= nlO1Ol;
			nll0ll <= nlO1OO;
			nll0lO <= nlO01i;
			nll0Oi <= nlO01l;
			nll0Ol <= nlO01O;
			nll0OO <= nlO00i;
			nll10i <= nllOil;
			nll10l <= nllOiO;
			nll10O <= nllOli;
			nll11i <= nllO0l;
			nll11l <= nllO0O;
			nll11O <= nllOii;
			nll1ii <= nllOll;
			nll1il <= nllOlO;
			nll1iO <= nllOOi;
			nll1li <= nllOOl;
			nll1ll <= nllOOO;
			nll1lO <= nlO11i;
			nll1Oi <= nlO11l;
			nll1Ol <= nlO11O;
			nll1OO <= nlO10i;
			nlli0i <= wire_nl0l0Ol_byte_des_fifo_data_in[3];
			nlli0l <= wire_nl0l0Ol_byte_des_fifo_data_in[4];
			nlli0O <= wire_nl0l0Ol_byte_des_fifo_data_in[5];
			nlli1i <= wire_nl0l0Ol_byte_des_fifo_data_in[0];
			nlli1l <= wire_nl0l0Ol_byte_des_fifo_data_in[1];
			nlli1O <= wire_nl0l0Ol_byte_des_fifo_data_in[2];
			nlliii <= wire_nl0l0Ol_byte_des_fifo_data_in[6];
			nlliil <= wire_nl0l0Ol_byte_des_fifo_data_in[7];
			nlliiO <= wire_nl0l0Ol_byte_des_fifo_data_in[8];
			nllili <= wire_nl0l0Ol_byte_des_fifo_data_in[9];
			nllill <= wire_nl0l0Ol_byte_des_fifo_data_in[10];
			nllilO <= wire_nl0l0Ol_byte_des_fifo_data_in[11];
			nlliOi <= wire_nl0l0Ol_byte_des_fifo_data_in[12];
			nlliOl <= wire_nl0l0Ol_byte_des_fifo_data_in[13];
			nlliOO <= wire_nl0l0Ol_byte_des_fifo_data_in[14];
			nlll0i <= wire_nl0l0Ol_byte_des_fifo_data_in[18];
			nlll0l <= wire_nl0l0Ol_byte_des_fifo_data_in[19];
			nlll0O <= wire_nl0l0Ol_byte_des_fifo_data_in[20];
			nlll1i <= wire_nl0l0Ol_byte_des_fifo_data_in[15];
			nlll1l <= wire_nl0l0Ol_byte_des_fifo_data_in[16];
			nlll1O <= wire_nl0l0Ol_byte_des_fifo_data_in[17];
			nlllii <= wire_nl0l0Ol_byte_des_fifo_data_in[21];
			nlllil <= wire_nl0l0Ol_byte_des_fifo_data_in[22];
			nllliO <= wire_nl0l0Ol_byte_des_fifo_data_in[23];
			nlllli <= wire_nl0l0Ol_byte_des_fifo_data_in[24];
			nlllll <= wire_nl0l0Ol_byte_des_fifo_data_in[25];
			nllllO <= wire_nl0l0Ol_byte_des_fifo_data_in[26];
			nlllOi <= wire_nl0l0Ol_byte_des_fifo_data_in[27];
			nlllOl <= wire_nl0l0Ol_byte_des_fifo_data_in[28];
			nlllOO <= wire_nl0l0Ol_byte_des_fifo_data_in[29];
			nllO0i <= wire_nl0l0Ol_byte_des_fifo_data_in[33];
			nllO0l <= wire_nl0l0Ol_byte_des_fifo_data_in[34];
			nllO0O <= wire_nl0l0Ol_byte_des_fifo_data_in[35];
			nllO1i <= wire_nl0l0Ol_byte_des_fifo_data_in[30];
			nllO1l <= wire_nl0l0Ol_byte_des_fifo_data_in[31];
			nllO1O <= wire_nl0l0Ol_byte_des_fifo_data_in[32];
			nllOii <= wire_nl0l0Ol_byte_des_fifo_data_in[36];
			nllOil <= wire_nl0l0Ol_byte_des_fifo_data_in[37];
			nllOiO <= wire_nl0l0Ol_byte_des_fifo_data_in[38];
			nllOli <= wire_nl0l0Ol_byte_des_fifo_data_in[39];
			nllOll <= wire_nl0l0Ol_byte_des_fifo_data_in[40];
			nllOlO <= wire_nl0l0Ol_byte_des_fifo_data_in[41];
			nllOOi <= wire_nl0l0Ol_byte_des_fifo_data_in[42];
			nllOOl <= wire_nl0l0Ol_byte_des_fifo_data_in[43];
			nllOOO <= wire_nl0l0Ol_byte_des_fifo_data_in[44];
			nlO00i <= wire_nl0l0Ol_byte_des_fifo_data_in[63];
			nlO00l <= wire_nlOilO_dataout;
			nlO00O <= wire_nlOiOi_dataout;
			nlO01i <= wire_nl0l0Ol_byte_des_fifo_data_in[60];
			nlO01l <= wire_nl0l0Ol_byte_des_fifo_data_in[61];
			nlO01O <= wire_nl0l0Ol_byte_des_fifo_data_in[62];
			nlO0ii <= wire_nlO0OO_dataout;
			nlO0il <= nlO0iO;
			nlO0iO <= nlO0li;
			nlO0li <= bytordplden;
			nlO10i <= wire_nl0l0Ol_byte_des_fifo_data_in[48];
			nlO10l <= wire_nl0l0Ol_byte_des_fifo_data_in[49];
			nlO10O <= wire_nl0l0Ol_byte_des_fifo_data_in[50];
			nlO11i <= wire_nl0l0Ol_byte_des_fifo_data_in[45];
			nlO11l <= wire_nl0l0Ol_byte_des_fifo_data_in[46];
			nlO11O <= wire_nl0l0Ol_byte_des_fifo_data_in[47];
			nlO1ii <= wire_nl0l0Ol_byte_des_fifo_data_in[51];
			nlO1il <= wire_nl0l0Ol_byte_des_fifo_data_in[52];
			nlO1iO <= wire_nl0l0Ol_byte_des_fifo_data_in[53];
			nlO1li <= wire_nl0l0Ol_byte_des_fifo_data_in[54];
			nlO1ll <= wire_nl0l0Ol_byte_des_fifo_data_in[55];
			nlO1lO <= wire_nl0l0Ol_byte_des_fifo_data_in[56];
			nlO1Oi <= wire_nl0l0Ol_byte_des_fifo_data_in[57];
			nlO1Ol <= wire_nl0l0Ol_byte_des_fifo_data_in[58];
			nlO1OO <= wire_nl0l0Ol_byte_des_fifo_data_in[59];
			nlOliO <= wire_nlOOil_dataout;
			nlOlOl <= wire_nlOOli_dataout;
			nlOlOO <= nlOO1i;
			nlOO0i <= nlOO0O;
			nlOO0O <= pld_wr_dis;
			nlOO1i <= nl0i01l;
			nlOO1l <= (nlOO0i ^ nlOO1O);
			nlOO1O <= nlOO0i;
		end
	end
	initial
	begin
		nlOOii = 0;
		nlOOOO = 0;
	end
	always @ (rx_rd_clk or nl0l0iO or wire_nlOOOl_CLRN)
	begin
		if (nl0l0iO == 1'b1) 
		begin
			nlOOii <= 1;
			nlOOOO <= 1;
		end
		else if  (wire_nlOOOl_CLRN == 1'b0) 
		begin
			nlOOii <= 0;
			nlOOOO <= 0;
		end
		else 
		if (rx_rd_clk != nlOOOl_clk_prev && rx_rd_clk == 1'b1) 
		begin
			nlOOii <= nlOOOO;
			nlOOOO <= nl0i1li;
		end
		nlOOOl_clk_prev <= rx_rd_clk;
	end
	assign
		wire_nlOOOl_CLRN = (nl0i1ii48 ^ nl0i1ii47);
	and(wire_n0000i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[31], ~((~ nl00i1l)));
	assign		wire_n0000l_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[0] : wire_nl0l0Ol_byte_des_fifo_data_in[32];
	assign		wire_n0000O_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[1] : wire_nl0l0Ol_byte_des_fifo_data_in[33];
	and(wire_n0001i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[28], ~((~ nl00i1l)));
	and(wire_n0001l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[29], ~((~ nl00i1l)));
	and(wire_n0001O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[30], ~((~ nl00i1l)));
	assign		wire_n000i_dataout = (endec_rx === 1'b1) ? wire_n0liO_dataout : ovr_undflow[1];
	assign		wire_n000ii_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[2] : wire_nl0l0Ol_byte_des_fifo_data_in[34];
	assign		wire_n000il_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[3] : wire_nl0l0Ol_byte_des_fifo_data_in[35];
	assign		wire_n000iO_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[4] : wire_nl0l0Ol_byte_des_fifo_data_in[36];
	assign		wire_n000l_dataout = (endec_rx === 1'b1) ? wire_n0lli_dataout : ovr_undflow[2];
	assign		wire_n000li_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[5] : wire_nl0l0Ol_byte_des_fifo_data_in[37];
	assign		wire_n000ll_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[6] : wire_nl0l0Ol_byte_des_fifo_data_in[38];
	assign		wire_n000lO_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[7] : wire_nl0l0Ol_byte_des_fifo_data_in[39];
	assign		wire_n000O_dataout = (endec_rx === 1'b1) ? wire_n0lll_dataout : ovr_undflow[3];
	assign		wire_n000Oi_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[8] : wire_nl0l0Ol_byte_des_fifo_data_in[40];
	assign		wire_n000Ol_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[9] : wire_nl0l0Ol_byte_des_fifo_data_in[41];
	assign		wire_n000OO_dataout = ((~ nl00i1l) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[10] : wire_nl0l0Ol_byte_des_fifo_data_in[42];
	and(wire_n0010i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[16], ~((~ nl00i1l)));
	and(wire_n0010l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[17], ~((~ nl00i1l)));
	and(wire_n0010O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[18], ~((~ nl00i1l)));
	assign		wire_n0011i_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[29] : wire_nl0l0Ol_byte_des_fifo_data_in[61];
	assign		wire_n0011l_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[30] : wire_nl0l0Ol_byte_des_fifo_data_in[62];
	assign		wire_n0011O_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[31] : wire_nl0l0Ol_byte_des_fifo_data_in[63];
	assign		wire_n001i_dataout = (endec_rx === 1'b1) ? wire_n0lii_dataout : tenb_data[18];
	and(wire_n001ii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[19], ~((~ nl00i1l)));
	and(wire_n001il_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[20], ~((~ nl00i1l)));
	and(wire_n001iO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[21], ~((~ nl00i1l)));
	assign		wire_n001l_dataout = (endec_rx === 1'b1) ? wire_nll_dataout : tenb_data[19];
	and(wire_n001li_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[22], ~((~ nl00i1l)));
	and(wire_n001ll_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[23], ~((~ nl00i1l)));
	and(wire_n001lO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[24], ~((~ nl00i1l)));
	assign		wire_n001O_dataout = (endec_rx === 1'b1) ? wire_n0lil_dataout : ovr_undflow[0];
	and(wire_n001Oi_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[25], ~((~ nl00i1l)));
	and(wire_n001Ol_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[26], ~((~ nl00i1l)));
	and(wire_n001OO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[27], ~((~ nl00i1l)));
	assign		wire_n00i_dataout = (rrxfifo_dis === 1'b1) ? wire_n100ii_o : nl0O10l;
	and(wire_n00i0i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[46], ~((~ nl00i1l)));
	and(wire_n00i0l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[47], ~((~ nl00i1l)));
	and(wire_n00i0O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[48], ~((~ nl00i1l)));
	and(wire_n00i1i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[43], ~((~ nl00i1l)));
	and(wire_n00i1l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[44], ~((~ nl00i1l)));
	and(wire_n00i1O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[45], ~((~ nl00i1l)));
	assign		wire_n00ii_dataout = (endec_rx === 1'b1) ? wire_n0llO_dataout : disp_val_delay[0];
	and(wire_n00iii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[49], ~((~ nl00i1l)));
	and(wire_n00iil_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[50], ~((~ nl00i1l)));
	and(wire_n00iiO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[51], ~((~ nl00i1l)));
	assign		wire_n00il_dataout = (endec_rx === 1'b1) ? wire_n0lOi_dataout : disp_val_delay[1];
	and(wire_n00ili_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[52], ~((~ nl00i1l)));
	and(wire_n00ill_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[53], ~((~ nl00i1l)));
	and(wire_n00ilO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[54], ~((~ nl00i1l)));
	assign		wire_n00iO_dataout = (endec_rx === 1'b1) ? wire_n0lOl_dataout : disp_err_delay[0];
	and(wire_n00iOi_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[55], ~((~ nl00i1l)));
	and(wire_n00iOl_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[56], ~((~ nl00i1l)));
	and(wire_n00iOO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[57], ~((~ nl00i1l)));
	assign		wire_n00l_dataout = (rrxfifo_dis === 1'b1) ? wire_n100il_o : nl0O10O;
	and(wire_n00l0i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[61], ~((~ nl00i1l)));
	and(wire_n00l0l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[62], ~((~ nl00i1l)));
	and(wire_n00l0O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[63], ~((~ nl00i1l)));
	and(wire_n00l1i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[58], ~((~ nl00i1l)));
	and(wire_n00l1l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[59], ~((~ nl00i1l)));
	and(wire_n00l1O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[60], ~((~ nl00i1l)));
	assign		wire_n00li_dataout = (endec_rx === 1'b1) ? wire_n0lOO_dataout : disp_err_delay[1];
	assign		wire_n00lii_dataout = (nl00i1O === 1'b1) ? nlli1i : wire_n0iill_dataout;
	assign		wire_n00lil_dataout = (nl00i1O === 1'b1) ? nlli1l : wire_n0iilO_dataout;
	assign		wire_n00liO_dataout = (nl00i1O === 1'b1) ? nlli1O : wire_n0iiOi_dataout;
	assign		wire_n00ll_dataout = (endec_rx === 1'b1) ? wire_n0O1i_dataout : sync_resync_delay[0];
	assign		wire_n00lli_dataout = (nl00i1O === 1'b1) ? nlli0i : wire_n0iiOl_dataout;
	assign		wire_n00lll_dataout = (nl00i1O === 1'b1) ? nlli0l : wire_n0iiOO_dataout;
	assign		wire_n00llO_dataout = (nl00i1O === 1'b1) ? nlli0O : wire_n0il1i_dataout;
	assign		wire_n00lO_dataout = (endec_rx === 1'b1) ? wire_n0O1l_dataout : sync_resync_delay[1];
	assign		wire_n00lOi_dataout = (nl00i1O === 1'b1) ? nlliii : wire_n0il1l_dataout;
	assign		wire_n00lOl_dataout = (nl00i1O === 1'b1) ? nlliil : wire_n0il1O_dataout;
	assign		wire_n00lOO_dataout = (nl00i1O === 1'b1) ? nlliiO : wire_n0il0i_dataout;
	assign		wire_n00O_dataout = (rrxfifo_dis === 1'b1) ? wire_n100iO_o : nl0O1ii;
	assign		wire_n00O0i_dataout = (nl00i1O === 1'b1) ? nlliOi : wire_n0ilil_dataout;
	assign		wire_n00O0l_dataout = (nl00i1O === 1'b1) ? nlliOl : wire_n0iliO_dataout;
	assign		wire_n00O0O_dataout = (nl00i1O === 1'b1) ? nlliOO : wire_n0illi_dataout;
	assign		wire_n00O1i_dataout = (nl00i1O === 1'b1) ? nllili : wire_n0il0l_dataout;
	assign		wire_n00O1l_dataout = (nl00i1O === 1'b1) ? nllill : wire_n0il0O_dataout;
	assign		wire_n00O1O_dataout = (nl00i1O === 1'b1) ? nllilO : wire_n0ilii_dataout;
	and(wire_n00Oi_dataout, wire_niOil_o, ~(((~ n110O) & (~ rsync_sm_dis))));
	assign		wire_n00Oii_dataout = (nl00i1O === 1'b1) ? nlll1i : wire_n0illl_dataout;
	assign		wire_n00Oil_dataout = (nl00i1O === 1'b1) ? wire_n0l0OO_dataout : wire_n0illO_dataout;
	assign		wire_n00OiO_dataout = (nl00i1O === 1'b1) ? wire_n0li1i_dataout : wire_n0ilOi_dataout;
	assign		wire_n00Oli_dataout = (nl00i1O === 1'b1) ? wire_n0li1l_dataout : wire_n0ilOl_dataout;
	assign		wire_n00Oll_dataout = (nl00i1O === 1'b1) ? wire_n0li1O_dataout : wire_n0ilOO_dataout;
	assign		wire_n00OlO_dataout = (nl00i1O === 1'b1) ? wire_n0li0i_dataout : wire_n0iO1i_dataout;
	and(wire_n00OO_dataout, wire_nliil_o, ~(((~ n110l) & (~ rsync_sm_dis))));
	assign		wire_n00OOi_dataout = (nl00i1O === 1'b1) ? wire_n0li0l_dataout : wire_n0iO1l_dataout;
	assign		wire_n00OOl_dataout = (nl00i1O === 1'b1) ? wire_n0li0O_dataout : wire_n0iO1O_dataout;
	assign		wire_n00OOO_dataout = (nl00i1O === 1'b1) ? wire_n0liii_dataout : wire_n0iO0i_dataout;
	assign		wire_n0100i_dataout = ((~ nl00i1i) === 1'b1) ? nllOii : wire_nl0l0Ol_byte_des_fifo_data_in[4];
	assign		wire_n0100l_dataout = ((~ nl00i1i) === 1'b1) ? nllOil : wire_nl0l0Ol_byte_des_fifo_data_in[5];
	assign		wire_n0100O_dataout = ((~ nl00i1i) === 1'b1) ? nllOiO : wire_nl0l0Ol_byte_des_fifo_data_in[6];
	assign		wire_n0101i_dataout = ((~ nl00i1i) === 1'b1) ? nllO0i : wire_nl0l0Ol_byte_des_fifo_data_in[1];
	assign		wire_n0101l_dataout = ((~ nl00i1i) === 1'b1) ? nllO0l : wire_nl0l0Ol_byte_des_fifo_data_in[2];
	assign		wire_n0101O_dataout = ((~ nl00i1i) === 1'b1) ? nllO0O : wire_nl0l0Ol_byte_des_fifo_data_in[3];
	assign		wire_n010i_dataout = (endec_rx === 1'b1) ? wire_n0ili_dataout : tenb_data[6];
	assign		wire_n010ii_dataout = ((~ nl00i1i) === 1'b1) ? nllOli : wire_nl0l0Ol_byte_des_fifo_data_in[7];
	assign		wire_n010il_dataout = ((~ nl00i1i) === 1'b1) ? nllOll : wire_nl0l0Ol_byte_des_fifo_data_in[8];
	assign		wire_n010iO_dataout = ((~ nl00i1i) === 1'b1) ? nllOlO : wire_nl0l0Ol_byte_des_fifo_data_in[9];
	assign		wire_n010l_dataout = (endec_rx === 1'b1) ? wire_n0ill_dataout : tenb_data[7];
	assign		wire_n010li_dataout = ((~ nl00i1i) === 1'b1) ? nllOOi : wire_nl0l0Ol_byte_des_fifo_data_in[10];
	assign		wire_n010ll_dataout = ((~ nl00i1i) === 1'b1) ? nllOOl : wire_nl0l0Ol_byte_des_fifo_data_in[11];
	assign		wire_n010lO_dataout = ((~ nl00i1i) === 1'b1) ? nllOOO : wire_nl0l0Ol_byte_des_fifo_data_in[12];
	assign		wire_n010O_dataout = (endec_rx === 1'b1) ? wire_n0ilO_dataout : tenb_data[8];
	assign		wire_n010Oi_dataout = ((~ nl00i1i) === 1'b1) ? nlO11i : wire_nl0l0Ol_byte_des_fifo_data_in[13];
	assign		wire_n010Ol_dataout = ((~ nl00i1i) === 1'b1) ? nlO11l : wire_nl0l0Ol_byte_des_fifo_data_in[14];
	assign		wire_n010OO_dataout = ((~ nl00i1i) === 1'b1) ? nlO11O : wire_nl0l0Ol_byte_des_fifo_data_in[15];
	assign		wire_n0110i_dataout = (nl0i10i === 1'b1) ? wire_n00ill_dataout : wire_n01Oil_dataout;
	assign		wire_n0110l_dataout = (nl0i10i === 1'b1) ? wire_n00ilO_dataout : wire_n01OiO_dataout;
	assign		wire_n0110O_dataout = (nl0i10i === 1'b1) ? wire_n00iOi_dataout : wire_n01Oli_dataout;
	assign		wire_n0111i_dataout = (nl0i10i === 1'b1) ? wire_n00iil_dataout : wire_n01O0l_dataout;
	assign		wire_n0111l_dataout = (nl0i10i === 1'b1) ? wire_n00iiO_dataout : wire_n01O0O_dataout;
	assign		wire_n0111O_dataout = (nl0i10i === 1'b1) ? wire_n00ili_dataout : wire_n01Oii_dataout;
	assign		wire_n011i_dataout = (endec_rx === 1'b1) ? wire_n0iii_dataout : tenb_data[3];
	assign		wire_n011ii_dataout = (nl0i10i === 1'b1) ? wire_n00iOl_dataout : wire_n01Oll_dataout;
	assign		wire_n011il_dataout = (nl0i10i === 1'b1) ? wire_n00iOO_dataout : wire_n01OlO_dataout;
	assign		wire_n011iO_dataout = (nl0i10i === 1'b1) ? wire_n00l1i_dataout : wire_n01OOi_dataout;
	assign		wire_n011l_dataout = (endec_rx === 1'b1) ? wire_n0iil_dataout : tenb_data[4];
	assign		wire_n011li_dataout = (nl0i10i === 1'b1) ? wire_n00l1l_dataout : wire_n01OOl_dataout;
	assign		wire_n011ll_dataout = (nl0i10i === 1'b1) ? wire_n00l1O_dataout : wire_n01OOO_dataout;
	assign		wire_n011lO_dataout = (nl0i10i === 1'b1) ? wire_n00l0i_dataout : wire_n0011i_dataout;
	assign		wire_n011O_dataout = (endec_rx === 1'b1) ? wire_n0iiO_dataout : tenb_data[5];
	assign		wire_n011Oi_dataout = (nl0i10i === 1'b1) ? wire_n00l0l_dataout : wire_n0011l_dataout;
	assign		wire_n011Ol_dataout = (nl0i10i === 1'b1) ? wire_n00l0O_dataout : wire_n0011O_dataout;
	assign		wire_n011OO_dataout = ((~ nl00i1i) === 1'b1) ? nllO1O : wire_nl0l0Ol_byte_des_fifo_data_in[0];
	assign		wire_n01i_dataout = (rrxfifo_dis === 1'b1) ? wire_n1000i_o : nl0O11l;
	assign		wire_n01i0i_dataout = ((~ nl00i1i) === 1'b1) ? nlO1ii : wire_nl0l0Ol_byte_des_fifo_data_in[19];
	assign		wire_n01i0l_dataout = ((~ nl00i1i) === 1'b1) ? nlO1il : wire_nl0l0Ol_byte_des_fifo_data_in[20];
	assign		wire_n01i0O_dataout = ((~ nl00i1i) === 1'b1) ? nlO1iO : wire_nl0l0Ol_byte_des_fifo_data_in[21];
	assign		wire_n01i1i_dataout = ((~ nl00i1i) === 1'b1) ? nlO10i : wire_nl0l0Ol_byte_des_fifo_data_in[16];
	assign		wire_n01i1l_dataout = ((~ nl00i1i) === 1'b1) ? nlO10l : wire_nl0l0Ol_byte_des_fifo_data_in[17];
	assign		wire_n01i1O_dataout = ((~ nl00i1i) === 1'b1) ? nlO10O : wire_nl0l0Ol_byte_des_fifo_data_in[18];
	assign		wire_n01ii_dataout = (endec_rx === 1'b1) ? wire_n0iOi_dataout : tenb_data[9];
	assign		wire_n01iii_dataout = ((~ nl00i1i) === 1'b1) ? nlO1li : wire_nl0l0Ol_byte_des_fifo_data_in[22];
	assign		wire_n01iil_dataout = ((~ nl00i1i) === 1'b1) ? nlO1ll : wire_nl0l0Ol_byte_des_fifo_data_in[23];
	assign		wire_n01iiO_dataout = ((~ nl00i1i) === 1'b1) ? nlO1lO : wire_nl0l0Ol_byte_des_fifo_data_in[24];
	assign		wire_n01il_dataout = (endec_rx === 1'b1) ? wire_n0iOl_dataout : tenb_data[10];
	assign		wire_n01ili_dataout = ((~ nl00i1i) === 1'b1) ? nlO1Oi : wire_nl0l0Ol_byte_des_fifo_data_in[25];
	assign		wire_n01ill_dataout = ((~ nl00i1i) === 1'b1) ? nlO1Ol : wire_nl0l0Ol_byte_des_fifo_data_in[26];
	assign		wire_n01ilO_dataout = ((~ nl00i1i) === 1'b1) ? nlO1OO : wire_nl0l0Ol_byte_des_fifo_data_in[27];
	assign		wire_n01iO_dataout = (endec_rx === 1'b1) ? wire_n0iOO_dataout : tenb_data[11];
	assign		wire_n01iOi_dataout = ((~ nl00i1i) === 1'b1) ? nlO01i : wire_nl0l0Ol_byte_des_fifo_data_in[28];
	assign		wire_n01iOl_dataout = ((~ nl00i1i) === 1'b1) ? nlO01l : wire_nl0l0Ol_byte_des_fifo_data_in[29];
	assign		wire_n01iOO_dataout = ((~ nl00i1i) === 1'b1) ? nlO01O : wire_nl0l0Ol_byte_des_fifo_data_in[30];
	assign		wire_n01l_dataout = (rrxfifo_dis === 1'b1) ? wire_n1000l_o : nl0O11O;
	assign		wire_n01l0i_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[2] : wire_nl0l0Ol_byte_des_fifo_data_in[34];
	assign		wire_n01l0l_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[3] : wire_nl0l0Ol_byte_des_fifo_data_in[35];
	assign		wire_n01l0O_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[4] : wire_nl0l0Ol_byte_des_fifo_data_in[36];
	assign		wire_n01l1i_dataout = ((~ nl00i1i) === 1'b1) ? nlO00i : wire_nl0l0Ol_byte_des_fifo_data_in[31];
	assign		wire_n01l1l_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[0] : wire_nl0l0Ol_byte_des_fifo_data_in[32];
	assign		wire_n01l1O_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[1] : wire_nl0l0Ol_byte_des_fifo_data_in[33];
	assign		wire_n01li_dataout = (endec_rx === 1'b1) ? wire_n0l1i_dataout : tenb_data[12];
	assign		wire_n01lii_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[5] : wire_nl0l0Ol_byte_des_fifo_data_in[37];
	assign		wire_n01lil_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[6] : wire_nl0l0Ol_byte_des_fifo_data_in[38];
	assign		wire_n01liO_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[7] : wire_nl0l0Ol_byte_des_fifo_data_in[39];
	assign		wire_n01ll_dataout = (endec_rx === 1'b1) ? wire_n0l1l_dataout : tenb_data[13];
	assign		wire_n01lli_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[8] : wire_nl0l0Ol_byte_des_fifo_data_in[40];
	assign		wire_n01lll_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[9] : wire_nl0l0Ol_byte_des_fifo_data_in[41];
	assign		wire_n01llO_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[10] : wire_nl0l0Ol_byte_des_fifo_data_in[42];
	assign		wire_n01lO_dataout = (endec_rx === 1'b1) ? wire_n0l1O_dataout : tenb_data[14];
	assign		wire_n01lOi_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[11] : wire_nl0l0Ol_byte_des_fifo_data_in[43];
	assign		wire_n01lOl_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[12] : wire_nl0l0Ol_byte_des_fifo_data_in[44];
	assign		wire_n01lOO_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[13] : wire_nl0l0Ol_byte_des_fifo_data_in[45];
	assign		wire_n01O_dataout = (rrxfifo_dis === 1'b1) ? wire_n1000O_o : nl0O10i;
	assign		wire_n01O0i_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[17] : wire_nl0l0Ol_byte_des_fifo_data_in[49];
	assign		wire_n01O0l_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[18] : wire_nl0l0Ol_byte_des_fifo_data_in[50];
	assign		wire_n01O0O_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[19] : wire_nl0l0Ol_byte_des_fifo_data_in[51];
	assign		wire_n01O1i_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[14] : wire_nl0l0Ol_byte_des_fifo_data_in[46];
	assign		wire_n01O1l_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[15] : wire_nl0l0Ol_byte_des_fifo_data_in[47];
	assign		wire_n01O1O_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[16] : wire_nl0l0Ol_byte_des_fifo_data_in[48];
	assign		wire_n01Oi_dataout = (endec_rx === 1'b1) ? wire_n0l0i_dataout : tenb_data[15];
	assign		wire_n01Oii_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[20] : wire_nl0l0Ol_byte_des_fifo_data_in[52];
	assign		wire_n01Oil_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[21] : wire_nl0l0Ol_byte_des_fifo_data_in[53];
	assign		wire_n01OiO_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[22] : wire_nl0l0Ol_byte_des_fifo_data_in[54];
	assign		wire_n01Ol_dataout = (endec_rx === 1'b1) ? wire_n0l0l_dataout : tenb_data[16];
	assign		wire_n01Oli_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[23] : wire_nl0l0Ol_byte_des_fifo_data_in[55];
	assign		wire_n01Oll_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[24] : wire_nl0l0Ol_byte_des_fifo_data_in[56];
	assign		wire_n01OlO_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[25] : wire_nl0l0Ol_byte_des_fifo_data_in[57];
	assign		wire_n01OO_dataout = (endec_rx === 1'b1) ? wire_n0l0O_dataout : tenb_data[17];
	assign		wire_n01OOi_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[26] : wire_nl0l0Ol_byte_des_fifo_data_in[58];
	assign		wire_n01OOl_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[27] : wire_nl0l0Ol_byte_des_fifo_data_in[59];
	assign		wire_n01OOO_dataout = ((~ nl00i1i) === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[28] : wire_nl0l0Ol_byte_des_fifo_data_in[60];
	assign		wire_n0i_dataout = (rrxfifo_dis === 1'b1) ? wire_n10Oii_o : nl0Ol0l;
	assign		wire_n0i00i_dataout = (nl00i1O === 1'b1) ? wire_n0llll_dataout : wire_n0l1il_dataout;
	assign		wire_n0i00l_dataout = (nl00i1O === 1'b1) ? wire_n0lllO_dataout : wire_n0l1iO_dataout;
	assign		wire_n0i00O_dataout = (nl00i1O === 1'b1) ? wire_n0llOi_dataout : wire_n0l1li_dataout;
	assign		wire_n0i01i_dataout = (nl00i1O === 1'b1) ? wire_n0llil_dataout : wire_n0l10l_dataout;
	assign		wire_n0i01l_dataout = (nl00i1O === 1'b1) ? wire_n0lliO_dataout : wire_n0l10O_dataout;
	assign		wire_n0i01O_dataout = (nl00i1O === 1'b1) ? wire_n0llli_dataout : wire_n0l1ii_dataout;
	assign		wire_n0i0i_dataout = (rendec_data_sel_rx === 1'b1) ? wire_ni0li_dataout : rx_data_rs[0];
	assign		wire_n0i0ii_dataout = (nl00i1O === 1'b1) ? wire_n0llOl_dataout : wire_n0l1ll_dataout;
	assign		wire_n0i0il_dataout = (nl00i1O === 1'b1) ? wire_n0llOO_dataout : wire_n0l1lO_dataout;
	assign		wire_n0i0iO_dataout = (nl00i1O === 1'b1) ? wire_n0lO1i_dataout : wire_n0l1Oi_dataout;
	assign		wire_n0i0l_dataout = (rendec_data_sel_rx === 1'b1) ? wire_ni0ll_dataout : rx_data_rs[1];
	assign		wire_n0i0li_dataout = (nl00i1O === 1'b1) ? wire_n0lO1l_dataout : wire_n0l1Ol_dataout;
	assign		wire_n0i0ll_dataout = (nl00i1O === 1'b1) ? wire_n0lO1O_dataout : wire_n0l1OO_dataout;
	assign		wire_n0i0lO_dataout = (nl00i1O === 1'b1) ? wire_n0lO0i_dataout : wire_n0l01i_dataout;
	assign		wire_n0i0O_dataout = (rendec_data_sel_rx === 1'b1) ? wire_ni0lO_dataout : rx_data_rs[2];
	assign		wire_n0i0Oi_dataout = (nl00i1O === 1'b1) ? wire_n0lO0l_dataout : wire_n0l01l_dataout;
	assign		wire_n0i0Ol_dataout = (nl00i1O === 1'b1) ? wire_n0lO0O_dataout : wire_n0l01O_dataout;
	assign		wire_n0i0OO_dataout = (nl00i1O === 1'b1) ? wire_n0lOii_dataout : wire_n0l00i_dataout;
	assign		wire_n0i10i_dataout = (nl00i1O === 1'b1) ? wire_n0lill_dataout : wire_n0iOil_dataout;
	assign		wire_n0i10l_dataout = (nl00i1O === 1'b1) ? wire_n0lilO_dataout : wire_n0iOiO_dataout;
	assign		wire_n0i10O_dataout = (nl00i1O === 1'b1) ? wire_n0liOi_dataout : wire_n0iOli_dataout;
	assign		wire_n0i11i_dataout = (nl00i1O === 1'b1) ? wire_n0liil_dataout : wire_n0iO0l_dataout;
	assign		wire_n0i11l_dataout = (nl00i1O === 1'b1) ? wire_n0liiO_dataout : wire_n0iO0O_dataout;
	assign		wire_n0i11O_dataout = (nl00i1O === 1'b1) ? wire_n0lili_dataout : wire_n0iOii_dataout;
	assign		wire_n0i1ii_dataout = (nl00i1O === 1'b1) ? wire_n0liOl_dataout : wire_n0iOll_dataout;
	assign		wire_n0i1il_dataout = (nl00i1O === 1'b1) ? wire_n0liOO_dataout : wire_n0iOlO_dataout;
	assign		wire_n0i1iO_dataout = (nl00i1O === 1'b1) ? wire_n0ll1i_dataout : wire_n0iOOi_dataout;
	assign		wire_n0i1l_dataout = (rendec_data_sel_rx === 1'b1) ? wire_ni0iO_dataout : n10iO;
	assign		wire_n0i1li_dataout = (nl00i1O === 1'b1) ? wire_n0ll1l_dataout : wire_n0iOOl_dataout;
	assign		wire_n0i1ll_dataout = (nl00i1O === 1'b1) ? wire_n0ll1O_dataout : wire_n0iOOO_dataout;
	assign		wire_n0i1lO_dataout = (nl00i1O === 1'b1) ? wire_n0ll0i_dataout : wire_n0l11i_dataout;
	assign		wire_n0i1O_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0O0l_dataout : n10li;
	assign		wire_n0i1Oi_dataout = (nl00i1O === 1'b1) ? wire_n0ll0l_dataout : wire_n0l11l_dataout;
	assign		wire_n0i1Ol_dataout = (nl00i1O === 1'b1) ? wire_n0ll0O_dataout : wire_n0l11O_dataout;
	assign		wire_n0i1OO_dataout = (nl00i1O === 1'b1) ? wire_n0llii_dataout : wire_n0l10i_dataout;
	assign		wire_n0ii_dataout = (rrxfifo_dis === 1'b1) ? wire_n100li_o : nl0O1il;
	assign		wire_n0ii0i_dataout = (nl00i1O === 1'b1) ? wire_n0lOll_dataout : wire_n0l0il_dataout;
	assign		wire_n0ii0l_dataout = (nl00i1O === 1'b1) ? wire_n0lOlO_dataout : wire_n0l0iO_dataout;
	assign		wire_n0ii0O_dataout = (nl00i1O === 1'b1) ? wire_n0lOOi_dataout : wire_n0l0li_dataout;
	assign		wire_n0ii1i_dataout = (nl00i1O === 1'b1) ? wire_n0lOil_dataout : wire_n0l00l_dataout;
	assign		wire_n0ii1l_dataout = (nl00i1O === 1'b1) ? wire_n0lOiO_dataout : wire_n0l00O_dataout;
	assign		wire_n0ii1O_dataout = (nl00i1O === 1'b1) ? wire_n0lOli_dataout : wire_n0l0ii_dataout;
	assign		wire_n0iii_dataout = (rendec_data_sel_rx === 1'b1) ? wire_ni0Oi_dataout : rx_data_rs[3];
	assign		wire_n0iiii_dataout = (nl00i1O === 1'b1) ? wire_n0lOOl_dataout : wire_n0l0ll_dataout;
	assign		wire_n0iiil_dataout = (nl00i1O === 1'b1) ? wire_n0lOOO_dataout : wire_n0l0lO_dataout;
	assign		wire_n0iiiO_dataout = (nl00i1O === 1'b1) ? wire_n0O11i_dataout : wire_n0l0Oi_dataout;
	assign		wire_n0iil_dataout = (rendec_data_sel_rx === 1'b1) ? wire_ni0Ol_dataout : rx_data_rs[4];
	assign		wire_n0iili_dataout = (nl00i1O === 1'b1) ? wire_n0O11l_dataout : wire_n0l0Ol_dataout;
	assign		wire_n0iill_dataout = (nl00i0i === 1'b1) ? nlilOi : nlli1i;
	assign		wire_n0iilO_dataout = (nl00i0i === 1'b1) ? nlilOl : nlli1l;
	assign		wire_n0iiO_dataout = (rendec_data_sel_rx === 1'b1) ? wire_ni0OO_dataout : rx_data_rs[5];
	assign		wire_n0iiOi_dataout = (nl00i0i === 1'b1) ? nlilOO : nlli1O;
	assign		wire_n0iiOl_dataout = (nl00i0i === 1'b1) ? nliO1i : nlli0i;
	assign		wire_n0iiOO_dataout = (nl00i0i === 1'b1) ? nliO1l : nlli0l;
	assign		wire_n0il_dataout = (rrxfifo_dis === 1'b1) ? wire_n100ll_o : nl0O1iO;
	assign		wire_n0il0i_dataout = (nl00i0i === 1'b1) ? nliO0O : nlliiO;
	assign		wire_n0il0l_dataout = (nl00i0i === 1'b1) ? nliOii : nllili;
	assign		wire_n0il0O_dataout = (nl00i0i === 1'b1) ? nliOil : nllill;
	assign		wire_n0il1i_dataout = (nl00i0i === 1'b1) ? nliO1O : nlli0O;
	assign		wire_n0il1l_dataout = (nl00i0i === 1'b1) ? nliO0i : nlliii;
	assign		wire_n0il1O_dataout = (nl00i0i === 1'b1) ? nliO0l : nlliil;
	assign		wire_n0ili_dataout = (rendec_data_sel_rx === 1'b1) ? wire_nii1i_dataout : rx_data_rs[6];
	assign		wire_n0ilii_dataout = (nl00i0i === 1'b1) ? nliOiO : nllilO;
	assign		wire_n0ilil_dataout = (nl00i0i === 1'b1) ? nliOli : nlliOi;
	assign		wire_n0iliO_dataout = (nl00i0i === 1'b1) ? nliOll : nlliOl;
	assign		wire_n0ill_dataout = (rendec_data_sel_rx === 1'b1) ? wire_nii1l_dataout : rx_data_rs[7];
	assign		wire_n0illi_dataout = (nl00i0i === 1'b1) ? nliOlO : nlliOO;
	assign		wire_n0illl_dataout = (nl00i0i === 1'b1) ? nliOOi : nlll1i;
	assign		wire_n0illO_dataout = (nl00i0i === 1'b1) ? nlli1i : nlll1l;
	assign		wire_n0ilO_dataout = (rendec_data_sel_rx === 1'b1) ? wire_nii1O_dataout : rx_control_rs;
	assign		wire_n0ilOi_dataout = (nl00i0i === 1'b1) ? nlli1l : nlll1O;
	assign		wire_n0ilOl_dataout = (nl00i0i === 1'b1) ? nlli1O : nlll0i;
	assign		wire_n0ilOO_dataout = (nl00i0i === 1'b1) ? nlli0i : nlll0l;
	assign		wire_n0iO_dataout = (rrxfifo_dis === 1'b1) ? wire_n100lO_o : nl0O1li;
	assign		wire_n0iO0i_dataout = (nl00i0i === 1'b1) ? nlliil : nllliO;
	assign		wire_n0iO0l_dataout = (nl00i0i === 1'b1) ? nlliiO : nlllli;
	assign		wire_n0iO0O_dataout = (nl00i0i === 1'b1) ? nllili : nlllll;
	assign		wire_n0iO1i_dataout = (nl00i0i === 1'b1) ? nlli0l : nlll0O;
	assign		wire_n0iO1l_dataout = (nl00i0i === 1'b1) ? nlli0O : nlllii;
	assign		wire_n0iO1O_dataout = (nl00i0i === 1'b1) ? nlliii : nlllil;
	assign		wire_n0iOi_dataout = (rendec_data_sel_rx === 1'b1) ? wire_nli_dataout : ((~ nl0i00i) & rx_control_rs);
	assign		wire_n0iOii_dataout = (nl00i0i === 1'b1) ? nllill : nllllO;
	assign		wire_n0iOil_dataout = (nl00i0i === 1'b1) ? nllilO : nlllOi;
	assign		wire_n0iOiO_dataout = (nl00i0i === 1'b1) ? nlliOi : nlllOl;
	assign		wire_n0iOl_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0O0O_dataout : rx_data_dt[8];
	assign		wire_n0iOli_dataout = (nl00i0i === 1'b1) ? nlliOl : nlllOO;
	assign		wire_n0iOll_dataout = (nl00i0i === 1'b1) ? nlliOO : nllO1i;
	assign		wire_n0iOlO_dataout = (nl00i0i === 1'b1) ? nlll1i : nllO1l;
	assign		wire_n0iOO_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0Oii_dataout : rx_data_dt[9];
	and(wire_n0iOOi_dataout, nllO1O, ~(nl00i0i));
	and(wire_n0iOOl_dataout, nllO0i, ~(nl00i0i));
	and(wire_n0iOOO_dataout, nllO0l, ~(nl00i0i));
	assign		wire_n0l_dataout = (rrxfifo_dis === 1'b1) ? wire_n10Oil_o : nl0Ol0O;
	and(wire_n0l00i_dataout, nlO1iO, ~(nl00i0i));
	and(wire_n0l00l_dataout, nlO1li, ~(nl00i0i));
	and(wire_n0l00O_dataout, nlO1ll, ~(nl00i0i));
	and(wire_n0l01i_dataout, nlO10O, ~(nl00i0i));
	and(wire_n0l01l_dataout, nlO1ii, ~(nl00i0i));
	and(wire_n0l01O_dataout, nlO1il, ~(nl00i0i));
	assign		wire_n0l0i_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0Oll_dataout : rx_data_dt[13];
	and(wire_n0l0ii_dataout, nlO1lO, ~(nl00i0i));
	and(wire_n0l0il_dataout, nlO1Oi, ~(nl00i0i));
	and(wire_n0l0iO_dataout, nlO1Ol, ~(nl00i0i));
	assign		wire_n0l0l_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0OlO_dataout : rx_data_dt[14];
	and(wire_n0l0li_dataout, nlO1OO, ~(nl00i0i));
	and(wire_n0l0ll_dataout, nlO01i, ~(nl00i0i));
	and(wire_n0l0lO_dataout, nlO01l, ~(nl00i0i));
	assign		wire_n0l0O_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0OOi_dataout : rx_data_dt[15];
	and(wire_n0l0Oi_dataout, nlO01O, ~(nl00i0i));
	and(wire_n0l0Ol_dataout, nlO00i, ~(nl00i0i));
	assign		wire_n0l0OO_dataout = (nl00i0l === 1'b1) ? rbytordpadval[0] : nlll1l;
	and(wire_n0l10i_dataout, nllOiO, ~(nl00i0i));
	and(wire_n0l10l_dataout, nllOli, ~(nl00i0i));
	and(wire_n0l10O_dataout, nllOll, ~(nl00i0i));
	and(wire_n0l11i_dataout, nllO0O, ~(nl00i0i));
	and(wire_n0l11l_dataout, nllOii, ~(nl00i0i));
	and(wire_n0l11O_dataout, nllOil, ~(nl00i0i));
	assign		wire_n0l1i_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0Oil_dataout : rx_data_dt[10];
	and(wire_n0l1ii_dataout, nllOlO, ~(nl00i0i));
	and(wire_n0l1il_dataout, nllOOi, ~(nl00i0i));
	and(wire_n0l1iO_dataout, nllOOl, ~(nl00i0i));
	assign		wire_n0l1l_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0OiO_dataout : rx_data_dt[11];
	and(wire_n0l1li_dataout, nllOOO, ~(nl00i0i));
	and(wire_n0l1ll_dataout, nlO11i, ~(nl00i0i));
	and(wire_n0l1lO_dataout, nlO11l, ~(nl00i0i));
	assign		wire_n0l1O_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0Oli_dataout : rx_data_dt[12];
	and(wire_n0l1Oi_dataout, nlO11O, ~(nl00i0i));
	and(wire_n0l1Ol_dataout, nlO10i, ~(nl00i0i));
	and(wire_n0l1OO_dataout, nlO10l, ~(nl00i0i));
	assign		wire_n0li_dataout = (rrxfifo_dis === 1'b1) ? wire_n100Oi_o : nl0O1ll;
	assign		wire_n0li0i_dataout = (nl00i0l === 1'b1) ? rbytordpadval[4] : nlll0O;
	assign		wire_n0li0l_dataout = (nl00i0l === 1'b1) ? rbytordpadval[5] : nlllii;
	assign		wire_n0li0O_dataout = (nl00i0l === 1'b1) ? rbytordpadval[6] : nlllil;
	assign		wire_n0li1i_dataout = (nl00i0l === 1'b1) ? rbytordpadval[1] : nlll1O;
	assign		wire_n0li1l_dataout = (nl00i0l === 1'b1) ? rbytordpadval[2] : nlll0i;
	assign		wire_n0li1O_dataout = (nl00i0l === 1'b1) ? rbytordpadval[3] : nlll0l;
	assign		wire_n0lii_dataout = (rendec_data_sel_rx === 1'b1) ? wire_n0OOl_dataout : rx_control_dt[1];
	assign		wire_n0liii_dataout = (nl00i0l === 1'b1) ? rbytordpadval[7] : nllliO;
	assign		wire_n0liil_dataout = (nl00i0l === 1'b1) ? rbytordpadval[8] : nlllli;
	assign		wire_n0liiO_dataout = (nl00i0l === 1'b1) ? rbytordpadval[9] : nlllll;
	assign		wire_n0lil_dataout = (rendec_data_sel_rx === 1'b1) ? ovr_undflow[0] : n11il;
	assign		wire_n0lili_dataout = (nl00i0l === 1'b1) ? nllill : nllllO;
	and(wire_n0lill_dataout, nlllOi, ~(nl00i0l));
	and(wire_n0lilO_dataout, nlllOl, ~(nl00i0l));
	assign		wire_n0liO_dataout = (rendec_data_sel_rx === 1'b1) ? ovr_undflow[1] : n11iO;
	and(wire_n0liOi_dataout, nlllOO, ~(nl00i0l));
	and(wire_n0liOl_dataout, nllO1i, ~(nl00i0l));
	and(wire_n0liOO_dataout, nllO1l, ~(nl00i0l));
	assign		wire_n0ll_dataout = (rrxfifo_dis === 1'b1) ? wire_n100Ol_o : nl0O1lO;
	and(wire_n0ll0i_dataout, nllO0O, ~(nl00i0l));
	and(wire_n0ll0l_dataout, nllOii, ~(nl00i0l));
	and(wire_n0ll0O_dataout, nllOil, ~(nl00i0l));
	and(wire_n0ll1i_dataout, nllO1O, ~(nl00i0l));
	and(wire_n0ll1l_dataout, nllO0i, ~(nl00i0l));
	and(wire_n0ll1O_dataout, nllO0l, ~(nl00i0l));
	assign		wire_n0lli_dataout = (rendec_data_sel_rx === 1'b1) ? ovr_undflow[2] : n11li;
	and(wire_n0llii_dataout, nllOiO, ~(nl00i0l));
	and(wire_n0llil_dataout, nllOli, ~(nl00i0l));
	and(wire_n0lliO_dataout, nllOll, ~(nl00i0l));
	assign		wire_n0lll_dataout = (rendec_data_sel_rx === 1'b1) ? ovr_undflow[3] : n11ll;
	and(wire_n0llli_dataout, nllOlO, ~(nl00i0l));
	and(wire_n0llll_dataout, nllOOi, ~(nl00i0l));
	and(wire_n0lllO_dataout, nllOOl, ~(nl00i0l));
	assign		wire_n0llO_dataout = (rendec_data_sel_rx === 1'b1) ? disp_val_delay[0] : n1i0i;
	and(wire_n0llOi_dataout, nllOOO, ~(nl00i0l));
	and(wire_n0llOl_dataout, nlO11i, ~(nl00i0l));
	and(wire_n0llOO_dataout, nlO11l, ~(nl00i0l));
	assign		wire_n0lO_dataout = (rrxfifo_dis === 1'b1) ? wire_n100OO_o : nl0O1Oi;
	and(wire_n0lO0i_dataout, nlO10O, ~(nl00i0l));
	and(wire_n0lO0l_dataout, nlO1ii, ~(nl00i0l));
	and(wire_n0lO0O_dataout, nlO1il, ~(nl00i0l));
	and(wire_n0lO1i_dataout, nlO11O, ~(nl00i0l));
	and(wire_n0lO1l_dataout, nlO10i, ~(nl00i0l));
	and(wire_n0lO1O_dataout, nlO10l, ~(nl00i0l));
	assign		wire_n0lOi_dataout = (rendec_data_sel_rx === 1'b1) ? disp_val_delay[1] : n1i0l;
	and(wire_n0lOii_dataout, nlO1iO, ~(nl00i0l));
	and(wire_n0lOil_dataout, nlO1li, ~(nl00i0l));
	and(wire_n0lOiO_dataout, nlO1ll, ~(nl00i0l));
	assign		wire_n0lOl_dataout = (rendec_data_sel_rx === 1'b1) ? disp_err_delay[0] : n1iil;
	and(wire_n0lOli_dataout, nlO1lO, ~(nl00i0l));
	and(wire_n0lOll_dataout, nlO1Oi, ~(nl00i0l));
	and(wire_n0lOlO_dataout, nlO1Ol, ~(nl00i0l));
	assign		wire_n0lOO_dataout = (rendec_data_sel_rx === 1'b1) ? disp_err_delay[1] : n1iiO;
	and(wire_n0lOOi_dataout, nlO1OO, ~(nl00i0l));
	and(wire_n0lOOl_dataout, nlO01i, ~(nl00i0l));
	and(wire_n0lOOO_dataout, nlO01l, ~(nl00i0l));
	assign		wire_n0O_dataout = (rrxfifo_dis === 1'b1) ? wire_n10OiO_o : nl0Olii;
	assign		wire_n0O00i_dataout = (nl00i1O === 1'b1) ? wire_ni1lll_dataout : wire_ni11il_dataout;
	assign		wire_n0O00l_dataout = (nl00i1O === 1'b1) ? wire_ni1llO_dataout : wire_ni11iO_dataout;
	assign		wire_n0O00O_dataout = (nl00i1O === 1'b1) ? wire_ni1lOi_dataout : wire_ni11li_dataout;
	assign		wire_n0O01i_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[13] : wire_ni110l_dataout;
	assign		wire_n0O01l_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[14] : wire_ni110O_dataout;
	assign		wire_n0O01O_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[15] : wire_ni11ii_dataout;
	assign		wire_n0O0ii_dataout = (nl00i1O === 1'b1) ? wire_ni1lOl_dataout : wire_ni11ll_dataout;
	assign		wire_n0O0il_dataout = (nl00i1O === 1'b1) ? wire_ni1lOO_dataout : wire_ni11lO_dataout;
	assign		wire_n0O0iO_dataout = (nl00i1O === 1'b1) ? wire_ni1O1i_dataout : wire_ni11Oi_dataout;
	assign		wire_n0O0l_dataout = ((~ n110O) === 1'b1) ? wire_ni1Oi_dataout : wire_niOil_o;
	assign		wire_n0O0li_dataout = (nl00i1O === 1'b1) ? wire_ni1O1l_dataout : wire_ni11Ol_dataout;
	assign		wire_n0O0ll_dataout = (nl00i1O === 1'b1) ? wire_ni1O1O_dataout : wire_ni11OO_dataout;
	assign		wire_n0O0lO_dataout = (nl00i1O === 1'b1) ? wire_ni1O0i_dataout : wire_ni101i_dataout;
	assign		wire_n0O0O_dataout = ((~ n110O) === 1'b1) ? wire_ni1Ol_dataout : wire_n0OOO_dataout;
	assign		wire_n0O0Oi_dataout = (nl00i1O === 1'b1) ? wire_ni1O0l_dataout : wire_ni101l_dataout;
	assign		wire_n0O0Ol_dataout = (nl00i1O === 1'b1) ? wire_ni1O0O_dataout : wire_ni101O_dataout;
	assign		wire_n0O0OO_dataout = (nl00i1O === 1'b1) ? wire_ni1Oii_dataout : wire_ni100i_dataout;
	assign		wire_n0O10i_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[1] : wire_n0OOil_dataout;
	assign		wire_n0O10l_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[2] : wire_n0OOiO_dataout;
	assign		wire_n0O10O_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[3] : wire_n0OOli_dataout;
	and(wire_n0O11i_dataout, nlO01O, ~(nl00i0l));
	and(wire_n0O11l_dataout, nlO00i, ~(nl00i0l));
	assign		wire_n0O11O_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[0] : wire_n0OOii_dataout;
	assign		wire_n0O1i_dataout = (rendec_data_sel_rx === 1'b1) ? sync_resync_delay[0] : n1ilO;
	assign		wire_n0O1ii_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[4] : wire_n0OOll_dataout;
	assign		wire_n0O1il_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[5] : wire_n0OOlO_dataout;
	assign		wire_n0O1iO_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[6] : wire_n0OOOi_dataout;
	assign		wire_n0O1l_dataout = (rendec_data_sel_rx === 1'b1) ? sync_resync_delay[1] : n1iOi;
	assign		wire_n0O1li_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[7] : wire_n0OOOl_dataout;
	assign		wire_n0O1ll_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[8] : wire_n0OOOO_dataout;
	assign		wire_n0O1lO_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[9] : wire_ni111i_dataout;
	assign		wire_n0O1Oi_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[10] : wire_ni111l_dataout;
	assign		wire_n0O1Ol_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[11] : wire_ni111O_dataout;
	assign		wire_n0O1OO_dataout = (nl00i1O === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[12] : wire_ni110i_dataout;
	assign		wire_n0Oi_dataout = (rrxfifo_dis === 1'b1) ? wire_n10i1i_o : nl0O1Ol;
	assign		wire_n0Oi0i_dataout = (nl00i1O === 1'b1) ? wire_ni1Oll_dataout : wire_ni10il_dataout;
	assign		wire_n0Oi0l_dataout = (nl00i1O === 1'b1) ? wire_ni1OlO_dataout : wire_ni10iO_dataout;
	assign		wire_n0Oi0O_dataout = (nl00i1O === 1'b1) ? wire_ni1OOi_dataout : wire_ni10li_dataout;
	assign		wire_n0Oi1i_dataout = (nl00i1O === 1'b1) ? wire_ni1Oil_dataout : wire_ni100l_dataout;
	assign		wire_n0Oi1l_dataout = (nl00i1O === 1'b1) ? wire_ni1OiO_dataout : wire_ni100O_dataout;
	assign		wire_n0Oi1O_dataout = (nl00i1O === 1'b1) ? wire_ni1Oli_dataout : wire_ni10ii_dataout;
	assign		wire_n0Oii_dataout = ((~ n110O) === 1'b1) ? wire_ni1OO_dataout : wire_ni11i_dataout;
	assign		wire_n0Oiii_dataout = (nl00i1O === 1'b1) ? wire_ni1OOl_dataout : wire_ni10ll_dataout;
	assign		wire_n0Oiil_dataout = (nl00i1O === 1'b1) ? wire_ni1OOO_dataout : wire_ni10lO_dataout;
	assign		wire_n0OiiO_dataout = (nl00i1O === 1'b1) ? wire_ni011i_dataout : wire_ni10Oi_dataout;
	assign		wire_n0Oil_dataout = ((~ n110O) === 1'b1) ? wire_ni01i_dataout : wire_ni11l_dataout;
	assign		wire_n0Oili_dataout = (nl00i1O === 1'b1) ? wire_ni011l_dataout : wire_ni10Ol_dataout;
	assign		wire_n0Oill_dataout = (nl00i1O === 1'b1) ? wire_ni011O_dataout : wire_ni10OO_dataout;
	assign		wire_n0OilO_dataout = (nl00i1O === 1'b1) ? wire_ni010i_dataout : wire_ni1i1i_dataout;
	assign		wire_n0OiO_dataout = ((~ n110O) === 1'b1) ? wire_ni01l_dataout : wire_ni11O_dataout;
	assign		wire_n0OiOi_dataout = (nl00i1O === 1'b1) ? wire_ni010l_dataout : wire_ni1i1l_dataout;
	assign		wire_n0OiOl_dataout = (nl00i1O === 1'b1) ? wire_ni010O_dataout : wire_ni1i1O_dataout;
	assign		wire_n0OiOO_dataout = (nl00i1O === 1'b1) ? wire_ni01ii_dataout : wire_ni1i0i_dataout;
	assign		wire_n0Ol_dataout = (rrxfifo_dis === 1'b1) ? wire_n10i1l_o : nl0O1OO;
	assign		wire_n0Ol0i_dataout = (nl00i1O === 1'b1) ? wire_ni01ll_dataout : wire_ni1iil_dataout;
	assign		wire_n0Ol0l_dataout = (nl00i1O === 1'b1) ? wire_ni01lO_dataout : wire_ni1iiO_dataout;
	assign		wire_n0Ol0O_dataout = (nl00i1O === 1'b1) ? wire_ni01Oi_dataout : wire_ni1ili_dataout;
	assign		wire_n0Ol1i_dataout = (nl00i1O === 1'b1) ? wire_ni01il_dataout : wire_ni1i0l_dataout;
	assign		wire_n0Ol1l_dataout = (nl00i1O === 1'b1) ? wire_ni01iO_dataout : wire_ni1i0O_dataout;
	assign		wire_n0Ol1O_dataout = (nl00i1O === 1'b1) ? wire_ni01li_dataout : wire_ni1iii_dataout;
	assign		wire_n0Oli_dataout = ((~ n110O) === 1'b1) ? wire_ni01O_dataout : wire_ni10i_dataout;
	assign		wire_n0Olii_dataout = (nl00i1O === 1'b1) ? wire_ni01Ol_dataout : wire_ni1ill_dataout;
	assign		wire_n0Olil_dataout = (nl00i1O === 1'b1) ? wire_ni01OO_dataout : wire_ni1ilO_dataout;
	assign		wire_n0OliO_dataout = (nl00i1O === 1'b1) ? wire_ni001i_dataout : wire_ni1iOi_dataout;
	assign		wire_n0Oll_dataout = ((~ n110O) === 1'b1) ? wire_ni00i_dataout : wire_ni10l_dataout;
	assign		wire_n0Olli_dataout = (nl00i1O === 1'b1) ? wire_ni001l_dataout : wire_ni1iOl_dataout;
	assign		wire_n0Olll_dataout = (nl00i1O === 1'b1) ? wire_ni001O_dataout : wire_ni1iOO_dataout;
	assign		wire_n0OllO_dataout = (nl00i1O === 1'b1) ? wire_ni000i_dataout : wire_ni1l1i_dataout;
	assign		wire_n0OlO_dataout = ((~ n110O) === 1'b1) ? wire_ni00l_dataout : wire_ni10O_dataout;
	assign		wire_n0OlOi_dataout = (nl00i1O === 1'b1) ? wire_ni000l_dataout : wire_ni1l1l_dataout;
	assign		wire_n0OlOl_dataout = (nl00i1O === 1'b1) ? wire_ni000O_dataout : wire_ni1l1O_dataout;
	assign		wire_n0OlOO_dataout = (nl00i1O === 1'b1) ? wire_ni00ii_dataout : wire_ni1l0i_dataout;
	assign		wire_n0OO_dataout = (rrxfifo_dis === 1'b1) ? wire_n10i1O_o : nl0O01i;
	assign		wire_n0OO0i_dataout = (nl00i1O === 1'b1) ? wire_ni00ll_dataout : wire_ni1lil_dataout;
	assign		wire_n0OO0l_dataout = (nl00i1O === 1'b1) ? wire_ni00lO_dataout : wire_ni1liO_dataout;
	assign		wire_n0OO0O_dataout = (nl00i1O === 1'b1) ? wire_ni00Oi_dataout : wire_ni1lli_dataout;
	assign		wire_n0OO1i_dataout = (nl00i1O === 1'b1) ? wire_ni00il_dataout : wire_ni1l0l_dataout;
	assign		wire_n0OO1l_dataout = (nl00i1O === 1'b1) ? wire_ni00iO_dataout : wire_ni1l0O_dataout;
	assign		wire_n0OO1O_dataout = (nl00i1O === 1'b1) ? wire_ni00li_dataout : wire_ni1lii_dataout;
	assign		wire_n0OOi_dataout = ((~ n110O) === 1'b1) ? wire_ni00O_dataout : wire_ni1ii_dataout;
	assign		wire_n0OOii_dataout = (nl00i0i === 1'b1) ? nlll1l : wire_nl0l0Ol_byte_des_fifo_data_in[0];
	assign		wire_n0OOil_dataout = (nl00i0i === 1'b1) ? nlll1O : wire_nl0l0Ol_byte_des_fifo_data_in[1];
	assign		wire_n0OOiO_dataout = (nl00i0i === 1'b1) ? nlll0i : wire_nl0l0Ol_byte_des_fifo_data_in[2];
	assign		wire_n0OOl_dataout = ((~ n110O) === 1'b1) ? wire_ni0ii_dataout : wire_ni1il_dataout;
	assign		wire_n0OOli_dataout = (nl00i0i === 1'b1) ? nlll0l : wire_nl0l0Ol_byte_des_fifo_data_in[3];
	assign		wire_n0OOll_dataout = (nl00i0i === 1'b1) ? nlll0O : wire_nl0l0Ol_byte_des_fifo_data_in[4];
	assign		wire_n0OOlO_dataout = (nl00i0i === 1'b1) ? nlllii : wire_nl0l0Ol_byte_des_fifo_data_in[5];
	assign		wire_n0OOO_dataout = (nl0i00l === 1'b1) ? rclkcmpinsertpad : rx_data_dt[8];
	assign		wire_n0OOOi_dataout = (nl00i0i === 1'b1) ? nlllil : wire_nl0l0Ol_byte_des_fifo_data_in[6];
	assign		wire_n0OOOl_dataout = (nl00i0i === 1'b1) ? nllliO : wire_nl0l0Ol_byte_des_fifo_data_in[7];
	assign		wire_n0OOOO_dataout = (nl00i0i === 1'b1) ? nlllli : wire_nl0l0Ol_byte_des_fifo_data_in[8];
	and(wire_n1010i_dataout, wire_n1010l_dataout, n11Oll);
	or(wire_n1010l_dataout, nlOliO, n1010O);
	and(wire_n1011i_dataout, wire_n1011l_dataout, n1010O);
	assign		wire_n1011l_dataout = (rphfifo_master_sel_rx === 1'b1) ? wire_n1011O_dataout : (~ rx_we_in_q0_ch0);
	assign		wire_n1011O_dataout = (indv_rx === 1'b1) ? (~ n11OOl) : (~ rx_we_in_ch0);
	or(wire_n101ii_dataout, nlillO, (wire_nlOilO_dataout & wire_nl01ll_dataout));
	assign		wire_n10i_dataout = (rrxfifo_dis === 1'b1) ? wire_n10l0i_o : nl0Oi1l;
	assign		wire_n10l_dataout = (rrxfifo_dis === 1'b1) ? wire_n10O0l_o : nl0Ol1O;
	assign		wire_n10O_dataout = (rrxfifo_dis === 1'b1) ? wire_n101iO_o : nl0llOi;
	assign		wire_n10OOi_dataout = (nl0i10i === 1'b1) ? nlli1i : wire_n1iO1l_dataout;
	assign		wire_n10OOl_dataout = (nl0i10i === 1'b1) ? nlli1l : wire_n1iO1O_dataout;
	assign		wire_n10OOO_dataout = (nl0i10i === 1'b1) ? nlli1O : wire_n1iO0i_dataout;
	and(wire_n111l_dataout, n111i, ~(scan_mode));
	assign		wire_n11i_dataout = (rrxfifo_dis === 1'b1) ? wire_n10i0i_o : nl0O01l;
	assign		wire_n11l_dataout = (rrxfifo_dis === 1'b1) ? wire_n1001l_o : nl0lOOO;
	assign		wire_n11O_dataout = (rrxfifo_dis === 1'b1) ? wire_n10i1O_o : nl0O01i;
	assign		wire_n1i_dataout = (rrxfifo_dis === 1'b1) ? wire_n10O0i_o : nl0Ol1l;
	assign		wire_n1i00i_dataout = (nl0i10i === 1'b1) ? wire_n1lllO_dataout : wire_n1l1il_dataout;
	assign		wire_n1i00l_dataout = (nl0i10i === 1'b1) ? wire_n1llOi_dataout : wire_n1l1iO_dataout;
	assign		wire_n1i00O_dataout = (nl0i10i === 1'b1) ? wire_n1llOl_dataout : wire_n1l1li_dataout;
	assign		wire_n1i01i_dataout = (nl0i10i === 1'b1) ? wire_n1lliO_dataout : wire_n1l10l_dataout;
	assign		wire_n1i01l_dataout = (nl0i10i === 1'b1) ? wire_n1llli_dataout : wire_n1l10O_dataout;
	assign		wire_n1i01O_dataout = (nl0i10i === 1'b1) ? wire_n1llll_dataout : wire_n1l1ii_dataout;
	assign		wire_n1i0ii_dataout = (nl0i10i === 1'b1) ? wire_n1llOO_dataout : wire_n1l1ll_dataout;
	assign		wire_n1i0il_dataout = (nl0i10i === 1'b1) ? wire_n1lO1i_dataout : wire_n1l1lO_dataout;
	assign		wire_n1i0iO_dataout = (nl0i10i === 1'b1) ? wire_n1lO1l_dataout : wire_n1l1Oi_dataout;
	assign		wire_n1i0li_dataout = (nl0i10i === 1'b1) ? wire_n1lO1O_dataout : wire_n1l1Ol_dataout;
	assign		wire_n1i0ll_dataout = (nl0i10i === 1'b1) ? wire_n1lO0i_dataout : wire_n1l1OO_dataout;
	assign		wire_n1i0lO_dataout = (nl0i10i === 1'b1) ? wire_n1lO0l_dataout : wire_n1l01i_dataout;
	assign		wire_n1i0Oi_dataout = (nl0i10i === 1'b1) ? wire_n1lO0O_dataout : wire_n1l01l_dataout;
	assign		wire_n1i0Ol_dataout = (nl0i10i === 1'b1) ? wire_n1lOii_dataout : wire_n1l01O_dataout;
	assign		wire_n1i0OO_dataout = (nl0i10i === 1'b1) ? wire_n1lOil_dataout : wire_n1l00i_dataout;
	assign		wire_n1i10i_dataout = (nl0i10i === 1'b1) ? nlliii : wire_n1iOil_dataout;
	assign		wire_n1i10l_dataout = (nl0i10i === 1'b1) ? nlliil : wire_n1iOiO_dataout;
	assign		wire_n1i10O_dataout = (nl0i10i === 1'b1) ? nlliiO : wire_n1iOli_dataout;
	assign		wire_n1i11i_dataout = (nl0i10i === 1'b1) ? nlli0i : wire_n1iO0l_dataout;
	assign		wire_n1i11l_dataout = (nl0i10i === 1'b1) ? nlli0l : wire_n1iO0O_dataout;
	assign		wire_n1i11O_dataout = (nl0i10i === 1'b1) ? nlli0O : wire_n1iOii_dataout;
	assign		wire_n1i1ii_dataout = (nl0i10i === 1'b1) ? nllili : wire_n1iOll_dataout;
	assign		wire_n1i1il_dataout = (nl0i10i === 1'b1) ? nllill : wire_n1iOlO_dataout;
	assign		wire_n1i1iO_dataout = (nl0i10i === 1'b1) ? nllilO : wire_n1iOOi_dataout;
	assign		wire_n1i1li_dataout = (nl0i10i === 1'b1) ? nlliOi : wire_n1iOOl_dataout;
	assign		wire_n1i1ll_dataout = (nl0i10i === 1'b1) ? nlliOl : wire_n1iOOO_dataout;
	assign		wire_n1i1lO_dataout = (nl0i10i === 1'b1) ? nlliOO : wire_n1l11i_dataout;
	assign		wire_n1i1Oi_dataout = (nl0i10i === 1'b1) ? nlll1i : wire_n1l11l_dataout;
	assign		wire_n1i1Ol_dataout = (nl0i10i === 1'b1) ? wire_n1llii_dataout : wire_n1l11O_dataout;
	assign		wire_n1i1OO_dataout = (nl0i10i === 1'b1) ? wire_n1llil_dataout : wire_n1l10i_dataout;
	assign		wire_n1ii_dataout = (rrxfifo_dis === 1'b1) ? wire_n101li_o : nl0lOil;
	assign		wire_n1ii0i_dataout = (nl0i10i === 1'b1) ? wire_n1lOlO_dataout : wire_n1l0il_dataout;
	assign		wire_n1ii0l_dataout = (nl0i10i === 1'b1) ? wire_n1lOOi_dataout : wire_n1l0iO_dataout;
	assign		wire_n1ii0O_dataout = (nl0i10i === 1'b1) ? wire_n1lOOl_dataout : wire_n1l0li_dataout;
	assign		wire_n1ii1i_dataout = (nl0i10i === 1'b1) ? wire_n1lOiO_dataout : wire_n1l00l_dataout;
	assign		wire_n1ii1l_dataout = (nl0i10i === 1'b1) ? wire_n1lOli_dataout : wire_n1l00O_dataout;
	assign		wire_n1ii1O_dataout = (nl0i10i === 1'b1) ? wire_n1lOll_dataout : wire_n1l0ii_dataout;
	assign		wire_n1iiii_dataout = (nl0i10i === 1'b1) ? wire_n1lOOO_dataout : wire_n1l0ll_dataout;
	assign		wire_n1iiil_dataout = (nl0i10i === 1'b1) ? wire_n1O11i_dataout : wire_n1l0lO_dataout;
	assign		wire_n1iiiO_dataout = (nl0i10i === 1'b1) ? wire_n1O11l_dataout : wire_n1l0Oi_dataout;
	assign		wire_n1iili_dataout = (nl0i10i === 1'b1) ? wire_n1O11O_dataout : wire_n1l0Ol_dataout;
	assign		wire_n1iill_dataout = (nl0i10i === 1'b1) ? wire_n1O10i_dataout : wire_n1l0OO_dataout;
	assign		wire_n1iilO_dataout = (nl0i10i === 1'b1) ? wire_n1O10l_dataout : wire_n1li1i_dataout;
	assign		wire_n1iiOi_dataout = (nl0i10i === 1'b1) ? wire_n1O10O_dataout : wire_n1li1l_dataout;
	assign		wire_n1iiOl_dataout = (nl0i10i === 1'b1) ? wire_n1O1ii_dataout : wire_n1li1O_dataout;
	assign		wire_n1iiOO_dataout = (nl0i10i === 1'b1) ? wire_n1O1il_dataout : wire_n1li0i_dataout;
	assign		wire_n1il_dataout = (rrxfifo_dis === 1'b1) ? wire_n101ll_o : nl0lOiO;
	assign		wire_n1il0i_dataout = (nl0i10i === 1'b1) ? wire_n1O1lO_dataout : wire_n1liil_dataout;
	assign		wire_n1il0l_dataout = (nl0i10i === 1'b1) ? wire_n1O1Oi_dataout : wire_n1liiO_dataout;
	assign		wire_n1il0O_dataout = (nl0i10i === 1'b1) ? wire_n1O1Ol_dataout : wire_n1lili_dataout;
	assign		wire_n1il1i_dataout = (nl0i10i === 1'b1) ? wire_n1O1iO_dataout : wire_n1li0l_dataout;
	assign		wire_n1il1l_dataout = (nl0i10i === 1'b1) ? wire_n1O1li_dataout : wire_n1li0O_dataout;
	assign		wire_n1il1O_dataout = (nl0i10i === 1'b1) ? wire_n1O1ll_dataout : wire_n1liii_dataout;
	assign		wire_n1ilii_dataout = (nl0i10i === 1'b1) ? wire_n1O1OO_dataout : wire_n1lill_dataout;
	assign		wire_n1ilil_dataout = (nl0i10i === 1'b1) ? wire_n1O01i_dataout : wire_n1lilO_dataout;
	assign		wire_n1iliO_dataout = (nl0i10i === 1'b1) ? wire_n1O01l_dataout : wire_n1liOi_dataout;
	assign		wire_n1illi_dataout = (nl0i10i === 1'b1) ? wire_n1O01O_dataout : wire_n1liOl_dataout;
	assign		wire_n1illl_dataout = (nl0i10i === 1'b1) ? wire_n1O00i_dataout : wire_n1liOO_dataout;
	assign		wire_n1illO_dataout = (nl0i10i === 1'b1) ? wire_n1O00l_dataout : wire_n1ll1i_dataout;
	assign		wire_n1ilOi_dataout = (nl0i10i === 1'b1) ? wire_n1O00O_dataout : wire_n1ll1l_dataout;
	assign		wire_n1ilOl_dataout = (nl0i10i === 1'b1) ? wire_n1O0ii_dataout : wire_n1ll1O_dataout;
	assign		wire_n1ilOO_dataout = (nl0i10i === 1'b1) ? wire_n1O0il_dataout : wire_n1ll0i_dataout;
	assign		wire_n1iO_dataout = (rrxfifo_dis === 1'b1) ? wire_n101lO_o : nl0lOli;
	assign		wire_n1iO0i_dataout = ((~ nl00i1i) === 1'b1) ? nll11i : nlli1O;
	assign		wire_n1iO0l_dataout = ((~ nl00i1i) === 1'b1) ? nll11l : nlli0i;
	assign		wire_n1iO0O_dataout = ((~ nl00i1i) === 1'b1) ? nll11O : nlli0l;
	assign		wire_n1iO1i_dataout = (nl0i10i === 1'b1) ? wire_n1O0iO_dataout : wire_n1ll0l_dataout;
	assign		wire_n1iO1l_dataout = ((~ nl00i1i) === 1'b1) ? nliOOl : nlli1i;
	assign		wire_n1iO1O_dataout = ((~ nl00i1i) === 1'b1) ? nliOOO : nlli1l;
	assign		wire_n1iOii_dataout = ((~ nl00i1i) === 1'b1) ? nll10i : nlli0O;
	assign		wire_n1iOil_dataout = ((~ nl00i1i) === 1'b1) ? nll10l : nlliii;
	assign		wire_n1iOiO_dataout = ((~ nl00i1i) === 1'b1) ? nll10O : nlliil;
	assign		wire_n1iOli_dataout = ((~ nl00i1i) === 1'b1) ? nll1ii : nlliiO;
	assign		wire_n1iOll_dataout = ((~ nl00i1i) === 1'b1) ? nll1il : nllili;
	assign		wire_n1iOlO_dataout = ((~ nl00i1i) === 1'b1) ? nll1iO : nllill;
	assign		wire_n1iOOi_dataout = ((~ nl00i1i) === 1'b1) ? nll1li : nllilO;
	assign		wire_n1iOOl_dataout = ((~ nl00i1i) === 1'b1) ? nll1ll : nlliOi;
	assign		wire_n1iOOO_dataout = ((~ nl00i1i) === 1'b1) ? nll1lO : nlliOl;
	assign		wire_n1l_dataout = (rrxfifo_dis === 1'b1) ? wire_n10O0l_o : nl0Ol1O;
	assign		wire_n1l00i_dataout = ((~ nl00i1i) === 1'b1) ? nlli1i : nllO1O;
	assign		wire_n1l00l_dataout = ((~ nl00i1i) === 1'b1) ? nlli1l : nllO0i;
	assign		wire_n1l00O_dataout = ((~ nl00i1i) === 1'b1) ? nlli1O : nllO0l;
	assign		wire_n1l01i_dataout = ((~ nl00i1i) === 1'b1) ? nll0Oi : nlllOO;
	assign		wire_n1l01l_dataout = ((~ nl00i1i) === 1'b1) ? nll0Ol : nllO1i;
	assign		wire_n1l01O_dataout = ((~ nl00i1i) === 1'b1) ? nll0OO : nllO1l;
	assign		wire_n1l0ii_dataout = ((~ nl00i1i) === 1'b1) ? nlli0i : nllO0O;
	assign		wire_n1l0il_dataout = ((~ nl00i1i) === 1'b1) ? nlli0l : nllOii;
	assign		wire_n1l0iO_dataout = ((~ nl00i1i) === 1'b1) ? nlli0O : nllOil;
	assign		wire_n1l0li_dataout = ((~ nl00i1i) === 1'b1) ? nlliii : nllOiO;
	assign		wire_n1l0ll_dataout = ((~ nl00i1i) === 1'b1) ? nlliil : nllOli;
	assign		wire_n1l0lO_dataout = ((~ nl00i1i) === 1'b1) ? nlliiO : nllOll;
	assign		wire_n1l0Oi_dataout = ((~ nl00i1i) === 1'b1) ? nllili : nllOlO;
	assign		wire_n1l0Ol_dataout = ((~ nl00i1i) === 1'b1) ? nllill : nllOOi;
	assign		wire_n1l0OO_dataout = ((~ nl00i1i) === 1'b1) ? nllilO : nllOOl;
	assign		wire_n1l10i_dataout = ((~ nl00i1i) === 1'b1) ? nll01i : nlll1O;
	assign		wire_n1l10l_dataout = ((~ nl00i1i) === 1'b1) ? nll01l : nlll0i;
	assign		wire_n1l10O_dataout = ((~ nl00i1i) === 1'b1) ? nll01O : nlll0l;
	assign		wire_n1l11i_dataout = ((~ nl00i1i) === 1'b1) ? nll1Oi : nlliOO;
	assign		wire_n1l11l_dataout = ((~ nl00i1i) === 1'b1) ? nll1Ol : nlll1i;
	assign		wire_n1l11O_dataout = ((~ nl00i1i) === 1'b1) ? nll1OO : nlll1l;
	assign		wire_n1l1ii_dataout = ((~ nl00i1i) === 1'b1) ? nll00i : nlll0O;
	assign		wire_n1l1il_dataout = ((~ nl00i1i) === 1'b1) ? nll00l : nlllii;
	assign		wire_n1l1iO_dataout = ((~ nl00i1i) === 1'b1) ? nll00O : nlllil;
	assign		wire_n1l1li_dataout = ((~ nl00i1i) === 1'b1) ? nll0ii : nllliO;
	assign		wire_n1l1ll_dataout = ((~ nl00i1i) === 1'b1) ? nll0il : nlllli;
	assign		wire_n1l1lO_dataout = ((~ nl00i1i) === 1'b1) ? nll0iO : nlllll;
	assign		wire_n1l1Oi_dataout = ((~ nl00i1i) === 1'b1) ? nll0li : nllllO;
	assign		wire_n1l1Ol_dataout = ((~ nl00i1i) === 1'b1) ? nll0ll : nlllOi;
	assign		wire_n1l1OO_dataout = ((~ nl00i1i) === 1'b1) ? nll0lO : nlllOl;
	assign		wire_n1li_dataout = (rrxfifo_dis === 1'b1) ? wire_n101Oi_o : nl0lOll;
	assign		wire_n1li0i_dataout = ((~ nl00i1i) === 1'b1) ? nlll1i : nlO11O;
	assign		wire_n1li0l_dataout = ((~ nl00i1i) === 1'b1) ? nlll1l : nlO10i;
	assign		wire_n1li0O_dataout = ((~ nl00i1i) === 1'b1) ? nlll1O : nlO10l;
	assign		wire_n1li1i_dataout = ((~ nl00i1i) === 1'b1) ? nlliOi : nllOOO;
	assign		wire_n1li1l_dataout = ((~ nl00i1i) === 1'b1) ? nlliOl : nlO11i;
	assign		wire_n1li1O_dataout = ((~ nl00i1i) === 1'b1) ? nlliOO : nlO11l;
	assign		wire_n1liii_dataout = ((~ nl00i1i) === 1'b1) ? nlll0i : nlO10O;
	assign		wire_n1liil_dataout = ((~ nl00i1i) === 1'b1) ? nlll0l : nlO1ii;
	assign		wire_n1liiO_dataout = ((~ nl00i1i) === 1'b1) ? nlll0O : nlO1il;
	assign		wire_n1lili_dataout = ((~ nl00i1i) === 1'b1) ? nlllii : nlO1iO;
	assign		wire_n1lill_dataout = ((~ nl00i1i) === 1'b1) ? nlllil : nlO1li;
	assign		wire_n1lilO_dataout = ((~ nl00i1i) === 1'b1) ? nllliO : nlO1ll;
	assign		wire_n1liOi_dataout = ((~ nl00i1i) === 1'b1) ? nlllli : nlO1lO;
	assign		wire_n1liOl_dataout = ((~ nl00i1i) === 1'b1) ? nlllll : nlO1Oi;
	assign		wire_n1liOO_dataout = ((~ nl00i1i) === 1'b1) ? nllllO : nlO1Ol;
	assign		wire_n1ll_dataout = (rrxfifo_dis === 1'b1) ? wire_n101Ol_o : nl0lOlO;
	assign		wire_n1ll0i_dataout = ((~ nl00i1i) === 1'b1) ? nllO1i : nlO01O;
	assign		wire_n1ll0l_dataout = ((~ nl00i1i) === 1'b1) ? nllO1l : nlO00i;
	assign		wire_n1ll1i_dataout = ((~ nl00i1i) === 1'b1) ? nlllOi : nlO1OO;
	assign		wire_n1ll1l_dataout = ((~ nl00i1i) === 1'b1) ? nlllOl : nlO01i;
	assign		wire_n1ll1O_dataout = ((~ nl00i1i) === 1'b1) ? nlllOO : nlO01l;
	and(wire_n1llii_dataout, nlll1l, ~((~ nl00i1l)));
	and(wire_n1llil_dataout, nlll1O, ~((~ nl00i1l)));
	and(wire_n1lliO_dataout, nlll0i, ~((~ nl00i1l)));
	and(wire_n1llli_dataout, nlll0l, ~((~ nl00i1l)));
	and(wire_n1llll_dataout, nlll0O, ~((~ nl00i1l)));
	and(wire_n1lllO_dataout, nlllii, ~((~ nl00i1l)));
	and(wire_n1llOi_dataout, nlllil, ~((~ nl00i1l)));
	and(wire_n1llOl_dataout, nllliO, ~((~ nl00i1l)));
	and(wire_n1llOO_dataout, nlllli, ~((~ nl00i1l)));
	assign		wire_n1lO_dataout = (rrxfifo_dis === 1'b1) ? wire_n101OO_o : nl0lOOi;
	and(wire_n1lO0i_dataout, nlllOl, ~((~ nl00i1l)));
	and(wire_n1lO0l_dataout, nlllOO, ~((~ nl00i1l)));
	and(wire_n1lO0O_dataout, nllO1i, ~((~ nl00i1l)));
	and(wire_n1lO1i_dataout, nlllll, ~((~ nl00i1l)));
	and(wire_n1lO1l_dataout, nllllO, ~((~ nl00i1l)));
	and(wire_n1lO1O_dataout, nlllOi, ~((~ nl00i1l)));
	and(wire_n1lOii_dataout, nllO1l, ~((~ nl00i1l)));
	assign		wire_n1lOil_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[0] : nllO1O;
	assign		wire_n1lOiO_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[1] : nllO0i;
	assign		wire_n1lOli_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[2] : nllO0l;
	assign		wire_n1lOll_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[3] : nllO0O;
	assign		wire_n1lOlO_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[4] : nllOii;
	assign		wire_n1lOOi_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[5] : nllOil;
	assign		wire_n1lOOl_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[6] : nllOiO;
	assign		wire_n1lOOO_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[7] : nllOli;
	assign		wire_n1O_dataout = (rrxfifo_dis === 1'b1) ? wire_n10O0O_o : nl0Ol0i;
	and(wire_n1O00i_dataout, nlO1Ol, ~((~ nl00i1l)));
	and(wire_n1O00l_dataout, nlO1OO, ~((~ nl00i1l)));
	and(wire_n1O00O_dataout, nlO01i, ~((~ nl00i1l)));
	and(wire_n1O01i_dataout, nlO1ll, ~((~ nl00i1l)));
	and(wire_n1O01l_dataout, nlO1lO, ~((~ nl00i1l)));
	and(wire_n1O01O_dataout, nlO1Oi, ~((~ nl00i1l)));
	and(wire_n1O0ii_dataout, nlO01l, ~((~ nl00i1l)));
	and(wire_n1O0il_dataout, nlO01O, ~((~ nl00i1l)));
	and(wire_n1O0iO_dataout, nlO00i, ~((~ nl00i1l)));
	or(wire_n1O0l_dataout, wire_n1O0O_dataout, n11ii);
	assign		wire_n1O0ll_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[0] : wire_n011OO_dataout;
	assign		wire_n1O0lO_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[1] : wire_n0101i_dataout;
	assign		wire_n1O0O_dataout = (rwa_6g_en === 1'b1) ? (sync_resync_delay[0] | sync_resync_delay[1]) : wire_n1Oii_dataout;
	assign		wire_n1O0Oi_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[2] : wire_n0101l_dataout;
	assign		wire_n1O0Ol_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[3] : wire_n0101O_dataout;
	assign		wire_n1O0OO_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[4] : wire_n0100i_dataout;
	and(wire_n1O10i_dataout, nllOOl, ~((~ nl00i1l)));
	and(wire_n1O10l_dataout, nllOOO, ~((~ nl00i1l)));
	and(wire_n1O10O_dataout, nlO11i, ~((~ nl00i1l)));
	assign		wire_n1O11i_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[8] : nllOll;
	assign		wire_n1O11l_dataout = ((~ nl00i1l) === 1'b1) ? rbytordpadval[9] : nllOlO;
	assign		wire_n1O11O_dataout = ((~ nl00i1l) === 1'b1) ? nllill : nllOOi;
	and(wire_n1O1ii_dataout, nlO11l, ~((~ nl00i1l)));
	and(wire_n1O1il_dataout, nlO11O, ~((~ nl00i1l)));
	and(wire_n1O1iO_dataout, nlO10i, ~((~ nl00i1l)));
	and(wire_n1O1li_dataout, nlO10l, ~((~ nl00i1l)));
	and(wire_n1O1ll_dataout, nlO10O, ~((~ nl00i1l)));
	and(wire_n1O1lO_dataout, nlO1ii, ~((~ nl00i1l)));
	and(wire_n1O1Oi_dataout, nlO1il, ~((~ nl00i1l)));
	and(wire_n1O1Ol_dataout, nlO1iO, ~((~ nl00i1l)));
	and(wire_n1O1OO_dataout, nlO1li, ~((~ nl00i1l)));
	assign		wire_n1Oi_dataout = (rrxfifo_dis === 1'b1) ? wire_n1001i_o : nl0lOOl;
	assign		wire_n1Oi0i_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[8] : wire_n010il_dataout;
	assign		wire_n1Oi0l_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[9] : wire_n010iO_dataout;
	assign		wire_n1Oi0O_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[10] : wire_n010li_dataout;
	assign		wire_n1Oi1i_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[5] : wire_n0100l_dataout;
	assign		wire_n1Oi1l_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[6] : wire_n0100O_dataout;
	assign		wire_n1Oi1O_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[7] : wire_n010ii_dataout;
	assign		wire_n1Oii_dataout = (rsync_sm_dis === 1'b1) ? wire_n1Oil_dataout : dec_data_valid_pre[0];
	assign		wire_n1Oiii_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[11] : wire_n010ll_dataout;
	assign		wire_n1Oiil_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[12] : wire_n010lO_dataout;
	assign		wire_n1OiiO_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[13] : wire_n010Oi_dataout;
	assign		wire_n1Oil_dataout = (((~ rpmadatawidth) & tenb_data[8]) === 1'b1) ? sync_resync_pre[0] : sync_resync_delay[0];
	assign		wire_n1Oili_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[14] : wire_n010Ol_dataout;
	assign		wire_n1Oill_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[15] : wire_n010OO_dataout;
	assign		wire_n1OilO_dataout = (nl0i10i === 1'b1) ? wire_n0010i_dataout : wire_n01i1i_dataout;
	assign		wire_n1OiOi_dataout = (nl0i10i === 1'b1) ? wire_n0010l_dataout : wire_n01i1l_dataout;
	assign		wire_n1OiOl_dataout = (nl0i10i === 1'b1) ? wire_n0010O_dataout : wire_n01i1O_dataout;
	assign		wire_n1OiOO_dataout = (nl0i10i === 1'b1) ? wire_n001ii_dataout : wire_n01i0i_dataout;
	assign		wire_n1Ol_dataout = (rrxfifo_dis === 1'b1) ? wire_n1001l_o : nl0lOOO;
	assign		wire_n1Ol0i_dataout = (nl0i10i === 1'b1) ? wire_n001ll_dataout : wire_n01iil_dataout;
	assign		wire_n1Ol0l_dataout = (nl0i10i === 1'b1) ? wire_n001lO_dataout : wire_n01iiO_dataout;
	assign		wire_n1Ol0O_dataout = (nl0i10i === 1'b1) ? wire_n001Oi_dataout : wire_n01ili_dataout;
	assign		wire_n1Ol1i_dataout = (nl0i10i === 1'b1) ? wire_n001il_dataout : wire_n01i0l_dataout;
	assign		wire_n1Ol1l_dataout = (nl0i10i === 1'b1) ? wire_n001iO_dataout : wire_n01i0O_dataout;
	assign		wire_n1Ol1O_dataout = (nl0i10i === 1'b1) ? wire_n001li_dataout : wire_n01iii_dataout;
	assign		wire_n1Olii_dataout = (nl0i10i === 1'b1) ? wire_n001Ol_dataout : wire_n01ill_dataout;
	assign		wire_n1Olil_dataout = (nl0i10i === 1'b1) ? wire_n001OO_dataout : wire_n01ilO_dataout;
	assign		wire_n1OliO_dataout = (nl0i10i === 1'b1) ? wire_n0001i_dataout : wire_n01iOi_dataout;
	assign		wire_n1Oll_dataout = (endec_rx === 1'b1) ? wire_n0i1l_dataout : wire_n00OO_dataout;
	assign		wire_n1Olli_dataout = (nl0i10i === 1'b1) ? wire_n0001l_dataout : wire_n01iOl_dataout;
	assign		wire_n1Olll_dataout = (nl0i10i === 1'b1) ? wire_n0001O_dataout : wire_n01iOO_dataout;
	assign		wire_n1OllO_dataout = (nl0i10i === 1'b1) ? wire_n0000i_dataout : wire_n01l1i_dataout;
	assign		wire_n1OlO_dataout = (endec_rx === 1'b1) ? wire_n0i1O_dataout : wire_n00Oi_dataout;
	assign		wire_n1OlOi_dataout = (nl0i10i === 1'b1) ? wire_n0000l_dataout : wire_n01l1l_dataout;
	assign		wire_n1OlOl_dataout = (nl0i10i === 1'b1) ? wire_n0000O_dataout : wire_n01l1O_dataout;
	assign		wire_n1OlOO_dataout = (nl0i10i === 1'b1) ? wire_n000ii_dataout : wire_n01l0i_dataout;
	assign		wire_n1OO_dataout = (rrxfifo_dis === 1'b1) ? wire_n1001O_o : nl0O11i;
	assign		wire_n1OO0i_dataout = (nl0i10i === 1'b1) ? wire_n000ll_dataout : wire_n01lil_dataout;
	assign		wire_n1OO0l_dataout = (nl0i10i === 1'b1) ? wire_n000lO_dataout : wire_n01liO_dataout;
	assign		wire_n1OO0O_dataout = (nl0i10i === 1'b1) ? wire_n000Oi_dataout : wire_n01lli_dataout;
	assign		wire_n1OO1i_dataout = (nl0i10i === 1'b1) ? wire_n000il_dataout : wire_n01l0l_dataout;
	assign		wire_n1OO1l_dataout = (nl0i10i === 1'b1) ? wire_n000iO_dataout : wire_n01l0O_dataout;
	assign		wire_n1OO1O_dataout = (nl0i10i === 1'b1) ? wire_n000li_dataout : wire_n01lii_dataout;
	assign		wire_n1OOi_dataout = (endec_rx === 1'b1) ? wire_n0i0i_dataout : tenb_data[0];
	assign		wire_n1OOii_dataout = (nl0i10i === 1'b1) ? wire_n000Ol_dataout : wire_n01lll_dataout;
	assign		wire_n1OOil_dataout = (nl0i10i === 1'b1) ? wire_n000OO_dataout : wire_n01llO_dataout;
	assign		wire_n1OOiO_dataout = (nl0i10i === 1'b1) ? wire_n00i1i_dataout : wire_n01lOi_dataout;
	assign		wire_n1OOl_dataout = (endec_rx === 1'b1) ? wire_n0i0l_dataout : tenb_data[1];
	assign		wire_n1OOli_dataout = (nl0i10i === 1'b1) ? wire_n00i1l_dataout : wire_n01lOl_dataout;
	assign		wire_n1OOll_dataout = (nl0i10i === 1'b1) ? wire_n00i1O_dataout : wire_n01lOO_dataout;
	assign		wire_n1OOlO_dataout = (nl0i10i === 1'b1) ? wire_n00i0i_dataout : wire_n01O1i_dataout;
	assign		wire_n1OOO_dataout = (endec_rx === 1'b1) ? wire_n0i0O_dataout : tenb_data[2];
	assign		wire_n1OOOi_dataout = (nl0i10i === 1'b1) ? wire_n00i0l_dataout : wire_n01O1l_dataout;
	assign		wire_n1OOOl_dataout = (nl0i10i === 1'b1) ? wire_n00i0O_dataout : wire_n01O1O_dataout;
	assign		wire_n1OOOO_dataout = (nl0i10i === 1'b1) ? wire_n00iii_dataout : wire_n01O0i_dataout;
	and(wire_ni000i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[54], ~(nl00i0l));
	and(wire_ni000l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[55], ~(nl00i0l));
	and(wire_ni000O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[56], ~(nl00i0l));
	and(wire_ni001i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[51], ~(nl00i0l));
	and(wire_ni001l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[52], ~(nl00i0l));
	and(wire_ni001O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[53], ~(nl00i0l));
	and(wire_ni00i_dataout, rx_data_dt[13], ~(nl0i00O));
	and(wire_ni00ii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[57], ~(nl00i0l));
	and(wire_ni00il_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[58], ~(nl00i0l));
	and(wire_ni00iO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[59], ~(nl00i0l));
	and(wire_ni00l_dataout, rx_data_dt[14], ~(nl0i00O));
	and(wire_ni00li_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[60], ~(nl00i0l));
	and(wire_ni00ll_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[61], ~(nl00i0l));
	and(wire_ni00lO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[62], ~(nl00i0l));
	or(wire_ni00O_dataout, rx_data_dt[15], nl0i00O);
	and(wire_ni00Oi_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[63], ~(nl00i0l));
	assign		wire_ni00Ol_dataout = (nl0i10i === 1'b1) ? nlli1i : wire_nii01O_o;
	assign		wire_ni00OO_dataout = (nl0i10i === 1'b1) ? nlli1l : wire_nii00i_o;
	and(wire_ni010i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[39], ~(nl00i0l));
	and(wire_ni010l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[40], ~(nl00i0l));
	and(wire_ni010O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[41], ~(nl00i0l));
	and(wire_ni011i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[36], ~(nl00i0l));
	and(wire_ni011l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[37], ~(nl00i0l));
	and(wire_ni011O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[38], ~(nl00i0l));
	or(wire_ni01i_dataout, rx_data_dt[10], nl0i00O);
	and(wire_ni01ii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[42], ~(nl00i0l));
	and(wire_ni01il_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[43], ~(nl00i0l));
	and(wire_ni01iO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[44], ~(nl00i0l));
	or(wire_ni01l_dataout, rx_data_dt[11], nl0i00O);
	and(wire_ni01li_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[45], ~(nl00i0l));
	and(wire_ni01ll_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[46], ~(nl00i0l));
	and(wire_ni01lO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[47], ~(nl00i0l));
	or(wire_ni01O_dataout, rx_data_dt[12], nl0i00O);
	and(wire_ni01Oi_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[48], ~(nl00i0l));
	and(wire_ni01Ol_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[49], ~(nl00i0l));
	and(wire_ni01OO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[50], ~(nl00i0l));
	assign		wire_ni0i_dataout = (rrxfifo_dis === 1'b1) ? wire_n10iii_o : nl0O00l;
	assign		wire_ni0i0i_dataout = (nl0i10i === 1'b1) ? nlli0O : wire_nii0il_o;
	assign		wire_ni0i0l_dataout = (nl0i10i === 1'b1) ? nlliii : wire_nii0iO_o;
	assign		wire_ni0i0O_dataout = (nl0i10i === 1'b1) ? nlliil : wire_nii0li_o;
	assign		wire_ni0i1i_dataout = (nl0i10i === 1'b1) ? nlli1O : wire_nii00l_o;
	assign		wire_ni0i1l_dataout = (nl0i10i === 1'b1) ? nlli0i : wire_nii00O_o;
	assign		wire_ni0i1O_dataout = (nl0i10i === 1'b1) ? nlli0l : wire_nii0ii_o;
	or(wire_ni0ii_dataout, rx_control_dt[1], nl0i00O);
	assign		wire_ni0iii_dataout = (nl0i10i === 1'b1) ? nlliiO : wire_nii0ll_o;
	assign		wire_ni0iil_dataout = (nl0i10i === 1'b1) ? nllili : wire_nii0lO_o;
	assign		wire_ni0iiO_dataout = (nl0i10i === 1'b1) ? nllill : wire_nii0Oi_o;
	assign		wire_ni0ili_dataout = (nl0i10i === 1'b1) ? nllilO : wire_nii0Ol_o;
	assign		wire_ni0ill_dataout = (nl0i10i === 1'b1) ? nlliOi : wire_nii0OO_o;
	assign		wire_ni0ilO_dataout = (nl0i10i === 1'b1) ? nlliOl : wire_niii1i_o;
	assign		wire_ni0iO_dataout = ((~ n110l) === 1'b1) ? wire_nil1l_dataout : wire_nliil_o;
	assign		wire_ni0iOi_dataout = (nl0i10i === 1'b1) ? nlliOO : wire_niii1l_o;
	assign		wire_ni0iOl_dataout = (nl0i10i === 1'b1) ? nlll1i : wire_niii1O_o;
	assign		wire_ni0iOO_dataout = (nl0i10i === 1'b1) ? wire_nil1ii_dataout : wire_niii0i_o;
	assign		wire_ni0l_dataout = (rrxfifo_dis === 1'b1) ? wire_n10iil_o : nl0O00O;
	assign		wire_ni0l0i_dataout = (nl0i10i === 1'b1) ? wire_nil1ll_dataout : wire_niiiil_o;
	assign		wire_ni0l0l_dataout = (nl0i10i === 1'b1) ? wire_nil1lO_dataout : wire_niiiiO_o;
	assign		wire_ni0l0O_dataout = (nl0i10i === 1'b1) ? wire_nil1Oi_dataout : wire_niiili_o;
	assign		wire_ni0l1i_dataout = (nl0i10i === 1'b1) ? wire_nil1il_dataout : wire_niii0l_o;
	assign		wire_ni0l1l_dataout = (nl0i10i === 1'b1) ? wire_nil1iO_dataout : wire_niii0O_o;
	assign		wire_ni0l1O_dataout = (nl0i10i === 1'b1) ? wire_nil1li_dataout : wire_niiiii_o;
	assign		wire_ni0li_dataout = ((~ n110l) === 1'b1) ? wire_nil1O_dataout : wire_nii0i_dataout;
	assign		wire_ni0lii_dataout = (nl0i10i === 1'b1) ? wire_nil1Ol_dataout : wire_niiill_o;
	assign		wire_ni0lil_dataout = (nl0i10i === 1'b1) ? wire_nil1OO_dataout : wire_niiilO_o;
	assign		wire_ni0liO_dataout = (nl0i10i === 1'b1) ? wire_nil01i_dataout : wire_niiiOi_o;
	assign		wire_ni0ll_dataout = ((~ n110l) === 1'b1) ? wire_nil0i_dataout : wire_nii0l_dataout;
	assign		wire_ni0lli_dataout = (nl0i10i === 1'b1) ? wire_nil01l_dataout : wire_niiiOl_o;
	assign		wire_ni0lll_dataout = (nl0i10i === 1'b1) ? wire_nil01O_dataout : wire_niiiOO_o;
	assign		wire_ni0llO_dataout = (nl0i10i === 1'b1) ? wire_nil00i_dataout : wire_niil1i_o;
	assign		wire_ni0lO_dataout = ((~ n110l) === 1'b1) ? wire_nil0l_dataout : wire_nii0O_dataout;
	assign		wire_ni0lOi_dataout = (nl0i10i === 1'b1) ? wire_nil00l_dataout : wire_niil1l_o;
	assign		wire_ni0lOl_dataout = (nl0i10i === 1'b1) ? wire_nil00O_dataout : wire_niil1O_o;
	assign		wire_ni0lOO_dataout = (nl0i10i === 1'b1) ? wire_nil0ii_dataout : wire_niil0i_o;
	assign		wire_ni0O_dataout = (rrxfifo_dis === 1'b1) ? wire_n10iiO_o : nl0O0ii;
	assign		wire_ni0O0i_dataout = (nl0i10i === 1'b1) ? wire_nil0lO_dataout : wire_niilil_o;
	assign		wire_ni0O0l_dataout = (nl0i10i === 1'b1) ? wire_nil0Oi_dataout : wire_niiliO_o;
	assign		wire_ni0O0O_dataout = (nl0i10i === 1'b1) ? wire_nil0Ol_dataout : wire_niilli_o;
	assign		wire_ni0O1i_dataout = (nl0i10i === 1'b1) ? wire_nil0iO_dataout : wire_niil0l_o;
	assign		wire_ni0O1l_dataout = (nl0i10i === 1'b1) ? wire_nil0li_dataout : wire_niil0O_o;
	assign		wire_ni0O1O_dataout = (nl0i10i === 1'b1) ? wire_nil0ll_dataout : wire_niilii_o;
	assign		wire_ni0Oi_dataout = ((~ n110l) === 1'b1) ? wire_nil0O_dataout : wire_niiii_dataout;
	assign		wire_ni0Oii_dataout = (nl0i10i === 1'b1) ? wire_nil0OO_dataout : wire_niilll_o;
	assign		wire_ni0Oil_dataout = (nl0i10i === 1'b1) ? wire_nili1i_dataout : wire_niillO_o;
	assign		wire_ni0OiO_dataout = (nl0i10i === 1'b1) ? wire_nili1l_dataout : wire_niilOi_o;
	assign		wire_ni0Ol_dataout = ((~ n110l) === 1'b1) ? wire_nilii_dataout : wire_niiil_dataout;
	assign		wire_ni0Oli_dataout = (nl0i10i === 1'b1) ? wire_nili1O_dataout : wire_niilOl_o;
	assign		wire_ni0Oll_dataout = (nl0i10i === 1'b1) ? wire_nili0i_o : wire_niilOO_o;
	assign		wire_ni0OlO_dataout = (nl0i10i === 1'b1) ? wire_nili0l_dataout : wire_niiO1i_o;
	assign		wire_ni0OO_dataout = ((~ n110l) === 1'b1) ? wire_nilil_dataout : wire_niiiO_dataout;
	assign		wire_ni0OOi_dataout = (nl0i10i === 1'b1) ? wire_nili0O_dataout : wire_niiO1l_o;
	assign		wire_ni0OOl_dataout = (nl0i10i === 1'b1) ? wire_niliii_dataout : wire_niiO1O_o;
	assign		wire_ni0OOO_dataout = (nl0i10i === 1'b1) ? wire_niliil_dataout : wire_niiO0i_o;
	assign		wire_ni100i_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[11] : wire_nl0l0Ol_byte_des_fifo_data_in[27];
	assign		wire_ni100l_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[12] : wire_nl0l0Ol_byte_des_fifo_data_in[28];
	assign		wire_ni100O_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[13] : wire_nl0l0Ol_byte_des_fifo_data_in[29];
	assign		wire_ni101i_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[8] : wire_nl0l0Ol_byte_des_fifo_data_in[24];
	assign		wire_ni101l_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[9] : wire_nl0l0Ol_byte_des_fifo_data_in[25];
	assign		wire_ni101O_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[10] : wire_nl0l0Ol_byte_des_fifo_data_in[26];
	or(wire_ni10i_dataout, rx_data_dt[12], nl0i00l);
	assign		wire_ni10ii_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[14] : wire_nl0l0Ol_byte_des_fifo_data_in[30];
	assign		wire_ni10il_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[15] : wire_nl0l0Ol_byte_des_fifo_data_in[31];
	and(wire_ni10iO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[32], ~(nl00i0i));
	or(wire_ni10l_dataout, rx_data_dt[13], nl0i00l);
	and(wire_ni10li_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[33], ~(nl00i0i));
	and(wire_ni10ll_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[34], ~(nl00i0i));
	and(wire_ni10lO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[35], ~(nl00i0i));
	or(wire_ni10O_dataout, rx_data_dt[14], nl0i00l);
	and(wire_ni10Oi_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[36], ~(nl00i0i));
	and(wire_ni10Ol_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[37], ~(nl00i0i));
	and(wire_ni10OO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[38], ~(nl00i0i));
	assign		wire_ni110i_dataout = (nl00i0i === 1'b1) ? nlllOl : wire_nl0l0Ol_byte_des_fifo_data_in[12];
	assign		wire_ni110l_dataout = (nl00i0i === 1'b1) ? nlllOO : wire_nl0l0Ol_byte_des_fifo_data_in[13];
	assign		wire_ni110O_dataout = (nl00i0i === 1'b1) ? nllO1i : wire_nl0l0Ol_byte_des_fifo_data_in[14];
	assign		wire_ni111i_dataout = (nl00i0i === 1'b1) ? nlllll : wire_nl0l0Ol_byte_des_fifo_data_in[9];
	assign		wire_ni111l_dataout = (nl00i0i === 1'b1) ? nllllO : wire_nl0l0Ol_byte_des_fifo_data_in[10];
	assign		wire_ni111O_dataout = (nl00i0i === 1'b1) ? nlllOi : wire_nl0l0Ol_byte_des_fifo_data_in[11];
	or(wire_ni11i_dataout, rx_data_dt[9], nl0i00l);
	assign		wire_ni11ii_dataout = (nl00i0i === 1'b1) ? nllO1l : wire_nl0l0Ol_byte_des_fifo_data_in[15];
	assign		wire_ni11il_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[0] : wire_nl0l0Ol_byte_des_fifo_data_in[16];
	assign		wire_ni11iO_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[1] : wire_nl0l0Ol_byte_des_fifo_data_in[17];
	or(wire_ni11l_dataout, rx_data_dt[10], nl0i00l);
	assign		wire_ni11li_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[2] : wire_nl0l0Ol_byte_des_fifo_data_in[18];
	assign		wire_ni11ll_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[3] : wire_nl0l0Ol_byte_des_fifo_data_in[19];
	assign		wire_ni11lO_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[4] : wire_nl0l0Ol_byte_des_fifo_data_in[20];
	assign		wire_ni11O_dataout = (nl0i00l === 1'b1) ? (~ rclkcmpinsertpad) : rx_data_dt[11];
	assign		wire_ni11Oi_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[5] : wire_nl0l0Ol_byte_des_fifo_data_in[21];
	assign		wire_ni11Ol_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[6] : wire_nl0l0Ol_byte_des_fifo_data_in[22];
	assign		wire_ni11OO_dataout = (nl00i0i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[7] : wire_nl0l0Ol_byte_des_fifo_data_in[23];
	assign		wire_ni1i_dataout = (rrxfifo_dis === 1'b1) ? wire_n10i0i_o : nl0O01l;
	and(wire_ni1i0i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[42], ~(nl00i0i));
	and(wire_ni1i0l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[43], ~(nl00i0i));
	and(wire_ni1i0O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[44], ~(nl00i0i));
	and(wire_ni1i1i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[39], ~(nl00i0i));
	and(wire_ni1i1l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[40], ~(nl00i0i));
	and(wire_ni1i1O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[41], ~(nl00i0i));
	or(wire_ni1ii_dataout, rx_data_dt[15], nl0i00l);
	and(wire_ni1iii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[45], ~(nl00i0i));
	and(wire_ni1iil_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[46], ~(nl00i0i));
	and(wire_ni1iiO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[47], ~(nl00i0i));
	or(wire_ni1il_dataout, rx_control_dt[1], nl0i00l);
	and(wire_ni1ili_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[48], ~(nl00i0i));
	and(wire_ni1ill_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[49], ~(nl00i0i));
	and(wire_ni1ilO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[50], ~(nl00i0i));
	and(wire_ni1iOi_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[51], ~(nl00i0i));
	and(wire_ni1iOl_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[52], ~(nl00i0i));
	and(wire_ni1iOO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[53], ~(nl00i0i));
	assign		wire_ni1l_dataout = (rrxfifo_dis === 1'b1) ? wire_n10i0l_o : nl0O01O;
	and(wire_ni1l0i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[57], ~(nl00i0i));
	and(wire_ni1l0l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[58], ~(nl00i0i));
	and(wire_ni1l0O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[59], ~(nl00i0i));
	and(wire_ni1l1i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[54], ~(nl00i0i));
	and(wire_ni1l1l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[55], ~(nl00i0i));
	and(wire_ni1l1O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[56], ~(nl00i0i));
	and(wire_ni1lii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[60], ~(nl00i0i));
	and(wire_ni1lil_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[61], ~(nl00i0i));
	and(wire_ni1liO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[62], ~(nl00i0i));
	and(wire_ni1lli_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[63], ~(nl00i0i));
	assign		wire_ni1lll_dataout = (nl00i0l === 1'b1) ? rbytordpadval[0] : wire_nl0l0Ol_byte_des_fifo_data_in[16];
	assign		wire_ni1llO_dataout = (nl00i0l === 1'b1) ? rbytordpadval[1] : wire_nl0l0Ol_byte_des_fifo_data_in[17];
	assign		wire_ni1lOi_dataout = (nl00i0l === 1'b1) ? rbytordpadval[2] : wire_nl0l0Ol_byte_des_fifo_data_in[18];
	assign		wire_ni1lOl_dataout = (nl00i0l === 1'b1) ? rbytordpadval[3] : wire_nl0l0Ol_byte_des_fifo_data_in[19];
	assign		wire_ni1lOO_dataout = (nl00i0l === 1'b1) ? rbytordpadval[4] : wire_nl0l0Ol_byte_des_fifo_data_in[20];
	assign		wire_ni1O_dataout = (rrxfifo_dis === 1'b1) ? wire_n10i0O_o : nl0O00i;
	assign		wire_ni1O0i_dataout = (nl00i0l === 1'b1) ? rbytordpadval[8] : wire_nl0l0Ol_byte_des_fifo_data_in[24];
	assign		wire_ni1O0l_dataout = (nl00i0l === 1'b1) ? rbytordpadval[9] : wire_nl0l0Ol_byte_des_fifo_data_in[25];
	assign		wire_ni1O0O_dataout = (nl00i0l === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[10] : wire_nl0l0Ol_byte_des_fifo_data_in[26];
	assign		wire_ni1O1i_dataout = (nl00i0l === 1'b1) ? rbytordpadval[5] : wire_nl0l0Ol_byte_des_fifo_data_in[21];
	assign		wire_ni1O1l_dataout = (nl00i0l === 1'b1) ? rbytordpadval[6] : wire_nl0l0Ol_byte_des_fifo_data_in[22];
	assign		wire_ni1O1O_dataout = (nl00i0l === 1'b1) ? rbytordpadval[7] : wire_nl0l0Ol_byte_des_fifo_data_in[23];
	and(wire_ni1Oi_dataout, wire_niOil_o, ~(nl0i00O));
	and(wire_ni1Oii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[27], ~(nl00i0l));
	and(wire_ni1Oil_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[28], ~(nl00i0l));
	and(wire_ni1OiO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[29], ~(nl00i0l));
	and(wire_ni1Ol_dataout, rx_data_dt[8], ~(nl0i00O));
	and(wire_ni1Oli_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[30], ~(nl00i0l));
	and(wire_ni1Oll_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[31], ~(nl00i0l));
	and(wire_ni1OlO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[32], ~(nl00i0l));
	and(wire_ni1OO_dataout, rx_data_dt[9], ~(nl0i00O));
	and(wire_ni1OOi_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[33], ~(nl00i0l));
	and(wire_ni1OOl_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[34], ~(nl00i0l));
	and(wire_ni1OOO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[35], ~(nl00i0l));
	assign		wire_nii_dataout = (rrxfifo_dis === 1'b1) ? wire_n10Oli_o : nl0Olil;
	assign		wire_nii01i_dataout = (nl0i10i === 1'b1) ? wire_nillll_dataout : wire_nil10l_o;
	assign		wire_nii01l_dataout = (nl0i10i === 1'b1) ? wire_nilllO_dataout : wire_nil10O_o;
	assign		wire_nii0i_dataout = (nl0i0ii === 1'b1) ? rclkcmpinsertpad : rx_data_dt[0];
	or(wire_nii0l_dataout, rx_data_dt[1], nl0i0ii);
	or(wire_nii0O_dataout, rx_data_dt[2], nl0i0ii);
	assign		wire_nii10i_dataout = (nl0i10i === 1'b1) ? wire_niliOl_dataout : wire_niiOil_o;
	assign		wire_nii10l_dataout = (nl0i10i === 1'b1) ? wire_niliOO_dataout : wire_niiOiO_o;
	assign		wire_nii10O_dataout = (nl0i10i === 1'b1) ? wire_nill1i_dataout : wire_niiOli_o;
	assign		wire_nii11i_dataout = (nl0i10i === 1'b1) ? wire_niliiO_dataout : wire_niiO0l_o;
	assign		wire_nii11l_dataout = (nl0i10i === 1'b1) ? wire_nililO_dataout : wire_niiO0O_o;
	assign		wire_nii11O_dataout = (nl0i10i === 1'b1) ? wire_niliOi_dataout : wire_niiOii_o;
	assign		wire_nii1i_dataout = ((~ n110l) === 1'b1) ? wire_niliO_dataout : wire_niili_dataout;
	assign		wire_nii1ii_dataout = (nl0i10i === 1'b1) ? wire_nill1l_dataout : wire_niiOll_o;
	assign		wire_nii1il_dataout = (nl0i10i === 1'b1) ? wire_nill1O_dataout : wire_niiOlO_o;
	assign		wire_nii1iO_dataout = (nl0i10i === 1'b1) ? wire_nill0i_dataout : wire_niiOOi_o;
	assign		wire_nii1l_dataout = ((~ n110l) === 1'b1) ? wire_nilli_dataout : wire_niill_dataout;
	assign		wire_nii1li_dataout = (nl0i10i === 1'b1) ? wire_nill0l_dataout : wire_niiOOl_o;
	assign		wire_nii1ll_dataout = (nl0i10i === 1'b1) ? wire_nill0O_dataout : wire_niiOOO_o;
	assign		wire_nii1lO_dataout = (nl0i10i === 1'b1) ? wire_nillii_o : wire_nil11i_o;
	assign		wire_nii1O_dataout = ((~ n110l) === 1'b1) ? wire_nilll_dataout : wire_niilO_dataout;
	assign		wire_nii1Oi_dataout = (nl0i10i === 1'b1) ? wire_nillil_dataout : wire_nil11l_o;
	assign		wire_nii1Ol_dataout = (nl0i10i === 1'b1) ? wire_nilliO_dataout : wire_nil11O_o;
	assign		wire_nii1OO_dataout = (nl0i10i === 1'b1) ? wire_nillli_dataout : wire_nil10i_o;
	assign		wire_niii_dataout = (rrxfifo_dis === 1'b1) ? wire_n10ili_o : nl0O0il;
	assign		wire_niiii_dataout = (nl0i0ii === 1'b1) ? (~ rclkcmpinsertpad) : rx_data_dt[3];
	or(wire_niiil_dataout, rx_data_dt[4], nl0i0ii);
	or(wire_niiiO_dataout, rx_data_dt[5], nl0i0ii);
	assign		wire_niil_dataout = (rrxfifo_dis === 1'b1) ? wire_n10ill_o : nl0O0iO;
	or(wire_niili_dataout, rx_data_dt[6], nl0i0ii);
	or(wire_niill_dataout, rx_data_dt[7], nl0i0ii);
	or(wire_niilO_dataout, rx_control_dt[0], nl0i0ii);
	assign		wire_niiO_dataout = (rrxfifo_dis === 1'b1) ? wire_n10ilO_o : nl0O0li;
	assign		wire_nil_dataout = (rrxfifo_dis === 1'b1) ? wire_n10Oll_o : nl0OliO;
	and(wire_nil00i_dataout, nlllOl, ~(wire_nil0il_o[2]));
	and(wire_nil00l_dataout, nlllOO, ~(wire_nil0il_o[2]));
	and(wire_nil00O_dataout, nllO1i, ~(wire_nil0il_o[2]));
	assign		wire_nil01i_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[9] : nlllll;
	assign		wire_nil01l_dataout = (wire_nil0il_o[2] === 1'b1) ? nllill : nllllO;
	and(wire_nil01O_dataout, nlllOi, ~(wire_nil0il_o[2]));
	and(wire_nil0i_dataout, rx_data_dt[1], ~(nl0i0il));
	and(wire_nil0ii_dataout, nllO1l, ~(wire_nil0il_o[2]));
	assign		wire_nil0iO_dataout = (nl00i0O === 1'b1) ? rbytordpadval[0] : nllO1O;
	or(wire_nil0l_dataout, rx_data_dt[2], nl0i0il);
	assign		wire_nil0li_dataout = (nl00i0O === 1'b1) ? rbytordpadval[1] : nllO0i;
	assign		wire_nil0ll_dataout = (nl00i0O === 1'b1) ? rbytordpadval[2] : nllO0l;
	assign		wire_nil0lO_dataout = (nl00i0O === 1'b1) ? rbytordpadval[3] : nllO0O;
	or(wire_nil0O_dataout, rx_data_dt[3], nl0i0il);
	assign		wire_nil0Oi_dataout = (nl00i0O === 1'b1) ? rbytordpadval[4] : nllOii;
	assign		wire_nil0Ol_dataout = (nl00i0O === 1'b1) ? rbytordpadval[5] : nllOil;
	assign		wire_nil0OO_dataout = (nl00i0O === 1'b1) ? rbytordpadval[6] : nllOiO;
	assign		wire_nil1ii_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[0] : nlll1l;
	assign		wire_nil1il_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[1] : nlll1O;
	assign		wire_nil1iO_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[2] : nlll0i;
	and(wire_nil1l_dataout, wire_nliil_o, ~(nl0i0il));
	assign		wire_nil1li_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[3] : nlll0l;
	assign		wire_nil1ll_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[4] : nlll0O;
	assign		wire_nil1lO_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[5] : nlllii;
	and(wire_nil1O_dataout, rx_data_dt[0], ~(nl0i0il));
	assign		wire_nil1Oi_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[6] : nlllil;
	assign		wire_nil1Ol_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[7] : nllliO;
	assign		wire_nil1OO_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[8] : nlllli;
	assign		wire_nili_dataout = (rrxfifo_dis === 1'b1) ? wire_n10iOi_o : nl0O0ll;
	and(wire_nili0l_dataout, nllOOl, ~(nl00i0O));
	and(wire_nili0O_dataout, nllOOO, ~(nl00i0O));
	assign		wire_nili1i_dataout = (nl00i0O === 1'b1) ? rbytordpadval[7] : nllOli;
	assign		wire_nili1l_dataout = (nl00i0O === 1'b1) ? rbytordpadval[8] : nllOll;
	assign		wire_nili1O_dataout = (nl00i0O === 1'b1) ? rbytordpadval[9] : nllOlO;
	or(wire_nilii_dataout, rx_data_dt[4], nl0i0il);
	and(wire_niliii_dataout, nlO11i, ~(nl00i0O));
	and(wire_niliil_dataout, nlO11l, ~(nl00i0O));
	and(wire_niliiO_dataout, nlO11O, ~(nl00i0O));
	and(wire_nilil_dataout, rx_data_dt[5], ~(nl0i0il));
	assign		wire_nililO_dataout = (nl00iii === 1'b1) ? rbytordpadval[0] : nlO10i;
	and(wire_niliO_dataout, rx_data_dt[6], ~(nl0i0il));
	assign		wire_niliOi_dataout = (nl00iii === 1'b1) ? rbytordpadval[1] : nlO10l;
	assign		wire_niliOl_dataout = (nl00iii === 1'b1) ? rbytordpadval[2] : nlO10O;
	assign		wire_niliOO_dataout = (nl00iii === 1'b1) ? rbytordpadval[3] : nlO1ii;
	assign		wire_nill_dataout = (rrxfifo_dis === 1'b1) ? wire_n10iOl_o : nl0O0lO;
	assign		wire_nill0i_dataout = (nl00iii === 1'b1) ? rbytordpadval[7] : nlO1ll;
	assign		wire_nill0l_dataout = (nl00iii === 1'b1) ? rbytordpadval[8] : nlO1lO;
	assign		wire_nill0O_dataout = (nl00iii === 1'b1) ? rbytordpadval[9] : nlO1Oi;
	assign		wire_nill1i_dataout = (nl00iii === 1'b1) ? rbytordpadval[4] : nlO1il;
	assign		wire_nill1l_dataout = (nl00iii === 1'b1) ? rbytordpadval[5] : nlO1iO;
	assign		wire_nill1O_dataout = (nl00iii === 1'b1) ? rbytordpadval[6] : nlO1li;
	or(wire_nilli_dataout, rx_data_dt[7], nl0i0il);
	and(wire_nillil_dataout, nlO1OO, ~(nl00iii));
	and(wire_nilliO_dataout, nlO01i, ~(nl00iii));
	or(wire_nilll_dataout, rx_control_dt[0], nl0i0il);
	and(wire_nillli_dataout, nlO01l, ~(nl00iii));
	and(wire_nillll_dataout, nlO01O, ~(nl00iii));
	and(wire_nilllO_dataout, nlO00i, ~(nl00iii));
	assign		wire_nillOO_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[0] : wire_niOl0i_o;
	assign		wire_nilO_dataout = (rrxfifo_dis === 1'b1) ? wire_n10iOO_o : nl0O0Oi;
	assign		wire_nilO0i_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[4] : wire_niOlil_o;
	assign		wire_nilO0l_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[5] : wire_niOliO_o;
	assign		wire_nilO0O_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[6] : wire_niOlli_o;
	assign		wire_nilO1i_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[1] : wire_niOl0l_o;
	assign		wire_nilO1l_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[2] : wire_niOl0O_o;
	assign		wire_nilO1O_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[3] : wire_niOlii_o;
	assign		wire_nilOii_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[7] : wire_niOlll_o;
	assign		wire_nilOil_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[8] : wire_niOllO_o;
	assign		wire_nilOiO_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[9] : wire_niOlOi_o;
	assign		wire_nilOli_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[10] : wire_niOlOl_o;
	assign		wire_nilOll_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[11] : wire_niOlOO_o;
	assign		wire_nilOlO_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[12] : wire_niOO1i_o;
	assign		wire_nilOOi_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[13] : wire_niOO1l_o;
	assign		wire_nilOOl_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[14] : wire_niOO1O_o;
	assign		wire_nilOOO_dataout = (nl0i10i === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[15] : wire_niOO0i_o;
	assign		wire_niO_dataout = (rrxfifo_dis === 1'b1) ? wire_n10OlO_o : nl0Olli;
	assign		wire_niO00i_dataout = (nl0i10i === 1'b1) ? wire_nl1lll_dataout : wire_nl11il_o;
	assign		wire_niO00l_dataout = (nl0i10i === 1'b1) ? wire_nl1llO_dataout : wire_nl11iO_o;
	assign		wire_niO00O_dataout = (nl0i10i === 1'b1) ? wire_nl1lOi_dataout : wire_nl11li_o;
	assign		wire_niO01i_dataout = (nl0i10i === 1'b1) ? wire_nl1lil_dataout : wire_nl110l_o;
	assign		wire_niO01l_dataout = (nl0i10i === 1'b1) ? wire_nl1liO_dataout : wire_nl110O_o;
	assign		wire_niO01O_dataout = (nl0i10i === 1'b1) ? wire_nl1lli_dataout : wire_nl11ii_o;
	assign		wire_niO0ii_dataout = (nl0i10i === 1'b1) ? wire_nl1lOl_dataout : wire_nl11ll_o;
	assign		wire_niO0il_dataout = (nl0i10i === 1'b1) ? wire_nl1lOO_dataout : wire_nl11lO_o;
	assign		wire_niO0iO_dataout = (nl0i10i === 1'b1) ? wire_nl1O1i_dataout : wire_nl11Oi_o;
	assign		wire_niO0li_dataout = (nl0i10i === 1'b1) ? wire_nl1O1l_dataout : wire_nl11Ol_o;
	assign		wire_niO0ll_dataout = (nl0i10i === 1'b1) ? wire_nl1O1O_dataout : wire_nl11OO_o;
	assign		wire_niO0lO_dataout = (nl0i10i === 1'b1) ? wire_nl1O0i_o : wire_nl101i_o;
	assign		wire_niO0Oi_dataout = (nl0i10i === 1'b1) ? wire_nl1O0l_dataout : wire_nl101l_o;
	assign		wire_niO0Ol_dataout = (nl0i10i === 1'b1) ? wire_nl1O0O_dataout : wire_nl101O_o;
	assign		wire_niO0OO_dataout = (nl0i10i === 1'b1) ? wire_nl1Oii_dataout : wire_nl100i_o;
	assign		wire_niO10i_dataout = (nl0i10i === 1'b1) ? wire_nl1ill_dataout : wire_niOOil_o;
	assign		wire_niO10l_dataout = (nl0i10i === 1'b1) ? wire_nl1ilO_dataout : wire_niOOiO_o;
	assign		wire_niO10O_dataout = (nl0i10i === 1'b1) ? wire_nl1iOi_dataout : wire_niOOli_o;
	assign		wire_niO11i_dataout = (nl0i10i === 1'b1) ? wire_nl1iil_dataout : wire_niOO0l_o;
	assign		wire_niO11l_dataout = (nl0i10i === 1'b1) ? wire_nl1iiO_dataout : wire_niOO0O_o;
	assign		wire_niO11O_dataout = (nl0i10i === 1'b1) ? wire_nl1ili_dataout : wire_niOOii_o;
	assign		wire_niO1ii_dataout = (nl0i10i === 1'b1) ? wire_nl1iOl_dataout : wire_niOOll_o;
	assign		wire_niO1il_dataout = (nl0i10i === 1'b1) ? wire_nl1iOO_dataout : wire_niOOlO_o;
	assign		wire_niO1iO_dataout = (nl0i10i === 1'b1) ? wire_nl1l1i_dataout : wire_niOOOi_o;
	assign		wire_niO1li_dataout = (nl0i10i === 1'b1) ? wire_nl1l1l_dataout : wire_niOOOl_o;
	assign		wire_niO1ll_dataout = (nl0i10i === 1'b1) ? wire_nl1l1O_dataout : wire_niOOOO_o;
	assign		wire_niO1lO_dataout = (nl0i10i === 1'b1) ? wire_nl1l0i_dataout : wire_nl111i_o;
	assign		wire_niO1Oi_dataout = (nl0i10i === 1'b1) ? wire_nl1l0l_dataout : wire_nl111l_o;
	assign		wire_niO1Ol_dataout = (nl0i10i === 1'b1) ? wire_nl1l0O_dataout : wire_nl111O_o;
	assign		wire_niO1OO_dataout = (nl0i10i === 1'b1) ? wire_nl1lii_dataout : wire_nl110i_o;
	assign		wire_niOi_dataout = (rrxfifo_dis === 1'b1) ? wire_n10l1i_o : nl0O0Ol;
	assign		wire_niOi0i_dataout = (nl0i10i === 1'b1) ? wire_nl1Oll_dataout : wire_nl10il_o;
	assign		wire_niOi0l_dataout = (nl0i10i === 1'b1) ? wire_nl1OlO_dataout : wire_nl10iO_o;
	assign		wire_niOi0O_dataout = (nl0i10i === 1'b1) ? wire_nl1OOi_dataout : wire_nl10li_o;
	assign		wire_niOi1i_dataout = (nl0i10i === 1'b1) ? wire_nl1Oil_dataout : wire_nl100l_o;
	assign		wire_niOi1l_dataout = (nl0i10i === 1'b1) ? wire_nl1OiO_dataout : wire_nl100O_o;
	assign		wire_niOi1O_dataout = (nl0i10i === 1'b1) ? wire_nl1Oli_dataout : wire_nl10ii_o;
	assign		wire_niOiii_dataout = (nl0i10i === 1'b1) ? wire_nl1OOl_dataout : wire_nl10ll_o;
	assign		wire_niOiil_dataout = (nl0i10i === 1'b1) ? wire_nl1OOO_dataout : wire_nl10lO_o;
	assign		wire_niOiiO_dataout = (nl0i10i === 1'b1) ? wire_nl011i_dataout : wire_nl10Oi_o;
	assign		wire_niOili_dataout = (nl0i10i === 1'b1) ? wire_nl011l_dataout : wire_nl10Ol_o;
	assign		wire_niOill_dataout = (nl0i10i === 1'b1) ? wire_nl011O_dataout : wire_nl10OO_o;
	assign		wire_niOilO_dataout = (nl0i10i === 1'b1) ? wire_nl010i_dataout : wire_nl1i1i_o;
	assign		wire_niOiOi_dataout = (nl0i10i === 1'b1) ? wire_nl010l_o : wire_nl1i1l_o;
	assign		wire_niOiOl_dataout = (nl0i10i === 1'b1) ? wire_nl010O_dataout : wire_nl1i1O_o;
	assign		wire_niOiOO_dataout = (nl0i10i === 1'b1) ? wire_nl01ii_dataout : wire_nl1i0i_o;
	assign		wire_niOl_dataout = (rrxfifo_dis === 1'b1) ? wire_n10l1l_o : nl0O0OO;
	assign		wire_niOl1i_dataout = (nl0i10i === 1'b1) ? wire_nl01il_dataout : wire_nl1i0l_o;
	assign		wire_niOl1l_dataout = (nl0i10i === 1'b1) ? wire_nl01iO_dataout : wire_nl1i0O_o;
	assign		wire_niOl1O_dataout = (nl0i10i === 1'b1) ? wire_nl01li_dataout : wire_nl1iii_o;
	assign		wire_niOO_dataout = (rrxfifo_dis === 1'b1) ? wire_n10l1O_o : nl0Oi1i;
	assign		wire_nl000i_dataout = (rwa_6g_en === 1'b1) ? (nl00iil & nl00iiO) : (nlO00l & (nl00ili & nl00iiO));
	and(wire_nl00il_dataout, wire_nl00iO_dataout, rwa_6g_en);
	assign		wire_nl00iO_dataout = (rdwidth === 1'b1) ? (nl00ili & nl00ill) : (nl00iOi & nl00ill);
	assign		wire_nl00lO_dataout = (rwa_6g_en === 1'b1) ? wire_nl00OO_dataout : (nlO00O & (nl00iOi & nl00O0O));
	and(wire_nl00OO_dataout, (nl00ilO & nl00O0O), rdwidth);
	assign		wire_nl010i_dataout = (nl00iii === 1'b1) ? rbytordpadval[9] : wire_nl0l0Ol_byte_des_fifo_data_in[57];
	and(wire_nl010O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[59], ~(nl00iii));
	assign		wire_nl011i_dataout = (nl00iii === 1'b1) ? rbytordpadval[6] : wire_nl0l0Ol_byte_des_fifo_data_in[54];
	assign		wire_nl011l_dataout = (nl00iii === 1'b1) ? rbytordpadval[7] : wire_nl0l0Ol_byte_des_fifo_data_in[55];
	assign		wire_nl011O_dataout = (nl00iii === 1'b1) ? rbytordpadval[8] : wire_nl0l0Ol_byte_des_fifo_data_in[56];
	and(wire_nl01ii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[60], ~(nl00iii));
	and(wire_nl01il_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[61], ~(nl00iii));
	and(wire_nl01iO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[62], ~(nl00iii));
	and(wire_nl01li_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[63], ~(nl00iii));
	and(wire_nl01ll_dataout, wire_nl01OO_o, ~(nl0i10l));
	and(wire_nl01lO_dataout, wire_nl001i_o, ~(nl0i10l));
	and(wire_nl01Oi_dataout, wire_nl001l_o, ~(nl0i10l));
	and(wire_nl01Ol_dataout, wire_nl001O_o, ~(nl0i10l));
	assign		wire_nl0i_dataout = (rrxfifo_dis === 1'b1) ? wire_n10lii_o : nl0Oi0l;
	assign		wire_nl0i0l_dataout = (rwa_6g_en === 1'b1) ? (nl00iOl & nl00iOO) : (nlO00O & (nl00l1i & nl00iOO));
	and(wire_nl0i1l_dataout, wire_nl0i1O_dataout, rwa_6g_en);
	and(wire_nl0i1O_dataout, (nl00O0l & nl00iOi), rdwidth);
	and(wire_nl0iiO_dataout, wire_nl0ili_dataout, rwa_6g_en);
	assign		wire_nl0ili_dataout = (rdwidth === 1'b1) ? (nl00l1i & nl00l1l) : (nl00l0i & nl00l1l);
	assign		wire_nl0iOi_dataout = (rwa_6g_en === 1'b1) ? wire_nl0l1i_dataout : (wire_nlOilO_dataout & (nl00l0i & nl00OOi));
	assign		wire_nl0l_dataout = (rrxfifo_dis === 1'b1) ? wire_n10lil_o : nl0Oi0O;
	and(wire_nl0l0i_dataout, (nl00OlO & nl00l0i), rdwidth);
	assign		wire_nl0l0O_dataout = (rwa_6g_en === 1'b1) ? (wire_nlOilO_dataout & ((((~ nl00l0O) & (~ nl00l0l)) | (~ rbytordplden)) & nl00liO)) : (wire_nlOilO_dataout & ((((~ nl00lil) & (~ nl00lii)) | (~ rbytordplden)) & nl00liO));
	and(wire_nl0l1i_dataout, (nl00l1O & nl00OOi), rdwidth);
	and(wire_nl0l1O_dataout, wire_nl0l0i_dataout, rwa_6g_en);
	assign		wire_nl0O_dataout = (rrxfifo_dis === 1'b1) ? wire_n10liO_o : nl0Oiii;
	assign		wire_nl0O0l_dataout = (rwa_6g_en === 1'b1) ? wire_nl0Oll_dataout : (wire_nlOiOi_dataout & (nl00lli & nl00lOi));
	and(wire_nl0O1i_dataout, (wire_nlOilO_dataout & (nl00lli & (nl00lOO | nl00lOl))), rwa_6g_en);
	and(wire_nl0Oll_dataout, (wire_nlOiOi_dataout & ((((~ nl00lOO) & (~ nl00lOl)) | (~ rbytordplden)) & nl00lOi)), rdwidth);
	assign		wire_nl10l_dataout = (tenb_data[18] === 1'b1) ? (n10Ol & nl0iiOi) : (n1i1O & nl0iiOi);
	assign		wire_nl1i_dataout = (rrxfifo_dis === 1'b1) ? wire_n10l0i_o : nl0Oi1l;
	assign		wire_nl1iil_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[0] : wire_nl0l0Ol_byte_des_fifo_data_in[16];
	assign		wire_nl1iiO_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[1] : wire_nl0l0Ol_byte_des_fifo_data_in[17];
	assign		wire_nl1ili_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[2] : wire_nl0l0Ol_byte_des_fifo_data_in[18];
	assign		wire_nl1ill_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[3] : wire_nl0l0Ol_byte_des_fifo_data_in[19];
	assign		wire_nl1ilO_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[4] : wire_nl0l0Ol_byte_des_fifo_data_in[20];
	assign		wire_nl1iOi_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[5] : wire_nl0l0Ol_byte_des_fifo_data_in[21];
	assign		wire_nl1iOl_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[6] : wire_nl0l0Ol_byte_des_fifo_data_in[22];
	assign		wire_nl1iOO_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[7] : wire_nl0l0Ol_byte_des_fifo_data_in[23];
	assign		wire_nl1l_dataout = (rrxfifo_dis === 1'b1) ? wire_n10l0l_o : nl0Oi1O;
	and(wire_nl1l0i_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[27], ~(wire_nil0il_o[2]));
	and(wire_nl1l0l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[28], ~(wire_nil0il_o[2]));
	and(wire_nl1l0O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[29], ~(wire_nil0il_o[2]));
	assign		wire_nl1l1i_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[8] : wire_nl0l0Ol_byte_des_fifo_data_in[24];
	assign		wire_nl1l1l_dataout = (wire_nil0il_o[2] === 1'b1) ? rbytordpadval[9] : wire_nl0l0Ol_byte_des_fifo_data_in[25];
	assign		wire_nl1l1O_dataout = (wire_nil0il_o[2] === 1'b1) ? wire_nl0l0Ol_byte_des_fifo_data_in[10] : wire_nl0l0Ol_byte_des_fifo_data_in[26];
	and(wire_nl1lii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[30], ~(wire_nil0il_o[2]));
	and(wire_nl1lil_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[31], ~(wire_nil0il_o[2]));
	assign		wire_nl1liO_dataout = (nl00i0O === 1'b1) ? rbytordpadval[0] : wire_nl0l0Ol_byte_des_fifo_data_in[32];
	assign		wire_nl1lli_dataout = (nl00i0O === 1'b1) ? rbytordpadval[1] : wire_nl0l0Ol_byte_des_fifo_data_in[33];
	assign		wire_nl1lll_dataout = (nl00i0O === 1'b1) ? rbytordpadval[2] : wire_nl0l0Ol_byte_des_fifo_data_in[34];
	assign		wire_nl1llO_dataout = (nl00i0O === 1'b1) ? rbytordpadval[3] : wire_nl0l0Ol_byte_des_fifo_data_in[35];
	assign		wire_nl1lOi_dataout = (nl00i0O === 1'b1) ? rbytordpadval[4] : wire_nl0l0Ol_byte_des_fifo_data_in[36];
	assign		wire_nl1lOl_dataout = (nl00i0O === 1'b1) ? rbytordpadval[5] : wire_nl0l0Ol_byte_des_fifo_data_in[37];
	assign		wire_nl1lOO_dataout = (nl00i0O === 1'b1) ? rbytordpadval[6] : wire_nl0l0Ol_byte_des_fifo_data_in[38];
	assign		wire_nl1O_dataout = (rrxfifo_dis === 1'b1) ? wire_n10l0O_o : nl0Oi0i;
	and(wire_nl1O0l_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[43], ~(nl00i0O));
	and(wire_nl1O0O_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[44], ~(nl00i0O));
	assign		wire_nl1O1i_dataout = (nl00i0O === 1'b1) ? rbytordpadval[7] : wire_nl0l0Ol_byte_des_fifo_data_in[39];
	assign		wire_nl1O1l_dataout = (nl00i0O === 1'b1) ? rbytordpadval[8] : wire_nl0l0Ol_byte_des_fifo_data_in[40];
	assign		wire_nl1O1O_dataout = (nl00i0O === 1'b1) ? rbytordpadval[9] : wire_nl0l0Ol_byte_des_fifo_data_in[41];
	and(wire_nl1Oii_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[45], ~(nl00i0O));
	and(wire_nl1Oil_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[46], ~(nl00i0O));
	and(wire_nl1OiO_dataout, wire_nl0l0Ol_byte_des_fifo_data_in[47], ~(nl00i0O));
	assign		wire_nl1Oli_dataout = (nl00iii === 1'b1) ? rbytordpadval[0] : wire_nl0l0Ol_byte_des_fifo_data_in[48];
	assign		wire_nl1Oll_dataout = (nl00iii === 1'b1) ? rbytordpadval[1] : wire_nl0l0Ol_byte_des_fifo_data_in[49];
	assign		wire_nl1OlO_dataout = (nl00iii === 1'b1) ? rbytordpadval[2] : wire_nl0l0Ol_byte_des_fifo_data_in[50];
	assign		wire_nl1OOi_dataout = (nl00iii === 1'b1) ? rbytordpadval[3] : wire_nl0l0Ol_byte_des_fifo_data_in[51];
	assign		wire_nl1OOl_dataout = (nl00iii === 1'b1) ? rbytordpadval[4] : wire_nl0l0Ol_byte_des_fifo_data_in[52];
	assign		wire_nl1OOO_dataout = (nl00iii === 1'b1) ? rbytordpadval[5] : wire_nl0l0Ol_byte_des_fifo_data_in[53];
	assign		wire_nli_dataout = (rinvalid_code_err_only === 1'b1) ? invalid_code_delay[0] : (invalid_code_delay[0] | disp_err_delay[0]);
	assign		wire_nli01O_dataout = (rwa_6g_en === 1'b1) ? wire_nli0ii_dataout : (wire_nlOiOi_dataout & (nl00Oii & nl00Oll));
	and(wire_nli0ii_dataout, (wire_nlOiOi_dataout & (((~ rbytordplden) | (~ nl00OiO)) & nl00Oll)), rdwidth);
	and(wire_nli0ll_dataout, wire_nli0lO_dataout, rwa_6g_en);
	and(wire_nli0lO_dataout, (wire_nlOiOi_dataout & (((~ rbytordplden) | (~ nl00Oll)) & nl00Oli)), rdwidth);
	or(wire_nli10Ol_dataout, wire_nli10OO_dataout, nl000li);
	and(wire_nli10OO_dataout, nl0OlOl, ~(((nl0OlOl & (~ nl000li)) & (~ nl000ll))));
	and(wire_nli11i_dataout, wire_nli11l_dataout, rwa_6g_en);
	and(wire_nli11l_dataout, (wire_nlOiOi_dataout & ((((~ nl00O0i) & (~ nl00O1O)) | (~ rbytordplden)) & (nl00O1l | nl00O1i))), rdwidth);
	and(wire_nli1i0i_dataout, nl0OlOO, ~(((nl0OlOO & (~ nl000lO)) & (~ nl000ll))));
	or(wire_nli1i1O_dataout, wire_nli1i0i_dataout, nl000lO);
	assign		wire_nli1iii_dataout = (nlO0ll === 1'b1) ? wire_nli1iOO_dataout : nli111l;
	assign		wire_nli1iil_dataout = (nlO0ll === 1'b1) ? wire_nli1l1i_dataout : nli111O;
	assign		wire_nli1iiO_dataout = (nlO0ll === 1'b1) ? wire_nli1l1l_dataout : nli110i;
	assign		wire_nli1il_dataout = (rwa_6g_en === 1'b1) ? (wire_nlOilO_dataout & (((~ rbytordplden) | (~ nl00O0l)) & nl00Oil)) : (wire_nlOilO_dataout & (((~ rbytordplden) | (~ nl00O0O)) & nl00Oil));
	assign		wire_nli1ili_dataout = (nlO0ll === 1'b1) ? wire_nli1l1O_dataout : nli110l;
	assign		wire_nli1ill_dataout = (nlO0ll === 1'b1) ? wire_nli1l0i_dataout : nli110O;
	assign		wire_nli1ilO_dataout = (nlO0ll === 1'b1) ? wire_nli1l0l_dataout : nli11ii;
	assign		wire_nli1iOi_dataout = (nlO0ll === 1'b1) ? wire_nli1l0O_dataout : nli11il;
	assign		wire_nli1iOl_dataout = (nlO0ll === 1'b1) ? wire_nli1lii_dataout : nli11iO;
	assign		wire_nli1iOO_dataout = (nl000Oi === 1'b1) ? nli11il : nli11iO;
	assign		wire_nli1l0i_dataout = (nl000Oi === 1'b1) ? nli110i : nli110l;
	assign		wire_nli1l0l_dataout = (nl000Oi === 1'b1) ? nli110l : nli110O;
	assign		wire_nli1l0O_dataout = (nl000Oi === 1'b1) ? nli110O : nli11ii;
	assign		wire_nli1l1i_dataout = (nl000Oi === 1'b1) ? nli11iO : nli111l;
	assign		wire_nli1l1l_dataout = (nl000Oi === 1'b1) ? nli111l : nli111O;
	assign		wire_nli1l1O_dataout = (nl000Oi === 1'b1) ? nli111O : nli110i;
	assign		wire_nli1lii_dataout = (nl000Oi === 1'b1) ? nli11ii : nli11il;
	assign		wire_nli1O0i_dataout = (nlOliO === 1'b1) ? nli1lli : nli1lll;
	assign		wire_nli1O0l_dataout = (nlOliO === 1'b1) ? nli1lll : nli1llO;
	assign		wire_nli1O0O_dataout = (nlOliO === 1'b1) ? nli1llO : nli1lOi;
	assign		wire_nli1O1l_dataout = (nlOliO === 1'b1) ? nli1O1i : nli10Oi;
	assign		wire_nli1O1O_dataout = (nlOliO === 1'b1) ? nli10Oi : nli1lli;
	assign		wire_nli1Oii_dataout = (nlOliO === 1'b1) ? nli1lOi : nli1lOl;
	assign		wire_nli1Oil_dataout = (nlOliO === 1'b1) ? nli1lOl : nli1lOO;
	assign		wire_nli1OiO_dataout = (nlOliO === 1'b1) ? nli1lOO : nli1O1i;
	and(wire_nli1OO_dataout, (wire_nlOilO_dataout & (nl00Oii & nl00OiO)), rwa_6g_en);
	assign		wire_nlii_dataout = (rrxfifo_dis === 1'b1) ? wire_n10lli_o : nl0Oiil;
	assign		wire_nlii1i_dataout = (rwa_6g_en === 1'b1) ? (wire_nlOilO_dataout & (((~ rbytordplden) | (~ nl00OlO)) & nl00OOO)) : (wire_nlOilO_dataout & (((~ rbytordplden) | (~ nl00OOi)) & nl00OOO));
	and(wire_nliiil_dataout, (wire_nlOilO_dataout & (nl00OOl & nl0i11i)), rwa_6g_en);
	assign		wire_nliill_dataout = (rwa_6g_en === 1'b1) ? wire_nliiOO_dataout : (wire_nlOiOi_dataout & (nl00OOl & nl0i11O));
	and(wire_nliiOO_dataout, (wire_nlOiOi_dataout & (((~ rbytordplden) | (~ nl0i11i)) & nl0i11O)), rdwidth);
	assign		wire_nlil_dataout = (rrxfifo_dis === 1'b1) ? wire_n10lll_o : nl0OiiO;
	and(wire_nlil0i_dataout, wire_nlil0l_dataout, rwa_6g_en);
	and(wire_nlil0l_dataout, (wire_nlOiOi_dataout & (((~ rbytordplden) | (~ nl0i11O)) & nl0i11l)), rdwidth);
	assign		wire_nliO_dataout = (rrxfifo_dis === 1'b1) ? wire_n10llO_o : nl0Oili;
	assign		wire_nll_dataout = (rinvalid_code_err_only === 1'b1) ? invalid_code_delay[1] : ((invalid_code_delay[1] | disp_err_delay[1]) | (~ (nl0l0ii4 ^ nl0l0ii3)));
	assign		wire_nll0l_dataout = (tenb_data[8] === 1'b1) ? (n10Oi & nl0l00O) : ((n1i1l & nl0l00O) & (nl0l00i6 ^ nl0l00i5));
	assign		wire_nlli_dataout = (rrxfifo_dis === 1'b1) ? wire_n10lOi_o : nl0Oill;
	assign		wire_nlll_dataout = (rrxfifo_dis === 1'b1) ? wire_n10lOl_o : nl0OilO;
	assign		wire_nllO_dataout = (rrxfifo_dis === 1'b1) ? wire_n10lOO_o : nl0OiOi;
	and(wire_nlO0lO_dataout, wire_nlO0Oi_dataout, ~(nl0i10l));
	or(wire_nlO0Oi_dataout, nlillO, (((wire_nl01Ol_dataout | wire_nl01Oi_dataout) | wire_nl01lO_dataout) | wire_nl01ll_dataout));
	and(wire_nlO0OO_dataout, wire_nlOi1i_dataout, ~((nlO0iO & (~ nlO0il))));
	assign		wire_nlOi_dataout = (rrxfifo_dis === 1'b1) ? wire_n10O1i_o : nl0OiOl;
	assign		wire_nlOi0i_dataout = (nl0i10i === 1'b1) ? wire_nl01ll_dataout : wire_nlOiil_dataout;
	assign		wire_nlOi0l_dataout = (nl0i10i === 1'b1) ? wire_nl01lO_dataout : wire_nlOiiO_dataout;
	assign		wire_nlOi0O_dataout = (nl0i10i === 1'b1) ? wire_nl01Oi_dataout : wire_nlOili_dataout;
	or(wire_nlOi1i_dataout, nlO0ii, (nlO0il & (~ nlO0ii)));
	assign		wire_nlOiii_dataout = (nl0i10i === 1'b1) ? wire_nl01Ol_dataout : wire_nlOill_dataout;
	and(wire_nlOiil_dataout, n11OOO, ~(nl0i10l));
	and(wire_nlOiiO_dataout, nliliO, ~(nl0i10l));
	and(wire_nlOili_dataout, nlilli, ~(nl0i10l));
	and(wire_nlOill_dataout, nlilll, ~(nl0i10l));
	and(wire_nlOilO_dataout, wire_nlOiOl_dataout, ~(nl0i10O));
	and(wire_nlOiOi_dataout, wire_nlOiOO_dataout, ~(nl0i10O));
	assign		wire_nlOiOl_dataout = (rbytordplden === 1'b1) ? nlO0ii : wire_nlOl1i_dataout;
	assign		wire_nlOiOO_dataout = (rbytordplden === 1'b1) ? nlO0ii : wire_nlOl1l_dataout;
	assign		wire_nlOl_dataout = (rrxfifo_dis === 1'b1) ? wire_n10O1l_o : nl0OiOO;
	assign		wire_nlOl1i_dataout = (rwa_6g_en === 1'b1) ? (wire_nl0l0Ol_byte_des_fifo_data_in[26] | wire_nl0l0Ol_byte_des_fifo_data_in[10]) : wire_nl0l0Ol_byte_des_bo_3g_start[0];
	assign		wire_nlOl1l_dataout = (rwa_6g_en === 1'b1) ? (wire_nl0l0Ol_byte_des_fifo_data_in[58] | wire_nl0l0Ol_byte_des_fifo_data_in[42]) : wire_nl0l0Ol_byte_des_bo_3g_start[1];
	assign		wire_nlOlli_dataout = (rphfifo_master_sel_rx === 1'b1) ? wire_nlOlll_dataout : rd_enable_q0_ch0;
	assign		wire_nlOlll_dataout = (indv_rx === 1'b1) ? nlOl0l : rd_enable_ch0;
	assign		wire_nlOllO_dataout = (rrxphfifopldctl_en === 1'b1) ? (nlOl0O & pld_re) : nlOl0O;
	assign		wire_nlOlO_dataout = (rrxfifo_dis === 1'b1) ? wire_n101ii_dataout : nl0Olll;
	assign		wire_nlOO_dataout = (rrxfifo_dis === 1'b1) ? wire_n10O1O_o : nl0Ol1i;
	assign		wire_nlOOi_dataout = (rrxfifo_dis === 1'b1) ? wire_n10l0l_o : nl0Oi1O;
	assign		wire_nlOOil_dataout = (rphfifo_master_sel_rx === 1'b1) ? wire_nlOOiO_dataout : wr_enable_q0_ch0;
	assign		wire_nlOOiO_dataout = (indv_rx === 1'b1) ? nlOlOl : wr_enable_ch0;
	assign		wire_nlOOl_dataout = (rrxfifo_dis === 1'b1) ? wire_n10O0O_o : nl0Ol0i;
	assign		wire_nlOOli_dataout = (rrxphfifopldctl_en === 1'b1) ? ((~ nlOO1l) & nlOlOO) : nlOlOO;
	assign		wire_nlOOO_dataout = (rrxfifo_dis === 1'b1) ? wire_n1001O_o : nl0O11i;
	and(wire_nlOOOi_dataout, nlOOii, ~(scan_mode));
	oper_decoder   nil0il
	( 
	.i({wire_nl01lO_dataout, wire_nl01ll_dataout}),
	.o(wire_nil0il_o));
	defparam
		nil0il.width_i = 2,
		nil0il.width_o = 4;
	oper_decoder   nilill
	( 
	.i({wire_nl01Oi_dataout, wire_nl01lO_dataout, wire_nl01ll_dataout}),
	.o(wire_nilill_o));
	defparam
		nilill.width_i = 3,
		nilill.width_o = 8;
	oper_decoder   nillOl
	( 
	.i({wire_nl01Ol_dataout, wire_nl01Oi_dataout, wire_nl01lO_dataout, wire_nl01ll_dataout}),
	.o(wire_nillOl_o));
	defparam
		nillOl.width_i = 4,
		nillOl.width_o = 16;
	oper_decoder   nl0lO1O
	( 
	.i({nli11iO, nli11il, nli11ii, nli110O, nli110l, nli110i, nli111O, nli111l}),
	.o(wire_nl0lO1O_o));
	defparam
		nl0lO1O.width_i = 8,
		nl0lO1O.width_o = 256;
	oper_decoder   nl0lOii
	( 
	.i({nli1O1i, nli1lOO, nli1lOl, nli1lOi, nli1llO, nli1lll, nli1lli, nli10Oi}),
	.o(wire_nl0lOii_o));
	defparam
		nl0lOii.width_i = 8,
		nl0lOii.width_o = 256;
	oper_decoder   nl10i
	( 
	.i({rwa_6g_en, rpmadatawidth, rsync_comp_size[2:0], tenb_data[18]}),
	.o(wire_nl10i_o));
	defparam
		nl10i.width_i = 6,
		nl10i.width_o = 64;
	oper_decoder   nll0i
	( 
	.i({((nl0l01i12 ^ nl0l01i11) & rwa_6g_en), rpmadatawidth, ((nl0l01l10 ^ nl0l01l9) & rsync_comp_size[2]), ((nl0l01O8 ^ nl0l01O7) & rsync_comp_size[1]), rsync_comp_size[0], tenb_data[8]}),
	.o(wire_nll0i_o));
	defparam
		nll0i.width_i = 6,
		nll0i.width_o = 64;
	oper_mux   n1000i
	( 
	.data({wire_ni0iiO_dataout, wire_nilOli_dataout, wire_n00O1l_dataout, wire_n0O1Oi_dataout, wire_n1i1il_dataout, wire_n1Oi0O_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[10]}}}),
	.o(wire_n1000i_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n1000i.width_data = 8,
		n1000i.width_sel = 3;
	oper_mux   n1000l
	( 
	.data({wire_ni0ili_dataout, wire_nilOll_dataout, wire_n00O1O_dataout, wire_n0O1Ol_dataout, wire_n1i1iO_dataout, wire_n1Oiii_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[11]}}}),
	.o(wire_n1000l_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n1000l.width_data = 8,
		n1000l.width_sel = 3;
	oper_mux   n1000O
	( 
	.data({wire_ni0ill_dataout, wire_nilOlO_dataout, wire_n00O0i_dataout, wire_n0O1OO_dataout, wire_n1i1li_dataout, wire_n1Oiil_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[12]}}}),
	.o(wire_n1000O_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n1000O.width_data = 8,
		n1000O.width_sel = 3;
	oper_mux   n1001i
	( 
	.data({wire_ni0i0O_dataout, wire_nilOii_dataout, wire_n00lOl_dataout, wire_n0O1li_dataout, wire_n1i10l_dataout, wire_n1Oi1O_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[7]}}}),
	.o(wire_n1001i_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n1001i.width_data = 8,
		n1001i.width_sel = 3;
	oper_mux   n1001l
	( 
	.data({wire_ni0iii_dataout, wire_nilOil_dataout, wire_n00lOO_dataout, wire_n0O1ll_dataout, wire_n1i10O_dataout, wire_n1Oi0i_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[8]}}}),
	.o(wire_n1001l_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n1001l.width_data = 8,
		n1001l.width_sel = 3;
	oper_mux   n1001O
	( 
	.data({wire_ni0iil_dataout, wire_nilOiO_dataout, wire_n00O1i_dataout, wire_n0O1lO_dataout, wire_n1i1ii_dataout, wire_n1Oi0l_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[9]}}}),
	.o(wire_n1001O_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n1001O.width_data = 8,
		n1001O.width_sel = 3;
	oper_mux   n100ii
	( 
	.data({wire_ni0ilO_dataout, wire_nilOOi_dataout, wire_n00O0l_dataout, wire_n0O01i_dataout, wire_n1i1ll_dataout, wire_n1OiiO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[13]}}}),
	.o(wire_n100ii_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100ii.width_data = 8,
		n100ii.width_sel = 3;
	oper_mux   n100il
	( 
	.data({wire_ni0iOi_dataout, wire_nilOOl_dataout, wire_n00O0O_dataout, wire_n0O01l_dataout, wire_n1i1lO_dataout, wire_n1Oili_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[14]}}}),
	.o(wire_n100il_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100il.width_data = 8,
		n100il.width_sel = 3;
	oper_mux   n100iO
	( 
	.data({wire_ni0iOl_dataout, wire_nilOOO_dataout, wire_n00Oii_dataout, wire_n0O01O_dataout, wire_n1i1Oi_dataout, wire_n1Oill_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[15]}}}),
	.o(wire_n100iO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100iO.width_data = 8,
		n100iO.width_sel = 3;
	oper_mux   n100li
	( 
	.data({wire_ni0iOO_dataout, wire_niO11i_dataout, wire_n00Oil_dataout, wire_n0O00i_dataout, wire_n1i1Ol_dataout, wire_n1OilO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[16]}}}),
	.o(wire_n100li_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100li.width_data = 8,
		n100li.width_sel = 3;
	oper_mux   n100ll
	( 
	.data({wire_ni0l1i_dataout, wire_niO11l_dataout, wire_n00OiO_dataout, wire_n0O00l_dataout, wire_n1i1OO_dataout, wire_n1OiOi_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[17]}}}),
	.o(wire_n100ll_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100ll.width_data = 8,
		n100ll.width_sel = 3;
	oper_mux   n100lO
	( 
	.data({wire_ni0l1l_dataout, wire_niO11O_dataout, wire_n00Oli_dataout, wire_n0O00O_dataout, wire_n1i01i_dataout, wire_n1OiOl_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[18]}}}),
	.o(wire_n100lO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100lO.width_data = 8,
		n100lO.width_sel = 3;
	oper_mux   n100Oi
	( 
	.data({wire_ni0l1O_dataout, wire_niO10i_dataout, wire_n00Oll_dataout, wire_n0O0ii_dataout, wire_n1i01l_dataout, wire_n1OiOO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[19]}}}),
	.o(wire_n100Oi_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100Oi.width_data = 8,
		n100Oi.width_sel = 3;
	oper_mux   n100Ol
	( 
	.data({wire_ni0l0i_dataout, wire_niO10l_dataout, wire_n00OlO_dataout, wire_n0O0il_dataout, wire_n1i01O_dataout, wire_n1Ol1i_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[20]}}}),
	.o(wire_n100Ol_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100Ol.width_data = 8,
		n100Ol.width_sel = 3;
	oper_mux   n100OO
	( 
	.data({wire_ni0l0l_dataout, wire_niO10O_dataout, wire_n00OOi_dataout, wire_n0O0iO_dataout, wire_n1i00i_dataout, wire_n1Ol1l_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[21]}}}),
	.o(wire_n100OO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n100OO.width_data = 8,
		n100OO.width_sel = 3;
	oper_mux   n101iO
	( 
	.data({wire_ni00Ol_dataout, wire_nillOO_dataout, wire_n00lii_dataout, wire_n0O11O_dataout, wire_n10OOi_dataout, wire_n1O0ll_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[0]}}}),
	.o(wire_n101iO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n101iO.width_data = 8,
		n101iO.width_sel = 3;
	oper_mux   n101li
	( 
	.data({wire_ni00OO_dataout, wire_nilO1i_dataout, wire_n00lil_dataout, wire_n0O10i_dataout, wire_n10OOl_dataout, wire_n1O0lO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[1]}}}),
	.o(wire_n101li_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n101li.width_data = 8,
		n101li.width_sel = 3;
	oper_mux   n101ll
	( 
	.data({wire_ni0i1i_dataout, wire_nilO1l_dataout, wire_n00liO_dataout, wire_n0O10l_dataout, wire_n10OOO_dataout, wire_n1O0Oi_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[2]}}}),
	.o(wire_n101ll_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n101ll.width_data = 8,
		n101ll.width_sel = 3;
	oper_mux   n101lO
	( 
	.data({wire_ni0i1l_dataout, wire_nilO1O_dataout, wire_n00lli_dataout, wire_n0O10O_dataout, wire_n1i11i_dataout, wire_n1O0Ol_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[3]}}}),
	.o(wire_n101lO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n101lO.width_data = 8,
		n101lO.width_sel = 3;
	oper_mux   n101Oi
	( 
	.data({wire_ni0i1O_dataout, wire_nilO0i_dataout, wire_n00lll_dataout, wire_n0O1ii_dataout, wire_n1i11l_dataout, wire_n1O0OO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[4]}}}),
	.o(wire_n101Oi_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n101Oi.width_data = 8,
		n101Oi.width_sel = 3;
	oper_mux   n101Ol
	( 
	.data({wire_ni0i0i_dataout, wire_nilO0l_dataout, wire_n00llO_dataout, wire_n0O1il_dataout, wire_n1i11O_dataout, wire_n1Oi1i_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[5]}}}),
	.o(wire_n101Ol_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n101Ol.width_data = 8,
		n101Ol.width_sel = 3;
	oper_mux   n101OO
	( 
	.data({wire_ni0i0l_dataout, wire_nilO0O_dataout, wire_n00lOi_dataout, wire_n0O1iO_dataout, wire_n1i10i_dataout, wire_n1Oi1l_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[6]}}}),
	.o(wire_n101OO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n101OO.width_data = 8,
		n101OO.width_sel = 3;
	oper_mux   n10i0i
	( 
	.data({wire_ni0liO_dataout, wire_niO1li_dataout, wire_n0i11l_dataout, wire_n0O0Oi_dataout, wire_n1i0il_dataout, wire_n1Ol0O_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[25]}}}),
	.o(wire_n10i0i_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10i0i.width_data = 8,
		n10i0i.width_sel = 3;
	oper_mux   n10i0l
	( 
	.data({wire_ni0lli_dataout, wire_niO1ll_dataout, wire_n0i11O_dataout, wire_n0O0Ol_dataout, wire_n1i0iO_dataout, wire_n1Olii_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[26]}}}),
	.o(wire_n10i0l_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10i0l.width_data = 8,
		n10i0l.width_sel = 3;
	oper_mux   n10i0O
	( 
	.data({wire_ni0lll_dataout, wire_niO1lO_dataout, wire_n0i10i_dataout, wire_n0O0OO_dataout, wire_n1i0li_dataout, wire_n1Olil_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[27]}}}),
	.o(wire_n10i0O_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10i0O.width_data = 8,
		n10i0O.width_sel = 3;
	oper_mux   n10i1i
	( 
	.data({wire_ni0l0O_dataout, wire_niO1ii_dataout, wire_n00OOl_dataout, wire_n0O0li_dataout, wire_n1i00l_dataout, wire_n1Ol1O_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[22]}}}),
	.o(wire_n10i1i_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10i1i.width_data = 8,
		n10i1i.width_sel = 3;
	oper_mux   n10i1l
	( 
	.data({wire_ni0lii_dataout, wire_niO1il_dataout, wire_n00OOO_dataout, wire_n0O0ll_dataout, wire_n1i00O_dataout, wire_n1Ol0i_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[23]}}}),
	.o(wire_n10i1l_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10i1l.width_data = 8,
		n10i1l.width_sel = 3;
	oper_mux   n10i1O
	( 
	.data({wire_ni0lil_dataout, wire_niO1iO_dataout, wire_n0i11i_dataout, wire_n0O0lO_dataout, wire_n1i0ii_dataout, wire_n1Ol0l_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[24]}}}),
	.o(wire_n10i1O_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10i1O.width_data = 8,
		n10i1O.width_sel = 3;
	oper_mux   n10iii
	( 
	.data({wire_ni0llO_dataout, wire_niO1Oi_dataout, wire_n0i10l_dataout, wire_n0Oi1i_dataout, wire_n1i0ll_dataout, wire_n1OliO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[28]}}}),
	.o(wire_n10iii_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10iii.width_data = 8,
		n10iii.width_sel = 3;
	oper_mux   n10iil
	( 
	.data({wire_ni0lOi_dataout, wire_niO1Ol_dataout, wire_n0i10O_dataout, wire_n0Oi1l_dataout, wire_n1i0lO_dataout, wire_n1Olli_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[29]}}}),
	.o(wire_n10iil_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10iil.width_data = 8,
		n10iil.width_sel = 3;
	oper_mux   n10iiO
	( 
	.data({wire_ni0lOl_dataout, wire_niO1OO_dataout, wire_n0i1ii_dataout, wire_n0Oi1O_dataout, wire_n1i0Oi_dataout, wire_n1Olll_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[30]}}}),
	.o(wire_n10iiO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10iiO.width_data = 8,
		n10iiO.width_sel = 3;
	oper_mux   n10ili
	( 
	.data({wire_ni0lOO_dataout, wire_niO01i_dataout, wire_n0i1il_dataout, wire_n0Oi0i_dataout, wire_n1i0Ol_dataout, wire_n1OllO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[31]}}}),
	.o(wire_n10ili_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10ili.width_data = 8,
		n10ili.width_sel = 3;
	oper_mux   n10ill
	( 
	.data({wire_ni0O1i_dataout, wire_niO01l_dataout, wire_n0i1iO_dataout, wire_n0Oi0l_dataout, wire_n1i0OO_dataout, wire_n1OlOi_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[32]}}}),
	.o(wire_n10ill_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10ill.width_data = 8,
		n10ill.width_sel = 3;
	oper_mux   n10ilO
	( 
	.data({wire_ni0O1l_dataout, wire_niO01O_dataout, wire_n0i1li_dataout, wire_n0Oi0O_dataout, wire_n1ii1i_dataout, wire_n1OlOl_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[33]}}}),
	.o(wire_n10ilO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10ilO.width_data = 8,
		n10ilO.width_sel = 3;
	oper_mux   n10iOi
	( 
	.data({wire_ni0O1O_dataout, wire_niO00i_dataout, wire_n0i1ll_dataout, wire_n0Oiii_dataout, wire_n1ii1l_dataout, wire_n1OlOO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[34]}}}),
	.o(wire_n10iOi_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10iOi.width_data = 8,
		n10iOi.width_sel = 3;
	oper_mux   n10iOl
	( 
	.data({wire_ni0O0i_dataout, wire_niO00l_dataout, wire_n0i1lO_dataout, wire_n0Oiil_dataout, wire_n1ii1O_dataout, wire_n1OO1i_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[35]}}}),
	.o(wire_n10iOl_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10iOl.width_data = 8,
		n10iOl.width_sel = 3;
	oper_mux   n10iOO
	( 
	.data({wire_ni0O0l_dataout, wire_niO00O_dataout, wire_n0i1Oi_dataout, wire_n0OiiO_dataout, wire_n1ii0i_dataout, wire_n1OO1l_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[36]}}}),
	.o(wire_n10iOO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10iOO.width_data = 8,
		n10iOO.width_sel = 3;
	oper_mux   n10l0i
	( 
	.data({wire_ni0OiO_dataout, wire_niO0li_dataout, wire_n0i01l_dataout, wire_n0OiOi_dataout, wire_n1iiil_dataout, wire_n1OO0O_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[40]}}}),
	.o(wire_n10l0i_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10l0i.width_data = 8,
		n10l0i.width_sel = 3;
	oper_mux   n10l0l
	( 
	.data({wire_ni0Oli_dataout, wire_niO0ll_dataout, wire_n0i01O_dataout, wire_n0OiOl_dataout, wire_n1iiiO_dataout, wire_n1OOii_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[41]}}}),
	.o(wire_n10l0l_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10l0l.width_data = 8,
		n10l0l.width_sel = 3;
	oper_mux   n10l0O
	( 
	.data({wire_ni0Oll_dataout, wire_niO0lO_dataout, wire_n0i00i_dataout, wire_n0OiOO_dataout, wire_n1iili_dataout, wire_n1OOil_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[42]}}}),
	.o(wire_n10l0O_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10l0O.width_data = 8,
		n10l0O.width_sel = 3;
	oper_mux   n10l1i
	( 
	.data({wire_ni0O0O_dataout, wire_niO0ii_dataout, wire_n0i1Ol_dataout, wire_n0Oili_dataout, wire_n1ii0l_dataout, wire_n1OO1O_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[37]}}}),
	.o(wire_n10l1i_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10l1i.width_data = 8,
		n10l1i.width_sel = 3;
	oper_mux   n10l1l
	( 
	.data({wire_ni0Oii_dataout, wire_niO0il_dataout, wire_n0i1OO_dataout, wire_n0Oill_dataout, wire_n1ii0O_dataout, wire_n1OO0i_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[38]}}}),
	.o(wire_n10l1l_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10l1l.width_data = 8,
		n10l1l.width_sel = 3;
	oper_mux   n10l1O
	( 
	.data({wire_ni0Oil_dataout, wire_niO0iO_dataout, wire_n0i01i_dataout, wire_n0OilO_dataout, wire_n1iiii_dataout, wire_n1OO0l_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[39]}}}),
	.o(wire_n10l1O_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10l1O.width_data = 8,
		n10l1O.width_sel = 3;
	oper_mux   n10lii
	( 
	.data({wire_ni0OlO_dataout, wire_niO0Oi_dataout, wire_n0i00l_dataout, wire_n0Ol1i_dataout, wire_n1iill_dataout, wire_n1OOiO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[43]}}}),
	.o(wire_n10lii_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10lii.width_data = 8,
		n10lii.width_sel = 3;
	oper_mux   n10lil
	( 
	.data({wire_ni0OOi_dataout, wire_niO0Ol_dataout, wire_n0i00O_dataout, wire_n0Ol1l_dataout, wire_n1iilO_dataout, wire_n1OOli_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[44]}}}),
	.o(wire_n10lil_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10lil.width_data = 8,
		n10lil.width_sel = 3;
	oper_mux   n10liO
	( 
	.data({wire_ni0OOl_dataout, wire_niO0OO_dataout, wire_n0i0ii_dataout, wire_n0Ol1O_dataout, wire_n1iiOi_dataout, wire_n1OOll_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[45]}}}),
	.o(wire_n10liO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10liO.width_data = 8,
		n10liO.width_sel = 3;
	oper_mux   n10lli
	( 
	.data({wire_ni0OOO_dataout, wire_niOi1i_dataout, wire_n0i0il_dataout, wire_n0Ol0i_dataout, wire_n1iiOl_dataout, wire_n1OOlO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[46]}}}),
	.o(wire_n10lli_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10lli.width_data = 8,
		n10lli.width_sel = 3;
	oper_mux   n10lll
	( 
	.data({wire_nii11i_dataout, wire_niOi1l_dataout, wire_n0i0iO_dataout, wire_n0Ol0l_dataout, wire_n1iiOO_dataout, wire_n1OOOi_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[47]}}}),
	.o(wire_n10lll_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10lll.width_data = 8,
		n10lll.width_sel = 3;
	oper_mux   n10llO
	( 
	.data({wire_nii11l_dataout, wire_niOi1O_dataout, wire_n0i0li_dataout, wire_n0Ol0O_dataout, wire_n1il1i_dataout, wire_n1OOOl_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[48]}}}),
	.o(wire_n10llO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10llO.width_data = 8,
		n10llO.width_sel = 3;
	oper_mux   n10lOi
	( 
	.data({wire_nii11O_dataout, wire_niOi0i_dataout, wire_n0i0ll_dataout, wire_n0Olii_dataout, wire_n1il1l_dataout, wire_n1OOOO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[49]}}}),
	.o(wire_n10lOi_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10lOi.width_data = 8,
		n10lOi.width_sel = 3;
	oper_mux   n10lOl
	( 
	.data({wire_nii10i_dataout, wire_niOi0l_dataout, wire_n0i0lO_dataout, wire_n0Olil_dataout, wire_n1il1O_dataout, wire_n0111i_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[50]}}}),
	.o(wire_n10lOl_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10lOl.width_data = 8,
		n10lOl.width_sel = 3;
	oper_mux   n10lOO
	( 
	.data({wire_nii10l_dataout, wire_niOi0O_dataout, wire_n0i0Oi_dataout, wire_n0OliO_dataout, wire_n1il0i_dataout, wire_n0111l_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[51]}}}),
	.o(wire_n10lOO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10lOO.width_data = 8,
		n10lOO.width_sel = 3;
	oper_mux   n10O0i
	( 
	.data({wire_nii1iO_dataout, wire_niOili_dataout, wire_n0ii1l_dataout, wire_n0OlOi_dataout, wire_n1ilil_dataout, wire_n0110O_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[55]}}}),
	.o(wire_n10O0i_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10O0i.width_data = 8,
		n10O0i.width_sel = 3;
	oper_mux   n10O0l
	( 
	.data({wire_nii1li_dataout, wire_niOill_dataout, wire_n0ii1O_dataout, wire_n0OlOl_dataout, wire_n1iliO_dataout, wire_n011ii_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[56]}}}),
	.o(wire_n10O0l_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10O0l.width_data = 8,
		n10O0l.width_sel = 3;
	oper_mux   n10O0O
	( 
	.data({wire_nii1ll_dataout, wire_niOilO_dataout, wire_n0ii0i_dataout, wire_n0OlOO_dataout, wire_n1illi_dataout, wire_n011il_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[57]}}}),
	.o(wire_n10O0O_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10O0O.width_data = 8,
		n10O0O.width_sel = 3;
	oper_mux   n10O1i
	( 
	.data({wire_nii10O_dataout, wire_niOiii_dataout, wire_n0i0Ol_dataout, wire_n0Olli_dataout, wire_n1il0l_dataout, wire_n0111O_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[52]}}}),
	.o(wire_n10O1i_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10O1i.width_data = 8,
		n10O1i.width_sel = 3;
	oper_mux   n10O1l
	( 
	.data({wire_nii1ii_dataout, wire_niOiil_dataout, wire_n0i0OO_dataout, wire_n0Olll_dataout, wire_n1il0O_dataout, wire_n0110i_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[53]}}}),
	.o(wire_n10O1l_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10O1l.width_data = 8,
		n10O1l.width_sel = 3;
	oper_mux   n10O1O
	( 
	.data({wire_nii1il_dataout, wire_niOiiO_dataout, wire_n0ii1i_dataout, wire_n0OllO_dataout, wire_n1ilii_dataout, wire_n0110l_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[54]}}}),
	.o(wire_n10O1O_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10O1O.width_data = 8,
		n10O1O.width_sel = 3;
	oper_mux   n10Oii
	( 
	.data({wire_nii1lO_dataout, wire_niOiOi_dataout, wire_n0ii0l_dataout, wire_n0OO1i_dataout, wire_n1illl_dataout, wire_n011iO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[58]}}}),
	.o(wire_n10Oii_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10Oii.width_data = 8,
		n10Oii.width_sel = 3;
	oper_mux   n10Oil
	( 
	.data({wire_nii1Oi_dataout, wire_niOiOl_dataout, wire_n0ii0O_dataout, wire_n0OO1l_dataout, wire_n1illO_dataout, wire_n011li_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[59]}}}),
	.o(wire_n10Oil_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10Oil.width_data = 8,
		n10Oil.width_sel = 3;
	oper_mux   n10OiO
	( 
	.data({wire_nii1Ol_dataout, wire_niOiOO_dataout, wire_n0iiii_dataout, wire_n0OO1O_dataout, wire_n1ilOi_dataout, wire_n011ll_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[60]}}}),
	.o(wire_n10OiO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10OiO.width_data = 8,
		n10OiO.width_sel = 3;
	oper_mux   n10Oli
	( 
	.data({wire_nii1OO_dataout, wire_niOl1i_dataout, wire_n0iiil_dataout, wire_n0OO0i_dataout, wire_n1ilOl_dataout, wire_n011lO_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[61]}}}),
	.o(wire_n10Oli_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10Oli.width_data = 8,
		n10Oli.width_sel = 3;
	oper_mux   n10Oll
	( 
	.data({wire_nii01i_dataout, wire_niOl1l_dataout, wire_n0iiiO_dataout, wire_n0OO0l_dataout, wire_n1ilOO_dataout, wire_n011Oi_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[62]}}}),
	.o(wire_n10Oll_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10Oll.width_data = 8,
		n10Oll.width_sel = 3;
	oper_mux   n10OlO
	( 
	.data({wire_nii01l_dataout, wire_niOl1O_dataout, wire_n0iili_dataout, wire_n0OO0O_dataout, wire_n1iO1i_dataout, wire_n011Ol_dataout, {2{wire_nl0l0Ol_byte_des_fifo_data_in[63]}}}),
	.o(wire_n10OlO_o),
	.sel({rwa_6g_en, rdwidth, rbytord_2sym_en}));
	defparam
		n10OlO.width_data = 8,
		n10OlO.width_sel = 3;
	oper_mux   nii00i
	( 
	.data({nlli1l, nlilOl, nlli1l, nliOOO, nlli1l, nlilOl, nlli1l, nll01i, nlli1l, nlilOl, nlli1l, nliOOO, nlli1l, nlilOl, {2{nlli1l}}}),
	.o(wire_nii00i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii00i.width_data = 16,
		nii00i.width_sel = 4;
	oper_mux   nii00l
	( 
	.data({nlli1O, nlilOO, nlli1O, nll11i, nlli1O, nlilOO, nlli1O, nll01l, nlli1O, nlilOO, nlli1O, nll11i, nlli1O, nlilOO, {2{nlli1O}}}),
	.o(wire_nii00l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii00l.width_data = 16,
		nii00l.width_sel = 4;
	oper_mux   nii00O
	( 
	.data({nlli0i, nliO1i, nlli0i, nll11l, nlli0i, nliO1i, nlli0i, nll01O, nlli0i, nliO1i, nlli0i, nll11l, nlli0i, nliO1i, {2{nlli0i}}}),
	.o(wire_nii00O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii00O.width_data = 16,
		nii00O.width_sel = 4;
	oper_mux   nii01O
	( 
	.data({nlli1i, nlilOi, nlli1i, nliOOl, nlli1i, nlilOi, nlli1i, nll1OO, nlli1i, nlilOi, nlli1i, nliOOl, nlli1i, nlilOi, {2{nlli1i}}}),
	.o(wire_nii01O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii01O.width_data = 16,
		nii01O.width_sel = 4;
	oper_mux   nii0ii
	( 
	.data({nlli0l, nliO1l, nlli0l, nll11O, nlli0l, nliO1l, nlli0l, nll00i, nlli0l, nliO1l, nlli0l, nll11O, nlli0l, nliO1l, {2{nlli0l}}}),
	.o(wire_nii0ii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0ii.width_data = 16,
		nii0ii.width_sel = 4;
	oper_mux   nii0il
	( 
	.data({nlli0O, nliO1O, nlli0O, nll10i, nlli0O, nliO1O, nlli0O, nll00l, nlli0O, nliO1O, nlli0O, nll10i, nlli0O, nliO1O, {2{nlli0O}}}),
	.o(wire_nii0il_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0il.width_data = 16,
		nii0il.width_sel = 4;
	oper_mux   nii0iO
	( 
	.data({nlliii, nliO0i, nlliii, nll10l, nlliii, nliO0i, nlliii, nll00O, nlliii, nliO0i, nlliii, nll10l, nlliii, nliO0i, {2{nlliii}}}),
	.o(wire_nii0iO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0iO.width_data = 16,
		nii0iO.width_sel = 4;
	oper_mux   nii0li
	( 
	.data({nlliil, nliO0l, nlliil, nll10O, nlliil, nliO0l, nlliil, nll0ii, nlliil, nliO0l, nlliil, nll10O, nlliil, nliO0l, {2{nlliil}}}),
	.o(wire_nii0li_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0li.width_data = 16,
		nii0li.width_sel = 4;
	oper_mux   nii0ll
	( 
	.data({nlliiO, nliO0O, nlliiO, nll1ii, nlliiO, nliO0O, nlliiO, nll0il, nlliiO, nliO0O, nlliiO, nll1ii, nlliiO, nliO0O, {2{nlliiO}}}),
	.o(wire_nii0ll_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0ll.width_data = 16,
		nii0ll.width_sel = 4;
	oper_mux   nii0lO
	( 
	.data({nllili, nliOii, nllili, nll1il, nllili, nliOii, nllili, nll0iO, nllili, nliOii, nllili, nll1il, nllili, nliOii, {2{nllili}}}),
	.o(wire_nii0lO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0lO.width_data = 16,
		nii0lO.width_sel = 4;
	oper_mux   nii0Oi
	( 
	.data({nllill, nliOil, nllill, nll1iO, nllill, nliOil, nllill, nll0li, nllill, nliOil, nllill, nll1iO, nllill, nliOil, {2{nllill}}}),
	.o(wire_nii0Oi_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0Oi.width_data = 16,
		nii0Oi.width_sel = 4;
	oper_mux   nii0Ol
	( 
	.data({nllilO, nliOiO, nllilO, nll1li, nllilO, nliOiO, nllilO, nll0ll, nllilO, nliOiO, nllilO, nll1li, nllilO, nliOiO, {2{nllilO}}}),
	.o(wire_nii0Ol_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0Ol.width_data = 16,
		nii0Ol.width_sel = 4;
	oper_mux   nii0OO
	( 
	.data({nlliOi, nliOli, nlliOi, nll1ll, nlliOi, nliOli, nlliOi, nll0lO, nlliOi, nliOli, nlliOi, nll1ll, nlliOi, nliOli, {2{nlliOi}}}),
	.o(wire_nii0OO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nii0OO.width_data = 16,
		nii0OO.width_sel = 4;
	oper_mux   niii0i
	( 
	.data({nlll1l, nliOOl, nlll1l, nll1OO, nlll1l, nliOOl, nlll1l, nlli1i, nlll1l, nliOOl, nlll1l, nll1OO, nlll1l, nliOOl, {2{nlll1l}}}),
	.o(wire_niii0i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niii0i.width_data = 16,
		niii0i.width_sel = 4;
	oper_mux   niii0l
	( 
	.data({nlll1O, nliOOO, nlll1O, nll01i, nlll1O, nliOOO, nlll1O, nlli1l, nlll1O, nliOOO, nlll1O, nll01i, nlll1O, nliOOO, {2{nlll1O}}}),
	.o(wire_niii0l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niii0l.width_data = 16,
		niii0l.width_sel = 4;
	oper_mux   niii0O
	( 
	.data({nlll0i, nll11i, nlll0i, nll01l, nlll0i, nll11i, nlll0i, nlli1O, nlll0i, nll11i, nlll0i, nll01l, nlll0i, nll11i, {2{nlll0i}}}),
	.o(wire_niii0O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niii0O.width_data = 16,
		niii0O.width_sel = 4;
	oper_mux   niii1i
	( 
	.data({nlliOl, nliOll, nlliOl, nll1lO, nlliOl, nliOll, nlliOl, nll0Oi, nlliOl, nliOll, nlliOl, nll1lO, nlliOl, nliOll, {2{nlliOl}}}),
	.o(wire_niii1i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niii1i.width_data = 16,
		niii1i.width_sel = 4;
	oper_mux   niii1l
	( 
	.data({nlliOO, nliOlO, nlliOO, nll1Oi, nlliOO, nliOlO, nlliOO, nll0Ol, nlliOO, nliOlO, nlliOO, nll1Oi, nlliOO, nliOlO, {2{nlliOO}}}),
	.o(wire_niii1l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niii1l.width_data = 16,
		niii1l.width_sel = 4;
	oper_mux   niii1O
	( 
	.data({nlll1i, nliOOi, nlll1i, nll1Ol, nlll1i, nliOOi, nlll1i, nll0OO, nlll1i, nliOOi, nlll1i, nll1Ol, nlll1i, nliOOi, {2{nlll1i}}}),
	.o(wire_niii1O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niii1O.width_data = 16,
		niii1O.width_sel = 4;
	oper_mux   niiiii
	( 
	.data({nlll0l, nll11l, nlll0l, nll01O, nlll0l, nll11l, nlll0l, nlli0i, nlll0l, nll11l, nlll0l, nll01O, nlll0l, nll11l, {2{nlll0l}}}),
	.o(wire_niiiii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiiii.width_data = 16,
		niiiii.width_sel = 4;
	oper_mux   niiiil
	( 
	.data({nlll0O, nll11O, nlll0O, nll00i, nlll0O, nll11O, nlll0O, nlli0l, nlll0O, nll11O, nlll0O, nll00i, nlll0O, nll11O, {2{nlll0O}}}),
	.o(wire_niiiil_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiiil.width_data = 16,
		niiiil.width_sel = 4;
	oper_mux   niiiiO
	( 
	.data({nlllii, nll10i, nlllii, nll00l, nlllii, nll10i, nlllii, nlli0O, nlllii, nll10i, nlllii, nll00l, nlllii, nll10i, {2{nlllii}}}),
	.o(wire_niiiiO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiiiO.width_data = 16,
		niiiiO.width_sel = 4;
	oper_mux   niiili
	( 
	.data({nlllil, nll10l, nlllil, nll00O, nlllil, nll10l, nlllil, nlliii, nlllil, nll10l, nlllil, nll00O, nlllil, nll10l, {2{nlllil}}}),
	.o(wire_niiili_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiili.width_data = 16,
		niiili.width_sel = 4;
	oper_mux   niiill
	( 
	.data({nllliO, nll10O, nllliO, nll0ii, nllliO, nll10O, nllliO, nlliil, nllliO, nll10O, nllliO, nll0ii, nllliO, nll10O, {2{nllliO}}}),
	.o(wire_niiill_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiill.width_data = 16,
		niiill.width_sel = 4;
	oper_mux   niiilO
	( 
	.data({nlllli, nll1ii, nlllli, nll0il, nlllli, nll1ii, nlllli, nlliiO, nlllli, nll1ii, nlllli, nll0il, nlllli, nll1ii, {2{nlllli}}}),
	.o(wire_niiilO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiilO.width_data = 16,
		niiilO.width_sel = 4;
	oper_mux   niiiOi
	( 
	.data({nlllll, nll1il, nlllll, nll0iO, nlllll, nll1il, nlllll, nllili, nlllll, nll1il, nlllll, nll0iO, nlllll, nll1il, {2{nlllll}}}),
	.o(wire_niiiOi_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiiOi.width_data = 16,
		niiiOi.width_sel = 4;
	oper_mux   niiiOl
	( 
	.data({nllllO, nll1iO, nllllO, nll0li, nllllO, nll1iO, nllllO, nllill, nllllO, nll1iO, nllllO, nll0li, nllllO, nll1iO, {2{nllllO}}}),
	.o(wire_niiiOl_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiiOl.width_data = 16,
		niiiOl.width_sel = 4;
	oper_mux   niiiOO
	( 
	.data({nlllOi, nll1li, nlllOi, nll0ll, nlllOi, nll1li, nlllOi, nllilO, nlllOi, nll1li, nlllOi, nll0ll, nlllOi, nll1li, {2{nlllOi}}}),
	.o(wire_niiiOO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiiOO.width_data = 16,
		niiiOO.width_sel = 4;
	oper_mux   niil0i
	( 
	.data({nllO1l, nll1Ol, nllO1l, nll0OO, nllO1l, nll1Ol, nllO1l, nlll1i, nllO1l, nll1Ol, nllO1l, nll0OO, nllO1l, nll1Ol, {2{nllO1l}}}),
	.o(wire_niil0i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niil0i.width_data = 16,
		niil0i.width_sel = 4;
	oper_mux   niil0l
	( 
	.data({nllO1O, nll1OO, nllO1O, nlli1i, nllO1O, nll1OO, nllO1O, nlll1l, nllO1O, nll1OO, nllO1O, nlli1i, nllO1O, nll1OO, {2{nllO1O}}}),
	.o(wire_niil0l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niil0l.width_data = 16,
		niil0l.width_sel = 4;
	oper_mux   niil0O
	( 
	.data({nllO0i, nll01i, nllO0i, nlli1l, nllO0i, nll01i, nllO0i, nlll1O, nllO0i, nll01i, nllO0i, nlli1l, nllO0i, nll01i, {2{nllO0i}}}),
	.o(wire_niil0O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niil0O.width_data = 16,
		niil0O.width_sel = 4;
	oper_mux   niil1i
	( 
	.data({nlllOl, nll1ll, nlllOl, nll0lO, nlllOl, nll1ll, nlllOl, nlliOi, nlllOl, nll1ll, nlllOl, nll0lO, nlllOl, nll1ll, {2{nlllOl}}}),
	.o(wire_niil1i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niil1i.width_data = 16,
		niil1i.width_sel = 4;
	oper_mux   niil1l
	( 
	.data({nlllOO, nll1lO, nlllOO, nll0Oi, nlllOO, nll1lO, nlllOO, nlliOl, nlllOO, nll1lO, nlllOO, nll0Oi, nlllOO, nll1lO, {2{nlllOO}}}),
	.o(wire_niil1l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niil1l.width_data = 16,
		niil1l.width_sel = 4;
	oper_mux   niil1O
	( 
	.data({nllO1i, nll1Oi, nllO1i, nll0Ol, nllO1i, nll1Oi, nllO1i, nlliOO, nllO1i, nll1Oi, nllO1i, nll0Ol, nllO1i, nll1Oi, {2{nllO1i}}}),
	.o(wire_niil1O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niil1O.width_data = 16,
		niil1O.width_sel = 4;
	oper_mux   niilii
	( 
	.data({nllO0l, nll01l, nllO0l, nlli1O, nllO0l, nll01l, nllO0l, nlll0i, nllO0l, nll01l, nllO0l, nlli1O, nllO0l, nll01l, {2{nllO0l}}}),
	.o(wire_niilii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niilii.width_data = 16,
		niilii.width_sel = 4;
	oper_mux   niilil
	( 
	.data({nllO0O, nll01O, nllO0O, nlli0i, nllO0O, nll01O, nllO0O, nlll0l, nllO0O, nll01O, nllO0O, nlli0i, nllO0O, nll01O, {2{nllO0O}}}),
	.o(wire_niilil_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niilil.width_data = 16,
		niilil.width_sel = 4;
	oper_mux   niiliO
	( 
	.data({nllOii, nll00i, nllOii, nlli0l, nllOii, nll00i, nllOii, nlll0O, nllOii, nll00i, nllOii, nlli0l, nllOii, nll00i, {2{nllOii}}}),
	.o(wire_niiliO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiliO.width_data = 16,
		niiliO.width_sel = 4;
	oper_mux   niilli
	( 
	.data({nllOil, nll00l, nllOil, nlli0O, nllOil, nll00l, nllOil, nlllii, nllOil, nll00l, nllOil, nlli0O, nllOil, nll00l, {2{nllOil}}}),
	.o(wire_niilli_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niilli.width_data = 16,
		niilli.width_sel = 4;
	oper_mux   niilll
	( 
	.data({nllOiO, nll00O, nllOiO, nlliii, nllOiO, nll00O, nllOiO, nlllil, nllOiO, nll00O, nllOiO, nlliii, nllOiO, nll00O, {2{nllOiO}}}),
	.o(wire_niilll_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niilll.width_data = 16,
		niilll.width_sel = 4;
	oper_mux   niillO
	( 
	.data({nllOli, nll0ii, nllOli, nlliil, nllOli, nll0ii, nllOli, nllliO, nllOli, nll0ii, nllOli, nlliil, nllOli, nll0ii, {2{nllOli}}}),
	.o(wire_niillO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niillO.width_data = 16,
		niillO.width_sel = 4;
	oper_mux   niilOi
	( 
	.data({nllOll, nll0il, nllOll, nlliiO, nllOll, nll0il, nllOll, nlllli, nllOll, nll0il, nllOll, nlliiO, nllOll, nll0il, {2{nllOll}}}),
	.o(wire_niilOi_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niilOi.width_data = 16,
		niilOi.width_sel = 4;
	oper_mux   niilOl
	( 
	.data({nllOlO, nll0iO, nllOlO, nllili, nllOlO, nll0iO, nllOlO, nlllll, nllOlO, nll0iO, nllOlO, nllili, nllOlO, nll0iO, {2{nllOlO}}}),
	.o(wire_niilOl_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niilOl.width_data = 16,
		niilOl.width_sel = 4;
	oper_mux   niilOO
	( 
	.data({nllOOi, nll0li, nllOOi, nllill, nllOOi, nll0li, nllOOi, nllllO, nllOOi, nll0li, nllOOi, nllill, nllOOi, nll0li, {2{nllOOi}}}),
	.o(wire_niilOO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niilOO.width_data = 16,
		niilOO.width_sel = 4;
	oper_mux   niiO0i
	( 
	.data({nlO11l, nll0Ol, nlO11l, nlliOO, nlO11l, nll0Ol, nlO11l, nllO1i, nlO11l, nll0Ol, nlO11l, nlliOO, nlO11l, nll0Ol, {2{nlO11l}}}),
	.o(wire_niiO0i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiO0i.width_data = 16,
		niiO0i.width_sel = 4;
	oper_mux   niiO0l
	( 
	.data({nlO11O, nll0OO, nlO11O, nlll1i, nlO11O, nll0OO, nlO11O, nllO1l, nlO11O, nll0OO, nlO11O, nlll1i, nlO11O, nll0OO, {2{nlO11O}}}),
	.o(wire_niiO0l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiO0l.width_data = 16,
		niiO0l.width_sel = 4;
	oper_mux   niiO0O
	( 
	.data({nlO10i, nlli1i, nlO10i, nlll1l, nlO10i, nlli1i, nlO10i, nllO1O, nlO10i, nlli1i, nlO10i, nlll1l, nlO10i, nlli1i, {2{nlO10i}}}),
	.o(wire_niiO0O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiO0O.width_data = 16,
		niiO0O.width_sel = 4;
	oper_mux   niiO1i
	( 
	.data({nllOOl, nll0ll, nllOOl, nllilO, nllOOl, nll0ll, nllOOl, nlllOi, nllOOl, nll0ll, nllOOl, nllilO, nllOOl, nll0ll, {2{nllOOl}}}),
	.o(wire_niiO1i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiO1i.width_data = 16,
		niiO1i.width_sel = 4;
	oper_mux   niiO1l
	( 
	.data({nllOOO, nll0lO, nllOOO, nlliOi, nllOOO, nll0lO, nllOOO, nlllOl, nllOOO, nll0lO, nllOOO, nlliOi, nllOOO, nll0lO, {2{nllOOO}}}),
	.o(wire_niiO1l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiO1l.width_data = 16,
		niiO1l.width_sel = 4;
	oper_mux   niiO1O
	( 
	.data({nlO11i, nll0Oi, nlO11i, nlliOl, nlO11i, nll0Oi, nlO11i, nlllOO, nlO11i, nll0Oi, nlO11i, nlliOl, nlO11i, nll0Oi, {2{nlO11i}}}),
	.o(wire_niiO1O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiO1O.width_data = 16,
		niiO1O.width_sel = 4;
	oper_mux   niiOii
	( 
	.data({nlO10l, nlli1l, nlO10l, nlll1O, nlO10l, nlli1l, nlO10l, nllO0i, nlO10l, nlli1l, nlO10l, nlll1O, nlO10l, nlli1l, {2{nlO10l}}}),
	.o(wire_niiOii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOii.width_data = 16,
		niiOii.width_sel = 4;
	oper_mux   niiOil
	( 
	.data({nlO10O, nlli1O, nlO10O, nlll0i, nlO10O, nlli1O, nlO10O, nllO0l, nlO10O, nlli1O, nlO10O, nlll0i, nlO10O, nlli1O, {2{nlO10O}}}),
	.o(wire_niiOil_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOil.width_data = 16,
		niiOil.width_sel = 4;
	oper_mux   niiOiO
	( 
	.data({nlO1ii, nlli0i, nlO1ii, nlll0l, nlO1ii, nlli0i, nlO1ii, nllO0O, nlO1ii, nlli0i, nlO1ii, nlll0l, nlO1ii, nlli0i, {2{nlO1ii}}}),
	.o(wire_niiOiO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOiO.width_data = 16,
		niiOiO.width_sel = 4;
	oper_mux   niiOli
	( 
	.data({nlO1il, nlli0l, nlO1il, nlll0O, nlO1il, nlli0l, nlO1il, nllOii, nlO1il, nlli0l, nlO1il, nlll0O, nlO1il, nlli0l, {2{nlO1il}}}),
	.o(wire_niiOli_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOli.width_data = 16,
		niiOli.width_sel = 4;
	oper_mux   niiOll
	( 
	.data({nlO1iO, nlli0O, nlO1iO, nlllii, nlO1iO, nlli0O, nlO1iO, nllOil, nlO1iO, nlli0O, nlO1iO, nlllii, nlO1iO, nlli0O, {2{nlO1iO}}}),
	.o(wire_niiOll_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOll.width_data = 16,
		niiOll.width_sel = 4;
	oper_mux   niiOlO
	( 
	.data({nlO1li, nlliii, nlO1li, nlllil, nlO1li, nlliii, nlO1li, nllOiO, nlO1li, nlliii, nlO1li, nlllil, nlO1li, nlliii, {2{nlO1li}}}),
	.o(wire_niiOlO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOlO.width_data = 16,
		niiOlO.width_sel = 4;
	oper_mux   niiOOi
	( 
	.data({nlO1ll, nlliil, nlO1ll, nllliO, nlO1ll, nlliil, nlO1ll, nllOli, nlO1ll, nlliil, nlO1ll, nllliO, nlO1ll, nlliil, {2{nlO1ll}}}),
	.o(wire_niiOOi_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOOi.width_data = 16,
		niiOOi.width_sel = 4;
	oper_mux   niiOOl
	( 
	.data({nlO1lO, nlliiO, nlO1lO, nlllli, nlO1lO, nlliiO, nlO1lO, nllOll, nlO1lO, nlliiO, nlO1lO, nlllli, nlO1lO, nlliiO, {2{nlO1lO}}}),
	.o(wire_niiOOl_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOOl.width_data = 16,
		niiOOl.width_sel = 4;
	oper_mux   niiOOO
	( 
	.data({nlO1Oi, nllili, nlO1Oi, nlllll, nlO1Oi, nllili, nlO1Oi, nllOlO, nlO1Oi, nllili, nlO1Oi, nlllll, nlO1Oi, nllili, {2{nlO1Oi}}}),
	.o(wire_niiOOO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niiOOO.width_data = 16,
		niiOOO.width_sel = 4;
	oper_mux   nil10i
	( 
	.data({nlO01l, nlliOl, nlO01l, nlllOO, nlO01l, nlliOl, nlO01l, nlO11i, nlO01l, nlliOl, nlO01l, nlllOO, nlO01l, nlliOl, {2{nlO01l}}}),
	.o(wire_nil10i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nil10i.width_data = 16,
		nil10i.width_sel = 4;
	oper_mux   nil10l
	( 
	.data({nlO01O, nlliOO, nlO01O, nllO1i, nlO01O, nlliOO, nlO01O, nlO11l, nlO01O, nlliOO, nlO01O, nllO1i, nlO01O, nlliOO, {2{nlO01O}}}),
	.o(wire_nil10l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nil10l.width_data = 16,
		nil10l.width_sel = 4;
	oper_mux   nil10O
	( 
	.data({nlO00i, nlll1i, nlO00i, nllO1l, nlO00i, nlll1i, nlO00i, nlO11O, nlO00i, nlll1i, nlO00i, nllO1l, nlO00i, nlll1i, {2{nlO00i}}}),
	.o(wire_nil10O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nil10O.width_data = 16,
		nil10O.width_sel = 4;
	oper_mux   nil11i
	( 
	.data({nlO1Ol, nllill, nlO1Ol, nllllO, nlO1Ol, nllill, nlO1Ol, nllOOi, nlO1Ol, nllill, nlO1Ol, nllllO, nlO1Ol, nllill, {2{nlO1Ol}}}),
	.o(wire_nil11i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nil11i.width_data = 16,
		nil11i.width_sel = 4;
	oper_mux   nil11l
	( 
	.data({nlO1OO, nllilO, nlO1OO, nlllOi, nlO1OO, nllilO, nlO1OO, nllOOl, nlO1OO, nllilO, nlO1OO, nlllOi, nlO1OO, nllilO, {2{nlO1OO}}}),
	.o(wire_nil11l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nil11l.width_data = 16,
		nil11l.width_sel = 4;
	oper_mux   nil11O
	( 
	.data({nlO01i, nlliOi, nlO01i, nlllOl, nlO01i, nlliOi, nlO01i, nllOOO, nlO01i, nlliOi, nlO01i, nlllOl, nlO01i, nlliOi, {2{nlO01i}}}),
	.o(wire_nil11O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nil11O.width_data = 16,
		nil11O.width_sel = 4;
	oper_mux   nili0i
	( 
	.data({nllOOi, nllill, nllOOi, nllllO, nllOOi, nllill, {2{nllOOi}}}),
	.o(wire_nili0i_o),
	.sel({wire_nl01Oi_dataout, wire_nl01lO_dataout, wire_nl01ll_dataout}));
	defparam
		nili0i.width_data = 8,
		nili0i.width_sel = 3;
	oper_mux   nillii
	( 
	.data({nlO1Ol, nllill, nlO1Ol, nllllO, nlO1Ol, nllill, nlO1Ol, nllOOi, nlO1Ol, nllill, nlO1Ol, nllllO, nlO1Ol, nllill, {2{nlO1Ol}}}),
	.o(wire_nillii_o),
	.sel({wire_nl01Ol_dataout, wire_nl01Oi_dataout, wire_nl01lO_dataout, wire_nl01ll_dataout}));
	defparam
		nillii.width_data = 16,
		nillii.width_sel = 4;
	oper_mux   niOl0i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[0], nlll1l, wire_nl0l0Ol_byte_des_fifo_data_in[0], nllO1O, wire_nl0l0Ol_byte_des_fifo_data_in[0], nlll1l, wire_nl0l0Ol_byte_des_fifo_data_in[0], nlO10i, wire_nl0l0Ol_byte_des_fifo_data_in[0], nlll1l, wire_nl0l0Ol_byte_des_fifo_data_in[0], nllO1O, wire_nl0l0Ol_byte_des_fifo_data_in[0], nlll1l, {2{wire_nl0l0Ol_byte_des_fifo_data_in[0]}}}),
	.o(wire_niOl0i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOl0i.width_data = 16,
		niOl0i.width_sel = 4;
	oper_mux   niOl0l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[1], nlll1O, wire_nl0l0Ol_byte_des_fifo_data_in[1], nllO0i, wire_nl0l0Ol_byte_des_fifo_data_in[1], nlll1O, wire_nl0l0Ol_byte_des_fifo_data_in[1], nlO10l, wire_nl0l0Ol_byte_des_fifo_data_in[1], nlll1O, wire_nl0l0Ol_byte_des_fifo_data_in[1], nllO0i, wire_nl0l0Ol_byte_des_fifo_data_in[1], nlll1O, {2{wire_nl0l0Ol_byte_des_fifo_data_in[1]}}}),
	.o(wire_niOl0l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOl0l.width_data = 16,
		niOl0l.width_sel = 4;
	oper_mux   niOl0O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[2], nlll0i, wire_nl0l0Ol_byte_des_fifo_data_in[2], nllO0l, wire_nl0l0Ol_byte_des_fifo_data_in[2], nlll0i, wire_nl0l0Ol_byte_des_fifo_data_in[2], nlO10O, wire_nl0l0Ol_byte_des_fifo_data_in[2], nlll0i, wire_nl0l0Ol_byte_des_fifo_data_in[2], nllO0l, wire_nl0l0Ol_byte_des_fifo_data_in[2], nlll0i, {2{wire_nl0l0Ol_byte_des_fifo_data_in[2]}}}),
	.o(wire_niOl0O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOl0O.width_data = 16,
		niOl0O.width_sel = 4;
	oper_mux   niOlii
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[3], nlll0l, wire_nl0l0Ol_byte_des_fifo_data_in[3], nllO0O, wire_nl0l0Ol_byte_des_fifo_data_in[3], nlll0l, wire_nl0l0Ol_byte_des_fifo_data_in[3], nlO1ii, wire_nl0l0Ol_byte_des_fifo_data_in[3], nlll0l, wire_nl0l0Ol_byte_des_fifo_data_in[3], nllO0O, wire_nl0l0Ol_byte_des_fifo_data_in[3], nlll0l, {2{wire_nl0l0Ol_byte_des_fifo_data_in[3]}}}),
	.o(wire_niOlii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOlii.width_data = 16,
		niOlii.width_sel = 4;
	oper_mux   niOlil
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[4], nlll0O, wire_nl0l0Ol_byte_des_fifo_data_in[4], nllOii, wire_nl0l0Ol_byte_des_fifo_data_in[4], nlll0O, wire_nl0l0Ol_byte_des_fifo_data_in[4], nlO1il, wire_nl0l0Ol_byte_des_fifo_data_in[4], nlll0O, wire_nl0l0Ol_byte_des_fifo_data_in[4], nllOii, wire_nl0l0Ol_byte_des_fifo_data_in[4], nlll0O, {2{wire_nl0l0Ol_byte_des_fifo_data_in[4]}}}),
	.o(wire_niOlil_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOlil.width_data = 16,
		niOlil.width_sel = 4;
	oper_mux   niOliO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[5], nlllii, wire_nl0l0Ol_byte_des_fifo_data_in[5], nllOil, wire_nl0l0Ol_byte_des_fifo_data_in[5], nlllii, wire_nl0l0Ol_byte_des_fifo_data_in[5], nlO1iO, wire_nl0l0Ol_byte_des_fifo_data_in[5], nlllii, wire_nl0l0Ol_byte_des_fifo_data_in[5], nllOil, wire_nl0l0Ol_byte_des_fifo_data_in[5], nlllii, {2{wire_nl0l0Ol_byte_des_fifo_data_in[5]}}}),
	.o(wire_niOliO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOliO.width_data = 16,
		niOliO.width_sel = 4;
	oper_mux   niOlli
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[6], nlllil, wire_nl0l0Ol_byte_des_fifo_data_in[6], nllOiO, wire_nl0l0Ol_byte_des_fifo_data_in[6], nlllil, wire_nl0l0Ol_byte_des_fifo_data_in[6], nlO1li, wire_nl0l0Ol_byte_des_fifo_data_in[6], nlllil, wire_nl0l0Ol_byte_des_fifo_data_in[6], nllOiO, wire_nl0l0Ol_byte_des_fifo_data_in[6], nlllil, {2{wire_nl0l0Ol_byte_des_fifo_data_in[6]}}}),
	.o(wire_niOlli_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOlli.width_data = 16,
		niOlli.width_sel = 4;
	oper_mux   niOlll
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[7], nllliO, wire_nl0l0Ol_byte_des_fifo_data_in[7], nllOli, wire_nl0l0Ol_byte_des_fifo_data_in[7], nllliO, wire_nl0l0Ol_byte_des_fifo_data_in[7], nlO1ll, wire_nl0l0Ol_byte_des_fifo_data_in[7], nllliO, wire_nl0l0Ol_byte_des_fifo_data_in[7], nllOli, wire_nl0l0Ol_byte_des_fifo_data_in[7], nllliO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[7]}}}),
	.o(wire_niOlll_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOlll.width_data = 16,
		niOlll.width_sel = 4;
	oper_mux   niOllO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[8], nlllli, wire_nl0l0Ol_byte_des_fifo_data_in[8], nllOll, wire_nl0l0Ol_byte_des_fifo_data_in[8], nlllli, wire_nl0l0Ol_byte_des_fifo_data_in[8], nlO1lO, wire_nl0l0Ol_byte_des_fifo_data_in[8], nlllli, wire_nl0l0Ol_byte_des_fifo_data_in[8], nllOll, wire_nl0l0Ol_byte_des_fifo_data_in[8], nlllli, {2{wire_nl0l0Ol_byte_des_fifo_data_in[8]}}}),
	.o(wire_niOllO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOllO.width_data = 16,
		niOllO.width_sel = 4;
	oper_mux   niOlOi
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[9], nlllll, wire_nl0l0Ol_byte_des_fifo_data_in[9], nllOlO, wire_nl0l0Ol_byte_des_fifo_data_in[9], nlllll, wire_nl0l0Ol_byte_des_fifo_data_in[9], nlO1Oi, wire_nl0l0Ol_byte_des_fifo_data_in[9], nlllll, wire_nl0l0Ol_byte_des_fifo_data_in[9], nllOlO, wire_nl0l0Ol_byte_des_fifo_data_in[9], nlllll, {2{wire_nl0l0Ol_byte_des_fifo_data_in[9]}}}),
	.o(wire_niOlOi_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOlOi.width_data = 16,
		niOlOi.width_sel = 4;
	oper_mux   niOlOl
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[10], nllllO, wire_nl0l0Ol_byte_des_fifo_data_in[10], nllOOi, wire_nl0l0Ol_byte_des_fifo_data_in[10], nllllO, wire_nl0l0Ol_byte_des_fifo_data_in[10], nlO1Ol, wire_nl0l0Ol_byte_des_fifo_data_in[10], nllllO, wire_nl0l0Ol_byte_des_fifo_data_in[10], nllOOi, wire_nl0l0Ol_byte_des_fifo_data_in[10], nllllO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[10]}}}),
	.o(wire_niOlOl_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOlOl.width_data = 16,
		niOlOl.width_sel = 4;
	oper_mux   niOlOO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[11], nlllOi, wire_nl0l0Ol_byte_des_fifo_data_in[11], nllOOl, wire_nl0l0Ol_byte_des_fifo_data_in[11], nlllOi, wire_nl0l0Ol_byte_des_fifo_data_in[11], nlO1OO, wire_nl0l0Ol_byte_des_fifo_data_in[11], nlllOi, wire_nl0l0Ol_byte_des_fifo_data_in[11], nllOOl, wire_nl0l0Ol_byte_des_fifo_data_in[11], nlllOi, {2{wire_nl0l0Ol_byte_des_fifo_data_in[11]}}}),
	.o(wire_niOlOO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOlOO.width_data = 16,
		niOlOO.width_sel = 4;
	oper_mux   niOO0i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[15], nllO1l, wire_nl0l0Ol_byte_des_fifo_data_in[15], nlO11O, wire_nl0l0Ol_byte_des_fifo_data_in[15], nllO1l, wire_nl0l0Ol_byte_des_fifo_data_in[15], nlO00i, wire_nl0l0Ol_byte_des_fifo_data_in[15], nllO1l, wire_nl0l0Ol_byte_des_fifo_data_in[15], nlO11O, wire_nl0l0Ol_byte_des_fifo_data_in[15], nllO1l, {2{wire_nl0l0Ol_byte_des_fifo_data_in[15]}}}),
	.o(wire_niOO0i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOO0i.width_data = 16,
		niOO0i.width_sel = 4;
	oper_mux   niOO0l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[16], nllO1O, wire_nl0l0Ol_byte_des_fifo_data_in[16], nlO10i, wire_nl0l0Ol_byte_des_fifo_data_in[16], nllO1O, wire_nl0l0Ol_byte_des_fifo_data_in[16], wire_nl0l0Ol_byte_des_fifo_data_in[0], wire_nl0l0Ol_byte_des_fifo_data_in[16], nllO1O, wire_nl0l0Ol_byte_des_fifo_data_in[16], nlO10i, wire_nl0l0Ol_byte_des_fifo_data_in[16], nllO1O, {2{wire_nl0l0Ol_byte_des_fifo_data_in[16]}}}),
	.o(wire_niOO0l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOO0l.width_data = 16,
		niOO0l.width_sel = 4;
	oper_mux   niOO0O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[17], nllO0i, wire_nl0l0Ol_byte_des_fifo_data_in[17], nlO10l, wire_nl0l0Ol_byte_des_fifo_data_in[17], nllO0i, wire_nl0l0Ol_byte_des_fifo_data_in[17], wire_nl0l0Ol_byte_des_fifo_data_in[1], wire_nl0l0Ol_byte_des_fifo_data_in[17], nllO0i, wire_nl0l0Ol_byte_des_fifo_data_in[17], nlO10l, wire_nl0l0Ol_byte_des_fifo_data_in[17], nllO0i, {2{wire_nl0l0Ol_byte_des_fifo_data_in[17]}}}),
	.o(wire_niOO0O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOO0O.width_data = 16,
		niOO0O.width_sel = 4;
	oper_mux   niOO1i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[12], nlllOl, wire_nl0l0Ol_byte_des_fifo_data_in[12], nllOOO, wire_nl0l0Ol_byte_des_fifo_data_in[12], nlllOl, wire_nl0l0Ol_byte_des_fifo_data_in[12], nlO01i, wire_nl0l0Ol_byte_des_fifo_data_in[12], nlllOl, wire_nl0l0Ol_byte_des_fifo_data_in[12], nllOOO, wire_nl0l0Ol_byte_des_fifo_data_in[12], nlllOl, {2{wire_nl0l0Ol_byte_des_fifo_data_in[12]}}}),
	.o(wire_niOO1i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOO1i.width_data = 16,
		niOO1i.width_sel = 4;
	oper_mux   niOO1l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[13], nlllOO, wire_nl0l0Ol_byte_des_fifo_data_in[13], nlO11i, wire_nl0l0Ol_byte_des_fifo_data_in[13], nlllOO, wire_nl0l0Ol_byte_des_fifo_data_in[13], nlO01l, wire_nl0l0Ol_byte_des_fifo_data_in[13], nlllOO, wire_nl0l0Ol_byte_des_fifo_data_in[13], nlO11i, wire_nl0l0Ol_byte_des_fifo_data_in[13], nlllOO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[13]}}}),
	.o(wire_niOO1l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOO1l.width_data = 16,
		niOO1l.width_sel = 4;
	oper_mux   niOO1O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[14], nllO1i, wire_nl0l0Ol_byte_des_fifo_data_in[14], nlO11l, wire_nl0l0Ol_byte_des_fifo_data_in[14], nllO1i, wire_nl0l0Ol_byte_des_fifo_data_in[14], nlO01O, wire_nl0l0Ol_byte_des_fifo_data_in[14], nllO1i, wire_nl0l0Ol_byte_des_fifo_data_in[14], nlO11l, wire_nl0l0Ol_byte_des_fifo_data_in[14], nllO1i, {2{wire_nl0l0Ol_byte_des_fifo_data_in[14]}}}),
	.o(wire_niOO1O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOO1O.width_data = 16,
		niOO1O.width_sel = 4;
	oper_mux   niOOii
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[18], nllO0l, wire_nl0l0Ol_byte_des_fifo_data_in[18], nlO10O, wire_nl0l0Ol_byte_des_fifo_data_in[18], nllO0l, wire_nl0l0Ol_byte_des_fifo_data_in[18], wire_nl0l0Ol_byte_des_fifo_data_in[2], wire_nl0l0Ol_byte_des_fifo_data_in[18], nllO0l, wire_nl0l0Ol_byte_des_fifo_data_in[18], nlO10O, wire_nl0l0Ol_byte_des_fifo_data_in[18], nllO0l, {2{wire_nl0l0Ol_byte_des_fifo_data_in[18]}}}),
	.o(wire_niOOii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOii.width_data = 16,
		niOOii.width_sel = 4;
	oper_mux   niOOil
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[19], nllO0O, wire_nl0l0Ol_byte_des_fifo_data_in[19], nlO1ii, wire_nl0l0Ol_byte_des_fifo_data_in[19], nllO0O, wire_nl0l0Ol_byte_des_fifo_data_in[19], wire_nl0l0Ol_byte_des_fifo_data_in[3], wire_nl0l0Ol_byte_des_fifo_data_in[19], nllO0O, wire_nl0l0Ol_byte_des_fifo_data_in[19], nlO1ii, wire_nl0l0Ol_byte_des_fifo_data_in[19], nllO0O, {2{wire_nl0l0Ol_byte_des_fifo_data_in[19]}}}),
	.o(wire_niOOil_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOil.width_data = 16,
		niOOil.width_sel = 4;
	oper_mux   niOOiO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[20], nllOii, wire_nl0l0Ol_byte_des_fifo_data_in[20], nlO1il, wire_nl0l0Ol_byte_des_fifo_data_in[20], nllOii, wire_nl0l0Ol_byte_des_fifo_data_in[20], wire_nl0l0Ol_byte_des_fifo_data_in[4], wire_nl0l0Ol_byte_des_fifo_data_in[20], nllOii, wire_nl0l0Ol_byte_des_fifo_data_in[20], nlO1il, wire_nl0l0Ol_byte_des_fifo_data_in[20], nllOii, {2{wire_nl0l0Ol_byte_des_fifo_data_in[20]}}}),
	.o(wire_niOOiO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOiO.width_data = 16,
		niOOiO.width_sel = 4;
	oper_mux   niOOli
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[21], nllOil, wire_nl0l0Ol_byte_des_fifo_data_in[21], nlO1iO, wire_nl0l0Ol_byte_des_fifo_data_in[21], nllOil, wire_nl0l0Ol_byte_des_fifo_data_in[21], wire_nl0l0Ol_byte_des_fifo_data_in[5], wire_nl0l0Ol_byte_des_fifo_data_in[21], nllOil, wire_nl0l0Ol_byte_des_fifo_data_in[21], nlO1iO, wire_nl0l0Ol_byte_des_fifo_data_in[21], nllOil, {2{wire_nl0l0Ol_byte_des_fifo_data_in[21]}}}),
	.o(wire_niOOli_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOli.width_data = 16,
		niOOli.width_sel = 4;
	oper_mux   niOOll
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[22], nllOiO, wire_nl0l0Ol_byte_des_fifo_data_in[22], nlO1li, wire_nl0l0Ol_byte_des_fifo_data_in[22], nllOiO, wire_nl0l0Ol_byte_des_fifo_data_in[22], wire_nl0l0Ol_byte_des_fifo_data_in[6], wire_nl0l0Ol_byte_des_fifo_data_in[22], nllOiO, wire_nl0l0Ol_byte_des_fifo_data_in[22], nlO1li, wire_nl0l0Ol_byte_des_fifo_data_in[22], nllOiO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[22]}}}),
	.o(wire_niOOll_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOll.width_data = 16,
		niOOll.width_sel = 4;
	oper_mux   niOOlO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[23], nllOli, wire_nl0l0Ol_byte_des_fifo_data_in[23], nlO1ll, wire_nl0l0Ol_byte_des_fifo_data_in[23], nllOli, wire_nl0l0Ol_byte_des_fifo_data_in[23], wire_nl0l0Ol_byte_des_fifo_data_in[7], wire_nl0l0Ol_byte_des_fifo_data_in[23], nllOli, wire_nl0l0Ol_byte_des_fifo_data_in[23], nlO1ll, wire_nl0l0Ol_byte_des_fifo_data_in[23], nllOli, {2{wire_nl0l0Ol_byte_des_fifo_data_in[23]}}}),
	.o(wire_niOOlO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOlO.width_data = 16,
		niOOlO.width_sel = 4;
	oper_mux   niOOOi
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[24], nllOll, wire_nl0l0Ol_byte_des_fifo_data_in[24], nlO1lO, wire_nl0l0Ol_byte_des_fifo_data_in[24], nllOll, wire_nl0l0Ol_byte_des_fifo_data_in[24], wire_nl0l0Ol_byte_des_fifo_data_in[8], wire_nl0l0Ol_byte_des_fifo_data_in[24], nllOll, wire_nl0l0Ol_byte_des_fifo_data_in[24], nlO1lO, wire_nl0l0Ol_byte_des_fifo_data_in[24], nllOll, {2{wire_nl0l0Ol_byte_des_fifo_data_in[24]}}}),
	.o(wire_niOOOi_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOOi.width_data = 16,
		niOOOi.width_sel = 4;
	oper_mux   niOOOl
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[25], nllOlO, wire_nl0l0Ol_byte_des_fifo_data_in[25], nlO1Oi, wire_nl0l0Ol_byte_des_fifo_data_in[25], nllOlO, wire_nl0l0Ol_byte_des_fifo_data_in[25], wire_nl0l0Ol_byte_des_fifo_data_in[9], wire_nl0l0Ol_byte_des_fifo_data_in[25], nllOlO, wire_nl0l0Ol_byte_des_fifo_data_in[25], nlO1Oi, wire_nl0l0Ol_byte_des_fifo_data_in[25], nllOlO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[25]}}}),
	.o(wire_niOOOl_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOOl.width_data = 16,
		niOOOl.width_sel = 4;
	oper_mux   niOOOO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[26], nllOOi, wire_nl0l0Ol_byte_des_fifo_data_in[26], nlO1Ol, wire_nl0l0Ol_byte_des_fifo_data_in[26], nllOOi, wire_nl0l0Ol_byte_des_fifo_data_in[26], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[26], nllOOi, wire_nl0l0Ol_byte_des_fifo_data_in[26], nlO1Ol, wire_nl0l0Ol_byte_des_fifo_data_in[26], nllOOi, {2{wire_nl0l0Ol_byte_des_fifo_data_in[26]}}}),
	.o(wire_niOOOO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		niOOOO.width_data = 16,
		niOOOO.width_sel = 4;
	oper_mux   nl001i
	( 
	.data({1'b0, wire_nl00il_dataout, wire_nl0iiO_dataout, 1'b0, wire_nl0O1i_dataout, wire_nli1OO_dataout, wire_nliiil_dataout, 1'b0}),
	.o(wire_nl001i_o),
	.sel({rbytord_2sym_en, rbytorden[1:0]}));
	defparam
		nl001i.width_data = 8,
		nl001i.width_sel = 3;
	oper_mux   nl001l
	( 
	.data({1'b0, wire_nl00lO_dataout, wire_nl0iOi_dataout, 1'b0, wire_nl0O0l_dataout, wire_nli01O_dataout, wire_nliill_dataout, 1'b0}),
	.o(wire_nl001l_o),
	.sel({rbytord_2sym_en, rbytorden[1:0]}));
	defparam
		nl001l.width_data = 8,
		nl001l.width_sel = 3;
	oper_mux   nl001O
	( 
	.data({1'b0, wire_nl0i1l_dataout, wire_nl0l1O_dataout, 1'b0, wire_nli11i_dataout, wire_nli0ll_dataout, wire_nlil0i_dataout, 1'b0}),
	.o(wire_nl001O_o),
	.sel({rbytord_2sym_en, rbytorden[1:0]}));
	defparam
		nl001O.width_data = 8,
		nl001O.width_sel = 3;
	oper_mux   nl010l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[26], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[42], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[26], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[10], {2{wire_nl0l0Ol_byte_des_fifo_data_in[58]}}}),
	.o(wire_nl010l_o),
	.sel({wire_nl01Ol_dataout, wire_nl01Oi_dataout, wire_nl01lO_dataout, wire_nl01ll_dataout}));
	defparam
		nl010l.width_data = 16,
		nl010l.width_sel = 4;
	oper_mux   nl01OO
	( 
	.data({1'b0, wire_nl000i_dataout, wire_nl0i0l_dataout, 1'b0, wire_nl0l0O_dataout, wire_nli1il_dataout, wire_nlii1i_dataout, 1'b0}),
	.o(wire_nl01OO_o),
	.sel({rbytord_2sym_en, rbytorden[1:0]}));
	defparam
		nl01OO.width_data = 8,
		nl01OO.width_sel = 3;
	oper_mux   nl100i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[45], nlO01l, wire_nl0l0Ol_byte_des_fifo_data_in[45], wire_nl0l0Ol_byte_des_fifo_data_in[13], wire_nl0l0Ol_byte_des_fifo_data_in[45], nlO01l, wire_nl0l0Ol_byte_des_fifo_data_in[45], wire_nl0l0Ol_byte_des_fifo_data_in[29], wire_nl0l0Ol_byte_des_fifo_data_in[45], nlO01l, wire_nl0l0Ol_byte_des_fifo_data_in[45], wire_nl0l0Ol_byte_des_fifo_data_in[13], wire_nl0l0Ol_byte_des_fifo_data_in[45], nlO01l, {2{wire_nl0l0Ol_byte_des_fifo_data_in[45]}}}),
	.o(wire_nl100i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl100i.width_data = 16,
		nl100i.width_sel = 4;
	oper_mux   nl100l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[46], nlO01O, wire_nl0l0Ol_byte_des_fifo_data_in[46], wire_nl0l0Ol_byte_des_fifo_data_in[14], wire_nl0l0Ol_byte_des_fifo_data_in[46], nlO01O, wire_nl0l0Ol_byte_des_fifo_data_in[46], wire_nl0l0Ol_byte_des_fifo_data_in[30], wire_nl0l0Ol_byte_des_fifo_data_in[46], nlO01O, wire_nl0l0Ol_byte_des_fifo_data_in[46], wire_nl0l0Ol_byte_des_fifo_data_in[14], wire_nl0l0Ol_byte_des_fifo_data_in[46], nlO01O, {2{wire_nl0l0Ol_byte_des_fifo_data_in[46]}}}),
	.o(wire_nl100l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl100l.width_data = 16,
		nl100l.width_sel = 4;
	oper_mux   nl100O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[47], nlO00i, wire_nl0l0Ol_byte_des_fifo_data_in[47], wire_nl0l0Ol_byte_des_fifo_data_in[15], wire_nl0l0Ol_byte_des_fifo_data_in[47], nlO00i, wire_nl0l0Ol_byte_des_fifo_data_in[47], wire_nl0l0Ol_byte_des_fifo_data_in[31], wire_nl0l0Ol_byte_des_fifo_data_in[47], nlO00i, wire_nl0l0Ol_byte_des_fifo_data_in[47], wire_nl0l0Ol_byte_des_fifo_data_in[15], wire_nl0l0Ol_byte_des_fifo_data_in[47], nlO00i, {2{wire_nl0l0Ol_byte_des_fifo_data_in[47]}}}),
	.o(wire_nl100O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl100O.width_data = 16,
		nl100O.width_sel = 4;
	oper_mux   nl101i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[42], nlO1Ol, wire_nl0l0Ol_byte_des_fifo_data_in[42], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[42], nlO1Ol, wire_nl0l0Ol_byte_des_fifo_data_in[42], wire_nl0l0Ol_byte_des_fifo_data_in[26], wire_nl0l0Ol_byte_des_fifo_data_in[42], nlO1Ol, wire_nl0l0Ol_byte_des_fifo_data_in[42], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[42], nlO1Ol, {2{wire_nl0l0Ol_byte_des_fifo_data_in[42]}}}),
	.o(wire_nl101i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl101i.width_data = 16,
		nl101i.width_sel = 4;
	oper_mux   nl101l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[43], nlO1OO, wire_nl0l0Ol_byte_des_fifo_data_in[43], wire_nl0l0Ol_byte_des_fifo_data_in[11], wire_nl0l0Ol_byte_des_fifo_data_in[43], nlO1OO, wire_nl0l0Ol_byte_des_fifo_data_in[43], wire_nl0l0Ol_byte_des_fifo_data_in[27], wire_nl0l0Ol_byte_des_fifo_data_in[43], nlO1OO, wire_nl0l0Ol_byte_des_fifo_data_in[43], wire_nl0l0Ol_byte_des_fifo_data_in[11], wire_nl0l0Ol_byte_des_fifo_data_in[43], nlO1OO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[43]}}}),
	.o(wire_nl101l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl101l.width_data = 16,
		nl101l.width_sel = 4;
	oper_mux   nl101O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[44], nlO01i, wire_nl0l0Ol_byte_des_fifo_data_in[44], wire_nl0l0Ol_byte_des_fifo_data_in[12], wire_nl0l0Ol_byte_des_fifo_data_in[44], nlO01i, wire_nl0l0Ol_byte_des_fifo_data_in[44], wire_nl0l0Ol_byte_des_fifo_data_in[28], wire_nl0l0Ol_byte_des_fifo_data_in[44], nlO01i, wire_nl0l0Ol_byte_des_fifo_data_in[44], wire_nl0l0Ol_byte_des_fifo_data_in[12], wire_nl0l0Ol_byte_des_fifo_data_in[44], nlO01i, {2{wire_nl0l0Ol_byte_des_fifo_data_in[44]}}}),
	.o(wire_nl101O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl101O.width_data = 16,
		nl101O.width_sel = 4;
	oper_mux   nl10ii
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[48], wire_nl0l0Ol_byte_des_fifo_data_in[0], wire_nl0l0Ol_byte_des_fifo_data_in[48], wire_nl0l0Ol_byte_des_fifo_data_in[16], wire_nl0l0Ol_byte_des_fifo_data_in[48], wire_nl0l0Ol_byte_des_fifo_data_in[0], wire_nl0l0Ol_byte_des_fifo_data_in[48], wire_nl0l0Ol_byte_des_fifo_data_in[32], wire_nl0l0Ol_byte_des_fifo_data_in[48], wire_nl0l0Ol_byte_des_fifo_data_in[0], wire_nl0l0Ol_byte_des_fifo_data_in[48], wire_nl0l0Ol_byte_des_fifo_data_in[16], wire_nl0l0Ol_byte_des_fifo_data_in[48], wire_nl0l0Ol_byte_des_fifo_data_in[0], {2{wire_nl0l0Ol_byte_des_fifo_data_in[48]}}}),
	.o(wire_nl10ii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10ii.width_data = 16,
		nl10ii.width_sel = 4;
	oper_mux   nl10il
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[49], wire_nl0l0Ol_byte_des_fifo_data_in[1], wire_nl0l0Ol_byte_des_fifo_data_in[49], wire_nl0l0Ol_byte_des_fifo_data_in[17], wire_nl0l0Ol_byte_des_fifo_data_in[49], wire_nl0l0Ol_byte_des_fifo_data_in[1], wire_nl0l0Ol_byte_des_fifo_data_in[49], wire_nl0l0Ol_byte_des_fifo_data_in[33], wire_nl0l0Ol_byte_des_fifo_data_in[49], wire_nl0l0Ol_byte_des_fifo_data_in[1], wire_nl0l0Ol_byte_des_fifo_data_in[49], wire_nl0l0Ol_byte_des_fifo_data_in[17], wire_nl0l0Ol_byte_des_fifo_data_in[49], wire_nl0l0Ol_byte_des_fifo_data_in[1], {2{wire_nl0l0Ol_byte_des_fifo_data_in[49]}}}),
	.o(wire_nl10il_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10il.width_data = 16,
		nl10il.width_sel = 4;
	oper_mux   nl10iO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[50], wire_nl0l0Ol_byte_des_fifo_data_in[2], wire_nl0l0Ol_byte_des_fifo_data_in[50], wire_nl0l0Ol_byte_des_fifo_data_in[18], wire_nl0l0Ol_byte_des_fifo_data_in[50], wire_nl0l0Ol_byte_des_fifo_data_in[2], wire_nl0l0Ol_byte_des_fifo_data_in[50], wire_nl0l0Ol_byte_des_fifo_data_in[34], wire_nl0l0Ol_byte_des_fifo_data_in[50], wire_nl0l0Ol_byte_des_fifo_data_in[2], wire_nl0l0Ol_byte_des_fifo_data_in[50], wire_nl0l0Ol_byte_des_fifo_data_in[18], wire_nl0l0Ol_byte_des_fifo_data_in[50], wire_nl0l0Ol_byte_des_fifo_data_in[2], {2{wire_nl0l0Ol_byte_des_fifo_data_in[50]}}}),
	.o(wire_nl10iO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10iO.width_data = 16,
		nl10iO.width_sel = 4;
	oper_mux   nl10li
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[51], wire_nl0l0Ol_byte_des_fifo_data_in[3], wire_nl0l0Ol_byte_des_fifo_data_in[51], wire_nl0l0Ol_byte_des_fifo_data_in[19], wire_nl0l0Ol_byte_des_fifo_data_in[51], wire_nl0l0Ol_byte_des_fifo_data_in[3], wire_nl0l0Ol_byte_des_fifo_data_in[51], wire_nl0l0Ol_byte_des_fifo_data_in[35], wire_nl0l0Ol_byte_des_fifo_data_in[51], wire_nl0l0Ol_byte_des_fifo_data_in[3], wire_nl0l0Ol_byte_des_fifo_data_in[51], wire_nl0l0Ol_byte_des_fifo_data_in[19], wire_nl0l0Ol_byte_des_fifo_data_in[51], wire_nl0l0Ol_byte_des_fifo_data_in[3], {2{wire_nl0l0Ol_byte_des_fifo_data_in[51]}}}),
	.o(wire_nl10li_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10li.width_data = 16,
		nl10li.width_sel = 4;
	oper_mux   nl10ll
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[52], wire_nl0l0Ol_byte_des_fifo_data_in[4], wire_nl0l0Ol_byte_des_fifo_data_in[52], wire_nl0l0Ol_byte_des_fifo_data_in[20], wire_nl0l0Ol_byte_des_fifo_data_in[52], wire_nl0l0Ol_byte_des_fifo_data_in[4], wire_nl0l0Ol_byte_des_fifo_data_in[52], wire_nl0l0Ol_byte_des_fifo_data_in[36], wire_nl0l0Ol_byte_des_fifo_data_in[52], wire_nl0l0Ol_byte_des_fifo_data_in[4], wire_nl0l0Ol_byte_des_fifo_data_in[52], wire_nl0l0Ol_byte_des_fifo_data_in[20], wire_nl0l0Ol_byte_des_fifo_data_in[52], wire_nl0l0Ol_byte_des_fifo_data_in[4], {2{wire_nl0l0Ol_byte_des_fifo_data_in[52]}}}),
	.o(wire_nl10ll_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10ll.width_data = 16,
		nl10ll.width_sel = 4;
	oper_mux   nl10lO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[53], wire_nl0l0Ol_byte_des_fifo_data_in[5], wire_nl0l0Ol_byte_des_fifo_data_in[53], wire_nl0l0Ol_byte_des_fifo_data_in[21], wire_nl0l0Ol_byte_des_fifo_data_in[53], wire_nl0l0Ol_byte_des_fifo_data_in[5], wire_nl0l0Ol_byte_des_fifo_data_in[53], wire_nl0l0Ol_byte_des_fifo_data_in[37], wire_nl0l0Ol_byte_des_fifo_data_in[53], wire_nl0l0Ol_byte_des_fifo_data_in[5], wire_nl0l0Ol_byte_des_fifo_data_in[53], wire_nl0l0Ol_byte_des_fifo_data_in[21], wire_nl0l0Ol_byte_des_fifo_data_in[53], wire_nl0l0Ol_byte_des_fifo_data_in[5], {2{wire_nl0l0Ol_byte_des_fifo_data_in[53]}}}),
	.o(wire_nl10lO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10lO.width_data = 16,
		nl10lO.width_sel = 4;
	oper_mux   nl10Oi
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[54], wire_nl0l0Ol_byte_des_fifo_data_in[6], wire_nl0l0Ol_byte_des_fifo_data_in[54], wire_nl0l0Ol_byte_des_fifo_data_in[22], wire_nl0l0Ol_byte_des_fifo_data_in[54], wire_nl0l0Ol_byte_des_fifo_data_in[6], wire_nl0l0Ol_byte_des_fifo_data_in[54], wire_nl0l0Ol_byte_des_fifo_data_in[38], wire_nl0l0Ol_byte_des_fifo_data_in[54], wire_nl0l0Ol_byte_des_fifo_data_in[6], wire_nl0l0Ol_byte_des_fifo_data_in[54], wire_nl0l0Ol_byte_des_fifo_data_in[22], wire_nl0l0Ol_byte_des_fifo_data_in[54], wire_nl0l0Ol_byte_des_fifo_data_in[6], {2{wire_nl0l0Ol_byte_des_fifo_data_in[54]}}}),
	.o(wire_nl10Oi_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10Oi.width_data = 16,
		nl10Oi.width_sel = 4;
	oper_mux   nl10Ol
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[55], wire_nl0l0Ol_byte_des_fifo_data_in[7], wire_nl0l0Ol_byte_des_fifo_data_in[55], wire_nl0l0Ol_byte_des_fifo_data_in[23], wire_nl0l0Ol_byte_des_fifo_data_in[55], wire_nl0l0Ol_byte_des_fifo_data_in[7], wire_nl0l0Ol_byte_des_fifo_data_in[55], wire_nl0l0Ol_byte_des_fifo_data_in[39], wire_nl0l0Ol_byte_des_fifo_data_in[55], wire_nl0l0Ol_byte_des_fifo_data_in[7], wire_nl0l0Ol_byte_des_fifo_data_in[55], wire_nl0l0Ol_byte_des_fifo_data_in[23], wire_nl0l0Ol_byte_des_fifo_data_in[55], wire_nl0l0Ol_byte_des_fifo_data_in[7], {2{wire_nl0l0Ol_byte_des_fifo_data_in[55]}}}),
	.o(wire_nl10Ol_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10Ol.width_data = 16,
		nl10Ol.width_sel = 4;
	oper_mux   nl10OO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[56], wire_nl0l0Ol_byte_des_fifo_data_in[8], wire_nl0l0Ol_byte_des_fifo_data_in[56], wire_nl0l0Ol_byte_des_fifo_data_in[24], wire_nl0l0Ol_byte_des_fifo_data_in[56], wire_nl0l0Ol_byte_des_fifo_data_in[8], wire_nl0l0Ol_byte_des_fifo_data_in[56], wire_nl0l0Ol_byte_des_fifo_data_in[40], wire_nl0l0Ol_byte_des_fifo_data_in[56], wire_nl0l0Ol_byte_des_fifo_data_in[8], wire_nl0l0Ol_byte_des_fifo_data_in[56], wire_nl0l0Ol_byte_des_fifo_data_in[24], wire_nl0l0Ol_byte_des_fifo_data_in[56], wire_nl0l0Ol_byte_des_fifo_data_in[8], {2{wire_nl0l0Ol_byte_des_fifo_data_in[56]}}}),
	.o(wire_nl10OO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl10OO.width_data = 16,
		nl10OO.width_sel = 4;
	oper_mux   nl110i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[30], nlO11l, wire_nl0l0Ol_byte_des_fifo_data_in[30], nlO01O, wire_nl0l0Ol_byte_des_fifo_data_in[30], nlO11l, wire_nl0l0Ol_byte_des_fifo_data_in[30], wire_nl0l0Ol_byte_des_fifo_data_in[14], wire_nl0l0Ol_byte_des_fifo_data_in[30], nlO11l, wire_nl0l0Ol_byte_des_fifo_data_in[30], nlO01O, wire_nl0l0Ol_byte_des_fifo_data_in[30], nlO11l, {2{wire_nl0l0Ol_byte_des_fifo_data_in[30]}}}),
	.o(wire_nl110i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl110i.width_data = 16,
		nl110i.width_sel = 4;
	oper_mux   nl110l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[31], nlO11O, wire_nl0l0Ol_byte_des_fifo_data_in[31], nlO00i, wire_nl0l0Ol_byte_des_fifo_data_in[31], nlO11O, wire_nl0l0Ol_byte_des_fifo_data_in[31], wire_nl0l0Ol_byte_des_fifo_data_in[15], wire_nl0l0Ol_byte_des_fifo_data_in[31], nlO11O, wire_nl0l0Ol_byte_des_fifo_data_in[31], nlO00i, wire_nl0l0Ol_byte_des_fifo_data_in[31], nlO11O, {2{wire_nl0l0Ol_byte_des_fifo_data_in[31]}}}),
	.o(wire_nl110l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl110l.width_data = 16,
		nl110l.width_sel = 4;
	oper_mux   nl110O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[32], nlO10i, wire_nl0l0Ol_byte_des_fifo_data_in[32], wire_nl0l0Ol_byte_des_fifo_data_in[0], wire_nl0l0Ol_byte_des_fifo_data_in[32], nlO10i, wire_nl0l0Ol_byte_des_fifo_data_in[32], wire_nl0l0Ol_byte_des_fifo_data_in[16], wire_nl0l0Ol_byte_des_fifo_data_in[32], nlO10i, wire_nl0l0Ol_byte_des_fifo_data_in[32], wire_nl0l0Ol_byte_des_fifo_data_in[0], wire_nl0l0Ol_byte_des_fifo_data_in[32], nlO10i, {2{wire_nl0l0Ol_byte_des_fifo_data_in[32]}}}),
	.o(wire_nl110O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl110O.width_data = 16,
		nl110O.width_sel = 4;
	oper_mux   nl111i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[27], nllOOl, wire_nl0l0Ol_byte_des_fifo_data_in[27], nlO1OO, wire_nl0l0Ol_byte_des_fifo_data_in[27], nllOOl, wire_nl0l0Ol_byte_des_fifo_data_in[27], wire_nl0l0Ol_byte_des_fifo_data_in[11], wire_nl0l0Ol_byte_des_fifo_data_in[27], nllOOl, wire_nl0l0Ol_byte_des_fifo_data_in[27], nlO1OO, wire_nl0l0Ol_byte_des_fifo_data_in[27], nllOOl, {2{wire_nl0l0Ol_byte_des_fifo_data_in[27]}}}),
	.o(wire_nl111i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl111i.width_data = 16,
		nl111i.width_sel = 4;
	oper_mux   nl111l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[28], nllOOO, wire_nl0l0Ol_byte_des_fifo_data_in[28], nlO01i, wire_nl0l0Ol_byte_des_fifo_data_in[28], nllOOO, wire_nl0l0Ol_byte_des_fifo_data_in[28], wire_nl0l0Ol_byte_des_fifo_data_in[12], wire_nl0l0Ol_byte_des_fifo_data_in[28], nllOOO, wire_nl0l0Ol_byte_des_fifo_data_in[28], nlO01i, wire_nl0l0Ol_byte_des_fifo_data_in[28], nllOOO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[28]}}}),
	.o(wire_nl111l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl111l.width_data = 16,
		nl111l.width_sel = 4;
	oper_mux   nl111O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[29], nlO11i, wire_nl0l0Ol_byte_des_fifo_data_in[29], nlO01l, wire_nl0l0Ol_byte_des_fifo_data_in[29], nlO11i, wire_nl0l0Ol_byte_des_fifo_data_in[29], wire_nl0l0Ol_byte_des_fifo_data_in[13], wire_nl0l0Ol_byte_des_fifo_data_in[29], nlO11i, wire_nl0l0Ol_byte_des_fifo_data_in[29], nlO01l, wire_nl0l0Ol_byte_des_fifo_data_in[29], nlO11i, {2{wire_nl0l0Ol_byte_des_fifo_data_in[29]}}}),
	.o(wire_nl111O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl111O.width_data = 16,
		nl111O.width_sel = 4;
	oper_mux   nl11ii
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[33], nlO10l, wire_nl0l0Ol_byte_des_fifo_data_in[33], wire_nl0l0Ol_byte_des_fifo_data_in[1], wire_nl0l0Ol_byte_des_fifo_data_in[33], nlO10l, wire_nl0l0Ol_byte_des_fifo_data_in[33], wire_nl0l0Ol_byte_des_fifo_data_in[17], wire_nl0l0Ol_byte_des_fifo_data_in[33], nlO10l, wire_nl0l0Ol_byte_des_fifo_data_in[33], wire_nl0l0Ol_byte_des_fifo_data_in[1], wire_nl0l0Ol_byte_des_fifo_data_in[33], nlO10l, {2{wire_nl0l0Ol_byte_des_fifo_data_in[33]}}}),
	.o(wire_nl11ii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11ii.width_data = 16,
		nl11ii.width_sel = 4;
	oper_mux   nl11il
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[34], nlO10O, wire_nl0l0Ol_byte_des_fifo_data_in[34], wire_nl0l0Ol_byte_des_fifo_data_in[2], wire_nl0l0Ol_byte_des_fifo_data_in[34], nlO10O, wire_nl0l0Ol_byte_des_fifo_data_in[34], wire_nl0l0Ol_byte_des_fifo_data_in[18], wire_nl0l0Ol_byte_des_fifo_data_in[34], nlO10O, wire_nl0l0Ol_byte_des_fifo_data_in[34], wire_nl0l0Ol_byte_des_fifo_data_in[2], wire_nl0l0Ol_byte_des_fifo_data_in[34], nlO10O, {2{wire_nl0l0Ol_byte_des_fifo_data_in[34]}}}),
	.o(wire_nl11il_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11il.width_data = 16,
		nl11il.width_sel = 4;
	oper_mux   nl11iO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[35], nlO1ii, wire_nl0l0Ol_byte_des_fifo_data_in[35], wire_nl0l0Ol_byte_des_fifo_data_in[3], wire_nl0l0Ol_byte_des_fifo_data_in[35], nlO1ii, wire_nl0l0Ol_byte_des_fifo_data_in[35], wire_nl0l0Ol_byte_des_fifo_data_in[19], wire_nl0l0Ol_byte_des_fifo_data_in[35], nlO1ii, wire_nl0l0Ol_byte_des_fifo_data_in[35], wire_nl0l0Ol_byte_des_fifo_data_in[3], wire_nl0l0Ol_byte_des_fifo_data_in[35], nlO1ii, {2{wire_nl0l0Ol_byte_des_fifo_data_in[35]}}}),
	.o(wire_nl11iO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11iO.width_data = 16,
		nl11iO.width_sel = 4;
	oper_mux   nl11li
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[36], nlO1il, wire_nl0l0Ol_byte_des_fifo_data_in[36], wire_nl0l0Ol_byte_des_fifo_data_in[4], wire_nl0l0Ol_byte_des_fifo_data_in[36], nlO1il, wire_nl0l0Ol_byte_des_fifo_data_in[36], wire_nl0l0Ol_byte_des_fifo_data_in[20], wire_nl0l0Ol_byte_des_fifo_data_in[36], nlO1il, wire_nl0l0Ol_byte_des_fifo_data_in[36], wire_nl0l0Ol_byte_des_fifo_data_in[4], wire_nl0l0Ol_byte_des_fifo_data_in[36], nlO1il, {2{wire_nl0l0Ol_byte_des_fifo_data_in[36]}}}),
	.o(wire_nl11li_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11li.width_data = 16,
		nl11li.width_sel = 4;
	oper_mux   nl11ll
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[37], nlO1iO, wire_nl0l0Ol_byte_des_fifo_data_in[37], wire_nl0l0Ol_byte_des_fifo_data_in[5], wire_nl0l0Ol_byte_des_fifo_data_in[37], nlO1iO, wire_nl0l0Ol_byte_des_fifo_data_in[37], wire_nl0l0Ol_byte_des_fifo_data_in[21], wire_nl0l0Ol_byte_des_fifo_data_in[37], nlO1iO, wire_nl0l0Ol_byte_des_fifo_data_in[37], wire_nl0l0Ol_byte_des_fifo_data_in[5], wire_nl0l0Ol_byte_des_fifo_data_in[37], nlO1iO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[37]}}}),
	.o(wire_nl11ll_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11ll.width_data = 16,
		nl11ll.width_sel = 4;
	oper_mux   nl11lO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[38], nlO1li, wire_nl0l0Ol_byte_des_fifo_data_in[38], wire_nl0l0Ol_byte_des_fifo_data_in[6], wire_nl0l0Ol_byte_des_fifo_data_in[38], nlO1li, wire_nl0l0Ol_byte_des_fifo_data_in[38], wire_nl0l0Ol_byte_des_fifo_data_in[22], wire_nl0l0Ol_byte_des_fifo_data_in[38], nlO1li, wire_nl0l0Ol_byte_des_fifo_data_in[38], wire_nl0l0Ol_byte_des_fifo_data_in[6], wire_nl0l0Ol_byte_des_fifo_data_in[38], nlO1li, {2{wire_nl0l0Ol_byte_des_fifo_data_in[38]}}}),
	.o(wire_nl11lO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11lO.width_data = 16,
		nl11lO.width_sel = 4;
	oper_mux   nl11Oi
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[39], nlO1ll, wire_nl0l0Ol_byte_des_fifo_data_in[39], wire_nl0l0Ol_byte_des_fifo_data_in[7], wire_nl0l0Ol_byte_des_fifo_data_in[39], nlO1ll, wire_nl0l0Ol_byte_des_fifo_data_in[39], wire_nl0l0Ol_byte_des_fifo_data_in[23], wire_nl0l0Ol_byte_des_fifo_data_in[39], nlO1ll, wire_nl0l0Ol_byte_des_fifo_data_in[39], wire_nl0l0Ol_byte_des_fifo_data_in[7], wire_nl0l0Ol_byte_des_fifo_data_in[39], nlO1ll, {2{wire_nl0l0Ol_byte_des_fifo_data_in[39]}}}),
	.o(wire_nl11Oi_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11Oi.width_data = 16,
		nl11Oi.width_sel = 4;
	oper_mux   nl11Ol
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[40], nlO1lO, wire_nl0l0Ol_byte_des_fifo_data_in[40], wire_nl0l0Ol_byte_des_fifo_data_in[8], wire_nl0l0Ol_byte_des_fifo_data_in[40], nlO1lO, wire_nl0l0Ol_byte_des_fifo_data_in[40], wire_nl0l0Ol_byte_des_fifo_data_in[24], wire_nl0l0Ol_byte_des_fifo_data_in[40], nlO1lO, wire_nl0l0Ol_byte_des_fifo_data_in[40], wire_nl0l0Ol_byte_des_fifo_data_in[8], wire_nl0l0Ol_byte_des_fifo_data_in[40], nlO1lO, {2{wire_nl0l0Ol_byte_des_fifo_data_in[40]}}}),
	.o(wire_nl11Ol_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11Ol.width_data = 16,
		nl11Ol.width_sel = 4;
	oper_mux   nl11OO
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[41], nlO1Oi, wire_nl0l0Ol_byte_des_fifo_data_in[41], wire_nl0l0Ol_byte_des_fifo_data_in[9], wire_nl0l0Ol_byte_des_fifo_data_in[41], nlO1Oi, wire_nl0l0Ol_byte_des_fifo_data_in[41], wire_nl0l0Ol_byte_des_fifo_data_in[25], wire_nl0l0Ol_byte_des_fifo_data_in[41], nlO1Oi, wire_nl0l0Ol_byte_des_fifo_data_in[41], wire_nl0l0Ol_byte_des_fifo_data_in[9], wire_nl0l0Ol_byte_des_fifo_data_in[41], nlO1Oi, {2{wire_nl0l0Ol_byte_des_fifo_data_in[41]}}}),
	.o(wire_nl11OO_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl11OO.width_data = 16,
		nl11OO.width_sel = 4;
	oper_mux   nl1i0i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[60], wire_nl0l0Ol_byte_des_fifo_data_in[12], wire_nl0l0Ol_byte_des_fifo_data_in[60], wire_nl0l0Ol_byte_des_fifo_data_in[28], wire_nl0l0Ol_byte_des_fifo_data_in[60], wire_nl0l0Ol_byte_des_fifo_data_in[12], wire_nl0l0Ol_byte_des_fifo_data_in[60], wire_nl0l0Ol_byte_des_fifo_data_in[44], wire_nl0l0Ol_byte_des_fifo_data_in[60], wire_nl0l0Ol_byte_des_fifo_data_in[12], wire_nl0l0Ol_byte_des_fifo_data_in[60], wire_nl0l0Ol_byte_des_fifo_data_in[28], wire_nl0l0Ol_byte_des_fifo_data_in[60], wire_nl0l0Ol_byte_des_fifo_data_in[12], {2{wire_nl0l0Ol_byte_des_fifo_data_in[60]}}}),
	.o(wire_nl1i0i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl1i0i.width_data = 16,
		nl1i0i.width_sel = 4;
	oper_mux   nl1i0l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[61], wire_nl0l0Ol_byte_des_fifo_data_in[13], wire_nl0l0Ol_byte_des_fifo_data_in[61], wire_nl0l0Ol_byte_des_fifo_data_in[29], wire_nl0l0Ol_byte_des_fifo_data_in[61], wire_nl0l0Ol_byte_des_fifo_data_in[13], wire_nl0l0Ol_byte_des_fifo_data_in[61], wire_nl0l0Ol_byte_des_fifo_data_in[45], wire_nl0l0Ol_byte_des_fifo_data_in[61], wire_nl0l0Ol_byte_des_fifo_data_in[13], wire_nl0l0Ol_byte_des_fifo_data_in[61], wire_nl0l0Ol_byte_des_fifo_data_in[29], wire_nl0l0Ol_byte_des_fifo_data_in[61], wire_nl0l0Ol_byte_des_fifo_data_in[13], {2{wire_nl0l0Ol_byte_des_fifo_data_in[61]}}}),
	.o(wire_nl1i0l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl1i0l.width_data = 16,
		nl1i0l.width_sel = 4;
	oper_mux   nl1i0O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[62], wire_nl0l0Ol_byte_des_fifo_data_in[14], wire_nl0l0Ol_byte_des_fifo_data_in[62], wire_nl0l0Ol_byte_des_fifo_data_in[30], wire_nl0l0Ol_byte_des_fifo_data_in[62], wire_nl0l0Ol_byte_des_fifo_data_in[14], wire_nl0l0Ol_byte_des_fifo_data_in[62], wire_nl0l0Ol_byte_des_fifo_data_in[46], wire_nl0l0Ol_byte_des_fifo_data_in[62], wire_nl0l0Ol_byte_des_fifo_data_in[14], wire_nl0l0Ol_byte_des_fifo_data_in[62], wire_nl0l0Ol_byte_des_fifo_data_in[30], wire_nl0l0Ol_byte_des_fifo_data_in[62], wire_nl0l0Ol_byte_des_fifo_data_in[14], {2{wire_nl0l0Ol_byte_des_fifo_data_in[62]}}}),
	.o(wire_nl1i0O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl1i0O.width_data = 16,
		nl1i0O.width_sel = 4;
	oper_mux   nl1i1i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[57], wire_nl0l0Ol_byte_des_fifo_data_in[9], wire_nl0l0Ol_byte_des_fifo_data_in[57], wire_nl0l0Ol_byte_des_fifo_data_in[25], wire_nl0l0Ol_byte_des_fifo_data_in[57], wire_nl0l0Ol_byte_des_fifo_data_in[9], wire_nl0l0Ol_byte_des_fifo_data_in[57], wire_nl0l0Ol_byte_des_fifo_data_in[41], wire_nl0l0Ol_byte_des_fifo_data_in[57], wire_nl0l0Ol_byte_des_fifo_data_in[9], wire_nl0l0Ol_byte_des_fifo_data_in[57], wire_nl0l0Ol_byte_des_fifo_data_in[25], wire_nl0l0Ol_byte_des_fifo_data_in[57], wire_nl0l0Ol_byte_des_fifo_data_in[9], {2{wire_nl0l0Ol_byte_des_fifo_data_in[57]}}}),
	.o(wire_nl1i1i_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl1i1i.width_data = 16,
		nl1i1i.width_sel = 4;
	oper_mux   nl1i1l
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[26], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[42], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[26], wire_nl0l0Ol_byte_des_fifo_data_in[58], wire_nl0l0Ol_byte_des_fifo_data_in[10], {2{wire_nl0l0Ol_byte_des_fifo_data_in[58]}}}),
	.o(wire_nl1i1l_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl1i1l.width_data = 16,
		nl1i1l.width_sel = 4;
	oper_mux   nl1i1O
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[59], wire_nl0l0Ol_byte_des_fifo_data_in[11], wire_nl0l0Ol_byte_des_fifo_data_in[59], wire_nl0l0Ol_byte_des_fifo_data_in[27], wire_nl0l0Ol_byte_des_fifo_data_in[59], wire_nl0l0Ol_byte_des_fifo_data_in[11], wire_nl0l0Ol_byte_des_fifo_data_in[59], wire_nl0l0Ol_byte_des_fifo_data_in[43], wire_nl0l0Ol_byte_des_fifo_data_in[59], wire_nl0l0Ol_byte_des_fifo_data_in[11], wire_nl0l0Ol_byte_des_fifo_data_in[59], wire_nl0l0Ol_byte_des_fifo_data_in[27], wire_nl0l0Ol_byte_des_fifo_data_in[59], wire_nl0l0Ol_byte_des_fifo_data_in[11], {2{wire_nl0l0Ol_byte_des_fifo_data_in[59]}}}),
	.o(wire_nl1i1O_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl1i1O.width_data = 16,
		nl1i1O.width_sel = 4;
	oper_mux   nl1iii
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[63], wire_nl0l0Ol_byte_des_fifo_data_in[15], wire_nl0l0Ol_byte_des_fifo_data_in[63], wire_nl0l0Ol_byte_des_fifo_data_in[31], wire_nl0l0Ol_byte_des_fifo_data_in[63], wire_nl0l0Ol_byte_des_fifo_data_in[15], wire_nl0l0Ol_byte_des_fifo_data_in[63], wire_nl0l0Ol_byte_des_fifo_data_in[47], wire_nl0l0Ol_byte_des_fifo_data_in[63], wire_nl0l0Ol_byte_des_fifo_data_in[15], wire_nl0l0Ol_byte_des_fifo_data_in[63], wire_nl0l0Ol_byte_des_fifo_data_in[31], wire_nl0l0Ol_byte_des_fifo_data_in[63], wire_nl0l0Ol_byte_des_fifo_data_in[15], {2{wire_nl0l0Ol_byte_des_fifo_data_in[63]}}}),
	.o(wire_nl1iii_o),
	.sel({nlilll, nlilli, nliliO, n11OOO}));
	defparam
		nl1iii.width_data = 16,
		nl1iii.width_sel = 4;
	oper_mux   nl1O0i
	( 
	.data({wire_nl0l0Ol_byte_des_fifo_data_in[42], wire_nl0l0Ol_byte_des_fifo_data_in[10], wire_nl0l0Ol_byte_des_fifo_data_in[42], wire_nl0l0Ol_byte_des_fifo_data_in[26], wire_nl0l0Ol_byte_des_fifo_data_in[42], wire_nl0l0Ol_byte_des_fifo_data_in[10], {2{wire_nl0l0Ol_byte_des_fifo_data_in[42]}}}),
	.o(wire_nl1O0i_o),
	.sel({wire_nl01Oi_dataout, wire_nl01lO_dataout, wire_nl01ll_dataout}));
	defparam
		nl1O0i.width_data = 8,
		nl1O0i.width_sel = 3;
	oper_selector   niOil
	( 
	.data({wire_nl10l_dataout, (((((nl0i0Oi | nl0i0lO) & rsync_comp_porn) & (nl0i0ll | nl0i0li)) | nl0i0iO) & n100l), nl0iiii, nl0iiOO, ((rsync_comp_porn & nl0ii0i) | nl0ii0l), (((((nl0ii1O | nl0ii1l) & rsync_comp_porn) & (nl0ii1i | nl0i0OO)) | nl0i0Ol) & n100O), nl0iill, nl0il1O, (nl0il1i | nl0il1l), (nl0ii0l | nl0ii0i)}),
	.o(wire_niOil_o),
	.sel({nl0ii0O, (wire_nl10i_o[61] | wire_nl10i_o[60]), (wire_nl10i_o[57] | wire_nl10i_o[56]), (wire_nl10i_o[53] | wire_nl10i_o[52]), (wire_nl10i_o[49] | wire_nl10i_o[48]), (wire_nl10i_o[43] | wire_nl10i_o[42]), (wire_nl10i_o[39] | wire_nl10i_o[38]), (wire_nl10i_o[35] | wire_nl10i_o[34]), (wire_nl10i_o[21] | wire_nl10i_o[20]), (wire_nl10i_o[17] | wire_nl10i_o[16])}));
	defparam
		niOil.width_data = 10,
		niOil.width_sel = 10;
	oper_selector   nliil
	( 
	.data({wire_nll0l_dataout, (((rsync_comp_porn & nl0ilii) | nl0il0O) & n101i), (((rsync_comp_porn & nl0iliO) | nl0ilil) & n10ii), ((((rsync_comp_porn & nl0ilOO) & (nl0ilOi38 ^ nl0ilOi37)) | nl0illO) | (~ (nl0illi40 ^ nl0illi39))), (((rsync_comp_porn & nl0l11l) | nl0l11O) | (~ (nl0iO1i36 ^ nl0iO1i35))), ((((rsync_comp_porn & nl0iO0O) & (nl0iO0i34 ^ nl0iO0i33)) | nl0iO1O) & n101O), ((nl0iOii32 ^ nl0iOii31) & ((((rsync_comp_porn & nl0iOli) & (nl0iOil30 ^ nl0iOil29)) | nl0l00O) & n10il)), (((rsync_comp_porn & nl0iOOl) & (nl0iOlO28 ^ nl0iOlO27)) | nl0iOll), nl0iOOO, ((nl0l11i26 ^ nl0l11i25) & (nl0l11O | nl0l11l))}),
	.o(wire_nliil_o),
	.sel({nl0l1OO, ((wire_nll0i_o[61] | wire_nll0i_o[60]) | (~ (nl0l10i24 ^ nl0l10i23))), ((wire_nll0i_o[57] | wire_nll0i_o[56]) | (~ (nl0l10O22 ^ nl0l10O21))), ((nl0l1il20 ^ nl0l1il19) & (wire_nll0i_o[53] | wire_nll0i_o[52])), ((wire_nll0i_o[49] | wire_nll0i_o[48]) | (~ (nl0l1iO18 ^ nl0l1iO17))), (wire_nll0i_o[43] | wire_nll0i_o[42]), ((wire_nll0i_o[39] | wire_nll0i_o[38]) | (~ (nl0l1ll16 ^ nl0l1ll15))), (wire_nll0i_o[35] | wire_nll0i_o[34]), ((wire_nll0i_o[21] | wire_nll0i_o[20]) | (~ (nl0l1Oi14 ^ nl0l1Oi13))), (wire_nll0i_o[17] | wire_nll0i_o[16])}));
	defparam
		nliil.width_data = 10,
		nliil.width_sel = 10;
	arriagx_hssi_ram8x65_syn   nl0l0OO
	( 
	.clk(rx_wr_clk),
	.data_in({wire_n101ii_dataout, wire_n10OlO_o, wire_n10Oll_o, wire_n10Oli_o, wire_n10OiO_o, wire_n10Oil_o, wire_n10Oii_o, wire_n10O0O_o, wire_n10O0l_o, wire_n10O0i_o, wire_n10O1O_o, wire_n10O1l_o, wire_n10O1i_o, wire_n10lOO_o, wire_n10lOl_o, wire_n10lOi_o, wire_n10llO_o, wire_n10lll_o, wire_n10lli_o, wire_n10liO_o, wire_n10lil_o, wire_n10lii_o, wire_n10l0O_o, wire_n10l0l_o, wire_n10l0i_o, wire_n10l1O_o, wire_n10l1l_o, wire_n10l1i_o, wire_n10iOO_o, wire_n10iOl_o, wire_n10iOi_o, wire_n10ilO_o, wire_n10ill_o, wire_n10ili_o, wire_n10iiO_o, wire_n10iil_o, wire_n10iii_o, wire_n10i0O_o, wire_n10i0l_o, wire_n10i0i_o, wire_n10i1O_o, wire_n10i1l_o, wire_n10i1i_o, wire_n100OO_o, wire_n100Ol_o, wire_n100Oi_o, wire_n100lO_o, wire_n100ll_o, wire_n100li_o, wire_n100iO_o, wire_n100il_o, wire_n100ii_o, wire_n1000O_o, wire_n1000l_o, wire_n1000i_o, wire_n1001O_o, wire_n1001l_o, wire_n1001i_o, wire_n101OO_o, wire_n101Ol_o, wire_n101Oi_o, wire_n101lO_o, wire_n101ll_o, wire_n101li_o, wire_n101iO_o}),
	.data_out(wire_nl0l0OO_data_out),
	.fifo_re({nli11iO, nli11il, nli11ii, nli110O, nli110l, nli110i, nli111O, nli111l}),
	.fifo_wr({nli1O1i, nli1lOO, nli1lOl, nli1lOi, nli1llO, nli1lll, nli1lli, nli10Oi}),
	.rst_l((~ wire_n111l_dataout)));
	defparam
		nl0l0OO.ram_width = 65,
		nl0l0OO.read_access_time = 0,
		nl0l0OO.write_access_time = 0;
	arriagx_hssi_rx_byte_des   nl0l0Ol
	( 
	.bo_3g_en(n11ii),
	.bo_en(wire_n1O0O_dataout),
	.byte_des_bo_3g_start(wire_nl0l0Ol_byte_des_bo_3g_start),
	.byte_des_fifo_data_in(wire_nl0l0Ol_byte_des_fifo_data_in),
	.clk_2(clk_2),
	.disp_err_d({wire_n00li_dataout, wire_n00iO_dataout}),
	.disp_val_d({wire_n00il_dataout, wire_n00ii_dataout}),
	.ovr_undflow_d({wire_n000O_dataout, wire_n000l_dataout, wire_n000i_dataout, wire_n001O_dataout}),
	.pattern_det_d({wire_n1OlO_dataout, wire_n1Oll_dataout}),
	.rdwidth(rdwidth),
	.rx_data_int({wire_n001l_dataout, wire_n001i_dataout, wire_n01OO_dataout, wire_n01Ol_dataout, wire_n01Oi_dataout, wire_n01lO_dataout, wire_n01ll_dataout, wire_n01li_dataout, wire_n01iO_dataout, wire_n01il_dataout, wire_n01ii_dataout, wire_n010O_dataout, wire_n010l_dataout, wire_n010i_dataout, wire_n011O_dataout, wire_n011l_dataout, wire_n011i_dataout, wire_n1OOO_dataout, wire_n1OOl_dataout, wire_n1OOi_dataout}),
	.rx_we_out(n11OOl),
	.rx_wr_clk(rx_wr_clk),
	.soft_reset(soft_reset),
	.soft_reset_wclk1(wire_n111l_dataout),
	.sync_resync_d({wire_n00lO_dataout, wire_n00ll_dataout}));
	assign
		bytord_valid_out = wire_nlOlO_dataout,
		nl000ii = ((((((wire_nl0lOii_o[64] | wire_nl0lOii_o[32]) | wire_nl0lOii_o[16]) | wire_nl0lOii_o[8]) | wire_nl0lOii_o[4]) | wire_nl0lOii_o[2]) | wire_nl0lOii_o[128]),
		nl000li = ((((((((~ (nli101l ^ nl0OOil)) & (~ (nli101i ^ nl0OO1i))) & (~ (nli11Ol ^ nl0OO1l))) & (~ (nli11OO ^ nl0OO1O))) & (~ (nli11ll ^ nl0OO0i))) & (~ (nli11li ^ nl0OO0l))) & (~ (nli11lO ^ nl0OO0O))) & (~ (nli11Oi ^ nl0OOii))),
		nl000ll = ((((((((~ (nli101l ^ nl0OO1i)) & (~ (nli101i ^ nl0OO1l))) & (~ (nli11Ol ^ nl0OO1O))) & (~ (nli11OO ^ nl0OO0i))) & (~ (nli11ll ^ nl0OO0l))) & (~ (nli11li ^ nl0OO0O))) & (~ (nli11lO ^ nl0OOii))) & (~ (nli11Oi ^ nl0OOil))),
		nl000lO = ((((((((~ (nli11Oi ^ nl0OO1i)) & (~ (nli101l ^ nl0OO1l))) & (~ (nli101i ^ nl0OO1O))) & (~ (nli11Ol ^ nl0OO0i))) & (~ (nli11OO ^ nl0OO0l))) & (~ (nli11ll ^ nl0OO0O))) & (~ (nli11li ^ nl0OOii))) & (~ (nli11lO ^ nl0OOil))),
		nl000Oi = (rrxfifo_lowlatency_en & nl0OlOi),
		nl00i0i = (nliliO & (~ n11OOO)),
		nl00i0l = (wire_nl01lO_dataout & (~ wire_nl01ll_dataout)),
		nl00i0O = ((wire_nilill_o[6] | wire_nilill_o[4]) | wire_nilill_o[2]),
		nl00i1i = (((~ nlilli) | nliliO) | n11OOO),
		nl00i1l = (((~ wire_nl01Oi_dataout) | wire_nl01lO_dataout) | wire_nl01ll_dataout),
		nl00i1O = ((~ nliliO) & (~ n11OOO)),
		nl00iii = ((((((wire_nillOl_o[14] | wire_nillOl_o[12]) | wire_nillOl_o[10]) | wire_nillOl_o[8]) | wire_nillOl_o[6]) | wire_nillOl_o[4]) | wire_nillOl_o[2]),
		nl00iil = (((((((((~ (nlll1l ^ rbytordpat[9])) & (~ (nlll1O ^ rsync_comp_pat[32]))) & (~ (nlll0i ^ rsync_comp_pat[33]))) & (~ (nlll0l ^ rsync_comp_pat[34]))) & (~ (nlll0O ^ rsync_comp_pat[35]))) & (~ (nlllii ^ rsync_comp_pat[36]))) & (~ (nlllil ^ rsync_comp_pat[37]))) & (~ (nllliO ^ rsync_comp_pat[38]))) & (~ (nlllli ^ rsync_comp_pat[39]))),
		nl00iiO = (((((((((~ (nlli1i ^ rbytordpat[0])) & (~ (nlli1l ^ rbytordpat[1]))) & (~ (nlli1O ^ rbytordpat[2]))) & (~ (nlli0i ^ rbytordpat[3]))) & (~ (nlli0l ^ rbytordpat[4]))) & (~ (nlli0O ^ rbytordpat[5]))) & (~ (nlliii ^ rbytordpat[6]))) & (~ (nlliil ^ rbytordpat[7]))) & (~ (nlliiO ^ rbytordpat[8]))),
		nl00ili = (((((((((~ (nllO1O ^ rbytordpat[9])) & (~ (nllO0i ^ rsync_comp_pat[32]))) & (~ (nllO0l ^ rsync_comp_pat[33]))) & (~ (nllO0O ^ rsync_comp_pat[34]))) & (~ (nllOii ^ rsync_comp_pat[35]))) & (~ (nllOil ^ rsync_comp_pat[36]))) & (~ (nllOiO ^ rsync_comp_pat[37]))) & (~ (nllOli ^ rsync_comp_pat[38]))) & (~ (nllOll ^ rsync_comp_pat[39]))),
		nl00ill = (((((((((~ (nlll1l ^ rbytordpat[0])) & (~ (nlll1O ^ rbytordpat[1]))) & (~ (nlll0i ^ rbytordpat[2]))) & (~ (nlll0l ^ rbytordpat[3]))) & (~ (nlll0O ^ rbytordpat[4]))) & (~ (nlllii ^ rbytordpat[5]))) & (~ (nlllil ^ rbytordpat[6]))) & (~ (nllliO ^ rbytordpat[7]))) & (~ (nlllli ^ rbytordpat[8]))),
		nl00ilO = (((((((((~ (nlO10i ^ rbytordpat[9])) & (~ (nlO10l ^ rsync_comp_pat[32]))) & (~ (nlO10O ^ rsync_comp_pat[33]))) & (~ (nlO1ii ^ rsync_comp_pat[34]))) & (~ (nlO1il ^ rsync_comp_pat[35]))) & (~ (nlO1iO ^ rsync_comp_pat[36]))) & (~ (nlO1li ^ rsync_comp_pat[37]))) & (~ (nlO1ll ^ rsync_comp_pat[38]))) & (~ (nlO1lO ^ rsync_comp_pat[39]))),
		nl00iOi = (((((((((~ (rbytordpat[9] ^ wire_nl0l0Ol_byte_des_fifo_data_in[0])) & (~ (rsync_comp_pat[32] ^ wire_nl0l0Ol_byte_des_fifo_data_in[1]))) & (~ (rsync_comp_pat[33] ^ wire_nl0l0Ol_byte_des_fifo_data_in[2]))) & (~ (rsync_comp_pat[34] ^ wire_nl0l0Ol_byte_des_fifo_data_in[3]))) & (~ (rsync_comp_pat[35] ^ wire_nl0l0Ol_byte_des_fifo_data_in[4]))) & (~ (rsync_comp_pat[36] ^ wire_nl0l0Ol_byte_des_fifo_data_in[5]))) & (~ (rsync_comp_pat[37] ^ wire_nl0l0Ol_byte_des_fifo_data_in[6]))) & (~ (rsync_comp_pat[38] ^ wire_nl0l0Ol_byte_des_fifo_data_in[7]))) & (~ (rsync_comp_pat[39] ^ wire_nl0l0Ol_byte_des_fifo_data_in[8]))),
		nl00iOl = ((((((((~ (nlll1l ^ rsync_comp_pat[32])) & (~ (nlll1O ^ rsync_comp_pat[33]))) & (~ (nlll0i ^ rsync_comp_pat[34]))) & (~ (nlll0l ^ rsync_comp_pat[35]))) & (~ (nlll0O ^ rsync_comp_pat[36]))) & (~ (nlllii ^ rsync_comp_pat[37]))) & (~ (nlllil ^ rsync_comp_pat[38]))) & (~ (nllliO ^ rsync_comp_pat[39]))),
		nl00iOO = ((((((((~ (nlli1i ^ rbytordpat[0])) & (~ (nlli1l ^ rbytordpat[1]))) & (~ (nlli1O ^ rbytordpat[2]))) & (~ (nlli0i ^ rbytordpat[3]))) & (~ (nlli0l ^ rbytordpat[4]))) & (~ (nlli0O ^ rbytordpat[5]))) & (~ (nlliii ^ rbytordpat[6]))) & (~ (nlliil ^ rbytordpat[7]))),
		nl00l0i = ((((((((~ (rsync_comp_pat[32] ^ wire_nl0l0Ol_byte_des_fifo_data_in[0])) & (~ (rsync_comp_pat[33] ^ wire_nl0l0Ol_byte_des_fifo_data_in[1]))) & (~ (rsync_comp_pat[34] ^ wire_nl0l0Ol_byte_des_fifo_data_in[2]))) & (~ (rsync_comp_pat[35] ^ wire_nl0l0Ol_byte_des_fifo_data_in[3]))) & (~ (rsync_comp_pat[36] ^ wire_nl0l0Ol_byte_des_fifo_data_in[4]))) & (~ (rsync_comp_pat[37] ^ wire_nl0l0Ol_byte_des_fifo_data_in[5]))) & (~ (rsync_comp_pat[38] ^ wire_nl0l0Ol_byte_des_fifo_data_in[6]))) & (~ (rsync_comp_pat[39] ^ wire_nl0l0Ol_byte_des_fifo_data_in[7]))),
		nl00l0l = ((((((((((~ (nlO10i ^ (~ rbytordpat[0]))) & (~ (nlO10l ^ (~ rbytordpat[1])))) & (~ (nlO10O ^ (~ rbytordpat[2])))) & (~ (nlO1ii ^ (~ rbytordpat[3])))) & (~ (nlO1il ^ (~ rbytordpat[4])))) & (~ (nlO1iO ^ (~ rbytordpat[5])))) & (~ (nlO1li ^ (~ rbytordpat[6])))) & (~ (nlO1ll ^ (~ rbytordpat[7])))) & (~ (nlO1lO ^ (~ rbytordpat[8])))) & (~ (nlO1Oi ^ (~ rbytordpat[9])))),
		nl00l0O = ((((((((((~ (nlO10i ^ rbytordpat[0])) & (~ (nlO10l ^ rbytordpat[1]))) & (~ (nlO10O ^ rbytordpat[2]))) & (~ (nlO1ii ^ rbytordpat[3]))) & (~ (nlO1il ^ rbytordpat[4]))) & (~ (nlO1iO ^ rbytordpat[5]))) & (~ (nlO1li ^ rbytordpat[6]))) & (~ (nlO1ll ^ rbytordpat[7]))) & (~ (nlO1lO ^ rbytordpat[8]))) & (~ (nlO1Oi ^ rbytordpat[9]))),
		nl00l1i = ((((((((~ (nllO1O ^ rsync_comp_pat[32])) & (~ (nllO0i ^ rsync_comp_pat[33]))) & (~ (nllO0l ^ rsync_comp_pat[34]))) & (~ (nllO0O ^ rsync_comp_pat[35]))) & (~ (nllOii ^ rsync_comp_pat[36]))) & (~ (nllOil ^ rsync_comp_pat[37]))) & (~ (nllOiO ^ rsync_comp_pat[38]))) & (~ (nllOli ^ rsync_comp_pat[39]))),
		nl00l1l = ((((((((~ (nlll1l ^ rbytordpat[0])) & (~ (nlll1O ^ rbytordpat[1]))) & (~ (nlll0i ^ rbytordpat[2]))) & (~ (nlll0l ^ rbytordpat[3]))) & (~ (nlll0O ^ rbytordpat[4]))) & (~ (nlllii ^ rbytordpat[5]))) & (~ (nlllil ^ rbytordpat[6]))) & (~ (nllliO ^ rbytordpat[7]))),
		nl00l1O = ((((((((~ (nlO10i ^ rsync_comp_pat[32])) & (~ (nlO10l ^ rsync_comp_pat[33]))) & (~ (nlO10O ^ rsync_comp_pat[34]))) & (~ (nlO1ii ^ rsync_comp_pat[35]))) & (~ (nlO1il ^ rsync_comp_pat[36]))) & (~ (nlO1iO ^ rsync_comp_pat[37]))) & (~ (nlO1li ^ rsync_comp_pat[38]))) & (~ (nlO1ll ^ rsync_comp_pat[39]))),
		nl00lii = ((((((((((~ (nllO1O ^ (~ rbytordpat[0]))) & (~ (nllO0i ^ (~ rbytordpat[1])))) & (~ (nllO0l ^ (~ rbytordpat[2])))) & (~ (nllO0O ^ (~ rbytordpat[3])))) & (~ (nllOii ^ (~ rbytordpat[4])))) & (~ (nllOil ^ (~ rbytordpat[5])))) & (~ (nllOiO ^ (~ rbytordpat[6])))) & (~ (nllOli ^ (~ rbytordpat[7])))) & (~ (nllOll ^ (~ rbytordpat[8])))) & (~ (nllOlO ^ (~ rbytordpat[9])))),
		nl00lil = ((((((((((~ (nllO1O ^ rbytordpat[0])) & (~ (nllO0i ^ rbytordpat[1]))) & (~ (nllO0l ^ rbytordpat[2]))) & (~ (nllO0O ^ rbytordpat[3]))) & (~ (nllOii ^ rbytordpat[4]))) & (~ (nllOil ^ rbytordpat[5]))) & (~ (nllOiO ^ rbytordpat[6]))) & (~ (nllOli ^ rbytordpat[7]))) & (~ (nllOll ^ rbytordpat[8]))) & (~ (nllOlO ^ rbytordpat[9]))),
		nl00liO = (nl00llO | nl00lll),
		nl00lli = (((~ nl00llO) & (~ nl00lll)) | (~ rbytordplden)),
		nl00lll = ((((((((((~ ((~ rbytordpat[0]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[0])) & (~ ((~ rbytordpat[1]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[1]))) & (~ ((~ rbytordpat[2]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[2]))) & (~ ((~ rbytordpat[3]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[3]))) & (~ ((~ rbytordpat[4]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[4]))) & (~ ((~ rbytordpat[5]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[5]))) & (~ ((~ rbytordpat[6]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[6]))) & (~ ((~ rbytordpat[7]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[7]))) & (~ ((~ rbytordpat[8]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[8]))) & (~ ((~ rbytordpat[9]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[9]))),
		nl00llO = ((((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[0])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[1]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[2]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[3]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[4]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[5]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[6]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[7]))) & (~ (rbytordpat[8] ^ wire_nl0l0Ol_byte_des_fifo_data_in[8]))) & (~ (rbytordpat[9] ^ wire_nl0l0Ol_byte_des_fifo_data_in[9]))),
		nl00lOi = (nl00O0i | nl00O1O),
		nl00lOl = ((((((((((~ ((~ rbytordpat[0]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[16])) & (~ ((~ rbytordpat[1]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[17]))) & (~ ((~ rbytordpat[2]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[18]))) & (~ ((~ rbytordpat[3]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[19]))) & (~ ((~ rbytordpat[4]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[20]))) & (~ ((~ rbytordpat[5]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[21]))) & (~ ((~ rbytordpat[6]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[22]))) & (~ ((~ rbytordpat[7]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[23]))) & (~ ((~ rbytordpat[8]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[24]))) & (~ ((~ rbytordpat[9]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[25]))),
		nl00lOO = ((((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[16])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[17]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[18]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[19]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[20]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[21]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[22]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[23]))) & (~ (rbytordpat[8] ^ wire_nl0l0Ol_byte_des_fifo_data_in[24]))) & (~ (rbytordpat[9] ^ wire_nl0l0Ol_byte_des_fifo_data_in[25]))),
		nl00O0i = ((((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[32])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[33]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[34]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[35]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[36]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[37]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[38]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[39]))) & (~ (rbytordpat[8] ^ wire_nl0l0Ol_byte_des_fifo_data_in[40]))) & (~ (rbytordpat[9] ^ wire_nl0l0Ol_byte_des_fifo_data_in[41]))),
		nl00O0l = (((((((((~ (nlO10i ^ rbytordpat[0])) & (~ (nlO10l ^ rbytordpat[1]))) & (~ (nlO10O ^ rbytordpat[2]))) & (~ (nlO1ii ^ rbytordpat[3]))) & (~ (nlO1il ^ rbytordpat[4]))) & (~ (nlO1iO ^ rbytordpat[5]))) & (~ (nlO1li ^ rbytordpat[6]))) & (~ (nlO1ll ^ rbytordpat[7]))) & (~ (nlO1lO ^ rbytordpat[8]))),
		nl00O0O = (((((((((~ (nllO1O ^ rbytordpat[0])) & (~ (nllO0i ^ rbytordpat[1]))) & (~ (nllO0l ^ rbytordpat[2]))) & (~ (nllO0O ^ rbytordpat[3]))) & (~ (nllOii ^ rbytordpat[4]))) & (~ (nllOil ^ rbytordpat[5]))) & (~ (nllOiO ^ rbytordpat[6]))) & (~ (nllOli ^ rbytordpat[7]))) & (~ (nllOll ^ rbytordpat[8]))),
		nl00O1i = ((((((((((~ ((~ rbytordpat[0]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[48])) & (~ ((~ rbytordpat[1]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[49]))) & (~ ((~ rbytordpat[2]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[50]))) & (~ ((~ rbytordpat[3]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[51]))) & (~ ((~ rbytordpat[4]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[52]))) & (~ ((~ rbytordpat[5]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[53]))) & (~ ((~ rbytordpat[6]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[54]))) & (~ ((~ rbytordpat[7]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[55]))) & (~ ((~ rbytordpat[8]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[56]))) & (~ ((~ rbytordpat[9]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[57]))),
		nl00O1l = ((((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[48])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[49]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[50]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[51]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[52]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[53]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[54]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[55]))) & (~ (rbytordpat[8] ^ wire_nl0l0Ol_byte_des_fifo_data_in[56]))) & (~ (rbytordpat[9] ^ wire_nl0l0Ol_byte_des_fifo_data_in[57]))),
		nl00O1O = ((((((((((~ ((~ rbytordpat[0]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[32])) & (~ ((~ rbytordpat[1]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[33]))) & (~ ((~ rbytordpat[2]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[34]))) & (~ ((~ rbytordpat[3]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[35]))) & (~ ((~ rbytordpat[4]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[36]))) & (~ ((~ rbytordpat[5]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[37]))) & (~ ((~ rbytordpat[6]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[38]))) & (~ ((~ rbytordpat[7]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[39]))) & (~ ((~ rbytordpat[8]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[40]))) & (~ ((~ rbytordpat[9]) ^ wire_nl0l0Ol_byte_des_fifo_data_in[41]))),
		nl00Oii = ((~ rbytordplden) | (~ nl00Oil)),
		nl00Oil = (((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[0])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[1]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[2]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[3]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[4]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[5]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[6]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[7]))) & (~ (rbytordpat[8] ^ wire_nl0l0Ol_byte_des_fifo_data_in[8]))),
		nl00OiO = (((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[16])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[17]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[18]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[19]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[20]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[21]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[22]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[23]))) & (~ (rbytordpat[8] ^ wire_nl0l0Ol_byte_des_fifo_data_in[24]))),
		nl00Oli = (((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[48])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[49]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[50]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[51]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[52]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[53]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[54]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[55]))) & (~ (rbytordpat[8] ^ wire_nl0l0Ol_byte_des_fifo_data_in[56]))),
		nl00Oll = (((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[32])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[33]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[34]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[35]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[36]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[37]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[38]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[39]))) & (~ (rbytordpat[8] ^ wire_nl0l0Ol_byte_des_fifo_data_in[40]))),
		nl00OlO = ((((((((~ (nlO10i ^ rbytordpat[0])) & (~ (nlO10l ^ rbytordpat[1]))) & (~ (nlO10O ^ rbytordpat[2]))) & (~ (nlO1ii ^ rbytordpat[3]))) & (~ (nlO1il ^ rbytordpat[4]))) & (~ (nlO1iO ^ rbytordpat[5]))) & (~ (nlO1li ^ rbytordpat[6]))) & (~ (nlO1ll ^ rbytordpat[7]))),
		nl00OOi = ((((((((~ (nllO1O ^ rbytordpat[0])) & (~ (nllO0i ^ rbytordpat[1]))) & (~ (nllO0l ^ rbytordpat[2]))) & (~ (nllO0O ^ rbytordpat[3]))) & (~ (nllOii ^ rbytordpat[4]))) & (~ (nllOil ^ rbytordpat[5]))) & (~ (nllOiO ^ rbytordpat[6]))) & (~ (nllOli ^ rbytordpat[7]))),
		nl00OOl = ((~ rbytordplden) | (~ nl00OOO)),
		nl00OOO = ((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[0])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[1]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[2]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[3]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[4]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[5]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[6]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[7]))),
		nl0i00i = (((((((rx_data_rs[0] | (~ rx_data_rs[1])) | (~ rx_data_rs[2])) | (~ rx_data_rs[3])) | (~ rx_data_rs[4])) | (~ rx_data_rs[5])) | (~ rx_data_rs[6])) | (~ rx_data_rs[7])),
		nl0i00l = ((~ (((((rwa_6g_en & (~ rinvalid_code_err_only)) & (~ invalid_code_delay[1])) & disp_err_delay[1]) & sync_resync_delay[1]) & (~ n1iOO))) & (wire_nll_dataout & ((n110O & (~ rautoinsdis)) & (~ rsync_sm_dis)))),
		nl0i00O = ((~ rautoinsdis) & (~ rsync_sm_dis)),
		nl0i01i = ((((((((~ (rsync_comp_pat[16] ^ tenb_data[10])) & (~ (rsync_comp_pat[17] ^ tenb_data[11]))) & (~ (rsync_comp_pat[18] ^ tenb_data[12]))) & (~ (rsync_comp_pat[19] ^ tenb_data[13]))) & (~ (rsync_comp_pat[20] ^ tenb_data[14]))) & (~ (rsync_comp_pat[21] ^ tenb_data[15]))) & (~ (rsync_comp_pat[22] ^ tenb_data[16]))) & (~ (rsync_comp_pat[23] ^ tenb_data[17]))),
		nl0i01l = 1'b1,
		nl0i0ii = ((~ (((((rwa_6g_en & (~ rinvalid_code_err_only)) & (~ invalid_code_delay[0])) & disp_err_delay[0]) & sync_resync_delay[0]) & (~ n1iOl))) & (wire_nli_dataout & ((n110l & (~ rautoinsdis)) & (~ rsync_sm_dis)))),
		nl0i0il = ((~ rautoinsdis) & (~ rsync_sm_dis)),
		nl0i0iO = ((((((((((((((((((((~ (rsync_comp_pat[20] ^ tenb_data[0])) & (~ (rsync_comp_pat[21] ^ tenb_data[1]))) & (~ (rsync_comp_pat[22] ^ tenb_data[2]))) & (~ (rsync_comp_pat[23] ^ tenb_data[3]))) & (~ (rsync_comp_pat[24] ^ tenb_data[4]))) & (~ (rsync_comp_pat[25] ^ tenb_data[5]))) & (~ (rsync_comp_pat[26] ^ tenb_data[6]))) & (~ (rsync_comp_pat[27] ^ tenb_data[7]))) & (~ (rsync_comp_pat[28] ^ tenb_data[8]))) & (~ (rsync_comp_pat[29] ^ tenb_data[9]))) & (~ (rsync_comp_pat[30] ^ tenb_data[10]))) & (~ (rsync_comp_pat[31] ^ tenb_data[11]))) & (~ (rsync_comp_pat[32] ^ tenb_data[12]))) & (~ (rsync_comp_pat[33] ^ tenb_data[13]))) & (~ (rsync_comp_pat[34] ^ tenb_data[14]))) & (~ (rsync_comp_pat[35] ^ tenb_data[15]))) & (~ (rsync_comp_pat[36] ^ tenb_data[16]))) & (~ (rsync_comp_pat[37] ^ tenb_data[17]))) & (~ (rsync_comp_pat[38] ^ tenb_data[18]))) & (~ (rsync_comp_pat[39] ^ tenb_data[19]))),
		nl0i0li = ((((((((((~ ((~ rsync_comp_pat[30]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[31]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[32]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[33]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[34]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[35]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[36]) ^ tenb_data[16]))) & (~ ((~ rsync_comp_pat[37]) ^ tenb_data[17]))) & (~ ((~ rsync_comp_pat[38]) ^ tenb_data[18]))) & (~ ((~ rsync_comp_pat[39]) ^ tenb_data[19]))),
		nl0i0ll = ((((((((((~ (rsync_comp_pat[30] ^ tenb_data[10])) & (~ (rsync_comp_pat[31] ^ tenb_data[11]))) & (~ (rsync_comp_pat[32] ^ tenb_data[12]))) & (~ (rsync_comp_pat[33] ^ tenb_data[13]))) & (~ (rsync_comp_pat[34] ^ tenb_data[14]))) & (~ (rsync_comp_pat[35] ^ tenb_data[15]))) & (~ (rsync_comp_pat[36] ^ tenb_data[16]))) & (~ (rsync_comp_pat[37] ^ tenb_data[17]))) & (~ (rsync_comp_pat[38] ^ tenb_data[18]))) & (~ (rsync_comp_pat[39] ^ tenb_data[19]))),
		nl0i0lO = ((((((((((~ ((~ rsync_comp_pat[20]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[21]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[22]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[23]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[24]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[25]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[26]) ^ tenb_data[6]))) & (~ ((~ rsync_comp_pat[27]) ^ tenb_data[7]))) & (~ ((~ rsync_comp_pat[28]) ^ tenb_data[8]))) & (~ ((~ rsync_comp_pat[29]) ^ tenb_data[9]))),
		nl0i0Oi = ((((((((((~ (rsync_comp_pat[20] ^ tenb_data[0])) & (~ (rsync_comp_pat[21] ^ tenb_data[1]))) & (~ (rsync_comp_pat[22] ^ tenb_data[2]))) & (~ (rsync_comp_pat[23] ^ tenb_data[3]))) & (~ (rsync_comp_pat[24] ^ tenb_data[4]))) & (~ (rsync_comp_pat[25] ^ tenb_data[5]))) & (~ (rsync_comp_pat[26] ^ tenb_data[6]))) & (~ (rsync_comp_pat[27] ^ tenb_data[7]))) & (~ (rsync_comp_pat[28] ^ tenb_data[8]))) & (~ (rsync_comp_pat[29] ^ tenb_data[9]))),
		nl0i0Ol = ((((((((((((((((~ (rsync_comp_pat[16] ^ tenb_data[0])) & (~ (rsync_comp_pat[17] ^ tenb_data[1]))) & (~ (rsync_comp_pat[18] ^ tenb_data[2]))) & (~ (rsync_comp_pat[19] ^ tenb_data[3]))) & (~ (rsync_comp_pat[20] ^ tenb_data[4]))) & (~ (rsync_comp_pat[21] ^ tenb_data[5]))) & (~ (rsync_comp_pat[22] ^ tenb_data[6]))) & (~ (rsync_comp_pat[23] ^ tenb_data[7]))) & (~ (rsync_comp_pat[24] ^ tenb_data[10]))) & (~ (rsync_comp_pat[25] ^ tenb_data[11]))) & (~ (rsync_comp_pat[26] ^ tenb_data[12]))) & (~ (rsync_comp_pat[27] ^ tenb_data[13]))) & (~ (rsync_comp_pat[28] ^ tenb_data[14]))) & (~ (rsync_comp_pat[29] ^ tenb_data[15]))) & (~ (rsync_comp_pat[30] ^ tenb_data[16]))) & (~ (rsync_comp_pat[31] ^ tenb_data[17]))),
		nl0i0OO = ((((((((~ ((~ rsync_comp_pat[24]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[25]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[26]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[27]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[28]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[29]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[30]) ^ tenb_data[16]))) & (~ ((~ rsync_comp_pat[31]) ^ tenb_data[17]))),
		nl0i10i = ((((~ nlilll) & (~ nlilli)) & (~ nliliO)) & (~ n11OOO)),
		nl0i10l = ((~ wire_nlOiOi_dataout) & (~ wire_nlOilO_dataout)),
		nl0i10O = ((~ rbytorden[0]) & (~ rbytorden[1])),
		nl0i11i = ((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[16])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[17]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[18]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[19]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[20]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[21]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[22]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[23]))),
		nl0i11l = ((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[48])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[49]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[50]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[51]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[52]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[53]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[54]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[55]))),
		nl0i11O = ((((((((~ (rbytordpat[0] ^ wire_nl0l0Ol_byte_des_fifo_data_in[32])) & (~ (rbytordpat[1] ^ wire_nl0l0Ol_byte_des_fifo_data_in[33]))) & (~ (rbytordpat[2] ^ wire_nl0l0Ol_byte_des_fifo_data_in[34]))) & (~ (rbytordpat[3] ^ wire_nl0l0Ol_byte_des_fifo_data_in[35]))) & (~ (rbytordpat[4] ^ wire_nl0l0Ol_byte_des_fifo_data_in[36]))) & (~ (rbytordpat[5] ^ wire_nl0l0Ol_byte_des_fifo_data_in[37]))) & (~ (rbytordpat[6] ^ wire_nl0l0Ol_byte_des_fifo_data_in[38]))) & (~ (rbytordpat[7] ^ wire_nl0l0Ol_byte_des_fifo_data_in[39]))),
		nl0i1li = 1'b0,
		nl0i1ll = ((((((((((((((((((((~ (rsync_comp_pat[10] ^ tenb_data[0])) & (~ (rsync_comp_pat[11] ^ tenb_data[1]))) & (~ (rsync_comp_pat[12] ^ tenb_data[2]))) & (~ (rsync_comp_pat[13] ^ tenb_data[3]))) & (~ (rsync_comp_pat[14] ^ tenb_data[4]))) & (~ (rsync_comp_pat[15] ^ tenb_data[5]))) & (~ (rsync_comp_pat[16] ^ tenb_data[6]))) & (~ (rsync_comp_pat[17] ^ tenb_data[7]))) & (~ (rsync_comp_pat[18] ^ tenb_data[8]))) & (~ (rsync_comp_pat[19] ^ tenb_data[9]))) & (~ (rsync_comp_pat[20] ^ tenb_data[10]))) & (~ (rsync_comp_pat[21] ^ tenb_data[11]))) & (~ (rsync_comp_pat[22] ^ tenb_data[12]))) & (~ (rsync_comp_pat[23] ^ tenb_data[13]))) & (~ (rsync_comp_pat[24] ^ tenb_data[14]))) & (~ (rsync_comp_pat[25] ^ tenb_data[15]))) & (~ (rsync_comp_pat[26] ^ tenb_data[16]))) & (~ (rsync_comp_pat[27] ^ tenb_data[17]))) & (~ (rsync_comp_pat[28] ^ tenb_data[18]))) & (~ (rsync_comp_pat[29] ^ tenb_data[19]))),
		nl0i1lO = ((((((((((~ ((~ rsync_comp_pat[20]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[21]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[22]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[23]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[24]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[25]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[26]) ^ tenb_data[16]))) & (~ ((~ rsync_comp_pat[27]) ^ tenb_data[17]))) & (~ ((~ rsync_comp_pat[28]) ^ tenb_data[18]))) & (~ ((~ rsync_comp_pat[29]) ^ tenb_data[19]))),
		nl0i1Oi = ((((((((((~ (rsync_comp_pat[20] ^ tenb_data[10])) & (~ (rsync_comp_pat[21] ^ tenb_data[11]))) & (~ (rsync_comp_pat[22] ^ tenb_data[12]))) & (~ (rsync_comp_pat[23] ^ tenb_data[13]))) & (~ (rsync_comp_pat[24] ^ tenb_data[14]))) & (~ (rsync_comp_pat[25] ^ tenb_data[15]))) & (~ (rsync_comp_pat[26] ^ tenb_data[16]))) & (~ (rsync_comp_pat[27] ^ tenb_data[17]))) & (~ (rsync_comp_pat[28] ^ tenb_data[18]))) & (~ (rsync_comp_pat[29] ^ tenb_data[19]))),
		nl0i1Ol = ((((((((((((((((~ (rsync_comp_pat[8] ^ tenb_data[0])) & (~ (rsync_comp_pat[9] ^ tenb_data[1]))) & (~ (rsync_comp_pat[10] ^ tenb_data[2]))) & (~ (rsync_comp_pat[11] ^ tenb_data[3]))) & (~ (rsync_comp_pat[12] ^ tenb_data[4]))) & (~ (rsync_comp_pat[13] ^ tenb_data[5]))) & (~ (rsync_comp_pat[14] ^ tenb_data[6]))) & (~ (rsync_comp_pat[15] ^ tenb_data[7]))) & (~ (rsync_comp_pat[16] ^ tenb_data[10]))) & (~ (rsync_comp_pat[17] ^ tenb_data[11]))) & (~ (rsync_comp_pat[18] ^ tenb_data[12]))) & (~ (rsync_comp_pat[19] ^ tenb_data[13]))) & (~ (rsync_comp_pat[20] ^ tenb_data[14]))) & (~ (rsync_comp_pat[21] ^ tenb_data[15]))) & (~ (rsync_comp_pat[22] ^ tenb_data[16]))) & (~ (rsync_comp_pat[23] ^ tenb_data[17]))),
		nl0i1OO = ((((((((~ ((~ rsync_comp_pat[16]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[17]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[18]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[19]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[20]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[21]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[22]) ^ tenb_data[16]))) & (~ ((~ rsync_comp_pat[23]) ^ tenb_data[17]))),
		nl0ii0i = (((((((~ ((~ rsync_comp_pat[0]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[1]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[2]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[3]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[4]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[5]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[6]) ^ tenb_data[16]))),
		nl0ii0l = (((((((~ (rsync_comp_pat[0] ^ tenb_data[10])) & (~ (rsync_comp_pat[1] ^ tenb_data[11]))) & (~ (rsync_comp_pat[2] ^ tenb_data[12]))) & (~ (rsync_comp_pat[3] ^ tenb_data[13]))) & (~ (rsync_comp_pat[4] ^ tenb_data[14]))) & (~ (rsync_comp_pat[5] ^ tenb_data[15]))) & (~ (rsync_comp_pat[6] ^ tenb_data[16]))),
		nl0ii0O = (((((((((((((((((((((((((((((((((((((((((((((wire_nl10i_o[63] | wire_nl10i_o[62]) | wire_nl10i_o[59]) | wire_nl10i_o[58]) | wire_nl10i_o[55]) | wire_nl10i_o[54]) | wire_nl10i_o[51]) | wire_nl10i_o[50]) | wire_nl10i_o[47]) | wire_nl10i_o[46]) | wire_nl10i_o[45]) | wire_nl10i_o[44]) | wire_nl10i_o[41]) | wire_nl10i_o[40]) | wire_nl10i_o[37]) | wire_nl10i_o[36]) | wire_nl10i_o[33]) | wire_nl10i_o[32]) | wire_nl10i_o[31]) | wire_nl10i_o[30]) | wire_nl10i_o[29]) | wire_nl10i_o[28]) | wire_nl10i_o[27]) | wire_nl10i_o[26]) | wire_nl10i_o[25]) | wire_nl10i_o[24]) | wire_nl10i_o[23]) | wire_nl10i_o[22]) | wire_nl10i_o[19]) | wire_nl10i_o[18]) | wire_nl10i_o[15]) | wire_nl10i_o[14]) | wire_nl10i_o[13]) | wire_nl10i_o[12]) | wire_nl10i_o[11]) | wire_nl10i_o[10]) | wire_nl10i_o[9]) | wire_nl10i_o[8]) | wire_nl10i_o[7]) | wire_nl10i_o[6]) | wire_nl10i_o[5]) | wire_nl10i_o[4]) | wire_nl10i_o[3]) | wire_nl10i_o[2]) | wire_nl10i_o[1]) | wire_nl10i_o[0]),
		nl0ii1i = ((((((((~ (rsync_comp_pat[24] ^ tenb_data[10])) & (~ (rsync_comp_pat[25] ^ tenb_data[11]))) & (~ (rsync_comp_pat[26] ^ tenb_data[12]))) & (~ (rsync_comp_pat[27] ^ tenb_data[13]))) & (~ (rsync_comp_pat[28] ^ tenb_data[14]))) & (~ (rsync_comp_pat[29] ^ tenb_data[15]))) & (~ (rsync_comp_pat[30] ^ tenb_data[16]))) & (~ (rsync_comp_pat[31] ^ tenb_data[17]))),
		nl0ii1l = ((((((((~ ((~ rsync_comp_pat[16]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[17]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[18]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[19]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[20]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[21]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[22]) ^ tenb_data[6]))) & (~ ((~ rsync_comp_pat[23]) ^ tenb_data[7]))),
		nl0ii1O = ((((((((~ (rsync_comp_pat[16] ^ tenb_data[0])) & (~ (rsync_comp_pat[17] ^ tenb_data[1]))) & (~ (rsync_comp_pat[18] ^ tenb_data[2]))) & (~ (rsync_comp_pat[19] ^ tenb_data[3]))) & (~ (rsync_comp_pat[20] ^ tenb_data[4]))) & (~ (rsync_comp_pat[21] ^ tenb_data[5]))) & (~ (rsync_comp_pat[22] ^ tenb_data[6]))) & (~ (rsync_comp_pat[23] ^ tenb_data[7]))),
		nl0iiii = (((nl0iOOO & rsync_comp_porn) & (nl0iili | nl0iiiO)) | nl0iiil),
		nl0iiil = ((((((((((((((((((((~ (rsync_comp_pat[0] ^ tenb_data[0])) & (~ (rsync_comp_pat[1] ^ tenb_data[1]))) & (~ (rsync_comp_pat[2] ^ tenb_data[2]))) & (~ (rsync_comp_pat[3] ^ tenb_data[3]))) & (~ (rsync_comp_pat[4] ^ tenb_data[4]))) & (~ (rsync_comp_pat[5] ^ tenb_data[5]))) & (~ (rsync_comp_pat[6] ^ tenb_data[6]))) & (~ (rsync_comp_pat[7] ^ tenb_data[7]))) & (~ (rsync_comp_pat[8] ^ tenb_data[8]))) & (~ (rsync_comp_pat[9] ^ tenb_data[9]))) & (~ (rsync_comp_pat[10] ^ tenb_data[10]))) & (~ (rsync_comp_pat[11] ^ tenb_data[11]))) & (~ (rsync_comp_pat[12] ^ tenb_data[12]))) & (~ (rsync_comp_pat[13] ^ tenb_data[13]))) & (~ (rsync_comp_pat[14] ^ tenb_data[14]))) & (~ (rsync_comp_pat[15] ^ tenb_data[15]))) & (~ (rsync_comp_pat[16] ^ tenb_data[16]))) & (~ (rsync_comp_pat[17] ^ tenb_data[17]))) & (~ (rsync_comp_pat[18] ^ tenb_data[18]))) & (~ (rsync_comp_pat[19] ^ tenb_data[19]))),
		nl0iiiO = ((((((((((~ ((~ rsync_comp_pat[10]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[11]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[12]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[13]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[14]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[15]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[16]) ^ tenb_data[16]))) & (~ ((~ rsync_comp_pat[17]) ^ tenb_data[17]))) & (~ ((~ rsync_comp_pat[18]) ^ tenb_data[18]))) & (~ ((~ rsync_comp_pat[19]) ^ tenb_data[19]))),
		nl0iili = ((((((((((~ (rsync_comp_pat[10] ^ tenb_data[10])) & (~ (rsync_comp_pat[11] ^ tenb_data[11]))) & (~ (rsync_comp_pat[12] ^ tenb_data[12]))) & (~ (rsync_comp_pat[13] ^ tenb_data[13]))) & (~ (rsync_comp_pat[14] ^ tenb_data[14]))) & (~ (rsync_comp_pat[15] ^ tenb_data[15]))) & (~ (rsync_comp_pat[16] ^ tenb_data[16]))) & (~ (rsync_comp_pat[17] ^ tenb_data[17]))) & (~ (rsync_comp_pat[18] ^ tenb_data[18]))) & (~ (rsync_comp_pat[19] ^ tenb_data[19]))),
		nl0iill = ((((nl0iOOl | nl0iOll) & rsync_comp_porn) & (nl0iiOl | nl0iiOi)) | nl0iilO),
		nl0iilO = ((((((((((((((((~ (rsync_comp_pat[0] ^ tenb_data[0])) & (~ (rsync_comp_pat[1] ^ tenb_data[1]))) & (~ (rsync_comp_pat[2] ^ tenb_data[2]))) & (~ (rsync_comp_pat[3] ^ tenb_data[3]))) & (~ (rsync_comp_pat[4] ^ tenb_data[4]))) & (~ (rsync_comp_pat[5] ^ tenb_data[5]))) & (~ (rsync_comp_pat[6] ^ tenb_data[6]))) & (~ (rsync_comp_pat[7] ^ tenb_data[7]))) & (~ (rsync_comp_pat[8] ^ tenb_data[10]))) & (~ (rsync_comp_pat[9] ^ tenb_data[11]))) & (~ (rsync_comp_pat[10] ^ tenb_data[12]))) & (~ (rsync_comp_pat[11] ^ tenb_data[13]))) & (~ (rsync_comp_pat[12] ^ tenb_data[14]))) & (~ (rsync_comp_pat[13] ^ tenb_data[15]))) & (~ (rsync_comp_pat[14] ^ tenb_data[16]))) & (~ (rsync_comp_pat[15] ^ tenb_data[17]))),
		nl0iiOi = ((((((((~ (rsync_comp_pat[8] ^ tenb_data[10])) & (~ (rsync_comp_pat[9] ^ tenb_data[11]))) & (~ (rsync_comp_pat[10] ^ tenb_data[12]))) & (~ (rsync_comp_pat[11] ^ tenb_data[13]))) & (~ (rsync_comp_pat[12] ^ tenb_data[14]))) & (~ (rsync_comp_pat[13] ^ tenb_data[15]))) & (~ (rsync_comp_pat[14] ^ tenb_data[16]))) & (~ (rsync_comp_pat[15] ^ tenb_data[17]))),
		nl0iiOl = ((((((((~ ((~ rsync_comp_pat[8]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[9]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[10]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[11]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[12]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[13]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[14]) ^ tenb_data[16]))) & (~ ((~ rsync_comp_pat[15]) ^ tenb_data[17]))),
		nl0iiOO = ((rsync_comp_porn & nl0il1l) | nl0il1i),
		nl0il0i = ((((((((~ (rsync_comp_pat[0] ^ tenb_data[10])) & (~ (rsync_comp_pat[1] ^ tenb_data[11]))) & (~ (rsync_comp_pat[2] ^ tenb_data[12]))) & (~ (rsync_comp_pat[3] ^ tenb_data[13]))) & (~ (rsync_comp_pat[4] ^ tenb_data[14]))) & (~ (rsync_comp_pat[5] ^ tenb_data[15]))) & (~ (rsync_comp_pat[6] ^ tenb_data[16]))) & (~ (rsync_comp_pat[7] ^ tenb_data[17]))),
		nl0il0l = ((((((((~ ((~ rsync_comp_pat[0]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[1]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[2]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[3]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[4]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[5]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[6]) ^ tenb_data[16]))) & (~ ((~ rsync_comp_pat[7]) ^ tenb_data[17]))),
		nl0il0O = ((((((((((~ (rsync_comp_pat[30] ^ tenb_data[0])) & (~ (rsync_comp_pat[31] ^ tenb_data[1]))) & (~ (rsync_comp_pat[32] ^ tenb_data[2]))) & (~ (rsync_comp_pat[33] ^ tenb_data[3]))) & (~ (rsync_comp_pat[34] ^ tenb_data[4]))) & (~ (rsync_comp_pat[35] ^ tenb_data[5]))) & (~ (rsync_comp_pat[36] ^ tenb_data[6]))) & (~ (rsync_comp_pat[37] ^ tenb_data[7]))) & (~ (rsync_comp_pat[38] ^ tenb_data[8]))) & (~ (rsync_comp_pat[39] ^ tenb_data[9]))),
		nl0il1i = ((((((((((~ (rsync_comp_pat[0] ^ tenb_data[10])) & (~ (rsync_comp_pat[1] ^ tenb_data[11]))) & (~ (rsync_comp_pat[2] ^ tenb_data[12]))) & (~ (rsync_comp_pat[3] ^ tenb_data[13]))) & (~ (rsync_comp_pat[4] ^ tenb_data[14]))) & (~ (rsync_comp_pat[5] ^ tenb_data[15]))) & (~ (rsync_comp_pat[6] ^ tenb_data[16]))) & (~ (rsync_comp_pat[7] ^ tenb_data[17]))) & (~ (rsync_comp_pat[8] ^ tenb_data[18]))) & (~ (rsync_comp_pat[9] ^ tenb_data[19]))),
		nl0il1l = ((((((((((~ ((~ rsync_comp_pat[0]) ^ tenb_data[10])) & (~ ((~ rsync_comp_pat[1]) ^ tenb_data[11]))) & (~ ((~ rsync_comp_pat[2]) ^ tenb_data[12]))) & (~ ((~ rsync_comp_pat[3]) ^ tenb_data[13]))) & (~ ((~ rsync_comp_pat[4]) ^ tenb_data[14]))) & (~ ((~ rsync_comp_pat[5]) ^ tenb_data[15]))) & (~ ((~ rsync_comp_pat[6]) ^ tenb_data[16]))) & (~ ((~ rsync_comp_pat[7]) ^ tenb_data[17]))) & (~ ((~ rsync_comp_pat[8]) ^ tenb_data[18]))) & (~ ((~ rsync_comp_pat[9]) ^ tenb_data[19]))),
		nl0il1O = ((rsync_comp_porn & nl0il0l) | nl0il0i),
		nl0ilii = ((((((((((~ ((~ rsync_comp_pat[30]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[31]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[32]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[33]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[34]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[35]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[36]) ^ tenb_data[6]))) & (~ ((~ rsync_comp_pat[37]) ^ tenb_data[7]))) & (~ ((~ rsync_comp_pat[38]) ^ tenb_data[8]))) & (~ ((~ rsync_comp_pat[39]) ^ tenb_data[9]))),
		nl0ilil = ((((((((((~ (rsync_comp_pat[10] ^ tenb_data[0])) & (~ (rsync_comp_pat[11] ^ tenb_data[1]))) & (~ (rsync_comp_pat[12] ^ tenb_data[2]))) & (~ (rsync_comp_pat[13] ^ tenb_data[3]))) & (~ (rsync_comp_pat[14] ^ tenb_data[4]))) & (~ (rsync_comp_pat[15] ^ tenb_data[5]))) & (~ (rsync_comp_pat[16] ^ tenb_data[6]))) & (~ (rsync_comp_pat[17] ^ tenb_data[7]))) & (~ (rsync_comp_pat[18] ^ tenb_data[8]))) & (~ (rsync_comp_pat[19] ^ tenb_data[9]))),
		nl0iliO = ((((((((((~ ((~ rsync_comp_pat[10]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[11]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[12]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[13]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[14]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[15]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[16]) ^ tenb_data[6]))) & (~ ((~ rsync_comp_pat[17]) ^ tenb_data[7]))) & (~ ((~ rsync_comp_pat[18]) ^ tenb_data[8]))) & (~ ((~ rsync_comp_pat[19]) ^ tenb_data[9]))),
		nl0illO = ((((((((((~ (rsync_comp_pat[0] ^ tenb_data[0])) & (~ (rsync_comp_pat[1] ^ tenb_data[1]))) & (~ (rsync_comp_pat[2] ^ tenb_data[2]))) & (~ (rsync_comp_pat[3] ^ tenb_data[3]))) & (~ (rsync_comp_pat[4] ^ tenb_data[4]))) & (~ (rsync_comp_pat[5] ^ tenb_data[5]))) & (~ (rsync_comp_pat[6] ^ tenb_data[6]))) & (~ (rsync_comp_pat[7] ^ tenb_data[7]))) & (~ (rsync_comp_pat[8] ^ tenb_data[8]))) & (~ (rsync_comp_pat[9] ^ tenb_data[9]))),
		nl0ilOO = ((((((((((~ ((~ rsync_comp_pat[0]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[1]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[2]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[3]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[4]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[5]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[6]) ^ tenb_data[6]))) & (~ ((~ rsync_comp_pat[7]) ^ tenb_data[7]))) & (~ ((~ rsync_comp_pat[8]) ^ tenb_data[8]))) & (~ ((~ rsync_comp_pat[9]) ^ tenb_data[9]))),
		nl0iO0O = ((((((((~ ((~ rsync_comp_pat[24]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[25]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[26]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[27]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[28]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[29]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[30]) ^ tenb_data[6]))) & (~ ((~ rsync_comp_pat[31]) ^ tenb_data[7]))),
		nl0iO1O = ((((((((~ (rsync_comp_pat[24] ^ tenb_data[0])) & (~ (rsync_comp_pat[25] ^ tenb_data[1]))) & (~ (rsync_comp_pat[26] ^ tenb_data[2]))) & (~ (rsync_comp_pat[27] ^ tenb_data[3]))) & (~ (rsync_comp_pat[28] ^ tenb_data[4]))) & (~ (rsync_comp_pat[29] ^ tenb_data[5]))) & (~ (rsync_comp_pat[30] ^ tenb_data[6]))) & (~ (rsync_comp_pat[31] ^ tenb_data[7]))),
		nl0iOli = ((((((((~ ((~ rsync_comp_pat[8]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[9]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[10]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[11]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[12]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[13]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[14]) ^ tenb_data[6]))) & (~ ((~ rsync_comp_pat[15]) ^ tenb_data[7]))),
		nl0iOll = ((((((((~ (rsync_comp_pat[0] ^ tenb_data[0])) & (~ (rsync_comp_pat[1] ^ tenb_data[1]))) & (~ (rsync_comp_pat[2] ^ tenb_data[2]))) & (~ (rsync_comp_pat[3] ^ tenb_data[3]))) & (~ (rsync_comp_pat[4] ^ tenb_data[4]))) & (~ (rsync_comp_pat[5] ^ tenb_data[5]))) & (~ (rsync_comp_pat[6] ^ tenb_data[6]))) & (~ (rsync_comp_pat[7] ^ tenb_data[7]))),
		nl0iOOl = ((((((((~ ((~ rsync_comp_pat[0]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[1]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[2]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[3]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[4]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[5]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[6]) ^ tenb_data[6]))) & (~ ((~ rsync_comp_pat[7]) ^ tenb_data[7]))),
		nl0iOOO = (nl0illO | nl0ilOO),
		nl0l00O = ((((((((~ (rsync_comp_pat[8] ^ tenb_data[0])) & (~ (rsync_comp_pat[9] ^ tenb_data[1]))) & (~ (rsync_comp_pat[10] ^ tenb_data[2]))) & (~ (rsync_comp_pat[11] ^ tenb_data[3]))) & (~ (rsync_comp_pat[12] ^ tenb_data[4]))) & (~ (rsync_comp_pat[13] ^ tenb_data[5]))) & (~ (rsync_comp_pat[14] ^ tenb_data[6]))) & (~ (rsync_comp_pat[15] ^ tenb_data[7]))),
		nl0l0iO = (((rrxfifo_urst_en & rxfifo_urst) & (nl0l0li2 ^ nl0l0li1)) | soft_reset),
		nl0l11l = (((((((~ ((~ rsync_comp_pat[0]) ^ tenb_data[0])) & (~ ((~ rsync_comp_pat[1]) ^ tenb_data[1]))) & (~ ((~ rsync_comp_pat[2]) ^ tenb_data[2]))) & (~ ((~ rsync_comp_pat[3]) ^ tenb_data[3]))) & (~ ((~ rsync_comp_pat[4]) ^ tenb_data[4]))) & (~ ((~ rsync_comp_pat[5]) ^ tenb_data[5]))) & (~ ((~ rsync_comp_pat[6]) ^ tenb_data[6]))),
		nl0l11O = (((((((~ (rsync_comp_pat[0] ^ tenb_data[0])) & (~ (rsync_comp_pat[1] ^ tenb_data[1]))) & (~ (rsync_comp_pat[2] ^ tenb_data[2]))) & (~ (rsync_comp_pat[3] ^ tenb_data[3]))) & (~ (rsync_comp_pat[4] ^ tenb_data[4]))) & (~ (rsync_comp_pat[5] ^ tenb_data[5]))) & (~ (rsync_comp_pat[6] ^ tenb_data[6]))),
		nl0l1OO = (((((((((((((((((((((((((((((((((((((((((((((wire_nll0i_o[63] | wire_nll0i_o[62]) | wire_nll0i_o[59]) | wire_nll0i_o[58]) | wire_nll0i_o[55]) | wire_nll0i_o[54]) | wire_nll0i_o[51]) | wire_nll0i_o[50]) | wire_nll0i_o[47]) | wire_nll0i_o[46]) | wire_nll0i_o[45]) | wire_nll0i_o[44]) | wire_nll0i_o[41]) | wire_nll0i_o[40]) | wire_nll0i_o[37]) | wire_nll0i_o[36]) | wire_nll0i_o[33]) | wire_nll0i_o[32]) | wire_nll0i_o[31]) | wire_nll0i_o[30]) | wire_nll0i_o[29]) | wire_nll0i_o[28]) | wire_nll0i_o[27]) | wire_nll0i_o[26]) | wire_nll0i_o[25]) | wire_nll0i_o[24]) | wire_nll0i_o[23]) | wire_nll0i_o[22]) | wire_nll0i_o[19]) | wire_nll0i_o[18]) | wire_nll0i_o[15]) | wire_nll0i_o[14]) | wire_nll0i_o[13]) | wire_nll0i_o[12]) | wire_nll0i_o[11]) | wire_nll0i_o[10]) | wire_nll0i_o[9]) | wire_nll0i_o[8]) | wire_nll0i_o[7]) | wire_nll0i_o[6]) | wire_nll0i_o[5]) | wire_nll0i_o[4]) | wire_nll0i_o[3]) | wire_nll0i_o[2]) | wire_nll0i_o[1]) | wire_nll0i_o[0]),
		ph_fifo_empty = nl0OlOl,
		ph_fifo_full = nl0OlOO,
		rd_enable2 = nlO0ll,
		rd_enable_out = nlOl0l,
		rptr_bin = {(~ (((wire_nl0lO1O_o[8] | wire_nl0lO1O_o[4]) | wire_nl0lO1O_o[2]) | wire_nl0lO1O_o[1])), (~ (((wire_nl0lO1O_o[32] | wire_nl0lO1O_o[16]) | wire_nl0lO1O_o[2]) | wire_nl0lO1O_o[1])), (~ (((wire_nl0lO1O_o[64] | wire_nl0lO1O_o[16]) | wire_nl0lO1O_o[4]) | wire_nl0lO1O_o[1]))},
		running_disp = {wire_nll_dataout, wire_nli_dataout},
		rx_we_out = n11OOl,
		rxc = {wire_n10l_dataout, wire_n10i_dataout, wire_n11O_dataout, wire_n11l_dataout},
		rxd = {wire_niO_dataout, wire_nil_dataout, wire_nii_dataout, wire_n0O_dataout, wire_n0l_dataout, wire_n0i_dataout, wire_n1O_dataout, wire_n1l_dataout, wire_n1i_dataout, wire_nlOO_dataout, wire_nlOl_dataout, wire_nlOi_dataout, wire_nllO_dataout, wire_nlll_dataout, wire_nlli_dataout, wire_nliO_dataout, wire_nlil_dataout, wire_nlii_dataout, wire_nl0O_dataout, wire_nl0l_dataout, wire_nl0i_dataout, wire_nl1O_dataout, wire_nl1l_dataout, wire_nl1i_dataout, wire_niOO_dataout, wire_niOl_dataout, wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout, wire_n0iO_dataout, wire_n0il_dataout, wire_n0ii_dataout, wire_n00O_dataout, wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout, wire_n1li_dataout, wire_n1iO_dataout, wire_n1il_dataout, wire_n1ii_dataout, wire_n10O_dataout},
		rxd_19 = {wire_nlOOl_dataout, wire_nlOOi_dataout},
		rxd_9 = {wire_n11i_dataout, wire_nlOOO_dataout},
		rxd_lpbk = {nl0Ol0i, nl0Ol1O, nl0Ol1l, nl0Ol1i, nl0OiOO, nl0OiOl, nl0OiOi, nl0OilO, nl0Oill, nl0Oili, nl0Oi1O, nl0Oi1l, nl0Oi1i, nl0O0OO, nl0O0Ol, nl0O0Oi, nl0O0lO, nl0O0ll, nl0O0li, nl0O0iO, nl0O01l, nl0O01i, nl0O1OO, nl0O1Ol, nl0O1Oi, nl0O1lO, nl0O1ll, nl0O1li, nl0O1iO, nl0O1il, nl0O11i, nl0lOOO, nl0lOOl, nl0lOOi, nl0lOlO, nl0lOll, nl0lOli, nl0lOiO, nl0lOil, nl0llOi},
		signal_detect_out = n1l1O,
		soft_reset_rclk1 = wire_nlOOOi_dataout,
		wptr_bin = {(~ (((wire_nl0lOii_o[8] | wire_nl0lOii_o[4]) | wire_nl0lOii_o[2]) | wire_nl0lOii_o[1])), (~ (((wire_nl0lOii_o[32] | wire_nl0lOii_o[16]) | wire_nl0lOii_o[2]) | wire_nl0lOii_o[1])), (~ (((wire_nl0lOii_o[64] | wire_nl0lOii_o[16]) | wire_nl0lOii_o[4]) | wire_nl0lOii_o[1]))},
		wr_enable2 = nlOliO,
		wr_enable_out = nlOlOl;
endmodule //arriagx_hssi_rx_ctrl
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 101 mux21 119 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_dec_chnl_top
	( 
	cascaded_8b10b_en,
	clk_2,
	data_in,
	data_in_valid,
	dec_crdchk_flags_sel,
	dec_ctl,
	dec_data,
	dec_data_valid,
	disp_err_delay,
	disp_val_delay,
	invalid_code_delay,
	ovr_undflow,
	polinv,
	r8b10b_dec_ibm_en,
	renpolinv,
	rlb_data,
	rst,
	sync_resync_delay,
	tenb_data) /* synthesis synthesis_clearbox=1 */;
	input   cascaded_8b10b_en;
	input   clk_2;
	input   [31:0]  data_in;
	input   [1:0]  data_in_valid;
	input   dec_crdchk_flags_sel;
	output   [1:0]  dec_ctl;
	output   [15:0]  dec_data;
	output   [1:0]  dec_data_valid;
	output   [1:0]  disp_err_delay;
	output   [1:0]  disp_val_delay;
	output   [1:0]  invalid_code_delay;
	output   [3:0]  ovr_undflow;
	input   polinv;
	input   [1:0]  r8b10b_dec_ibm_en;
	input   renpolinv;
	output   [19:0]  rlb_data;
	input   rst;
	output   [1:0]  sync_resync_delay;
	output   [19:0]  tenb_data;

	reg	n0lili45;
	reg	n0lili46;
	reg	n0liOl43;
	reg	n0liOl44;
	reg	n0ll0i41;
	reg	n0ll0i42;
	reg	n0ll0O39;
	reg	n0ll0O40;
	reg	n0llll37;
	reg	n0llll38;
	reg	n0llOl35;
	reg	n0llOl36;
	reg	n0lO1O33;
	reg	n0lO1O34;
	reg	n0lOii31;
	reg	n0lOii32;
	reg	n0lOli29;
	reg	n0lOli30;
	reg	n0lOOl27;
	reg	n0lOOl28;
	reg	n0O00l15;
	reg	n0O00l16;
	reg	n0O01i17;
	reg	n0O01i18;
	reg	n0O0iO13;
	reg	n0O0iO14;
	reg	n0O0Oi11;
	reg	n0O0Oi12;
	reg	n0O10l23;
	reg	n0O10l24;
	reg	n0O11i25;
	reg	n0O11i26;
	reg	n0O1li21;
	reg	n0O1li22;
	reg	n0O1lO19;
	reg	n0O1lO20;
	reg	n0Oi1i10;
	reg	n0Oi1i9;
	reg	n0Oiil7;
	reg	n0Oiil8;
	reg	n0Oili5;
	reg	n0Oili6;
	reg	n0Oill3;
	reg	n0Oill4;
	reg	n0OilO1;
	reg	n0OilO2;
	reg	n00i;
	reg	n00l;
	reg	n00O;
	reg	n01i;
	reg	n01l;
	reg	n01O;
	reg	n0OO;
	reg	n10i;
	reg	n10l;
	reg	n10O;
	reg	n11i;
	reg	n11l;
	reg	n11O;
	reg	n1ii;
	reg	n1il;
	reg	n1iO;
	reg	n1li;
	reg	n1ll;
	reg	n1lO;
	reg	n1Oi;
	reg	n1Ol;
	reg	n1OO;
	reg	ni0l;
	reg	ni0O;
	reg	ni1i;
	reg	niii;
	reg	niil;
	reg	niiO;
	reg	niOl;
	reg	niOO;
	reg	nl;
	reg	nl0i;
	reg	nl0l;
	reg	nl1i;
	reg	nl1l;
	reg	nl1O;
	reg	nlii;
	reg	nlO0O;
	reg	nlOii;
	reg	nlOil;
	reg	nlOiO;
	reg	nlOli;
	reg	nlOll;
	reg	nlOlO;
	reg	nlOOi;
	reg	nlOOl;
	reg	nlOOO;
	reg	ni_clk_prev;
	wire	wire_ni_CLRN;
	wire	wire_ni_PRN;
	reg	n0ii;
	reg	n0Ol;
	reg	ni0i;
	reg	ni1l;
	reg	ni1O;
	reg	nili;
	reg	nill;
	reg	niOi;
	wire	wire_nilO_PRN;
	wire	wire_n0i_dataout;
	wire	wire_n0i0i_dataout;
	wire	wire_n0i0l_dataout;
	wire	wire_n0i0O_dataout;
	wire	wire_n0i1i_dataout;
	wire	wire_n0i1l_dataout;
	wire	wire_n0i1O_dataout;
	wire	wire_n0iii_dataout;
	wire	wire_n0iil_dataout;
	wire	wire_n0iiO_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0ili_dataout;
	wire	wire_n0ill_dataout;
	wire	wire_n0ilO_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0iOi_dataout;
	wire	wire_n0iOl_dataout;
	wire	wire_n0iOO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0l0i_dataout;
	wire	wire_n0l0l_dataout;
	wire	wire_n0l1i_dataout;
	wire	wire_n0l1l_dataout;
	wire	wire_n0l1O_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0lii_dataout;
	wire	wire_n0lil_dataout;
	wire	wire_n0liO_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n100i_dataout;
	wire	wire_n100O_dataout;
	wire	wire_n101i_dataout;
	wire	wire_n101l_dataout;
	wire	wire_n101O_dataout;
	wire	wire_n10ii_dataout;
	wire	wire_n10il_dataout;
	wire	wire_n110i_dataout;
	wire	wire_n110l_dataout;
	wire	wire_n110O_dataout;
	wire	wire_n111i_dataout;
	wire	wire_n111l_dataout;
	wire	wire_n111O_dataout;
	wire	wire_n11ii_dataout;
	wire	wire_n11il_dataout;
	wire	wire_n11iO_dataout;
	wire	wire_n11li_dataout;
	wire	wire_n11ll_dataout;
	wire	wire_n11lO_dataout;
	wire	wire_n11Oi_dataout;
	wire	wire_n11Ol_dataout;
	wire	wire_n11OO_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1iOO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1l0i_dataout;
	wire	wire_n1l1i_dataout;
	wire	wire_n1l1l_dataout;
	wire	wire_n1l1O_dataout;
	wire	wire_n1liO_dataout;
	wire	wire_n1lli_dataout;
	wire	wire_n1lll_dataout;
	wire	wire_n1llO_dataout;
	wire	wire_n1lOi_dataout;
	wire	wire_n1lOl_dataout;
	wire	wire_n1lOO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1O0i_dataout;
	wire	wire_n1O0l_dataout;
	wire	wire_n1O1i_dataout;
	wire	wire_n1O1l_dataout;
	wire	wire_n1O1O_dataout;
	wire	wire_n1Oil_dataout;
	wire	wire_n1OiO_dataout;
	wire	wire_n1Oli_dataout;
	wire	wire_ni00i_dataout;
	wire	wire_ni00l_dataout;
	wire	wire_ni00O_dataout;
	wire	wire_ni01i_dataout;
	wire	wire_ni01l_dataout;
	wire	wire_ni01O_dataout;
	wire	wire_ni0iO_dataout;
	wire	wire_ni0li_dataout;
	wire	wire_ni0ll_dataout;
	wire	wire_ni10i_dataout;
	wire	wire_ni10l_dataout;
	wire	wire_ni11i_dataout;
	wire	wire_ni11l_dataout;
	wire	wire_ni11O_dataout;
	wire	wire_ni1i1i_dataout;
	wire	wire_ni1li_dataout;
	wire	wire_ni1ll_dataout;
	wire	wire_ni1lO_dataout;
	wire	wire_ni1Oi_dataout;
	wire	wire_ni1Ol_dataout;
	wire	wire_ni1OO_dataout;
	wire	wire_nii_dataout;
	wire	wire_nii10O_dataout;
	wire	wire_nil_dataout;
	wire	wire_niO_dataout;
	wire	wire_niOilO_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl10Oi_dataout;
	wire	wire_nli_dataout;
	wire	wire_nli11O_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOiiO_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOOOO_dataout;
	wire  n0i00i;
	wire  n0i00l;
	wire  n0i00O;
	wire  n0i01i;
	wire  n0i01l;
	wire  n0i01O;
	wire  n0i0ii;
	wire  n0i0il;
	wire  n0i0iO;
	wire  n0i0li;
	wire  n0i0ll;
	wire  n0i0lO;
	wire  n0i0Oi;
	wire  n0i0Ol;
	wire  n0i0OO;
	wire  n0ii0i;
	wire  n0ii0l;
	wire  n0ii0O;
	wire  n0ii1i;
	wire  n0ii1l;
	wire  n0ii1O;
	wire  n0iiii;
	wire  n0iiil;
	wire  n0iiiO;
	wire  n0iili;
	wire  n0iill;
	wire  n0iilO;
	wire  n0iiOi;
	wire  n0iiOl;
	wire  n0iiOO;
	wire  n0il0i;
	wire  n0il0l;
	wire  n0il0O;
	wire  n0il1i;
	wire  n0il1l;
	wire  n0il1O;
	wire  n0ilii;
	wire  n0ilil;
	wire  n0iliO;
	wire  n0illi;
	wire  n0illl;
	wire  n0illO;
	wire  n0ilOi;
	wire  n0ilOl;
	wire  n0ilOO;
	wire  n0iO0i;
	wire  n0iO0l;
	wire  n0iO0O;
	wire  n0iO1i;
	wire  n0iO1l;
	wire  n0iO1O;
	wire  n0iOii;
	wire  n0iOil;
	wire  n0iOiO;
	wire  n0iOli;
	wire  n0iOll;
	wire  n0iOlO;
	wire  n0iOOi;
	wire  n0iOOl;
	wire  n0iOOO;
	wire  n0l00i;
	wire  n0l00l;
	wire  n0l00O;
	wire  n0l01i;
	wire  n0l01l;
	wire  n0l01O;
	wire  n0l0ii;
	wire  n0l0il;
	wire  n0l0iO;
	wire  n0l0li;
	wire  n0l0ll;
	wire  n0l0lO;
	wire  n0l0Oi;
	wire  n0l0Ol;
	wire  n0l0OO;
	wire  n0l10i;
	wire  n0l10l;
	wire  n0l10O;
	wire  n0l11i;
	wire  n0l11l;
	wire  n0l11O;
	wire  n0l1ii;
	wire  n0l1il;
	wire  n0l1iO;
	wire  n0l1li;
	wire  n0l1ll;
	wire  n0l1lO;
	wire  n0l1Oi;
	wire  n0l1Ol;
	wire  n0l1OO;
	wire  n0li0i;
	wire  n0li0l;
	wire  n0li0O;
	wire  n0li1i;
	wire  n0li1l;
	wire  n0li1O;
	wire  n0liii;
	wire  n0liil;
	wire  n0liiO;
	wire  n0lilO;
	wire  n0liOi;
	wire  n0ll1i;
	wire  n0ll1l;
	wire  n0ll1O;
	wire  n0llil;
	wire  n0lliO;
	wire  n0llli;
	wire  n0llOi;
	wire  n0lO0l;
	wire  n0lO0O;
	wire  n0lO1i;
	wire  n0lO1l;
	wire  n0lOiO;
	wire  n0lOlO;
	wire  n0lOOi;
	wire  n0O00i;
	wire  n0O01O;
	wire  n0O0ii;
	wire  n0O0il;
	wire  n0O0ll;
	wire  n0O0lO;
	wire  n0O0OO;
	wire  n0O10i;
	wire  n0O11O;
	wire  n0O1ii;
	wire  n0O1il;
	wire  n0O1iO;
	wire  n0O1Ol;
	wire  n0O1OO;
	wire  n0Oi0i;
	wire  n0Oi0l;
	wire  n0Oi0O;
	wire  n0Oi1O;
	wire  n0Oiii;
	wire  n0OiiO;

	initial
		n0lili45 = 0;
	always @ ( posedge clk_2)
		  n0lili45 <= n0lili46;
	event n0lili45_event;
	initial
		#1 ->n0lili45_event;
	always @(n0lili45_event)
		n0lili45 <= {1{1'b1}};
	initial
		n0lili46 = 0;
	always @ ( posedge clk_2)
		  n0lili46 <= n0lili45;
	initial
		n0liOl43 = 0;
	always @ ( posedge clk_2)
		  n0liOl43 <= n0liOl44;
	event n0liOl43_event;
	initial
		#1 ->n0liOl43_event;
	always @(n0liOl43_event)
		n0liOl43 <= {1{1'b1}};
	initial
		n0liOl44 = 0;
	always @ ( posedge clk_2)
		  n0liOl44 <= n0liOl43;
	initial
		n0ll0i41 = 0;
	always @ ( posedge clk_2)
		  n0ll0i41 <= n0ll0i42;
	event n0ll0i41_event;
	initial
		#1 ->n0ll0i41_event;
	always @(n0ll0i41_event)
		n0ll0i41 <= {1{1'b1}};
	initial
		n0ll0i42 = 0;
	always @ ( posedge clk_2)
		  n0ll0i42 <= n0ll0i41;
	initial
		n0ll0O39 = 0;
	always @ ( posedge clk_2)
		  n0ll0O39 <= n0ll0O40;
	event n0ll0O39_event;
	initial
		#1 ->n0ll0O39_event;
	always @(n0ll0O39_event)
		n0ll0O39 <= {1{1'b1}};
	initial
		n0ll0O40 = 0;
	always @ ( posedge clk_2)
		  n0ll0O40 <= n0ll0O39;
	initial
		n0llll37 = 0;
	always @ ( posedge clk_2)
		  n0llll37 <= n0llll38;
	event n0llll37_event;
	initial
		#1 ->n0llll37_event;
	always @(n0llll37_event)
		n0llll37 <= {1{1'b1}};
	initial
		n0llll38 = 0;
	always @ ( posedge clk_2)
		  n0llll38 <= n0llll37;
	initial
		n0llOl35 = 0;
	always @ ( posedge clk_2)
		  n0llOl35 <= n0llOl36;
	event n0llOl35_event;
	initial
		#1 ->n0llOl35_event;
	always @(n0llOl35_event)
		n0llOl35 <= {1{1'b1}};
	initial
		n0llOl36 = 0;
	always @ ( posedge clk_2)
		  n0llOl36 <= n0llOl35;
	initial
		n0lO1O33 = 0;
	always @ ( posedge clk_2)
		  n0lO1O33 <= n0lO1O34;
	event n0lO1O33_event;
	initial
		#1 ->n0lO1O33_event;
	always @(n0lO1O33_event)
		n0lO1O33 <= {1{1'b1}};
	initial
		n0lO1O34 = 0;
	always @ ( posedge clk_2)
		  n0lO1O34 <= n0lO1O33;
	initial
		n0lOii31 = 0;
	always @ ( posedge clk_2)
		  n0lOii31 <= n0lOii32;
	event n0lOii31_event;
	initial
		#1 ->n0lOii31_event;
	always @(n0lOii31_event)
		n0lOii31 <= {1{1'b1}};
	initial
		n0lOii32 = 0;
	always @ ( posedge clk_2)
		  n0lOii32 <= n0lOii31;
	initial
		n0lOli29 = 0;
	always @ ( posedge clk_2)
		  n0lOli29 <= n0lOli30;
	event n0lOli29_event;
	initial
		#1 ->n0lOli29_event;
	always @(n0lOli29_event)
		n0lOli29 <= {1{1'b1}};
	initial
		n0lOli30 = 0;
	always @ ( posedge clk_2)
		  n0lOli30 <= n0lOli29;
	initial
		n0lOOl27 = 0;
	always @ ( posedge clk_2)
		  n0lOOl27 <= n0lOOl28;
	event n0lOOl27_event;
	initial
		#1 ->n0lOOl27_event;
	always @(n0lOOl27_event)
		n0lOOl27 <= {1{1'b1}};
	initial
		n0lOOl28 = 0;
	always @ ( posedge clk_2)
		  n0lOOl28 <= n0lOOl27;
	initial
		n0O00l15 = 0;
	always @ ( posedge clk_2)
		  n0O00l15 <= n0O00l16;
	event n0O00l15_event;
	initial
		#1 ->n0O00l15_event;
	always @(n0O00l15_event)
		n0O00l15 <= {1{1'b1}};
	initial
		n0O00l16 = 0;
	always @ ( posedge clk_2)
		  n0O00l16 <= n0O00l15;
	initial
		n0O01i17 = 0;
	always @ ( posedge clk_2)
		  n0O01i17 <= n0O01i18;
	event n0O01i17_event;
	initial
		#1 ->n0O01i17_event;
	always @(n0O01i17_event)
		n0O01i17 <= {1{1'b1}};
	initial
		n0O01i18 = 0;
	always @ ( posedge clk_2)
		  n0O01i18 <= n0O01i17;
	initial
		n0O0iO13 = 0;
	always @ ( posedge clk_2)
		  n0O0iO13 <= n0O0iO14;
	event n0O0iO13_event;
	initial
		#1 ->n0O0iO13_event;
	always @(n0O0iO13_event)
		n0O0iO13 <= {1{1'b1}};
	initial
		n0O0iO14 = 0;
	always @ ( posedge clk_2)
		  n0O0iO14 <= n0O0iO13;
	initial
		n0O0Oi11 = 0;
	always @ ( posedge clk_2)
		  n0O0Oi11 <= n0O0Oi12;
	event n0O0Oi11_event;
	initial
		#1 ->n0O0Oi11_event;
	always @(n0O0Oi11_event)
		n0O0Oi11 <= {1{1'b1}};
	initial
		n0O0Oi12 = 0;
	always @ ( posedge clk_2)
		  n0O0Oi12 <= n0O0Oi11;
	initial
		n0O10l23 = 0;
	always @ ( posedge clk_2)
		  n0O10l23 <= n0O10l24;
	event n0O10l23_event;
	initial
		#1 ->n0O10l23_event;
	always @(n0O10l23_event)
		n0O10l23 <= {1{1'b1}};
	initial
		n0O10l24 = 0;
	always @ ( posedge clk_2)
		  n0O10l24 <= n0O10l23;
	initial
		n0O11i25 = 0;
	always @ ( posedge clk_2)
		  n0O11i25 <= n0O11i26;
	event n0O11i25_event;
	initial
		#1 ->n0O11i25_event;
	always @(n0O11i25_event)
		n0O11i25 <= {1{1'b1}};
	initial
		n0O11i26 = 0;
	always @ ( posedge clk_2)
		  n0O11i26 <= n0O11i25;
	initial
		n0O1li21 = 0;
	always @ ( posedge clk_2)
		  n0O1li21 <= n0O1li22;
	event n0O1li21_event;
	initial
		#1 ->n0O1li21_event;
	always @(n0O1li21_event)
		n0O1li21 <= {1{1'b1}};
	initial
		n0O1li22 = 0;
	always @ ( posedge clk_2)
		  n0O1li22 <= n0O1li21;
	initial
		n0O1lO19 = 0;
	always @ ( posedge clk_2)
		  n0O1lO19 <= n0O1lO20;
	event n0O1lO19_event;
	initial
		#1 ->n0O1lO19_event;
	always @(n0O1lO19_event)
		n0O1lO19 <= {1{1'b1}};
	initial
		n0O1lO20 = 0;
	always @ ( posedge clk_2)
		  n0O1lO20 <= n0O1lO19;
	initial
		n0Oi1i10 = 0;
	always @ ( posedge clk_2)
		  n0Oi1i10 <= n0Oi1i9;
	initial
		n0Oi1i9 = 0;
	always @ ( posedge clk_2)
		  n0Oi1i9 <= n0Oi1i10;
	event n0Oi1i9_event;
	initial
		#1 ->n0Oi1i9_event;
	always @(n0Oi1i9_event)
		n0Oi1i9 <= {1{1'b1}};
	initial
		n0Oiil7 = 0;
	always @ ( posedge clk_2)
		  n0Oiil7 <= n0Oiil8;
	event n0Oiil7_event;
	initial
		#1 ->n0Oiil7_event;
	always @(n0Oiil7_event)
		n0Oiil7 <= {1{1'b1}};
	initial
		n0Oiil8 = 0;
	always @ ( posedge clk_2)
		  n0Oiil8 <= n0Oiil7;
	initial
		n0Oili5 = 0;
	always @ ( posedge clk_2)
		  n0Oili5 <= n0Oili6;
	event n0Oili5_event;
	initial
		#1 ->n0Oili5_event;
	always @(n0Oili5_event)
		n0Oili5 <= {1{1'b1}};
	initial
		n0Oili6 = 0;
	always @ ( posedge clk_2)
		  n0Oili6 <= n0Oili5;
	initial
		n0Oill3 = 0;
	always @ ( posedge clk_2)
		  n0Oill3 <= n0Oill4;
	event n0Oill3_event;
	initial
		#1 ->n0Oill3_event;
	always @(n0Oill3_event)
		n0Oill3 <= {1{1'b1}};
	initial
		n0Oill4 = 0;
	always @ ( posedge clk_2)
		  n0Oill4 <= n0Oill3;
	initial
		n0OilO1 = 0;
	always @ ( posedge clk_2)
		  n0OilO1 <= n0OilO2;
	event n0OilO1_event;
	initial
		#1 ->n0OilO1_event;
	always @(n0OilO1_event)
		n0OilO1 <= {1{1'b1}};
	initial
		n0OilO2 = 0;
	always @ ( posedge clk_2)
		  n0OilO2 <= n0OilO1;
	initial
	begin
		n00i = 0;
		n00l = 0;
		n00O = 0;
		n01i = 0;
		n01l = 0;
		n01O = 0;
		n0OO = 0;
		n10i = 0;
		n10l = 0;
		n10O = 0;
		n11i = 0;
		n11l = 0;
		n11O = 0;
		n1ii = 0;
		n1il = 0;
		n1iO = 0;
		n1li = 0;
		n1ll = 0;
		n1lO = 0;
		n1Oi = 0;
		n1Ol = 0;
		n1OO = 0;
		ni0l = 0;
		ni0O = 0;
		ni1i = 0;
		niii = 0;
		niil = 0;
		niiO = 0;
		niOl = 0;
		niOO = 0;
		nl = 0;
		nl0i = 0;
		nl0l = 0;
		nl1i = 0;
		nl1l = 0;
		nl1O = 0;
		nlii = 0;
		nlO0O = 0;
		nlOii = 0;
		nlOil = 0;
		nlOiO = 0;
		nlOli = 0;
		nlOll = 0;
		nlOlO = 0;
		nlOOi = 0;
		nlOOl = 0;
		nlOOO = 0;
	end
	always @ (clk_2 or wire_ni_PRN or wire_ni_CLRN)
	begin
		if (wire_ni_PRN == 1'b0) 
		begin
			n00i <= 1;
			n00l <= 1;
			n00O <= 1;
			n01i <= 1;
			n01l <= 1;
			n01O <= 1;
			n0OO <= 1;
			n10i <= 1;
			n10l <= 1;
			n10O <= 1;
			n11i <= 1;
			n11l <= 1;
			n11O <= 1;
			n1ii <= 1;
			n1il <= 1;
			n1iO <= 1;
			n1li <= 1;
			n1ll <= 1;
			n1lO <= 1;
			n1Oi <= 1;
			n1Ol <= 1;
			n1OO <= 1;
			ni0l <= 1;
			ni0O <= 1;
			ni1i <= 1;
			niii <= 1;
			niil <= 1;
			niiO <= 1;
			niOl <= 1;
			niOO <= 1;
			nl <= 1;
			nl0i <= 1;
			nl0l <= 1;
			nl1i <= 1;
			nl1l <= 1;
			nl1O <= 1;
			nlii <= 1;
			nlO0O <= 1;
			nlOii <= 1;
			nlOil <= 1;
			nlOiO <= 1;
			nlOli <= 1;
			nlOll <= 1;
			nlOlO <= 1;
			nlOOi <= 1;
			nlOOl <= 1;
			nlOOO <= 1;
		end
		else if  (wire_ni_CLRN == 1'b0) 
		begin
			n00i <= 0;
			n00l <= 0;
			n00O <= 0;
			n01i <= 0;
			n01l <= 0;
			n01O <= 0;
			n0OO <= 0;
			n10i <= 0;
			n10l <= 0;
			n10O <= 0;
			n11i <= 0;
			n11l <= 0;
			n11O <= 0;
			n1ii <= 0;
			n1il <= 0;
			n1iO <= 0;
			n1li <= 0;
			n1ll <= 0;
			n1lO <= 0;
			n1Oi <= 0;
			n1Ol <= 0;
			n1OO <= 0;
			ni0l <= 0;
			ni0O <= 0;
			ni1i <= 0;
			niii <= 0;
			niil <= 0;
			niiO <= 0;
			niOl <= 0;
			niOO <= 0;
			nl <= 0;
			nl0i <= 0;
			nl0l <= 0;
			nl1i <= 0;
			nl1l <= 0;
			nl1O <= 0;
			nlii <= 0;
			nlO0O <= 0;
			nlOii <= 0;
			nlOil <= 0;
			nlOiO <= 0;
			nlOli <= 0;
			nlOll <= 0;
			nlOlO <= 0;
			nlOOi <= 0;
			nlOOl <= 0;
			nlOOO <= 0;
		end
		else 
		if (clk_2 != ni_clk_prev && clk_2 == 1'b1) 
		begin
			n00i <= wire_n0li_dataout;
			n00l <= wire_n0Oi_dataout;
			n00O <= wire_n0lO_dataout;
			n01i <= wire_n0iO_dataout;
			n01l <= wire_n0il_dataout;
			n01O <= wire_n0ll_dataout;
			n0OO <= data_in_valid[0];
			n10i <= data_in[20];
			n10l <= data_in[21];
			n10O <= data_in[22];
			n11i <= data_in[17];
			n11l <= data_in[18];
			n11O <= data_in[19];
			n1ii <= data_in[23];
			n1il <= data_in[24];
			n1iO <= data_in[25];
			n1li <= data_in[14];
			n1ll <= data_in[15];
			n1lO <= data_in[30];
			n1Oi <= data_in[31];
			n1Ol <= data_in[11];
			n1OO <= data_in[27];
			ni0l <= wire_n111i_dataout;
			ni0O <= wire_nlOOOO_dataout;
			ni1i <= data_in_valid[1];
			niii <= wire_n1lll_dataout;
			niil <= wire_n1lli_dataout;
			niiO <= wire_n1liO_dataout;
			niOl <= wire_n0i1l_dataout;
			niOO <= wire_n0i1i_dataout;
			nl <= ((renpolinv & polinv) & (n0OilO2 ^ n0OilO1));
			nl0i <= wire_nl0O_dataout;
			nl0l <= nl;
			nl1i <= wire_ni1lO_dataout;
			nl1l <= wire_ni1ll_dataout;
			nl1O <= wire_ni1li_dataout;
			nlii <= data_in[0];
			nlO0O <= data_in[1];
			nlOii <= data_in[2];
			nlOil <= data_in[3];
			nlOiO <= data_in[4];
			nlOli <= data_in[5];
			nlOll <= data_in[6];
			nlOlO <= data_in[7];
			nlOOi <= data_in[8];
			nlOOl <= data_in[9];
			nlOOO <= data_in[16];
		end
		ni_clk_prev <= clk_2;
	end
	assign
		wire_ni_CLRN = ((n0Oill4 ^ n0Oill3) & (~ rst)),
		wire_ni_PRN = (n0Oili6 ^ n0Oili5);
	initial
	begin
		n0ii = 0;
		n0Ol = 0;
		ni0i = 0;
		ni1l = 0;
		ni1O = 0;
		nili = 0;
		nill = 0;
		niOi = 0;
	end
	always @ ( posedge clk_2 or  negedge wire_nilO_PRN)
	begin
		if (wire_nilO_PRN == 1'b0) 
		begin
			n0ii <= 1;
			n0Ol <= 1;
			ni0i <= 1;
			ni1l <= 1;
			ni1O <= 1;
			nili <= 1;
			nill <= 1;
			niOi <= 1;
		end
		else 
		begin
			n0ii <= (n0liiO | (n0liil & n0liii));
			n0Ol <= (n0Oiii | (n0Oi0O & n0Oi0l));
			ni0i <= wire_n111l_dataout;
			ni1l <= wire_n110i_dataout;
			ni1O <= wire_n111O_dataout;
			nili <= wire_n0i0l_dataout;
			nill <= wire_n0i0i_dataout;
			niOi <= wire_n0i1O_dataout;
		end
	end
	assign
		wire_nilO_PRN = ((n0Oiil8 ^ n0Oiil7) & (~ rst));
	assign		wire_n0i_dataout = (nl0l === 1'b1) ? (~ data_in[1]) : data_in[1];
	and(wire_n0i0i_dataout, wire_n0iiO_dataout, ~(n0Oiii));
	and(wire_n0i0l_dataout, wire_n0ili_dataout, ~(n0Oiii));
	or(wire_n0i0O_dataout, wire_n0ill_dataout, n0li1O);
	or(wire_n0i1i_dataout, wire_n0i0O_dataout, n0Oiii);
	or(wire_n0i1l_dataout, wire_n0iii_dataout, n0Oiii);
	or(wire_n0i1O_dataout, wire_n0iil_dataout, n0Oiii);
	or(wire_n0iii_dataout, wire_n0ilO_dataout, n0li1O);
	and(wire_n0iil_dataout, wire_n0iOi_dataout, ~(n0li1O));
	and(wire_n0iiO_dataout, wire_n0iOl_dataout, ~(n0li1O));
	assign		wire_n0il_dataout = (renpolinv === 1'b1) ? wire_nli11O_dataout : data_in[29];
	and(wire_n0ili_dataout, wire_n0iOO_dataout, ~(n0li1O));
	assign		wire_n0ill_dataout = (n0li1l === 1'b1) ? wire_n0lii_dataout : wire_n0l1i_dataout;
	assign		wire_n0ilO_dataout = (n0li1l === 1'b1) ? wire_n0lil_dataout : wire_n0l1l_dataout;
	assign		wire_n0iO_dataout = (renpolinv === 1'b1) ? wire_nii10O_dataout : data_in[13];
	assign		wire_n0iOi_dataout = (n0li1l === 1'b1) ? wire_n0lil_dataout : wire_n0l1O_dataout;
	assign		wire_n0iOl_dataout = (n0li1l === 1'b1) ? wire_n0lil_dataout : wire_n0l0i_dataout;
	assign		wire_n0iOO_dataout = (n0li1l === 1'b1) ? wire_n0lil_dataout : wire_n0l0l_dataout;
	assign		wire_n0l_dataout = (nl0l === 1'b1) ? (~ data_in[2]) : data_in[2];
	assign		wire_n0l0i_dataout = (n0l0Oi === 1'b1) ? wire_nliO_dataout : (~ wire_ni10i_dataout);
	assign		wire_n0l0l_dataout = (n0l0Oi === 1'b1) ? wire_nlil_dataout : (~ wire_ni10l_dataout);
	assign		wire_n0l1i_dataout = (n0l0Oi === 1'b1) ? wire_nllO_dataout : n0Oi0O;
	assign		wire_n0l1l_dataout = (n0l0Oi === 1'b1) ? wire_nlll_dataout : (~ wire_ni11l_dataout);
	assign		wire_n0l1O_dataout = (n0l0Oi === 1'b1) ? wire_nlli_dataout : (~ wire_ni11O_dataout);
	assign		wire_n0li_dataout = (renpolinv === 1'b1) ? ((((((~ wire_nii10O_dataout) & (((((((((n0lOOi | n0lOlO) | (~ (n0lOli30 ^ n0lOli29))) | n0lOiO) | (~ (n0lOii32 ^ n0lOii31))) | ((n0lO0O & n0lO0l) & (n0lO1O34 ^ n0lO1O33))) | ((n0lO1l & n0lO1i) & (n0llOl36 ^ n0llOl35))) | n0llOi) | (~ (n0llll38 ^ n0llll37))) | n0llli)) | (wire_nii10O_dataout & (n0lliO | (((~ wire_nlll_dataout) & n0llil) & (n0ll0O40 ^ n0ll0O39))))) | (~ (n0ll0i42 ^ n0ll0i41))) | ((n0ll1O | ((n0ll1l | n0ll1i) | (~ (n0liOl44 ^ n0liOl43)))) & (~ wire_nl10Oi_dataout))) | ((n0liOi | ((wire_nlOO_dataout & (wire_nlOl_dataout & n0lilO)) & (n0lili46 ^ n0lili45))) & wire_nl10Oi_dataout)) : data_in[28];
	and(wire_n0lii_dataout, wire_n0liO_dataout, ~(n0l0lO));
	and(wire_n0lil_dataout, (~ n0l0ll), ~(n0l0lO));
	or(wire_n0liO_dataout, (~ (wire_ni10i_dataout & (~ wire_ni11O_dataout))), n0l0ll);
	assign		wire_n0ll_dataout = (renpolinv === 1'b1) ? ((((((((~ nl0i) & ((((((((n0Oi0i | n0Oi1O) | (~ (n0Oi1i10 ^ n0Oi1i9))) | n0O0OO) | (~ (n0O0Oi12 ^ n0O0Oi11))) | ((n0O0lO & n0O0ll) & (n0O0iO14 ^ n0O0iO13))) | ((n0O0il & n0O0ii) & (n0O00l16 ^ n0O00l15))) | n0O00i) | n0O01O)) & (n0O01i18 ^ n0O01i17)) | ((nl0i & (n0O1OO | ((~ wire_n0O_dataout) & n0O1Ol))) & (n0O1lO20 ^ n0O1lO19))) | (~ (n0O1li22 ^ n0O1li21))) | ((n0O1iO | (n0O1il | n0O1ii)) & (~ wire_ni1i1i_dataout))) | (~ (n0O10l24 ^ n0O10l23))) | (((n0O10i | (wire_nli_dataout & ((wire_niO_dataout & n0O11O) & (n0O11i26 ^ n0O11i25)))) & wire_ni1i1i_dataout) & (n0lOOl28 ^ n0lOOl27))) : data_in[12];
	assign		wire_n0lO_dataout = (renpolinv === 1'b1) ? (~ wire_nlOiiO_dataout) : data_in[26];
	assign		wire_n0O_dataout = (nl0l === 1'b1) ? (~ data_in[3]) : data_in[3];
	assign		wire_n0Oi_dataout = (renpolinv === 1'b1) ? (~ wire_niOilO_dataout) : data_in[10];
	assign		wire_n100i_dataout = (n0l01i === 1'b1) ? wire_n1O_dataout : (~ wire_n1l0i_dataout);
	and(wire_n100O_dataout, wire_n10il_dataout, ~(n0l1OO));
	assign		wire_n101i_dataout = (n0l01i === 1'b1) ? wire_n0O_dataout : (~ wire_n1l1i_dataout);
	assign		wire_n101l_dataout = (n0l01i === 1'b1) ? wire_n0l_dataout : (~ wire_n1l1l_dataout);
	assign		wire_n101O_dataout = (n0l01i === 1'b1) ? wire_n0i_dataout : (~ wire_n1l1O_dataout);
	and(wire_n10ii_dataout, (~ n0l1Ol), ~(n0l1OO));
	or(wire_n10il_dataout, (~ (wire_n1l1O_dataout & (~ wire_n1l1l_dataout))), n0l1Ol);
	and(wire_n110i_dataout, wire_n11iO_dataout, ~(n0liiO));
	or(wire_n110l_dataout, wire_n11li_dataout, n0l00O);
	or(wire_n110O_dataout, wire_n11ll_dataout, n0l00O);
	or(wire_n111i_dataout, wire_n110O_dataout, n0liiO);
	or(wire_n111l_dataout, wire_n11ii_dataout, n0liiO);
	and(wire_n111O_dataout, wire_n11il_dataout, ~(n0liiO));
	and(wire_n11ii_dataout, wire_n11lO_dataout, ~(n0l00O));
	and(wire_n11il_dataout, wire_n11Oi_dataout, ~(n0l00O));
	and(wire_n11iO_dataout, wire_n11Ol_dataout, ~(n0l00O));
	assign		wire_n11li_dataout = (n0l00l === 1'b1) ? wire_n100O_dataout : wire_n11OO_dataout;
	assign		wire_n11ll_dataout = (n0l00l === 1'b1) ? wire_n10ii_dataout : wire_n101i_dataout;
	assign		wire_n11lO_dataout = (n0l00l === 1'b1) ? wire_n10ii_dataout : wire_n101l_dataout;
	assign		wire_n11Oi_dataout = (n0l00l === 1'b1) ? wire_n10ii_dataout : wire_n101O_dataout;
	assign		wire_n11Ol_dataout = (n0l00l === 1'b1) ? wire_n10ii_dataout : wire_n100i_dataout;
	assign		wire_n11OO_dataout = (n0l01i === 1'b1) ? wire_nii_dataout : n0liil;
	assign		wire_n1i_dataout = (nl0l === 1'b1) ? (~ data_in[24]) : data_in[24];
	assign		wire_n1iOO_dataout = (wire_nil_dataout === 1'b1) ? wire_nii_dataout : (~ wire_nii_dataout);
	assign		wire_n1l_dataout = (nl0l === 1'b1) ? (~ data_in[25]) : data_in[25];
	assign		wire_n1l0i_dataout = (wire_nil_dataout === 1'b1) ? wire_n1O_dataout : (~ wire_n1O_dataout);
	assign		wire_n1l1i_dataout = (wire_nil_dataout === 1'b1) ? wire_n0O_dataout : (~ wire_n0O_dataout);
	assign		wire_n1l1l_dataout = (wire_nil_dataout === 1'b1) ? wire_n0l_dataout : (~ wire_n0l_dataout);
	assign		wire_n1l1O_dataout = (wire_nil_dataout === 1'b1) ? wire_n0i_dataout : (~ wire_n0i_dataout);
	and(wire_n1liO_dataout, wire_n1llO_dataout, ~(n0l0ii));
	and(wire_n1lli_dataout, wire_n1lOi_dataout, ~(n0l0ii));
	and(wire_n1lll_dataout, wire_n1lOl_dataout, ~(n0l0ii));
	or(wire_n1llO_dataout, wire_n1lOO_dataout, n0liii);
	or(wire_n1lOi_dataout, wire_n1O1i_dataout, n0liii);
	or(wire_n1lOl_dataout, wire_n1O1l_dataout, n0liii);
	assign		wire_n1lOO_dataout = ((~ n0l0iO) === 1'b1) ? wire_n1Oil_dataout : wire_n1O1O_dataout;
	assign		wire_n1O_dataout = (nl0l === 1'b1) ? (~ data_in[0]) : data_in[0];
	assign		wire_n1O0i_dataout = (n0l0il === 1'b1) ? (~ wire_nli_dataout) : wire_nli_dataout;
	assign		wire_n1O0l_dataout = (n0l0il === 1'b1) ? (~ wire_niO_dataout) : wire_niO_dataout;
	assign		wire_n1O1i_dataout = ((~ n0l0iO) === 1'b1) ? wire_n1OiO_dataout : wire_n1O0i_dataout;
	assign		wire_n1O1l_dataout = ((~ n0l0iO) === 1'b1) ? wire_n1Oli_dataout : wire_n1O0l_dataout;
	assign		wire_n1O1O_dataout = (n0l0il === 1'b1) ? (~ wire_nll_dataout) : wire_nll_dataout;
	assign		wire_n1Oil_dataout = (wire_nlO_dataout === 1'b1) ? (~ wire_nll_dataout) : wire_nll_dataout;
	assign		wire_n1OiO_dataout = (wire_nlO_dataout === 1'b1) ? (~ wire_nli_dataout) : wire_nli_dataout;
	assign		wire_n1Oli_dataout = (wire_nlO_dataout === 1'b1) ? (~ wire_niO_dataout) : wire_niO_dataout;
	assign		wire_ni00i_dataout = (n0li0l === 1'b1) ? (~ wire_n1i_dataout) : wire_n1i_dataout;
	assign		wire_ni00l_dataout = (n0li0l === 1'b1) ? (~ wire_nlOO_dataout) : wire_nlOO_dataout;
	assign		wire_ni00O_dataout = (n0li0l === 1'b1) ? (~ wire_nlOl_dataout) : wire_nlOl_dataout;
	assign		wire_ni01i_dataout = ((~ n0li0O) === 1'b1) ? wire_ni0iO_dataout : wire_ni00i_dataout;
	assign		wire_ni01l_dataout = ((~ n0li0O) === 1'b1) ? wire_ni0li_dataout : wire_ni00l_dataout;
	assign		wire_ni01O_dataout = ((~ n0li0O) === 1'b1) ? wire_ni0ll_dataout : wire_ni00O_dataout;
	assign		wire_ni0iO_dataout = (wire_n1l_dataout === 1'b1) ? (~ wire_n1i_dataout) : wire_n1i_dataout;
	assign		wire_ni0li_dataout = (wire_n1l_dataout === 1'b1) ? (~ wire_nlOO_dataout) : wire_nlOO_dataout;
	assign		wire_ni0ll_dataout = (wire_n1l_dataout === 1'b1) ? (~ wire_nlOl_dataout) : wire_nlOl_dataout;
	assign		wire_ni10i_dataout = (wire_nlOi_dataout === 1'b1) ? wire_nliO_dataout : (~ wire_nliO_dataout);
	assign		wire_ni10l_dataout = (wire_nlOi_dataout === 1'b1) ? wire_nlil_dataout : (~ wire_nlil_dataout);
	assign		wire_ni11i_dataout = (wire_nlOi_dataout === 1'b1) ? wire_nllO_dataout : (~ wire_nllO_dataout);
	assign		wire_ni11l_dataout = (wire_nlOi_dataout === 1'b1) ? wire_nlll_dataout : (~ wire_nlll_dataout);
	assign		wire_ni11O_dataout = (wire_nlOi_dataout === 1'b1) ? wire_nlli_dataout : (~ wire_nlli_dataout);
	assign		wire_ni1i1i_dataout = (((((~ wire_n0O_dataout) & n0i00l) | (wire_n0O_dataout & n0O1Ol)) | (n0O0lO & n0O0ii)) === 1'b1) ? nl0i : (n0O1OO | n0O01O);
	and(wire_ni1li_dataout, wire_ni1Oi_dataout, ~(n0li0i));
	and(wire_ni1ll_dataout, wire_ni1Ol_dataout, ~(n0li0i));
	and(wire_ni1lO_dataout, wire_ni1OO_dataout, ~(n0li0i));
	or(wire_ni1Oi_dataout, wire_ni01i_dataout, n0Oi0l);
	or(wire_ni1Ol_dataout, wire_ni01l_dataout, n0Oi0l);
	or(wire_ni1OO_dataout, wire_ni01O_dataout, n0Oi0l);
	assign		wire_nii_dataout = (nl0l === 1'b1) ? (~ data_in[4]) : data_in[4];
	assign		wire_nii10O_dataout = (((wire_nli_dataout ^ wire_niO_dataout) & n0O11O) === 1'b1) ? wire_ni1i1i_dataout : (n0O10i | n0O1iO);
	assign		wire_nil_dataout = (nl0l === 1'b1) ? (~ data_in[5]) : data_in[5];
	assign		wire_niO_dataout = (nl0l === 1'b1) ? (~ data_in[6]) : data_in[6];
	assign		wire_niOilO_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ ((n0iili | (n0iiiO | n0iiil)) | (n0O00i | (n0Oi1O | (n0Oi0i | n0O0OO))))) & (~ (((n0iiii | n0O1ii) | ((~ (((n0ii0O | n0ii0l) | (wire_nil_dataout & ((~ wire_nii_dataout) & n0O0il))) | ((~ wire_nil_dataout) & (wire_nii_dataout & n0ii0i)))) & ((~ n0ii1O) & (((~ wire_niO_dataout) & n0ii1l) | (wire_niO_dataout & n0O1il))))) | ((((~ wire_nlO_dataout) & n0ii1l) | (wire_nlO_dataout & n0O1il)) & (n0ii0l | (n0ii0O | n0ii1O)))))) : (~ ((((((((((((((n0il0O | n0il0l) | ((~ wire_nil_dataout) & ((~ wire_nii_dataout) & n0il0i))) | (wire_nil_dataout & (wire_nii_dataout & n0il1O))) | ((wire_nlO_dataout & (wire_nll_dataout & (wire_nli_dataout & wire_niO_dataout))) | ((~ wire_nlO_dataout) & ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & (~ wire_niO_dataout)))))) | ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & ((~ wire_nil_dataout) & (~ wire_nii_dataout)))))) | (wire_nll_dataout & (wire_nli_dataout & (wire_niO_dataout & (wire_nil_dataout & wire_nii_dataout))))) | ((~ wire_nlO_dataout) & ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & n0il1l)))) | (wire_nlO_dataout & (wire_nll_dataout & (wire_nli_dataout & n0il1i)))) | ((((~ wire_nlO_dataout) & ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & wire_nil_dataout))) | (wire_nlO_dataout & (wire_nll_dataout & (wire_nli_dataout & (~ wire_nil_dataout))))) & (~ n0iiOO))) | (n0iiOO & ((wire_nll_dataout & n0iiOl) | ((~ wire_nll_dataout) & n0iiOi)))) | (((~ wire_nlO_dataout) & ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & n0il1i))) & (~ n0il1O))) | ((wire_nlO_dataout & (wire_nll_dataout & (wire_nli_dataout & n0il1l))) & (~ n0il0i))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nil_dataout) & ((~ wire_nii_dataout) & n0iilO)) | n0il0l) | (((~ wire_nil_dataout) | (~ wire_nii_dataout)) & n0il0i)) | ((~ wire_nil_dataout) & ((~ wire_nii_dataout) & (~ wire_n0O_dataout)))) & ((n0iiOi | (n0iiOi & n0iill)) | (n0iill & ((~ wire_nli_dataout) | (~ wire_niO_dataout))))))) | (r8b10b_dec_ibm_en[1]
 & (((((wire_nil_dataout & (wire_nii_dataout & n0iilO)) | n0il0O) | ((wire_nil_dataout | wire_nii_dataout) & n0il1O)) | (wire_nil_dataout & (wire_nii_dataout & wire_n0O_dataout))) & ((n0iiOl | (n0iiOl & (wire_nlO_dataout | wire_nll_dataout))) | ((wire_nlO_dataout & wire_nll_dataout) & (wire_nli_dataout | wire_niO_dataout)))))));
	assign		wire_nl0O_dataout = (cascaded_8b10b_en === 1'b1) ? wire_nli11O_dataout : wire_nii10O_dataout;
	assign		wire_nl10Oi_dataout = (((((~ wire_nlll_dataout) & n0illl) | (wire_nlll_dataout & n0llil)) | (n0lO0O & n0lO1i)) === 1'b1) ? wire_nii10O_dataout : (n0lliO | n0llli);
	assign		wire_nli_dataout = (nl0l === 1'b1) ? (~ data_in[7]) : data_in[7];
	assign		wire_nli11O_dataout = (((wire_nlOO_dataout ^ wire_nlOl_dataout) & n0lilO) === 1'b1) ? wire_nl10Oi_dataout : (n0liOi | n0ll1O);
	assign		wire_nlil_dataout = (nl0l === 1'b1) ? (~ data_in[16]) : data_in[16];
	assign		wire_nliO_dataout = (nl0l === 1'b1) ? (~ data_in[17]) : data_in[17];
	assign		wire_nll_dataout = (nl0l === 1'b1) ? (~ data_in[8]) : data_in[8];
	assign		wire_nlli_dataout = (nl0l === 1'b1) ? (~ data_in[18]) : data_in[18];
	assign		wire_nlll_dataout = (nl0l === 1'b1) ? (~ data_in[19]) : data_in[19];
	assign		wire_nllO_dataout = (nl0l === 1'b1) ? (~ data_in[20]) : data_in[20];
	assign		wire_nlO_dataout = (nl0l === 1'b1) ? (~ data_in[9]) : data_in[9];
	assign		wire_nlOi_dataout = (nl0l === 1'b1) ? (~ data_in[21]) : data_in[21];
	assign		wire_nlOiiO_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ ((n0l11i | (n0iOOO | n0iOOl)) | (n0llOi | (n0lOlO | (n0lOOi | n0lOiO))))) & (~ (((n0iOOi | n0ll1i) | ((~ (((n0iOlO | n0iOll) | (wire_nlOi_dataout & ((~ wire_nllO_dataout) & n0lO1l))) | ((~ wire_nlOi_dataout) & (wire_nllO_dataout & n0iOli)))) & ((~ n0iOiO) & (((~ wire_nlOl_dataout) & n0iOil) | (wire_nlOl_dataout & n0ll1l))))) | ((((~ wire_n1l_dataout) & n0iOil) | (wire_n1l_dataout & n0ll1l)) & (n0iOll | (n0iOlO | n0iOiO)))))) : (~ ((((((((((((((n0l1lO | n0l1ll) | ((~ wire_nlOi_dataout) & ((~ wire_nllO_dataout) & n0l1li))) | (wire_nlOi_dataout & (wire_nllO_dataout & n0l1iO))) | ((wire_n1l_dataout & (wire_n1i_dataout & (wire_nlOO_dataout & wire_nlOl_dataout))) | ((~ wire_n1l_dataout) & ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)))))) | ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & ((~ wire_nlOi_dataout) & (~ wire_nllO_dataout)))))) | (wire_n1i_dataout & (wire_nlOO_dataout & (wire_nlOl_dataout & (wire_nlOi_dataout & wire_nllO_dataout))))) | ((~ wire_n1l_dataout) & ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & n0l1il)))) | (wire_n1l_dataout & (wire_n1i_dataout & (wire_nlOO_dataout & n0l1ii)))) | ((((~ wire_n1l_dataout) & ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & wire_nlOi_dataout))) | (wire_n1l_dataout & (wire_n1i_dataout & (wire_nlOO_dataout & (~ wire_nlOi_dataout))))) & (~ n0l10O))) | (n0l10O & ((wire_n1i_dataout & n0l10l) | ((~ wire_n1i_dataout) & n0l10i)))) | (((~ wire_n1l_dataout) & ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & n0l1ii))) & (~ n0l1iO))) | ((wire_n1l_dataout & (wire_n1i_dataout & (wire_nlOO_dataout & n0l1il))) & (~ n0l1li))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nlOi_dataout) & ((~ wire_nllO_dataout) & n0l11O)) | n0l1ll) | (((~ wire_nlOi_dataout) | (~ wire_nllO_dataout)) & n0l1li)) | ((~ wire_nlOi_dataout) & ((~ wire_nllO_dataout) & (~ wire_nlll_dataout)))) & ((n0l10i | (n0l10i & n0l11l)) | (n0l11l & ((~ wire_nlOO_dataout) | (~ wire_nlOl_dataout
))))))) | (r8b10b_dec_ibm_en[1] & (((((wire_nlOi_dataout & (wire_nllO_dataout & n0l11O)) | n0l1lO) | ((wire_nlOi_dataout | wire_nllO_dataout) & n0l1iO)) | (wire_nlOi_dataout & (wire_nllO_dataout & wire_nlll_dataout))) & ((n0l10l | (n0l10l & (wire_n1l_dataout | wire_n1i_dataout))) | ((wire_n1l_dataout & wire_n1i_dataout) & (wire_nlOO_dataout | wire_nlOl_dataout)))))));
	assign		wire_nlOl_dataout = (nl0l === 1'b1) ? (~ data_in[22]) : data_in[22];
	assign		wire_nlOO_dataout = (nl0l === 1'b1) ? (~ data_in[23]) : data_in[23];
	or(wire_nlOOOO_dataout, wire_n110l_dataout, n0liiO);
	assign
		dec_ctl = {n0Ol, n0ii},
		dec_data = {nl1O, nl1l, nl1i, niOO, niOl, niOi, nill, nili, niiO, niil, niii, ni0O, ni0l, ni0i, ni1O, ni1l},
		dec_data_valid = {ni1i, n0OO},
		disp_err_delay = {n00i, n01O},
		disp_val_delay = {n01l, n01i},
		invalid_code_delay = {n00O, n00l},
		n0i00i = ((~ wire_n0i_dataout) & wire_n1O_dataout),
		n0i00l = (n0O0il & n0i0ii),
		n0i00O = ((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & (~ wire_n1O_dataout)))),
		n0i01i = (wire_n0i_dataout & wire_n1O_dataout),
		n0i01l = ((~ wire_n0i_dataout) & (~ wire_n1O_dataout)),
		n0i01O = (wire_n0i_dataout & (~ wire_n1O_dataout)),
		n0i0ii = (wire_nil_dataout & wire_nii_dataout),
		n0i0il = (wire_n0O_dataout & (wire_n0l_dataout & (wire_n0i_dataout & wire_n1O_dataout))),
		n0i0iO = (wire_nli_dataout & wire_niO_dataout),
		n0i0li = ((~ wire_nli_dataout) & (~ wire_niO_dataout)),
		n0i0ll = (wire_nli_dataout & (~ wire_niO_dataout)),
		n0i0lO = ((~ wire_nli_dataout) & wire_niO_dataout),
		n0i0Oi = (wire_n0i_dataout & wire_n1O_dataout),
		n0i0Ol = ((~ wire_n0i_dataout) & (~ wire_n1O_dataout)),
		n0i0OO = (wire_n0i_dataout & (~ wire_n1O_dataout)),
		n0ii0i = (((((~ wire_n0O_dataout) & (wire_n0l_dataout & n0i01i)) | (wire_n0O_dataout & ((~ wire_n0l_dataout) & n0i01i))) | (wire_n0O_dataout & (wire_n0l_dataout & ((~ wire_n0i_dataout) & wire_n1O_dataout)))) | (wire_n0O_dataout & (wire_n0l_dataout & (wire_n0i_dataout & (~ wire_n1O_dataout))))),
		n0ii0l = ((~ wire_nil_dataout) & ((~ wire_nii_dataout) & ((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & (wire_n0i_dataout & wire_n1O_dataout))))),
		n0ii0O = (wire_nil_dataout & (wire_nii_dataout & (wire_n0O_dataout & (wire_n0l_dataout & ((~ wire_n0i_dataout) & (~ wire_n1O_dataout)))))),
		n0ii1i = ((~ wire_n0i_dataout) & wire_n1O_dataout),
		n0ii1l = (((((~ wire_nlO_dataout) & (wire_nll_dataout & n0i0iO)) | (wire_nlO_dataout & ((~ wire_nll_dataout) & n0i0iO))) | (wire_nlO_dataout & (wire_nll_dataout & ((~ wire_nli_dataout) & wire_niO_dataout)))) | (wire_nlO_dataout & (wire_nll_dataout & (wire_nli_dataout & (~ wire_niO_dataout))))),
		n0ii1O = (((~ wire_ni1i1i_dataout) & n0i0ii) | (wire_ni1i1i_dataout & n0O0ll)),
		n0iiii = (wire_nlO_dataout & (wire_nll_dataout & (wire_nli_dataout & wire_niO_dataout))),
		n0iiil = (n0i0il & n0O0ii),
		n0iiiO = ((n0i0il & n0i0ii) | (n0ii0i & n0i0ii)),
		n0iili = (n0i0il & n0O0ll),
		n0iill = ((~ wire_nlO_dataout) & (~ wire_nll_dataout)),
		n0iilO = (((((((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & (wire_n0i_dataout & wire_n1O_dataout))) | ((~ wire_n0O_dataout) & (wire_n0l_dataout & n0ii1i))) | ((~ wire_n0O_dataout) & (wire_n0l_dataout & n0i0OO))) | (wire_n0O_dataout & ((~ wire_n0l_dataout) & n0ii1i))) | (wire_n0O_dataout & ((~ wire_n0l_dataout) & n0i0OO))) | (wire_n0O_dataout & (wire_n0l_dataout & ((~ wire_n0i_dataout) & (~ wire_n1O_dataout))))),
		n0iiOi = ((~ wire_nli_dataout) & (~ wire_niO_dataout)),
		n0iiOl = (wire_nli_dataout & wire_niO_dataout),
		n0iiOO = ((wire_nil_dataout & (wire_nii_dataout & (wire_n0O_dataout & wire_n0l_dataout))) | ((~ wire_nil_dataout) & ((~ wire_nii_dataout) & ((~ wire_n0O_dataout) & (~ wire_n0l_dataout))))),
		n0il0i = (((((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & wire_n1O_dataout))) | ((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & (wire_n0i_dataout & (~ wire_n1O_dataout))))) | ((~ wire_n0O_dataout) & (wire_n0l_dataout & n0i0Ol))) | (wire_n0O_dataout & ((~ wire_n0l_dataout) & n0i0Ol))),
		n0il0l = ((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & (~ wire_n1O_dataout)))),
		n0il0O = (wire_n0O_dataout & (wire_n0l_dataout & (wire_n0i_dataout & wire_n1O_dataout))),
		n0il1i = ((~ wire_nil_dataout) & wire_nii_dataout),
		n0il1l = (wire_nil_dataout & (~ wire_nii_dataout)),
		n0il1O = (((((~ wire_n0O_dataout) & (wire_n0l_dataout & n0i0Oi)) | (wire_n0O_dataout & ((~ wire_n0l_dataout) & n0i0Oi))) | (wire_n0O_dataout & (wire_n0l_dataout & ((~ wire_n0i_dataout) & wire_n1O_dataout)))) | (wire_n0O_dataout & (wire_n0l_dataout & (wire_n0i_dataout & (~ wire_n1O_dataout))))),
		n0ilii = (wire_nliO_dataout & wire_nlil_dataout),
		n0ilil = ((~ wire_nliO_dataout) & (~ wire_nlil_dataout)),
		n0iliO = (wire_nliO_dataout & (~ wire_nlil_dataout)),
		n0illi = ((~ wire_nliO_dataout) & wire_nlil_dataout),
		n0illl = (n0lO1l & n0ilOi),
		n0illO = ((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & (~ wire_nlil_dataout)))),
		n0ilOi = (wire_nlOi_dataout & wire_nllO_dataout),
		n0ilOl = (wire_nlll_dataout & (wire_nlli_dataout & (wire_nliO_dataout & wire_nlil_dataout))),
		n0ilOO = (wire_nlOO_dataout & wire_nlOl_dataout),
		n0iO0i = (wire_nliO_dataout & wire_nlil_dataout),
		n0iO0l = ((~ wire_nliO_dataout) & (~ wire_nlil_dataout)),
		n0iO0O = (wire_nliO_dataout & (~ wire_nlil_dataout)),
		n0iO1i = ((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)),
		n0iO1l = (wire_nlOO_dataout & (~ wire_nlOl_dataout)),
		n0iO1O = ((~ wire_nlOO_dataout) & wire_nlOl_dataout),
		n0iOii = ((~ wire_nliO_dataout) & wire_nlil_dataout),
		n0iOil = (((((~ wire_n1l_dataout) & (wire_n1i_dataout & n0ilOO)) | (wire_n1l_dataout & ((~ wire_n1i_dataout) & n0ilOO))) | (wire_n1l_dataout & (wire_n1i_dataout & ((~ wire_nlOO_dataout) & wire_nlOl_dataout)))) | (wire_n1l_dataout & (wire_n1i_dataout & (wire_nlOO_dataout & (~ wire_nlOl_dataout))))),
		n0iOiO = (((~ wire_nl10Oi_dataout) & n0ilOi) | (wire_nl10Oi_dataout & n0lO0l)),
		n0iOli = (((((~ wire_nlll_dataout) & (wire_nlli_dataout & n0ilii)) | (wire_nlll_dataout & ((~ wire_nlli_dataout) & n0ilii))) | (wire_nlll_dataout & (wire_nlli_dataout & ((~ wire_nliO_dataout) & wire_nlil_dataout)))) | (wire_nlll_dataout & (wire_nlli_dataout & (wire_nliO_dataout & (~ wire_nlil_dataout))))),
		n0iOll = ((~ wire_nlOi_dataout) & ((~ wire_nllO_dataout) & ((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & (wire_nliO_dataout & wire_nlil_dataout))))),
		n0iOlO = (wire_nlOi_dataout & (wire_nllO_dataout & (wire_nlll_dataout & (wire_nlli_dataout & ((~ wire_nliO_dataout) & (~ wire_nlil_dataout)))))),
		n0iOOi = (wire_n1l_dataout & (wire_n1i_dataout & (wire_nlOO_dataout & wire_nlOl_dataout))),
		n0iOOl = (n0ilOl & n0lO1i),
		n0iOOO = ((n0ilOl & n0ilOi) | (n0iOli & n0ilOi)),
		n0l00i = (wire_n1l0i_dataout & (~ wire_n1l1O_dataout)),
		n0l00l = (wire_n1iOO_dataout & ((wire_n1l0i_dataout ^ wire_n1l1O_dataout) & (wire_n1l1l_dataout ^ wire_n1l1i_dataout))),
		n0l00O = (wire_n1iOO_dataout & ((~ wire_n1l1i_dataout) & ((~ wire_n1l1l_dataout) & (wire_n1l0i_dataout & wire_n1l1O_dataout)))),
		n0l01i = ((((~ wire_n1iOO_dataout) & (((((((~ wire_n1l1i_dataout) & ((~ wire_n1l1l_dataout) & (wire_n1l0i_dataout & wire_n1l1O_dataout))) | ((~ wire_n1l1i_dataout) & (wire_n1l1l_dataout & n0l00i))) | ((~ wire_n1l1i_dataout) & (wire_n1l1l_dataout & n0l01O))) | (wire_n1l1i_dataout & ((~ wire_n1l1l_dataout) & n0l00i))) | (wire_n1l1i_dataout & ((~ wire_n1l1l_dataout) & n0l01O))) | (wire_n1l1i_dataout & (wire_n1l1l_dataout & ((~ wire_n1l0i_dataout) & (~ wire_n1l1O_dataout)))))) | (wire_n1iOO_dataout & n0l01l)) & (wire_n1l1l_dataout | (wire_n1l0i_dataout | wire_n1l1O_dataout))),
		n0l01l = (((((~ wire_n1l1i_dataout) & ((~ wire_n1l1l_dataout) & (wire_n1l0i_dataout & (~ wire_n1l1O_dataout)))) | ((~ wire_n1l1i_dataout) & ((~ wire_n1l1l_dataout) & ((~ wire_n1l0i_dataout) & wire_n1l1O_dataout)))) | ((~ wire_n1l1i_dataout) & (wire_n1l1l_dataout & n0l1Oi))) | (wire_n1l1i_dataout & ((~ wire_n1l1l_dataout) & n0l1Oi))),
		n0l01O = ((~ wire_n1l0i_dataout) & wire_n1l1O_dataout),
		n0l0ii = (((~ wire_n1Oli_dataout) & wire_n1OiO_dataout) & (~ wire_n1Oil_dataout)),
		n0l0il = ((~ wire_nil_dataout) & n0liiO),
		n0l0iO = (wire_nli_dataout ^ wire_niO_dataout),
		n0l0li = ((~ wire_ni10l_dataout) & (~ wire_ni10i_dataout)),
		n0l0ll = (wire_ni10i_dataout & wire_ni11O_dataout),
		n0l0lO = ((~ wire_ni10i_dataout) & (~ wire_ni11O_dataout)),
		n0l0Oi = ((((~ wire_ni11i_dataout) & (((((((~ wire_ni11l_dataout) & ((~ wire_ni11O_dataout) & (wire_ni10l_dataout & wire_ni10i_dataout))) | ((~ wire_ni11l_dataout) & (wire_ni11O_dataout & n0li1i))) | ((~ wire_ni11l_dataout) & (wire_ni11O_dataout & n0l0OO))) | (wire_ni11l_dataout & ((~ wire_ni11O_dataout) & n0li1i))) | (wire_ni11l_dataout & ((~ wire_ni11O_dataout) & n0l0OO))) | (wire_ni11l_dataout & (wire_ni11O_dataout & ((~ wire_ni10l_dataout) & (~ wire_ni10i_dataout)))))) | (wire_ni11i_dataout & n0l0Ol)) & (wire_ni11O_dataout | (wire_ni10l_dataout | wire_ni10i_dataout))),
		n0l0Ol = (((((~ wire_ni11l_dataout) & ((~ wire_ni11O_dataout) & (wire_ni10l_dataout & (~ wire_ni10i_dataout)))) | ((~ wire_ni11l_dataout) & ((~ wire_ni11O_dataout) & ((~ wire_ni10l_dataout) & wire_ni10i_dataout)))) | ((~ wire_ni11l_dataout) & (wire_ni11O_dataout & n0l0li))) | (wire_ni11l_dataout & ((~ wire_ni11O_dataout) & n0l0li))),
		n0l0OO = ((~ wire_ni10l_dataout) & wire_ni10i_dataout),
		n0l10i = ((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)),
		n0l10l = (wire_nlOO_dataout & wire_nlOl_dataout),
		n0l10O = ((wire_nlOi_dataout & (wire_nllO_dataout & (wire_nlll_dataout & wire_nlli_dataout))) | ((~ wire_nlOi_dataout) & ((~ wire_nllO_dataout) & ((~ wire_nlll_dataout) & (~ wire_nlli_dataout))))),
		n0l11i = (n0ilOl & n0lO0l),
		n0l11l = ((~ wire_n1l_dataout) & (~ wire_n1i_dataout)),
		n0l11O = (((((((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & (wire_nliO_dataout & wire_nlil_dataout))) | ((~ wire_nlll_dataout) & (wire_nlli_dataout & n0iOii))) | ((~ wire_nlll_dataout) & (wire_nlli_dataout & n0iO0O))) | (wire_nlll_dataout & ((~ wire_nlli_dataout) & n0iOii))) | (wire_nlll_dataout & ((~ wire_nlli_dataout) & n0iO0O))) | (wire_nlll_dataout & (wire_nlli_dataout & ((~ wire_nliO_dataout) & (~ wire_nlil_dataout))))),
		n0l1ii = ((~ wire_nlOi_dataout) & wire_nllO_dataout),
		n0l1il = (wire_nlOi_dataout & (~ wire_nllO_dataout)),
		n0l1iO = (((((~ wire_nlll_dataout) & (wire_nlli_dataout & n0iO0i)) | (wire_nlll_dataout & ((~ wire_nlli_dataout) & n0iO0i))) | (wire_nlll_dataout & (wire_nlli_dataout & ((~ wire_nliO_dataout) & wire_nlil_dataout)))) | (wire_nlll_dataout & (wire_nlli_dataout & (wire_nliO_dataout & (~ wire_nlil_dataout))))),
		n0l1li = (((((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & wire_nlil_dataout))) | ((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & (wire_nliO_dataout & (~ wire_nlil_dataout))))) | ((~ wire_nlll_dataout) & (wire_nlli_dataout & n0iO0l))) | (wire_nlll_dataout & ((~ wire_nlli_dataout) & n0iO0l))),
		n0l1ll = ((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & (~ wire_nlil_dataout)))),
		n0l1lO = (wire_nlll_dataout & (wire_nlli_dataout & (wire_nliO_dataout & wire_nlil_dataout))),
		n0l1Oi = ((~ wire_n1l0i_dataout) & (~ wire_n1l1O_dataout)),
		n0l1Ol = (wire_n1l1O_dataout & wire_n1l1l_dataout),
		n0l1OO = ((~ wire_n1l1O_dataout) & (~ wire_n1l1l_dataout)),
		n0li0i = (((~ wire_ni0ll_dataout) & wire_ni0li_dataout) & (~ wire_ni0iO_dataout)),
		n0li0l = ((~ wire_nlOi_dataout) & n0Oiii),
		n0li0O = (wire_nlOO_dataout ^ wire_nlOl_dataout),
		n0li1i = (wire_ni10l_dataout & (~ wire_ni10i_dataout)),
		n0li1l = (wire_ni11i_dataout & ((wire_ni10l_dataout ^ wire_ni10i_dataout) & (wire_ni11O_dataout ^ wire_ni11l_dataout))),
		n0li1O = (wire_ni11i_dataout & ((~ wire_ni11l_dataout) & ((~ wire_ni11O_dataout) & (wire_ni10l_dataout & wire_ni10i_dataout)))),
		n0liii = ((wire_n1Oli_dataout & (~ wire_n1OiO_dataout)) & (~ wire_n1Oil_dataout)),
		n0liil = ((~ wire_n1iOO_dataout) & n0l01l),
		n0liiO = (wire_n1iOO_dataout & (wire_n1l1i_dataout & (wire_n1l1l_dataout & ((~ wire_n1l0i_dataout) & (~ wire_n1l1O_dataout))))),
		n0lilO = (((((((~ wire_n1l_dataout) & ((~ wire_n1i_dataout) & (wire_nlOO_dataout & wire_nlOl_dataout))) | ((~ wire_n1l_dataout) & (wire_n1i_dataout & n0iO1O))) | ((~ wire_n1l_dataout) & (wire_n1i_dataout & n0iO1l))) | (wire_n1l_dataout & ((~ wire_n1i_dataout) & n0iO1O))) | (wire_n1l_dataout & ((~ wire_n1i_dataout) & n0iO1l))) | (wire_n1l_dataout & (wire_n1i_dataout & ((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout))))),
		n0liOi = (n0iOil | n0iOOi),
		n0ll1i = ((~ wire_n1l_dataout) & ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)))),
		n0ll1l = (((((~ wire_n1l_dataout) & ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & wire_nlOl_dataout))) | ((~ wire_n1l_dataout) & ((~ wire_n1i_dataout) & (wire_nlOO_dataout & (~ wire_nlOl_dataout))))) | ((~ wire_n1l_dataout) & (wire_n1i_dataout & n0iO1i))) | (wire_n1l_dataout & ((~ wire_n1i_dataout) & n0iO1i))),
		n0ll1O = ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & n0lilO)),
		n0llil = (n0iOli & n0lO0l),
		n0lliO = ((((n0iOOO | (n0lO0O & n0ilOi)) | (n0iOli & n0lO1i)) | n0iOOl) | n0l11i),
		n0llli = (wire_nlll_dataout & n0illl),
		n0llOi = (n0illO & n0ilOi),
		n0lO0l = ((~ wire_nlOi_dataout) & (~ wire_nllO_dataout)),
		n0lO0O = (((((((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & (wire_nliO_dataout & wire_nlil_dataout))) | ((~ wire_nlll_dataout) & (wire_nlli_dataout & n0illi))) | ((~ wire_nlll_dataout) & (wire_nlli_dataout & n0iliO))) | (wire_nlll_dataout & ((~ wire_nlli_dataout) & n0illi))) | (wire_nlll_dataout & ((~ wire_nlli_dataout) & n0iliO))) | (wire_nlll_dataout & (wire_nlli_dataout & ((~ wire_nliO_dataout) & (~ wire_nlil_dataout))))),
		n0lO1i = (((~ wire_nlOi_dataout) & wire_nllO_dataout) | (wire_nlOi_dataout & (~ wire_nllO_dataout))),
		n0lO1l = (((((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & wire_nlil_dataout))) | ((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & (wire_nliO_dataout & (~ wire_nlil_dataout))))) | ((~ wire_nlll_dataout) & (wire_nlli_dataout & n0ilil))) | (wire_nlll_dataout & ((~ wire_nlli_dataout) & n0ilil))),
		n0lOiO = (n0lO1l & n0lO0l),
		n0lOlO = (n0illO & n0lO1i),
		n0lOOi = (n0illO & n0lO0l),
		n0O00i = (n0i00O & n0i0ii),
		n0O01O = (wire_n0O_dataout & n0i00l),
		n0O0ii = (((~ wire_nil_dataout) & wire_nii_dataout) | (wire_nil_dataout & (~ wire_nii_dataout))),
		n0O0il = (((((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & wire_n1O_dataout))) | ((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & (wire_n0i_dataout & (~ wire_n1O_dataout))))) | ((~ wire_n0O_dataout) & (wire_n0l_dataout & n0i01l))) | (wire_n0O_dataout & ((~ wire_n0l_dataout) & n0i01l))),
		n0O0ll = ((~ wire_nil_dataout) & (~ wire_nii_dataout)),
		n0O0lO = (((((((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & (wire_n0i_dataout & wire_n1O_dataout))) | ((~ wire_n0O_dataout) & (wire_n0l_dataout & n0i00i))) | ((~ wire_n0O_dataout) & (wire_n0l_dataout & n0i01O))) | (wire_n0O_dataout & ((~ wire_n0l_dataout) & n0i00i))) | (wire_n0O_dataout & ((~ wire_n0l_dataout) & n0i01O))) | (wire_n0O_dataout & (wire_n0l_dataout & ((~ wire_n0i_dataout) & (~ wire_n1O_dataout))))),
		n0O0OO = (n0O0il & n0O0ll),
		n0O10i = (n0ii1l | n0iiii),
		n0O11O = (((((((~ wire_nlO_dataout) & ((~ wire_nll_dataout) & (wire_nli_dataout & wire_niO_dataout))) | ((~ wire_nlO_dataout) & (wire_nll_dataout & n0i0lO))) | ((~ wire_nlO_dataout) & (wire_nll_dataout & n0i0ll))) | (wire_nlO_dataout & ((~ wire_nll_dataout) & n0i0lO))) | (wire_nlO_dataout & ((~ wire_nll_dataout) & n0i0ll))) | (wire_nlO_dataout & (wire_nll_dataout & ((~ wire_nli_dataout) & (~ wire_niO_dataout))))),
		n0O1ii = ((~ wire_nlO_dataout) & ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & (~ wire_niO_dataout)))),
		n0O1il = (((((~ wire_nlO_dataout) & ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & wire_niO_dataout))) | ((~ wire_nlO_dataout) & ((~ wire_nll_dataout) & (wire_nli_dataout & (~ wire_niO_dataout))))) | ((~ wire_nlO_dataout) & (wire_nll_dataout & n0i0li))) | (wire_nlO_dataout & ((~ wire_nll_dataout) & n0i0li))),
		n0O1iO = ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & n0O11O)),
		n0O1Ol = (n0ii0i & n0O0ll),
		n0O1OO = ((((n0iiiO | (n0O0lO & n0i0ii)) | (n0ii0i & n0O0ii)) | n0iiil) | n0iili),
		n0Oi0i = (n0i00O & n0O0ll),
		n0Oi0l = ((wire_ni0ll_dataout & (~ wire_ni0li_dataout)) & (~ wire_ni0iO_dataout)),
		n0Oi0O = ((~ wire_ni11i_dataout) & n0l0Ol),
		n0Oi1O = (n0i00O & n0O0ii),
		n0Oiii = (wire_ni11i_dataout & (wire_ni11l_dataout & (wire_ni11O_dataout & ((~ wire_ni10l_dataout) & (~ wire_ni10i_dataout))))),
		n0OiiO = 1'b1,
		ovr_undflow = {n1Oi, n1lO, n1ll, n1li},
		rlb_data = {wire_n1l_dataout, wire_n1i_dataout, wire_nlOO_dataout, wire_nlOl_dataout, wire_nlOi_dataout, wire_nllO_dataout, wire_nlll_dataout, wire_nlli_dataout, wire_nliO_dataout, wire_nlil_dataout, wire_nlO_dataout, wire_nll_dataout, wire_nli_dataout, wire_niO_dataout, wire_nil_dataout, wire_nii_dataout, wire_n0O_dataout, wire_n0l_dataout, wire_n0i_dataout, wire_n1O_dataout},
		sync_resync_delay = {n1OO, n1Ol},
		tenb_data = {n1iO, n1il, n1ii, n10O, n10l, n10i, n11O, n11l, n11i, nlOOO, nlOOl, nlOOi, nlOlO, nlOll, nlOli, nlOiO, nlOil, nlOii, nlO0O, nlii};
endmodule //arriagx_hssi_rx_dec_chnl_top
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 135 mux21 124 oper_add 1 arriagx_hssi_ram16x14_syn 1 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_dskw_fifo
	( 
	align_det_sync,
	audi,
	audi_pre,
	clk_1,
	en_dskw_gp,
	en_dskw_qd,
	fifo_rst_rd_gp,
	fifo_rst_rd_qd,
	rcvd_clk,
	rd_align,
	rdskchrp,
	rdskposdisp,
	sel_gp_md,
	soft_reset,
	sudi) /* synthesis synthesis_clearbox=1 */;
	output   align_det_sync;
	output   [13:0]  audi;
	output   [13:0]  audi_pre;
	input   clk_1;
	input   en_dskw_gp;
	input   en_dskw_qd;
	input   fifo_rst_rd_gp;
	input   fifo_rst_rd_qd;
	input   rcvd_clk;
	output   rd_align;
	input   [9:0]  rdskchrp;
	input   rdskposdisp;
	input   sel_gp_md;
	input   soft_reset;
	input   [13:0]  sudi;

	reg	n100l17;
	reg	n100l18;
	reg	n101i21;
	reg	n101i22;
	reg	n101O19;
	reg	n101O20;
	reg	n10iO15;
	reg	n10iO16;
	reg	n10lO13;
	reg	n10lO14;
	reg	n10Ol11;
	reg	n10Ol12;
	reg	n10OO10;
	reg	n10OO9;
	reg	n110i33;
	reg	n110i34;
	reg	n110O31;
	reg	n110O32;
	reg	n111l35;
	reg	n111l36;
	reg	n11il29;
	reg	n11il30;
	reg	n11li27;
	reg	n11li28;
	reg	n11lO25;
	reg	n11lO26;
	reg	n11Ol23;
	reg	n11Ol24;
	reg	n1i0l3;
	reg	n1i0l4;
	reg	n1i1i7;
	reg	n1i1i8;
	reg	n1i1O5;
	reg	n1i1O6;
	reg	n1ili1;
	reg	n1ili2;
	reg	nlOO0l47;
	reg	nlOO0l48;
	reg	nlOOii45;
	reg	nlOOii46;
	reg	nlOOiO43;
	reg	nlOOiO44;
	reg	nlOOll41;
	reg	nlOOll42;
	reg	nlOOOi39;
	reg	nlOOOi40;
	reg	nlOOOO37;
	reg	nlOOOO38;
	reg	ni00l;
	reg	ni10i;
	wire	wire_ni00i_PRN;
	reg	n0Oi;
	reg	ni0l;
	reg	ni0O;
	reg	niii;
	reg	niiO;
	reg	nlliO;
	reg	nllli;
	reg	nllll;
	reg	nlllO;
	reg	nllOi;
	reg	nllOl;
	reg	nllOO;
	reg	nlO0i;
	reg	nlO0l;
	reg	nlO0O;
	reg	nlO1i;
	reg	nlO1l;
	reg	nlO1O;
	reg	nlOii;
	reg	nlOil;
	reg	nlOiO;
	reg	niil_clk_prev;
	wire	wire_niil_PRN;
	reg	ni00O;
	reg	ni01i;
	reg	ni01l;
	reg	ni01O;
	reg	ni0ii;
	reg	ni0il;
	reg	ni0iO;
	reg	ni0li;
	reg	ni0ll;
	reg	ni0lO;
	reg	ni0Oi;
	reg	ni0Ol;
	reg	ni0OO;
	reg	ni10l;
	reg	ni10O;
	reg	ni11l;
	reg	ni11O;
	reg	ni1ii;
	reg	ni1il;
	reg	ni1iO;
	reg	ni1li;
	reg	ni1ll;
	reg	ni1lO;
	reg	ni1Oi;
	reg	ni1Ol;
	reg	ni1OO;
	reg	nii0i;
	reg	nii0l;
	reg	nii0O;
	reg	nii1i;
	reg	nii1l;
	reg	nii1O;
	reg	nl0ll;
	reg	nl0lO;
	reg	nl0Oi;
	reg	nl0Ol;
	reg	nl0OO;
	reg	nli0i;
	reg	nli0l;
	reg	nli0O;
	reg	nli1i;
	reg	nli1l;
	reg	nli1O;
	reg	nliii;
	reg	nliil;
	reg	nliiO;
	reg	nlili;
	reg	nlill;
	reg	nlilO;
	reg	nliOi;
	reg	nliOl;
	reg	nliOO;
	reg	nll0i;
	reg	nll0l;
	reg	nll0O;
	reg	nll1i;
	reg	nll1l;
	reg	nll1O;
	reg	nllii;
	reg	nlOi;
	wire	wire_nllO_CLRN;
	reg	ni;
	reg	nlil;
	reg	nll;
	reg	nllil;
	reg	nlO_clk_prev;
	wire	wire_nlO_CLRN;
	wire	wire_n00i_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_nii_dataout;
	wire	wire_niiii_dataout;
	wire	wire_niiil_dataout;
	wire	wire_niiiO_dataout;
	wire	wire_niili_dataout;
	wire	wire_niill_dataout;
	wire	wire_niilO_dataout;
	wire	wire_niiOi_dataout;
	wire	wire_niiOl_dataout;
	wire	wire_niiOO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nil0i_dataout;
	wire	wire_nil0l_dataout;
	wire	wire_nil0O_dataout;
	wire	wire_nil1i_dataout;
	wire	wire_nil1l_dataout;
	wire	wire_nil1O_dataout;
	wire	wire_nili_dataout;
	wire	wire_nilii_dataout;
	wire	wire_nilil_dataout;
	wire	wire_niliO_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilli_dataout;
	wire	wire_nilll_dataout;
	wire	wire_nillO_dataout;
	wire	wire_nilO_dataout;
	wire	wire_nilOi_dataout;
	wire	wire_nilOl_dataout;
	wire	wire_nilOO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niO0i_dataout;
	wire	wire_niO0l_dataout;
	wire	wire_niO0O_dataout;
	wire	wire_niO1i_dataout;
	wire	wire_niO1l_dataout;
	wire	wire_niO1O_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOii_dataout;
	wire	wire_niOil_dataout;
	wire	wire_niOiO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOli_dataout;
	wire	wire_niOll_dataout;
	wire	wire_niOlO_dataout;
	wire	wire_niOO_dataout;
	wire	wire_niOOi_dataout;
	wire	wire_niOOl_dataout;
	wire	wire_niOOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl00i_dataout;
	wire	wire_nl00l_dataout;
	wire	wire_nl00O_dataout;
	wire	wire_nl01i_dataout;
	wire	wire_nl01l_dataout;
	wire	wire_nl01O_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0ii_dataout;
	wire	wire_nl0il_dataout;
	wire	wire_nl0iO_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl10i_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl10O_dataout;
	wire	wire_nl11i_dataout;
	wire	wire_nl11l_dataout;
	wire	wire_nl11O_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1ii_dataout;
	wire	wire_nl1il_dataout;
	wire	wire_nl1iO_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1li_dataout;
	wire	wire_nl1ll_dataout;
	wire	wire_nl1lO_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nl1Oi_dataout;
	wire	wire_nl1Ol_dataout;
	wire	wire_nl1OO_dataout;
	wire	wire_nli_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nlOli_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOO_dataout;
	wire	wire_nO_dataout;
	wire  [4:0]   wire_nlii_o;
	wire  [13:0]   wire_n1iOi_data_out1;
	wire  [13:0]   wire_n1iOi_data_out2;
	wire  n10ii;
	wire  n10il;
	wire  n10li;
	wire  n10ll;
	wire  n1i0i;
	wire  n1i1l;
	wire  n1iii;
	wire  n1iil;
	wire  n1iiO;

	initial
		n100l17 = 0;
	always @ ( posedge clk_1)
		  n100l17 <= n100l18;
	event n100l17_event;
	initial
		#1 ->n100l17_event;
	always @(n100l17_event)
		n100l17 <= {1{1'b1}};
	initial
		n100l18 = 0;
	always @ ( posedge clk_1)
		  n100l18 <= n100l17;
	initial
		n101i21 = 0;
	always @ ( posedge clk_1)
		  n101i21 <= n101i22;
	event n101i21_event;
	initial
		#1 ->n101i21_event;
	always @(n101i21_event)
		n101i21 <= {1{1'b1}};
	initial
		n101i22 = 0;
	always @ ( posedge clk_1)
		  n101i22 <= n101i21;
	initial
		n101O19 = 0;
	always @ ( posedge clk_1)
		  n101O19 <= n101O20;
	event n101O19_event;
	initial
		#1 ->n101O19_event;
	always @(n101O19_event)
		n101O19 <= {1{1'b1}};
	initial
		n101O20 = 0;
	always @ ( posedge clk_1)
		  n101O20 <= n101O19;
	initial
		n10iO15 = 0;
	always @ ( posedge clk_1)
		  n10iO15 <= n10iO16;
	event n10iO15_event;
	initial
		#1 ->n10iO15_event;
	always @(n10iO15_event)
		n10iO15 <= {1{1'b1}};
	initial
		n10iO16 = 0;
	always @ ( posedge clk_1)
		  n10iO16 <= n10iO15;
	initial
		n10lO13 = 0;
	always @ ( posedge clk_1)
		  n10lO13 <= n10lO14;
	event n10lO13_event;
	initial
		#1 ->n10lO13_event;
	always @(n10lO13_event)
		n10lO13 <= {1{1'b1}};
	initial
		n10lO14 = 0;
	always @ ( posedge clk_1)
		  n10lO14 <= n10lO13;
	initial
		n10Ol11 = 0;
	always @ ( posedge clk_1)
		  n10Ol11 <= n10Ol12;
	event n10Ol11_event;
	initial
		#1 ->n10Ol11_event;
	always @(n10Ol11_event)
		n10Ol11 <= {1{1'b1}};
	initial
		n10Ol12 = 0;
	always @ ( posedge clk_1)
		  n10Ol12 <= n10Ol11;
	initial
		n10OO10 = 0;
	always @ ( posedge clk_1)
		  n10OO10 <= n10OO9;
	initial
		n10OO9 = 0;
	always @ ( posedge clk_1)
		  n10OO9 <= n10OO10;
	event n10OO9_event;
	initial
		#1 ->n10OO9_event;
	always @(n10OO9_event)
		n10OO9 <= {1{1'b1}};
	initial
		n110i33 = 0;
	always @ ( posedge clk_1)
		  n110i33 <= n110i34;
	event n110i33_event;
	initial
		#1 ->n110i33_event;
	always @(n110i33_event)
		n110i33 <= {1{1'b1}};
	initial
		n110i34 = 0;
	always @ ( posedge clk_1)
		  n110i34 <= n110i33;
	initial
		n110O31 = 0;
	always @ ( posedge clk_1)
		  n110O31 <= n110O32;
	event n110O31_event;
	initial
		#1 ->n110O31_event;
	always @(n110O31_event)
		n110O31 <= {1{1'b1}};
	initial
		n110O32 = 0;
	always @ ( posedge clk_1)
		  n110O32 <= n110O31;
	initial
		n111l35 = 0;
	always @ ( posedge clk_1)
		  n111l35 <= n111l36;
	event n111l35_event;
	initial
		#1 ->n111l35_event;
	always @(n111l35_event)
		n111l35 <= {1{1'b1}};
	initial
		n111l36 = 0;
	always @ ( posedge clk_1)
		  n111l36 <= n111l35;
	initial
		n11il29 = 0;
	always @ ( posedge clk_1)
		  n11il29 <= n11il30;
	event n11il29_event;
	initial
		#1 ->n11il29_event;
	always @(n11il29_event)
		n11il29 <= {1{1'b1}};
	initial
		n11il30 = 0;
	always @ ( posedge clk_1)
		  n11il30 <= n11il29;
	initial
		n11li27 = 0;
	always @ ( posedge clk_1)
		  n11li27 <= n11li28;
	event n11li27_event;
	initial
		#1 ->n11li27_event;
	always @(n11li27_event)
		n11li27 <= {1{1'b1}};
	initial
		n11li28 = 0;
	always @ ( posedge clk_1)
		  n11li28 <= n11li27;
	initial
		n11lO25 = 0;
	always @ ( posedge clk_1)
		  n11lO25 <= n11lO26;
	event n11lO25_event;
	initial
		#1 ->n11lO25_event;
	always @(n11lO25_event)
		n11lO25 <= {1{1'b1}};
	initial
		n11lO26 = 0;
	always @ ( posedge clk_1)
		  n11lO26 <= n11lO25;
	initial
		n11Ol23 = 0;
	always @ ( posedge clk_1)
		  n11Ol23 <= n11Ol24;
	event n11Ol23_event;
	initial
		#1 ->n11Ol23_event;
	always @(n11Ol23_event)
		n11Ol23 <= {1{1'b1}};
	initial
		n11Ol24 = 0;
	always @ ( posedge clk_1)
		  n11Ol24 <= n11Ol23;
	initial
		n1i0l3 = 0;
	always @ ( posedge clk_1)
		  n1i0l3 <= n1i0l4;
	event n1i0l3_event;
	initial
		#1 ->n1i0l3_event;
	always @(n1i0l3_event)
		n1i0l3 <= {1{1'b1}};
	initial
		n1i0l4 = 0;
	always @ ( posedge clk_1)
		  n1i0l4 <= n1i0l3;
	initial
		n1i1i7 = 0;
	always @ ( posedge clk_1)
		  n1i1i7 <= n1i1i8;
	event n1i1i7_event;
	initial
		#1 ->n1i1i7_event;
	always @(n1i1i7_event)
		n1i1i7 <= {1{1'b1}};
	initial
		n1i1i8 = 0;
	always @ ( posedge clk_1)
		  n1i1i8 <= n1i1i7;
	initial
		n1i1O5 = 0;
	always @ ( posedge clk_1)
		  n1i1O5 <= n1i1O6;
	event n1i1O5_event;
	initial
		#1 ->n1i1O5_event;
	always @(n1i1O5_event)
		n1i1O5 <= {1{1'b1}};
	initial
		n1i1O6 = 0;
	always @ ( posedge clk_1)
		  n1i1O6 <= n1i1O5;
	initial
		n1ili1 = 0;
	always @ ( posedge clk_1)
		  n1ili1 <= n1ili2;
	event n1ili1_event;
	initial
		#1 ->n1ili1_event;
	always @(n1ili1_event)
		n1ili1 <= {1{1'b1}};
	initial
		n1ili2 = 0;
	always @ ( posedge clk_1)
		  n1ili2 <= n1ili1;
	initial
		nlOO0l47 = 0;
	always @ ( posedge clk_1)
		  nlOO0l47 <= nlOO0l48;
	event nlOO0l47_event;
	initial
		#1 ->nlOO0l47_event;
	always @(nlOO0l47_event)
		nlOO0l47 <= {1{1'b1}};
	initial
		nlOO0l48 = 0;
	always @ ( posedge clk_1)
		  nlOO0l48 <= nlOO0l47;
	initial
		nlOOii45 = 0;
	always @ ( posedge clk_1)
		  nlOOii45 <= nlOOii46;
	event nlOOii45_event;
	initial
		#1 ->nlOOii45_event;
	always @(nlOOii45_event)
		nlOOii45 <= {1{1'b1}};
	initial
		nlOOii46 = 0;
	always @ ( posedge clk_1)
		  nlOOii46 <= nlOOii45;
	initial
		nlOOiO43 = 0;
	always @ ( posedge clk_1)
		  nlOOiO43 <= nlOOiO44;
	event nlOOiO43_event;
	initial
		#1 ->nlOOiO43_event;
	always @(nlOOiO43_event)
		nlOOiO43 <= {1{1'b1}};
	initial
		nlOOiO44 = 0;
	always @ ( posedge clk_1)
		  nlOOiO44 <= nlOOiO43;
	initial
		nlOOll41 = 0;
	always @ ( posedge clk_1)
		  nlOOll41 <= nlOOll42;
	event nlOOll41_event;
	initial
		#1 ->nlOOll41_event;
	always @(nlOOll41_event)
		nlOOll41 <= {1{1'b1}};
	initial
		nlOOll42 = 0;
	always @ ( posedge clk_1)
		  nlOOll42 <= nlOOll41;
	initial
		nlOOOi39 = 0;
	always @ ( posedge clk_1)
		  nlOOOi39 <= nlOOOi40;
	event nlOOOi39_event;
	initial
		#1 ->nlOOOi39_event;
	always @(nlOOOi39_event)
		nlOOOi39 <= {1{1'b1}};
	initial
		nlOOOi40 = 0;
	always @ ( posedge clk_1)
		  nlOOOi40 <= nlOOOi39;
	initial
		nlOOOO37 = 0;
	always @ ( posedge clk_1)
		  nlOOOO37 <= nlOOOO38;
	event nlOOOO37_event;
	initial
		#1 ->nlOOOO37_event;
	always @(nlOOOO37_event)
		nlOOOO37 <= {1{1'b1}};
	initial
		nlOOOO38 = 0;
	always @ ( posedge clk_1)
		  nlOOOO38 <= nlOOOO37;
	initial
	begin
		ni00l = 0;
		ni10i = 0;
	end
	always @ ( posedge clk_1 or  negedge wire_ni00i_PRN)
	begin
		if (wire_ni00i_PRN == 1'b0) 
		begin
			ni00l <= 1;
			ni10i <= 1;
		end
		else 
		begin
			ni00l <= wire_nilil_dataout;
			ni10i <= wire_niiil_dataout;
		end
	end
	assign
		wire_ni00i_PRN = ((n10iO16 ^ n10iO15) & (~ soft_reset));
	initial
	begin
		n0Oi = 0;
		ni0l = 0;
		ni0O = 0;
		niii = 0;
		niiO = 0;
		nlliO = 0;
		nllli = 0;
		nllll = 0;
		nlllO = 0;
		nllOi = 0;
		nllOl = 0;
		nllOO = 0;
		nlO0i = 0;
		nlO0l = 0;
		nlO0O = 0;
		nlO1i = 0;
		nlO1l = 0;
		nlO1O = 0;
		nlOii = 0;
		nlOil = 0;
		nlOiO = 0;
	end
	always @ (rcvd_clk or wire_niil_PRN or soft_reset)
	begin
		if (wire_niil_PRN == 1'b0) 
		begin
			n0Oi <= 1;
			ni0l <= 1;
			ni0O <= 1;
			niii <= 1;
			niiO <= 1;
			nlliO <= 1;
			nllli <= 1;
			nllll <= 1;
			nlllO <= 1;
			nllOi <= 1;
			nllOl <= 1;
			nllOO <= 1;
			nlO0i <= 1;
			nlO0l <= 1;
			nlO0O <= 1;
			nlO1i <= 1;
			nlO1l <= 1;
			nlO1O <= 1;
			nlOii <= 1;
			nlOil <= 1;
			nlOiO <= 1;
		end
		else if  (soft_reset == 1'b1) 
		begin
			n0Oi <= 0;
			ni0l <= 0;
			ni0O <= 0;
			niii <= 0;
			niiO <= 0;
			nlliO <= 0;
			nllli <= 0;
			nllll <= 0;
			nlllO <= 0;
			nllOi <= 0;
			nllOl <= 0;
			nllOO <= 0;
			nlO0i <= 0;
			nlO0l <= 0;
			nlO0O <= 0;
			nlO1i <= 0;
			nlO1l <= 0;
			nlO1O <= 0;
			nlOii <= 0;
			nlOil <= 0;
			nlOiO <= 0;
		end
		else 
		if (rcvd_clk != niil_clk_prev && rcvd_clk == 1'b1) 
		begin
			n0Oi <= wire_nili_dataout;
			ni0l <= wire_nill_dataout;
			ni0O <= wire_nilO_dataout;
			niii <= wire_niOi_dataout;
			niiO <= wire_nliO_dataout;
			nlliO <= wire_nlOll_dataout;
			nllli <= wire_nlOlO_dataout;
			nllll <= wire_nlOOi_dataout;
			nlllO <= wire_nlOOl_dataout;
			nllOi <= wire_nlOOO_dataout;
			nllOl <= wire_n11i_dataout;
			nllOO <= wire_n11l_dataout;
			nlO0i <= wire_n10O_dataout;
			nlO0l <= wire_n1ii_dataout;
			nlO0O <= wire_n1il_dataout;
			nlO1i <= wire_n11O_dataout;
			nlO1l <= wire_n10i_dataout;
			nlO1O <= wire_n10l_dataout;
			nlOii <= wire_n1iO_dataout;
			nlOil <= wire_n1li_dataout;
			nlOiO <= wire_n0Ol_dataout;
		end
		niil_clk_prev <= rcvd_clk;
	end
	assign
		wire_niil_PRN = (n10Ol12 ^ n10Ol11);
	initial
	begin
		ni00O = 0;
		ni01i = 0;
		ni01l = 0;
		ni01O = 0;
		ni0ii = 0;
		ni0il = 0;
		ni0iO = 0;
		ni0li = 0;
		ni0ll = 0;
		ni0lO = 0;
		ni0Oi = 0;
		ni0Ol = 0;
		ni0OO = 0;
		ni10l = 0;
		ni10O = 0;
		ni11l = 0;
		ni11O = 0;
		ni1ii = 0;
		ni1il = 0;
		ni1iO = 0;
		ni1li = 0;
		ni1ll = 0;
		ni1lO = 0;
		ni1Oi = 0;
		ni1Ol = 0;
		ni1OO = 0;
		nii0i = 0;
		nii0l = 0;
		nii0O = 0;
		nii1i = 0;
		nii1l = 0;
		nii1O = 0;
		nl0ll = 0;
		nl0lO = 0;
		nl0Oi = 0;
		nl0Ol = 0;
		nl0OO = 0;
		nli0i = 0;
		nli0l = 0;
		nli0O = 0;
		nli1i = 0;
		nli1l = 0;
		nli1O = 0;
		nliii = 0;
		nliil = 0;
		nliiO = 0;
		nlili = 0;
		nlill = 0;
		nlilO = 0;
		nliOi = 0;
		nliOl = 0;
		nliOO = 0;
		nll0i = 0;
		nll0l = 0;
		nll0O = 0;
		nll1i = 0;
		nll1l = 0;
		nll1O = 0;
		nllii = 0;
		nlOi = 0;
	end
	always @ ( posedge clk_1 or  negedge wire_nllO_CLRN)
	begin
		if (wire_nllO_CLRN == 1'b0) 
		begin
			ni00O <= 0;
			ni01i <= 0;
			ni01l <= 0;
			ni01O <= 0;
			ni0ii <= 0;
			ni0il <= 0;
			ni0iO <= 0;
			ni0li <= 0;
			ni0ll <= 0;
			ni0lO <= 0;
			ni0Oi <= 0;
			ni0Ol <= 0;
			ni0OO <= 0;
			ni10l <= 0;
			ni10O <= 0;
			ni11l <= 0;
			ni11O <= 0;
			ni1ii <= 0;
			ni1il <= 0;
			ni1iO <= 0;
			ni1li <= 0;
			ni1ll <= 0;
			ni1lO <= 0;
			ni1Oi <= 0;
			ni1Ol <= 0;
			ni1OO <= 0;
			nii0i <= 0;
			nii0l <= 0;
			nii0O <= 0;
			nii1i <= 0;
			nii1l <= 0;
			nii1O <= 0;
			nl0ll <= 0;
			nl0lO <= 0;
			nl0Oi <= 0;
			nl0Ol <= 0;
			nl0OO <= 0;
			nli0i <= 0;
			nli0l <= 0;
			nli0O <= 0;
			nli1i <= 0;
			nli1l <= 0;
			nli1O <= 0;
			nliii <= 0;
			nliil <= 0;
			nliiO <= 0;
			nlili <= 0;
			nlill <= 0;
			nlilO <= 0;
			nliOi <= 0;
			nliOl <= 0;
			nliOO <= 0;
			nll0i <= 0;
			nll0l <= 0;
			nll0O <= 0;
			nll1i <= 0;
			nll1l <= 0;
			nll1O <= 0;
			nllii <= 0;
			nlOi <= 0;
		end
		else 
		begin
			ni00O <= wire_niliO_dataout;
			ni01i <= wire_nil0l_dataout;
			ni01l <= wire_nil0O_dataout;
			ni01O <= wire_nilii_dataout;
			ni0ii <= wire_nilli_dataout;
			ni0il <= wire_nilll_dataout;
			ni0iO <= wire_nillO_dataout;
			ni0li <= wire_nilOi_dataout;
			ni0ll <= wire_nilOl_dataout;
			ni0lO <= wire_nilOO_dataout;
			ni0Oi <= wire_niO1i_dataout;
			ni0Ol <= wire_niO1l_dataout;
			ni0OO <= wire_niO1O_dataout;
			ni10l <= wire_niiiO_dataout;
			ni10O <= wire_niili_dataout;
			ni11l <= niiO;
			ni11O <= wire_niiii_dataout;
			ni1ii <= wire_niill_dataout;
			ni1il <= wire_niilO_dataout;
			ni1iO <= wire_niiOi_dataout;
			ni1li <= wire_niiOl_dataout;
			ni1ll <= wire_niiOO_dataout;
			ni1lO <= wire_nil1i_dataout;
			ni1Oi <= wire_nil1l_dataout;
			ni1Ol <= wire_nil1O_dataout;
			ni1OO <= wire_nil0i_dataout;
			nii0i <= wire_niOii_dataout;
			nii0l <= wire_niOil_dataout;
			nii0O <= wire_n1iOi_data_out2[0];
			nii1i <= wire_niO0i_dataout;
			nii1l <= wire_niO0l_dataout;
			nii1O <= wire_niO0O_dataout;
			nl0ll <= wire_n1iOi_data_out2[1];
			nl0lO <= wire_n1iOi_data_out2[2];
			nl0Oi <= wire_n1iOi_data_out2[3];
			nl0Ol <= wire_n1iOi_data_out2[4];
			nl0OO <= wire_n1iOi_data_out2[5];
			nli0i <= wire_n1iOi_data_out2[9];
			nli0l <= wire_n1iOi_data_out2[10];
			nli0O <= wire_n1iOi_data_out2[11];
			nli1i <= wire_n1iOi_data_out2[6];
			nli1l <= wire_n1iOi_data_out2[7];
			nli1O <= wire_n1iOi_data_out2[8];
			nliii <= wire_n1iOi_data_out2[12];
			nliil <= wire_n1iOi_data_out2[13];
			nliiO <= wire_n1iOi_data_out1[0];
			nlili <= wire_n1iOi_data_out1[1];
			nlill <= wire_n1iOi_data_out1[2];
			nlilO <= wire_n1iOi_data_out1[3];
			nliOi <= wire_n1iOi_data_out1[4];
			nliOl <= wire_n1iOi_data_out1[5];
			nliOO <= wire_n1iOi_data_out1[6];
			nll0i <= wire_n1iOi_data_out1[10];
			nll0l <= wire_n1iOi_data_out1[11];
			nll0O <= wire_n1iOi_data_out1[12];
			nll1i <= wire_n1iOi_data_out1[7];
			nll1l <= wire_n1iOi_data_out1[8];
			nll1O <= wire_n1iOi_data_out1[9];
			nllii <= wire_n1iOi_data_out1[13];
			nlOi <= ni11l;
		end
	end
	assign
		wire_nllO_CLRN = ((n1i1O6 ^ n1i1O5) & (~ soft_reset));
	initial
	begin
		ni = 0;
		nlil = 0;
		nll = 0;
		nllil = 0;
	end
	always @ (rcvd_clk or soft_reset or wire_nlO_CLRN)
	begin
		if (soft_reset == 1'b1) 
		begin
			ni <= 1;
			nlil <= 1;
			nll <= 1;
			nllil <= 1;
		end
		else if  (wire_nlO_CLRN == 1'b0) 
		begin
			ni <= 0;
			nlil <= 0;
			nll <= 0;
			nllil <= 0;
		end
		else 
		if (rcvd_clk != nlO_clk_prev && rcvd_clk == 1'b1) 
		begin
			ni <= wire_nO_dataout;
			nlil <= nll;
			nll <= ni;
			nllil <= wire_nlOli_dataout;
		end
		nlO_clk_prev <= rcvd_clk;
	end
	assign
		wire_nlO_CLRN = (n1ili2 ^ n1ili1);
	assign		wire_n00i_dataout = (n10li === 1'b1) ? nllOO : nlO1i;
	assign		wire_n00l_dataout = (n10li === 1'b1) ? nlO1i : nlO1l;
	assign		wire_n00O_dataout = (n10li === 1'b1) ? nlO1l : nlO1O;
	assign		wire_n01i_dataout = (n10li === 1'b1) ? nlllO : nllOi;
	assign		wire_n01l_dataout = (n10li === 1'b1) ? nllOi : nllOl;
	assign		wire_n01O_dataout = (n10li === 1'b1) ? nllOl : nllOO;
	assign		wire_n0i_dataout = (rdskposdisp === 1'b1) ? rdskchrp[3] : (~ rdskchrp[3]);
	assign		wire_n0ii_dataout = (n10li === 1'b1) ? nlO1O : nlO0i;
	assign		wire_n0il_dataout = (n10li === 1'b1) ? nlO0i : nlO0l;
	assign		wire_n0iO_dataout = (n10li === 1'b1) ? nlO0l : nlO0O;
	assign		wire_n0l_dataout = (rdskposdisp === 1'b1) ? rdskchrp[4] : (~ rdskchrp[4]);
	assign		wire_n0li_dataout = (n10li === 1'b1) ? nlO0O : nlOii;
	assign		wire_n0ll_dataout = (n10li === 1'b1) ? nlOii : nlOil;
	assign		wire_n0O_dataout = (rdskposdisp === 1'b1) ? rdskchrp[5] : (~ rdskchrp[5]);
	and(wire_n0Ol_dataout, wire_n0OO_dataout, ~(n10ll));
	or(wire_n0OO_dataout, nlOiO, n1i0i);
	and(wire_n10i_dataout, wire_n00l_dataout, ~(n10ll));
	and(wire_n10l_dataout, wire_n00O_dataout, ~(n10ll));
	and(wire_n10O_dataout, wire_n0ii_dataout, ~(n10ll));
	and(wire_n11i_dataout, wire_n01l_dataout, ~(n10ll));
	and(wire_n11l_dataout, wire_n01O_dataout, ~(n10ll));
	and(wire_n11O_dataout, wire_n00i_dataout, ~(n10ll));
	assign		wire_n1i_dataout = (rdskposdisp === 1'b1) ? rdskchrp[0] : (~ rdskchrp[0]);
	and(wire_n1ii_dataout, wire_n0il_dataout, ~(n10ll));
	and(wire_n1il_dataout, wire_n0iO_dataout, ~(n10ll));
	and(wire_n1iO_dataout, wire_n0li_dataout, ~(n10ll));
	assign		wire_n1l_dataout = (rdskposdisp === 1'b1) ? rdskchrp[1] : (~ rdskchrp[1]);
	and(wire_n1li_dataout, wire_n0ll_dataout, ~(n10ll));
	assign		wire_n1ll_dataout = (n10li === 1'b1) ? nlOil : nllil;
	assign		wire_n1lO_dataout = (n10li === 1'b1) ? nllil : nlliO;
	assign		wire_n1O_dataout = (rdskposdisp === 1'b1) ? rdskchrp[2] : (~ rdskchrp[2]);
	assign		wire_n1Oi_dataout = (n10li === 1'b1) ? nlliO : nllli;
	assign		wire_n1Ol_dataout = (n10li === 1'b1) ? nllli : nllll;
	assign		wire_n1OO_dataout = (n10li === 1'b1) ? nllll : nlllO;
	assign		wire_nii_dataout = (rdskposdisp === 1'b1) ? rdskchrp[6] : (~ rdskchrp[6]);
	and(wire_niiii_dataout, wire_niOiO_dataout, ~(wire_nl_dataout));
	or(wire_niiil_dataout, wire_niOli_dataout, wire_nl_dataout);
	and(wire_niiiO_dataout, wire_niOll_dataout, ~(wire_nl_dataout));
	and(wire_niili_dataout, wire_niOlO_dataout, ~(wire_nl_dataout));
	and(wire_niill_dataout, wire_niOOi_dataout, ~(wire_nl_dataout));
	and(wire_niilO_dataout, wire_niOOl_dataout, ~(wire_nl_dataout));
	and(wire_niiOi_dataout, wire_niOOO_dataout, ~(wire_nl_dataout));
	and(wire_niiOl_dataout, wire_nl11i_dataout, ~(wire_nl_dataout));
	and(wire_niiOO_dataout, wire_nl11l_dataout, ~(wire_nl_dataout));
	assign		wire_nil_dataout = (rdskposdisp === 1'b1) ? rdskchrp[7] : (~ rdskchrp[7]);
	and(wire_nil0i_dataout, wire_nl10O_dataout, ~(wire_nl_dataout));
	and(wire_nil0l_dataout, wire_nl1ii_dataout, ~(wire_nl_dataout));
	and(wire_nil0O_dataout, wire_nl1il_dataout, ~(wire_nl_dataout));
	and(wire_nil1i_dataout, wire_nl11O_dataout, ~(wire_nl_dataout));
	and(wire_nil1l_dataout, wire_nl10i_dataout, ~(wire_nl_dataout));
	and(wire_nil1O_dataout, wire_nl10l_dataout, ~(wire_nl_dataout));
	and(wire_nili_dataout, wire_niOl_dataout, ~((~ nll)));
	and(wire_nilii_dataout, wire_nl1iO_dataout, ~(wire_nl_dataout));
	or(wire_nilil_dataout, wire_nl1li_dataout, wire_nl_dataout);
	and(wire_niliO_dataout, wire_nl1ll_dataout, ~(wire_nl_dataout));
	and(wire_nill_dataout, wire_niOO_dataout, ~((~ nll)));
	and(wire_nilli_dataout, wire_nl1lO_dataout, ~(wire_nl_dataout));
	and(wire_nilll_dataout, wire_nl1Oi_dataout, ~(wire_nl_dataout));
	and(wire_nillO_dataout, wire_nl1Ol_dataout, ~(wire_nl_dataout));
	and(wire_nilO_dataout, wire_nl1i_dataout, ~((~ nll)));
	and(wire_nilOi_dataout, wire_nl1OO_dataout, ~(wire_nl_dataout));
	and(wire_nilOl_dataout, wire_nl01i_dataout, ~(wire_nl_dataout));
	and(wire_nilOO_dataout, wire_nl01l_dataout, ~(wire_nl_dataout));
	assign		wire_niO_dataout = (rdskposdisp === 1'b1) ? rdskchrp[8] : (~ rdskchrp[8]);
	and(wire_niO0i_dataout, wire_nl00O_dataout, ~(wire_nl_dataout));
	and(wire_niO0l_dataout, wire_nl0ii_dataout, ~(wire_nl_dataout));
	and(wire_niO0O_dataout, wire_nl0il_dataout, ~(wire_nl_dataout));
	and(wire_niO1i_dataout, wire_nl01O_dataout, ~(wire_nl_dataout));
	and(wire_niO1l_dataout, wire_nl00i_dataout, ~(wire_nl_dataout));
	and(wire_niO1O_dataout, wire_nl00l_dataout, ~(wire_nl_dataout));
	and(wire_niOi_dataout, wire_nl1l_dataout, ~((~ nll)));
	and(wire_niOii_dataout, wire_nl0iO_dataout, ~(wire_nl_dataout));
	and(wire_niOil_dataout, wire_nl0li_dataout, ~(wire_nl_dataout));
	and(wire_niOiO_dataout, ni01O, (~ wire_nO_dataout));
	or(wire_niOl_dataout, wire_nl1O_dataout, n1i0i);
	or(wire_niOli_dataout, ni11O, ~((~ wire_nO_dataout)));
	and(wire_niOll_dataout, ni10i, (~ wire_nO_dataout));
	and(wire_niOlO_dataout, ni10l, (~ wire_nO_dataout));
	and(wire_niOO_dataout, wire_nl0i_dataout, ~(n1i0i));
	and(wire_niOOi_dataout, ni10O, (~ wire_nO_dataout));
	and(wire_niOOl_dataout, ni1ii, (~ wire_nO_dataout));
	and(wire_niOOO_dataout, ni1il, (~ wire_nO_dataout));
	assign		wire_nl_dataout = (sel_gp_md === 1'b1) ? fifo_rst_rd_gp : fifo_rst_rd_qd;
	and(wire_nl00i_dataout, ni0Oi, (~ wire_nO_dataout));
	and(wire_nl00l_dataout, ni0Ol, (~ wire_nO_dataout));
	and(wire_nl00O_dataout, ni0OO, (~ wire_nO_dataout));
	and(wire_nl01i_dataout, ni0li, (~ wire_nO_dataout));
	and(wire_nl01l_dataout, ni0ll, (~ wire_nO_dataout));
	and(wire_nl01O_dataout, ni0lO, (~ wire_nO_dataout));
	assign		wire_nl0i_dataout = ((~ n1i1l) === 1'b1) ? wire_nlii_o[2] : ni0l;
	and(wire_nl0ii_dataout, nii1i, (~ wire_nO_dataout));
	and(wire_nl0il_dataout, nii1l, (~ wire_nO_dataout));
	and(wire_nl0iO_dataout, nii1O, (~ wire_nO_dataout));
	assign		wire_nl0l_dataout = ((~ n1i1l) === 1'b1) ? wire_nlii_o[3] : ni0O;
	and(wire_nl0li_dataout, nii0i, (~ wire_nO_dataout));
	assign		wire_nl0O_dataout = ((~ n1i1l) === 1'b1) ? wire_nlii_o[4] : niii;
	and(wire_nl10i_dataout, ni1lO, (~ wire_nO_dataout));
	and(wire_nl10l_dataout, ni1Oi, (~ wire_nO_dataout));
	and(wire_nl10O_dataout, ni1Ol, (~ wire_nO_dataout));
	and(wire_nl11i_dataout, ni1iO, (~ wire_nO_dataout));
	and(wire_nl11l_dataout, ni1li, (~ wire_nO_dataout));
	and(wire_nl11O_dataout, ni1ll, (~ wire_nO_dataout));
	and(wire_nl1i_dataout, wire_nl0l_dataout, ~(n1i0i));
	and(wire_nl1ii_dataout, ni1OO, (~ wire_nO_dataout));
	and(wire_nl1il_dataout, ni01i, (~ wire_nO_dataout));
	and(wire_nl1iO_dataout, ni01l, (~ wire_nO_dataout));
	or(wire_nl1l_dataout, wire_nl0O_dataout, n1i0i);
	or(wire_nl1li_dataout, nii0l, ~((~ wire_nO_dataout)));
	and(wire_nl1ll_dataout, ni00l, (~ wire_nO_dataout));
	and(wire_nl1lO_dataout, ni00O, (~ wire_nO_dataout));
	assign		wire_nl1O_dataout = ((~ n1i1l) === 1'b1) ? wire_nlii_o[1] : n0Oi;
	and(wire_nl1Oi_dataout, ni0ii, (~ wire_nO_dataout));
	and(wire_nl1Ol_dataout, ni0il, (~ wire_nO_dataout));
	and(wire_nl1OO_dataout, ni0iO, (~ wire_nO_dataout));
	assign		wire_nli_dataout = (rdskposdisp === 1'b1) ? rdskchrp[9] : (~ rdskchrp[9]);
	or(wire_nliO_dataout, wire_nlli_dataout, n1i0i);
	and(wire_nlli_dataout, niiO, ~(n1i1l));
	or(wire_nlOli_dataout, wire_n1ll_dataout, n10ll);
	and(wire_nlOll_dataout, wire_n1lO_dataout, ~(n10ll));
	and(wire_nlOlO_dataout, wire_n1Oi_dataout, ~(n10ll));
	and(wire_nlOOi_dataout, wire_n1Ol_dataout, ~(n10ll));
	and(wire_nlOOl_dataout, wire_n1OO_dataout, ~(n10ll));
	and(wire_nlOOO_dataout, wire_n01i_dataout, ~(n10ll));
	assign		wire_nO_dataout = (sel_gp_md === 1'b1) ? en_dskw_gp : en_dskw_qd;
	oper_add   nlii
	( 
	.a({((n10OO10 ^ n10OO9) & niii), ((n1i1i8 ^ n1i1i7) & ni0O), ni0l, n0Oi, 1'b1}),
	.b({{3{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlii_o));
	defparam
		nlii.sgate_representation = 0,
		nlii.width_a = 5,
		nlii.width_b = 5,
		nlii.width_o = 5;
	arriagx_hssi_ram16x14_syn   n1iOi
	( 
	.addr_rd1({nii0l, nii0i, nii1O, nii1l, nii1i, ni0OO, ni0Ol, ni0Oi, ni0lO, ni0ll, ni0li, ni0iO, ni0il, ni0ii, ni00O, ni00l}),
	.addr_rd2({ni01O, ni01l, ni01i, ni1OO, ni1Ol, ni1Oi, ni1lO, ni1ll, ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni10i, ni11O}),
	.addr_wr({nlOil, nlOii, nlO0O, nlO0l, nlO0i, nlO1O, nlO1l, nlO1i, nllOO, nllOl, nllOi, nlllO, nllll, nllli, nlliO, nllil}),
	.clk(rcvd_clk),
	.data_in({sudi[13:0]}),
	.data_out1(wire_n1iOi_data_out1),
	.data_out2(wire_n1iOi_data_out2),
	.re_l(1'b0),
	.rst_l((~ soft_reset)),
	.we(1'b1));
	defparam
		n1iOi.ram_width = 14,
		n1iOi.read_access_time = 0,
		n1iOi.write_access_time = 0;
	assign
		align_det_sync = nlOi,
		audi = {nllii, nll0O, nll0l, nll0i, nll1O, nll1l, nll1i, nliOO, nliOl, nliOi, nlilO, nlill, nlili, nliiO},
		audi_pre = {nliil, nliii, nli0O, nli0l, nli0i, nli1O, nli1l, nli1i, nl0OO, nl0Ol, nl0Oi, nl0lO, nl0ll, nii0O},
		n10ii = ((((((((((((~ nll0O) & (~ nll0i)) & (~ (wire_n1i_dataout ^ nliiO))) & (~ (wire_n1l_dataout ^ nlili))) & (~ (wire_n1O_dataout ^ nlill))) & (~ (wire_n0i_dataout ^ nlilO))) & (~ (wire_n0l_dataout ^ nliOi))) & (~ (wire_n0O_dataout ^ nliOl))) & (~ (wire_nii_dataout ^ nliOO))) & (~ (wire_nil_dataout ^ nll1i))) & (~ (wire_niO_dataout ^ nll1l))) & (~ (wire_nli_dataout ^ nll1O))),
		n10il = ((((((((((((~ nll0O) & (~ nll0i)) & (~ ((nliiO ^ rdskchrp[0]) ^ (~ (nlOOOi40 ^ nlOOOi39))))) & (~ (nlili ^ rdskchrp[1]))) & (~ (nlill ^ rdskchrp[2]))) & (~ (nlilO ^ rdskchrp[3]))) & (~ (nliOi ^ rdskchrp[4]))) & (~ ((nliOl ^ rdskchrp[5]) ^ (~ (nlOOll42 ^ nlOOll41))))) & (~ (nliOO ^ rdskchrp[6]))) & (~ ((nll1i ^ rdskchrp[7]) ^ (~ (nlOOiO44 ^ nlOOiO43))))) & (~ ((nll1l ^ rdskchrp[8]) ^ (~ (nlOOii46 ^ nlOOii45))))) & (~ ((nll1O ^ rdskchrp[9]) ^ (~ (nlOO0l48 ^ nlOO0l47))))),
		n10li = (n1i0i | nlOiO),
		n10ll = (((nll & (nlOiO & nlOil)) | (nll & (~ nlil))) | (~ (n10lO14 ^ n10lO13))),
		n1i0i = (nll & ((n1iil | n1iii) | (~ (n1i0l4 ^ n1i0l3)))),
		n1i1l = ((((~ niii) & (~ ni0O)) & (~ ni0l)) & (~ n0Oi)),
		n1iii = (((((((((((((~ sudi[10]) & (~ sudi[12])) & (~ ((wire_n1i_dataout ^ sudi[0]) ^ (~ (n11il30 ^ n11il29))))) & (~ (wire_n1l_dataout ^ sudi[1]))) & (~ ((wire_n1O_dataout ^ sudi[2]) ^ (~ (n110O32 ^ n110O31))))) & (~ (wire_n0i_dataout ^ sudi[3]))) & (~ ((wire_n0l_dataout ^ sudi[4]) ^ (~ (n110i34 ^ n110i33))))) & (~ (wire_n0O_dataout ^ sudi[5]))) & (~ (wire_nii_dataout ^ sudi[6]))) & (~ ((wire_nil_dataout ^ sudi[7]) ^ (~ (n111l36 ^ n111l35))))) & (~ (wire_niO_dataout ^ sudi[8]))) & (~ (wire_nli_dataout ^ sudi[9]))) & (nlOOOO38 ^ nlOOOO37)),
		n1iil = (((((((((((((~ sudi[10]) & (~ sudi[12])) & (~ (sudi[0] ^ rdskchrp[0]))) & (~ (sudi[1] ^ rdskchrp[1]))) & (~ (sudi[2] ^ rdskchrp[2]))) & (~ ((sudi[3] ^ rdskchrp[3]) ^ (~ (n101O20 ^ n101O19))))) & (~ ((sudi[4] ^ rdskchrp[4]) ^ (~ (n101i22 ^ n101i21))))) & (~ (sudi[5] ^ rdskchrp[5]))) & (~ (sudi[6] ^ rdskchrp[6]))) & (~ ((sudi[7] ^ rdskchrp[7]) ^ (~ (n11Ol24 ^ n11Ol23))))) & (~ (sudi[8] ^ rdskchrp[8]))) & (~ ((sudi[9] ^ rdskchrp[9]) ^ (~ (n11lO26 ^ n11lO25))))) & (n11li28 ^ n11li27)),
		n1iiO = 1'b1,
		rd_align = ((n10il | n10ii) | (~ (n100l18 ^ n100l17)));
endmodule //arriagx_hssi_rx_dskw_fifo
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 121 mux21 90 oper_add 4 oper_less_than 12 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_freqdet
	( 
	fref,
	freq_lock,
	fvcobyn,
	hard_reset,
	pd,
	ppm_cnt_latch,
	ppm_cnt_reset,
	ppmsel,
	rforcehigh,
	rforcelow,
	scan_mode) /* synthesis synthesis_clearbox=1 */;
	input   fref;
	output   freq_lock;
	input   fvcobyn;
	input   hard_reset;
	input   pd;
	output   [6:0]  ppm_cnt_latch;
	input   ppm_cnt_reset;
	input   [5:0]  ppmsel;
	input   rforcehigh;
	input   rforcelow;
	input   scan_mode;

	reg	n000i31;
	reg	n000i32;
	reg	n000O29;
	reg	n000O30;
	reg	n001O33;
	reg	n001O34;
	reg	n00iO27;
	reg	n00iO28;
	reg	n00li25;
	reg	n00li26;
	reg	n00ll23;
	reg	n00ll24;
	reg	n00lO21;
	reg	n00lO22;
	reg	n00Oi19;
	reg	n00Oi20;
	reg	n00Ol17;
	reg	n00Ol18;
	reg	n00OO15;
	reg	n00OO16;
	reg	n01ii47;
	reg	n01ii48;
	reg	n01iO45;
	reg	n01iO46;
	reg	n01li43;
	reg	n01li44;
	reg	n01ll41;
	reg	n01ll42;
	reg	n01lO39;
	reg	n01lO40;
	reg	n01Oi37;
	reg	n01Oi38;
	reg	n01OO35;
	reg	n01OO36;
	reg	n0i0i7;
	reg	n0i0i8;
	reg	n0i0O5;
	reg	n0i0O6;
	reg	n0i1i13;
	reg	n0i1i14;
	reg	n0i1l11;
	reg	n0i1l12;
	reg	n0i1O10;
	reg	n0i1O9;
	reg	n0iil3;
	reg	n0iil4;
	reg	n0ill1;
	reg	n0ill2;
	reg	n1OiO49;
	reg	n1OiO50;
	reg	n0i;
	reg	nii;
	reg	n0O_clk_prev;
	wire	wire_n0O_CLRN;
	reg	n1O;
	reg	nlOl;
	wire	wire_n1l_PRN;
	reg	ni1lO;
	reg	ni1ll_clk_prev;
	wire	wire_ni1ll_PRN;
	reg	nl00O;
	reg	nlil;
	reg	niOi;
	reg	nl1l;
	reg	nliiO;
	reg	nlili;
	reg	nlill;
	reg	nlilO;
	reg	nliOi;
	reg	nliOl;
	reg	nliOO;
	reg	nll0i;
	reg	nll0l;
	reg	nll0O;
	reg	nll1i;
	reg	nll1l;
	reg	nll1O;
	reg	nlli;
	reg	nllii;
	reg	nllil;
	reg	nlliO;
	wire	wire_nliO_CLRN;
	reg	n01i;
	reg	n10i;
	reg	n10l;
	reg	n10O;
	reg	n11i;
	reg	n11l;
	reg	n11O;
	reg	n1ii;
	reg	n1il;
	reg	n1iO;
	reg	n1li;
	reg	n1ll;
	reg	n1lO;
	reg	n1Oi;
	reg	n1Ol;
	reg	n1OO;
	reg	ni0l;
	reg	ni0lO;
	reg	ni0O;
	reg	ni0OO;
	reg	ni10l;
	reg	ni10O;
	reg	ni1ii;
	reg	ni1il;
	reg	ni1iO;
	reg	ni1li;
	reg	nilO;
	reg	niO0i;
	reg	niO0l;
	reg	niO0O;
	reg	niO1l;
	reg	niO1O;
	reg	niOii;
	reg	niOil;
	reg	nl01i;
	reg	nl01l;
	reg	nl01O;
	reg	nl0i;
	reg	nl0l;
	reg	nl0O;
	reg	nl1O;
	reg	nllO;
	reg	nlOOO;
	reg	nlll_clk_prev;
	wire	wire_nlll_PRN;
	reg	nl00i;
	reg	nllll;
	wire	wire_n00i_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n1i_dataout;
	wire	wire_ni00i_dataout;
	wire	wire_ni00l_dataout;
	wire	wire_ni00O_dataout;
	wire	wire_ni01i_dataout;
	wire	wire_ni01l_dataout;
	wire	wire_ni01O_dataout;
	wire	wire_ni0ii_dataout;
	wire	wire_ni0il_dataout;
	wire	wire_ni0iO_dataout;
	wire	wire_ni0li_dataout;
	wire	wire_ni0ll_dataout;
	wire	wire_ni10i_dataout;
	wire	wire_ni11O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_ni1Oi_dataout;
	wire	wire_ni1Ol_dataout;
	wire	wire_ni1OO_dataout;
	wire	wire_niOiO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOli_dataout;
	wire	wire_niOll_dataout;
	wire	wire_niOlO_dataout;
	wire	wire_niOO_dataout;
	wire	wire_niOOi_dataout;
	wire	wire_niOOl_dataout;
	wire	wire_niOOO_dataout;
	wire	wire_nl0ii_dataout;
	wire	wire_nl0il_dataout;
	wire	wire_nl0iO_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0ll_dataout;
	wire	wire_nl0lO_dataout;
	wire	wire_nl0Oi_dataout;
	wire	wire_nl0Ol_dataout;
	wire	wire_nl0OO_dataout;
	wire	wire_nl10i_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl10O_dataout;
	wire	wire_nl11i_dataout;
	wire	wire_nl11l_dataout;
	wire	wire_nl11O_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1ii_dataout;
	wire	wire_nl1il_dataout;
	wire	wire_nl1iO_dataout;
	wire	wire_nl1li_dataout;
	wire	wire_nl1ll_dataout;
	wire	wire_nl1lO_dataout;
	wire	wire_nl1Oi_dataout;
	wire	wire_nl1Ol_dataout;
	wire	wire_nli0i_dataout;
	wire	wire_nli0l_dataout;
	wire	wire_nli1i_dataout;
	wire	wire_nli1l_dataout;
	wire	wire_nli1O_dataout;
	wire	wire_nlllO_dataout;
	wire	wire_nllOi_dataout;
	wire	wire_nllOl_dataout;
	wire	wire_nllOO_dataout;
	wire	wire_nlO0i_dataout;
	wire	wire_nlO0l_dataout;
	wire	wire_nlO0O_dataout;
	wire	wire_nlO1i_dataout;
	wire	wire_nlO1l_dataout;
	wire	wire_nlO1O_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOli_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOOi_dataout;
	wire  [15:0]   wire_ni0i_o;
	wire  [6:0]   wire_nl1OO_o;
	wire  [4:0]   wire_nli0O_o;
	wire  [15:0]   wire_nlOOl_o;
	wire  wire_nii1O_o;
	wire  wire_niiii_o;
	wire  wire_niill_o;
	wire  wire_niiOO_o;
	wire  wire_nil0i_o;
	wire  wire_nili_o;
	wire  wire_nilil_o;
	wire  wire_nill_o;
	wire  wire_nillO_o;
	wire  wire_nilOO_o;
	wire  wire_nlOi_o;
	wire  wire_nlOO_o;
	wire  n001l;
	wire  n00il;
	wire  n010i;
	wire  n010l;
	wire  n010O;
	wire  n011i;
	wire  n011l;
	wire  n011O;
	wire  n0i0l;
	wire  n0iii;
	wire  n0ili;
	wire  n1Oli;
	wire  n1Oll;
	wire  n1OlO;
	wire  n1OOi;
	wire  n1OOl;
	wire  n1OOO;

	initial
		n000i31 = 0;
	always @ ( posedge fref)
		  n000i31 <= n000i32;
	event n000i31_event;
	initial
		#1 ->n000i31_event;
	always @(n000i31_event)
		n000i31 <= {1{1'b1}};
	initial
		n000i32 = 0;
	always @ ( posedge fref)
		  n000i32 <= n000i31;
	initial
		n000O29 = 0;
	always @ ( posedge fref)
		  n000O29 <= n000O30;
	event n000O29_event;
	initial
		#1 ->n000O29_event;
	always @(n000O29_event)
		n000O29 <= {1{1'b1}};
	initial
		n000O30 = 0;
	always @ ( posedge fref)
		  n000O30 <= n000O29;
	initial
		n001O33 = 0;
	always @ ( posedge fref)
		  n001O33 <= n001O34;
	event n001O33_event;
	initial
		#1 ->n001O33_event;
	always @(n001O33_event)
		n001O33 <= {1{1'b1}};
	initial
		n001O34 = 0;
	always @ ( posedge fref)
		  n001O34 <= n001O33;
	initial
		n00iO27 = 0;
	always @ ( posedge fref)
		  n00iO27 <= n00iO28;
	event n00iO27_event;
	initial
		#1 ->n00iO27_event;
	always @(n00iO27_event)
		n00iO27 <= {1{1'b1}};
	initial
		n00iO28 = 0;
	always @ ( posedge fref)
		  n00iO28 <= n00iO27;
	initial
		n00li25 = 0;
	always @ ( posedge fref)
		  n00li25 <= n00li26;
	event n00li25_event;
	initial
		#1 ->n00li25_event;
	always @(n00li25_event)
		n00li25 <= {1{1'b1}};
	initial
		n00li26 = 0;
	always @ ( posedge fref)
		  n00li26 <= n00li25;
	initial
		n00ll23 = 0;
	always @ ( posedge fref)
		  n00ll23 <= n00ll24;
	event n00ll23_event;
	initial
		#1 ->n00ll23_event;
	always @(n00ll23_event)
		n00ll23 <= {1{1'b1}};
	initial
		n00ll24 = 0;
	always @ ( posedge fref)
		  n00ll24 <= n00ll23;
	initial
		n00lO21 = 0;
	always @ ( posedge fref)
		  n00lO21 <= n00lO22;
	event n00lO21_event;
	initial
		#1 ->n00lO21_event;
	always @(n00lO21_event)
		n00lO21 <= {1{1'b1}};
	initial
		n00lO22 = 0;
	always @ ( posedge fref)
		  n00lO22 <= n00lO21;
	initial
		n00Oi19 = 0;
	always @ ( posedge fref)
		  n00Oi19 <= n00Oi20;
	event n00Oi19_event;
	initial
		#1 ->n00Oi19_event;
	always @(n00Oi19_event)
		n00Oi19 <= {1{1'b1}};
	initial
		n00Oi20 = 0;
	always @ ( posedge fref)
		  n00Oi20 <= n00Oi19;
	initial
		n00Ol17 = 0;
	always @ ( posedge fref)
		  n00Ol17 <= n00Ol18;
	event n00Ol17_event;
	initial
		#1 ->n00Ol17_event;
	always @(n00Ol17_event)
		n00Ol17 <= {1{1'b1}};
	initial
		n00Ol18 = 0;
	always @ ( posedge fref)
		  n00Ol18 <= n00Ol17;
	initial
		n00OO15 = 0;
	always @ ( posedge fref)
		  n00OO15 <= n00OO16;
	event n00OO15_event;
	initial
		#1 ->n00OO15_event;
	always @(n00OO15_event)
		n00OO15 <= {1{1'b1}};
	initial
		n00OO16 = 0;
	always @ ( posedge fref)
		  n00OO16 <= n00OO15;
	initial
		n01ii47 = 0;
	always @ ( posedge fref)
		  n01ii47 <= n01ii48;
	event n01ii47_event;
	initial
		#1 ->n01ii47_event;
	always @(n01ii47_event)
		n01ii47 <= {1{1'b1}};
	initial
		n01ii48 = 0;
	always @ ( posedge fref)
		  n01ii48 <= n01ii47;
	initial
		n01iO45 = 0;
	always @ ( posedge fref)
		  n01iO45 <= n01iO46;
	event n01iO45_event;
	initial
		#1 ->n01iO45_event;
	always @(n01iO45_event)
		n01iO45 <= {1{1'b1}};
	initial
		n01iO46 = 0;
	always @ ( posedge fref)
		  n01iO46 <= n01iO45;
	initial
		n01li43 = 0;
	always @ ( posedge fref)
		  n01li43 <= n01li44;
	event n01li43_event;
	initial
		#1 ->n01li43_event;
	always @(n01li43_event)
		n01li43 <= {1{1'b1}};
	initial
		n01li44 = 0;
	always @ ( posedge fref)
		  n01li44 <= n01li43;
	initial
		n01ll41 = 0;
	always @ ( posedge fref)
		  n01ll41 <= n01ll42;
	event n01ll41_event;
	initial
		#1 ->n01ll41_event;
	always @(n01ll41_event)
		n01ll41 <= {1{1'b1}};
	initial
		n01ll42 = 0;
	always @ ( posedge fref)
		  n01ll42 <= n01ll41;
	initial
		n01lO39 = 0;
	always @ ( posedge fref)
		  n01lO39 <= n01lO40;
	event n01lO39_event;
	initial
		#1 ->n01lO39_event;
	always @(n01lO39_event)
		n01lO39 <= {1{1'b1}};
	initial
		n01lO40 = 0;
	always @ ( posedge fref)
		  n01lO40 <= n01lO39;
	initial
		n01Oi37 = 0;
	always @ ( posedge fref)
		  n01Oi37 <= n01Oi38;
	event n01Oi37_event;
	initial
		#1 ->n01Oi37_event;
	always @(n01Oi37_event)
		n01Oi37 <= {1{1'b1}};
	initial
		n01Oi38 = 0;
	always @ ( posedge fref)
		  n01Oi38 <= n01Oi37;
	initial
		n01OO35 = 0;
	always @ ( posedge fref)
		  n01OO35 <= n01OO36;
	event n01OO35_event;
	initial
		#1 ->n01OO35_event;
	always @(n01OO35_event)
		n01OO35 <= {1{1'b1}};
	initial
		n01OO36 = 0;
	always @ ( posedge fref)
		  n01OO36 <= n01OO35;
	initial
		n0i0i7 = 0;
	always @ ( posedge fref)
		  n0i0i7 <= n0i0i8;
	event n0i0i7_event;
	initial
		#1 ->n0i0i7_event;
	always @(n0i0i7_event)
		n0i0i7 <= {1{1'b1}};
	initial
		n0i0i8 = 0;
	always @ ( posedge fref)
		  n0i0i8 <= n0i0i7;
	initial
		n0i0O5 = 0;
	always @ ( posedge fref)
		  n0i0O5 <= n0i0O6;
	event n0i0O5_event;
	initial
		#1 ->n0i0O5_event;
	always @(n0i0O5_event)
		n0i0O5 <= {1{1'b1}};
	initial
		n0i0O6 = 0;
	always @ ( posedge fref)
		  n0i0O6 <= n0i0O5;
	initial
		n0i1i13 = 0;
	always @ ( posedge fref)
		  n0i1i13 <= n0i1i14;
	event n0i1i13_event;
	initial
		#1 ->n0i1i13_event;
	always @(n0i1i13_event)
		n0i1i13 <= {1{1'b1}};
	initial
		n0i1i14 = 0;
	always @ ( posedge fref)
		  n0i1i14 <= n0i1i13;
	initial
		n0i1l11 = 0;
	always @ ( posedge fref)
		  n0i1l11 <= n0i1l12;
	event n0i1l11_event;
	initial
		#1 ->n0i1l11_event;
	always @(n0i1l11_event)
		n0i1l11 <= {1{1'b1}};
	initial
		n0i1l12 = 0;
	always @ ( posedge fref)
		  n0i1l12 <= n0i1l11;
	initial
		n0i1O10 = 0;
	always @ ( posedge fref)
		  n0i1O10 <= n0i1O9;
	initial
		n0i1O9 = 0;
	always @ ( posedge fref)
		  n0i1O9 <= n0i1O10;
	event n0i1O9_event;
	initial
		#1 ->n0i1O9_event;
	always @(n0i1O9_event)
		n0i1O9 <= {1{1'b1}};
	initial
		n0iil3 = 0;
	always @ ( posedge fref)
		  n0iil3 <= n0iil4;
	event n0iil3_event;
	initial
		#1 ->n0iil3_event;
	always @(n0iil3_event)
		n0iil3 <= {1{1'b1}};
	initial
		n0iil4 = 0;
	always @ ( posedge fref)
		  n0iil4 <= n0iil3;
	initial
		n0ill1 = 0;
	always @ ( posedge fref)
		  n0ill1 <= n0ill2;
	event n0ill1_event;
	initial
		#1 ->n0ill1_event;
	always @(n0ill1_event)
		n0ill1 <= {1{1'b1}};
	initial
		n0ill2 = 0;
	always @ ( posedge fref)
		  n0ill2 <= n0ill1;
	initial
		n1OiO49 = 0;
	always @ ( posedge fref)
		  n1OiO49 <= n1OiO50;
	event n1OiO49_event;
	initial
		#1 ->n1OiO49_event;
	always @(n1OiO49_event)
		n1OiO49 <= {1{1'b1}};
	initial
		n1OiO50 = 0;
	always @ ( posedge fref)
		  n1OiO50 <= n1OiO49;
	initial
	begin
		n0i = 0;
		nii = 0;
	end
	always @ (fref or hard_reset or wire_n0O_CLRN)
	begin
		if (hard_reset == 1'b0) 
		begin
			n0i <= 1;
			nii <= 1;
		end
		else if  (wire_n0O_CLRN == 1'b0) 
		begin
			n0i <= 0;
			nii <= 0;
		end
		else 
		if (fref != n0O_clk_prev && fref == 1'b1) 
		begin
			n0i <= nii;
			nii <= pd;
		end
		n0O_clk_prev <= fref;
	end
	assign
		wire_n0O_CLRN = (n0i0O6 ^ n0i0O5);
	initial
	begin
		n1O = 0;
		nlOl = 0;
	end
	always @ ( posedge fvcobyn or  negedge wire_n1l_PRN)
	begin
		if (wire_n1l_PRN == 1'b0) 
		begin
			n1O <= 1;
			nlOl <= 1;
		end
		else 
		begin
			n1O <= pd;
			nlOl <= n1O;
		end
	end
	assign
		wire_n1l_PRN = ((n0i0i8 ^ n0i0i7) & hard_reset);
	initial
	begin
		ni1lO = 0;
	end
	always @ (fref or wire_ni1ll_PRN or wire_n0l_dataout)
	begin
		if (wire_ni1ll_PRN == 1'b0) 
		begin
			ni1lO <= 1;
		end
		else if  (wire_n0l_dataout == 1'b1) 
		begin
			ni1lO <= 0;
		end
		else if  (n0iii == 1'b1) 
		if (fref != ni1ll_clk_prev && fref == 1'b1) 
		begin
			ni1lO <= ((((((((((n0iii & n011O) & wire_nilOO_o) | ((n0iii & n011l) & wire_nillO_o)) | ((n0iii & n011i) & wire_nilil_o)) | ((n0iii & n1OOO) & wire_nil0i_o)) | ((n0iii & n1OOl) & wire_niiOO_o)) | ((n0iii & n1OOi) & wire_niill_o)) | ((n0iii & n1OlO) & wire_niiii_o)) | ((n0iii & n1Oll) & wire_nii1O_o)) | (n0iii & n1Oli));
		end
		ni1ll_clk_prev <= fref;
	end
	assign
		wire_ni1ll_PRN = (n1OiO50 ^ n1OiO49);
	initial
	begin
		nl00O = 0;
	end
	always @ ( posedge fvcobyn or  posedge wire_n1i_dataout)
	begin
		if (wire_n1i_dataout == 1'b1) 
		begin
			nl00O <= 1;
		end
		else 
		begin
			nl00O <= wire_nlllO_dataout;
		end
	end
	initial
	begin
		nlil = 0;
	end
	always @ ( posedge fvcobyn or  posedge wire_n1i_dataout)
	begin
		if (wire_n1i_dataout == 1'b1) 
		begin
			nlil <= 0;
		end
		else if  (n00il == 1'b1) 
		begin
			nlil <= n0i0l;
		end
	end
	initial
	begin
		niOi = 0;
		nl1l = 0;
		nliiO = 0;
		nlili = 0;
		nlill = 0;
		nlilO = 0;
		nliOi = 0;
		nliOl = 0;
		nliOO = 0;
		nll0i = 0;
		nll0l = 0;
		nll0O = 0;
		nll1i = 0;
		nll1l = 0;
		nll1O = 0;
		nlli = 0;
		nllii = 0;
		nllil = 0;
		nlliO = 0;
	end
	always @ ( posedge fvcobyn or  negedge wire_nliO_CLRN)
	begin
		if (wire_nliO_CLRN == 1'b0) 
		begin
			niOi <= 0;
			nl1l <= 0;
			nliiO <= 0;
			nlili <= 0;
			nlill <= 0;
			nlilO <= 0;
			nliOi <= 0;
			nliOl <= 0;
			nliOO <= 0;
			nll0i <= 0;
			nll0l <= 0;
			nll0O <= 0;
			nll1i <= 0;
			nll1l <= 0;
			nll1O <= 0;
			nlli <= 0;
			nllii <= 0;
			nllil <= 0;
			nlliO <= 0;
		end
		else 
		begin
			niOi <= nl1l;
			nl1l <= ni0l;
			nliiO <= wire_nllOi_dataout;
			nlili <= wire_nllOl_dataout;
			nlill <= wire_nllOO_dataout;
			nlilO <= wire_nlO1i_dataout;
			nliOi <= wire_nlO1l_dataout;
			nliOl <= wire_nlO1O_dataout;
			nliOO <= wire_nlO0i_dataout;
			nll0i <= wire_nlOil_dataout;
			nll0l <= wire_nlOiO_dataout;
			nll0O <= wire_nlOli_dataout;
			nll1i <= wire_nlO0l_dataout;
			nll1l <= wire_nlO0O_dataout;
			nll1O <= wire_nlOii_dataout;
			nlli <= wire_nlOi_o;
			nllii <= wire_nlOll_dataout;
			nllil <= wire_nlOlO_dataout;
			nlliO <= wire_nlOOi_dataout;
		end
	end
	assign
		wire_nliO_CLRN = ((n00iO28 ^ n00iO27) & (~ wire_n1i_dataout));
	initial
	begin
		n01i = 0;
		n10i = 0;
		n10l = 0;
		n10O = 0;
		n11i = 0;
		n11l = 0;
		n11O = 0;
		n1ii = 0;
		n1il = 0;
		n1iO = 0;
		n1li = 0;
		n1ll = 0;
		n1lO = 0;
		n1Oi = 0;
		n1Ol = 0;
		n1OO = 0;
		ni0l = 0;
		ni0lO = 0;
		ni0O = 0;
		ni0OO = 0;
		ni10l = 0;
		ni10O = 0;
		ni1ii = 0;
		ni1il = 0;
		ni1iO = 0;
		ni1li = 0;
		nilO = 0;
		niO0i = 0;
		niO0l = 0;
		niO0O = 0;
		niO1l = 0;
		niO1O = 0;
		niOii = 0;
		niOil = 0;
		nl01i = 0;
		nl01l = 0;
		nl01O = 0;
		nl0i = 0;
		nl0l = 0;
		nl0O = 0;
		nl1O = 0;
		nllO = 0;
		nlOOO = 0;
	end
	always @ (fref or wire_nlll_PRN or wire_n0l_dataout)
	begin
		if (wire_nlll_PRN == 1'b0) 
		begin
			n01i <= 1;
			n10i <= 1;
			n10l <= 1;
			n10O <= 1;
			n11i <= 1;
			n11l <= 1;
			n11O <= 1;
			n1ii <= 1;
			n1il <= 1;
			n1iO <= 1;
			n1li <= 1;
			n1ll <= 1;
			n1lO <= 1;
			n1Oi <= 1;
			n1Ol <= 1;
			n1OO <= 1;
			ni0l <= 1;
			ni0lO <= 1;
			ni0O <= 1;
			ni0OO <= 1;
			ni10l <= 1;
			ni10O <= 1;
			ni1ii <= 1;
			ni1il <= 1;
			ni1iO <= 1;
			ni1li <= 1;
			nilO <= 1;
			niO0i <= 1;
			niO0l <= 1;
			niO0O <= 1;
			niO1l <= 1;
			niO1O <= 1;
			niOii <= 1;
			niOil <= 1;
			nl01i <= 1;
			nl01l <= 1;
			nl01O <= 1;
			nl0i <= 1;
			nl0l <= 1;
			nl0O <= 1;
			nl1O <= 1;
			nllO <= 1;
			nlOOO <= 1;
		end
		else if  (wire_n0l_dataout == 1'b1) 
		begin
			n01i <= 0;
			n10i <= 0;
			n10l <= 0;
			n10O <= 0;
			n11i <= 0;
			n11l <= 0;
			n11O <= 0;
			n1ii <= 0;
			n1il <= 0;
			n1iO <= 0;
			n1li <= 0;
			n1ll <= 0;
			n1lO <= 0;
			n1Oi <= 0;
			n1Ol <= 0;
			n1OO <= 0;
			ni0l <= 0;
			ni0lO <= 0;
			ni0O <= 0;
			ni0OO <= 0;
			ni10l <= 0;
			ni10O <= 0;
			ni1ii <= 0;
			ni1il <= 0;
			ni1iO <= 0;
			ni1li <= 0;
			nilO <= 0;
			niO0i <= 0;
			niO0l <= 0;
			niO0O <= 0;
			niO1l <= 0;
			niO1O <= 0;
			niOii <= 0;
			niOil <= 0;
			nl01i <= 0;
			nl01l <= 0;
			nl01O <= 0;
			nl0i <= 0;
			nl0l <= 0;
			nl0O <= 0;
			nl1O <= 0;
			nllO <= 0;
			nlOOO <= 0;
		end
		else 
		if (fref != nlll_clk_prev && fref == 1'b1) 
		begin
			n01i <= ni0l;
			n10i <= wire_n0ii_dataout;
			n10l <= wire_n0il_dataout;
			n10O <= wire_n0iO_dataout;
			n11i <= wire_n00i_dataout;
			n11l <= wire_n00l_dataout;
			n11O <= wire_n00O_dataout;
			n1ii <= wire_n0li_dataout;
			n1il <= wire_n0ll_dataout;
			n1iO <= wire_n0lO_dataout;
			n1li <= wire_n0Oi_dataout;
			n1ll <= wire_n0Ol_dataout;
			n1lO <= wire_n0OO_dataout;
			n1Oi <= wire_ni1i_dataout;
			n1Ol <= wire_ni1l_dataout;
			n1OO <= wire_ni1O_dataout;
			ni0l <= ((((wire_nill_o & wire_nili_o) & (n01OO36 ^ n01OO35)) | n001l) | (~ (n01Oi38 ^ n01Oi37)));
			ni0lO <= wire_niOiO_dataout;
			ni0O <= wire_niOl_dataout;
			ni0OO <= wire_ni1Oi_dataout;
			ni10l <= wire_ni1Ol_dataout;
			ni10O <= wire_ni1OO_dataout;
			ni1ii <= wire_ni01i_dataout;
			ni1il <= wire_ni01l_dataout;
			ni1iO <= wire_ni01O_dataout;
			ni1li <= wire_ni00i_dataout;
			nilO <= wire_niOO_dataout;
			niO0i <= wire_niOlO_dataout;
			niO0l <= wire_niOOi_dataout;
			niO0O <= wire_niOOl_dataout;
			niO1l <= wire_niOli_dataout;
			niO1O <= wire_niOll_dataout;
			niOii <= wire_niOOO_dataout;
			niOil <= wire_nl0ii_dataout;
			nl01i <= wire_nl0il_dataout;
			nl01l <= wire_nl0iO_dataout;
			nl01O <= wire_nl0li_dataout;
			nl0i <= nlli;
			nl0l <= nl0O;
			nl0O <= nlil;
			nl1O <= nl0i;
			nllO <= wire_nlOO_o;
			nlOOO <= wire_n01O_dataout;
		end
		nlll_clk_prev <= fref;
	end
	assign
		wire_nlll_PRN = (n00li26 ^ n00li25);
	initial
	begin
		nl00i = 0;
		nllll = 0;
	end
	always @ ( posedge fref or  posedge wire_n0l_dataout)
	begin
		if (wire_n0l_dataout == 1'b1) 
		begin
			nl00i <= 1;
			nllll <= 1;
		end
		else 
		begin
			nl00i <= wire_nl0ll_dataout;
			nllll <= wire_n01l_dataout;
		end
	end
	and(wire_n00i_dataout, wire_ni0i_o[1], ~(n01i));
	and(wire_n00l_dataout, wire_ni0i_o[2], ~(n01i));
	and(wire_n00O_dataout, wire_ni0i_o[3], ~(n01i));
	or(wire_n01l_dataout, (~ n1OO), n01i);
	and(wire_n01O_dataout, wire_ni0i_o[0], ~(n01i));
	and(wire_n0ii_dataout, wire_ni0i_o[4], ~(n01i));
	and(wire_n0il_dataout, wire_ni0i_o[5], ~(n01i));
	and(wire_n0iO_dataout, wire_ni0i_o[6], ~(n01i));
	and(wire_n0l_dataout, n0i, ~(scan_mode));
	and(wire_n0li_dataout, wire_ni0i_o[7], ~(n01i));
	and(wire_n0ll_dataout, wire_ni0i_o[8], ~(n01i));
	and(wire_n0lO_dataout, wire_ni0i_o[9], ~(n01i));
	and(wire_n0Oi_dataout, wire_ni0i_o[10], ~(n01i));
	and(wire_n0Ol_dataout, wire_ni0i_o[11], ~(n01i));
	and(wire_n0OO_dataout, wire_ni0i_o[12], ~(n01i));
	and(wire_n1i_dataout, nlOl, ~(scan_mode));
	and(wire_ni00i_dataout, wire_ni0ll_dataout, ~(ppm_cnt_reset));
	assign		wire_ni00l_dataout = (n0iii === 1'b1) ? ni0lO : ni0OO;
	assign		wire_ni00O_dataout = (n0iii === 1'b1) ? niO1l : ni10l;
	and(wire_ni01i_dataout, wire_ni0il_dataout, ~(ppm_cnt_reset));
	and(wire_ni01l_dataout, wire_ni0iO_dataout, ~(ppm_cnt_reset));
	and(wire_ni01O_dataout, wire_ni0li_dataout, ~(ppm_cnt_reset));
	assign		wire_ni0ii_dataout = (n0iii === 1'b1) ? niO1O : ni10O;
	assign		wire_ni0il_dataout = (n0iii === 1'b1) ? niO0i : ni1ii;
	assign		wire_ni0iO_dataout = (n0iii === 1'b1) ? niO0l : ni1il;
	assign		wire_ni0li_dataout = (n0iii === 1'b1) ? niO0O : ni1iO;
	assign		wire_ni0ll_dataout = (n0iii === 1'b1) ? niOii : ni1li;
	and(wire_ni10i_dataout, ni1lO, ~(rforcelow));
	or(wire_ni11O_dataout, wire_ni10i_dataout, rforcehigh);
	and(wire_ni1i_dataout, wire_ni0i_o[13], ~(n01i));
	and(wire_ni1l_dataout, wire_ni0i_o[14], ~(n01i));
	and(wire_ni1O_dataout, wire_ni0i_o[15], ~(n01i));
	and(wire_ni1Oi_dataout, wire_ni00l_dataout, ~(ppm_cnt_reset));
	and(wire_ni1Ol_dataout, wire_ni00O_dataout, ~(ppm_cnt_reset));
	and(wire_ni1OO_dataout, wire_ni0ii_dataout, ~(ppm_cnt_reset));
	and(wire_niOiO_dataout, wire_nl11i_dataout, ~((~ n0ili)));
	and(wire_niOl_dataout, nilO, ~((~ nl0l)));
	and(wire_niOli_dataout, wire_nl11l_dataout, ~((~ n0ili)));
	and(wire_niOll_dataout, wire_nl11O_dataout, ~((~ n0ili)));
	and(wire_niOlO_dataout, wire_nl10i_dataout, ~((~ n0ili)));
	and(wire_niOO_dataout, wire_nl1i_dataout, ~((~ nl0l)));
	and(wire_niOOi_dataout, wire_nl10l_dataout, ~((~ n0ili)));
	and(wire_niOOl_dataout, wire_nl10O_dataout, ~((~ n0ili)));
	and(wire_niOOO_dataout, wire_nl1ii_dataout, ~((~ n0ili)));
	and(wire_nl0ii_dataout, wire_nli1i_dataout, ~((~ n0ili)));
	and(wire_nl0il_dataout, wire_nl0lO_dataout, ~((~ n0ili)));
	and(wire_nl0iO_dataout, wire_nl0Oi_dataout, ~((~ n0ili)));
	and(wire_nl0li_dataout, wire_nl0Ol_dataout, ~((~ n0ili)));
	or(wire_nl0ll_dataout, wire_nl0OO_dataout, (~ n0ili));
	assign		wire_nl0lO_dataout = (n010O === 1'b1) ? nl01i : wire_nli1l_dataout;
	assign		wire_nl0Oi_dataout = (n010O === 1'b1) ? nl01l : wire_nli1O_dataout;
	assign		wire_nl0Ol_dataout = (n010O === 1'b1) ? nl01O : wire_nli0i_dataout;
	assign		wire_nl0OO_dataout = (n010O === 1'b1) ? nl00i : wire_nli0l_dataout;
	or(wire_nl10i_dataout, wire_nl1ll_dataout, n010i);
	or(wire_nl10l_dataout, wire_nl1lO_dataout, n010i);
	or(wire_nl10O_dataout, wire_nl1Oi_dataout, n010i);
	or(wire_nl11i_dataout, wire_nl1il_dataout, n010i);
	or(wire_nl11l_dataout, wire_nl1iO_dataout, n010i);
	or(wire_nl11O_dataout, wire_nl1li_dataout, n010i);
	and(wire_nl1i_dataout, (nllll ^ nl00O), (((((nl00i & (~ nl01O)) & (n000O30 ^ n000O29)) & (~ nl01l)) & (~ nl01i)) & (n000i32 ^ n000i31)));
	or(wire_nl1ii_dataout, wire_nl1Ol_dataout, n010i);
	assign		wire_nl1il_dataout = (ni0O === 1'b1) ? wire_nl1OO_o[0] : ni0lO;
	assign		wire_nl1iO_dataout = (ni0O === 1'b1) ? wire_nl1OO_o[1] : niO1l;
	assign		wire_nl1li_dataout = (ni0O === 1'b1) ? wire_nl1OO_o[2] : niO1O;
	assign		wire_nl1ll_dataout = (ni0O === 1'b1) ? wire_nl1OO_o[3] : niO0i;
	assign		wire_nl1lO_dataout = (ni0O === 1'b1) ? wire_nl1OO_o[4] : niO0l;
	assign		wire_nl1Oi_dataout = (ni0O === 1'b1) ? wire_nl1OO_o[5] : niO0O;
	assign		wire_nl1Ol_dataout = (ni0O === 1'b1) ? wire_nl1OO_o[6] : niOii;
	assign		wire_nli0i_dataout = (n010l === 1'b1) ? wire_nli0O_o[3] : nl01O;
	assign		wire_nli0l_dataout = (n010l === 1'b1) ? wire_nli0O_o[4] : nl00i;
	or(wire_nli1i_dataout, niOil, n010O);
	assign		wire_nli1l_dataout = (n010l === 1'b1) ? wire_nli0O_o[1] : nl01i;
	assign		wire_nli1O_dataout = (n010l === 1'b1) ? wire_nli0O_o[2] : nl01l;
	or(wire_nlllO_dataout, (~ nlliO), niOi);
	and(wire_nllOi_dataout, wire_nlOOl_o[0], ~(niOi));
	and(wire_nllOl_dataout, wire_nlOOl_o[1], ~(niOi));
	and(wire_nllOO_dataout, wire_nlOOl_o[2], ~(niOi));
	and(wire_nlO0i_dataout, wire_nlOOl_o[6], ~(niOi));
	and(wire_nlO0l_dataout, wire_nlOOl_o[7], ~(niOi));
	and(wire_nlO0O_dataout, wire_nlOOl_o[8], ~(niOi));
	and(wire_nlO1i_dataout, wire_nlOOl_o[3], ~(niOi));
	and(wire_nlO1l_dataout, wire_nlOOl_o[4], ~(niOi));
	and(wire_nlO1O_dataout, wire_nlOOl_o[5], ~(niOi));
	and(wire_nlOii_dataout, wire_nlOOl_o[9], ~(niOi));
	and(wire_nlOil_dataout, wire_nlOOl_o[10], ~(niOi));
	and(wire_nlOiO_dataout, wire_nlOOl_o[11], ~(niOi));
	and(wire_nlOli_dataout, wire_nlOOl_o[12], ~(niOi));
	and(wire_nlOll_dataout, wire_nlOOl_o[13], ~(niOi));
	and(wire_nlOlO_dataout, wire_nlOOl_o[14], ~(niOi));
	and(wire_nlOOi_dataout, wire_nlOOl_o[15], ~(niOi));
	oper_add   ni0i
	( 
	.a({n1OO, n1Ol, n1Oi, n1lO, n1ll, n1li, n1iO, n1il, n1ii, n10O, ((n01lO40 ^ n01lO39) & n10l), n10i, n11O, n11l, n11i, nlOOO}),
	.b({{15{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_ni0i_o));
	defparam
		ni0i.sgate_representation = 0,
		ni0i.width_a = 16,
		ni0i.width_b = 16,
		ni0i.width_o = 16;
	oper_add   nl1OO
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({{6{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nl1OO_o));
	defparam
		nl1OO.sgate_representation = 0,
		nl1OO.width_a = 7,
		nl1OO.width_b = 7,
		nl1OO.width_o = 7;
	oper_add   nli0O
	( 
	.a({nl00i, nl01O, nl01l, nl01i, 1'b1}),
	.b({{3{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nli0O_o));
	defparam
		nli0O.sgate_representation = 0,
		nli0O.width_a = 5,
		nli0O.width_b = 5,
		nli0O.width_o = 5;
	oper_add   nlOOl
	( 
	.a({nlliO, ((n01iO46 ^ n01iO45) & nllil), nllii, nll0O, ((n01li44 ^ n01li43) & nll0l), nll0i, nll1O, nll1l, ((n01ll42 ^ n01ll41) & nll1i), nliOO, nliOl, nliOi, nlilO, nlill, nlili, nliiO}),
	.b({{15{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlOOl_o));
	defparam
		nlOOl.sgate_representation = 0,
		nlOOl.width_a = 16,
		nlOOl.width_b = 16,
		nlOOl.width_o = 16;
	oper_less_than   nii1O
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({{4{1'b0}}, {2{1'b1}}, 1'b0}),
	.cin(1'b1),
	.o(wire_nii1O_o));
	defparam
		nii1O.sgate_representation = 0,
		nii1O.width_a = 7,
		nii1O.width_b = 7;
	oper_less_than   niiii
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({{3{1'b0}}, 1'b1, {3{1'b0}}}),
	.cin(1'b1),
	.o(wire_niiii_o));
	defparam
		niiii.sgate_representation = 0,
		niiii.width_a = 7,
		niiii.width_b = 7;
	oper_less_than   niill
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({{3{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0}),
	.cin(1'b1),
	.o(wire_niill_o));
	defparam
		niill.sgate_representation = 0,
		niill.width_a = 7,
		niill.width_b = 7;
	oper_less_than   niiOO
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({{3{1'b0}}, {4{1'b1}}}),
	.cin(1'b1),
	.o(wire_niiOO_o));
	defparam
		niiOO.sgate_representation = 0,
		niiOO.width_a = 7,
		niiOO.width_b = 7;
	oper_less_than   nil0i
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({{2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0}),
	.cin(1'b1),
	.o(wire_nil0i_o));
	defparam
		nil0i.sgate_representation = 0,
		nil0i.width_a = 7,
		nil0i.width_b = 7;
	oper_less_than   nili
	( 
	.a({nl00i, nl01O, nl01l, nl01i}),
	.b({1'b1, {3{1'b0}}}),
	.cin(1'b0),
	.o(wire_nili_o));
	defparam
		nili.sgate_representation = 0,
		nili.width_a = 4,
		nili.width_b = 4;
	oper_less_than   nilil
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({{2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}),
	.cin(1'b1),
	.o(wire_nilil_o));
	defparam
		nilil.sgate_representation = 0,
		nilil.width_a = 7,
		nilil.width_b = 7;
	oper_less_than   nill
	( 
	.a({4{1'b0}}),
	.b({nl00i, ((n001O34 ^ n001O33) & nl01O), nl01l, nl01i}),
	.cin(1'b0),
	.o(wire_nill_o));
	defparam
		nill.sgate_representation = 0,
		nill.width_a = 4,
		nill.width_b = 4;
	oper_less_than   nillO
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({1'b0, 1'b1, {3{1'b0}}, 1'b1, 1'b0}),
	.cin(1'b1),
	.o(wire_nillO_o));
	defparam
		nillO.sgate_representation = 0,
		nillO.width_a = 7,
		nillO.width_b = 7;
	oper_less_than   nilOO
	( 
	.a({niOii, niO0O, niO0l, niO0i, niO1O, niO1l, ni0lO}),
	.b({1'b1, {4{1'b0}}, {2{1'b1}}}),
	.cin(1'b1),
	.o(wire_nilOO_o));
	defparam
		nilOO.sgate_representation = 0,
		nilOO.width_a = 7,
		nilOO.width_b = 7;
	oper_less_than   nlOi
	( 
	.a({1'b1, {10{1'b0}}, 1'b1, {4{1'b0}}}),
	.b({nlliO, nllil, nllii, nll0O, nll0l, nll0i, ((n00ll24 ^ n00ll23) & nll1O), nll1l, nll1i, nliOO, nliOl, nliOi, nlilO, ((n00lO22 ^ n00lO21) & nlill), ((n00Oi20 ^ n00Oi19) & nlili), nliiO}),
	.cin(1'b0),
	.o(wire_nlOi_o));
	defparam
		nlOi.sgate_representation = 0,
		nlOi.width_a = 16,
		nlOi.width_b = 16;
	oper_less_than   nlOO
	( 
	.a({1'b1, {10{1'b0}}, 1'b1, {4{1'b0}}}),
	.b({n1OO, n1Ol, ((n00Ol18 ^ n00Ol17) & n1Oi), n1lO, n1ll, n1li, ((n00OO16 ^ n00OO15) & n1iO), n1il, n1ii, n10O, n10l, n10i, ((n0i1i14 ^ n0i1i13) & n11O), n11l, ((n0i1l12 ^ n0i1l11) & n11i), ((n0i1O10 ^ n0i1O9) & nlOOO)}),
	.cin(1'b0),
	.o(wire_nlOO_o));
	defparam
		nlOO.sgate_representation = 0,
		nlOO.width_a = 16,
		nlOO.width_b = 16;
	assign
		freq_lock = wire_ni11O_dataout,
		n001l = (nllO & nl1O),
		n00il = ((((((((((((((((~ nlliO) & (~ nllil)) & (~ nllii)) & (~ nll0O)) & (~ nll0l)) & (~ nll0i)) & (~ nll1O)) & (~ nll1l)) & nll1i) & nliOO) & nliOl) & nliOi) & nlilO) & nlill) & nlili) & nliiO),
		n010i = ((((((niOii & niO0O) & niO0l) & niO0i) & niO1O) & niO1l) & ni0lO),
		n010l = ((~ ni0O) & niOil),
		n010O = ((n001l | ni0O) | (~ (n01ii48 ^ n01ii47))),
		n011i = ((((((~ ppmsel[0]) & (~ ppmsel[1])) & (~ ppmsel[2])) & ppmsel[3]) & (~ ppmsel[4])) & (~ ppmsel[5])),
		n011l = ((((((~ ppmsel[0]) & (~ ppmsel[1])) & (~ ppmsel[2])) & (~ ppmsel[3])) & ppmsel[4]) & (~ ppmsel[5])),
		n011O = ((((((~ ppmsel[0]) & (~ ppmsel[1])) & (~ ppmsel[2])) & (~ ppmsel[3])) & (~ ppmsel[4])) & ppmsel[5]),
		n0i0l = 1'b1,
		n0iii = (((((~ nl00i) & nl01O) & (~ nl01l)) & (n0iil4 ^ n0iil3)) & (~ nl01i)),
		n0ili = ((((nl00i | nl01O) | nl01l) | nl01i) | (~ (n0ill2 ^ n0ill1))),
		n1Oli = (((((ppmsel[0] & ppmsel[1]) & ppmsel[2]) & ppmsel[3]) & ppmsel[4]) & ppmsel[5]),
		n1Oll = (((((ppmsel[0] & ppmsel[1]) & (~ ppmsel[2])) & (~ ppmsel[3])) & (~ ppmsel[4])) & (~ ppmsel[5])),
		n1OlO = (((((ppmsel[0] & (~ ppmsel[1])) & (~ ppmsel[2])) & (~ ppmsel[3])) & (~ ppmsel[4])) & (~ ppmsel[5])),
		n1OOi = ((((((~ ppmsel[0]) & ppmsel[1]) & (~ ppmsel[2])) & (~ ppmsel[3])) & (~ ppmsel[4])) & (~ ppmsel[5])),
		n1OOl = ((((((~ ppmsel[0]) & (~ ppmsel[1])) & ppmsel[2]) & (~ ppmsel[3])) & (~ ppmsel[4])) & (~ ppmsel[5])),
		n1OOO = (((((ppmsel[0] & (~ ppmsel[1])) & (~ ppmsel[2])) & ppmsel[3]) & (~ ppmsel[4])) & (~ ppmsel[5])),
		ppm_cnt_latch = {ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni0OO};
endmodule //arriagx_hssi_rx_freqdet
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 8 mux21 80 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_pcs_channel_testbus
	( 
	chnl_test_bus_out,
	rtest_bus_sel,
	test_bus_in0,
	test_bus_in1,
	test_bus_in2,
	test_bus_in3,
	test_bus_in4,
	test_bus_in5,
	test_bus_in6,
	test_bus_in7) /* synthesis synthesis_clearbox=1 */;
	output   [9:0]  chnl_test_bus_out;
	input   [2:0]  rtest_bus_sel;
	input   [9:0]  test_bus_in0;
	input   [9:0]  test_bus_in1;
	input   [9:0]  test_bus_in2;
	input   [9:0]  test_bus_in3;
	input   [9:0]  test_bus_in4;
	input   [9:0]  test_bus_in5;
	input   [9:0]  test_bus_in6;
	input   [9:0]  test_bus_in7;

	reg	ni0ll7;
	reg	ni0ll8;
	reg	ni0Oi5;
	reg	ni0Oi6;
	reg	ni0OO3;
	reg	ni0OO4;
	reg	nii1O1;
	reg	nii1O2;
	wire	wire_n00i_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_ni_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_nii_dataout;
	wire	wire_niii_dataout;
	wire	wire_niil_dataout;
	wire	wire_niiO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nili_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nli_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOO_dataout;
	wire	wire_nO_dataout;
	wire  nii0l;
	wire  nii0O;
	wire  nii1l;
	wire  niiii;
	wire  niiil;
	wire  niiiO;
	wire  niili;
	wire  niill;
	wire  niilO;

	initial
		ni0ll7 = 0;
	always @ ( posedge nii1l)
		  ni0ll7 <= ni0ll8;
	event ni0ll7_event;
	initial
		#1 ->ni0ll7_event;
	always @(ni0ll7_event)
		ni0ll7 <= {1{1'b1}};
	initial
		ni0ll8 = 0;
	always @ ( posedge nii1l)
		  ni0ll8 <= ni0ll7;
	initial
		ni0Oi5 = 0;
	always @ ( posedge nii1l)
		  ni0Oi5 <= ni0Oi6;
	event ni0Oi5_event;
	initial
		#1 ->ni0Oi5_event;
	always @(ni0Oi5_event)
		ni0Oi5 <= {1{1'b1}};
	initial
		ni0Oi6 = 0;
	always @ ( posedge nii1l)
		  ni0Oi6 <= ni0Oi5;
	initial
		ni0OO3 = 0;
	always @ ( posedge nii1l)
		  ni0OO3 <= ni0OO4;
	event ni0OO3_event;
	initial
		#1 ->ni0OO3_event;
	always @(ni0OO3_event)
		ni0OO3 <= {1{1'b1}};
	initial
		ni0OO4 = 0;
	always @ ( posedge nii1l)
		  ni0OO4 <= ni0OO3;
	initial
		nii1O1 = 0;
	always @ ( posedge nii1l)
		  nii1O1 <= nii1O2;
	event nii1O1_event;
	initial
		#1 ->nii1O1_event;
	always @(nii1O1_event)
		nii1O1 <= {1{1'b1}};
	initial
		nii1O2 = 0;
	always @ ( posedge nii1l)
		  nii1O2 <= nii1O1;
	assign		wire_n00i_dataout = (niiii === 1'b1) ? test_bus_in2[3] : wire_n0Ol_dataout;
	assign		wire_n00l_dataout = (niiii === 1'b1) ? test_bus_in2[4] : wire_n0OO_dataout;
	assign		wire_n00O_dataout = (niiii === 1'b1) ? test_bus_in2[5] : wire_ni1i_dataout;
	assign		wire_n01i_dataout = (niiii === 1'b1) ? test_bus_in2[0] : wire_n0ll_dataout;
	assign		wire_n01l_dataout = (niiii === 1'b1) ? test_bus_in2[1] : wire_n0lO_dataout;
	assign		wire_n01O_dataout = (niiii === 1'b1) ? test_bus_in2[2] : wire_n0Oi_dataout;
	assign		wire_n0i_dataout = (niill === 1'b1) ? test_bus_in6[8] : wire_nl_dataout;
	assign		wire_n0ii_dataout = (niiii === 1'b1) ? test_bus_in2[6] : wire_ni1l_dataout;
	assign		wire_n0il_dataout = (niiii === 1'b1) ? test_bus_in2[7] : wire_ni1O_dataout;
	assign		wire_n0iO_dataout = (niiii === 1'b1) ? test_bus_in2[8] : wire_ni0i_dataout;
	assign		wire_n0l_dataout = (niill === 1'b1) ? test_bus_in6[9] : wire_nO_dataout;
	assign		wire_n0li_dataout = (niiii === 1'b1) ? test_bus_in2[9] : wire_ni0l_dataout;
	assign		wire_n0ll_dataout = (niiil === 1'b1) ? test_bus_in3[0] : wire_ni0O_dataout;
	assign		wire_n0lO_dataout = (niiil === 1'b1) ? test_bus_in3[1] : wire_niii_dataout;
	assign		wire_n0O_dataout = (niilO === 1'b1) ? test_bus_in7[0] : test_bus_in0[0];
	assign		wire_n0Oi_dataout = (niiil === 1'b1) ? test_bus_in3[2] : wire_niil_dataout;
	assign		wire_n0Ol_dataout = (niiil === 1'b1) ? test_bus_in3[3] : wire_niiO_dataout;
	assign		wire_n0OO_dataout = (niiil === 1'b1) ? test_bus_in3[4] : wire_nili_dataout;
	assign		wire_n10i_dataout = (nii0l === 1'b1) ? test_bus_in0[8] : wire_n1Ol_dataout;
	assign		wire_n10l_dataout = (nii0l === 1'b1) ? test_bus_in0[9] : wire_n1OO_dataout;
	assign		wire_n10O_dataout = (nii0O === 1'b1) ? test_bus_in1[0] : wire_n01i_dataout;
	assign		wire_n11i_dataout = (nii0l === 1'b1) ? test_bus_in0[5] : wire_n1ll_dataout;
	assign		wire_n11l_dataout = (nii0l === 1'b1) ? test_bus_in0[6] : wire_n1lO_dataout;
	assign		wire_n11O_dataout = (nii0l === 1'b1) ? test_bus_in0[7] : wire_n1Oi_dataout;
	assign		wire_n1i_dataout = (niill === 1'b1) ? test_bus_in6[5] : wire_nll_dataout;
	assign		wire_n1ii_dataout = (nii0O === 1'b1) ? test_bus_in1[1] : wire_n01l_dataout;
	assign		wire_n1il_dataout = (nii0O === 1'b1) ? test_bus_in1[2] : wire_n01O_dataout;
	assign		wire_n1iO_dataout = (nii0O === 1'b1) ? test_bus_in1[3] : wire_n00i_dataout;
	assign		wire_n1l_dataout = (niill === 1'b1) ? test_bus_in6[6] : wire_nlO_dataout;
	assign		wire_n1li_dataout = (nii0O === 1'b1) ? test_bus_in1[4] : wire_n00l_dataout;
	assign		wire_n1ll_dataout = (nii0O === 1'b1) ? test_bus_in1[5] : wire_n00O_dataout;
	assign		wire_n1lO_dataout = (nii0O === 1'b1) ? test_bus_in1[6] : wire_n0ii_dataout;
	assign		wire_n1O_dataout = (niill === 1'b1) ? test_bus_in6[7] : wire_ni_dataout;
	assign		wire_n1Oi_dataout = (nii0O === 1'b1) ? test_bus_in1[7] : wire_n0il_dataout;
	assign		wire_n1Ol_dataout = (nii0O === 1'b1) ? test_bus_in1[8] : wire_n0iO_dataout;
	assign		wire_n1OO_dataout = (nii0O === 1'b1) ? test_bus_in1[9] : wire_n0li_dataout;
	assign		wire_ni_dataout = (niilO === 1'b1) ? test_bus_in7[7] : test_bus_in0[7];
	assign		wire_ni0i_dataout = (niiil === 1'b1) ? test_bus_in3[8] : wire_niOl_dataout;
	assign		wire_ni0l_dataout = (niiil === 1'b1) ? test_bus_in3[9] : wire_niOO_dataout;
	assign		wire_ni0O_dataout = (niiiO === 1'b1) ? test_bus_in4[0] : wire_nl1i_dataout;
	assign		wire_ni1i_dataout = (niiil === 1'b1) ? test_bus_in3[5] : wire_nill_dataout;
	assign		wire_ni1l_dataout = (niiil === 1'b1) ? test_bus_in3[6] : wire_nilO_dataout;
	assign		wire_ni1O_dataout = (niiil === 1'b1) ? test_bus_in3[7] : wire_niOi_dataout;
	assign		wire_nii_dataout = (niilO === 1'b1) ? test_bus_in7[1] : test_bus_in0[1];
	assign		wire_niii_dataout = (niiiO === 1'b1) ? test_bus_in4[1] : wire_nl1l_dataout;
	assign		wire_niil_dataout = (niiiO === 1'b1) ? test_bus_in4[2] : wire_nl1O_dataout;
	assign		wire_niiO_dataout = (niiiO === 1'b1) ? test_bus_in4[3] : wire_nl0i_dataout;
	assign		wire_nil_dataout = (niilO === 1'b1) ? test_bus_in7[2] : test_bus_in0[2];
	assign		wire_nili_dataout = (niiiO === 1'b1) ? test_bus_in4[4] : wire_nl0l_dataout;
	assign		wire_nill_dataout = (niiiO === 1'b1) ? test_bus_in4[5] : wire_nl0O_dataout;
	assign		wire_nilO_dataout = (niiiO === 1'b1) ? test_bus_in4[6] : wire_nlii_dataout;
	assign		wire_niO_dataout = (niilO === 1'b1) ? test_bus_in7[3] : test_bus_in0[3];
	assign		wire_niOi_dataout = (niiiO === 1'b1) ? test_bus_in4[7] : wire_nlil_dataout;
	assign		wire_niOl_dataout = (niiiO === 1'b1) ? test_bus_in4[8] : wire_nliO_dataout;
	assign		wire_niOO_dataout = (niiiO === 1'b1) ? test_bus_in4[9] : wire_nlli_dataout;
	assign		wire_nl_dataout = (niilO === 1'b1) ? test_bus_in7[8] : test_bus_in0[8];
	assign		wire_nl0i_dataout = (niili === 1'b1) ? test_bus_in5[3] : wire_nlOl_dataout;
	assign		wire_nl0l_dataout = (niili === 1'b1) ? test_bus_in5[4] : wire_nlOO_dataout;
	assign		wire_nl0O_dataout = (niili === 1'b1) ? test_bus_in5[5] : wire_n1i_dataout;
	assign		wire_nl1i_dataout = (niili === 1'b1) ? test_bus_in5[0] : wire_nlll_dataout;
	assign		wire_nl1l_dataout = (niili === 1'b1) ? test_bus_in5[1] : wire_nllO_dataout;
	assign		wire_nl1O_dataout = (niili === 1'b1) ? test_bus_in5[2] : wire_nlOi_dataout;
	assign		wire_nli_dataout = (niilO === 1'b1) ? test_bus_in7[4] : test_bus_in0[4];
	assign		wire_nlii_dataout = (niili === 1'b1) ? test_bus_in5[6] : wire_n1l_dataout;
	assign		wire_nlil_dataout = (niili === 1'b1) ? test_bus_in5[7] : wire_n1O_dataout;
	assign		wire_nliO_dataout = (niili === 1'b1) ? test_bus_in5[8] : wire_n0i_dataout;
	assign		wire_nll_dataout = (niilO === 1'b1) ? test_bus_in7[5] : test_bus_in0[5];
	assign		wire_nlli_dataout = (niili === 1'b1) ? test_bus_in5[9] : wire_n0l_dataout;
	assign		wire_nlll_dataout = (niill === 1'b1) ? test_bus_in6[0] : wire_n0O_dataout;
	assign		wire_nllO_dataout = (niill === 1'b1) ? test_bus_in6[1] : wire_nii_dataout;
	assign		wire_nlO_dataout = (niilO === 1'b1) ? test_bus_in7[6] : test_bus_in0[6];
	assign		wire_nlOi_dataout = (niill === 1'b1) ? test_bus_in6[2] : wire_nil_dataout;
	assign		wire_nlOl_dataout = (niill === 1'b1) ? test_bus_in6[3] : wire_niO_dataout;
	assign		wire_nlOll_dataout = (nii0l === 1'b1) ? test_bus_in0[0] : wire_n10O_dataout;
	assign		wire_nlOlO_dataout = (nii0l === 1'b1) ? test_bus_in0[1] : wire_n1ii_dataout;
	assign		wire_nlOO_dataout = (niill === 1'b1) ? test_bus_in6[4] : wire_nli_dataout;
	assign		wire_nlOOi_dataout = (nii0l === 1'b1) ? test_bus_in0[2] : wire_n1il_dataout;
	assign		wire_nlOOl_dataout = (nii0l === 1'b1) ? test_bus_in0[3] : wire_n1iO_dataout;
	assign		wire_nlOOO_dataout = (nii0l === 1'b1) ? test_bus_in0[4] : wire_n1li_dataout;
	assign		wire_nO_dataout = (niilO === 1'b1) ? test_bus_in7[9] : test_bus_in0[9];
	assign
		chnl_test_bus_out = {wire_n10l_dataout, wire_n10i_dataout, wire_n11O_dataout, wire_n11l_dataout, wire_n11i_dataout, wire_nlOOO_dataout, wire_nlOOl_dataout, wire_nlOOi_dataout, wire_nlOlO_dataout, wire_nlOll_dataout},
		nii0l = ((((~ rtest_bus_sel[0]) & (~ rtest_bus_sel[1])) & (~ rtest_bus_sel[2])) & (nii1O2 ^ nii1O1)),
		nii0O = ((rtest_bus_sel[0] & (~ rtest_bus_sel[1])) & (~ rtest_bus_sel[2])),
		niiii = ((((~ rtest_bus_sel[0]) & rtest_bus_sel[1]) & (~ rtest_bus_sel[2])) & (ni0OO4 ^ ni0OO3)),
		niiil = ((rtest_bus_sel[0] & rtest_bus_sel[1]) & (~ rtest_bus_sel[2])),
		niiiO = ((((~ rtest_bus_sel[0]) & (~ rtest_bus_sel[1])) & rtest_bus_sel[2]) & (ni0Oi6 ^ ni0Oi5)),
		niili = ((rtest_bus_sel[0] & (~ rtest_bus_sel[1])) & rtest_bus_sel[2]),
		niill = (((~ rtest_bus_sel[0]) & rtest_bus_sel[1]) & rtest_bus_sel[2]),
		niilO = (((rtest_bus_sel[0] & rtest_bus_sel[1]) & rtest_bus_sel[2]) & (ni0ll8 ^ ni0ll7));
endmodule //arriagx_hssi_rx_pcs_channel_testbus
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 88 mux21 147 oper_decoder 1 oper_selector 38 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_prbs_ver
	( 
	data_in,
	encdet_prbs,
	prbs_done,
	prbs_err,
	prbs_err_lt,
	rall_one_dect_only,
	rcvd_clk,
	rpma_doublewidth_rx,
	rpmadwidth_rx,
	rprbs_clr_rslt_rx,
	rprbs_en_rx,
	rprbs_sel,
	scan_mode,
	soft_reset,
	verify_on) /* synthesis synthesis_clearbox=1 */;
	input   [19:0]  data_in;
	output   encdet_prbs;
	output   prbs_done;
	output   prbs_err;
	output   prbs_err_lt;
	input   rall_one_dect_only;
	input   rcvd_clk;
	input   rpma_doublewidth_rx;
	input   rpmadwidth_rx;
	input   rprbs_clr_rslt_rx;
	input   rprbs_en_rx;
	input   [2:0]  rprbs_sel;
	input   scan_mode;
	input   soft_reset;
	output   verify_on;

	reg	nl0lOl45;
	reg	nl0lOl46;
	reg	nl0lOO43;
	reg	nl0lOO44;
	reg	nl0O0l39;
	reg	nl0O0l40;
	reg	nl0O0O37;
	reg	nl0O0O38;
	reg	nl0O1O41;
	reg	nl0O1O42;
	reg	nl0Oil35;
	reg	nl0Oil36;
	reg	nl0Oll33;
	reg	nl0Oll34;
	reg	nl0OOi31;
	reg	nl0OOi32;
	reg	nli00l19;
	reg	nli00l20;
	reg	nli01O21;
	reg	nli01O22;
	reg	nli0iO17;
	reg	nli0iO18;
	reg	nli0li15;
	reg	nli0li16;
	reg	nli10O27;
	reg	nli10O28;
	reg	nli11l29;
	reg	nli11l30;
	reg	nli1iO25;
	reg	nli1iO26;
	reg	nli1ll23;
	reg	nli1ll24;
	reg	nlii0i7;
	reg	nlii0i8;
	reg	nlii0l5;
	reg	nlii0l6;
	reg	nlii1i13;
	reg	nlii1i14;
	reg	nlii1l11;
	reg	nlii1l12;
	reg	nlii1O10;
	reg	nlii1O9;
	reg	nliiil3;
	reg	nliiil4;
	reg	nliili1;
	reg	nliili2;
	reg	n0OO;
	reg	n1ilO;
	reg	n1iOi;
	reg	n1iOl;
	reg	n1iOO;
	reg	n1l0i;
	reg	n1l0l;
	reg	n1l0O;
	reg	n1l1i;
	reg	n1l1l;
	reg	n1l1O;
	reg	n1lii;
	reg	n1lil;
	reg	n1liO;
	reg	n1lli;
	reg	n1lll;
	reg	n1llO;
	reg	n1lOi;
	reg	n1lOl;
	reg	n1lOO;
	reg	n1O1i;
	reg	n1O1l;
	reg	n1O1O;
	reg	nlOO1l;
	reg	nlOOll;
	reg	n0Ol_clk_prev;
	wire	wire_n0Ol_CLRN;
	reg	n0li;
	reg	n0ll;
	reg	n0lO;
	reg	n0Oi;
	reg	n1O0i;
	reg	ni0l;
	reg	ni1i;
	reg	ni1l;
	reg	ni1O;
	reg	nlOlll;
	reg	nlOllO;
	reg	nlOlOi;
	reg	nlOlOl;
	reg	nlOlOO;
	reg	nlOO1i;
	wire	wire_ni0i_CLRN;
	reg	ni0O;
	reg	niiO;
	reg	niil_clk_prev;
	wire	wire_niil_CLRN;
	wire	wire_n000i_dataout;
	wire	wire_n000l_dataout;
	wire	wire_n000O_dataout;
	wire	wire_n001i_dataout;
	wire	wire_n001l_dataout;
	wire	wire_n001O_dataout;
	wire	wire_n00i_dataout;
	wire	wire_n00ii_dataout;
	wire	wire_n00il_dataout;
	wire	wire_n00iO_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00li_dataout;
	wire	wire_n00ll_dataout;
	wire	wire_n00lO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n00Oi_dataout;
	wire	wire_n00Ol_dataout;
	wire	wire_n00OO_dataout;
	wire	wire_n010i_dataout;
	wire	wire_n010l_dataout;
	wire	wire_n010O_dataout;
	wire	wire_n011i_dataout;
	wire	wire_n011l_dataout;
	wire	wire_n011O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01ii_dataout;
	wire	wire_n01il_dataout;
	wire	wire_n01iO_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01li_dataout;
	wire	wire_n01ll_dataout;
	wire	wire_n01lO_dataout;
	wire	wire_n01Oi_dataout;
	wire	wire_n01Ol_dataout;
	wire	wire_n01OO_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0i0i_dataout;
	wire	wire_n0i0l_dataout;
	wire	wire_n0i0O_dataout;
	wire	wire_n0i1i_dataout;
	wire	wire_n0i1l_dataout;
	wire	wire_n0i1O_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0iii_dataout;
	wire	wire_n0iil_dataout;
	wire	wire_n0iiO_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0ili_dataout;
	wire	wire_n0ill_dataout;
	wire	wire_n0ilO_dataout;
	wire	wire_n0iOi_dataout;
	wire	wire_n0iOl_dataout;
	wire	wire_n0iOO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0l0i_dataout;
	wire	wire_n0l0l_dataout;
	wire	wire_n0l0O_dataout;
	wire	wire_n0l1i_dataout;
	wire	wire_n0l1l_dataout;
	wire	wire_n0l1O_dataout;
	wire	wire_n0lii_dataout;
	wire	wire_n0lil_dataout;
	wire	wire_n0liO_dataout;
	wire	wire_n0lli_dataout;
	wire	wire_n0lll_dataout;
	wire	wire_n0llO_dataout;
	wire	wire_n0lOi_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10lO_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1i0l_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1O0l_dataout;
	wire	wire_n1O0O_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Oii_dataout;
	wire	wire_n1Oil_dataout;
	wire	wire_n1OiO_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1Oli_dataout;
	wire	wire_n1Oll_dataout;
	wire	wire_n1OlO_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_n1OOi_dataout;
	wire	wire_n1OOl_dataout;
	wire	wire_n1OOO_dataout;
	wire	wire_ni_dataout;
	wire	wire_nii_dataout;
	wire	wire_niii_dataout;
	wire	wire_nil_dataout;
	wire	wire_nili_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nli_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOO0i_dataout;
	wire	wire_nlOO0l_dataout;
	wire	wire_nlOO0O_dataout;
	wire	wire_nlOO1O_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOii_dataout;
	wire	wire_nlOOil_dataout;
	wire	wire_nlOOiO_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOli_dataout;
	wire	wire_nlOOlO_dataout;
	wire	wire_nlOOO_dataout;
	wire	wire_nlOOOi_dataout;
	wire	wire_nO_dataout;
	wire  [31:0]   wire_n110l_o;
	wire  wire_n01O_o;
	wire  wire_n0iO_o;
	wire  wire_n0lOl_o;
	wire  wire_n0lOO_o;
	wire  wire_n0O0i_o;
	wire  wire_n0O0l_o;
	wire  wire_n0O0O_o;
	wire  wire_n0O1i_o;
	wire  wire_n0O1l_o;
	wire  wire_n0O1O_o;
	wire  wire_n0Oii_o;
	wire  wire_n0Oil_o;
	wire  wire_n0OiO_o;
	wire  wire_n0Oli_o;
	wire  wire_n0Oll_o;
	wire  wire_n0OlO_o;
	wire  wire_n0OOi_o;
	wire  wire_n0OOl_o;
	wire  wire_n111i_o;
	wire  wire_n111l_o;
	wire  wire_n111O_o;
	wire  wire_ni10i_o;
	wire  wire_ni10O_o;
	wire  wire_ni11i_o;
	wire  wire_ni11l_o;
	wire  wire_ni11O_o;
	wire  wire_ni1ii_o;
	wire  wire_ni1il_o;
	wire  wire_nli0O_o;
	wire  wire_nliiO_o;
	wire  wire_nlilO_o;
	wire  wire_nliOO_o;
	wire  wire_nll0l_o;
	wire  wire_nll1O_o;
	wire  wire_nllil_o;
	wire  wire_nllll_o;
	wire  wire_nlOOOl_o;
	wire  wire_nlOOOO_o;
	wire  nl000i;
	wire  nl000l;
	wire  nl000O;
	wire  nl001i;
	wire  nl001l;
	wire  nl001O;
	wire  nl00ii;
	wire  nl00il;
	wire  nl00iO;
	wire  nl00li;
	wire  nl00ll;
	wire  nl00lO;
	wire  nl00Oi;
	wire  nl00Ol;
	wire  nl00OO;
	wire  nl010i;
	wire  nl010l;
	wire  nl010O;
	wire  nl011i;
	wire  nl011l;
	wire  nl011O;
	wire  nl01ii;
	wire  nl01il;
	wire  nl01iO;
	wire  nl01li;
	wire  nl01ll;
	wire  nl01lO;
	wire  nl01Oi;
	wire  nl01Ol;
	wire  nl01OO;
	wire  nl0i0i;
	wire  nl0i0l;
	wire  nl0i0O;
	wire  nl0i1i;
	wire  nl0i1l;
	wire  nl0i1O;
	wire  nl0iii;
	wire  nl0iil;
	wire  nl0iiO;
	wire  nl0ili;
	wire  nl0ill;
	wire  nl0ilO;
	wire  nl0iOi;
	wire  nl0iOl;
	wire  nl0iOO;
	wire  nl0l0i;
	wire  nl0l0l;
	wire  nl0l0O;
	wire  nl0l1i;
	wire  nl0l1l;
	wire  nl0l1O;
	wire  nl0lii;
	wire  nl0lil;
	wire  nl0liO;
	wire  nl0lli;
	wire  nl0lll;
	wire  nl0llO;
	wire  nl0lOi;
	wire  nl0O1l;
	wire  nl0Oii;
	wire  nl0Oli;
	wire  nl0OOl;
	wire  nl0OOO;
	wire  nl1OiO;
	wire  nl1Oli;
	wire  nl1Oll;
	wire  nl1OlO;
	wire  nl1OOi;
	wire  nl1OOl;
	wire  nl1OOO;
	wire  nli00i;
	wire  nli00O;
	wire  nli01i;
	wire  nli01l;
	wire  nli0ii;
	wire  nli0il;
	wire  nli0ll;
	wire  nli0lO;
	wire  nli0Oi;
	wire  nli0Ol;
	wire  nli0OO;
	wire  nli10i;
	wire  nli10l;
	wire  nli11i;
	wire  nli1il;
	wire  nli1Oi;
	wire  nli1Ol;
	wire  nli1OO;
	wire  nlii0O;
	wire  nliiii;
	wire  nliiiO;
	wire  nliill;
	wire  nliilO;
	wire  nliiOi;

	initial
		nl0lOl45 = 0;
	always @ ( posedge rcvd_clk)
		  nl0lOl45 <= nl0lOl46;
	event nl0lOl45_event;
	initial
		#1 ->nl0lOl45_event;
	always @(nl0lOl45_event)
		nl0lOl45 <= {1{1'b1}};
	initial
		nl0lOl46 = 0;
	always @ ( posedge rcvd_clk)
		  nl0lOl46 <= nl0lOl45;
	initial
		nl0lOO43 = 0;
	always @ ( posedge rcvd_clk)
		  nl0lOO43 <= nl0lOO44;
	event nl0lOO43_event;
	initial
		#1 ->nl0lOO43_event;
	always @(nl0lOO43_event)
		nl0lOO43 <= {1{1'b1}};
	initial
		nl0lOO44 = 0;
	always @ ( posedge rcvd_clk)
		  nl0lOO44 <= nl0lOO43;
	initial
		nl0O0l39 = 0;
	always @ ( posedge rcvd_clk)
		  nl0O0l39 <= nl0O0l40;
	event nl0O0l39_event;
	initial
		#1 ->nl0O0l39_event;
	always @(nl0O0l39_event)
		nl0O0l39 <= {1{1'b1}};
	initial
		nl0O0l40 = 0;
	always @ ( posedge rcvd_clk)
		  nl0O0l40 <= nl0O0l39;
	initial
		nl0O0O37 = 0;
	always @ ( posedge rcvd_clk)
		  nl0O0O37 <= nl0O0O38;
	event nl0O0O37_event;
	initial
		#1 ->nl0O0O37_event;
	always @(nl0O0O37_event)
		nl0O0O37 <= {1{1'b1}};
	initial
		nl0O0O38 = 0;
	always @ ( posedge rcvd_clk)
		  nl0O0O38 <= nl0O0O37;
	initial
		nl0O1O41 = 0;
	always @ ( posedge rcvd_clk)
		  nl0O1O41 <= nl0O1O42;
	event nl0O1O41_event;
	initial
		#1 ->nl0O1O41_event;
	always @(nl0O1O41_event)
		nl0O1O41 <= {1{1'b1}};
	initial
		nl0O1O42 = 0;
	always @ ( posedge rcvd_clk)
		  nl0O1O42 <= nl0O1O41;
	initial
		nl0Oil35 = 0;
	always @ ( posedge rcvd_clk)
		  nl0Oil35 <= nl0Oil36;
	event nl0Oil35_event;
	initial
		#1 ->nl0Oil35_event;
	always @(nl0Oil35_event)
		nl0Oil35 <= {1{1'b1}};
	initial
		nl0Oil36 = 0;
	always @ ( posedge rcvd_clk)
		  nl0Oil36 <= nl0Oil35;
	initial
		nl0Oll33 = 0;
	always @ ( posedge rcvd_clk)
		  nl0Oll33 <= nl0Oll34;
	event nl0Oll33_event;
	initial
		#1 ->nl0Oll33_event;
	always @(nl0Oll33_event)
		nl0Oll33 <= {1{1'b1}};
	initial
		nl0Oll34 = 0;
	always @ ( posedge rcvd_clk)
		  nl0Oll34 <= nl0Oll33;
	initial
		nl0OOi31 = 0;
	always @ ( posedge rcvd_clk)
		  nl0OOi31 <= nl0OOi32;
	event nl0OOi31_event;
	initial
		#1 ->nl0OOi31_event;
	always @(nl0OOi31_event)
		nl0OOi31 <= {1{1'b1}};
	initial
		nl0OOi32 = 0;
	always @ ( posedge rcvd_clk)
		  nl0OOi32 <= nl0OOi31;
	initial
		nli00l19 = 0;
	always @ ( posedge rcvd_clk)
		  nli00l19 <= nli00l20;
	event nli00l19_event;
	initial
		#1 ->nli00l19_event;
	always @(nli00l19_event)
		nli00l19 <= {1{1'b1}};
	initial
		nli00l20 = 0;
	always @ ( posedge rcvd_clk)
		  nli00l20 <= nli00l19;
	initial
		nli01O21 = 0;
	always @ ( posedge rcvd_clk)
		  nli01O21 <= nli01O22;
	event nli01O21_event;
	initial
		#1 ->nli01O21_event;
	always @(nli01O21_event)
		nli01O21 <= {1{1'b1}};
	initial
		nli01O22 = 0;
	always @ ( posedge rcvd_clk)
		  nli01O22 <= nli01O21;
	initial
		nli0iO17 = 0;
	always @ ( posedge rcvd_clk)
		  nli0iO17 <= nli0iO18;
	event nli0iO17_event;
	initial
		#1 ->nli0iO17_event;
	always @(nli0iO17_event)
		nli0iO17 <= {1{1'b1}};
	initial
		nli0iO18 = 0;
	always @ ( posedge rcvd_clk)
		  nli0iO18 <= nli0iO17;
	initial
		nli0li15 = 0;
	always @ ( posedge rcvd_clk)
		  nli0li15 <= nli0li16;
	event nli0li15_event;
	initial
		#1 ->nli0li15_event;
	always @(nli0li15_event)
		nli0li15 <= {1{1'b1}};
	initial
		nli0li16 = 0;
	always @ ( posedge rcvd_clk)
		  nli0li16 <= nli0li15;
	initial
		nli10O27 = 0;
	always @ ( posedge rcvd_clk)
		  nli10O27 <= nli10O28;
	event nli10O27_event;
	initial
		#1 ->nli10O27_event;
	always @(nli10O27_event)
		nli10O27 <= {1{1'b1}};
	initial
		nli10O28 = 0;
	always @ ( posedge rcvd_clk)
		  nli10O28 <= nli10O27;
	initial
		nli11l29 = 0;
	always @ ( posedge rcvd_clk)
		  nli11l29 <= nli11l30;
	event nli11l29_event;
	initial
		#1 ->nli11l29_event;
	always @(nli11l29_event)
		nli11l29 <= {1{1'b1}};
	initial
		nli11l30 = 0;
	always @ ( posedge rcvd_clk)
		  nli11l30 <= nli11l29;
	initial
		nli1iO25 = 0;
	always @ ( posedge rcvd_clk)
		  nli1iO25 <= nli1iO26;
	event nli1iO25_event;
	initial
		#1 ->nli1iO25_event;
	always @(nli1iO25_event)
		nli1iO25 <= {1{1'b1}};
	initial
		nli1iO26 = 0;
	always @ ( posedge rcvd_clk)
		  nli1iO26 <= nli1iO25;
	initial
		nli1ll23 = 0;
	always @ ( posedge rcvd_clk)
		  nli1ll23 <= nli1ll24;
	event nli1ll23_event;
	initial
		#1 ->nli1ll23_event;
	always @(nli1ll23_event)
		nli1ll23 <= {1{1'b1}};
	initial
		nli1ll24 = 0;
	always @ ( posedge rcvd_clk)
		  nli1ll24 <= nli1ll23;
	initial
		nlii0i7 = 0;
	always @ ( posedge rcvd_clk)
		  nlii0i7 <= nlii0i8;
	event nlii0i7_event;
	initial
		#1 ->nlii0i7_event;
	always @(nlii0i7_event)
		nlii0i7 <= {1{1'b1}};
	initial
		nlii0i8 = 0;
	always @ ( posedge rcvd_clk)
		  nlii0i8 <= nlii0i7;
	initial
		nlii0l5 = 0;
	always @ ( posedge rcvd_clk)
		  nlii0l5 <= nlii0l6;
	event nlii0l5_event;
	initial
		#1 ->nlii0l5_event;
	always @(nlii0l5_event)
		nlii0l5 <= {1{1'b1}};
	initial
		nlii0l6 = 0;
	always @ ( posedge rcvd_clk)
		  nlii0l6 <= nlii0l5;
	initial
		nlii1i13 = 0;
	always @ ( posedge rcvd_clk)
		  nlii1i13 <= nlii1i14;
	event nlii1i13_event;
	initial
		#1 ->nlii1i13_event;
	always @(nlii1i13_event)
		nlii1i13 <= {1{1'b1}};
	initial
		nlii1i14 = 0;
	always @ ( posedge rcvd_clk)
		  nlii1i14 <= nlii1i13;
	initial
		nlii1l11 = 0;
	always @ ( posedge rcvd_clk)
		  nlii1l11 <= nlii1l12;
	event nlii1l11_event;
	initial
		#1 ->nlii1l11_event;
	always @(nlii1l11_event)
		nlii1l11 <= {1{1'b1}};
	initial
		nlii1l12 = 0;
	always @ ( posedge rcvd_clk)
		  nlii1l12 <= nlii1l11;
	initial
		nlii1O10 = 0;
	always @ ( posedge rcvd_clk)
		  nlii1O10 <= nlii1O9;
	initial
		nlii1O9 = 0;
	always @ ( posedge rcvd_clk)
		  nlii1O9 <= nlii1O10;
	event nlii1O9_event;
	initial
		#1 ->nlii1O9_event;
	always @(nlii1O9_event)
		nlii1O9 <= {1{1'b1}};
	initial
		nliiil3 = 0;
	always @ ( posedge rcvd_clk)
		  nliiil3 <= nliiil4;
	event nliiil3_event;
	initial
		#1 ->nliiil3_event;
	always @(nliiil3_event)
		nliiil3 <= {1{1'b1}};
	initial
		nliiil4 = 0;
	always @ ( posedge rcvd_clk)
		  nliiil4 <= nliiil3;
	initial
		nliili1 = 0;
	always @ ( posedge rcvd_clk)
		  nliili1 <= nliili2;
	event nliili1_event;
	initial
		#1 ->nliili1_event;
	always @(nliili1_event)
		nliili1 <= {1{1'b1}};
	initial
		nliili2 = 0;
	always @ ( posedge rcvd_clk)
		  nliili2 <= nliili1;
	initial
	begin
		n0OO = 0;
		n1ilO = 0;
		n1iOi = 0;
		n1iOl = 0;
		n1iOO = 0;
		n1l0i = 0;
		n1l0l = 0;
		n1l0O = 0;
		n1l1i = 0;
		n1l1l = 0;
		n1l1O = 0;
		n1lii = 0;
		n1lil = 0;
		n1liO = 0;
		n1lli = 0;
		n1lll = 0;
		n1llO = 0;
		n1lOi = 0;
		n1lOl = 0;
		n1lOO = 0;
		n1O1i = 0;
		n1O1l = 0;
		n1O1O = 0;
		nlOO1l = 0;
		nlOOll = 0;
	end
	always @ (rcvd_clk or wire_niii_dataout or wire_n0Ol_CLRN)
	begin
		if (wire_niii_dataout == 1'b1) 
		begin
			n0OO <= 1;
			n1ilO <= 1;
			n1iOi <= 1;
			n1iOl <= 1;
			n1iOO <= 1;
			n1l0i <= 1;
			n1l0l <= 1;
			n1l0O <= 1;
			n1l1i <= 1;
			n1l1l <= 1;
			n1l1O <= 1;
			n1lii <= 1;
			n1lil <= 1;
			n1liO <= 1;
			n1lli <= 1;
			n1lll <= 1;
			n1llO <= 1;
			n1lOi <= 1;
			n1lOl <= 1;
			n1lOO <= 1;
			n1O1i <= 1;
			n1O1l <= 1;
			n1O1O <= 1;
			nlOO1l <= 1;
			nlOOll <= 1;
		end
		else if  (wire_n0Ol_CLRN == 1'b0) 
		begin
			n0OO <= 0;
			n1ilO <= 0;
			n1iOi <= 0;
			n1iOl <= 0;
			n1iOO <= 0;
			n1l0i <= 0;
			n1l0l <= 0;
			n1l0O <= 0;
			n1l1i <= 0;
			n1l1l <= 0;
			n1l1O <= 0;
			n1lii <= 0;
			n1lil <= 0;
			n1liO <= 0;
			n1lli <= 0;
			n1lll <= 0;
			n1llO <= 0;
			n1lOi <= 0;
			n1lOl <= 0;
			n1lOO <= 0;
			n1O1i <= 0;
			n1O1l <= 0;
			n1O1O <= 0;
			nlOO1l <= 0;
			nlOOll <= 0;
		end
		else 
		if (rcvd_clk != n0Ol_clk_prev && rcvd_clk == 1'b1) 
		begin
			n0OO <= wire_n10i_dataout;
			n1ilO <= wire_n1O0O_dataout;
			n1iOi <= wire_n1Oii_dataout;
			n1iOl <= wire_n1Oil_dataout;
			n1iOO <= wire_n1OiO_dataout;
			n1l0i <= wire_n1OOi_dataout;
			n1l0l <= wire_n1OOl_dataout;
			n1l0O <= wire_n1OOO_dataout;
			n1l1i <= wire_n1Oli_dataout;
			n1l1l <= wire_n1Oll_dataout;
			n1l1O <= wire_n1OlO_dataout;
			n1lii <= wire_n011i_dataout;
			n1lil <= wire_n011l_dataout;
			n1liO <= wire_n011O_dataout;
			n1lli <= wire_n010i_dataout;
			n1lll <= wire_n010l_dataout;
			n1llO <= wire_n010O_dataout;
			n1lOi <= wire_n01ii_dataout;
			n1lOl <= wire_n01il_dataout;
			n1lOO <= wire_n01iO_dataout;
			n1O1i <= wire_n01li_dataout;
			n1O1l <= wire_n01ll_dataout;
			n1O1O <= wire_n01lO_dataout;
			nlOO1l <= wire_n1O0l_dataout;
			nlOOll <= wire_nlOO1O_dataout;
		end
		n0Ol_clk_prev <= rcvd_clk;
	end
	assign
		wire_n0Ol_CLRN = (nlii0l6 ^ nlii0l5);
	initial
	begin
		n0li = 0;
		n0ll = 0;
		n0lO = 0;
		n0Oi = 0;
		n1O0i = 0;
		ni0l = 0;
		ni1i = 0;
		ni1l = 0;
		ni1O = 0;
		nlOlll = 0;
		nlOllO = 0;
		nlOlOi = 0;
		nlOlOl = 0;
		nlOlOO = 0;
		nlOO1i = 0;
	end
	always @ ( posedge rcvd_clk or  negedge wire_ni0i_CLRN)
	begin
		if (wire_ni0i_CLRN == 1'b0) 
		begin
			n0li <= 0;
			n0ll <= 0;
			n0lO <= 0;
			n0Oi <= 0;
			n1O0i <= 0;
			ni0l <= 0;
			ni1i <= 0;
			ni1l <= 0;
			ni1O <= 0;
			nlOlll <= 0;
			nlOllO <= 0;
			nlOlOi <= 0;
			nlOlOl <= 0;
			nlOlOO <= 0;
			nlOO1i <= 0;
		end
		else 
		begin
			n0li <= wire_nlOOO_dataout;
			n0ll <= wire_n11i_dataout;
			n0lO <= wire_n11l_dataout;
			n0Oi <= wire_n11O_dataout;
			n1O0i <= wire_nlOOl_dataout;
			ni0l <= rprbs_en_rx;
			ni1i <= nlii0O;
			ni1l <= nliiii;
			ni1O <= ni0l;
			nlOlll <= wire_nlOO0i_dataout;
			nlOllO <= nlOlOi;
			nlOlOi <= nlOlOl;
			nlOlOl <= wire_nlOO0l_dataout;
			nlOlOO <= wire_nlOOii_dataout;
			nlOO1i <= wire_nlOO0O_dataout;
		end
	end
	assign
		wire_ni0i_CLRN = ((nliiil4 ^ nliiil3) & (~ wire_niii_dataout));
	initial
	begin
		ni0O = 0;
		niiO = 0;
	end
	always @ (rcvd_clk or soft_reset or wire_niil_CLRN)
	begin
		if (soft_reset == 1'b1) 
		begin
			ni0O <= 1;
			niiO <= 1;
		end
		else if  (wire_niil_CLRN == 1'b0) 
		begin
			ni0O <= 0;
			niiO <= 0;
		end
		else 
		if (rcvd_clk != niil_clk_prev && rcvd_clk == 1'b1) 
		begin
			ni0O <= niiO;
			niiO <= nliill;
		end
		niil_clk_prev <= rcvd_clk;
	end
	assign
		wire_niil_CLRN = (nliili2 ^ nliili1);
	assign		wire_n000i_dataout = ((~ nlOlOO) === 1'b1) ? wire_nll0l_o : wire_n0ilO_dataout;
	assign		wire_n000l_dataout = ((~ nlOlOO) === 1'b1) ? (~ nl0Oli) : wire_n0iOi_dataout;
	assign		wire_n000O_dataout = ((~ nlOlOO) === 1'b1) ? wire_nllil_o : wire_n0iOl_dataout;
	assign		wire_n001i_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli10l) : wire_n0iiO_dataout;
	assign		wire_n001l_dataout = ((~ nlOlOO) === 1'b1) ? wire_nliOO_o : wire_n0ili_dataout;
	assign		wire_n001O_dataout = ((~ nlOlOO) === 1'b1) ? wire_nll1O_o : wire_n0ill_dataout;
	and(wire_n00i_dataout, nli0ll, n0OO);
	assign		wire_n00ii_dataout = ((~ nlOlOO) === 1'b1) ? wire_nllll_o : wire_n0iOO_dataout;
	assign		wire_n00il_dataout = ((~ nlOlOO) === 1'b1) ? (~ ((wire_n110l_o[25] | wire_n110l_o[8]) | wire_n110l_o[0])) : wire_n0l1i_dataout;
	assign		wire_n00iO_dataout = ((~ nlOlOO) === 1'b1) ? (~ (((wire_n110l_o[25] | wire_n110l_o[24]) | wire_n110l_o[8]) | wire_n110l_o[0])) : wire_n0l1l_dataout;
	and(wire_n00l_dataout, nli0OO, n0li);
	assign		wire_n00li_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli11i) : wire_n0l1O_dataout;
	assign		wire_n00ll_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli11i) : wire_n0l0i_dataout;
	assign		wire_n00lO_dataout = ((~ nlOlOO) === 1'b1) ? (~ (((wire_n110l_o[25] | wire_n110l_o[17]) | wire_n110l_o[8]) | wire_n110l_o[0])) : wire_n0l0l_dataout;
	and(wire_n00O_dataout, nli0Ol, n0ll);
	assign		wire_n00Oi_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli1il) : wire_n0l0O_dataout;
	assign		wire_n00Ol_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli10i) : wire_n0lii_dataout;
	assign		wire_n00OO_dataout = ((~ nlOlOO) === 1'b1) ? (~ (((wire_n110l_o[17] | wire_n110l_o[16]) | wire_n110l_o[8]) | wire_n110l_o[0])) : wire_n0lil_dataout;
	or(wire_n010i_dataout, wire_n00lO_dataout, (~ ni1O));
	or(wire_n010l_dataout, wire_n00Oi_dataout, (~ ni1O));
	or(wire_n010O_dataout, wire_n00Ol_dataout, (~ ni1O));
	or(wire_n011i_dataout, wire_n00iO_dataout, (~ ni1O));
	or(wire_n011l_dataout, wire_n00li_dataout, (~ ni1O));
	or(wire_n011O_dataout, wire_n00ll_dataout, (~ ni1O));
	and(wire_n01i_dataout, nli00O, n0lO);
	or(wire_n01ii_dataout, wire_n00OO_dataout, (~ ni1O));
	or(wire_n01il_dataout, wire_n0i1i_dataout, (~ ni1O));
	or(wire_n01iO_dataout, wire_n0i1l_dataout, (~ ni1O));
	and(wire_n01l_dataout, nli00i, n0Oi);
	or(wire_n01li_dataout, wire_n0i1O_dataout, (~ ni1O));
	or(wire_n01ll_dataout, wire_n0i0i_dataout, (~ ni1O));
	or(wire_n01lO_dataout, wire_n0i0l_dataout, (~ ni1O));
	assign		wire_n01Oi_dataout = ((~ nlOlOO) === 1'b1) ? wire_nli0O_o : wire_n0i0O_dataout;
	assign		wire_n01Ol_dataout = ((~ nlOlOO) === 1'b1) ? wire_nliiO_o : wire_n0iii_dataout;
	assign		wire_n01OO_dataout = ((~ nlOlOO) === 1'b1) ? wire_nlilO_o : wire_n0iil_dataout;
	and(wire_n0i_dataout, n1lOl, nliiOi);
	assign		wire_n0i0i_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli10l) : wire_n0llO_dataout;
	assign		wire_n0i0l_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli1il) : wire_n0lOi_dataout;
	assign		wire_n0i0O_dataout = (nl0lli === 1'b1) ? wire_n0lOl_o : nlOO1l;
	assign		wire_n0i1i_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli10l) : wire_n0liO_dataout;
	assign		wire_n0i1l_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli10l) : wire_n0lli_dataout;
	assign		wire_n0i1O_dataout = ((~ nlOlOO) === 1'b1) ? (~ nli10l) : wire_n0lll_dataout;
	and(wire_n0ii_dataout, nli0Oi, n0lO);
	assign		wire_n0iii_dataout = (nl0lli === 1'b1) ? wire_n0lOO_o : n1ilO;
	assign		wire_n0iil_dataout = (nl0lli === 1'b1) ? wire_n0O1i_o : n1iOi;
	assign		wire_n0iiO_dataout = (nl0lli === 1'b1) ? wire_n0O1l_o : n1iOl;
	and(wire_n0il_dataout, nli0lO, n0Oi);
	assign		wire_n0ili_dataout = (nl0lli === 1'b1) ? wire_n0O1O_o : n1iOO;
	assign		wire_n0ill_dataout = (nl0lli === 1'b1) ? wire_n0O0i_o : n1l1i;
	assign		wire_n0ilO_dataout = (nl0lli === 1'b1) ? wire_n0O0l_o : n1l1l;
	assign		wire_n0iOi_dataout = (nl0lli === 1'b1) ? wire_n0O0O_o : n1l1O;
	assign		wire_n0iOl_dataout = (nl0lli === 1'b1) ? wire_n0Oii_o : n1l0i;
	assign		wire_n0iOO_dataout = (nl0lli === 1'b1) ? wire_n0Oil_o : n1l0l;
	and(wire_n0l_dataout, n1lOi, nliiOi);
	assign		wire_n0l0i_dataout = (nl0lli === 1'b1) ? wire_n0OlO_o : n1liO;
	assign		wire_n0l0l_dataout = (nl0lli === 1'b1) ? wire_n0OOi_o : n1lli;
	assign		wire_n0l0O_dataout = (nl0lli === 1'b1) ? wire_n0OOl_o : n1lll;
	assign		wire_n0l1i_dataout = (nl0lli === 1'b1) ? wire_n0OiO_o : n1l0O;
	assign		wire_n0l1l_dataout = (nl0lli === 1'b1) ? wire_n0Oli_o : n1lii;
	assign		wire_n0l1O_dataout = (nl0lli === 1'b1) ? wire_n0Oll_o : n1lil;
	assign		wire_n0lii_dataout = (nl0lli === 1'b1) ? wire_ni11i_o : n1llO;
	assign		wire_n0lil_dataout = (nl0lli === 1'b1) ? wire_ni11l_o : n1lOi;
	assign		wire_n0liO_dataout = (nl0lli === 1'b1) ? wire_ni11O_o : n1lOl;
	assign		wire_n0lli_dataout = (nl0lli === 1'b1) ? wire_ni10i_o : n1lOO;
	assign		wire_n0lll_dataout = (nl0lli === 1'b1) ? wire_ni10O_o : n1O1i;
	assign		wire_n0llO_dataout = (nl0lli === 1'b1) ? wire_ni1ii_o : n1O1l;
	assign		wire_n0lOi_dataout = (nl0lli === 1'b1) ? wire_ni1il_o : n1O1O;
	and(wire_n0O_dataout, n1llO, nliiOi);
	assign		wire_n10i_dataout = (nli1OO === 1'b1) ? wire_n0iO_o : wire_n1lO_dataout;
	and(wire_n10l_dataout, n1O0i, nli01i);
	assign		wire_n10lO_dataout = (rall_one_dect_only === 1'b1) ? ((nlOlOO & nl01ll) | nlOO1i) : ((nlOlOO & nl01lO) | nlOO1i);
	and(wire_n10O_dataout, wire_n1Oi_dataout, nli01i);
	assign		wire_n11i_dataout = (nli1OO === 1'b1) ? wire_n0ii_dataout : wire_n1iO_dataout;
	assign		wire_n11l_dataout = (nli1OO === 1'b1) ? wire_n0il_dataout : wire_n1li_dataout;
	assign		wire_n11O_dataout = (nli1OO === 1'b1) ? wire_n00i_dataout : wire_n1ll_dataout;
	and(wire_n1i_dataout, n1O1l, nliiOi);
	assign		wire_n1i0l_dataout = (rall_one_dect_only === 1'b1) ? ((nlOlOO & nl001i) | nlOO1i) : ((nlOlOO & nl001l) | nlOO1i);
	assign		wire_n1ii_dataout = (nli01i === 1'b1) ? wire_n1Ol_dataout : n1O0i;
	assign		wire_n1il_dataout = (nli01i === 1'b1) ? wire_n1OO_dataout : n0li;
	assign		wire_n1iO_dataout = (nli01i === 1'b1) ? wire_n01i_dataout : n0ll;
	and(wire_n1l_dataout, n1O1i, nliiOi);
	assign		wire_n1li_dataout = (nli01i === 1'b1) ? wire_n01l_dataout : n0lO;
	assign		wire_n1ll_dataout = (nli01i === 1'b1) ? wire_n1Oi_dataout : n0Oi;
	assign		wire_n1lO_dataout = (nli01i === 1'b1) ? wire_n01O_o : n0OO;
	and(wire_n1O_dataout, n1lOO, nliiOi);
	or(wire_n1O0l_dataout, wire_n01Oi_dataout, (~ ni1O));
	or(wire_n1O0O_dataout, wire_n01Ol_dataout, (~ ni1O));
	and(wire_n1Oi_dataout, nli01l, n0OO);
	or(wire_n1Oii_dataout, wire_n01OO_dataout, (~ ni1O));
	or(wire_n1Oil_dataout, wire_n001i_dataout, (~ ni1O));
	or(wire_n1OiO_dataout, wire_n001l_dataout, (~ ni1O));
	and(wire_n1Ol_dataout, nli0il, n0li);
	or(wire_n1Oli_dataout, wire_n001O_dataout, (~ ni1O));
	or(wire_n1Oll_dataout, wire_n000i_dataout, (~ ni1O));
	or(wire_n1OlO_dataout, wire_n000l_dataout, (~ ni1O));
	and(wire_n1OO_dataout, nli0ii, n0ll);
	or(wire_n1OOi_dataout, wire_n000O_dataout, (~ ni1O));
	or(wire_n1OOl_dataout, wire_n00ii_dataout, (~ ni1O));
	or(wire_n1OOO_dataout, wire_n00il_dataout, (~ ni1O));
	and(wire_ni_dataout, n1l0l, nliiOi);
	and(wire_nii_dataout, n1lll, nliiOi);
	and(wire_niii_dataout, ni0O, ~(scan_mode));
	and(wire_nil_dataout, n1lli, nliiOi);
	assign		wire_nili_dataout = (nliilO === 1'b1) ? n1O1O : wire_nlOO_dataout;
	assign		wire_nill_dataout = (nliilO === 1'b1) ? n1O1l : wire_n1i_dataout;
	assign		wire_nilO_dataout = (nliilO === 1'b1) ? n1O1i : wire_n1l_dataout;
	and(wire_niO_dataout, n1liO, nliiOi);
	assign		wire_niOi_dataout = (nliilO === 1'b1) ? n1lOO : wire_n1O_dataout;
	assign		wire_niOl_dataout = (nliilO === 1'b1) ? n1lOl : wire_n0i_dataout;
	assign		wire_niOO_dataout = (nliilO === 1'b1) ? n1lOi : wire_n0l_dataout;
	and(wire_nl_dataout, n1l0i, nliiOi);
	assign		wire_nl0i_dataout = (nliilO === 1'b1) ? n1liO : wire_niO_dataout;
	assign		wire_nl0l_dataout = (nliilO === 1'b1) ? n1lil : wire_nli_dataout;
	assign		wire_nl0O_dataout = (nliilO === 1'b1) ? n1lii : wire_nll_dataout;
	assign		wire_nl1i_dataout = (nliilO === 1'b1) ? n1llO : wire_n0O_dataout;
	assign		wire_nl1l_dataout = (nliilO === 1'b1) ? n1lll : wire_nii_dataout;
	assign		wire_nl1O_dataout = (nliilO === 1'b1) ? n1lli : wire_nil_dataout;
	and(wire_nli_dataout, n1lil, nliiOi);
	assign		wire_nlii_dataout = (nliilO === 1'b1) ? n1l0O : wire_nlO_dataout;
	assign		wire_nlil_dataout = (nliilO === 1'b1) ? n1l0l : wire_ni_dataout;
	assign		wire_nliO_dataout = (nliilO === 1'b1) ? n1l0i : wire_nl_dataout;
	and(wire_nll_dataout, n1lii, nliiOi);
	assign		wire_nlli_dataout = (nliilO === 1'b1) ? n1l1O : wire_nO_dataout;
	and(wire_nlll_dataout, n1l1l, nliilO);
	and(wire_nllO_dataout, n1l1i, nliilO);
	and(wire_nlO_dataout, n1l0O, nliiOi);
	and(wire_nlOi_dataout, n1iOO, nliilO);
	assign		wire_nlOii_dataout = (rall_one_dect_only === 1'b1) ? wire_nlOOi_dataout : wire_nlOlO_dataout;
	assign		wire_nlOil_dataout = (nliilO === 1'b1) ? ((ni1l & nli1Oi) & (nli1ll24 ^ nli1ll23)) : wire_nlOiO_dataout;
	and(wire_nlOiO_dataout, (ni1i & nli1Ol), nliiOi);
	and(wire_nlOl_dataout, n1iOl, nliilO);
	assign		wire_nlOlO_dataout = (nli1OO === 1'b1) ? n1O0i : wire_n10l_dataout;
	and(wire_nlOO_dataout, n1O1O, nliiOi);
	and(wire_nlOO0i_dataout, wire_nlOOli_dataout, ~((~ ni1O)));
	and(wire_nlOO0l_dataout, wire_nlOOlO_dataout, ~((~ ni1O)));
	and(wire_nlOO0O_dataout, wire_nlOOOi_dataout, ~((~ ni1O)));
	or(wire_nlOO1O_dataout, wire_nlOOil_dataout, (~ ni1O));
	assign		wire_nlOOi_dataout = (nli1OO === 1'b1) ? wire_n00i_dataout : wire_n10O_dataout;
	and(wire_nlOOii_dataout, wire_nlOOiO_dataout, ~((~ ni1O)));
	assign		wire_nlOOil_dataout = (rprbs_clr_rslt_rx === 1'b1) ? nlOOll : wire_nlOOOl_o;
	assign		wire_nlOOiO_dataout = (rprbs_clr_rslt_rx === 1'b1) ? nlOlOO : wire_n111O_o;
	assign		wire_nlOOl_dataout = (nli1OO === 1'b1) ? wire_n00l_dataout : wire_n1ii_dataout;
	and(wire_nlOOli_dataout, wire_n111i_o, ~(rprbs_clr_rslt_rx));
	and(wire_nlOOlO_dataout, wire_n111l_o, ~(rprbs_clr_rslt_rx));
	assign		wire_nlOOO_dataout = (nli1OO === 1'b1) ? wire_n00O_dataout : wire_n1il_dataout;
	and(wire_nlOOOi_dataout, wire_nlOOOO_o, ~(rprbs_clr_rslt_rx));
	and(wire_nO_dataout, n1l1O, nliiOi);
	oper_decoder   n110l
	( 
	.i({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]}),
	.o(wire_n110l_o));
	defparam
		n110l.width_i = 5,
		n110l.width_o = 32;
	oper_selector   n01O
	( 
	.data({(~ nli01l), ((nli01O22 ^ nli01O21) & (~ nli00i)), ((nli00l20 ^ nli00l19) & (~ nli00O)), (~ nli0ii), (~ nli0il), 1'b1}),
	.o(wire_n01O_o),
	.sel({n0OO, ((nli0iO18 ^ nli0iO17) & n0Oi), n0lO, n0ll, n0li, ((nli0li16 ^ nli0li15) & n1O0i)}));
	defparam
		n01O.width_data = 6,
		n01O.width_sel = 6;
	oper_selector   n0iO
	( 
	.data({(~ nli0ll), (~ nli0lO), (~ nli0Oi), (~ nli0Ol), (~ nli0OO), 1'b1}),
	.o(wire_n0iO_o),
	.sel({((nlii1i14 ^ nlii1i13) & n0OO), n0Oi, ((nlii1l12 ^ nlii1l11) & n0lO), ((nlii1O10 ^ nlii1O9) & n0ll), n0li, ((nlii0i8 ^ nlii0i7) & n1O0i)}));
	defparam
		n0iO.width_data = 6,
		n0iO.width_sel = 6;
	oper_selector   n0lOl
	( 
	.data({1'b0, ((n1llO ^ n1iOl) ^ n1O1l), nl0iOO, nl00iO, (n1l0O ^ n1l0l), nl0lii, ((nl0lil ^ n1ilO) ^ nlOO1l)}),
	.o(wire_n0lOl_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0lOl.width_data = 7,
		n0lOl.width_sel = 7;
	oper_selector   n0lOO
	( 
	.data({1'b0, ((n1lOi ^ n1iOO) ^ n1O1O), nl0l1i, nl00li, (n1lii ^ n1l0O), nl0l0O, ((nl0liO ^ n1iOi) ^ n1ilO)}),
	.o(wire_n0lOO_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0lOO.width_data = 7,
		n0lOO.width_sel = 7;
	oper_selector   n0O0i
	( 
	.data({1'b0, nl00li, nl0iOl, nl00Ol, nl0l1i, (n1l0i ^ n1l1i), ((n1l1i ^ n1iOO) ^ n1ilO)}),
	.o(wire_n0O0i_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0O0i.width_data = 7,
		n0O0i.width_sel = 7;
	oper_selector   n0O0l
	( 
	.data({1'b0, nl00ll, (nl0i0O ^ n1liO), nl00OO, (nl0i1l ^ n1l0l), (n1l0l ^ n1l1l), (nl0lil ^ n1iOi)}),
	.o(wire_n0O0l_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0O0l.width_data = 7,
		n0O0l.width_sel = 7;
	oper_selector   n0O0O
	( 
	.data({1'b0, nl00lO, nl0l1l, nl0i1i, (n1lii ^ n1l0l), (nl0lii ^ n1l1O), (nl0liO ^ n1iOl)}),
	.o(wire_n0O0O_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0O0O.width_data = 7,
		n0O0O.width_sel = 7;
	oper_selector   n0O1i
	( 
	.data({1'b0, (n1l1i ^ nlOO1l), nl0ili, nl00ll, nl0l1O, nl0l0l, (((((nl0liO ^ n1l1i) ^ n1iOl) ^ n1iOi) ^ n1ilO) ^ nlOO1l)}),
	.o(wire_n0O1i_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0O1i.width_data = 7,
		n0O1i.width_sel = 7;
	oper_selector   n0O1l
	( 
	.data({1'b0, (n1l1l ^ n1ilO), nl0ill, nl00lO, nl0l0i, (n1l1l ^ n1iOl), (((((n1l1O ^ n1l1i) ^ n1iOO) ^ n1iOl) ^ n1iOi) ^ nlOO1l)}),
	.o(wire_n0O1l_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0O1l.width_data = 7,
		n0O1l.width_sel = 7;
	oper_selector   n0O1O
	( 
	.data({1'b0, nl00iO, nl0ilO, nl00Oi, nl0iOO, (n1l1O ^ n1iOO), ((n1iOO ^ n1iOl) ^ nlOO1l)}),
	.o(wire_n0O1O_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0O1O.width_data = 7,
		n0O1O.width_sel = 7;
	oper_selector   n0Oii
	( 
	.data({1'b0, nl00Oi, (n1llO ^ n1lli), nl0i1l, (n1lil ^ n1l0O), (nl0l0O ^ n1l0i), 1'b1}),
	.o(wire_n0Oii_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0Oii.width_data = 7,
		n0Oii.width_sel = 7;
	oper_selector   n0Oil
	( 
	.data({1'b0, nl00Ol, (n1lOi ^ n1lll), nl0i1O, (n1liO ^ n1lii), (nl0l0l ^ n1l0l), 1'b1}),
	.o(wire_n0Oil_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n0Oil.width_data = 7,
		n0Oil.width_sel = 7;
	oper_selector   n0OiO
	( 
	.data({1'b0, nl00OO, (n1lOl ^ n1llO), nl0i0i, (n1lli ^ n1lil), 1'b1}),
	.o(wire_n0OiO_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], nl000l}));
	defparam
		n0OiO.width_data = 6,
		n0OiO.width_sel = 6;
	oper_selector   n0Oli
	( 
	.data({1'b0, nl0i1i, (n1lOO ^ n1lOi), nl0i0l, nl0l1l, 1'b1}),
	.o(wire_n0Oli_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], nl000l}));
	defparam
		n0Oli.width_data = 6,
		n0Oli.width_sel = 6;
	oper_selector   n0Oll
	( 
	.data({1'b0, nl0i1l, ((n1lOl ^ n1lli) ^ n1liO), nl0i0O, ((n1lli ^ n1l0O) ^ n1l0l), 1'b1}),
	.o(wire_n0Oll_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], nl000l}));
	defparam
		n0Oll.width_data = 6,
		n0Oll.width_sel = 6;
	oper_selector   n0OlO
	( 
	.data({1'b0, nl0i1O, ((n1lOO ^ n1lll) ^ n1lli), nl0iii, ((n1lll ^ n1lii) ^ n1l0O), 1'b1}),
	.o(wire_n0OlO_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], nl000l}));
	defparam
		n0OlO.width_data = 6,
		n0OlO.width_sel = 6;
	oper_selector   n0OOi
	( 
	.data({1'b0, nl0i0i, ((nl0ili ^ n1lli) ^ n1liO), nl0iil, ((nl0l1O ^ n1l0O) ^ n1l0l), 1'b1}),
	.o(wire_n0OOi_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], nl000l}));
	defparam
		n0OOi.width_data = 6,
		n0OOi.width_sel = 6;
	oper_selector   n0OOl
	( 
	.data({1'b0, nl0i0l, ((nl0ill ^ n1lll) ^ n1lli), nl0iiO, ((nl0l0i ^ n1lii) ^ n1l0O), 1'b1}),
	.o(wire_n0OOl_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], nl000l}));
	defparam
		n0OOl.width_data = 6,
		n0OOl.width_sel = 6;
	oper_selector   n111i
	( 
	.data({1'b0, (nl011i | nlOlll), (nl010i | nlOlll), (nl010O | nlOlll), (nl01il | nlOlll), (nl01Oi | nlOlll), (nl001O | nlOlll)}),
	.o(wire_n111i_o),
	.sel({nl1OOi, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n111i.width_data = 7,
		n111i.width_sel = 7;
	oper_selector   n111l
	( 
	.data({1'b0, nl011i, nl010i, nl010O, nl01il, nl01Oi, nl001O}),
	.o(wire_n111l_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n111l.width_data = 7,
		n111l.width_sel = 7;
	oper_selector   n111O
	( 
	.data({1'b0, nl011O, (nlOlOO | nl1Oll), nl011O, (nlOlOO | nl1OlO), {2{nl01OO}}}),
	.o(wire_n111O_o),
	.sel({nl1OOi, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		n111O.width_data = 7,
		n111O.width_sel = 7;
	oper_selector   ni10i
	( 
	.data({1'b0, nl0iiO, ((nl0iOl ^ n1lll) ^ n1liO), n1iOl, 1'b1}),
	.o(wire_ni10i_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17], nl000O}));
	defparam
		ni10i.width_data = 5,
		ni10i.width_sel = 5;
	oper_selector   ni10O
	( 
	.data({1'b0, nlOO1l, 1'b1, n1iOO}),
	.o(wire_ni10O_o),
	.sel({nl00il, wire_n110l_o[25], nl00ii, wire_n110l_o[17]}));
	defparam
		ni10O.width_data = 4,
		ni10O.width_sel = 4;
	oper_selector   ni11i
	( 
	.data({1'b0, nl0i0O, ((nl0ilO ^ n1llO) ^ n1lll), nlOO1l, 1'b1}),
	.o(wire_ni11i_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17], nl000O}));
	defparam
		ni11i.width_data = 5,
		ni11i.width_sel = 5;
	oper_selector   ni11l
	( 
	.data({1'b0, nl0iii, (nl0iOi ^ n1llO), n1ilO, 1'b1}),
	.o(wire_ni11l_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17], nl000O}));
	defparam
		ni11l.width_data = 5,
		ni11l.width_sel = 5;
	oper_selector   ni11O
	( 
	.data({1'b0, nl0iil, ((nl0iOi ^ n1lli) ^ n1liO), n1iOi, 1'b1}),
	.o(wire_ni11O_o),
	.sel({nl00il, wire_n110l_o[25:24], wire_n110l_o[17], nl000O}));
	defparam
		ni11O.width_data = 5,
		ni11O.width_sel = 5;
	oper_selector   ni1ii
	( 
	.data({1'b0, n1ilO, 1'b1, n1l1i}),
	.o(wire_ni1ii_o),
	.sel({nl00il, wire_n110l_o[25], nl00ii, wire_n110l_o[17]}));
	defparam
		ni1ii.width_data = 4,
		ni1ii.width_sel = 4;
	oper_selector   ni1il
	( 
	.data({1'b0, n1iOi, 1'b1, n1l1l}),
	.o(wire_ni1il_o),
	.sel({nl00il, wire_n110l_o[25], nl00ii, wire_n110l_o[17]}));
	defparam
		ni1il.width_data = 4,
		ni1il.width_sel = 4;
	oper_selector   nli0O
	( 
	.data({1'b1, 1'b0, (~ rall_one_dect_only)}),
	.o(wire_nli0O_o),
	.sel({nl0lll, ((wire_n110l_o[17] | wire_n110l_o[16]) | wire_n110l_o[0]), wire_n110l_o[8]}));
	defparam
		nli0O.width_data = 3,
		nli0O.width_sel = 3;
	oper_selector   nliiO
	( 
	.data({1'b1, 1'b0, {2{(~ rall_one_dect_only)}}}),
	.o(wire_nliiO_o),
	.sel({nl0llO, ((wire_n110l_o[24] | wire_n110l_o[17]) | wire_n110l_o[16]), wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		nliiO.width_data = 4,
		nliiO.width_sel = 4;
	oper_selector   nlilO
	( 
	.data({1'b1, 1'b0, rall_one_dect_only}),
	.o(wire_nlilO_o),
	.sel({nl0lOi, ((wire_n110l_o[24] | wire_n110l_o[17]) | wire_n110l_o[8]), wire_n110l_o[0]}));
	defparam
		nlilO.width_data = 3,
		nlilO.width_sel = 3;
	oper_selector   nliOO
	( 
	.data({1'b1, 1'b0, ((nl0lOl46 ^ nl0lOl45) & (~ rall_one_dect_only)), rall_one_dect_only}),
	.o(wire_nliOO_o),
	.sel({nl0O1l, ((wire_n110l_o[25] | wire_n110l_o[17]) | (~ (nl0lOO44 ^ nl0lOO43))), wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		nliOO.width_data = 4,
		nliOO.width_sel = 4;
	oper_selector   nll0l
	( 
	.data({1'b1, 1'b0, (~ rall_one_dect_only), ((nl0O0l40 ^ nl0O0l39) & rall_one_dect_only)}),
	.o(wire_nll0l_o),
	.sel({nl0Oii, nl0Oli, ((nl0O0O38 ^ nl0O0O37) & wire_n110l_o[8]), wire_n110l_o[0]}));
	defparam
		nll0l.width_data = 4,
		nll0l.width_sel = 4;
	oper_selector   nll1O
	( 
	.data({1'b1, 1'b0, rall_one_dect_only}),
	.o(wire_nll1O_o),
	.sel({nl0Oii, (((wire_n110l_o[25] | wire_n110l_o[17]) | wire_n110l_o[16]) | wire_n110l_o[8]), wire_n110l_o[0]}));
	defparam
		nll1O.width_data = 3,
		nll1O.width_sel = 3;
	oper_selector   nllil
	( 
	.data({1'b1, 1'b0, rall_one_dect_only}),
	.o(wire_nllil_o),
	.sel({nl0OOl, ((((wire_n110l_o[25] | wire_n110l_o[24]) | wire_n110l_o[17]) | wire_n110l_o[0]) | (~ (nl0Oll34 ^ nl0Oll33))), ((nl0OOi32 ^ nl0OOi31) & wire_n110l_o[8])}));
	defparam
		nllil.width_data = 3,
		nllil.width_sel = 3;
	oper_selector   nllll
	( 
	.data({1'b1, 1'b0, rall_one_dect_only}),
	.o(wire_nllll_o),
	.sel({nl0OOO, ((wire_n110l_o[25] | wire_n110l_o[24]) | wire_n110l_o[0]), wire_n110l_o[8]}));
	defparam
		nllll.width_data = 3,
		nllll.width_sel = 3;
	oper_selector   nlOOOl
	( 
	.data({nlOOll, nl1OOl, (nlOOll & (~ nl1Oll)), nl1OOl, (nlOOll & (~ nl1OlO)), {2{nl01li}}}),
	.o(wire_nlOOOl_o),
	.sel({nl1OOi, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		nlOOOl.width_data = 7,
		nlOOOl.width_sel = 7;
	oper_selector   nlOOOO
	( 
	.data({1'b0, nl1OOO, ((nlOlOO & nl1OiO) | nlOO1i), nl1OOO, ((nlOlOO & nl1Oli) | nlOO1i), wire_n10lO_dataout, wire_n1i0l_dataout}),
	.o(wire_nlOOOO_o),
	.sel({nl1OOi, wire_n110l_o[25:24], wire_n110l_o[17:16], wire_n110l_o[8], wire_n110l_o[0]}));
	defparam
		nlOOOO.width_data = 7,
		nlOOOO.width_sel = 7;
	assign
		encdet_prbs = nlOOll,
		nl000i = ((((((((~ (nlOO1l ^ data_in[0])) & (~ (n1ilO ^ data_in[1]))) & (~ (n1iOi ^ data_in[2]))) & (~ (n1iOl ^ data_in[3]))) & (~ (n1iOO ^ data_in[4]))) & (~ (n1l1i ^ data_in[5]))) & (~ (n1l1l ^ data_in[6]))) & (~ (n1l1O ^ data_in[7]))),
		nl000l = (wire_n110l_o[8] | wire_n110l_o[0]),
		nl000O = ((wire_n110l_o[16] | wire_n110l_o[8]) | wire_n110l_o[0]),
		nl001i = (((((((n1l1O & n1l1l) & n1l1i) & n1iOO) & n1iOl) & n1iOi) & n1ilO) & nlOO1l),
		nl001l = (((((((n1l1O & n1l1l) & n1l1i) & (~ n1iOO)) & n1iOl) & (~ n1iOi)) & n1ilO) & nlOO1l),
		nl001O = (nlOlOO & (~ nl000i)),
		nl00ii = (((wire_n110l_o[24] | wire_n110l_o[16]) | wire_n110l_o[8]) | wire_n110l_o[0]),
		nl00il = (((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]),
		nl00iO = (n1l1O ^ n1iOi),
		nl00li = (n1l0i ^ n1iOl),
		nl00ll = (n1l0l ^ n1iOO),
		nl00lO = (n1l0O ^ n1l1i),
		nl00Oi = (n1lii ^ n1l1l),
		nl00Ol = (n1lil ^ n1l1O),
		nl00OO = (n1liO ^ n1l0i),
		nl010i = (nlOlOO & (~ nl010l)),
		nl010l = ((((((((((((((((((((~ (nlOO1l ^ data_in[0])) & (~ (n1ilO ^ data_in[1]))) & (~ (n1iOi ^ data_in[2]))) & (~ (n1iOl ^ data_in[3]))) & (~ (n1iOO ^ data_in[4]))) & (~ (n1l1i ^ data_in[5]))) & (~ (n1l1l ^ data_in[6]))) & (~ (n1l1O ^ data_in[7]))) & (~ (n1l0i ^ data_in[8]))) & (~ (n1l0l ^ data_in[9]))) & (~ (n1l0O ^ data_in[10]))) & (~ (n1lii ^ data_in[11]))) & (~ (n1lil ^ data_in[12]))) & (~ (n1liO ^ data_in[13]))) & (~ (n1lli ^ data_in[14]))) & (~ (n1lll ^ data_in[15]))) & (~ (n1llO ^ data_in[16]))) & (~ (n1lOi ^ data_in[17]))) & (~ (n1lOl ^ data_in[18]))) & (~ (n1lOO ^ data_in[19]))),
		nl010O = (nlOlOO & (~ nl01ii)),
		nl011i = (nlOlOO & (~ nl011l)),
		nl011l = ((((((((((((((((((((~ (wire_nili_dataout ^ data_in[0])) & (~ (wire_nill_dataout ^ data_in[1]))) & (~ (wire_nilO_dataout ^ data_in[2]))) & (~ (wire_niOi_dataout ^ data_in[3]))) & (~ (wire_niOl_dataout ^ data_in[4]))) & (~ (wire_niOO_dataout ^ data_in[5]))) & (~ (wire_nl1i_dataout ^ data_in[6]))) & (~ (wire_nl1l_dataout ^ data_in[7]))) & (~ (wire_nl1O_dataout ^ data_in[8]))) & (~ (wire_nl0i_dataout ^ data_in[9]))) & (~ (wire_nl0l_dataout ^ data_in[10]))) & (~ (wire_nl0O_dataout ^ data_in[11]))) & (~ (wire_nlii_dataout ^ data_in[12]))) & (~ (wire_nlil_dataout ^ data_in[13]))) & (~ (wire_nliO_dataout ^ data_in[14]))) & (~ (wire_nlli_dataout ^ data_in[15]))) & (~ (wire_nlll_dataout ^ data_in[16]))) & (~ (wire_nllO_dataout ^ data_in[17]))) & (~ (wire_nlOi_dataout ^ data_in[18]))) & (~ (wire_nlOl_dataout ^ data_in[19]))),
		nl011O = (wire_nlOil_dataout | nlOlOO),
		nl01ii = ((((((((((((((((~ (wire_nili_dataout ^ data_in[0])) & (~ (wire_nill_dataout ^ data_in[1]))) & (~ (wire_nilO_dataout ^ data_in[2]))) & (~ (wire_niOi_dataout ^ data_in[3]))) & (~ (wire_niOl_dataout ^ data_in[4]))) & (~ (wire_niOO_dataout ^ data_in[5]))) & (~ (wire_nl1i_dataout ^ data_in[6]))) & (~ (wire_nl1l_dataout ^ data_in[7]))) & (~ (wire_nl1O_dataout ^ data_in[10]))) & (~ (wire_nl0i_dataout ^ data_in[11]))) & (~ (wire_nl0l_dataout ^ data_in[12]))) & (~ (wire_nl0O_dataout ^ data_in[13]))) & (~ (wire_nlii_dataout ^ data_in[14]))) & (~ (wire_nlil_dataout ^ data_in[15]))) & (~ (wire_nliO_dataout ^ data_in[16]))) & (~ (wire_nlli_dataout ^ data_in[17]))),
		nl01il = (nlOlOO & (~ nl01iO)),
		nl01iO = ((((((((((((((((~ (nlOO1l ^ data_in[0])) & (~ (n1ilO ^ data_in[1]))) & (~ (n1iOi ^ data_in[2]))) & (~ (n1iOl ^ data_in[3]))) & (~ (n1iOO ^ data_in[4]))) & (~ (n1l1i ^ data_in[5]))) & (~ (n1l1l ^ data_in[6]))) & (~ (n1l1O ^ data_in[7]))) & (~ (n1l0i ^ data_in[10]))) & (~ (n1l0l ^ data_in[11]))) & (~ (n1l0O ^ data_in[12]))) & (~ (n1lii ^ data_in[13]))) & (~ (n1lil ^ data_in[14]))) & (~ (n1liO ^ data_in[15]))) & (~ (n1lli ^ data_in[16]))) & (~ (n1lll ^ data_in[17]))),
		nl01li = ((~ wire_nlOii_dataout) & nlOOll),
		nl01ll = (((((((((n1l0l & n1l0i) & n1l1O) & n1l1l) & n1l1i) & n1iOO) & n1iOl) & n1iOi) & n1ilO) & nlOO1l),
		nl01lO = ((((((((((~ n1l0l) & n1l0i) & (~ n1l1O)) & n1l1l) & n1l1i) & n1iOO) & n1iOl) & n1iOi) & (~ n1ilO)) & (~ nlOO1l)),
		nl01Oi = (nlOlOO & (~ nl01Ol)),
		nl01Ol = ((((((((((~ (nlOO1l ^ data_in[0])) & (~ (n1ilO ^ data_in[1]))) & (~ (n1iOi ^ data_in[2]))) & (~ (n1iOl ^ data_in[3]))) & (~ (n1iOO ^ data_in[4]))) & (~ (n1l1i ^ data_in[5]))) & (~ (n1l1l ^ data_in[6]))) & (~ (n1l1O ^ data_in[7]))) & (~ (n1l0i ^ data_in[8]))) & (~ (n1l0l ^ data_in[9]))),
		nl01OO = (wire_nlOii_dataout | nlOlOO),
		nl0i0i = (n1lOi ^ n1lil),
		nl0i0l = (n1lOl ^ n1liO),
		nl0i0O = (n1lOO ^ n1lli),
		nl0i1i = (n1lli ^ n1l0l),
		nl0i1l = (n1lll ^ n1l0O),
		nl0i1O = (n1llO ^ n1lii),
		nl0iii = (n1O1i ^ n1lll),
		nl0iil = (n1O1l ^ n1llO),
		nl0iiO = (n1O1O ^ n1lOi),
		nl0ili = (n1llO ^ n1lll),
		nl0ill = (n1lOi ^ n1llO),
		nl0ilO = (n1lOl ^ n1lOi),
		nl0iOi = (nl0iOl ^ n1lOi),
		nl0iOl = (n1lOO ^ n1lOl),
		nl0iOO = (n1lli ^ n1liO),
		nl0l0i = (n1liO ^ n1lil),
		nl0l0l = (n1l1i ^ n1iOi),
		nl0l0O = (n1iOO ^ n1ilO),
		nl0l1i = (n1lll ^ n1lli),
		nl0l1l = (n1lll ^ n1liO),
		nl0l1O = (n1lil ^ n1lii),
		nl0lii = (n1iOl ^ nlOO1l),
		nl0lil = (n1l1l ^ n1l1i),
		nl0liO = (n1l1O ^ n1l1l),
		nl0lli = (ni1O & nlOlOO),
		nl0lll = (((((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[25]) | wire_n110l_o[24]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]),
		nl0llO = ((((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[25]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]),
		nl0lOi = (((((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[25]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[16]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]),
		nl0O1l = ((((((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[24]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[16]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]) | (~ (nl0O1O42 ^ nl0O1O41))),
		nl0Oii = (((((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[24]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]) | (~ (nl0Oil36 ^ nl0Oil35))),
		nl0Oli = ((wire_n110l_o[25] | wire_n110l_o[17]) | wire_n110l_o[16]),
		nl0OOl = ((((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[16]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]),
		nl0OOO = (((((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[17]) | wire_n110l_o[16]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]),
		nl1OiO = ((((((((((((((((((((~ n1lOO) & n1lOl) & (~ n1lOi)) & (~ n1llO)) & (~ n1lll)) & (~ n1lli)) & n1liO) & n1lil) & (~ n1lii)) & (~ n1l0O)) & (~ n1l0l)) & (~ n1l0i)) & (~ n1l1O)) & n1l1l) & (~ n1l1i)) & (~ n1iOO)) & (~ n1iOl)) & (~ n1iOi)) & (~ n1ilO)) & (~ nlOO1l)),
		nl1Oli = ((((((((((((((((~ n1lll) & (~ n1lli)) & n1liO) & n1lil) & (~ n1lii)) & (~ n1l0O)) & (~ n1l0l)) & (~ n1l0i)) & (~ n1l1O)) & n1l1l) & (~ n1l1i)) & (~ n1iOO)) & (~ n1iOl)) & (~ n1iOi)) & (~ n1ilO)) & (~ nlOO1l)),
		nl1Oll = ((((((((((((((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])) & (~ data_in[8])) & (~ data_in[9])) & (~ data_in[10])) & (~ data_in[11])) & data_in[12]) & data_in[13]) & (~ data_in[14])) & (~ data_in[15])) & (~ data_in[16])) & (~ data_in[17])) & data_in[18]) & (~ data_in[19])),
		nl1OlO = ((((((((((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])) & (~ data_in[10])) & (~ data_in[11])) & (~ data_in[12])) & (~ data_in[13])) & data_in[14]) & data_in[15]) & (~ data_in[16])) & (~ data_in[17])),
		nl1OOi = (((((((((((((((((((((((((wire_n110l_o[31] | wire_n110l_o[30]) | wire_n110l_o[29]) | wire_n110l_o[28]) | wire_n110l_o[27]) | wire_n110l_o[26]) | wire_n110l_o[23]) | wire_n110l_o[22]) | wire_n110l_o[21]) | wire_n110l_o[20]) | wire_n110l_o[19]) | wire_n110l_o[18]) | wire_n110l_o[15]) | wire_n110l_o[14]) | wire_n110l_o[13]) | wire_n110l_o[12]) | wire_n110l_o[11]) | wire_n110l_o[10]) | wire_n110l_o[9]) | wire_n110l_o[7]) | wire_n110l_o[6]) | wire_n110l_o[5]) | wire_n110l_o[4]) | wire_n110l_o[3]) | wire_n110l_o[2]) | wire_n110l_o[1]),
		nl1OOl = ((~ wire_nlOil_dataout) & nlOOll),
		nl1OOO = ((wire_nlOil_dataout & nlOlOO) | nlOO1i),
		nli00i = ((((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & (~ data_in[6])) & data_in[7]) & data_in[8]) & data_in[9]),
		nli00O = ((((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]) & data_in[8]) & data_in[9]),
		nli01i = ((((rpmadwidth_rx & (~ rpma_doublewidth_rx)) & (~ rprbs_sel[0])) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])),
		nli01l = (((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]) & data_in[8]) & data_in[9]),
		nli0ii = ((((((((((~ data_in[0]) & data_in[1]) & data_in[2]) & data_in[3]) & (~ data_in[4])) & (~ data_in[5])) & (~ data_in[6])) & data_in[7]) & (~ data_in[8])) & (~ data_in[9])),
		nli0il = (((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & (~ data_in[5])) & (~ data_in[6])) & (~ data_in[7])) & data_in[8]) & data_in[9]),
		nli0ll = (((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]),
		nli0lO = ((((((((~ data_in[0]) & (~ data_in[1])) & data_in[2]) & (~ data_in[3])) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]),
		nli0Oi = ((((((((~ data_in[0]) & data_in[1]) & (~ data_in[2])) & (~ data_in[3])) & data_in[4]) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])),
		nli0Ol = ((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & data_in[3]) & data_in[4]) & (~ data_in[5])) & data_in[6]) & data_in[7]),
		nli0OO = (((((((data_in[0] & (~ data_in[1])) & data_in[2]) & data_in[3]) & (~ data_in[4])) & data_in[5]) & data_in[6]) & data_in[7]),
		nli10i = ((((wire_n110l_o[25] | wire_n110l_o[17]) | wire_n110l_o[16]) | wire_n110l_o[8]) | wire_n110l_o[0]),
		nli10l = (((((wire_n110l_o[24] | wire_n110l_o[17]) | wire_n110l_o[16]) | wire_n110l_o[8]) | wire_n110l_o[0]) | (~ (nli10O28 ^ nli10O27))),
		nli11i = (((((wire_n110l_o[25] | wire_n110l_o[24]) | wire_n110l_o[16]) | wire_n110l_o[8]) | wire_n110l_o[0]) | (~ (nli11l30 ^ nli11l29))),
		nli1il = ((((((wire_n110l_o[25] | wire_n110l_o[24]) | wire_n110l_o[17]) | wire_n110l_o[16]) | wire_n110l_o[8]) | wire_n110l_o[0]) | (~ (nli1iO26 ^ nli1iO25))),
		nli1Oi = (((((((((((((((((((data_in[0] & data_in[1]) & data_in[2]) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & (~ data_in[6])) & (~ data_in[7])) & (~ data_in[8])) & (~ data_in[9])) & (~ data_in[10])) & (~ data_in[11])) & (~ data_in[12])) & (~ data_in[13])) & (~ data_in[14])) & (~ data_in[15])) & (~ data_in[16])) & (~ data_in[17])) & (~ data_in[18])) & (~ data_in[19])),
		nli1Ol = (((((((((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & (~ data_in[7])) & (~ data_in[10])) & (~ data_in[11])) & (~ data_in[12])) & (~ data_in[13])) & (~ data_in[14])) & (~ data_in[15])) & (~ data_in[16])) & (~ data_in[17])),
		nli1OO = (((((~ rpmadwidth_rx) & (~ rpma_doublewidth_rx)) & (~ rprbs_sel[0])) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])),
		nlii0O = (((((((((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]) & data_in[10]) & data_in[11]) & data_in[12]) & data_in[13]) & data_in[14]) & data_in[15]) & data_in[16]) & data_in[17]),
		nliiii = (((((((((((((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]) & data_in[8]) & data_in[9]) & data_in[10]) & data_in[11]) & data_in[12]) & data_in[13]) & data_in[14]) & data_in[15]) & data_in[16]) & data_in[17]) & data_in[18]) & data_in[19]),
		nliiiO = 1'b1,
		nliill = 1'b0,
		nliilO = ((((rpmadwidth_rx & rpma_doublewidth_rx) & rprbs_sel[0]) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])),
		nliiOi = (((((~ rpmadwidth_rx) & rpma_doublewidth_rx) & rprbs_sel[0]) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])),
		prbs_done = nlOO1i,
		prbs_err = (nlOllO | (nlOlOl | nlOlOi)),
		prbs_err_lt = nlOlll,
		verify_on = nlOlOO;
endmodule //arriagx_hssi_rx_prbs_ver
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 572 mux21 810 oper_add 13 oper_less_than 8 oper_mux 147 oper_selector 80 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rx_wordalign
	( 
	a1a2_k1k2_flag,
	a1a2_size,
	autobytealign_dis,
	bitloc_rev_en,
	bitslip,
	byte_rev_en,
	cg_syncpat,
	clk,
	comp_pat,
	comp_pat_porn,
	comp_pat_size,
	disable_rx_disp,
	dwidth,
	encdet_prbs,
	encdt,
	enumber,
	gnumber,
	ib_invalid_code,
	knumber,
	lpbk_en,
	max_rlv_sel,
	pmadwidth,
	polinv_en,
	prbs_en,
	pudi,
	pudr,
	r8b10b_dec_ibm_en,
	rbitloc_rev_en,
	rbyte_rev_en,
	rencdt_rising,
	resync_badcg_en,
	rforce_sig_det_pcs,
	rkchar,
	rlv,
	rlv_en,
	rlv_lt,
	rosbased,
	rosnumber,
	rpolinv_en,
	rst,
	scan_mode,
	signal_detect,
	signal_detect_rcvdclk,
	sudi,
	sudi_pre,
	sync_sm_dis,
	sync_status,
	testbus,
	wa_6g_en) /* synthesis synthesis_clearbox=1 */;
	output   [3:0]  a1a2_k1k2_flag;
	input   a1a2_size;
	input   autobytealign_dis;
	input   bitloc_rev_en;
	input   bitslip;
	input   byte_rev_en;
	output   [1:0]  cg_syncpat;
	input   clk;
	input   [39:0]  comp_pat;
	input   comp_pat_porn;
	input   [2:0]  comp_pat_size;
	input   disable_rx_disp;
	input   dwidth;
	input   encdet_prbs;
	input   encdt;
	input   [9:0]  enumber;
	input   [9:0]  gnumber;
	input   [1:0]  ib_invalid_code;
	input   [9:0]  knumber;
	input   lpbk_en;
	input   [5:0]  max_rlv_sel;
	input   [1:0]  pmadwidth;
	input   polinv_en;
	input   prbs_en;
	input   [19:0]  pudi;
	input   [19:0]  pudr;
	input   [1:0]  r8b10b_dec_ibm_en;
	input   rbitloc_rev_en;
	input   rbyte_rev_en;
	input   rencdt_rising;
	input   [1:0]  resync_badcg_en;
	input   rforce_sig_det_pcs;
	input   rkchar;
	output   rlv;
	input   rlv_en;
	output   rlv_lt;
	input   rosbased;
	input   [3:0]  rosnumber;
	input   rpolinv_en;
	input   rst;
	input   scan_mode;
	input   signal_detect;
	output   signal_detect_rcvdclk;
	output   [31:0]  sudi;
	output   [13:0]  sudi_pre;
	input   sync_sm_dis;
	output   sync_status;
	output   [9:0]  testbus;
	input   wa_6g_en;

	reg	n1ilO1l51;
	reg	n1ilO1l52;
	reg	n1ilO1O49;
	reg	n1ilO1O50;
	reg	n1iO00l41;
	reg	n1iO00l42;
	reg	n1iO01O43;
	reg	n1iO01O44;
	reg	n1iO0ii39;
	reg	n1iO0ii40;
	reg	n1iO0ll37;
	reg	n1iO0ll38;
	reg	n1iO0Oi35;
	reg	n1iO0Oi36;
	reg	n1iO0OO33;
	reg	n1iO0OO34;
	reg	n1iO1lO47;
	reg	n1iO1lO48;
	reg	n1iO1Ol45;
	reg	n1iO1Ol46;
	reg	n1iOi0O29;
	reg	n1iOi0O30;
	reg	n1iOi1l31;
	reg	n1iOi1l32;
	reg	n1iOiil27;
	reg	n1iOiil28;
	reg	n1iOiOl25;
	reg	n1iOiOl26;
	reg	n1iOiOO23;
	reg	n1iOiOO24;
	reg	n1iOl1i21;
	reg	n1iOl1i22;
	reg	n1iOl1l19;
	reg	n1iOl1l20;
	reg	n1iOl1O17;
	reg	n1iOl1O18;
	reg	n1iOlli15;
	reg	n1iOlli16;
	reg	n1iOlOi13;
	reg	n1iOlOi14;
	reg	n1iOO1l11;
	reg	n1iOO1l12;
	reg	n1iOO1O10;
	reg	n1iOO1O9;
	reg	n1iOOii7;
	reg	n1iOOii8;
	reg	n1iOOiO5;
	reg	n1iOOiO6;
	reg	n1iOOll3;
	reg	n1iOOll4;
	reg	n1l110i1;
	reg	n1l110i2;
	reg	nii0O;
	reg	niili;
	reg	niiiO_clk_prev;
	wire	wire_niiiO_CLRN;
	wire	wire_niiiO_PRN;
	reg	n0000i;
	reg	n0000l;
	reg	n0001l;
	reg	n0001O;
	reg	n000ll;
	reg	n000lO;
	reg	n000Oi;
	reg	n000Ol;
	reg	n0011l;
	reg	n00lOi;
	reg	n00lOl;
	reg	n00lOO;
	reg	n00O0i;
	reg	n00O0l;
	reg	n00O0O;
	reg	n00O1i;
	reg	n00O1l;
	reg	n00O1O;
	reg	n00Oii;
	reg	n00Oil;
	reg	n00OiO;
	reg	n00Oli;
	reg	n00Oll;
	reg	n00OlO;
	reg	n0100O;
	reg	n010ili;
	reg	n010ill;
	reg	n010ilO;
	reg	n010iOi;
	reg	n010iOl;
	reg	n010iOO;
	reg	n010l1l;
	reg	n010lii;
	reg	n010lil;
	reg	n010liO;
	reg	n010lli;
	reg	n010O1i;
	reg	n010O1l;
	reg	n0110l;
	reg	n0110O;
	reg	n011ii;
	reg	n011il;
	reg	n011ilO;
	reg	n011iO;
	reg	n011iOi;
	reg	n011iOl;
	reg	n011iOO;
	reg	n011l0i;
	reg	n011l0l;
	reg	n011l0O;
	reg	n011l1i;
	reg	n011l1l;
	reg	n011l1O;
	reg	n011li;
	reg	n011ll;
	reg	n011lO;
	reg	n011O1l;
	reg	n01iOOi;
	reg	n01iOOl;
	reg	n01iOOO;
	reg	n01l10i;
	reg	n01l10l;
	reg	n01l10O;
	reg	n01l11i;
	reg	n01l11l;
	reg	n01l11O;
	reg	n01l1ii;
	reg	n01l1il;
	reg	n01l1iO;
	reg	n01l1li;
	reg	n01l1ll;
	reg	n01l1lO;
	reg	n01l1Oi;
	reg	n01l1Ol;
	reg	n01l1OO;
	reg	n01li0i;
	reg	n01li0l;
	reg	n01li0O;
	reg	n01liii;
	reg	n01liil;
	reg	n01liiO;
	reg	n01lili;
	reg	n01lill;
	reg	n01lilO;
	reg	n01liOi;
	reg	n01liOl;
	reg	n01liOO;
	reg	n01ll0i;
	reg	n01ll1i;
	reg	n01ll1l;
	reg	n01ll1O;
	reg	n01Oli;
	reg	n01Oll;
	reg	n01OlO;
	reg	n01OOi;
	reg	n01OOl;
	reg	n01OOO;
	reg	n0i00i;
	reg	n0i00l;
	reg	n0i00O;
	reg	n0i01i;
	reg	n0i01l;
	reg	n0i01O;
	reg	n0i0ii;
	reg	n0i0il;
	reg	n0i0iO;
	reg	n0i0li;
	reg	n0i1Oi;
	reg	n0i1Ol;
	reg	n0i1OO;
	reg	nii0l;
	reg	niO0il;
	reg	niO0iO;
	reg	niO0li;
	reg	niO0ll;
	reg	niO0lO;
	reg	niO0Ol;
	reg	niO0OO;
	reg	niO11i;
	reg	niO11l;
	reg	niO11O;
	reg	niO1il;
	reg	niOi0i;
	reg	niOi0l;
	reg	niOi0O;
	reg	niOi1i;
	reg	niOi1l;
	reg	niOi1O;
	reg	niOiii;
	reg	niOiil;
	reg	niOiiO;
	reg	niOili;
	reg	niOill;
	reg	niOilO;
	reg	niOiOi;
	reg	niOiOl;
	reg	niOiOO;
	reg	niOl0i;
	reg	niOl0l;
	reg	niOl0O;
	reg	niOl1i;
	reg	niOl1l;
	reg	niOl1O;
	reg	niOlii;
	reg	niOlil;
	reg	niOliO;
	reg	niOlli;
	reg	niOlll;
	reg	niOllO;
	reg	niOlOi;
	reg	niOlOl;
	reg	niOlOO;
	reg	niOO0i;
	reg	niOO0l;
	reg	niOO1i;
	reg	niOO1l;
	reg	niOO1O;
	reg	nl0000l;
	reg	nl0000O;
	reg	nl000ii;
	reg	nl000il;
	reg	nl000iO;
	reg	nl000li;
	reg	nl000ll;
	reg	nl000lO;
	reg	nl000Oi;
	reg	nl000Ol;
	reg	nl000OO;
	reg	nl00i0i;
	reg	nl00i0l;
	reg	nl00i0O;
	reg	nl00i1i;
	reg	nl00i1l;
	reg	nl00i1O;
	reg	nl00iii;
	reg	nl00iil;
	reg	nl00iiO;
	reg	nl00il;
	reg	nl00ili;
	reg	nl00ill;
	reg	nl00ilO;
	reg	nl00iOi;
	reg	nl00iOl;
	reg	nl00iOO;
	reg	nl00l0i;
	reg	nl00l0l;
	reg	nl00l0O;
	reg	nl00l1i;
	reg	nl00l1l;
	reg	nl00l1O;
	reg	nl00li;
	reg	nl00lii;
	reg	nl00lil;
	reg	nl00liO;
	reg	nl00ll;
	reg	nl00lli;
	reg	nl00lll;
	reg	nl00llO;
	reg	nl00lO;
	reg	nl00lOi;
	reg	nl00lOl;
	reg	nl00lOO;
	reg	nl00O0i;
	reg	nl00O0l;
	reg	nl00O0O;
	reg	nl00O1i;
	reg	nl00O1l;
	reg	nl00O1O;
	reg	nl00Oi;
	reg	nl00Oii;
	reg	nl00Oil;
	reg	nl00OiO;
	reg	nl00Ol;
	reg	nl0100i;
	reg	nl010i;
	reg	nl011l;
	reg	nl011O;
	reg	nl01ll;
	reg	nl01lOO;
	reg	nl0i00i;
	reg	nl0i00l;
	reg	nl0i00O;
	reg	nl0i01i;
	reg	nl0i01l;
	reg	nl0i01O;
	reg	nl0i0i;
	reg	nl0i0ii;
	reg	nl0i0il;
	reg	nl0i0iO;
	reg	nl0i0l;
	reg	nl0i0li;
	reg	nl0i0ll;
	reg	nl0i0lO;
	reg	nl0i0Oi;
	reg	nl0i0Ol;
	reg	nl0i0OO;
	reg	nl0i1li;
	reg	nl0i1ll;
	reg	nl0i1lO;
	reg	nl0i1Oi;
	reg	nl0i1Ol;
	reg	nl0i1OO;
	reg	nl0ii0i;
	reg	nl0ii0l;
	reg	nl0ii0O;
	reg	nl0ii1i;
	reg	nl0ii1l;
	reg	nl0ii1O;
	reg	nl0iiii;
	reg	nl0iiil;
	reg	nl0iiiO;
	reg	nl0iili;
	reg	nl0iill;
	reg	nl0iilO;
	reg	nl0iiOi;
	reg	nl0iiOl;
	reg	nl0iiOO;
	reg	nl0il0i;
	reg	nl0il0l;
	reg	nl0il1i;
	reg	nl0il1l;
	reg	nl0il1O;
	reg	nl0ill;
	reg	nl1liO;
	reg	nl1lli;
	reg	nl1llO;
	reg	nl1lOi;
	reg	nl1lOl;
	reg	nl1lOO;
	reg	nl1O0i;
	reg	nl1O0l;
	reg	nl1O0O;
	reg	nl1O1i;
	reg	nl1O1l;
	reg	nl1O1O;
	reg	nll0lO;
	reg	nll0Oi;
	reg	nll0Ol;
	reg	nll0OO;
	reg	nlli0i;
	reg	nlli0l;
	reg	nlli1i;
	reg	nlli1l;
	reg	nlli1O;
	reg	nlliiO;
	reg	nllili;
	reg	nllill;
	reg	nllilO;
	reg	nlliOi;
	reg	nlliOl;
	reg	nlliOll;
	reg	nlliOlO;
	reg	nlliOO;
	reg	nlliOOi;
	reg	nlliOOl;
	reg	nlliOOO;
	reg	nlll00i;
	reg	nlll00l;
	reg	nlll00O;
	reg	nlll01i;
	reg	nlll01l;
	reg	nlll01O;
	reg	nlll0i;
	reg	nlll0ii;
	reg	nlll0il;
	reg	nlll0iO;
	reg	nlll0l;
	reg	nlll0li;
	reg	nlll0ll;
	reg	nlll0lO;
	reg	nlll0O;
	reg	nlll0Oi;
	reg	nlll0Ol;
	reg	nlll0OO;
	reg	nlll10i;
	reg	nlll10l;
	reg	nlll10O;
	reg	nlll11i;
	reg	nlll11l;
	reg	nlll11O;
	reg	nlll1i;
	reg	nlll1ii;
	reg	nlll1il;
	reg	nlll1iO;
	reg	nlll1l;
	reg	nlll1li;
	reg	nlll1ll;
	reg	nlll1lO;
	reg	nlll1O;
	reg	nlll1Oi;
	reg	nlll1Ol;
	reg	nlll1OO;
	reg	nllli0i;
	reg	nllli0l;
	reg	nllli0O;
	reg	nllli1i;
	reg	nllli1l;
	reg	nllli1O;
	reg	nlllii;
	reg	nllliii;
	reg	nllliil;
	reg	nllliiO;
	reg	nlllil;
	reg	nlllili;
	reg	nlllill;
	reg	nlllilO;
	reg	nllliO;
	reg	nllliOi;
	reg	nllliOl;
	reg	nllliOO;
	reg	nllll0i;
	reg	nllll0l;
	reg	nllll0O;
	reg	nllll1i;
	reg	nllll1l;
	reg	nllll1O;
	reg	nlllli;
	reg	nllllii;
	reg	nllllil;
	reg	nlllliO;
	reg	nlllll;
	reg	nllllli;
	reg	nllllll;
	reg	nlllllO;
	reg	nllllO;
	reg	nllllOi;
	reg	nllllOl;
	reg	nllllOO;
	reg	nlllO0i;
	reg	nlllO0l;
	reg	nlllO0O;
	reg	nlllO1i;
	reg	nlllO1l;
	reg	nlllO1O;
	reg	nlllOi;
	reg	nlllOii;
	reg	nlllOil;
	reg	nlllOiO;
	reg	nlllOl;
	reg	nlllOli;
	reg	nlllOll;
	reg	nlllOlO;
	reg	nlllOO;
	reg	nlllOOi;
	reg	nlllOOl;
	reg	nlllOOO;
	reg	nllO00i;
	reg	nllO00l;
	reg	nllO01i;
	reg	nllO01l;
	reg	nllO01O;
	reg	nllO10i;
	reg	nllO10l;
	reg	nllO10O;
	reg	nllO11i;
	reg	nllO11l;
	reg	nllO11O;
	reg	nllO1i;
	reg	nllO1ii;
	reg	nllO1il;
	reg	nllO1iO;
	reg	nllO1l;
	reg	nllO1li;
	reg	nllO1ll;
	reg	nllO1lO;
	reg	nllO1Oi;
	reg	nllO1Ol;
	reg	nllO1OO;
	reg	nlO0OO;
	reg	nlO1i1i;
	reg	nlOi1i;
	reg	nlOiO0i;
	reg	nlOiO0l;
	reg	nlOiO1i;
	reg	nlOiO1l;
	reg	nlOiO1O;
	reg	nlOiOii;
	reg	nlOiOil;
	reg	nlOiOiO;
	reg	nlOiOli;
	reg	nlOiOll;
	reg	nlOiOlO;
	reg	nlOiOOi;
	reg	nlOiOOl;
	reg	nlOiOOO;
	reg	nlOl00i;
	reg	nlOl00l;
	reg	nlOl00O;
	reg	nlOl01i;
	reg	nlOl01l;
	reg	nlOl01O;
	reg	nlOl0ii;
	reg	nlOl0il;
	reg	nlOl0iO;
	reg	nlOl0li;
	reg	nlOl0ll;
	reg	nlOl0lO;
	reg	nlOl10i;
	reg	nlOl10l;
	reg	nlOl10O;
	reg	nlOl11i;
	reg	nlOl11l;
	reg	nlOl11O;
	reg	nlOl1ii;
	reg	nlOl1il;
	reg	nlOl1iO;
	reg	nlOl1li;
	reg	nlOl1ll;
	reg	nlOl1lO;
	reg	nlOl1Oi;
	reg	nlOl1Ol;
	reg	nlOl1OO;
	reg	nlOli1i;
	reg	nlOli1l;
	reg	nlOli1O;
	reg	nlOO00i;
	reg	nlOO00l;
	reg	nlOO00O;
	reg	nlOO01i;
	reg	nlOO01l;
	reg	nlOO01O;
	reg	nlOO0ii;
	reg	nlOO0il;
	reg	nlOO0iO;
	reg	nlOO0li;
	reg	nlOO0ll;
	reg	nlOO1li;
	reg	nlOO1ll;
	reg	nlOO1lO;
	reg	nlOO1Oi;
	reg	nlOO1Ol;
	reg	nlOO1OO;
	reg	nlOOiOi;
	reg	nlOOiOl;
	reg	nlOOiOO;
	reg	nlOOl0i;
	reg	nlOOl1i;
	reg	nlOOl1l;
	reg	nlOOl1O;
	reg	nO;
	wire	wire_nl_CLRN;
	reg	nl010l;
	reg	nl01ii;
	reg	nl01il;
	reg	nl01li;
	reg	nl0i0O;
	reg	nl0iii;
	reg	nl0iil;
	reg	nl0ili;
	reg	nl0iiO_clk_prev;
	wire	wire_nl0iiO_CLRN;
	wire	wire_nl0iiO_PRN;
	reg	nlli0O;
	reg	nlliii;
	reg	nlliil;
	reg	nllO0l;
	reg	nllO1O;
	reg	nllO0i_clk_prev;
	wire	wire_nllO0i_PRN;
	wire	wire_nllO0i_ENA;
	reg	n0011i;
	reg	n010l1i;
	reg	niO0Oi;
	reg	nl00Oli;
	reg	nl00Oll;
	reg	nl00OlO;
	reg	nl00OO;
	reg	nl00OOi;
	reg	nl00OOl;
	reg	nl00OOO;
	reg	nl0i10i;
	reg	nl0i10l;
	reg	nl0i10O;
	reg	nl0i11i;
	reg	nl0i11l;
	reg	nl0i11O;
	reg	nl0i1i;
	reg	nl0i1ii;
	reg	nl0i1il;
	reg	nl0i1iO;
	reg	nl0i1l;
	reg	nl0i1O;
	reg	nlliOli;
	reg	nlOi1O;
	reg	nlOiO0O;
	wire	wire_n0000O_dataout;
	wire	wire_n000ii_dataout;
	wire	wire_n000il_dataout;
	wire	wire_n000iO_dataout;
	wire	wire_n0010i_dataout;
	wire	wire_n0010l_dataout;
	wire	wire_n0010O_dataout;
	wire	wire_n0011O_dataout;
	wire	wire_n001ii_dataout;
	wire	wire_n001il_dataout;
	wire	wire_n001iO_dataout;
	wire	wire_n001li_dataout;
	wire	wire_n00i_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00llO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n00OOi_dataout;
	wire	wire_n00OOl_dataout;
	wire	wire_n00OOO_dataout;
	wire	wire_n01000i_dataout;
	wire	wire_n01000l_dataout;
	wire	wire_n01000O_dataout;
	wire	wire_n01001i_dataout;
	wire	wire_n01001l_dataout;
	wire	wire_n01001O_dataout;
	wire	wire_n0100i_dataout;
	wire	wire_n0100ii_dataout;
	wire	wire_n0100l_dataout;
	wire	wire_n0100li_dataout;
	wire	wire_n0100ll_dataout;
	wire	wire_n0100lO_dataout;
	wire	wire_n0100Oi_dataout;
	wire	wire_n0100Ol_dataout;
	wire	wire_n01010O_dataout;
	wire	wire_n0101i_dataout;
	wire	wire_n0101ll_dataout;
	wire	wire_n0101lO_dataout;
	wire	wire_n0101Oi_dataout;
	wire	wire_n0101Ol_dataout;
	wire	wire_n0101OO_dataout;
	wire	wire_n010i0i_dataout;
	wire	wire_n010i0l_dataout;
	wire	wire_n010i1i_dataout;
	wire	wire_n010i1l_dataout;
	wire	wire_n010i1O_dataout;
	wire	wire_n010ii_dataout;
	wire	wire_n010iil_dataout;
	wire	wire_n010iiO_dataout;
	wire	wire_n010il_dataout;
	wire	wire_n010lll_dataout;
	wire	wire_n010llO_dataout;
	wire	wire_n010lOi_dataout;
	wire	wire_n010lOl_dataout;
	wire	wire_n011i0i_dataout;
	wire	wire_n011lii_dataout;
	wire	wire_n011lil_dataout;
	wire	wire_n011liO_dataout;
	wire	wire_n011lli_dataout;
	wire	wire_n011lll_dataout;
	wire	wire_n011lOl_dataout;
	wire	wire_n011lOO_dataout;
	wire	wire_n011O0i_dataout;
	wire	wire_n011O1i_dataout;
	wire	wire_n011O1O_dataout;
	wire	wire_n011Oi_dataout;
	wire	wire_n011Ol_dataout;
	wire	wire_n011OO_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01iil_dataout;
	wire	wire_n01il0O_dataout;
	wire	wire_n01ilii_dataout;
	wire	wire_n01ilil_dataout;
	wire	wire_n01iliO_dataout;
	wire	wire_n01illi_dataout;
	wire	wire_n01illl_dataout;
	wire	wire_n01illO_dataout;
	wire	wire_n01ilOi_dataout;
	wire	wire_n01ilOl_dataout;
	wire	wire_n01ilOO_dataout;
	wire	wire_n01iO0i_dataout;
	wire	wire_n01iO0l_dataout;
	wire	wire_n01iO1i_dataout;
	wire	wire_n01iO1l_dataout;
	wire	wire_n01iO1O_dataout;
	wire	wire_n01iOi_dataout;
	wire	wire_n01iOii_dataout;
	wire	wire_n01iOil_dataout;
	wire	wire_n01iOiO_dataout;
	wire	wire_n01iOl_dataout;
	wire	wire_n01iOli_dataout;
	wire	wire_n01iOll_dataout;
	wire	wire_n01iOlO_dataout;
	wire	wire_n01iOO_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01l00i_dataout;
	wire	wire_n01l00l_dataout;
	wire	wire_n01l00O_dataout;
	wire	wire_n01l01i_dataout;
	wire	wire_n01l01l_dataout;
	wire	wire_n01l01O_dataout;
	wire	wire_n01l0i_dataout;
	wire	wire_n01l0ii_dataout;
	wire	wire_n01l0il_dataout;
	wire	wire_n01l0iO_dataout;
	wire	wire_n01l0l_dataout;
	wire	wire_n01l0li_dataout;
	wire	wire_n01l0ll_dataout;
	wire	wire_n01l0lO_dataout;
	wire	wire_n01l0O_dataout;
	wire	wire_n01l0Oi_dataout;
	wire	wire_n01l0Ol_dataout;
	wire	wire_n01l0OO_dataout;
	wire	wire_n01l1i_dataout;
	wire	wire_n01l1l_dataout;
	wire	wire_n01l1O_dataout;
	wire	wire_n01li1i_dataout;
	wire	wire_n01li1l_dataout;
	wire	wire_n01li1O_dataout;
	wire	wire_n01lii_dataout;
	wire	wire_n01lil_dataout;
	wire	wire_n01ll0l_dataout;
	wire	wire_n01ll0O_dataout;
	wire	wire_n01llii_dataout;
	wire	wire_n01llil_dataout;
	wire	wire_n01lliO_dataout;
	wire	wire_n01lll_dataout;
	wire	wire_n01llli_dataout;
	wire	wire_n01llll_dataout;
	wire	wire_n01lllO_dataout;
	wire	wire_n01llO_dataout;
	wire	wire_n01llOi_dataout;
	wire	wire_n01llOl_dataout;
	wire	wire_n01llOO_dataout;
	wire	wire_n01lO0i_dataout;
	wire	wire_n01lO0l_dataout;
	wire	wire_n01lO0O_dataout;
	wire	wire_n01lO1i_dataout;
	wire	wire_n01lO1l_dataout;
	wire	wire_n01lO1O_dataout;
	wire	wire_n01lOi_dataout;
	wire	wire_n01lOl_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n01O0i_dataout;
	wire	wire_n01O0l_dataout;
	wire	wire_n01O1i_dataout;
	wire	wire_n01O1l_dataout;
	wire	wire_n01O1O_dataout;
	wire	wire_n01Oil_dataout;
	wire	wire_n01OiO_dataout;
	wire	wire_n0i_dataout;
	wire	wire_n0i0ll_dataout;
	wire	wire_n0i0lO_dataout;
	wire	wire_n0i0Oi_dataout;
	wire	wire_n0i0Ol_dataout;
	wire	wire_n0i0OO_dataout;
	wire	wire_n0i10i_dataout;
	wire	wire_n0i10l_dataout;
	wire	wire_n0i10O_dataout;
	wire	wire_n0i11i_dataout;
	wire	wire_n0i11l_dataout;
	wire	wire_n0i11O_dataout;
	wire	wire_n0i1ii_dataout;
	wire	wire_n0i1il_dataout;
	wire	wire_n0i1iO_dataout;
	wire	wire_n0i1li_dataout;
	wire	wire_n0i1ll_dataout;
	wire	wire_n0i1lO_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0ii0i_dataout;
	wire	wire_n0ii0l_dataout;
	wire	wire_n0ii0O_dataout;
	wire	wire_n0ii1i_dataout;
	wire	wire_n0ii1l_dataout;
	wire	wire_n0ii1O_dataout;
	wire	wire_n0iiii_dataout;
	wire	wire_n0iiil_dataout;
	wire	wire_n0iiiO_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0lO_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n0Oi_dataout;
	wire	wire_n0Ol_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11i0l_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1i1li_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1l1O0l_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1liili_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1O010l_dataout;
	wire	wire_n1O100i_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Oilli_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_n1OOOi_dataout;
	wire	wire_ni_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_ni1O_dataout;
	wire	wire_nii_dataout;
	wire	wire_niii_dataout;
	wire	wire_niiil_dataout;
	wire	wire_niil_dataout;
	wire	wire_niill_dataout;
	wire	wire_niilO_dataout;
	wire	wire_niiO_dataout;
	wire	wire_niiOi_dataout;
	wire	wire_niiOl_dataout;
	wire	wire_niiOO_dataout;
	wire	wire_nil_dataout;
	wire	wire_nil0i_dataout;
	wire	wire_nil0l_dataout;
	wire	wire_nil0O_dataout;
	wire	wire_nil1i_dataout;
	wire	wire_nil1l_dataout;
	wire	wire_nil1O_dataout;
	wire	wire_nili_dataout;
	wire	wire_nilii_dataout;
	wire	wire_nilil_dataout;
	wire	wire_niliO_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilli_dataout;
	wire	wire_nilll_dataout;
	wire	wire_nillO_dataout;
	wire	wire_nilO_dataout;
	wire	wire_nilOi_dataout;
	wire	wire_nilOl_dataout;
	wire	wire_nilOO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niO00l_dataout;
	wire	wire_niO0i_dataout;
	wire	wire_niO0l_dataout;
	wire	wire_niO0O_dataout;
	wire	wire_niO1i_dataout;
	wire	wire_niO1l_dataout;
	wire	wire_niO1O_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOii_dataout;
	wire	wire_niOil_dataout;
	wire	wire_niOiO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOli_dataout;
	wire	wire_niOll_dataout;
	wire	wire_niOlO_dataout;
	wire	wire_niOO_dataout;
	wire	wire_niOOi_dataout;
	wire	wire_niOOii_dataout;
	wire	wire_niOOil_dataout;
	wire	wire_niOOl_dataout;
	wire	wire_niOOO_dataout;
	wire	wire_nl0000i_dataout;
	wire	wire_nl0001i_dataout;
	wire	wire_nl0001l_dataout;
	wire	wire_nl0001O_dataout;
	wire	wire_nl000i_dataout;
	wire	wire_nl0010i_dataout;
	wire	wire_nl0010l_dataout;
	wire	wire_nl0010O_dataout;
	wire	wire_nl0011l_dataout;
	wire	wire_nl0011O_dataout;
	wire	wire_nl001i_dataout;
	wire	wire_nl001ii_dataout;
	wire	wire_nl001il_dataout;
	wire	wire_nl001iO_dataout;
	wire	wire_nl001l_dataout;
	wire	wire_nl001li_dataout;
	wire	wire_nl001ll_dataout;
	wire	wire_nl001lO_dataout;
	wire	wire_nl001O_dataout;
	wire	wire_nl001Oi_dataout;
	wire	wire_nl001Ol_dataout;
	wire	wire_nl001OO_dataout;
	wire	wire_nl00i_dataout;
	wire	wire_nl00l_dataout;
	wire	wire_nl00O_dataout;
	wire	wire_nl01i_dataout;
	wire	wire_nl01l_dataout;
	wire	wire_nl01lO_dataout;
	wire	wire_nl01O_dataout;
	wire	wire_nl01Oi_dataout;
	wire	wire_nl01Ol_dataout;
	wire	wire_nl01OO_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0ii_dataout;
	wire	wire_nl0il_dataout;
	wire	wire_nl0il0O_dataout;
	wire	wire_nl0ilii_dataout;
	wire	wire_nl0ilil_dataout;
	wire	wire_nl0iliO_dataout;
	wire	wire_nl0illi_dataout;
	wire	wire_nl0illl_dataout;
	wire	wire_nl0illO_dataout;
	wire	wire_nl0ilOi_dataout;
	wire	wire_nl0ilOl_dataout;
	wire	wire_nl0ilOO_dataout;
	wire	wire_nl0iO_dataout;
	wire	wire_nl0iO0i_dataout;
	wire	wire_nl0iO0l_dataout;
	wire	wire_nl0iO0O_dataout;
	wire	wire_nl0iO1i_dataout;
	wire	wire_nl0iO1l_dataout;
	wire	wire_nl0iO1O_dataout;
	wire	wire_nl0iOii_dataout;
	wire	wire_nl0iOil_dataout;
	wire	wire_nl0iOiO_dataout;
	wire	wire_nl0iOli_dataout;
	wire	wire_nl0iOll_dataout;
	wire	wire_nl0iOlO_dataout;
	wire	wire_nl0iOOi_dataout;
	wire	wire_nl0iOOl_dataout;
	wire	wire_nl0iOOO_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0l00i_dataout;
	wire	wire_nl0l00l_dataout;
	wire	wire_nl0l00O_dataout;
	wire	wire_nl0l01i_dataout;
	wire	wire_nl0l01l_dataout;
	wire	wire_nl0l01O_dataout;
	wire	wire_nl0l0ii_dataout;
	wire	wire_nl0l0il_dataout;
	wire	wire_nl0l0iO_dataout;
	wire	wire_nl0l0li_dataout;
	wire	wire_nl0l0ll_dataout;
	wire	wire_nl0l0lO_dataout;
	wire	wire_nl0l0Oi_dataout;
	wire	wire_nl0l0Ol_dataout;
	wire	wire_nl0l0OO_dataout;
	wire	wire_nl0l10i_dataout;
	wire	wire_nl0l10l_dataout;
	wire	wire_nl0l10O_dataout;
	wire	wire_nl0l11i_dataout;
	wire	wire_nl0l11l_dataout;
	wire	wire_nl0l11O_dataout;
	wire	wire_nl0l1ii_dataout;
	wire	wire_nl0l1il_dataout;
	wire	wire_nl0l1iO_dataout;
	wire	wire_nl0l1li_dataout;
	wire	wire_nl0l1ll_dataout;
	wire	wire_nl0l1lO_dataout;
	wire	wire_nl0l1Oi_dataout;
	wire	wire_nl0l1Ol_dataout;
	wire	wire_nl0l1OO_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0li0i_dataout;
	wire	wire_nl0li0l_dataout;
	wire	wire_nl0li1i_dataout;
	wire	wire_nl0li1l_dataout;
	wire	wire_nl0li1O_dataout;
	wire	wire_nl0ll_dataout;
	wire	wire_nl0llO_dataout;
	wire	wire_nl0lO_dataout;
	wire	wire_nl0lOi_dataout;
	wire	wire_nl0lOl_dataout;
	wire	wire_nl0lOO_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl0O00O_dataout;
	wire	wire_nl0O0ii_dataout;
	wire	wire_nl0O0il_dataout;
	wire	wire_nl0O0iO_dataout;
	wire	wire_nl0O0l_dataout;
	wire	wire_nl0O0li_dataout;
	wire	wire_nl0O0ll_dataout;
	wire	wire_nl0O0lO_dataout;
	wire	wire_nl0O0Oi_dataout;
	wire	wire_nl0O0Ol_dataout;
	wire	wire_nl0O0OO_dataout;
	wire	wire_nl0O10i_dataout;
	wire	wire_nl0O10l_dataout;
	wire	wire_nl0O10O_dataout;
	wire	wire_nl0O11i_dataout;
	wire	wire_nl0O11l_dataout;
	wire	wire_nl0O11O_dataout;
	wire	wire_nl0O1i_dataout;
	wire	wire_nl0O1ii_dataout;
	wire	wire_nl0O1il_dataout;
	wire	wire_nl0O1iO_dataout;
	wire	wire_nl0O1li_dataout;
	wire	wire_nl0O1ll_dataout;
	wire	wire_nl0O1lO_dataout;
	wire	wire_nl0O1O_dataout;
	wire	wire_nl0O1Oi_dataout;
	wire	wire_nl0O1Ol_dataout;
	wire	wire_nl0O1OO_dataout;
	wire	wire_nl0Oi_dataout;
	wire	wire_nl0Oi0i_dataout;
	wire	wire_nl0Oi0l_dataout;
	wire	wire_nl0Oi0O_dataout;
	wire	wire_nl0Oi1O_dataout;
	wire	wire_nl0Oiii_dataout;
	wire	wire_nl0Oiil_dataout;
	wire	wire_nl0OiiO_dataout;
	wire	wire_nl0Oil_dataout;
	wire	wire_nl0Oili_dataout;
	wire	wire_nl0Oill_dataout;
	wire	wire_nl0OilO_dataout;
	wire	wire_nl0OiOl_dataout;
	wire	wire_nl0OiOO_dataout;
	wire	wire_nl0Ol_dataout;
	wire	wire_nl0Ol0i_dataout;
	wire	wire_nl0Ol0l_dataout;
	wire	wire_nl0Ol0O_dataout;
	wire	wire_nl0Ol1i_dataout;
	wire	wire_nl0Ol1l_dataout;
	wire	wire_nl0Ol1O_dataout;
	wire	wire_nl0Olii_dataout;
	wire	wire_nl0Olil_dataout;
	wire	wire_nl0Oll_dataout;
	wire	wire_nl0Olli_dataout;
	wire	wire_nl0Olll_dataout;
	wire	wire_nl0OllO_dataout;
	wire	wire_nl0OlOi_dataout;
	wire	wire_nl0OlOl_dataout;
	wire	wire_nl0OlOO_dataout;
	wire	wire_nl0OO_dataout;
	wire	wire_nl0OO0i_dataout;
	wire	wire_nl0OO1i_dataout;
	wire	wire_nl0OO1l_dataout;
	wire	wire_nl0OO1O_dataout;
	wire	wire_nl0OOiO_dataout;
	wire	wire_nl0OOl_dataout;
	wire	wire_nl0OOli_dataout;
	wire	wire_nl0OOOl_dataout;
	wire	wire_nl0OOOO_dataout;
	wire	wire_nl100i_dataout;
	wire	wire_nl100l_dataout;
	wire	wire_nl100O_dataout;
	wire	wire_nl101i_dataout;
	wire	wire_nl101l_dataout;
	wire	wire_nl101O_dataout;
	wire	wire_nl10i_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl10ll_dataout;
	wire	wire_nl10lO_dataout;
	wire	wire_nl10O_dataout;
	wire	wire_nl10Oi_dataout;
	wire	wire_nl10Ol_dataout;
	wire	wire_nl10OO_dataout;
	wire	wire_nl110i_dataout;
	wire	wire_nl110l_dataout;
	wire	wire_nl110O_dataout;
	wire	wire_nl111l_dataout;
	wire	wire_nl111O_dataout;
	wire	wire_nl11i_dataout;
	wire	wire_nl11ii_dataout;
	wire	wire_nl11il_dataout;
	wire	wire_nl11iO_dataout;
	wire	wire_nl11l_dataout;
	wire	wire_nl11li_dataout;
	wire	wire_nl11ll_dataout;
	wire	wire_nl11lO_dataout;
	wire	wire_nl11O_dataout;
	wire	wire_nl11Oi_dataout;
	wire	wire_nl11Ol_dataout;
	wire	wire_nl11OO_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1i1i_dataout;
	wire	wire_nl1i1l_dataout;
	wire	wire_nl1i1O_dataout;
	wire	wire_nl1ii_dataout;
	wire	wire_nl1il_dataout;
	wire	wire_nl1iO_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1l0O_dataout;
	wire	wire_nl1li_dataout;
	wire	wire_nl1lii_dataout;
	wire	wire_nl1ll_dataout;
	wire	wire_nl1lO_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nl1Oi_dataout;
	wire	wire_nl1Ol_dataout;
	wire	wire_nl1OO_dataout;
	wire	wire_nli_dataout;
	wire	wire_nli00i_dataout;
	wire	wire_nli00l_dataout;
	wire	wire_nli00O_dataout;
	wire	wire_nli01i_dataout;
	wire	wire_nli01l_dataout;
	wire	wire_nli01O_dataout;
	wire	wire_nli0i_dataout;
	wire	wire_nli0ii_dataout;
	wire	wire_nli0il_dataout;
	wire	wire_nli0iO_dataout;
	wire	wire_nli0l_dataout;
	wire	wire_nli0li_dataout;
	wire	wire_nli0ll_dataout;
	wire	wire_nli0lO_dataout;
	wire	wire_nli0O_dataout;
	wire	wire_nli0Oi_dataout;
	wire	wire_nli0Ol_dataout;
	wire	wire_nli0OO_dataout;
	wire	wire_nli10l_dataout;
	wire	wire_nli110i_dataout;
	wire	wire_nli110O_dataout;
	wire	wire_nli111i_dataout;
	wire	wire_nli111l_dataout;
	wire	wire_nli111O_dataout;
	wire	wire_nli11iO_dataout;
	wire	wire_nli11l_dataout;
	wire	wire_nli11li_dataout;
	wire	wire_nli11ll_dataout;
	wire	wire_nli11Oi_dataout;
	wire	wire_nli11Ol_dataout;
	wire	wire_nli1i_dataout;
	wire	wire_nli1il_dataout;
	wire	wire_nli1l_dataout;
	wire	wire_nli1ll_dataout;
	wire	wire_nli1O_dataout;
	wire	wire_nli1Ol_dataout;
	wire	wire_nli1OO_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlii0i_dataout;
	wire	wire_nlii0l_dataout;
	wire	wire_nlii0O_dataout;
	wire	wire_nlii1i_dataout;
	wire	wire_nlii1l_dataout;
	wire	wire_nlii1O_dataout;
	wire	wire_nliii_dataout;
	wire	wire_nliiii_dataout;
	wire	wire_nliiil_dataout;
	wire	wire_nliiiO_dataout;
	wire	wire_nliil_dataout;
	wire	wire_nliili_dataout;
	wire	wire_nliill_dataout;
	wire	wire_nliilO_dataout;
	wire	wire_nliiO_dataout;
	wire	wire_nliiOi_dataout;
	wire	wire_nliiOl_dataout;
	wire	wire_nliiOO_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nlil0i_dataout;
	wire	wire_nlil0l_dataout;
	wire	wire_nlil0O_dataout;
	wire	wire_nlil1i_dataout;
	wire	wire_nlil1l_dataout;
	wire	wire_nlil1O_dataout;
	wire	wire_nlili_dataout;
	wire	wire_nlilii_dataout;
	wire	wire_nlilil_dataout;
	wire	wire_nliliO_dataout;
	wire	wire_nlill_dataout;
	wire	wire_nlilli_dataout;
	wire	wire_nlilll_dataout;
	wire	wire_nlillO_dataout;
	wire	wire_nlilO_dataout;
	wire	wire_nlilOi_dataout;
	wire	wire_nlilOl_dataout;
	wire	wire_nlilOO_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nliO0i_dataout;
	wire	wire_nliO0l_dataout;
	wire	wire_nliO0O_dataout;
	wire	wire_nliO1i_dataout;
	wire	wire_nliO1l_dataout;
	wire	wire_nliO1O_dataout;
	wire	wire_nliOi_dataout;
	wire	wire_nliOii_dataout;
	wire	wire_nliOil_dataout;
	wire	wire_nliOiO_dataout;
	wire	wire_nliOl_dataout;
	wire	wire_nliOli_dataout;
	wire	wire_nliOll_dataout;
	wire	wire_nliOlO_dataout;
	wire	wire_nliOO_dataout;
	wire	wire_nliOOi_dataout;
	wire	wire_nliOOl_dataout;
	wire	wire_nliOOO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nll00i_dataout;
	wire	wire_nll00l_dataout;
	wire	wire_nll00O_dataout;
	wire	wire_nll01i_dataout;
	wire	wire_nll01l_dataout;
	wire	wire_nll01O_dataout;
	wire	wire_nll0i_dataout;
	wire	wire_nll0ii_dataout;
	wire	wire_nll0il_dataout;
	wire	wire_nll0iO_dataout;
	wire	wire_nll0l_dataout;
	wire	wire_nll0li_dataout;
	wire	wire_nll0ll_dataout;
	wire	wire_nll0O_dataout;
	wire	wire_nll10i_dataout;
	wire	wire_nll10l_dataout;
	wire	wire_nll10O_dataout;
	wire	wire_nll11i_dataout;
	wire	wire_nll11l_dataout;
	wire	wire_nll11O_dataout;
	wire	wire_nll1i_dataout;
	wire	wire_nll1ii_dataout;
	wire	wire_nll1il_dataout;
	wire	wire_nll1iO_dataout;
	wire	wire_nll1l_dataout;
	wire	wire_nll1li_dataout;
	wire	wire_nll1ll_dataout;
	wire	wire_nll1lO_dataout;
	wire	wire_nll1O_dataout;
	wire	wire_nll1Oi_dataout;
	wire	wire_nll1Ol_dataout;
	wire	wire_nll1OO_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nllii_dataout;
	wire	wire_nlliiOl_dataout;
	wire	wire_nlliiOO_dataout;
	wire	wire_nllil_dataout;
	wire	wire_nllil0l_dataout;
	wire	wire_nllil0O_dataout;
	wire	wire_nllil1i_dataout;
	wire	wire_nlliO_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllli_dataout;
	wire	wire_nllll_dataout;
	wire	wire_nlllO_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nllO00O_dataout;
	wire	wire_nllO0ii_dataout;
	wire	wire_nllO0il_dataout;
	wire	wire_nllO0iO_dataout;
	wire	wire_nllO0li_dataout;
	wire	wire_nllO0ll_dataout;
	wire	wire_nllO0lO_dataout;
	wire	wire_nllO0O_dataout;
	wire	wire_nllO0Oi_dataout;
	wire	wire_nllO0Ol_dataout;
	wire	wire_nllO0OO_dataout;
	wire	wire_nllOi_dataout;
	wire	wire_nllOi0i_dataout;
	wire	wire_nllOi0l_dataout;
	wire	wire_nllOi0O_dataout;
	wire	wire_nllOi1i_dataout;
	wire	wire_nllOi1l_dataout;
	wire	wire_nllOi1O_dataout;
	wire	wire_nllOii_dataout;
	wire	wire_nllOiii_dataout;
	wire	wire_nllOiil_dataout;
	wire	wire_nllOiiO_dataout;
	wire	wire_nllOil_dataout;
	wire	wire_nllOili_dataout;
	wire	wire_nllOiO_dataout;
	wire	wire_nllOiOO_dataout;
	wire	wire_nllOl_dataout;
	wire	wire_nllOl1i_dataout;
	wire	wire_nllOli_dataout;
	wire	wire_nllOll_dataout;
	wire	wire_nllOlO_dataout;
	wire	wire_nllOO_dataout;
	wire	wire_nllOOi_dataout;
	wire	wire_nllOOl_dataout;
	wire	wire_nllOOO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlO000l_dataout;
	wire	wire_nlO000O_dataout;
	wire	wire_nlO001l_dataout;
	wire	wire_nlO001O_dataout;
	wire	wire_nlO00ii_dataout;
	wire	wire_nlO00il_dataout;
	wire	wire_nlO00iO_dataout;
	wire	wire_nlO00li_dataout;
	wire	wire_nlO00ll_dataout;
	wire	wire_nlO00lO_dataout;
	wire	wire_nlO00O_dataout;
	wire	wire_nlO00Oi_dataout;
	wire	wire_nlO00Ol_dataout;
	wire	wire_nlO00OO_dataout;
	wire	wire_nlO010i_dataout;
	wire	wire_nlO010l_dataout;
	wire	wire_nlO010O_dataout;
	wire	wire_nlO011i_dataout;
	wire	wire_nlO011l_dataout;
	wire	wire_nlO011O_dataout;
	wire	wire_nlO01i_dataout;
	wire	wire_nlO01ii_dataout;
	wire	wire_nlO01il_dataout;
	wire	wire_nlO0i_dataout;
	wire	wire_nlO0i0i_dataout;
	wire	wire_nlO0i0l_dataout;
	wire	wire_nlO0i0O_dataout;
	wire	wire_nlO0i1i_dataout;
	wire	wire_nlO0i1l_dataout;
	wire	wire_nlO0i1O_dataout;
	wire	wire_nlO0ii_dataout;
	wire	wire_nlO0iii_dataout;
	wire	wire_nlO0iil_dataout;
	wire	wire_nlO0iiO_dataout;
	wire	wire_nlO0il_dataout;
	wire	wire_nlO0iO_dataout;
	wire	wire_nlO0l_dataout;
	wire	wire_nlO0l0O_dataout;
	wire	wire_nlO0li_dataout;
	wire	wire_nlO0lii_dataout;
	wire	wire_nlO0lil_dataout;
	wire	wire_nlO0liO_dataout;
	wire	wire_nlO0ll_dataout;
	wire	wire_nlO0lli_dataout;
	wire	wire_nlO0lll_dataout;
	wire	wire_nlO0llO_dataout;
	wire	wire_nlO0lOi_dataout;
	wire	wire_nlO0lOl_dataout;
	wire	wire_nlO0lOO_dataout;
	wire	wire_nlO0O_dataout;
	wire	wire_nlO0O0O_dataout;
	wire	wire_nlO0Oii_dataout;
	wire	wire_nlO0Oil_dataout;
	wire	wire_nlO0OiO_dataout;
	wire	wire_nlO0Oli_dataout;
	wire	wire_nlO0Oll_dataout;
	wire	wire_nlO0OlO_dataout;
	wire	wire_nlO0OOi_dataout;
	wire	wire_nlO0OOl_dataout;
	wire	wire_nlO0OOO_dataout;
	wire	wire_nlO10i_dataout;
	wire	wire_nlO10il_dataout;
	wire	wire_nlO10iO_dataout;
	wire	wire_nlO10l_dataout;
	wire	wire_nlO10li_dataout;
	wire	wire_nlO10ll_dataout;
	wire	wire_nlO10lO_dataout;
	wire	wire_nlO10O_dataout;
	wire	wire_nlO10Oi_dataout;
	wire	wire_nlO10Ol_dataout;
	wire	wire_nlO11i_dataout;
	wire	wire_nlO11l_dataout;
	wire	wire_nlO11O_dataout;
	wire	wire_nlO1i_dataout;
	wire	wire_nlO1ii_dataout;
	wire	wire_nlO1il_dataout;
	wire	wire_nlO1iO_dataout;
	wire	wire_nlO1l_dataout;
	wire	wire_nlO1li_dataout;
	wire	wire_nlO1ll_dataout;
	wire	wire_nlO1lO_dataout;
	wire	wire_nlO1O_dataout;
	wire	wire_nlO1Oi_dataout;
	wire	wire_nlO1Ol_dataout;
	wire	wire_nlO1OO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOi00i_dataout;
	wire	wire_nlOi00l_dataout;
	wire	wire_nlOi00O_dataout;
	wire	wire_nlOi01i_dataout;
	wire	wire_nlOi01l_dataout;
	wire	wire_nlOi01O_dataout;
	wire	wire_nlOi0ii_dataout;
	wire	wire_nlOi0il_dataout;
	wire	wire_nlOi0iO_dataout;
	wire	wire_nlOi0li_dataout;
	wire	wire_nlOi0ll_dataout;
	wire	wire_nlOi0lO_dataout;
	wire	wire_nlOi0Oi_dataout;
	wire	wire_nlOi0Ol_dataout;
	wire	wire_nlOi0OO_dataout;
	wire	wire_nlOi10i_dataout;
	wire	wire_nlOi10l_dataout;
	wire	wire_nlOi11i_dataout;
	wire	wire_nlOi11l_dataout;
	wire	wire_nlOi11O_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOii0i_dataout;
	wire	wire_nlOii0l_dataout;
	wire	wire_nlOii0O_dataout;
	wire	wire_nlOii1l_dataout;
	wire	wire_nlOii1O_dataout;
	wire	wire_nlOiiii_dataout;
	wire	wire_nlOiiil_dataout;
	wire	wire_nlOiiiO_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOil0i_dataout;
	wire	wire_nlOil0l_dataout;
	wire	wire_nlOil0O_dataout;
	wire	wire_nlOil1l_dataout;
	wire	wire_nlOil1O_dataout;
	wire	wire_nlOilll_dataout;
	wire	wire_nlOillO_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOli_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOll0i_dataout;
	wire	wire_nlOlliO_dataout;
	wire	wire_nlOllOl_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOlO0i_dataout;
	wire	wire_nlOlOiO_dataout;
	wire	wire_nlOlOOl_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nlOO10i_dataout;
	wire	wire_nlOO1iO_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOO_dataout;
	wire  [5:0]   wire_n001ll_o;
	wire  [3:0]   wire_n0101l_o;
	wire  [4:0]   wire_n0101O_o;
	wire  [4:0]   wire_n011llO_o;
	wire  [5:0]   wire_n011lOi_o;
	wire  [5:0]   wire_n01iO0O_o;
	wire  [4:0]   wire_nl000l_o;
	wire  [4:0]   wire_nl0Oi1i_o;
	wire  [10:0]   wire_nlO1OlO_o;
	wire  [9:0]   wire_nlO1OOi_o;
	wire  [9:0]   wire_nlO1OOl_o;
	wire  [9:0]   wire_nlO1OOO_o;
	wire  [3:0]   wire_nlOli0i_o;
	wire  wire_n000li_o;
	wire  wire_n010lOO_o;
	wire  wire_nl0Oi1l_o;
	wire  wire_nl0OiOi_o;
	wire  wire_nl0OliO_o;
	wire  wire_nl0OO0l_o;
	wire  wire_nlO0l1l_o;
	wire  wire_nlOi1Ol_o;
	wire  wire_nl0011i_o;
	wire  wire_nl0100l_o;
	wire  wire_nl0100O_o;
	wire  wire_nl010ii_o;
	wire  wire_nl010il_o;
	wire  wire_nl010iO_o;
	wire  wire_nl010li_o;
	wire  wire_nl010ll_o;
	wire  wire_nl010lO_o;
	wire  wire_nl010Oi_o;
	wire  wire_nl010Ol_o;
	wire  wire_nl010OO_o;
	wire  wire_nl011i_o;
	wire  wire_nl01i0i_o;
	wire  wire_nl01i0l_o;
	wire  wire_nl01i0O_o;
	wire  wire_nl01i1i_o;
	wire  wire_nl01i1l_o;
	wire  wire_nl01i1O_o;
	wire  wire_nl01iii_o;
	wire  wire_nl01iil_o;
	wire  wire_nl01iiO_o;
	wire  wire_nl01ili_o;
	wire  wire_nl01ill_o;
	wire  wire_nl01ilO_o;
	wire  wire_nl01iOi_o;
	wire  wire_nl01iOl_o;
	wire  wire_nl01iOO_o;
	wire  wire_nl01l0i_o;
	wire  wire_nl01l0l_o;
	wire  wire_nl01l0O_o;
	wire  wire_nl01l1i_o;
	wire  wire_nl01l1l_o;
	wire  wire_nl01l1O_o;
	wire  wire_nl01lii_o;
	wire  wire_nl01lil_o;
	wire  wire_nl01liO_o;
	wire  wire_nl01lli_o;
	wire  wire_nl01lll_o;
	wire  wire_nl01llO_o;
	wire  wire_nl01lOi_o;
	wire  wire_nl01lOl_o;
	wire  wire_nl01O0i_o;
	wire  wire_nl01O0l_o;
	wire  wire_nl01O0O_o;
	wire  wire_nl01O1i_o;
	wire  wire_nl01O1l_o;
	wire  wire_nl01O1O_o;
	wire  wire_nl01Oii_o;
	wire  wire_nl01Oil_o;
	wire  wire_nl01OiO_o;
	wire  wire_nl01Oli_o;
	wire  wire_nl01Oll_o;
	wire  wire_nl01OlO_o;
	wire  wire_nl01OOi_o;
	wire  wire_nl01OOl_o;
	wire  wire_nl01OOO_o;
	wire  wire_nl0li0O_o;
	wire  wire_nl0liii_o;
	wire  wire_nl0liil_o;
	wire  wire_nl0liiO_o;
	wire  wire_nl0lili_o;
	wire  wire_nl0lill_o;
	wire  wire_nl0lilO_o;
	wire  wire_nl0liOi_o;
	wire  wire_nl0liOl_o;
	wire  wire_nl0liOO_o;
	wire  wire_nl0ll0i_o;
	wire  wire_nl0ll0l_o;
	wire  wire_nl0ll0O_o;
	wire  wire_nl0ll1i_o;
	wire  wire_nl0ll1l_o;
	wire  wire_nl0ll1O_o;
	wire  wire_nl0llii_o;
	wire  wire_nl0llil_o;
	wire  wire_nl0llli_o;
	wire  wire_nl0llll_o;
	wire  wire_nl0lllO_o;
	wire  wire_nl0llOi_o;
	wire  wire_nl0llOl_o;
	wire  wire_nl0llOO_o;
	wire  wire_nl0lO0i_o;
	wire  wire_nl0lO0l_o;
	wire  wire_nl0lO0O_o;
	wire  wire_nl0lO1i_o;
	wire  wire_nl0lO1l_o;
	wire  wire_nl0lO1O_o;
	wire  wire_nl0lOii_o;
	wire  wire_nl0lOil_o;
	wire  wire_nl0lOiO_o;
	wire  wire_nl0lOli_o;
	wire  wire_nl0lOll_o;
	wire  wire_nl0lOlO_o;
	wire  wire_nl0lOOi_o;
	wire  wire_nl0lOOl_o;
	wire  wire_nl0O00i_o;
	wire  wire_nl0O00l_o;
	wire  wire_nl0O01i_o;
	wire  wire_nl0O01l_o;
	wire  wire_nl0O01O_o;
	wire  wire_nl1Oii_o;
	wire  wire_nl1Oil_o;
	wire  wire_nl1OiO_o;
	wire  wire_nl1Oli_o;
	wire  wire_nl1Oll_o;
	wire  wire_nl1OlO_o;
	wire  wire_nl1OOi_o;
	wire  wire_nl1OOl_o;
	wire  wire_nl1OOO_o;
	wire  wire_nli0i0i_o;
	wire  wire_nli0i0l_o;
	wire  wire_nli0i0O_o;
	wire  wire_nli0i1i_o;
	wire  wire_nli0i1l_o;
	wire  wire_nli0i1O_o;
	wire  wire_nli0iii_o;
	wire  wire_nli0iil_o;
	wire  wire_nli0iiO_o;
	wire  wire_nli0ili_o;
	wire  wire_nli0ill_o;
	wire  wire_nli0ilO_o;
	wire  wire_nli0iOi_o;
	wire  wire_nli0iOl_o;
	wire  wire_nli0iOO_o;
	wire  wire_nli0l0i_o;
	wire  wire_nli0l0l_o;
	wire  wire_nli0l1i_o;
	wire  wire_nli0l1l_o;
	wire  wire_nli0l1O_o;
	wire  wire_nli101l_o;
	wire  wire_nli101O_o;
	wire  wire_nlO001i_o;
	wire  wire_nlO01iO_o;
	wire  wire_nlO01li_o;
	wire  wire_nlO01ll_o;
	wire  wire_nlO01lO_o;
	wire  wire_nlO01Oi_o;
	wire  wire_nlO01Ol_o;
	wire  wire_nlO01OO_o;
	wire  wire_nlOll1O_o;
	wire  wire_nlOllil_o;
	wire  wire_nlOllOi_o;
	wire  wire_nlOlO1O_o;
	wire  wire_nlOlOil_o;
	wire  wire_nlOlOOi_o;
	wire  wire_nlOO11O_o;
	wire  wire_nlOO1il_o;
	wire  wire_n01010l_o;
	wire  wire_n01011O_o;
	wire  wire_n0101ii_o;
	wire  wire_n0101iO_o;
	wire  wire_n010iO_o;
	wire  wire_n010li_o;
	wire  wire_n010ll_o;
	wire  wire_n010lO_o;
	wire  wire_n010Ol_o;
	wire  wire_n010OO_o;
	wire  wire_n011O0l_o;
	wire  wire_n011O0O_o;
	wire  wire_n011Oii_o;
	wire  wire_n011Oil_o;
	wire  wire_n011OiO_o;
	wire  wire_n011Oll_o;
	wire  wire_n011OlO_o;
	wire  wire_n011OOi_o;
	wire  wire_n011OOl_o;
	wire  wire_n011OOO_o;
	wire  wire_n01i0l_o;
	wire  wire_n01i1i_o;
	wire  wire_n01i1l_o;
	wire  wire_n01iii_o;
	wire  wire_n01iiO_o;
	wire  wire_n01ill_o;
	wire  wire_nl1i0i_o;
	wire  wire_nl1i0l_o;
	wire  wire_nl1i0O_o;
	wire  wire_nl1iii_o;
	wire  wire_nl1iil_o;
	wire  wire_nl1iiO_o;
	wire  wire_nl1ili_o;
	wire  wire_nl1ill_o;
	wire  wire_nl1iOi_o;
	wire  wire_nl1iOl_o;
	wire  wire_nl1iOO_o;
	wire  wire_nl1l0i_o;
	wire  wire_nl1l0l_o;
	wire  wire_nl1l1i_o;
	wire  wire_nl1l1l_o;
	wire  wire_nl1l1O_o;
	wire  wire_nllil1l_o;
	wire  wire_nllil1O_o;
	wire  wire_nlO00i_o;
	wire  wire_nlO00l_o;
	wire  wire_nlO01l_o;
	wire  wire_nlO01O_o;
	wire  wire_nlO1i0i_o;
	wire  wire_nlO1i0l_o;
	wire  wire_nlO1i0O_o;
	wire  wire_nlO1i1l_o;
	wire  wire_nlO1i1O_o;
	wire  wire_nlO1iii_o;
	wire  wire_nlO1iil_o;
	wire  wire_nlO1iiO_o;
	wire  wire_nlO1ili_o;
	wire  wire_nlO1ill_o;
	wire  wire_nlO1iOl_o;
	wire  wire_nlO1iOO_o;
	wire  wire_nlO1l0i_o;
	wire  wire_nlO1l0l_o;
	wire  wire_nlO1l0O_o;
	wire  wire_nlO1l1i_o;
	wire  wire_nlO1l1l_o;
	wire  wire_nlO1l1O_o;
	wire  wire_nlO1lii_o;
	wire  wire_nlO1lil_o;
	wire  wire_nlO1lli_o;
	wire  wire_nlO1lOi_o;
	wire  wire_nlO1lOl_o;
	wire  wire_nlO1lOO_o;
	wire  wire_nlO1O0i_o;
	wire  wire_nlO1O0l_o;
	wire  wire_nlO1O0O_o;
	wire  wire_nlO1O1i_o;
	wire  wire_nlO1O1l_o;
	wire  wire_nlO1O1O_o;
	wire  wire_nlO1Oii_o;
	wire  wire_nlO1OiO_o;
	wire  n10000i;
	wire  n10000l;
	wire  n10000O;
	wire  n10001i;
	wire  n10001l;
	wire  n10001O;
	wire  n1000ii;
	wire  n1000il;
	wire  n1000iO;
	wire  n1000li;
	wire  n1000ll;
	wire  n1000lO;
	wire  n1000Oi;
	wire  n1000Ol;
	wire  n1000OO;
	wire  n10010i;
	wire  n10010l;
	wire  n10010O;
	wire  n10011i;
	wire  n10011l;
	wire  n10011O;
	wire  n1001ii;
	wire  n1001il;
	wire  n1001iO;
	wire  n1001li;
	wire  n1001ll;
	wire  n1001lO;
	wire  n1001Oi;
	wire  n1001Ol;
	wire  n1001OO;
	wire  n100i0i;
	wire  n100i0l;
	wire  n100i0O;
	wire  n100i1i;
	wire  n100i1l;
	wire  n100i1O;
	wire  n100iii;
	wire  n100iil;
	wire  n100iiO;
	wire  n100ili;
	wire  n100ill;
	wire  n100ilO;
	wire  n100iOi;
	wire  n100iOl;
	wire  n100iOO;
	wire  n100l0i;
	wire  n100l0l;
	wire  n100l0O;
	wire  n100l1i;
	wire  n100l1l;
	wire  n100l1O;
	wire  n100lii;
	wire  n100lil;
	wire  n100liO;
	wire  n100lli;
	wire  n100lll;
	wire  n100llO;
	wire  n100lOi;
	wire  n100lOl;
	wire  n100lOO;
	wire  n100O0i;
	wire  n100O0l;
	wire  n100O0O;
	wire  n100O1i;
	wire  n100O1l;
	wire  n100O1O;
	wire  n100Oii;
	wire  n100Oil;
	wire  n100OiO;
	wire  n100Oli;
	wire  n100Oll;
	wire  n100OlO;
	wire  n100OOi;
	wire  n100OOl;
	wire  n100OOO;
	wire  n10100i;
	wire  n10100l;
	wire  n10100O;
	wire  n10101i;
	wire  n10101l;
	wire  n10101O;
	wire  n1010ii;
	wire  n1010il;
	wire  n1010iO;
	wire  n1010li;
	wire  n1010ll;
	wire  n1010lO;
	wire  n1010Oi;
	wire  n1010Ol;
	wire  n1010OO;
	wire  n10110i;
	wire  n10110l;
	wire  n10110O;
	wire  n10111i;
	wire  n10111l;
	wire  n10111O;
	wire  n1011ii;
	wire  n1011il;
	wire  n1011iO;
	wire  n1011li;
	wire  n1011ll;
	wire  n1011lO;
	wire  n1011Oi;
	wire  n1011Ol;
	wire  n1011OO;
	wire  n101i0i;
	wire  n101i0l;
	wire  n101i0O;
	wire  n101i1i;
	wire  n101i1l;
	wire  n101i1O;
	wire  n101iii;
	wire  n101iil;
	wire  n101iiO;
	wire  n101ili;
	wire  n101ill;
	wire  n101ilO;
	wire  n101iOi;
	wire  n101iOl;
	wire  n101iOO;
	wire  n101l0i;
	wire  n101l0l;
	wire  n101l0O;
	wire  n101l1i;
	wire  n101l1l;
	wire  n101l1O;
	wire  n101lii;
	wire  n101lil;
	wire  n101liO;
	wire  n101lli;
	wire  n101lll;
	wire  n101llO;
	wire  n101lOi;
	wire  n101lOl;
	wire  n101lOO;
	wire  n101O0i;
	wire  n101O0l;
	wire  n101O0O;
	wire  n101O1i;
	wire  n101O1l;
	wire  n101O1O;
	wire  n101Oii;
	wire  n101Oil;
	wire  n101OiO;
	wire  n101Oli;
	wire  n101Oll;
	wire  n101OlO;
	wire  n101OOi;
	wire  n101OOl;
	wire  n101OOO;
	wire  n10i00i;
	wire  n10i00l;
	wire  n10i00O;
	wire  n10i01i;
	wire  n10i01l;
	wire  n10i01O;
	wire  n10i0ii;
	wire  n10i0il;
	wire  n10i0iO;
	wire  n10i0li;
	wire  n10i0ll;
	wire  n10i0lO;
	wire  n10i0Oi;
	wire  n10i0Ol;
	wire  n10i0OO;
	wire  n10i10i;
	wire  n10i10l;
	wire  n10i10O;
	wire  n10i11i;
	wire  n10i11l;
	wire  n10i11O;
	wire  n10i1ii;
	wire  n10i1il;
	wire  n10i1iO;
	wire  n10i1li;
	wire  n10i1ll;
	wire  n10i1lO;
	wire  n10i1Oi;
	wire  n10i1Ol;
	wire  n10i1OO;
	wire  n10ii0i;
	wire  n10ii0l;
	wire  n10ii0O;
	wire  n10ii1i;
	wire  n10ii1l;
	wire  n10ii1O;
	wire  n10iiii;
	wire  n10iiil;
	wire  n10iiiO;
	wire  n10iili;
	wire  n10iill;
	wire  n10iilO;
	wire  n10iiOi;
	wire  n10iiOl;
	wire  n10iiOO;
	wire  n10il0i;
	wire  n10il0l;
	wire  n10il0O;
	wire  n10il1i;
	wire  n10il1l;
	wire  n10il1O;
	wire  n10ilii;
	wire  n10ilil;
	wire  n10iliO;
	wire  n10illi;
	wire  n10illl;
	wire  n10illO;
	wire  n10ilOi;
	wire  n10ilOl;
	wire  n10ilOO;
	wire  n10iO0i;
	wire  n10iO0l;
	wire  n10iO0O;
	wire  n10iO1i;
	wire  n10iO1l;
	wire  n10iO1O;
	wire  n10iOii;
	wire  n10iOil;
	wire  n10iOiO;
	wire  n10iOli;
	wire  n10iOll;
	wire  n10iOlO;
	wire  n10iOOi;
	wire  n10iOOl;
	wire  n10iOOO;
	wire  n10l00i;
	wire  n10l00l;
	wire  n10l00O;
	wire  n10l01i;
	wire  n10l01l;
	wire  n10l01O;
	wire  n10l0ii;
	wire  n10l0il;
	wire  n10l0iO;
	wire  n10l0li;
	wire  n10l0ll;
	wire  n10l0lO;
	wire  n10l0Oi;
	wire  n10l0Ol;
	wire  n10l0OO;
	wire  n10l10i;
	wire  n10l10l;
	wire  n10l10O;
	wire  n10l11i;
	wire  n10l11l;
	wire  n10l11O;
	wire  n10l1ii;
	wire  n10l1il;
	wire  n10l1iO;
	wire  n10l1li;
	wire  n10l1ll;
	wire  n10l1lO;
	wire  n10l1Oi;
	wire  n10l1Ol;
	wire  n10l1OO;
	wire  n10li0i;
	wire  n10li0l;
	wire  n10li0O;
	wire  n10li1i;
	wire  n10li1l;
	wire  n10li1O;
	wire  n10liii;
	wire  n10liil;
	wire  n10liiO;
	wire  n10lili;
	wire  n10lill;
	wire  n10lilO;
	wire  n10liOi;
	wire  n10liOl;
	wire  n10liOO;
	wire  n10ll0i;
	wire  n10ll0l;
	wire  n10ll0O;
	wire  n10ll1i;
	wire  n10ll1l;
	wire  n10ll1O;
	wire  n10llii;
	wire  n10llil;
	wire  n10lliO;
	wire  n10llli;
	wire  n10llll;
	wire  n10lllO;
	wire  n10llOi;
	wire  n10llOl;
	wire  n10llOO;
	wire  n10lO0i;
	wire  n10lO0l;
	wire  n10lO0O;
	wire  n10lO1i;
	wire  n10lO1l;
	wire  n10lO1O;
	wire  n10lOii;
	wire  n10lOil;
	wire  n10lOiO;
	wire  n10lOli;
	wire  n10lOll;
	wire  n10lOlO;
	wire  n10lOOi;
	wire  n10lOOl;
	wire  n10lOOO;
	wire  n10O00i;
	wire  n10O00l;
	wire  n10O00O;
	wire  n10O01i;
	wire  n10O01l;
	wire  n10O01O;
	wire  n10O0ii;
	wire  n10O0il;
	wire  n10O0iO;
	wire  n10O0li;
	wire  n10O0ll;
	wire  n10O0lO;
	wire  n10O0Oi;
	wire  n10O0Ol;
	wire  n10O0OO;
	wire  n10O10i;
	wire  n10O10l;
	wire  n10O10O;
	wire  n10O11i;
	wire  n10O11l;
	wire  n10O11O;
	wire  n10O1ii;
	wire  n10O1il;
	wire  n10O1iO;
	wire  n10O1li;
	wire  n10O1ll;
	wire  n10O1lO;
	wire  n10O1Oi;
	wire  n10O1Ol;
	wire  n10O1OO;
	wire  n10Oi0i;
	wire  n10Oi0l;
	wire  n10Oi0O;
	wire  n10Oi1i;
	wire  n10Oi1l;
	wire  n10Oi1O;
	wire  n10Oiii;
	wire  n10Oiil;
	wire  n10OiiO;
	wire  n10Oili;
	wire  n10Oill;
	wire  n10OilO;
	wire  n10OiOi;
	wire  n10OiOl;
	wire  n10OiOO;
	wire  n10Ol0i;
	wire  n10Ol0l;
	wire  n10Ol0O;
	wire  n10Ol1i;
	wire  n10Ol1l;
	wire  n10Ol1O;
	wire  n10Olii;
	wire  n10Olil;
	wire  n10OliO;
	wire  n10Olli;
	wire  n10Olll;
	wire  n10OllO;
	wire  n10OlOi;
	wire  n10OlOl;
	wire  n10OlOO;
	wire  n10OO0i;
	wire  n10OO0l;
	wire  n10OO0O;
	wire  n10OO1i;
	wire  n10OO1l;
	wire  n10OO1O;
	wire  n10OOii;
	wire  n10OOil;
	wire  n10OOiO;
	wire  n10OOli;
	wire  n10OOll;
	wire  n10OOlO;
	wire  n10OOOi;
	wire  n10OOOl;
	wire  n10OOOO;
	wire  n11000i;
	wire  n11000l;
	wire  n11000O;
	wire  n11001i;
	wire  n11001l;
	wire  n11001O;
	wire  n1100ii;
	wire  n1100il;
	wire  n1100iO;
	wire  n1100li;
	wire  n1100ll;
	wire  n1100lO;
	wire  n1100Oi;
	wire  n1100Ol;
	wire  n1100OO;
	wire  n11010i;
	wire  n11010l;
	wire  n11010O;
	wire  n11011i;
	wire  n11011l;
	wire  n11011O;
	wire  n1101ii;
	wire  n1101il;
	wire  n1101iO;
	wire  n1101li;
	wire  n1101ll;
	wire  n1101lO;
	wire  n1101Oi;
	wire  n1101Ol;
	wire  n1101OO;
	wire  n110i0i;
	wire  n110i0l;
	wire  n110i0O;
	wire  n110i1i;
	wire  n110i1l;
	wire  n110i1O;
	wire  n110iii;
	wire  n110iil;
	wire  n110iiO;
	wire  n110ili;
	wire  n110ill;
	wire  n110ilO;
	wire  n110iOi;
	wire  n110iOl;
	wire  n110iOO;
	wire  n110l0i;
	wire  n110l0l;
	wire  n110l0O;
	wire  n110l1i;
	wire  n110l1l;
	wire  n110l1O;
	wire  n110lii;
	wire  n110lil;
	wire  n110liO;
	wire  n110lli;
	wire  n110lll;
	wire  n110llO;
	wire  n110lOi;
	wire  n110lOl;
	wire  n110lOO;
	wire  n110O0i;
	wire  n110O0l;
	wire  n110O0O;
	wire  n110O1i;
	wire  n110O1l;
	wire  n110O1O;
	wire  n110Oii;
	wire  n110Oil;
	wire  n110OiO;
	wire  n110Oli;
	wire  n110Oll;
	wire  n110OlO;
	wire  n110OOi;
	wire  n110OOl;
	wire  n110OOO;
	wire  n11100i;
	wire  n11100l;
	wire  n11100O;
	wire  n11101i;
	wire  n11101l;
	wire  n11101O;
	wire  n1110ii;
	wire  n1110il;
	wire  n1110iO;
	wire  n1110li;
	wire  n1110ll;
	wire  n1110lO;
	wire  n1110Oi;
	wire  n1110Ol;
	wire  n1110OO;
	wire  n11110i;
	wire  n11110l;
	wire  n11110O;
	wire  n11111i;
	wire  n11111l;
	wire  n11111O;
	wire  n1111ii;
	wire  n1111il;
	wire  n1111iO;
	wire  n1111li;
	wire  n1111ll;
	wire  n1111lO;
	wire  n1111Oi;
	wire  n1111Ol;
	wire  n1111OO;
	wire  n111i0i;
	wire  n111i0l;
	wire  n111i0O;
	wire  n111i1i;
	wire  n111i1l;
	wire  n111i1O;
	wire  n111iii;
	wire  n111iil;
	wire  n111iiO;
	wire  n111ili;
	wire  n111ill;
	wire  n111ilO;
	wire  n111iOi;
	wire  n111iOl;
	wire  n111iOO;
	wire  n111l0i;
	wire  n111l0l;
	wire  n111l0O;
	wire  n111l1i;
	wire  n111l1l;
	wire  n111l1O;
	wire  n111lii;
	wire  n111lil;
	wire  n111liO;
	wire  n111lli;
	wire  n111lll;
	wire  n111llO;
	wire  n111lOi;
	wire  n111lOl;
	wire  n111lOO;
	wire  n111O0i;
	wire  n111O0l;
	wire  n111O0O;
	wire  n111O1i;
	wire  n111O1l;
	wire  n111O1O;
	wire  n111Oii;
	wire  n111Oil;
	wire  n111OiO;
	wire  n111Oli;
	wire  n111Oll;
	wire  n111OlO;
	wire  n111OOi;
	wire  n111OOl;
	wire  n111OOO;
	wire  n11i00i;
	wire  n11i00l;
	wire  n11i00O;
	wire  n11i01i;
	wire  n11i01l;
	wire  n11i01O;
	wire  n11i0ii;
	wire  n11i0il;
	wire  n11i0iO;
	wire  n11i0li;
	wire  n11i0ll;
	wire  n11i0lO;
	wire  n11i0Oi;
	wire  n11i0Ol;
	wire  n11i0OO;
	wire  n11i10i;
	wire  n11i10l;
	wire  n11i10O;
	wire  n11i11i;
	wire  n11i11l;
	wire  n11i11O;
	wire  n11i1ii;
	wire  n11i1il;
	wire  n11i1iO;
	wire  n11i1li;
	wire  n11i1ll;
	wire  n11i1lO;
	wire  n11i1Oi;
	wire  n11i1Ol;
	wire  n11i1OO;
	wire  n11ii0i;
	wire  n11ii0l;
	wire  n11ii0O;
	wire  n11ii1i;
	wire  n11ii1l;
	wire  n11ii1O;
	wire  n11iiii;
	wire  n11iiil;
	wire  n11iiiO;
	wire  n11iili;
	wire  n11iill;
	wire  n11iilO;
	wire  n11iiOi;
	wire  n11iiOl;
	wire  n11iiOO;
	wire  n11il0i;
	wire  n11il0l;
	wire  n11il0O;
	wire  n11il1i;
	wire  n11il1l;
	wire  n11il1O;
	wire  n11ilii;
	wire  n11ilil;
	wire  n11iliO;
	wire  n11illi;
	wire  n11illl;
	wire  n11illO;
	wire  n11ilOi;
	wire  n11ilOl;
	wire  n11ilOO;
	wire  n11iO0i;
	wire  n11iO0l;
	wire  n11iO0O;
	wire  n11iO1i;
	wire  n11iO1l;
	wire  n11iO1O;
	wire  n11iOii;
	wire  n11iOil;
	wire  n11iOiO;
	wire  n11iOli;
	wire  n11iOll;
	wire  n11iOlO;
	wire  n11iOOi;
	wire  n11iOOl;
	wire  n11iOOO;
	wire  n11l00i;
	wire  n11l00l;
	wire  n11l00O;
	wire  n11l01i;
	wire  n11l01l;
	wire  n11l01O;
	wire  n11l0ii;
	wire  n11l0il;
	wire  n11l0iO;
	wire  n11l0li;
	wire  n11l0ll;
	wire  n11l0lO;
	wire  n11l0Oi;
	wire  n11l0Ol;
	wire  n11l0OO;
	wire  n11l10i;
	wire  n11l10l;
	wire  n11l10O;
	wire  n11l11i;
	wire  n11l11l;
	wire  n11l11O;
	wire  n11l1ii;
	wire  n11l1il;
	wire  n11l1iO;
	wire  n11l1li;
	wire  n11l1ll;
	wire  n11l1lO;
	wire  n11l1Oi;
	wire  n11l1Ol;
	wire  n11l1OO;
	wire  n11li0i;
	wire  n11li0l;
	wire  n11li0O;
	wire  n11li1i;
	wire  n11li1l;
	wire  n11li1O;
	wire  n11liii;
	wire  n11liil;
	wire  n11liiO;
	wire  n11lili;
	wire  n11lill;
	wire  n11lilO;
	wire  n11liOi;
	wire  n11liOl;
	wire  n11liOO;
	wire  n11ll0i;
	wire  n11ll0l;
	wire  n11ll0O;
	wire  n11ll1i;
	wire  n11ll1l;
	wire  n11ll1O;
	wire  n11llii;
	wire  n11llil;
	wire  n11lliO;
	wire  n11llli;
	wire  n11llll;
	wire  n11lllO;
	wire  n11llOi;
	wire  n11llOl;
	wire  n11llOO;
	wire  n11lO0i;
	wire  n11lO0l;
	wire  n11lO0O;
	wire  n11lO1i;
	wire  n11lO1l;
	wire  n11lO1O;
	wire  n11lOii;
	wire  n11lOil;
	wire  n11lOiO;
	wire  n11lOli;
	wire  n11lOll;
	wire  n11lOlO;
	wire  n11lOOi;
	wire  n11lOOl;
	wire  n11lOOO;
	wire  n11O00i;
	wire  n11O00l;
	wire  n11O00O;
	wire  n11O01i;
	wire  n11O01l;
	wire  n11O01O;
	wire  n11O0ii;
	wire  n11O0il;
	wire  n11O0iO;
	wire  n11O0li;
	wire  n11O0ll;
	wire  n11O0lO;
	wire  n11O0Oi;
	wire  n11O0Ol;
	wire  n11O0OO;
	wire  n11O10i;
	wire  n11O10l;
	wire  n11O10O;
	wire  n11O11i;
	wire  n11O11l;
	wire  n11O11O;
	wire  n11O1ii;
	wire  n11O1il;
	wire  n11O1iO;
	wire  n11O1li;
	wire  n11O1ll;
	wire  n11O1lO;
	wire  n11O1Oi;
	wire  n11O1Ol;
	wire  n11O1OO;
	wire  n11Oi0i;
	wire  n11Oi0l;
	wire  n11Oi0O;
	wire  n11Oi1i;
	wire  n11Oi1l;
	wire  n11Oi1O;
	wire  n11Oiii;
	wire  n11Oiil;
	wire  n11OiiO;
	wire  n11Oili;
	wire  n11Oill;
	wire  n11OilO;
	wire  n11OiOi;
	wire  n11OiOl;
	wire  n11OiOO;
	wire  n11Ol0i;
	wire  n11Ol0l;
	wire  n11Ol0O;
	wire  n11Ol1i;
	wire  n11Ol1l;
	wire  n11Ol1O;
	wire  n11Olii;
	wire  n11Olil;
	wire  n11OliO;
	wire  n11Olli;
	wire  n11Olll;
	wire  n11OllO;
	wire  n11OlOi;
	wire  n11OlOl;
	wire  n11OlOO;
	wire  n11OO0i;
	wire  n11OO0l;
	wire  n11OO0O;
	wire  n11OO1i;
	wire  n11OO1l;
	wire  n11OO1O;
	wire  n11OOii;
	wire  n11OOil;
	wire  n11OOiO;
	wire  n11OOli;
	wire  n11OOll;
	wire  n11OOlO;
	wire  n11OOOi;
	wire  n11OOOl;
	wire  n11OOOO;
	wire  n1i000i;
	wire  n1i000l;
	wire  n1i000O;
	wire  n1i001i;
	wire  n1i001l;
	wire  n1i001O;
	wire  n1i00ii;
	wire  n1i00il;
	wire  n1i00iO;
	wire  n1i00li;
	wire  n1i00ll;
	wire  n1i00lO;
	wire  n1i00Oi;
	wire  n1i00Ol;
	wire  n1i00OO;
	wire  n1i010i;
	wire  n1i010l;
	wire  n1i010O;
	wire  n1i011i;
	wire  n1i011l;
	wire  n1i011O;
	wire  n1i01ii;
	wire  n1i01il;
	wire  n1i01iO;
	wire  n1i01li;
	wire  n1i01ll;
	wire  n1i01lO;
	wire  n1i01Oi;
	wire  n1i01Ol;
	wire  n1i01OO;
	wire  n1i0i0i;
	wire  n1i0i0l;
	wire  n1i0i0O;
	wire  n1i0i1i;
	wire  n1i0i1l;
	wire  n1i0i1O;
	wire  n1i0iii;
	wire  n1i0iil;
	wire  n1i0iiO;
	wire  n1i0ili;
	wire  n1i0ill;
	wire  n1i0ilO;
	wire  n1i0iOi;
	wire  n1i0iOl;
	wire  n1i0iOO;
	wire  n1i0l0i;
	wire  n1i0l0l;
	wire  n1i0l0O;
	wire  n1i0l1i;
	wire  n1i0l1l;
	wire  n1i0l1O;
	wire  n1i0lii;
	wire  n1i0lil;
	wire  n1i0liO;
	wire  n1i0lli;
	wire  n1i0lll;
	wire  n1i0llO;
	wire  n1i0lOi;
	wire  n1i0lOl;
	wire  n1i0lOO;
	wire  n1i0O0i;
	wire  n1i0O0l;
	wire  n1i0O0O;
	wire  n1i0O1i;
	wire  n1i0O1l;
	wire  n1i0O1O;
	wire  n1i0Oii;
	wire  n1i0Oil;
	wire  n1i0OiO;
	wire  n1i0Oli;
	wire  n1i0Oll;
	wire  n1i0OlO;
	wire  n1i0OOi;
	wire  n1i0OOl;
	wire  n1i0OOO;
	wire  n1i100i;
	wire  n1i100l;
	wire  n1i100O;
	wire  n1i101i;
	wire  n1i101l;
	wire  n1i101O;
	wire  n1i10ii;
	wire  n1i10il;
	wire  n1i10iO;
	wire  n1i10li;
	wire  n1i10ll;
	wire  n1i10lO;
	wire  n1i10Oi;
	wire  n1i10Ol;
	wire  n1i10OO;
	wire  n1i110i;
	wire  n1i110l;
	wire  n1i110O;
	wire  n1i111i;
	wire  n1i111l;
	wire  n1i111O;
	wire  n1i11ii;
	wire  n1i11il;
	wire  n1i11iO;
	wire  n1i11li;
	wire  n1i11ll;
	wire  n1i11lO;
	wire  n1i11Oi;
	wire  n1i11Ol;
	wire  n1i11OO;
	wire  n1i1i0i;
	wire  n1i1i0l;
	wire  n1i1i0O;
	wire  n1i1i1i;
	wire  n1i1i1l;
	wire  n1i1i1O;
	wire  n1i1iii;
	wire  n1i1iil;
	wire  n1i1iiO;
	wire  n1i1ili;
	wire  n1i1ill;
	wire  n1i1ilO;
	wire  n1i1iOi;
	wire  n1i1iOl;
	wire  n1i1iOO;
	wire  n1i1l0i;
	wire  n1i1l0l;
	wire  n1i1l0O;
	wire  n1i1l1i;
	wire  n1i1l1l;
	wire  n1i1l1O;
	wire  n1i1lii;
	wire  n1i1lil;
	wire  n1i1liO;
	wire  n1i1lli;
	wire  n1i1lll;
	wire  n1i1llO;
	wire  n1i1lOi;
	wire  n1i1lOl;
	wire  n1i1lOO;
	wire  n1i1O0i;
	wire  n1i1O0l;
	wire  n1i1O0O;
	wire  n1i1O1i;
	wire  n1i1O1l;
	wire  n1i1O1O;
	wire  n1i1Oii;
	wire  n1i1Oil;
	wire  n1i1OiO;
	wire  n1i1Oli;
	wire  n1i1Oll;
	wire  n1i1OlO;
	wire  n1i1OOi;
	wire  n1i1OOl;
	wire  n1i1OOO;
	wire  n1ii00i;
	wire  n1ii00l;
	wire  n1ii00O;
	wire  n1ii01i;
	wire  n1ii01l;
	wire  n1ii01O;
	wire  n1ii0ii;
	wire  n1ii0il;
	wire  n1ii0iO;
	wire  n1ii0li;
	wire  n1ii0ll;
	wire  n1ii0lO;
	wire  n1ii0Oi;
	wire  n1ii0Ol;
	wire  n1ii0OO;
	wire  n1ii10i;
	wire  n1ii10l;
	wire  n1ii10O;
	wire  n1ii11i;
	wire  n1ii11l;
	wire  n1ii11O;
	wire  n1ii1ii;
	wire  n1ii1il;
	wire  n1ii1iO;
	wire  n1ii1li;
	wire  n1ii1ll;
	wire  n1ii1lO;
	wire  n1ii1Oi;
	wire  n1ii1Ol;
	wire  n1ii1OO;
	wire  n1iii0i;
	wire  n1iii0l;
	wire  n1iii0O;
	wire  n1iii1i;
	wire  n1iii1l;
	wire  n1iii1O;
	wire  n1iiiii;
	wire  n1iiiil;
	wire  n1iiiiO;
	wire  n1iiili;
	wire  n1iiill;
	wire  n1iiilO;
	wire  n1iiiOi;
	wire  n1iiiOl;
	wire  n1iiiOO;
	wire  n1iil0i;
	wire  n1iil0l;
	wire  n1iil0O;
	wire  n1iil1i;
	wire  n1iil1l;
	wire  n1iil1O;
	wire  n1iilii;
	wire  n1iilil;
	wire  n1iiliO;
	wire  n1iilli;
	wire  n1iilll;
	wire  n1iillO;
	wire  n1iilOi;
	wire  n1iilOl;
	wire  n1iilOO;
	wire  n1iiO0i;
	wire  n1iiO0l;
	wire  n1iiO0O;
	wire  n1iiO1i;
	wire  n1iiO1l;
	wire  n1iiO1O;
	wire  n1iiOii;
	wire  n1iiOil;
	wire  n1iiOiO;
	wire  n1iiOli;
	wire  n1iiOll;
	wire  n1iiOlO;
	wire  n1iiOOi;
	wire  n1iiOOl;
	wire  n1iiOOO;
	wire  n1il00i;
	wire  n1il00l;
	wire  n1il00O;
	wire  n1il01i;
	wire  n1il01l;
	wire  n1il01O;
	wire  n1il0ii;
	wire  n1il0il;
	wire  n1il0iO;
	wire  n1il0li;
	wire  n1il0ll;
	wire  n1il0lO;
	wire  n1il0Oi;
	wire  n1il0Ol;
	wire  n1il0OO;
	wire  n1il10i;
	wire  n1il10l;
	wire  n1il10O;
	wire  n1il11i;
	wire  n1il11l;
	wire  n1il11O;
	wire  n1il1ii;
	wire  n1il1il;
	wire  n1il1iO;
	wire  n1il1li;
	wire  n1il1ll;
	wire  n1il1lO;
	wire  n1il1Oi;
	wire  n1il1Ol;
	wire  n1il1OO;
	wire  n1ili0i;
	wire  n1ili0l;
	wire  n1ili0O;
	wire  n1ili1i;
	wire  n1ili1l;
	wire  n1ili1O;
	wire  n1iliii;
	wire  n1iliil;
	wire  n1iliiO;
	wire  n1ilili;
	wire  n1ilill;
	wire  n1ililO;
	wire  n1iliOi;
	wire  n1iliOl;
	wire  n1iliOO;
	wire  n1ill0i;
	wire  n1ill0l;
	wire  n1ill0O;
	wire  n1ill1i;
	wire  n1ill1l;
	wire  n1ill1O;
	wire  n1illii;
	wire  n1illil;
	wire  n1illiO;
	wire  n1illli;
	wire  n1illll;
	wire  n1illlO;
	wire  n1illOi;
	wire  n1illOl;
	wire  n1illOO;
	wire  n1ilO0i;
	wire  n1ilO0l;
	wire  n1ilO0O;
	wire  n1ilO1i;
	wire  n1ilOii;
	wire  n1ilOil;
	wire  n1ilOiO;
	wire  n1ilOli;
	wire  n1ilOll;
	wire  n1ilOlO;
	wire  n1ilOOi;
	wire  n1ilOOl;
	wire  n1ilOOO;
	wire  n1iO01i;
	wire  n1iO01l;
	wire  n1iO0iO;
	wire  n1iO0li;
	wire  n1iO10i;
	wire  n1iO10l;
	wire  n1iO10O;
	wire  n1iO11i;
	wire  n1iO11l;
	wire  n1iO11O;
	wire  n1iO1ii;
	wire  n1iO1il;
	wire  n1iO1iO;
	wire  n1iO1li;
	wire  n1iO1ll;
	wire  n1iOi0i;
	wire  n1iOi0l;
	wire  n1iOili;
	wire  n1iOill;
	wire  n1iOilO;
	wire  n1iOiOi;
	wire  n1iOl0i;
	wire  n1iOl0l;
	wire  n1iOl0O;
	wire  n1iOlii;
	wire  n1iOlil;
	wire  n1iOliO;
	wire  n1iOllO;
	wire  n1iOlOO;
	wire  n1iOO0i;
	wire  n1iOO0l;
	wire  n1iOO0O;
	wire  n1iOO1i;
	wire  n1iOOOi;
	wire  n1iOOOl;
	wire  n1iOOOO;
	wire  n1l111l;
	wire  nlOOiOOl;
	wire  nlOOiOOO;
	wire  nlOOl00i;
	wire  nlOOl00l;
	wire  nlOOl00O;
	wire  nlOOl01i;
	wire  nlOOl01l;
	wire  nlOOl01O;
	wire  nlOOl0ii;
	wire  nlOOl0il;
	wire  nlOOl0iO;
	wire  nlOOl0li;
	wire  nlOOl0ll;
	wire  nlOOl0lO;
	wire  nlOOl0Oi;
	wire  nlOOl0Ol;
	wire  nlOOl0OO;
	wire  nlOOl10i;
	wire  nlOOl10l;
	wire  nlOOl10O;
	wire  nlOOl11i;
	wire  nlOOl11l;
	wire  nlOOl11O;
	wire  nlOOl1ii;
	wire  nlOOl1il;
	wire  nlOOl1iO;
	wire  nlOOl1li;
	wire  nlOOl1ll;
	wire  nlOOl1lO;
	wire  nlOOl1Oi;
	wire  nlOOl1Ol;
	wire  nlOOl1OO;
	wire  nlOOli0i;
	wire  nlOOli0l;
	wire  nlOOli0O;
	wire  nlOOli1i;
	wire  nlOOli1l;
	wire  nlOOli1O;
	wire  nlOOliii;
	wire  nlOOliil;
	wire  nlOOliiO;
	wire  nlOOlili;
	wire  nlOOlill;
	wire  nlOOlilO;
	wire  nlOOliOi;
	wire  nlOOliOl;
	wire  nlOOliOO;
	wire  nlOOll0i;
	wire  nlOOll0l;
	wire  nlOOll0O;
	wire  nlOOll1i;
	wire  nlOOll1l;
	wire  nlOOll1O;
	wire  nlOOllii;
	wire  nlOOllil;
	wire  nlOOlliO;
	wire  nlOOllli;
	wire  nlOOllll;
	wire  nlOOlllO;
	wire  nlOOllOi;
	wire  nlOOllOl;
	wire  nlOOllOO;
	wire  nlOOlO0i;
	wire  nlOOlO0l;
	wire  nlOOlO0O;
	wire  nlOOlO1i;
	wire  nlOOlO1l;
	wire  nlOOlO1O;
	wire  nlOOlOii;
	wire  nlOOlOil;
	wire  nlOOlOiO;
	wire  nlOOlOli;
	wire  nlOOlOll;
	wire  nlOOlOlO;
	wire  nlOOlOOi;
	wire  nlOOlOOl;
	wire  nlOOlOOO;
	wire  nlOOO00i;
	wire  nlOOO00l;
	wire  nlOOO00O;
	wire  nlOOO01i;
	wire  nlOOO01l;
	wire  nlOOO01O;
	wire  nlOOO0ii;
	wire  nlOOO0il;
	wire  nlOOO0iO;
	wire  nlOOO0li;
	wire  nlOOO0ll;
	wire  nlOOO0lO;
	wire  nlOOO0Oi;
	wire  nlOOO0Ol;
	wire  nlOOO0OO;
	wire  nlOOO10i;
	wire  nlOOO10l;
	wire  nlOOO10O;
	wire  nlOOO11i;
	wire  nlOOO11l;
	wire  nlOOO11O;
	wire  nlOOO1ii;
	wire  nlOOO1il;
	wire  nlOOO1iO;
	wire  nlOOO1li;
	wire  nlOOO1ll;
	wire  nlOOO1lO;
	wire  nlOOO1Oi;
	wire  nlOOO1Ol;
	wire  nlOOO1OO;
	wire  nlOOOi0i;
	wire  nlOOOi0l;
	wire  nlOOOi0O;
	wire  nlOOOi1i;
	wire  nlOOOi1l;
	wire  nlOOOi1O;
	wire  nlOOOiii;
	wire  nlOOOiil;
	wire  nlOOOiiO;
	wire  nlOOOili;
	wire  nlOOOill;
	wire  nlOOOilO;
	wire  nlOOOiOi;
	wire  nlOOOiOl;
	wire  nlOOOiOO;
	wire  nlOOOl0i;
	wire  nlOOOl0l;
	wire  nlOOOl0O;
	wire  nlOOOl1i;
	wire  nlOOOl1l;
	wire  nlOOOl1O;
	wire  nlOOOlii;
	wire  nlOOOlil;
	wire  nlOOOliO;
	wire  nlOOOlli;
	wire  nlOOOlll;
	wire  nlOOOllO;
	wire  nlOOOlOi;
	wire  nlOOOlOl;
	wire  nlOOOlOO;
	wire  nlOOOO0i;
	wire  nlOOOO0l;
	wire  nlOOOO0O;
	wire  nlOOOO1i;
	wire  nlOOOO1l;
	wire  nlOOOO1O;
	wire  nlOOOOii;
	wire  nlOOOOil;
	wire  nlOOOOiO;
	wire  nlOOOOli;
	wire  nlOOOOll;
	wire  nlOOOOlO;
	wire  nlOOOOOi;
	wire  nlOOOOOl;
	wire  nlOOOOOO;

	initial
		n1ilO1l51 = 0;
	always @ ( posedge clk)
		  n1ilO1l51 <= n1ilO1l52;
	event n1ilO1l51_event;
	initial
		#1 ->n1ilO1l51_event;
	always @(n1ilO1l51_event)
		n1ilO1l51 <= {1{1'b1}};
	initial
		n1ilO1l52 = 0;
	always @ ( posedge clk)
		  n1ilO1l52 <= n1ilO1l51;
	initial
		n1ilO1O49 = 0;
	always @ ( posedge clk)
		  n1ilO1O49 <= n1ilO1O50;
	event n1ilO1O49_event;
	initial
		#1 ->n1ilO1O49_event;
	always @(n1ilO1O49_event)
		n1ilO1O49 <= {1{1'b1}};
	initial
		n1ilO1O50 = 0;
	always @ ( posedge clk)
		  n1ilO1O50 <= n1ilO1O49;
	initial
		n1iO00l41 = 0;
	always @ ( posedge clk)
		  n1iO00l41 <= n1iO00l42;
	event n1iO00l41_event;
	initial
		#1 ->n1iO00l41_event;
	always @(n1iO00l41_event)
		n1iO00l41 <= {1{1'b1}};
	initial
		n1iO00l42 = 0;
	always @ ( posedge clk)
		  n1iO00l42 <= n1iO00l41;
	initial
		n1iO01O43 = 0;
	always @ ( posedge clk)
		  n1iO01O43 <= n1iO01O44;
	event n1iO01O43_event;
	initial
		#1 ->n1iO01O43_event;
	always @(n1iO01O43_event)
		n1iO01O43 <= {1{1'b1}};
	initial
		n1iO01O44 = 0;
	always @ ( posedge clk)
		  n1iO01O44 <= n1iO01O43;
	initial
		n1iO0ii39 = 0;
	always @ ( posedge clk)
		  n1iO0ii39 <= n1iO0ii40;
	event n1iO0ii39_event;
	initial
		#1 ->n1iO0ii39_event;
	always @(n1iO0ii39_event)
		n1iO0ii39 <= {1{1'b1}};
	initial
		n1iO0ii40 = 0;
	always @ ( posedge clk)
		  n1iO0ii40 <= n1iO0ii39;
	initial
		n1iO0ll37 = 0;
	always @ ( posedge clk)
		  n1iO0ll37 <= n1iO0ll38;
	event n1iO0ll37_event;
	initial
		#1 ->n1iO0ll37_event;
	always @(n1iO0ll37_event)
		n1iO0ll37 <= {1{1'b1}};
	initial
		n1iO0ll38 = 0;
	always @ ( posedge clk)
		  n1iO0ll38 <= n1iO0ll37;
	initial
		n1iO0Oi35 = 0;
	always @ ( posedge clk)
		  n1iO0Oi35 <= n1iO0Oi36;
	event n1iO0Oi35_event;
	initial
		#1 ->n1iO0Oi35_event;
	always @(n1iO0Oi35_event)
		n1iO0Oi35 <= {1{1'b1}};
	initial
		n1iO0Oi36 = 0;
	always @ ( posedge clk)
		  n1iO0Oi36 <= n1iO0Oi35;
	initial
		n1iO0OO33 = 0;
	always @ ( posedge clk)
		  n1iO0OO33 <= n1iO0OO34;
	event n1iO0OO33_event;
	initial
		#1 ->n1iO0OO33_event;
	always @(n1iO0OO33_event)
		n1iO0OO33 <= {1{1'b1}};
	initial
		n1iO0OO34 = 0;
	always @ ( posedge clk)
		  n1iO0OO34 <= n1iO0OO33;
	initial
		n1iO1lO47 = 0;
	always @ ( posedge clk)
		  n1iO1lO47 <= n1iO1lO48;
	event n1iO1lO47_event;
	initial
		#1 ->n1iO1lO47_event;
	always @(n1iO1lO47_event)
		n1iO1lO47 <= {1{1'b1}};
	initial
		n1iO1lO48 = 0;
	always @ ( posedge clk)
		  n1iO1lO48 <= n1iO1lO47;
	initial
		n1iO1Ol45 = 0;
	always @ ( posedge clk)
		  n1iO1Ol45 <= n1iO1Ol46;
	event n1iO1Ol45_event;
	initial
		#1 ->n1iO1Ol45_event;
	always @(n1iO1Ol45_event)
		n1iO1Ol45 <= {1{1'b1}};
	initial
		n1iO1Ol46 = 0;
	always @ ( posedge clk)
		  n1iO1Ol46 <= n1iO1Ol45;
	initial
		n1iOi0O29 = 0;
	always @ ( posedge clk)
		  n1iOi0O29 <= n1iOi0O30;
	event n1iOi0O29_event;
	initial
		#1 ->n1iOi0O29_event;
	always @(n1iOi0O29_event)
		n1iOi0O29 <= {1{1'b1}};
	initial
		n1iOi0O30 = 0;
	always @ ( posedge clk)
		  n1iOi0O30 <= n1iOi0O29;
	initial
		n1iOi1l31 = 0;
	always @ ( posedge clk)
		  n1iOi1l31 <= n1iOi1l32;
	event n1iOi1l31_event;
	initial
		#1 ->n1iOi1l31_event;
	always @(n1iOi1l31_event)
		n1iOi1l31 <= {1{1'b1}};
	initial
		n1iOi1l32 = 0;
	always @ ( posedge clk)
		  n1iOi1l32 <= n1iOi1l31;
	initial
		n1iOiil27 = 0;
	always @ ( posedge clk)
		  n1iOiil27 <= n1iOiil28;
	event n1iOiil27_event;
	initial
		#1 ->n1iOiil27_event;
	always @(n1iOiil27_event)
		n1iOiil27 <= {1{1'b1}};
	initial
		n1iOiil28 = 0;
	always @ ( posedge clk)
		  n1iOiil28 <= n1iOiil27;
	initial
		n1iOiOl25 = 0;
	always @ ( posedge clk)
		  n1iOiOl25 <= n1iOiOl26;
	event n1iOiOl25_event;
	initial
		#1 ->n1iOiOl25_event;
	always @(n1iOiOl25_event)
		n1iOiOl25 <= {1{1'b1}};
	initial
		n1iOiOl26 = 0;
	always @ ( posedge clk)
		  n1iOiOl26 <= n1iOiOl25;
	initial
		n1iOiOO23 = 0;
	always @ ( posedge clk)
		  n1iOiOO23 <= n1iOiOO24;
	event n1iOiOO23_event;
	initial
		#1 ->n1iOiOO23_event;
	always @(n1iOiOO23_event)
		n1iOiOO23 <= {1{1'b1}};
	initial
		n1iOiOO24 = 0;
	always @ ( posedge clk)
		  n1iOiOO24 <= n1iOiOO23;
	initial
		n1iOl1i21 = 0;
	always @ ( posedge clk)
		  n1iOl1i21 <= n1iOl1i22;
	event n1iOl1i21_event;
	initial
		#1 ->n1iOl1i21_event;
	always @(n1iOl1i21_event)
		n1iOl1i21 <= {1{1'b1}};
	initial
		n1iOl1i22 = 0;
	always @ ( posedge clk)
		  n1iOl1i22 <= n1iOl1i21;
	initial
		n1iOl1l19 = 0;
	always @ ( posedge clk)
		  n1iOl1l19 <= n1iOl1l20;
	event n1iOl1l19_event;
	initial
		#1 ->n1iOl1l19_event;
	always @(n1iOl1l19_event)
		n1iOl1l19 <= {1{1'b1}};
	initial
		n1iOl1l20 = 0;
	always @ ( posedge clk)
		  n1iOl1l20 <= n1iOl1l19;
	initial
		n1iOl1O17 = 0;
	always @ ( posedge clk)
		  n1iOl1O17 <= n1iOl1O18;
	event n1iOl1O17_event;
	initial
		#1 ->n1iOl1O17_event;
	always @(n1iOl1O17_event)
		n1iOl1O17 <= {1{1'b1}};
	initial
		n1iOl1O18 = 0;
	always @ ( posedge clk)
		  n1iOl1O18 <= n1iOl1O17;
	initial
		n1iOlli15 = 0;
	always @ ( posedge clk)
		  n1iOlli15 <= n1iOlli16;
	event n1iOlli15_event;
	initial
		#1 ->n1iOlli15_event;
	always @(n1iOlli15_event)
		n1iOlli15 <= {1{1'b1}};
	initial
		n1iOlli16 = 0;
	always @ ( posedge clk)
		  n1iOlli16 <= n1iOlli15;
	initial
		n1iOlOi13 = 0;
	always @ ( posedge clk)
		  n1iOlOi13 <= n1iOlOi14;
	event n1iOlOi13_event;
	initial
		#1 ->n1iOlOi13_event;
	always @(n1iOlOi13_event)
		n1iOlOi13 <= {1{1'b1}};
	initial
		n1iOlOi14 = 0;
	always @ ( posedge clk)
		  n1iOlOi14 <= n1iOlOi13;
	initial
		n1iOO1l11 = 0;
	always @ ( posedge clk)
		  n1iOO1l11 <= n1iOO1l12;
	event n1iOO1l11_event;
	initial
		#1 ->n1iOO1l11_event;
	always @(n1iOO1l11_event)
		n1iOO1l11 <= {1{1'b1}};
	initial
		n1iOO1l12 = 0;
	always @ ( posedge clk)
		  n1iOO1l12 <= n1iOO1l11;
	initial
		n1iOO1O10 = 0;
	always @ ( posedge clk)
		  n1iOO1O10 <= n1iOO1O9;
	initial
		n1iOO1O9 = 0;
	always @ ( posedge clk)
		  n1iOO1O9 <= n1iOO1O10;
	event n1iOO1O9_event;
	initial
		#1 ->n1iOO1O9_event;
	always @(n1iOO1O9_event)
		n1iOO1O9 <= {1{1'b1}};
	initial
		n1iOOii7 = 0;
	always @ ( posedge clk)
		  n1iOOii7 <= n1iOOii8;
	event n1iOOii7_event;
	initial
		#1 ->n1iOOii7_event;
	always @(n1iOOii7_event)
		n1iOOii7 <= {1{1'b1}};
	initial
		n1iOOii8 = 0;
	always @ ( posedge clk)
		  n1iOOii8 <= n1iOOii7;
	initial
		n1iOOiO5 = 0;
	always @ ( posedge clk)
		  n1iOOiO5 <= n1iOOiO6;
	event n1iOOiO5_event;
	initial
		#1 ->n1iOOiO5_event;
	always @(n1iOOiO5_event)
		n1iOOiO5 <= {1{1'b1}};
	initial
		n1iOOiO6 = 0;
	always @ ( posedge clk)
		  n1iOOiO6 <= n1iOOiO5;
	initial
		n1iOOll3 = 0;
	always @ ( posedge clk)
		  n1iOOll3 <= n1iOOll4;
	event n1iOOll3_event;
	initial
		#1 ->n1iOOll3_event;
	always @(n1iOOll3_event)
		n1iOOll3 <= {1{1'b1}};
	initial
		n1iOOll4 = 0;
	always @ ( posedge clk)
		  n1iOOll4 <= n1iOOll3;
	initial
		n1l110i1 = 0;
	always @ ( posedge clk)
		  n1l110i1 <= n1l110i2;
	event n1l110i1_event;
	initial
		#1 ->n1l110i1_event;
	always @(n1l110i1_event)
		n1l110i1 <= {1{1'b1}};
	initial
		n1l110i2 = 0;
	always @ ( posedge clk)
		  n1l110i2 <= n1l110i1;
	initial
	begin
		nii0O = 0;
		niili = 0;
	end
	always @ (clk or wire_niiiO_PRN or wire_niiiO_CLRN)
	begin
		if (wire_niiiO_PRN == 1'b0) 
		begin
			nii0O <= 1;
			niili <= 1;
		end
		else if  (wire_niiiO_CLRN == 1'b0) 
		begin
			nii0O <= 0;
			niili <= 0;
		end
		else 
		if (clk != niiiO_clk_prev && clk == 1'b1) 
		begin
			nii0O <= niili;
			niili <= n1iOO0i;
		end
		niiiO_clk_prev <= clk;
	end
	assign
		wire_niiiO_CLRN = (n1iOO1O10 ^ n1iOO1O9),
		wire_niiiO_PRN = ((n1iOO1l12 ^ n1iOO1l11) & (~ rst));
	initial
	begin
		n0000i = 0;
		n0000l = 0;
		n0001l = 0;
		n0001O = 0;
		n000ll = 0;
		n000lO = 0;
		n000Oi = 0;
		n000Ol = 0;
		n0011l = 0;
		n00lOi = 0;
		n00lOl = 0;
		n00lOO = 0;
		n00O0i = 0;
		n00O0l = 0;
		n00O0O = 0;
		n00O1i = 0;
		n00O1l = 0;
		n00O1O = 0;
		n00Oii = 0;
		n00Oil = 0;
		n00OiO = 0;
		n00Oli = 0;
		n00Oll = 0;
		n00OlO = 0;
		n0100O = 0;
		n010ili = 0;
		n010ill = 0;
		n010ilO = 0;
		n010iOi = 0;
		n010iOl = 0;
		n010iOO = 0;
		n010l1l = 0;
		n010lii = 0;
		n010lil = 0;
		n010liO = 0;
		n010lli = 0;
		n010O1i = 0;
		n010O1l = 0;
		n0110l = 0;
		n0110O = 0;
		n011ii = 0;
		n011il = 0;
		n011ilO = 0;
		n011iO = 0;
		n011iOi = 0;
		n011iOl = 0;
		n011iOO = 0;
		n011l0i = 0;
		n011l0l = 0;
		n011l0O = 0;
		n011l1i = 0;
		n011l1l = 0;
		n011l1O = 0;
		n011li = 0;
		n011ll = 0;
		n011lO = 0;
		n011O1l = 0;
		n01iOOi = 0;
		n01iOOl = 0;
		n01iOOO = 0;
		n01l10i = 0;
		n01l10l = 0;
		n01l10O = 0;
		n01l11i = 0;
		n01l11l = 0;
		n01l11O = 0;
		n01l1ii = 0;
		n01l1il = 0;
		n01l1iO = 0;
		n01l1li = 0;
		n01l1ll = 0;
		n01l1lO = 0;
		n01l1Oi = 0;
		n01l1Ol = 0;
		n01l1OO = 0;
		n01li0i = 0;
		n01li0l = 0;
		n01li0O = 0;
		n01liii = 0;
		n01liil = 0;
		n01liiO = 0;
		n01lili = 0;
		n01lill = 0;
		n01lilO = 0;
		n01liOi = 0;
		n01liOl = 0;
		n01liOO = 0;
		n01ll0i = 0;
		n01ll1i = 0;
		n01ll1l = 0;
		n01ll1O = 0;
		n01Oli = 0;
		n01Oll = 0;
		n01OlO = 0;
		n01OOi = 0;
		n01OOl = 0;
		n01OOO = 0;
		n0i00i = 0;
		n0i00l = 0;
		n0i00O = 0;
		n0i01i = 0;
		n0i01l = 0;
		n0i01O = 0;
		n0i0ii = 0;
		n0i0il = 0;
		n0i0iO = 0;
		n0i0li = 0;
		n0i1Oi = 0;
		n0i1Ol = 0;
		n0i1OO = 0;
		nii0l = 0;
		niO0il = 0;
		niO0iO = 0;
		niO0li = 0;
		niO0ll = 0;
		niO0lO = 0;
		niO0Ol = 0;
		niO0OO = 0;
		niO11i = 0;
		niO11l = 0;
		niO11O = 0;
		niO1il = 0;
		niOi0i = 0;
		niOi0l = 0;
		niOi0O = 0;
		niOi1i = 0;
		niOi1l = 0;
		niOi1O = 0;
		niOiii = 0;
		niOiil = 0;
		niOiiO = 0;
		niOili = 0;
		niOill = 0;
		niOilO = 0;
		niOiOi = 0;
		niOiOl = 0;
		niOiOO = 0;
		niOl0i = 0;
		niOl0l = 0;
		niOl0O = 0;
		niOl1i = 0;
		niOl1l = 0;
		niOl1O = 0;
		niOlii = 0;
		niOlil = 0;
		niOliO = 0;
		niOlli = 0;
		niOlll = 0;
		niOllO = 0;
		niOlOi = 0;
		niOlOl = 0;
		niOlOO = 0;
		niOO0i = 0;
		niOO0l = 0;
		niOO1i = 0;
		niOO1l = 0;
		niOO1O = 0;
		nl0000l = 0;
		nl0000O = 0;
		nl000ii = 0;
		nl000il = 0;
		nl000iO = 0;
		nl000li = 0;
		nl000ll = 0;
		nl000lO = 0;
		nl000Oi = 0;
		nl000Ol = 0;
		nl000OO = 0;
		nl00i0i = 0;
		nl00i0l = 0;
		nl00i0O = 0;
		nl00i1i = 0;
		nl00i1l = 0;
		nl00i1O = 0;
		nl00iii = 0;
		nl00iil = 0;
		nl00iiO = 0;
		nl00il = 0;
		nl00ili = 0;
		nl00ill = 0;
		nl00ilO = 0;
		nl00iOi = 0;
		nl00iOl = 0;
		nl00iOO = 0;
		nl00l0i = 0;
		nl00l0l = 0;
		nl00l0O = 0;
		nl00l1i = 0;
		nl00l1l = 0;
		nl00l1O = 0;
		nl00li = 0;
		nl00lii = 0;
		nl00lil = 0;
		nl00liO = 0;
		nl00ll = 0;
		nl00lli = 0;
		nl00lll = 0;
		nl00llO = 0;
		nl00lO = 0;
		nl00lOi = 0;
		nl00lOl = 0;
		nl00lOO = 0;
		nl00O0i = 0;
		nl00O0l = 0;
		nl00O0O = 0;
		nl00O1i = 0;
		nl00O1l = 0;
		nl00O1O = 0;
		nl00Oi = 0;
		nl00Oii = 0;
		nl00Oil = 0;
		nl00OiO = 0;
		nl00Ol = 0;
		nl0100i = 0;
		nl010i = 0;
		nl011l = 0;
		nl011O = 0;
		nl01ll = 0;
		nl01lOO = 0;
		nl0i00i = 0;
		nl0i00l = 0;
		nl0i00O = 0;
		nl0i01i = 0;
		nl0i01l = 0;
		nl0i01O = 0;
		nl0i0i = 0;
		nl0i0ii = 0;
		nl0i0il = 0;
		nl0i0iO = 0;
		nl0i0l = 0;
		nl0i0li = 0;
		nl0i0ll = 0;
		nl0i0lO = 0;
		nl0i0Oi = 0;
		nl0i0Ol = 0;
		nl0i0OO = 0;
		nl0i1li = 0;
		nl0i1ll = 0;
		nl0i1lO = 0;
		nl0i1Oi = 0;
		nl0i1Ol = 0;
		nl0i1OO = 0;
		nl0ii0i = 0;
		nl0ii0l = 0;
		nl0ii0O = 0;
		nl0ii1i = 0;
		nl0ii1l = 0;
		nl0ii1O = 0;
		nl0iiii = 0;
		nl0iiil = 0;
		nl0iiiO = 0;
		nl0iili = 0;
		nl0iill = 0;
		nl0iilO = 0;
		nl0iiOi = 0;
		nl0iiOl = 0;
		nl0iiOO = 0;
		nl0il0i = 0;
		nl0il0l = 0;
		nl0il1i = 0;
		nl0il1l = 0;
		nl0il1O = 0;
		nl0ill = 0;
		nl1liO = 0;
		nl1lli = 0;
		nl1llO = 0;
		nl1lOi = 0;
		nl1lOl = 0;
		nl1lOO = 0;
		nl1O0i = 0;
		nl1O0l = 0;
		nl1O0O = 0;
		nl1O1i = 0;
		nl1O1l = 0;
		nl1O1O = 0;
		nll0lO = 0;
		nll0Oi = 0;
		nll0Ol = 0;
		nll0OO = 0;
		nlli0i = 0;
		nlli0l = 0;
		nlli1i = 0;
		nlli1l = 0;
		nlli1O = 0;
		nlliiO = 0;
		nllili = 0;
		nllill = 0;
		nllilO = 0;
		nlliOi = 0;
		nlliOl = 0;
		nlliOll = 0;
		nlliOlO = 0;
		nlliOO = 0;
		nlliOOi = 0;
		nlliOOl = 0;
		nlliOOO = 0;
		nlll00i = 0;
		nlll00l = 0;
		nlll00O = 0;
		nlll01i = 0;
		nlll01l = 0;
		nlll01O = 0;
		nlll0i = 0;
		nlll0ii = 0;
		nlll0il = 0;
		nlll0iO = 0;
		nlll0l = 0;
		nlll0li = 0;
		nlll0ll = 0;
		nlll0lO = 0;
		nlll0O = 0;
		nlll0Oi = 0;
		nlll0Ol = 0;
		nlll0OO = 0;
		nlll10i = 0;
		nlll10l = 0;
		nlll10O = 0;
		nlll11i = 0;
		nlll11l = 0;
		nlll11O = 0;
		nlll1i = 0;
		nlll1ii = 0;
		nlll1il = 0;
		nlll1iO = 0;
		nlll1l = 0;
		nlll1li = 0;
		nlll1ll = 0;
		nlll1lO = 0;
		nlll1O = 0;
		nlll1Oi = 0;
		nlll1Ol = 0;
		nlll1OO = 0;
		nllli0i = 0;
		nllli0l = 0;
		nllli0O = 0;
		nllli1i = 0;
		nllli1l = 0;
		nllli1O = 0;
		nlllii = 0;
		nllliii = 0;
		nllliil = 0;
		nllliiO = 0;
		nlllil = 0;
		nlllili = 0;
		nlllill = 0;
		nlllilO = 0;
		nllliO = 0;
		nllliOi = 0;
		nllliOl = 0;
		nllliOO = 0;
		nllll0i = 0;
		nllll0l = 0;
		nllll0O = 0;
		nllll1i = 0;
		nllll1l = 0;
		nllll1O = 0;
		nlllli = 0;
		nllllii = 0;
		nllllil = 0;
		nlllliO = 0;
		nlllll = 0;
		nllllli = 0;
		nllllll = 0;
		nlllllO = 0;
		nllllO = 0;
		nllllOi = 0;
		nllllOl = 0;
		nllllOO = 0;
		nlllO0i = 0;
		nlllO0l = 0;
		nlllO0O = 0;
		nlllO1i = 0;
		nlllO1l = 0;
		nlllO1O = 0;
		nlllOi = 0;
		nlllOii = 0;
		nlllOil = 0;
		nlllOiO = 0;
		nlllOl = 0;
		nlllOli = 0;
		nlllOll = 0;
		nlllOlO = 0;
		nlllOO = 0;
		nlllOOi = 0;
		nlllOOl = 0;
		nlllOOO = 0;
		nllO00i = 0;
		nllO00l = 0;
		nllO01i = 0;
		nllO01l = 0;
		nllO01O = 0;
		nllO10i = 0;
		nllO10l = 0;
		nllO10O = 0;
		nllO11i = 0;
		nllO11l = 0;
		nllO11O = 0;
		nllO1i = 0;
		nllO1ii = 0;
		nllO1il = 0;
		nllO1iO = 0;
		nllO1l = 0;
		nllO1li = 0;
		nllO1ll = 0;
		nllO1lO = 0;
		nllO1Oi = 0;
		nllO1Ol = 0;
		nllO1OO = 0;
		nlO0OO = 0;
		nlO1i1i = 0;
		nlOi1i = 0;
		nlOiO0i = 0;
		nlOiO0l = 0;
		nlOiO1i = 0;
		nlOiO1l = 0;
		nlOiO1O = 0;
		nlOiOii = 0;
		nlOiOil = 0;
		nlOiOiO = 0;
		nlOiOli = 0;
		nlOiOll = 0;
		nlOiOlO = 0;
		nlOiOOi = 0;
		nlOiOOl = 0;
		nlOiOOO = 0;
		nlOl00i = 0;
		nlOl00l = 0;
		nlOl00O = 0;
		nlOl01i = 0;
		nlOl01l = 0;
		nlOl01O = 0;
		nlOl0ii = 0;
		nlOl0il = 0;
		nlOl0iO = 0;
		nlOl0li = 0;
		nlOl0ll = 0;
		nlOl0lO = 0;
		nlOl10i = 0;
		nlOl10l = 0;
		nlOl10O = 0;
		nlOl11i = 0;
		nlOl11l = 0;
		nlOl11O = 0;
		nlOl1ii = 0;
		nlOl1il = 0;
		nlOl1iO = 0;
		nlOl1li = 0;
		nlOl1ll = 0;
		nlOl1lO = 0;
		nlOl1Oi = 0;
		nlOl1Ol = 0;
		nlOl1OO = 0;
		nlOli1i = 0;
		nlOli1l = 0;
		nlOli1O = 0;
		nlOO00i = 0;
		nlOO00l = 0;
		nlOO00O = 0;
		nlOO01i = 0;
		nlOO01l = 0;
		nlOO01O = 0;
		nlOO0ii = 0;
		nlOO0il = 0;
		nlOO0iO = 0;
		nlOO0li = 0;
		nlOO0ll = 0;
		nlOO1li = 0;
		nlOO1ll = 0;
		nlOO1lO = 0;
		nlOO1Oi = 0;
		nlOO1Ol = 0;
		nlOO1OO = 0;
		nlOOiOi = 0;
		nlOOiOl = 0;
		nlOOiOO = 0;
		nlOOl0i = 0;
		nlOOl1i = 0;
		nlOOl1l = 0;
		nlOOl1O = 0;
		nO = 0;
	end
	always @ ( posedge clk or  negedge wire_nl_CLRN)
	begin
		if (wire_nl_CLRN == 1'b0) 
		begin
			n0000i <= 0;
			n0000l <= 0;
			n0001l <= 0;
			n0001O <= 0;
			n000ll <= 0;
			n000lO <= 0;
			n000Oi <= 0;
			n000Ol <= 0;
			n0011l <= 0;
			n00lOi <= 0;
			n00lOl <= 0;
			n00lOO <= 0;
			n00O0i <= 0;
			n00O0l <= 0;
			n00O0O <= 0;
			n00O1i <= 0;
			n00O1l <= 0;
			n00O1O <= 0;
			n00Oii <= 0;
			n00Oil <= 0;
			n00OiO <= 0;
			n00Oli <= 0;
			n00Oll <= 0;
			n00OlO <= 0;
			n0100O <= 0;
			n010ili <= 0;
			n010ill <= 0;
			n010ilO <= 0;
			n010iOi <= 0;
			n010iOl <= 0;
			n010iOO <= 0;
			n010l1l <= 0;
			n010lii <= 0;
			n010lil <= 0;
			n010liO <= 0;
			n010lli <= 0;
			n010O1i <= 0;
			n010O1l <= 0;
			n0110l <= 0;
			n0110O <= 0;
			n011ii <= 0;
			n011il <= 0;
			n011ilO <= 0;
			n011iO <= 0;
			n011iOi <= 0;
			n011iOl <= 0;
			n011iOO <= 0;
			n011l0i <= 0;
			n011l0l <= 0;
			n011l0O <= 0;
			n011l1i <= 0;
			n011l1l <= 0;
			n011l1O <= 0;
			n011li <= 0;
			n011ll <= 0;
			n011lO <= 0;
			n011O1l <= 0;
			n01iOOi <= 0;
			n01iOOl <= 0;
			n01iOOO <= 0;
			n01l10i <= 0;
			n01l10l <= 0;
			n01l10O <= 0;
			n01l11i <= 0;
			n01l11l <= 0;
			n01l11O <= 0;
			n01l1ii <= 0;
			n01l1il <= 0;
			n01l1iO <= 0;
			n01l1li <= 0;
			n01l1ll <= 0;
			n01l1lO <= 0;
			n01l1Oi <= 0;
			n01l1Ol <= 0;
			n01l1OO <= 0;
			n01li0i <= 0;
			n01li0l <= 0;
			n01li0O <= 0;
			n01liii <= 0;
			n01liil <= 0;
			n01liiO <= 0;
			n01lili <= 0;
			n01lill <= 0;
			n01lilO <= 0;
			n01liOi <= 0;
			n01liOl <= 0;
			n01liOO <= 0;
			n01ll0i <= 0;
			n01ll1i <= 0;
			n01ll1l <= 0;
			n01ll1O <= 0;
			n01Oli <= 0;
			n01Oll <= 0;
			n01OlO <= 0;
			n01OOi <= 0;
			n01OOl <= 0;
			n01OOO <= 0;
			n0i00i <= 0;
			n0i00l <= 0;
			n0i00O <= 0;
			n0i01i <= 0;
			n0i01l <= 0;
			n0i01O <= 0;
			n0i0ii <= 0;
			n0i0il <= 0;
			n0i0iO <= 0;
			n0i0li <= 0;
			n0i1Oi <= 0;
			n0i1Ol <= 0;
			n0i1OO <= 0;
			nii0l <= 0;
			niO0il <= 0;
			niO0iO <= 0;
			niO0li <= 0;
			niO0ll <= 0;
			niO0lO <= 0;
			niO0Ol <= 0;
			niO0OO <= 0;
			niO11i <= 0;
			niO11l <= 0;
			niO11O <= 0;
			niO1il <= 0;
			niOi0i <= 0;
			niOi0l <= 0;
			niOi0O <= 0;
			niOi1i <= 0;
			niOi1l <= 0;
			niOi1O <= 0;
			niOiii <= 0;
			niOiil <= 0;
			niOiiO <= 0;
			niOili <= 0;
			niOill <= 0;
			niOilO <= 0;
			niOiOi <= 0;
			niOiOl <= 0;
			niOiOO <= 0;
			niOl0i <= 0;
			niOl0l <= 0;
			niOl0O <= 0;
			niOl1i <= 0;
			niOl1l <= 0;
			niOl1O <= 0;
			niOlii <= 0;
			niOlil <= 0;
			niOliO <= 0;
			niOlli <= 0;
			niOlll <= 0;
			niOllO <= 0;
			niOlOi <= 0;
			niOlOl <= 0;
			niOlOO <= 0;
			niOO0i <= 0;
			niOO0l <= 0;
			niOO1i <= 0;
			niOO1l <= 0;
			niOO1O <= 0;
			nl0000l <= 0;
			nl0000O <= 0;
			nl000ii <= 0;
			nl000il <= 0;
			nl000iO <= 0;
			nl000li <= 0;
			nl000ll <= 0;
			nl000lO <= 0;
			nl000Oi <= 0;
			nl000Ol <= 0;
			nl000OO <= 0;
			nl00i0i <= 0;
			nl00i0l <= 0;
			nl00i0O <= 0;
			nl00i1i <= 0;
			nl00i1l <= 0;
			nl00i1O <= 0;
			nl00iii <= 0;
			nl00iil <= 0;
			nl00iiO <= 0;
			nl00il <= 0;
			nl00ili <= 0;
			nl00ill <= 0;
			nl00ilO <= 0;
			nl00iOi <= 0;
			nl00iOl <= 0;
			nl00iOO <= 0;
			nl00l0i <= 0;
			nl00l0l <= 0;
			nl00l0O <= 0;
			nl00l1i <= 0;
			nl00l1l <= 0;
			nl00l1O <= 0;
			nl00li <= 0;
			nl00lii <= 0;
			nl00lil <= 0;
			nl00liO <= 0;
			nl00ll <= 0;
			nl00lli <= 0;
			nl00lll <= 0;
			nl00llO <= 0;
			nl00lO <= 0;
			nl00lOi <= 0;
			nl00lOl <= 0;
			nl00lOO <= 0;
			nl00O0i <= 0;
			nl00O0l <= 0;
			nl00O0O <= 0;
			nl00O1i <= 0;
			nl00O1l <= 0;
			nl00O1O <= 0;
			nl00Oi <= 0;
			nl00Oii <= 0;
			nl00Oil <= 0;
			nl00OiO <= 0;
			nl00Ol <= 0;
			nl0100i <= 0;
			nl010i <= 0;
			nl011l <= 0;
			nl011O <= 0;
			nl01ll <= 0;
			nl01lOO <= 0;
			nl0i00i <= 0;
			nl0i00l <= 0;
			nl0i00O <= 0;
			nl0i01i <= 0;
			nl0i01l <= 0;
			nl0i01O <= 0;
			nl0i0i <= 0;
			nl0i0ii <= 0;
			nl0i0il <= 0;
			nl0i0iO <= 0;
			nl0i0l <= 0;
			nl0i0li <= 0;
			nl0i0ll <= 0;
			nl0i0lO <= 0;
			nl0i0Oi <= 0;
			nl0i0Ol <= 0;
			nl0i0OO <= 0;
			nl0i1li <= 0;
			nl0i1ll <= 0;
			nl0i1lO <= 0;
			nl0i1Oi <= 0;
			nl0i1Ol <= 0;
			nl0i1OO <= 0;
			nl0ii0i <= 0;
			nl0ii0l <= 0;
			nl0ii0O <= 0;
			nl0ii1i <= 0;
			nl0ii1l <= 0;
			nl0ii1O <= 0;
			nl0iiii <= 0;
			nl0iiil <= 0;
			nl0iiiO <= 0;
			nl0iili <= 0;
			nl0iill <= 0;
			nl0iilO <= 0;
			nl0iiOi <= 0;
			nl0iiOl <= 0;
			nl0iiOO <= 0;
			nl0il0i <= 0;
			nl0il0l <= 0;
			nl0il1i <= 0;
			nl0il1l <= 0;
			nl0il1O <= 0;
			nl0ill <= 0;
			nl1liO <= 0;
			nl1lli <= 0;
			nl1llO <= 0;
			nl1lOi <= 0;
			nl1lOl <= 0;
			nl1lOO <= 0;
			nl1O0i <= 0;
			nl1O0l <= 0;
			nl1O0O <= 0;
			nl1O1i <= 0;
			nl1O1l <= 0;
			nl1O1O <= 0;
			nll0lO <= 0;
			nll0Oi <= 0;
			nll0Ol <= 0;
			nll0OO <= 0;
			nlli0i <= 0;
			nlli0l <= 0;
			nlli1i <= 0;
			nlli1l <= 0;
			nlli1O <= 0;
			nlliiO <= 0;
			nllili <= 0;
			nllill <= 0;
			nllilO <= 0;
			nlliOi <= 0;
			nlliOl <= 0;
			nlliOll <= 0;
			nlliOlO <= 0;
			nlliOO <= 0;
			nlliOOi <= 0;
			nlliOOl <= 0;
			nlliOOO <= 0;
			nlll00i <= 0;
			nlll00l <= 0;
			nlll00O <= 0;
			nlll01i <= 0;
			nlll01l <= 0;
			nlll01O <= 0;
			nlll0i <= 0;
			nlll0ii <= 0;
			nlll0il <= 0;
			nlll0iO <= 0;
			nlll0l <= 0;
			nlll0li <= 0;
			nlll0ll <= 0;
			nlll0lO <= 0;
			nlll0O <= 0;
			nlll0Oi <= 0;
			nlll0Ol <= 0;
			nlll0OO <= 0;
			nlll10i <= 0;
			nlll10l <= 0;
			nlll10O <= 0;
			nlll11i <= 0;
			nlll11l <= 0;
			nlll11O <= 0;
			nlll1i <= 0;
			nlll1ii <= 0;
			nlll1il <= 0;
			nlll1iO <= 0;
			nlll1l <= 0;
			nlll1li <= 0;
			nlll1ll <= 0;
			nlll1lO <= 0;
			nlll1O <= 0;
			nlll1Oi <= 0;
			nlll1Ol <= 0;
			nlll1OO <= 0;
			nllli0i <= 0;
			nllli0l <= 0;
			nllli0O <= 0;
			nllli1i <= 0;
			nllli1l <= 0;
			nllli1O <= 0;
			nlllii <= 0;
			nllliii <= 0;
			nllliil <= 0;
			nllliiO <= 0;
			nlllil <= 0;
			nlllili <= 0;
			nlllill <= 0;
			nlllilO <= 0;
			nllliO <= 0;
			nllliOi <= 0;
			nllliOl <= 0;
			nllliOO <= 0;
			nllll0i <= 0;
			nllll0l <= 0;
			nllll0O <= 0;
			nllll1i <= 0;
			nllll1l <= 0;
			nllll1O <= 0;
			nlllli <= 0;
			nllllii <= 0;
			nllllil <= 0;
			nlllliO <= 0;
			nlllll <= 0;
			nllllli <= 0;
			nllllll <= 0;
			nlllllO <= 0;
			nllllO <= 0;
			nllllOi <= 0;
			nllllOl <= 0;
			nllllOO <= 0;
			nlllO0i <= 0;
			nlllO0l <= 0;
			nlllO0O <= 0;
			nlllO1i <= 0;
			nlllO1l <= 0;
			nlllO1O <= 0;
			nlllOi <= 0;
			nlllOii <= 0;
			nlllOil <= 0;
			nlllOiO <= 0;
			nlllOl <= 0;
			nlllOli <= 0;
			nlllOll <= 0;
			nlllOlO <= 0;
			nlllOO <= 0;
			nlllOOi <= 0;
			nlllOOl <= 0;
			nlllOOO <= 0;
			nllO00i <= 0;
			nllO00l <= 0;
			nllO01i <= 0;
			nllO01l <= 0;
			nllO01O <= 0;
			nllO10i <= 0;
			nllO10l <= 0;
			nllO10O <= 0;
			nllO11i <= 0;
			nllO11l <= 0;
			nllO11O <= 0;
			nllO1i <= 0;
			nllO1ii <= 0;
			nllO1il <= 0;
			nllO1iO <= 0;
			nllO1l <= 0;
			nllO1li <= 0;
			nllO1ll <= 0;
			nllO1lO <= 0;
			nllO1Oi <= 0;
			nllO1Ol <= 0;
			nllO1OO <= 0;
			nlO0OO <= 0;
			nlO1i1i <= 0;
			nlOi1i <= 0;
			nlOiO0i <= 0;
			nlOiO0l <= 0;
			nlOiO1i <= 0;
			nlOiO1l <= 0;
			nlOiO1O <= 0;
			nlOiOii <= 0;
			nlOiOil <= 0;
			nlOiOiO <= 0;
			nlOiOli <= 0;
			nlOiOll <= 0;
			nlOiOlO <= 0;
			nlOiOOi <= 0;
			nlOiOOl <= 0;
			nlOiOOO <= 0;
			nlOl00i <= 0;
			nlOl00l <= 0;
			nlOl00O <= 0;
			nlOl01i <= 0;
			nlOl01l <= 0;
			nlOl01O <= 0;
			nlOl0ii <= 0;
			nlOl0il <= 0;
			nlOl0iO <= 0;
			nlOl0li <= 0;
			nlOl0ll <= 0;
			nlOl0lO <= 0;
			nlOl10i <= 0;
			nlOl10l <= 0;
			nlOl10O <= 0;
			nlOl11i <= 0;
			nlOl11l <= 0;
			nlOl11O <= 0;
			nlOl1ii <= 0;
			nlOl1il <= 0;
			nlOl1iO <= 0;
			nlOl1li <= 0;
			nlOl1ll <= 0;
			nlOl1lO <= 0;
			nlOl1Oi <= 0;
			nlOl1Ol <= 0;
			nlOl1OO <= 0;
			nlOli1i <= 0;
			nlOli1l <= 0;
			nlOli1O <= 0;
			nlOO00i <= 0;
			nlOO00l <= 0;
			nlOO00O <= 0;
			nlOO01i <= 0;
			nlOO01l <= 0;
			nlOO01O <= 0;
			nlOO0ii <= 0;
			nlOO0il <= 0;
			nlOO0iO <= 0;
			nlOO0li <= 0;
			nlOO0ll <= 0;
			nlOO1li <= 0;
			nlOO1ll <= 0;
			nlOO1lO <= 0;
			nlOO1Oi <= 0;
			nlOO1Ol <= 0;
			nlOO1OO <= 0;
			nlOOiOi <= 0;
			nlOOiOl <= 0;
			nlOOiOO <= 0;
			nlOOl0i <= 0;
			nlOOl1i <= 0;
			nlOOl1l <= 0;
			nlOOl1O <= 0;
			nO <= 0;
		end
		else 
		begin
			n0000i <= wire_n000iO_dataout;
			n0000l <= n000ll;
			n0001l <= wire_n000ii_dataout;
			n0001O <= wire_n000il_dataout;
			n000ll <= (n00OlO | n000Ol);
			n000lO <= n000Oi;
			n000Oi <= rlv_en;
			n000Ol <= wire_n00OOi_dataout;
			n0011l <= wire_n0000O_dataout;
			n00lOi <= wire_n00OOl_dataout;
			n00lOl <= wire_n00OOO_dataout;
			n00lOO <= wire_n0i11i_dataout;
			n00O0i <= wire_n0i10l_dataout;
			n00O0l <= wire_n0i10O_dataout;
			n00O0O <= wire_n0i1ii_dataout;
			n00O1i <= wire_n0i11l_dataout;
			n00O1l <= wire_n0i11O_dataout;
			n00O1O <= wire_n0i10i_dataout;
			n00Oii <= wire_n0i1il_dataout;
			n00Oil <= wire_n0i1iO_dataout;
			n00OiO <= wire_n0i1li_dataout;
			n00Oli <= wire_n0i1ll_dataout;
			n00Oll <= wire_n0i1lO_dataout;
			n00OlO <= wire_n0i0ll_dataout;
			n0100O <= wire_n0101O_o[0];
			n010ili <= wire_n01010l_o;
			n010ill <= wire_n01010O_dataout;
			n010ilO <= wire_n0101ii_o;
			n010iOi <= wire_n0101iO_o;
			n010iOl <= wire_n0101ll_dataout;
			n010iOO <= wire_n0101lO_dataout;
			n010l1l <= wire_n010lll_dataout;
			n010lii <= wire_n010llO_dataout;
			n010lil <= wire_n010lOi_dataout;
			n010liO <= wire_n010lOl_dataout;
			n010lli <= n010O1i;
			n010O1i <= (n01l1OO | n010O1l);
			n010O1l <= wire_n01l01i_dataout;
			n0110l <= wire_n0101O_o[1];
			n0110O <= wire_n0101O_o[2];
			n011ii <= wire_n0101O_o[3];
			n011il <= wire_n011Oi_dataout;
			n011ilO <= wire_n011lOi_o[1];
			n011iO <= wire_n011Ol_dataout;
			n011iOi <= wire_n011lOi_o[2];
			n011iOl <= wire_n011lOi_o[3];
			n011iOO <= wire_n011lOi_o[4];
			n011l0i <= wire_n011lli_dataout;
			n011l0l <= wire_n011lll_dataout;
			n011l0O <= wire_n01011O_o;
			n011l1i <= wire_n011lii_dataout;
			n011l1l <= wire_n011lil_dataout;
			n011l1O <= wire_n011liO_dataout;
			n011li <= wire_n011OO_dataout;
			n011ll <= wire_n0101i_dataout;
			n011lO <= wire_n01i0l_o;
			n011O1l <= wire_n011lOi_o[0];
			n01iOOi <= wire_n01l01l_dataout;
			n01iOOl <= wire_n01l01O_dataout;
			n01iOOO <= wire_n01l00i_dataout;
			n01l10i <= wire_n01l0il_dataout;
			n01l10l <= wire_n01l0iO_dataout;
			n01l10O <= wire_n01l0li_dataout;
			n01l11i <= wire_n01l00l_dataout;
			n01l11l <= wire_n01l00O_dataout;
			n01l11O <= wire_n01l0ii_dataout;
			n01l1ii <= wire_n01l0ll_dataout;
			n01l1il <= wire_n01l0lO_dataout;
			n01l1iO <= wire_n01l0Oi_dataout;
			n01l1li <= wire_n01l0Ol_dataout;
			n01l1ll <= wire_n01l0OO_dataout;
			n01l1lO <= wire_n01li1i_dataout;
			n01l1Oi <= wire_n01li1l_dataout;
			n01l1Ol <= wire_n01li1O_dataout;
			n01l1OO <= wire_n01ll0l_dataout;
			n01li0i <= wire_n01ll0O_dataout;
			n01li0l <= wire_n01llii_dataout;
			n01li0O <= wire_n01llil_dataout;
			n01liii <= wire_n01lliO_dataout;
			n01liil <= wire_n01llli_dataout;
			n01liiO <= wire_n01llll_dataout;
			n01lili <= wire_n01lllO_dataout;
			n01lill <= wire_n01llOi_dataout;
			n01lilO <= wire_n01llOl_dataout;
			n01liOi <= wire_n01llOO_dataout;
			n01liOl <= wire_n01lO1i_dataout;
			n01liOO <= wire_n01lO1l_dataout;
			n01ll0i <= wire_n01lO0O_dataout;
			n01ll1i <= wire_n01lO1O_dataout;
			n01ll1l <= wire_n01lO0i_dataout;
			n01ll1O <= wire_n01lO0l_dataout;
			n01Oli <= wire_n01iii_o;
			n01Oll <= wire_n01iil_dataout;
			n01OlO <= wire_n01iiO_o;
			n01OOi <= wire_n01ill_o;
			n01OOl <= wire_n01iOi_dataout;
			n01OOO <= wire_n01iOl_dataout;
			n0i00i <= wire_n0ii1O_dataout;
			n0i00l <= wire_n0ii0i_dataout;
			n0i00O <= wire_n0ii0l_dataout;
			n0i01i <= wire_n0i0OO_dataout;
			n0i01l <= wire_n0ii1i_dataout;
			n0i01O <= wire_n0ii1l_dataout;
			n0i0ii <= wire_n0ii0O_dataout;
			n0i0il <= wire_n0iiii_dataout;
			n0i0iO <= wire_n0iiil_dataout;
			n0i0li <= wire_n0iiiO_dataout;
			n0i1Oi <= wire_n0i0lO_dataout;
			n0i1Ol <= wire_n0i0Oi_dataout;
			n0i1OO <= wire_n0i0Ol_dataout;
			nii0l <= (rpolinv_en & polinv_en);
			niO0il <= niO0ll;
			niO0iO <= niO0lO;
			niO0li <= wire_niO00l_dataout;
			niO0ll <= n1ili1l;
			niO0lO <= n1ili1O;
			niO0Ol <= niO0OO;
			niO0OO <= nl01ll;
			niO11i <= wire_n1i1li_dataout;
			niO11l <= (((n1il0ii | n1il00O) & n1il0lO) | (pmadwidth[0] & ((n1il00l | n1il00i) & n1iOilO)));
			niO11O <= niO0li;
			niO1il <= (((n1il0ll | n1il0li) | ((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & n1il0iO)))) | (wire_nl1lii_dataout & (wire_nl1l0O_dataout & (wire_nl1l0l_o & n1il0il))));
			niOi0i <= wire_nl110l_dataout;
			niOi0l <= wire_nl110O_dataout;
			niOi0O <= wire_nl11ii_dataout;
			niOi1i <= wire_nl111l_dataout;
			niOi1l <= wire_nl111O_dataout;
			niOi1O <= wire_nl110i_dataout;
			niOiii <= wire_nl11il_dataout;
			niOiil <= wire_nl11iO_dataout;
			niOiiO <= wire_nl11li_dataout;
			niOili <= wire_nl11ll_dataout;
			niOill <= (~ wire_n1OOOi_dataout);
			niOilO <= n1iOO1i;
			niOiOi <= n1iOlOO;
			niOiOl <= wire_n1i1li_dataout;
			niOiOO <= wire_niOOil_dataout;
			niOl0i <= wire_nl10Oi_dataout;
			niOl0l <= wire_nl10Ol_dataout;
			niOl0O <= wire_nl10OO_dataout;
			niOl1i <= wire_niOOii_dataout;
			niOl1l <= wire_nl10ll_dataout;
			niOl1O <= wire_nl10lO_dataout;
			niOlii <= wire_nl1i1i_dataout;
			niOlil <= wire_nl1i1l_dataout;
			niOliO <= wire_nl1i1O_dataout;
			niOlli <= niOO0i;
			niOlll <= wire_nl1i0i_o;
			niOllO <= wire_nl1i0l_o;
			niOlOi <= wire_nl1i0O_o;
			niOlOl <= wire_nl1iii_o;
			niOlOO <= wire_nl1iil_o;
			niOO0i <= nl0i0i;
			niOO0l <= nl1liO;
			niOO1i <= wire_nl1iiO_o;
			niOO1l <= wire_nl1ili_o;
			niOO1O <= wire_nl1ill_o;
			nl0000l <= ((~ wire_nlliiOl_dataout) & ((~ n11l1Oi) & (~ n11l1lO)));
			nl0000O <= wire_nli11Oi_dataout;
			nl000ii <= nl000OO;
			nl000il <= nl00i1i;
			nl000iO <= nl00i1l;
			nl000li <= nl00i1O;
			nl000ll <= nl00i0i;
			nl000lO <= nl00i0l;
			nl000Oi <= nl00i0O;
			nl000Ol <= nl00iii;
			nl000OO <= n11lill;
			nl00i0i <= n11llil;
			nl00i0l <= n11ll0l;
			nl00i0O <= n11llOl;
			nl00i1i <= n11liil;
			nl00i1l <= n11ll1l;
			nl00i1O <= n11liOl;
			nl00iii <= n11llll;
			nl00iil <= wire_nl0100l_o;
			nl00iiO <= wire_nl0100O_o;
			nl00il <= nl00li;
			nl00ili <= wire_nl010ii_o;
			nl00ill <= wire_nl010il_o;
			nl00ilO <= wire_nl010iO_o;
			nl00iOi <= wire_nl010li_o;
			nl00iOl <= wire_nl010ll_o;
			nl00iOO <= wire_nl010lO_o;
			nl00l0i <= wire_nl0OOiO_dataout;
			nl00l0l <= ((~ disable_rx_disp) & n1i1i0O);
			nl00l0O <= wire_n1liili_dataout;
			nl00l1i <= wire_nl010Oi_o;
			nl00l1l <= wire_nl010Ol_o;
			nl00l1O <= (~ wire_n1O100i_dataout);
			nl00li <= a1a2_size;
			nl00lii <= wire_nl0OOOl_dataout;
			nl00lil <= wire_nl0OOOO_dataout;
			nl00liO <= wire_nl010OO_o;
			nl00ll <= nl0i0O;
			nl00lli <= wire_nl01i1i_o;
			nl00lll <= wire_nl01i1l_o;
			nl00llO <= wire_nl01i1O_o;
			nl00lO <= nl0iii;
			nl00lOi <= wire_nl01i0i_o;
			nl00lOl <= wire_nl01i0l_o;
			nl00lOO <= wire_nl01i0O_o;
			nl00O0i <= (~ wire_n011i0i_dataout);
			nl00O0l <= wire_nli111l_dataout;
			nl00O0O <= ((~ disable_rx_disp) & n1i1i0l);
			nl00O1i <= wire_nl01iii_o;
			nl00O1l <= wire_nl01iil_o;
			nl00O1O <= wire_nl01iiO_o;
			nl00Oi <= nl0iil;
			nl00Oii <= wire_n1Oilli_dataout;
			nl00Oil <= wire_nli11iO_dataout;
			nl00OiO <= wire_nli11li_dataout;
			nl00Ol <= nl0ili;
			nl0100i <= wire_nli11Ol_dataout;
			nl010i <= bitslip;
			nl011l <= nl011O;
			nl011O <= nl010i;
			nl01ll <= (~ ((((nl0i1O & nl0i1l) & nl0i1i) & nl00OO) | ((((~ (nl00OO ^ nl00ll)) & (~ (nl0i1i ^ nl00lO))) & (~ (nl0i1l ^ nl00Oi))) & (~ (nl0i1O ^ nl00Ol)))));
			nl01lOO <= wire_n1Oilli_dataout;
			nl0i00i <= nl0iiiO;
			nl0i00l <= nl0iili;
			nl0i00O <= nl0iill;
			nl0i01i <= nl0ii0O;
			nl0i01l <= nl0iiii;
			nl0i01O <= nl0iiil;
			nl0i0i <= nl00il;
			nl0i0ii <= nl0iilO;
			nl0i0il <= nl0iiOi;
			nl0i0iO <= nl0iiOl;
			nl0i0l <= n1ilO0i;
			nl0i0li <= nl0iiOO;
			nl0i0ll <= nl0il1i;
			nl0i0lO <= nl0il1l;
			nl0i0Oi <= nl0il1O;
			nl0i0Ol <= nl0il0i;
			nl0i0OO <= wire_nl0il0O_dataout;
			nl0i1li <= nl0i0OO;
			nl0i1ll <= nl0ii1i;
			nl0i1lO <= nl0ii1l;
			nl0i1Oi <= nl0ii1O;
			nl0i1Ol <= nl0ii0i;
			nl0i1OO <= nl0ii0l;
			nl0ii0i <= wire_nl0illi_dataout;
			nl0ii0l <= wire_nl0illl_dataout;
			nl0ii0O <= wire_nl0illO_dataout;
			nl0ii1i <= wire_nl0ilii_dataout;
			nl0ii1l <= wire_nl0ilil_dataout;
			nl0ii1O <= wire_nl0iliO_dataout;
			nl0iiii <= wire_nl0ilOi_dataout;
			nl0iiil <= wire_nl0ilOl_dataout;
			nl0iiiO <= wire_nl0ilOO_dataout;
			nl0iili <= wire_nl0iO1i_dataout;
			nl0iill <= wire_nl0iO1l_dataout;
			nl0iilO <= wire_nl0iO1O_dataout;
			nl0iiOi <= wire_nl0iO0i_dataout;
			nl0iiOl <= wire_nl0iO0l_dataout;
			nl0iiOO <= wire_nl0iO0O_dataout;
			nl0il0i <= wire_nl0iOli_dataout;
			nl0il0l <= wire_nllil1i_dataout;
			nl0il1i <= wire_nl0iOii_dataout;
			nl0il1l <= wire_nl0iOil_dataout;
			nl0il1O <= wire_nl0iOiO_dataout;
			nl0ill <= nlllli;
			nl1liO <= (rbitloc_rev_en & bitloc_rev_en);
			nl1lli <= wire_nl1Oii_o;
			nl1llO <= wire_nl1Oil_o;
			nl1lOi <= wire_nl1OiO_o;
			nl1lOl <= wire_nl1Oli_o;
			nl1lOO <= wire_nl1Oll_o;
			nl1O0i <= wire_nl1OOO_o;
			nl1O0l <= wire_nl011i_o;
			nl1O0O <= (nl011O & (~ nl011l));
			nl1O1i <= wire_nl1OlO_o;
			nl1O1l <= wire_nl1OOi_o;
			nl1O1O <= wire_nl1OOl_o;
			nll0lO <= nlllll;
			nll0Oi <= nllllO;
			nll0Ol <= nlllOi;
			nll0OO <= nlllOl;
			nlli0i <= nllO1O;
			nlli0l <= nllO0l;
			nlli1i <= nlllOO;
			nlli1l <= nllO1i;
			nlli1O <= nllO1l;
			nlliiO <= wire_nllO0O_dataout;
			nllili <= wire_nllOii_dataout;
			nllill <= wire_nllOil_dataout;
			nllilO <= wire_nllOiO_dataout;
			nlliOi <= wire_nllOli_dataout;
			nlliOl <= wire_nllOll_dataout;
			nlliOll <= wire_nllil1O_o;
			nlliOlO <= nlliOOi;
			nlliOO <= wire_nllOlO_dataout;
			nlliOOi <= (signal_detect | rforce_sig_det_pcs);
			nlliOOl <= nlll00i;
			nlliOOO <= nlll00l;
			nlll00i <= nllliiO;
			nlll00l <= nlllili;
			nlll00O <= nlllill;
			nlll01i <= nllli0O;
			nlll01l <= nllliii;
			nlll01O <= nllliil;
			nlll0i <= wire_nlO11i_dataout;
			nlll0ii <= nlllilO;
			nlll0il <= nllliOi;
			nlll0iO <= nllliOl;
			nlll0l <= wire_nlO11l_dataout;
			nlll0li <= nllliOO;
			nlll0ll <= nllll1i;
			nlll0lO <= nllll1l;
			nlll0O <= wire_nlO11O_dataout;
			nlll0Oi <= nllll1O;
			nlll0Ol <= nllll0i;
			nlll0OO <= nllll0l;
			nlll10i <= nlll0iO;
			nlll10l <= nlll0li;
			nlll10O <= nlll0ll;
			nlll11i <= nlll00O;
			nlll11l <= nlll0ii;
			nlll11O <= nlll0il;
			nlll1i <= wire_nllOOi_dataout;
			nlll1ii <= nlll0lO;
			nlll1il <= nlll0Oi;
			nlll1iO <= nlll0Ol;
			nlll1l <= wire_nllOOl_dataout;
			nlll1li <= nlll0OO;
			nlll1ll <= nllli1i;
			nlll1lO <= nllli1l;
			nlll1O <= wire_nllOOO_dataout;
			nlll1Oi <= nllli1O;
			nlll1Ol <= nllli0i;
			nlll1OO <= nllli0l;
			nllli0i <= nlllliO;
			nllli0l <= nllllli;
			nllli0O <= nllllll;
			nllli1i <= nllll0O;
			nllli1l <= nllllii;
			nllli1O <= nllllil;
			nlllii <= wire_nlO10i_dataout;
			nllliii <= nlllllO;
			nllliil <= nllllOi;
			nllliiO <= nllllOl;
			nlllil <= wire_nlO10l_dataout;
			nlllili <= nllllOO;
			nlllill <= nlllO1i;
			nlllilO <= nlllO1l;
			nllliO <= wire_nlO10O_dataout;
			nllliOi <= nlllO1O;
			nllliOl <= nlllO0i;
			nllliOO <= nlllO0l;
			nllll0i <= nlllOiO;
			nllll0l <= nlllOli;
			nllll0O <= nlllOll;
			nllll1i <= nlllO0O;
			nllll1l <= nlllOii;
			nllll1O <= nlllOil;
			nlllli <= wire_nlO1ii_dataout;
			nllllii <= nlllOlO;
			nllllil <= nlllOOi;
			nlllliO <= nlllOOl;
			nlllll <= wire_nlO1il_dataout;
			nllllli <= nlllOOO;
			nllllll <= nllO11i;
			nlllllO <= nllO11l;
			nllllO <= wire_nlO1iO_dataout;
			nllllOi <= nllO11O;
			nllllOl <= wire_nllO00O_dataout;
			nllllOO <= wire_nllO0ii_dataout;
			nlllO0i <= wire_nllO0ll_dataout;
			nlllO0l <= wire_nllO0lO_dataout;
			nlllO0O <= wire_nllO0Oi_dataout;
			nlllO1i <= wire_nllO0il_dataout;
			nlllO1l <= wire_nllO0iO_dataout;
			nlllO1O <= wire_nllO0li_dataout;
			nlllOi <= wire_nlO1li_dataout;
			nlllOii <= wire_nllO0Ol_dataout;
			nlllOil <= wire_nllO0OO_dataout;
			nlllOiO <= wire_nllOi1i_dataout;
			nlllOl <= wire_nlO1ll_dataout;
			nlllOli <= wire_nllOi1l_dataout;
			nlllOll <= wire_nllOi1O_dataout;
			nlllOlO <= wire_nllOi0i_dataout;
			nlllOO <= wire_nlO1lO_dataout;
			nlllOOi <= wire_nllOi0l_dataout;
			nlllOOl <= wire_nllOi0O_dataout;
			nlllOOO <= wire_nllOiii_dataout;
			nllO00i <= nllO00l;
			nllO00l <= encdt;
			nllO01i <= nllO01l;
			nllO01l <= nllO01O;
			nllO01O <= nllO00i;
			nllO10i <= (nllO10O & (~ nllO10l));
			nllO10l <= nllO10O;
			nllO10O <= nllO1ii;
			nllO11i <= wire_nllOiil_dataout;
			nllO11l <= wire_nllOiiO_dataout;
			nllO11O <= wire_nllOili_dataout;
			nllO1i <= wire_nlO1Oi_dataout;
			nllO1ii <= bitslip;
			nllO1il <= nllO1iO;
			nllO1iO <= (rbyte_rev_en & byte_rev_en);
			nllO1l <= wire_nlO1Ol_dataout;
			nllO1li <= nllO1ll;
			nllO1ll <= (rbitloc_rev_en & bitloc_rev_en);
			nllO1lO <= nllO1Oi;
			nllO1Oi <= rlv_en;
			nllO1Ol <= (nllO00i & (~ nllO01O));
			nllO1OO <= wire_nllOiOO_dataout;
			nlO0OO <= wire_nlO01O_o;
			nlO1i1i <= (((wire_nlO01ii_dataout | wire_nlO010l_dataout) | wire_nlO010i_dataout) | wire_nlO011l_dataout);
			nlOi1i <= wire_nlO00i_o;
			nlOiO0i <= (rforce_sig_det_pcs | (signal_detect | lpbk_en));
			nlOiO0l <= nlOiO0i;
			nlOiO1i <= (((wire_nlO010O_dataout | wire_nlO010l_dataout) | wire_nlO011O_dataout) | wire_nlO011l_dataout);
			nlOiO1l <= (~ (((wire_nlO01il_dataout | wire_nlO01ii_dataout) | wire_nlO010O_dataout) | wire_nlO010l_dataout));
			nlOiO1O <= wire_nlO011i_dataout;
			nlOiOii <= wire_nlO1OiO_o;
			nlOiOil <= wire_nlO10ll_dataout;
			nlOiOiO <= wire_nlO10lO_dataout;
			nlOiOli <= wire_nlO10Oi_dataout;
			nlOiOll <= wire_nlO10Ol_dataout;
			nlOiOlO <= wire_nlO1i1l_o;
			nlOiOOi <= wire_nlO1i1O_o;
			nlOiOOl <= wire_nlO1i0i_o;
			nlOiOOO <= wire_nlO1i0l_o;
			nlOl00i <= wire_nlO1lOO_o;
			nlOl00l <= wire_nlO1O1i_o;
			nlOl00O <= wire_nlO1O1l_o;
			nlOl01i <= wire_nlO1lil_o;
			nlOl01l <= wire_nlO1lOi_o;
			nlOl01O <= wire_nlO1lOl_o;
			nlOl0ii <= wire_nlO1O1O_o;
			nlOl0il <= wire_nlO1O0i_o;
			nlOl0iO <= wire_nlO1O0l_o;
			nlOl0li <= wire_nlO1O0O_o;
			nlOl0ll <= wire_nlO1Oii_o;
			nlOl0lO <= nlOli1i;
			nlOl10i <= wire_nlO1iiO_o;
			nlOl10l <= wire_nlO1ili_o;
			nlOl10O <= wire_nlO1ill_o;
			nlOl11i <= wire_nlO1i0O_o;
			nlOl11l <= wire_nlO1iii_o;
			nlOl11O <= wire_nlO1iil_o;
			nlOl1ii <= wire_nlO1iOl_o;
			nlOl1il <= wire_nlO1iOO_o;
			nlOl1iO <= wire_nlO1l1i_o;
			nlOl1li <= wire_nlO1l1l_o;
			nlOl1ll <= wire_nlO1l1O_o;
			nlOl1lO <= wire_nlO1l0i_o;
			nlOl1Oi <= wire_nlO1l0l_o;
			nlOl1Ol <= wire_nlO1l0O_o;
			nlOl1OO <= wire_nlO1lii_o;
			nlOli1i <= prbs_en;
			nlOli1l <= nlOli1O;
			nlOli1O <= encdt;
			nlOO00i <= wire_nlOlO1O_o;
			nlOO00l <= n1iO0li;
			nlOO00O <= wire_nlOllOi_o;
			nlOO01i <= n1iO1ll;
			nlOO01l <= wire_nlOlOil_o;
			nlOO01O <= n1iO01l;
			nlOO0ii <= n1iOi0l;
			nlOO0il <= wire_nlOllil_o;
			nlOO0iO <= n1iOill;
			nlOO0li <= wire_nlOll1O_o;
			nlOO0ll <= n1iOill;
			nlOO1li <= n1iO10l;
			nlOO1ll <= wire_nlOO1il_o;
			nlOO1lO <= n1iO1ii;
			nlOO1Oi <= wire_nlOO11O_o;
			nlOO1Ol <= n1iO1iO;
			nlOO1OO <= wire_nlOlOOi_o;
			nlOOiOi <= n1iOi0l;
			nlOOiOl <= n1iO0li;
			nlOOiOO <= n1iO01l;
			nlOOl0i <= n1iO10l;
			nlOOl1i <= n1iO1ll;
			nlOOl1l <= n1iO1iO;
			nlOOl1O <= n1iO1ii;
			nO <= nii0l;
		end
	end
	assign
		wire_nl_CLRN = ((n1l110i2 ^ n1l110i1) & (~ wire_niiil_dataout));
	initial
	begin
		nl010l = 0;
		nl01ii = 0;
		nl01il = 0;
		nl01li = 0;
	end
	always @ ( posedge clk or  posedge wire_niiil_dataout)
	begin
		if (wire_niiil_dataout == 1'b1) 
		begin
			nl010l <= 0;
			nl01ii <= 0;
			nl01il <= 0;
			nl01li <= 0;
		end
		else if  (nl1O0O == 1'b1) 
		begin
			nl010l <= wire_nl01lO_dataout;
			nl01ii <= wire_nl01Oi_dataout;
			nl01il <= wire_nl01Ol_dataout;
			nl01li <= wire_nl01OO_dataout;
		end
	end
	initial
	begin
		nl0i0O = 0;
		nl0iii = 0;
		nl0iil = 0;
		nl0ili = 0;
	end
	always @ (clk or wire_nl0iiO_PRN or wire_nl0iiO_CLRN)
	begin
		if (wire_nl0iiO_PRN == 1'b0) 
		begin
			nl0i0O <= 1;
			nl0iii <= 1;
			nl0iil <= 1;
			nl0ili <= 1;
		end
		else if  (wire_nl0iiO_CLRN == 1'b0) 
		begin
			nl0i0O <= 0;
			nl0iii <= 0;
			nl0iil <= 0;
			nl0ili <= 0;
		end
		else if  (n1ilO0i == 1'b1) 
		if (clk != nl0iiO_clk_prev && clk == 1'b1) 
		begin
			nl0i0O <= (~ n1iOl0l);
			nl0iii <= n1iOl0O;
			nl0iil <= n1iOlii;
			nl0ili <= n1iOlil;
		end
		nl0iiO_clk_prev <= clk;
	end
	assign
		wire_nl0iiO_CLRN = (n1ilO1O50 ^ n1ilO1O49),
		wire_nl0iiO_PRN = ((n1ilO1l52 ^ n1ilO1l51) & (~ wire_niiil_dataout));
	initial
	begin
		nlli0O = 0;
		nlliii = 0;
		nlliil = 0;
		nllO0l = 0;
		nllO1O = 0;
	end
	always @ (clk or wire_nllO0i_PRN or wire_niiil_dataout)
	begin
		if (wire_nllO0i_PRN == 1'b0) 
		begin
			nlli0O <= 1;
			nlliii <= 1;
			nlliil <= 1;
			nllO0l <= 1;
			nllO1O <= 1;
		end
		else if  (wire_niiil_dataout == 1'b1) 
		begin
			nlli0O <= 0;
			nlliii <= 0;
			nlliil <= 0;
			nllO0l <= 0;
			nllO1O <= 0;
		end
		else if  (wire_nllO0i_ENA == 1'b1) 
		if (clk != nllO0i_clk_prev && clk == 1'b1) 
		begin
			nlli0O <= nlll1i;
			nlliii <= nlll1l;
			nlliil <= nlll1O;
			nllO0l <= wire_nlO01i_dataout;
			nllO1O <= wire_nlO1OO_dataout;
		end
		nllO0i_clk_prev <= clk;
	end
	assign
		wire_nllO0i_ENA = pmadwidth[0],
		wire_nllO0i_PRN = (n1iOiOl26 ^ n1iOiOl25);
	initial
	begin
		n0011i = 0;
		n010l1i = 0;
		niO0Oi = 0;
		nl00Oli = 0;
		nl00Oll = 0;
		nl00OlO = 0;
		nl00OO = 0;
		nl00OOi = 0;
		nl00OOl = 0;
		nl00OOO = 0;
		nl0i10i = 0;
		nl0i10l = 0;
		nl0i10O = 0;
		nl0i11i = 0;
		nl0i11l = 0;
		nl0i11O = 0;
		nl0i1i = 0;
		nl0i1ii = 0;
		nl0i1il = 0;
		nl0i1iO = 0;
		nl0i1l = 0;
		nl0i1O = 0;
		nlliOli = 0;
		nlOi1O = 0;
		nlOiO0O = 0;
	end
	always @ ( posedge clk or  posedge wire_niiil_dataout)
	begin
		if (wire_niiil_dataout == 1'b1) 
		begin
			n0011i <= 1;
			n010l1i <= 1;
			niO0Oi <= 1;
			nl00Oli <= 1;
			nl00Oll <= 1;
			nl00OlO <= 1;
			nl00OO <= 1;
			nl00OOi <= 1;
			nl00OOl <= 1;
			nl00OOO <= 1;
			nl0i10i <= 1;
			nl0i10l <= 1;
			nl0i10O <= 1;
			nl0i11i <= 1;
			nl0i11l <= 1;
			nl0i11O <= 1;
			nl0i1i <= 1;
			nl0i1ii <= 1;
			nl0i1il <= 1;
			nl0i1iO <= 1;
			nl0i1l <= 1;
			nl0i1O <= 1;
			nlliOli <= 1;
			nlOi1O <= 1;
			nlOiO0O <= 1;
		end
		else 
		begin
			n0011i <= (~ n000lO);
			n010l1i <= (~ nllO1lO);
			niO0Oi <= (n1iOlOO | (~ wire_n1OOOi_dataout));
			nl00Oli <= (~ n11lOiO);
			nl00Oll <= (~ n11lOli);
			nl00OlO <= n11lOll;
			nl00OO <= (~ n1iOl0l);
			nl00OOi <= n11lOlO;
			nl00OOl <= n11lOOi;
			nl00OOO <= nl0i10l;
			nl0i10i <= nl0i1iO;
			nl0i10l <= wire_nl0O11i_dataout;
			nl0i10O <= wire_nl0O11l_dataout;
			nl0i11i <= nl0i10O;
			nl0i11l <= nl0i1ii;
			nl0i11O <= nl0i1il;
			nl0i1i <= n1iOl0O;
			nl0i1ii <= wire_nl0O11O_dataout;
			nl0i1il <= wire_nl0O10i_dataout;
			nl0i1iO <= wire_nl0O10l_dataout;
			nl0i1l <= n1iOlii;
			nl0i1O <= n1iOlil;
			nlliOli <= wire_nllil1l_o;
			nlOi1O <= wire_nlO00l_o;
			nlOiO0O <= wire_nlO1lli_o;
		end
	end
	and(wire_n0000O_dataout, n0001l, n000lO);
	and(wire_n000ii_dataout, n0001O, n000lO);
	and(wire_n000il_dataout, n1iOOOl, n000lO);
	and(wire_n000iO_dataout, wire_n000li_o, n000lO);
	and(wire_n0010i_dataout, max_rlv_sel[1], ~((~ pmadwidth[0])));
	assign		wire_n0010l_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[0] : wire_n001ll_o[0];
	assign		wire_n0010O_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[1] : wire_n001ll_o[1];
	and(wire_n0011O_dataout, max_rlv_sel[0], ~((~ pmadwidth[0])));
	assign		wire_n001ii_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[2] : wire_n001ll_o[2];
	assign		wire_n001il_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[3] : wire_n001ll_o[3];
	assign		wire_n001iO_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[4] : wire_n001ll_o[4];
	assign		wire_n001li_dataout = ((~ pmadwidth[0]) === 1'b1) ? (~ n1i0liO) : wire_n001ll_o[5];
	assign		wire_n00i_dataout = (nO === 1'b1) ? (~ pudi[10]) : pudi[10];
	assign		wire_n00l_dataout = (nO === 1'b1) ? (~ pudi[11]) : pudi[11];
	assign		wire_n00llO_dataout = ((~ pmadwidth[0]) === 1'b1) ? n1i0lli : n1i0lll;
	assign		wire_n00O_dataout = (nO === 1'b1) ? (~ pudi[12]) : pudi[12];
	and(wire_n00OOi_dataout, ((~ n1i0O1O) | ((~ n1i0O1l) | ((~ n1i0O1i) | ((~ n1i0lOO) | ((~ n1i0lOl) | ((~ n1i0lOi) | (~ n1i0llO))))))), n000lO);
	and(wire_n00OOl_dataout, (n1iiO0l | n1iiO0i), n000lO);
	and(wire_n00OOO_dataout, ((pmadwidth[0] & n1iii0O) | ((~ pmadwidth[0]) & n1iil0l)), n000lO);
	and(wire_n01000i_dataout, nlOOOiiO, ~((~ nllO1lO)));
	and(wire_n01000l_dataout, wire_n0100ii_dataout, ~((~ nllO1lO)));
	and(wire_n01000O_dataout, (~ nlOOOiil), ~(nlOOOiiO));
	and(wire_n01001i_dataout, n01l11O, ~(nlOOOili));
	and(wire_n01001l_dataout, n01l10i, ~(nlOOOili));
	and(wire_n01001O_dataout, wire_n01000O_dataout, ~((~ nllO1lO)));
	and(wire_n0100i_dataout, n011il, n1i0iOi);
	and(wire_n0100ii_dataout, nlOOOiil, ~(nlOOOiiO));
	and(wire_n0100l_dataout, n011iO, n1i0iOi);
	and(wire_n0100li_dataout, n01li0l, ~(nlOOOili));
	and(wire_n0100ll_dataout, n01li0O, ~(nlOOOili));
	and(wire_n0100lO_dataout, n01liii, ~(nlOOOili));
	and(wire_n0100Oi_dataout, n01liil, ~(nlOOOili));
	and(wire_n0100Ol_dataout, n01liiO, ~(nlOOOili));
	and(wire_n01010O_dataout, wire_n010iil_dataout, n010iOO);
	assign		wire_n0101i_dataout = (wire_n0101O_o[4] === 1'b1) ? wire_n0101l_o[3] : wire_n010il_dataout;
	and(wire_n0101ll_dataout, wire_n010iiO_dataout, n010iOO);
	and(wire_n0101lO_dataout, nllO1lO, n010l1i);
	and(wire_n0101Oi_dataout, n01iOOO, ~(nlOOOili));
	and(wire_n0101Ol_dataout, n01l11i, ~(nlOOOili));
	and(wire_n0101OO_dataout, n01l11l, ~(nlOOOili));
	and(wire_n010i0i_dataout, (~ nlOOOill), ~(nlOOOilO));
	and(wire_n010i0l_dataout, nlOOOill, ~(nlOOOilO));
	and(wire_n010i1i_dataout, nlOOOilO, ~((~ nllO1lO)));
	and(wire_n010i1l_dataout, wire_n010i0i_dataout, ~((~ nllO1lO)));
	and(wire_n010i1O_dataout, wire_n010i0l_dataout, ~((~ nllO1lO)));
	and(wire_n010ii_dataout, n011li, n1i0iOi);
	and(wire_n010iil_dataout, n01iOOi, ~((~ nllO1lO)));
	and(wire_n010iiO_dataout, (~ n01iOOi), ~((~ nllO1lO)));
	and(wire_n010il_dataout, n011ll, n1i0iOi);
	and(wire_n010lll_dataout, n010lii, nllO1lO);
	and(wire_n010llO_dataout, n010lil, nllO1lO);
	and(wire_n010lOi_dataout, n1iOOOi, nllO1lO);
	and(wire_n010lOl_dataout, wire_n010lOO_o, nllO1lO);
	assign		wire_n011i0i_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ nlOOOi1i) & ((~ ((nlOOO00i | (nlOOO01O | nlOOO01l)) | (nlOOO01i | (nlOOO1OO | (nlOOO1Ol | nlOOO1Oi))))) & (~ (((nlOOO1lO | nlOOO1ll) | ((~ (((nlOOO1li | nlOOO1iO) | (wire_nl01i0l_o & ((~ wire_nl01i0i_o) & nlOOO1il))) | ((~ wire_nl01i0l_o) & (wire_nl01i0i_o & nlOOO1ii)))) & ((~ nlOOO10O) & (((~ wire_nl01i0O_o) & nlOOO10l) | (wire_nl01i0O_o & nlOOO10i))))) | ((((~ wire_nl01iiO_o) & nlOOO10l) | (wire_nl01iiO_o & nlOOO10i)) & (nlOOO1iO | (nlOOO1li | nlOOO10O))))))) : (~ ((((((((((((((nlOOOi1i | (nlOOO0OO | nlOOO0Ol)) | ((~ wire_nl01i0l_o) & ((~ wire_nl01i0i_o) & nlOOO0Oi))) | (wire_nl01i0l_o & (wire_nl01i0i_o & nlOOO0lO))) | ((wire_nl01iiO_o & (wire_nl01iil_o & (wire_nl01iii_o & wire_nl01i0O_o))) | ((~ wire_nl01iiO_o) & ((~ wire_nl01iil_o) & ((~ wire_nl01iii_o) & (~ wire_nl01i0O_o)))))) | ((~ wire_nl01iil_o) & ((~ wire_nl01iii_o) & ((~ wire_nl01i0O_o) & ((~ wire_nl01i0l_o) & (~ wire_nl01i0i_o)))))) | (wire_nl01iil_o & (wire_nl01iii_o & (wire_nl01i0O_o & (wire_nl01i0l_o & wire_nl01i0i_o))))) | ((~ wire_nl01iiO_o) & ((~ wire_nl01iil_o) & ((~ wire_nl01iii_o) & nlOOO0ll)))) | (wire_nl01iiO_o & (wire_nl01iil_o & (wire_nl01iii_o & nlOOO0li)))) | ((((~ wire_nl01iiO_o) & ((~ wire_nl01iil_o) & ((~ wire_nl01iii_o) & wire_nl01i0l_o))) | (wire_nl01iiO_o & (wire_nl01iil_o & (wire_nl01iii_o & (~ wire_nl01i0l_o))))) & (~ nlOOO0iO))) | (nlOOO0iO & ((wire_nl01iil_o & nlOOO0il) | ((~ wire_nl01iil_o) & nlOOO0ii)))) | (((~ wire_nl01iiO_o) & ((~ wire_nl01iil_o) & ((~ wire_nl01iii_o) & nlOOO0li))) & (~ nlOOO0lO))) | ((wire_nl01iiO_o & (wire_nl01iil_o & (wire_nl01iii_o & nlOOO0ll))) & (~ nlOOO0Oi))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nl01i0l_o) & ((~ wire_nl01i0i_o) & nlOOO00O)) | nlOOO0Ol) | (((~ wire_nl01i0l_o) | (~ wire_nl01i0i_o)) & nlOOO0Oi)) | ((~ wire_nl01i0l_o) & ((~ wire_nl01i0i_o) & (~ wire_nl01i1O_o)))) & ((nlOOO0ii | (nlOOO0ii & nlOOO00l)) | (nlOOO00l & ((~ wire_nl01iii_o) | (~ wire_nl01i0O_o))))))) | (r8b10b_dec_ibm_en[1]
 & (((((wire_nl01i0l_o & (wire_nl01i0i_o & nlOOO00O)) | nlOOO0OO) | ((wire_nl01i0l_o | wire_nl01i0i_o) & nlOOO0lO)) | (wire_nl01i0l_o & (wire_nl01i0i_o & wire_nl01i1O_o))) & ((nlOOO0il | (nlOOO0il & (wire_nl01iiO_o | wire_nl01iil_o))) | ((wire_nl01iiO_o & wire_nl01iil_o) & (wire_nl01iii_o | wire_nl01i0O_o)))))));
	assign		wire_n011lii_dataout = (wire_n011lOi_o[5] === 1'b1) ? wire_n011llO_o[0] : wire_n011lOl_dataout;
	assign		wire_n011lil_dataout = (wire_n011lOi_o[5] === 1'b1) ? wire_n011llO_o[1] : wire_n011lOO_dataout;
	assign		wire_n011liO_dataout = (wire_n011lOi_o[5] === 1'b1) ? wire_n011llO_o[2] : wire_n011O1i_dataout;
	assign		wire_n011lli_dataout = (wire_n011lOi_o[5] === 1'b1) ? wire_n011llO_o[3] : wire_n011O1O_dataout;
	assign		wire_n011lll_dataout = (wire_n011lOi_o[5] === 1'b1) ? wire_n011llO_o[4] : wire_n011O0i_dataout;
	and(wire_n011lOl_dataout, n011l1i, nlOOOi1l);
	and(wire_n011lOO_dataout, n011l1l, nlOOOi1l);
	and(wire_n011O0i_dataout, n011l0l, nlOOOi1l);
	and(wire_n011O1i_dataout, n011l1O, nlOOOi1l);
	and(wire_n011O1O_dataout, n011l0i, nlOOOi1l);
	assign		wire_n011Oi_dataout = (wire_n0101O_o[4] === 1'b1) ? wire_n0101l_o[0] : wire_n0100i_dataout;
	assign		wire_n011Ol_dataout = (wire_n0101O_o[4] === 1'b1) ? wire_n0101l_o[1] : wire_n0100l_dataout;
	assign		wire_n011OO_dataout = (wire_n0101O_o[4] === 1'b1) ? wire_n0101l_o[2] : wire_n010ii_dataout;
	assign		wire_n01i_dataout = (nO === 1'b1) ? (~ pudi[5]) : pudi[5];
	and(wire_n01iil_dataout, wire_n01Oil_dataout, n01OOO);
	assign		wire_n01il0O_dataout = ((~ pmadwidth[0]) === 1'b1) ? nlOOOiOi : nlOOOiOl;
	and(wire_n01ilii_dataout, wire_n01iOii_dataout, ~((~ pmadwidth[0])));
	and(wire_n01ilil_dataout, wire_n01iOil_dataout, ~((~ pmadwidth[0])));
	assign		wire_n01iliO_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n01iOii_dataout : wire_n01ilOO_dataout;
	assign		wire_n01illi_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n01iOil_dataout : wire_n01iO1i_dataout;
	assign		wire_n01illl_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n01iOiO_dataout : wire_n01iO1l_dataout;
	assign		wire_n01illO_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n01iOli_dataout : wire_n01iO1O_dataout;
	assign		wire_n01ilOi_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n01iOll_dataout : wire_n01iO0i_dataout;
	assign		wire_n01ilOl_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n01iOlO_dataout : wire_n01iO0l_dataout;
	and(wire_n01ilOO_dataout, wire_n01iO0O_o[0], ~(nlOOOiOO));
	or(wire_n01iO0i_dataout, wire_n01iO0O_o[4], nlOOOiOO);
	and(wire_n01iO0l_dataout, wire_n01iO0O_o[5], ~(nlOOOiOO));
	and(wire_n01iO1i_dataout, wire_n01iO0O_o[1], ~(nlOOOiOO));
	and(wire_n01iO1l_dataout, wire_n01iO0O_o[2], ~(nlOOOiOO));
	and(wire_n01iO1O_dataout, wire_n01iO0O_o[3], ~(nlOOOiOO));
	and(wire_n01iOi_dataout, wire_n01OiO_dataout, n01OOO);
	and(wire_n01iOii_dataout, max_rlv_sel[0], ~(nlOOOiOO));
	and(wire_n01iOil_dataout, max_rlv_sel[1], ~(nlOOOiOO));
	and(wire_n01iOiO_dataout, max_rlv_sel[2], ~(nlOOOiOO));
	and(wire_n01iOl_dataout, n000lO, n0011i);
	and(wire_n01iOli_dataout, max_rlv_sel[3], ~(nlOOOiOO));
	and(wire_n01iOll_dataout, max_rlv_sel[4], ~(nlOOOiOO));
	and(wire_n01iOlO_dataout, max_rlv_sel[5], ~(nlOOOiOO));
	and(wire_n01iOO_dataout, n00lOO, ~(n1i0l0O));
	assign		wire_n01l_dataout = (nO === 1'b1) ? (~ pudi[6]) : pudi[6];
	and(wire_n01l00i_dataout, n11111O, nllO1lO);
	and(wire_n01l00l_dataout, n11110l, nllO1lO);
	and(wire_n01l00O_dataout, n11110O, nllO1lO);
	and(wire_n01l01i_dataout, ((~ nlOOOO1i) | ((~ nlOOOlOO) | ((~ nlOOOlOl) | ((~ nlOOOlOi) | ((~ nlOOOllO) | ((~ nlOOOlll) | ((~ nlOOOlli) | ((~ nlOOOliO) | ((~ nlOOOlil) | ((~ nlOOOlii) | ((~ nlOOOl0O) | ((~ nlOOOl0l) | ((~ nlOOOl0i) | ((~ nlOOOl1O) | ((~ nlOOOl1l) | (~ nlOOOl1i)))))))))))))))), nllO1lO);
	and(wire_n01l01l_dataout, (n11i01O | n11i01l), nllO1lO);
	and(wire_n01l01O_dataout, ((pmadwidth[0] & n1100iO) | ((~ pmadwidth[0]) & n110liO)), nllO1lO);
	and(wire_n01l0i_dataout, wire_n01lii_dataout, ~((~ n000lO)));
	and(wire_n01l0ii_dataout, n1111ii, nllO1lO);
	and(wire_n01l0il_dataout, n1111il, nllO1lO);
	and(wire_n01l0iO_dataout, n01l1li, nllO1lO);
	and(wire_n01l0l_dataout, n1i0l0l, ~((~ n000lO)));
	and(wire_n01l0li_dataout, n01l1ll, nllO1lO);
	and(wire_n01l0ll_dataout, n01l1lO, nllO1lO);
	and(wire_n01l0lO_dataout, n01l1Oi, nllO1lO);
	and(wire_n01l0O_dataout, wire_n01lil_dataout, ~((~ n000lO)));
	and(wire_n01l0Oi_dataout, n01l1Ol, nllO1lO);
	and(wire_n01l0Ol_dataout, n1110lO, nllO1lO);
	and(wire_n01l0OO_dataout, n1110Ol, nllO1lO);
	and(wire_n01l1i_dataout, n00O1i, ~(n1i0l0O));
	and(wire_n01l1l_dataout, n00O1l, ~(n1i0l0O));
	and(wire_n01l1O_dataout, n00O1O, ~(n1i0l0O));
	and(wire_n01li1i_dataout, n1110OO, nllO1lO);
	and(wire_n01li1l_dataout, n111i1i, nllO1lO);
	and(wire_n01li1O_dataout, n111i1l, nllO1lO);
	and(wire_n01lii_dataout, (~ n1i0l0i), ~(n1i0l0l));
	and(wire_n01lil_dataout, n1i0l0i, ~(n1i0l0l));
	and(wire_n01ll0l_dataout, ((~ n11111l) | ((~ n11111i) | ((~ nlOOOOOO) | ((~ nlOOOOOl) | ((~ nlOOOOOi) | ((~ nlOOOOlO) | ((~ nlOOOOll) | ((~ nlOOOOli) | ((~ nlOOOOiO) | ((~ nlOOOOil) | ((~ nlOOOOii) | ((~ nlOOOO0O) | ((~ nlOOOO0l) | ((~ nlOOOO0i) | ((~ nlOOOO1O) | (~ nlOOOO1l)))))))))))))))), nllO1lO);
	and(wire_n01ll0O_dataout, ((pmadwidth[0] & n11i00i) | ((~ pmadwidth[0]) & (~ n11il0i))), nllO1lO);
	and(wire_n01llii_dataout, n111l0O, nllO1lO);
	and(wire_n01llil_dataout, n111lil, nllO1lO);
	and(wire_n01lliO_dataout, n111liO, nllO1lO);
	and(wire_n01lll_dataout, n0i1Ol, ~(n1i0l0O));
	and(wire_n01llli_dataout, n111lli, nllO1lO);
	and(wire_n01llll_dataout, n111lll, nllO1lO);
	and(wire_n01lllO_dataout, n01liOO, nllO1lO);
	and(wire_n01llO_dataout, n0i1OO, ~(n1i0l0O));
	and(wire_n01llOi_dataout, n01ll1i, nllO1lO);
	and(wire_n01llOl_dataout, n01ll1l, nllO1lO);
	and(wire_n01llOO_dataout, n01ll1O, nllO1lO);
	and(wire_n01lO0i_dataout, n11011O, nllO1lO);
	and(wire_n01lO0l_dataout, n11010i, nllO1lO);
	and(wire_n01lO0O_dataout, n11010l, nllO1lO);
	and(wire_n01lO1i_dataout, n01ll0i, nllO1lO);
	and(wire_n01lO1l_dataout, n111OOO, nllO1lO);
	and(wire_n01lO1O_dataout, n11011l, nllO1lO);
	and(wire_n01lOi_dataout, n0i01i, ~(n1i0l0O));
	and(wire_n01lOl_dataout, n0i01l, ~(n1i0l0O));
	assign		wire_n01O_dataout = (nO === 1'b1) ? (~ pudi[7]) : pudi[7];
	and(wire_n01O0i_dataout, (~ n1i0lii), ~(n1i0lil));
	and(wire_n01O0l_dataout, n1i0lii, ~(n1i0lil));
	and(wire_n01O1i_dataout, n1i0lil, ~((~ n000lO)));
	and(wire_n01O1l_dataout, wire_n01O0i_dataout, ~((~ n000lO)));
	and(wire_n01O1O_dataout, wire_n01O0l_dataout, ~((~ n000lO)));
	and(wire_n01Oil_dataout, n00lOi, ~((~ n000lO)));
	and(wire_n01OiO_dataout, (~ n00lOi), ~((~ n000lO)));
	assign		wire_n0i_dataout = (wa_6g_en === 1'b1) ? n1iOOOO : nlO1i1i;
	and(wire_n0i0ll_dataout, ((~ n1i0Oli) | ((~ n1i0OiO) | ((~ n1i0Oil) | ((~ n1i0Oii) | ((~ n1i0O0O) | ((~ n1i0O0l) | (~ n1i0O0i))))))), n000lO);
	and(wire_n0i0lO_dataout, ((pmadwidth[0] & n1iiO0O) | ((~ pmadwidth[0]) & (~ n1il10l))), n000lO);
	and(wire_n0i0Oi_dataout, n1ii01i, n000lO);
	and(wire_n0i0Ol_dataout, n1ii01O, n000lO);
	and(wire_n0i0OO_dataout, ((((~ n1ii0iO) | (~ n1ii0il)) | (~ n1ii0ii)) | (~ n1ii00O)), n000lO);
	and(wire_n0i10i_dataout, ((n1iii0O | (~ n1ii10l)) | (~ (((~ n1iil0l) | n1iiiii) | n1iii0O))), n000lO);
	and(wire_n0i10l_dataout, n00Oil, n000lO);
	and(wire_n0i10O_dataout, n00OiO, n000lO);
	and(wire_n0i11i_dataout, n1i0Oll, n000lO);
	and(wire_n0i11l_dataout, n1i0OOi, n000lO);
	and(wire_n0i11O_dataout, ((((~ n1ii10i) | (~ n1ii11O)) | (~ n1ii11l)) | (~ n1ii11i)), n000lO);
	and(wire_n0i1ii_dataout, n00Oli, n000lO);
	and(wire_n0i1il_dataout, n00Oll, n000lO);
	and(wire_n0i1iO_dataout, n1ii10O, n000lO);
	and(wire_n0i1li_dataout, n1ii1il, n000lO);
	and(wire_n0i1ll_dataout, ((((~ n1ii1Ol) | (~ n1ii1Oi)) | (~ n1ii1lO)) | (~ n1ii1ll)), n000lO);
	and(wire_n0i1lO_dataout, ((n1iiiOO | (~ n1ii1OO)) | (~ (((~ n1iil0i) | n1iil1l) | n1iiiOO))), n000lO);
	assign		wire_n0ii_dataout = (nO === 1'b1) ? (~ pudi[13]) : pudi[13];
	and(wire_n0ii0i_dataout, n0i0iO, n000lO);
	and(wire_n0ii0l_dataout, n0i0li, n000lO);
	and(wire_n0ii0O_dataout, n1ii0ll, n000lO);
	and(wire_n0ii1i_dataout, ((n1iiO0O | (~ n1ii0li)) | (~ ((n1il10l | n1iiOii) | n1iiO0O))), n000lO);
	and(wire_n0ii1l_dataout, n0i0ii, n000lO);
	and(wire_n0ii1O_dataout, n0i0il, n000lO);
	and(wire_n0iiii_dataout, n1ii0Oi, n000lO);
	and(wire_n0iiil_dataout, ((((~ n1iii0i) | (~ n1iii1O)) | (~ n1iii1l)) | (~ n1iii1i)), n000lO);
	and(wire_n0iiiO_dataout, ((n1iiOOO | (~ n1iii0l)) | (~ (((~ n1il10i) | n1il11l) | n1iiOOO))), n000lO);
	assign		wire_n0il_dataout = (nO === 1'b1) ? (~ pudi[14]) : pudi[14];
	assign		wire_n0iO_dataout = (nO === 1'b1) ? (~ pudi[15]) : pudi[15];
	assign		wire_n0l_dataout = (wa_6g_en === 1'b1) ? nlliOli : nlOiO1i;
	assign		wire_n0li_dataout = (nO === 1'b1) ? (~ pudi[16]) : pudi[16];
	assign		wire_n0ll_dataout = (nO === 1'b1) ? (~ pudi[17]) : pudi[17];
	assign		wire_n0lO_dataout = (wa_6g_en === 1'b1) ? (((n010lil | n010lii) | (dwidth & n010l1l)) | (~ (n1iOOii8 ^ n1iOOii7))) : ((((n0001O | n0001l) | (~ (n1iOOll4 ^ n1iOOll3))) | (dwidth & n0011l)) | (~ (n1iOOiO6 ^ n1iOOiO5)));
	assign		wire_n0O_dataout = (wa_6g_en === 1'b1) ? nlliOll : nlOiO1l;
	assign		wire_n0Oi_dataout = (wa_6g_en === 1'b1) ? n1iOOOi : n1iOOOl;
	assign		wire_n0Ol_dataout = (wa_6g_en === 1'b1) ? nl0il0l : nlOiOii;
	assign		wire_n0OO_dataout = (wa_6g_en === 1'b1) ? nl00iil : niOi1i;
	assign		wire_n10i_dataout = (nO === 1'b1) ? (~ pudi[13]) : pudi[13];
	assign		wire_n10l_dataout = (nO === 1'b1) ? (~ pudi[14]) : pudi[14];
	assign		wire_n10O_dataout = (nO === 1'b1) ? (~ pudi[15]) : pudi[15];
	assign		wire_n11i_dataout = (nO === 1'b1) ? (~ pudi[10]) : pudi[10];
	assign		wire_n11i0l_dataout = (((((~ wire_nl1l1i_o) & n1i01ll) | (wire_nl1l1i_o & n1iliiO)) | (n1ill1i & n1iliOi)) === 1'b1) ? niO11i : (n1ilili | n1ilill);
	assign		wire_n11l_dataout = (nO === 1'b1) ? (~ pudi[11]) : pudi[11];
	assign		wire_n11O_dataout = (nO === 1'b1) ? (~ pudi[12]) : pudi[12];
	and(wire_n1i_dataout, nl00OiO, wa_6g_en);
	assign		wire_n1i1li_dataout = (((wire_nl1l0l_o ^ wire_nl1l0i_o) & n1ili0i) === 1'b1) ? wire_n11i0l_dataout : (n1ili0l | n1iliil);
	assign		wire_n1ii_dataout = (nO === 1'b1) ? (~ pudi[16]) : pudi[16];
	assign		wire_n1il_dataout = (nO === 1'b1) ? (~ pudi[17]) : pudi[17];
	assign		wire_n1iO_dataout = (nO === 1'b1) ? (~ pudi[18]) : pudi[18];
	assign		wire_n1l_dataout = (wa_6g_en === 1'b1) ? wire_nli101l_o : niO11l;
	assign		wire_n1l1O0l_dataout = (((((~ wire_nl010il_o) & nlOOl11O) | (wire_nl010il_o & nlOOl1ii)) | (nlOOl1lO & nlOOl1li)) === 1'b1) ? nl01lOO : (nlOOl1il | nlOOl1iO);
	assign		wire_n1li_dataout = (nO === 1'b1) ? (~ pudi[19]) : pudi[19];
	assign		wire_n1liili_dataout = (((wire_nl010lO_o ^ wire_nl010ll_o) & nlOOl00i) === 1'b1) ? wire_n1l1O0l_dataout : (nlOOl00l | nlOOl01O);
	assign		wire_n1ll_dataout = (nO === 1'b1) ? (~ pudi[0]) : pudi[0];
	assign		wire_n1lO_dataout = (nO === 1'b1) ? (~ pudi[1]) : pudi[1];
	and(wire_n1O_dataout, wire_nli101O_o, wa_6g_en);
	assign		wire_n1O010l_dataout = (((((~ wire_nl01i1O_o) & nlOOlllO) | (wire_nl01i1O_o & nlOOlO1i)) | (nlOOlO0O & nlOOlO0i)) === 1'b1) ? wire_n1liili_dataout : (nlOOlO1l | nlOOlO1O);
	assign		wire_n1O100i_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ nlOOllii) & ((~ ((nlOOlili | (nlOOliiO | nlOOliil)) | (nlOOliii | (nlOOli0O | (nlOOli0l | nlOOli0i))))) & (~ (((nlOOli1O | nlOOli1l) | ((~ (((nlOOli1i | nlOOl0OO) | (wire_nl010li_o & ((~ wire_nl010iO_o) & nlOOl0Ol))) | ((~ wire_nl010li_o) & (wire_nl010iO_o & nlOOl0Oi)))) & ((~ nlOOl0lO) & (((~ wire_nl010ll_o) & nlOOl0ll) | (wire_nl010ll_o & nlOOl0li))))) | ((((~ wire_nl010Ol_o) & nlOOl0ll) | (wire_nl010Ol_o & nlOOl0li)) & (nlOOl0OO | (nlOOli1i | nlOOl0lO))))))) : (~ ((((((((((((((nlOOllii | (nlOOll0O | nlOOll0l)) | ((~ wire_nl010li_o) & ((~ wire_nl010iO_o) & nlOOll0i))) | (wire_nl010li_o & (wire_nl010iO_o & nlOOll1O))) | ((wire_nl010Ol_o & (wire_nl010Oi_o & (wire_nl010lO_o & wire_nl010ll_o))) | ((~ wire_nl010Ol_o) & ((~ wire_nl010Oi_o) & ((~ wire_nl010lO_o) & (~ wire_nl010ll_o)))))) | ((~ wire_nl010Oi_o) & ((~ wire_nl010lO_o) & ((~ wire_nl010ll_o) & ((~ wire_nl010li_o) & (~ wire_nl010iO_o)))))) | (wire_nl010Oi_o & (wire_nl010lO_o & (wire_nl010ll_o & (wire_nl010li_o & wire_nl010iO_o))))) | ((~ wire_nl010Ol_o) & ((~ wire_nl010Oi_o) & ((~ wire_nl010lO_o) & nlOOll1l)))) | (wire_nl010Ol_o & (wire_nl010Oi_o & (wire_nl010lO_o & nlOOll1i)))) | ((((~ wire_nl010Ol_o) & ((~ wire_nl010Oi_o) & ((~ wire_nl010lO_o) & wire_nl010li_o))) | (wire_nl010Ol_o & (wire_nl010Oi_o & (wire_nl010lO_o & (~ wire_nl010li_o))))) & (~ nlOOliOO))) | (nlOOliOO & ((wire_nl010Oi_o & nlOOliOl) | ((~ wire_nl010Oi_o) & nlOOliOi)))) | (((~ wire_nl010Ol_o) & ((~ wire_nl010Oi_o) & ((~ wire_nl010lO_o) & nlOOll1i))) & (~ nlOOll1O))) | ((wire_nl010Ol_o & (wire_nl010Oi_o & (wire_nl010lO_o & nlOOll1l))) & (~ nlOOll0i))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nl010li_o) & ((~ wire_nl010iO_o) & nlOOlilO)) | nlOOll0l) | (((~ wire_nl010li_o) | (~ wire_nl010iO_o)) & nlOOll0i)) | ((~ wire_nl010li_o) & ((~ wire_nl010iO_o) & (~ wire_nl010il_o)))) & ((nlOOliOi | (nlOOliOi & nlOOlill)) | (nlOOlill & ((~ wire_nl010lO_o) | (~ wire_nl010ll_o))))))) | (r8b10b_dec_ibm_en[1]
 & (((((wire_nl010li_o & (wire_nl010iO_o & nlOOlilO)) | nlOOll0O) | ((wire_nl010li_o | wire_nl010iO_o) & nlOOll1O)) | (wire_nl010li_o & (wire_nl010iO_o & wire_nl010il_o))) & ((nlOOliOl | (nlOOliOl & (wire_nl010Ol_o | wire_nl010Oi_o))) | ((wire_nl010Ol_o & wire_nl010Oi_o) & (wire_nl010lO_o | wire_nl010ll_o)))))));
	assign		wire_n1Oi_dataout = (nO === 1'b1) ? (~ pudi[2]) : pudi[2];
	assign		wire_n1Oilli_dataout = (((wire_nl01iii_o ^ wire_nl01i0O_o) & nlOOlOOi) === 1'b1) ? wire_n1O010l_dataout : (nlOOlOOl | nlOOlOlO);
	assign		wire_n1Ol_dataout = (nO === 1'b1) ? (~ pudi[3]) : pudi[3];
	assign		wire_n1OO_dataout = (nO === 1'b1) ? (~ pudi[4]) : pudi[4];
	assign		wire_n1OOOi_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ n1i0ilO) & ((~ ((n1i00OO | (n1i00Ol | n1i00Oi)) | (n1ililO | (n1ill1O | (n1ill0i | n1ill1l))))) & (~ (((n1i00lO | n1ili0O) | ((~ (((n1il0ll | n1il0li) | n1il0il) | n1il0iO)) & ((~ n1i00ll) & (((~ wire_nl1l0i_o) & n1i00li) | (wire_nl1l0i_o & n1iliii))))) | ((((~ wire_nl1lii_dataout) & n1i00li) | (wire_nl1lii_dataout & n1iliii)) & (n1il0li | (n1il0ll | n1i00ll))))))) : (~ ((((((((((((((n1i0ilO | (n1i0ill | n1i0ili)) | ((~ wire_nl1l1O_o) & ((~ wire_nl1l1l_o) & n1i0iiO))) | (wire_nl1l1O_o & (wire_nl1l1l_o & n1i0iil))) | ((wire_nl1lii_dataout & (wire_nl1l0O_dataout & (wire_nl1l0l_o & wire_nl1l0i_o))) | ((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & (~ wire_nl1l0i_o)))))) | ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & ((~ wire_nl1l0i_o) & ((~ wire_nl1l1O_o) & (~ wire_nl1l1l_o)))))) | (wire_nl1l0O_dataout & (wire_nl1l0l_o & (wire_nl1l0i_o & (wire_nl1l1O_o & wire_nl1l1l_o))))) | ((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & n1i0iii)))) | (wire_nl1lii_dataout & (wire_nl1l0O_dataout & (wire_nl1l0l_o & n1i0i0O)))) | ((((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & wire_nl1l1O_o))) | (wire_nl1lii_dataout & (wire_nl1l0O_dataout & (wire_nl1l0l_o & (~ wire_nl1l1O_o))))) & (~ n1i0i0l))) | (n1i0i0l & ((wire_nl1l0O_dataout & n1i0i0i) | ((~ wire_nl1l0O_dataout) & n1i0i1O)))) | (((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & n1i0i0O))) & (~ n1i0iil))) | ((wire_nl1lii_dataout & (wire_nl1l0O_dataout & (wire_nl1l0l_o & n1i0iii))) & (~ n1i0iiO))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nl1l1O_o) & ((~ wire_nl1l1l_o) & n1i0i1l)) | n1i0ili) | (((~ wire_nl1l1O_o) | (~ wire_nl1l1l_o)) & n1i0iiO)) | ((~ wire_nl1l1O_o) & ((~ wire_nl1l1l_o) & (~ wire_nl1l1i_o)))) & ((n1i0i1O | (n1i0i1O & n1i0i1i)) | (n1i0i1i & ((~ wire_nl1l0l_o) | (~ wire_nl1l0i_o))))))) | (r8b10b_dec_ibm_en[1] & (((((wire_nl1l1O_o & (wire_nl1l1l_o & n1i0i1l)) | n1i0ill
) | ((wire_nl1l1O_o | wire_nl1l1l_o) & n1i0iil)) | (wire_nl1l1O_o & (wire_nl1l1l_o & wire_nl1l1i_o))) & ((n1i0i0i | (n1i0i0i & (wire_nl1lii_dataout | wire_nl1l0O_dataout))) | ((wire_nl1lii_dataout & wire_nl1l0O_dataout) & (wire_nl1l0l_o | wire_nl1l0i_o)))))));
	assign		wire_ni_dataout = (wa_6g_en === 1'b1) ? nl0i1iO : nlOiOii;
	assign		wire_ni0i_dataout = (wa_6g_en === 1'b1) ? nl00ilO : niOi0l;
	assign		wire_ni0l_dataout = (wa_6g_en === 1'b1) ? nl00iOi : niOi0O;
	assign		wire_ni0O_dataout = (wa_6g_en === 1'b1) ? nl00iOl : niOiii;
	assign		wire_ni1i_dataout = (wa_6g_en === 1'b1) ? nl00iiO : niOi1l;
	assign		wire_ni1l_dataout = (wa_6g_en === 1'b1) ? nl00ili : niOi1O;
	assign		wire_ni1O_dataout = (wa_6g_en === 1'b1) ? nl00ill : niOi0i;
	assign		wire_nii_dataout = (wa_6g_en === 1'b1) ? wire_n1l_dataout : nlOiO1O;
	assign		wire_niii_dataout = (wa_6g_en === 1'b1) ? nl00iOO : niOiil;
	and(wire_niiil_dataout, nii0O, ~(scan_mode));
	assign		wire_niil_dataout = (wa_6g_en === 1'b1) ? nl00l1i : niOiiO;
	assign		wire_niill_dataout = (wa_6g_en === 1'b1) ? nl00lii : niOiOO;
	assign		wire_niilO_dataout = (wa_6g_en === 1'b1) ? nl00lil : niOl1i;
	assign		wire_niiO_dataout = (wa_6g_en === 1'b1) ? nl00l1l : niOili;
	and(wire_niiOi_dataout, nl00Oil, wa_6g_en);
	and(wire_niiOl_dataout, nl00OiO, wa_6g_en);
	assign		wire_niiOO_dataout = (nO === 1'b1) ? (~ pudr[0]) : pudr[0];
	assign		wire_nil_dataout = (wa_6g_en === 1'b1) ? wire_n1O_dataout : nl0i0O;
	assign		wire_nil0i_dataout = (nO === 1'b1) ? (~ pudr[4]) : pudr[4];
	assign		wire_nil0l_dataout = (nO === 1'b1) ? (~ pudr[5]) : pudr[5];
	assign		wire_nil0O_dataout = (nO === 1'b1) ? (~ pudr[6]) : pudr[6];
	assign		wire_nil1i_dataout = (nO === 1'b1) ? (~ pudr[1]) : pudr[1];
	assign		wire_nil1l_dataout = (nO === 1'b1) ? (~ pudr[2]) : pudr[2];
	assign		wire_nil1O_dataout = (nO === 1'b1) ? (~ pudr[3]) : pudr[3];
	assign		wire_nili_dataout = (wa_6g_en === 1'b1) ? nl00l1O : niOill;
	assign		wire_nilii_dataout = (nO === 1'b1) ? (~ pudr[7]) : pudr[7];
	assign		wire_nilil_dataout = (nO === 1'b1) ? (~ pudr[8]) : pudr[8];
	assign		wire_niliO_dataout = (nO === 1'b1) ? (~ pudr[9]) : pudr[9];
	assign		wire_nill_dataout = (wa_6g_en === 1'b1) ? nl00l0i : niOilO;
	assign		wire_nilli_dataout = (nO === 1'b1) ? (~ pudi[0]) : pudi[0];
	assign		wire_nilll_dataout = (nO === 1'b1) ? (~ pudi[1]) : pudi[1];
	assign		wire_nillO_dataout = (nO === 1'b1) ? (~ pudi[2]) : pudi[2];
	assign		wire_nilO_dataout = (wa_6g_en === 1'b1) ? nl00l0l : niOiOi;
	assign		wire_nilOi_dataout = (nO === 1'b1) ? (~ pudi[3]) : pudi[3];
	assign		wire_nilOl_dataout = (nO === 1'b1) ? (~ pudi[4]) : pudi[4];
	assign		wire_nilOO_dataout = (nO === 1'b1) ? (~ pudi[5]) : pudi[5];
	assign		wire_niO_dataout = (wa_6g_en === 1'b1) ? nl0i10l : nl0iii;
	assign		wire_niO00l_dataout = (n1il0lO === 1'b1) ? (n1il0Ol | n1il0Oi) : (n1ili1i | n1il0OO);
	assign		wire_niO0i_dataout = (nO === 1'b1) ? (~ pudi[9]) : pudi[9];
	assign		wire_niO0l_dataout = (n1iOO0l === 1'b1) ? wire_nl0OO_dataout : wire_nl1li_dataout;
	assign		wire_niO0O_dataout = (n1iOO0l === 1'b1) ? wire_nli1i_dataout : wire_nl1ll_dataout;
	assign		wire_niO1i_dataout = (nO === 1'b1) ? (~ pudi[6]) : pudi[6];
	assign		wire_niO1l_dataout = (nO === 1'b1) ? (~ pudi[7]) : pudi[7];
	assign		wire_niO1O_dataout = (nO === 1'b1) ? (~ pudi[8]) : pudi[8];
	assign		wire_niOi_dataout = (wa_6g_en === 1'b1) ? nl00l0O : niOiOl;
	assign		wire_niOii_dataout = (n1iOO0l === 1'b1) ? wire_nli1l_dataout : wire_nl1lO_dataout;
	assign		wire_niOil_dataout = (n1iOO0l === 1'b1) ? wire_nli1O_dataout : wire_nl1Oi_dataout;
	assign		wire_niOiO_dataout = (n1iOO0l === 1'b1) ? wire_nli0i_dataout : wire_nl1Ol_dataout;
	assign		wire_niOl_dataout = (wa_6g_en === 1'b1) ? nl00lii : niOiOO;
	assign		wire_niOli_dataout = (n1iOO0l === 1'b1) ? wire_nli0l_dataout : wire_nl1OO_dataout;
	assign		wire_niOll_dataout = (n1iOO0l === 1'b1) ? wire_nli0O_dataout : wire_nl01i_dataout;
	assign		wire_niOlO_dataout = (n1iOO0l === 1'b1) ? wire_nliii_dataout : wire_nl01l_dataout;
	assign		wire_niOO_dataout = (wa_6g_en === 1'b1) ? nl00lil : niOl1i;
	assign		wire_niOOi_dataout = (n1iOO0l === 1'b1) ? wire_nliil_dataout : wire_nl01O_dataout;
	and(wire_niOOii_dataout, ((niO0ll | n1ili1l) | (dwidth & niO0il)), n1iOiOi);
	assign		wire_niOOil_dataout = (n1iOiOi === 1'b1) ? ((niO0lO | n1ili1O) | (dwidth & niO0iO)) : ((niO0li | wire_niO00l_dataout) | (dwidth & niO11O));
	assign		wire_niOOl_dataout = (n1iOO0l === 1'b1) ? wire_nliiO_dataout : wire_nl00i_dataout;
	assign		wire_niOOO_dataout = (n1iOO0l === 1'b1) ? wire_nlili_dataout : wire_nl00l_dataout;
	assign		wire_nl0000i_dataout = (nllO1li === 1'b1) ? nl0i0OO : nl0iiii;
	assign		wire_nl0001i_dataout = (nllO1li === 1'b1) ? nl0ii1O : nl0ii0i;
	assign		wire_nl0001l_dataout = (nllO1li === 1'b1) ? nl0ii1l : nl0ii0l;
	assign		wire_nl0001O_dataout = (nllO1li === 1'b1) ? nl0ii1i : nl0ii0O;
	and(wire_nl000i_dataout, wire_nl000l_o[4], ~(n1illOl));
	assign		wire_nl0010i_dataout = (nllO1li === 1'b1) ? nl0iiii : nl0ii1l;
	assign		wire_nl0010l_dataout = (nllO1li === 1'b1) ? nl0ii0O : nl0ii1O;
	assign		wire_nl0010O_dataout = (nllO1li === 1'b1) ? nl0ii0l : nl0ii0i;
	assign		wire_nl0011l_dataout = (nllO1li === 1'b1) ? nl0iiiO : nl0i0OO;
	assign		wire_nl0011O_dataout = (nllO1li === 1'b1) ? nl0iiil : nl0ii1i;
	or(wire_nl001i_dataout, wire_nl000l_o[1], n1illOl);
	assign		wire_nl001ii_dataout = (nllO1li === 1'b1) ? nl0ii0i : nl0ii0l;
	assign		wire_nl001il_dataout = (nllO1li === 1'b1) ? nl0ii1O : nl0ii0O;
	assign		wire_nl001iO_dataout = (nllO1li === 1'b1) ? nl0ii1l : nl0iiii;
	or(wire_nl001l_dataout, wire_nl000l_o[2], n1illOl);
	assign		wire_nl001li_dataout = (nllO1li === 1'b1) ? nl0ii1i : nl0iiil;
	assign		wire_nl001ll_dataout = (nllO1li === 1'b1) ? nl0i0OO : nl0iiiO;
	assign		wire_nl001lO_dataout = (nllO1li === 1'b1) ? nl0iiii : nl0i0OO;
	or(wire_nl001O_dataout, wire_nl000l_o[3], n1illOl);
	assign		wire_nl001Oi_dataout = (nllO1li === 1'b1) ? nl0ii0O : nl0ii1i;
	assign		wire_nl001Ol_dataout = (nllO1li === 1'b1) ? nl0ii0l : nl0ii1l;
	assign		wire_nl001OO_dataout = (nllO1li === 1'b1) ? nl0ii0i : nl0ii1O;
	assign		wire_nl00i_dataout = (nO === 1'b1) ? (~ pudr[9]) : pudr[9];
	assign		wire_nl00l_dataout = (nO === 1'b1) ? (~ pudr[10]) : pudr[10];
	assign		wire_nl00O_dataout = (nO === 1'b1) ? (~ pudr[11]) : pudr[11];
	assign		wire_nl01i_dataout = (nO === 1'b1) ? (~ pudr[6]) : pudr[6];
	assign		wire_nl01l_dataout = (nO === 1'b1) ? (~ pudr[7]) : pudr[7];
	or(wire_nl01lO_dataout, wire_nl001i_dataout, n1illOO);
	assign		wire_nl01O_dataout = (nO === 1'b1) ? (~ pudr[8]) : pudr[8];
	and(wire_nl01Oi_dataout, wire_nl001l_dataout, ~(n1illOO));
	and(wire_nl01Ol_dataout, wire_nl001O_dataout, ~(n1illOO));
	or(wire_nl01OO_dataout, wire_nl000i_dataout, n1illOO);
	and(wire_nl0i_dataout, nl00llO, wa_6g_en);
	assign		wire_nl0ii_dataout = (nO === 1'b1) ? (~ pudr[12]) : pudr[12];
	assign		wire_nl0il_dataout = (nO === 1'b1) ? (~ pudr[13]) : pudr[13];
	assign		wire_nl0il0O_dataout = (n11l1OO === 1'b1) ? wire_nl0llli_o : wire_nl0iOll_dataout;
	assign		wire_nl0ilii_dataout = (n11l1OO === 1'b1) ? wire_nl0llll_o : wire_nl0iOlO_dataout;
	assign		wire_nl0ilil_dataout = (n11l1OO === 1'b1) ? wire_nl0lllO_o : wire_nl0iOOi_dataout;
	assign		wire_nl0iliO_dataout = (n11l1OO === 1'b1) ? wire_nl0llOi_o : wire_nl0iOOl_dataout;
	assign		wire_nl0illi_dataout = (n11l1OO === 1'b1) ? wire_nl0llOl_o : wire_nl0iOOO_dataout;
	assign		wire_nl0illl_dataout = (n11l1OO === 1'b1) ? wire_nl0llOO_o : wire_nl0l11i_dataout;
	assign		wire_nl0illO_dataout = (n11l1OO === 1'b1) ? wire_nl0lO1i_o : wire_nl0l11l_dataout;
	assign		wire_nl0ilOi_dataout = (n11l1OO === 1'b1) ? wire_nl0lO1l_o : wire_nl0l11O_dataout;
	assign		wire_nl0ilOl_dataout = (n11l1OO === 1'b1) ? wire_nl0lO1O_o : wire_nl0l10i_dataout;
	assign		wire_nl0ilOO_dataout = (n11l1OO === 1'b1) ? wire_nl0lO0i_o : wire_nl0l10l_dataout;
	assign		wire_nl0iO_dataout = (nO === 1'b1) ? (~ pudr[14]) : pudr[14];
	assign		wire_nl0iO0i_dataout = (n11l1OO === 1'b1) ? wire_nl0lOil_o : wire_nl0l1iO_dataout;
	assign		wire_nl0iO0l_dataout = (n11l1OO === 1'b1) ? wire_nl0lOiO_o : wire_nl0l1li_dataout;
	assign		wire_nl0iO0O_dataout = (n11l1OO === 1'b1) ? wire_nl0lOli_o : wire_nl0l1ll_dataout;
	assign		wire_nl0iO1i_dataout = (n11l1OO === 1'b1) ? wire_nl0lO0l_o : wire_nl0l10O_dataout;
	assign		wire_nl0iO1l_dataout = (n11l1OO === 1'b1) ? wire_nl0lO0O_o : wire_nl0l1ii_dataout;
	assign		wire_nl0iO1O_dataout = (n11l1OO === 1'b1) ? wire_nl0lOii_o : wire_nl0l1il_dataout;
	assign		wire_nl0iOii_dataout = (n11l1OO === 1'b1) ? wire_nl0lOll_o : wire_nl0l1lO_dataout;
	assign		wire_nl0iOil_dataout = (n11l1OO === 1'b1) ? wire_nl0lOlO_o : wire_nl0l1Oi_dataout;
	assign		wire_nl0iOiO_dataout = (n11l1OO === 1'b1) ? wire_nl0lOOi_o : wire_nl0l1Ol_dataout;
	assign		wire_nl0iOli_dataout = (n11l1OO === 1'b1) ? wire_nl0lOOl_o : wire_nl0l1OO_dataout;
	assign		wire_nl0iOll_dataout = (n11l1Ol === 1'b1) ? wire_nl0liil_o : wire_nl0l01i_dataout;
	assign		wire_nl0iOlO_dataout = (n11l1Ol === 1'b1) ? wire_nl0liiO_o : wire_nl0l01l_dataout;
	assign		wire_nl0iOOi_dataout = (n11l1Ol === 1'b1) ? wire_nl0lili_o : wire_nl0l01O_dataout;
	assign		wire_nl0iOOl_dataout = (n11l1Ol === 1'b1) ? wire_nl0lill_o : wire_nl0l00i_dataout;
	assign		wire_nl0iOOO_dataout = (n11l1Ol === 1'b1) ? wire_nl0lilO_o : wire_nl0l00l_dataout;
	and(wire_nl0l_dataout, nl00lOi, wa_6g_en);
	assign		wire_nl0l00i_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0llOl_o : wire_nl0lilO_o;
	assign		wire_nl0l00l_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0llOO_o : wire_nl0liOi_o;
	assign		wire_nl0l00O_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lO1i_o : wire_nl0liOl_o;
	assign		wire_nl0l01i_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0llll_o : wire_nl0liiO_o;
	assign		wire_nl0l01l_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lllO_o : wire_nl0lili_o;
	assign		wire_nl0l01O_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0llOi_o : wire_nl0lill_o;
	assign		wire_nl0l0ii_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lO1l_o : wire_nl0liOO_o;
	assign		wire_nl0l0il_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lO1O_o : wire_nl0ll1i_o;
	assign		wire_nl0l0iO_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lO0i_o : wire_nl0ll1l_o;
	assign		wire_nl0l0li_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lO0l_o : wire_nl0ll1O_o;
	assign		wire_nl0l0ll_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lO0O_o : wire_nl0ll0i_o;
	assign		wire_nl0l0lO_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lOii_o : wire_nl0ll0l_o;
	assign		wire_nl0l0Oi_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lOil_o : wire_nl0ll0O_o;
	assign		wire_nl0l0Ol_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lOiO_o : wire_nl0llii_o;
	assign		wire_nl0l0OO_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lOli_o : wire_nl0llil_o;
	assign		wire_nl0l10i_dataout = (n11l1Ol === 1'b1) ? wire_nl0ll1i_o : wire_nl0l0iO_dataout;
	assign		wire_nl0l10l_dataout = (n11l1Ol === 1'b1) ? wire_nl0ll1l_o : wire_nl0l0li_dataout;
	assign		wire_nl0l10O_dataout = (n11l1Ol === 1'b1) ? wire_nl0ll1O_o : wire_nl0l0ll_dataout;
	assign		wire_nl0l11i_dataout = (n11l1Ol === 1'b1) ? wire_nl0liOi_o : wire_nl0l00O_dataout;
	assign		wire_nl0l11l_dataout = (n11l1Ol === 1'b1) ? wire_nl0liOl_o : wire_nl0l0ii_dataout;
	assign		wire_nl0l11O_dataout = (n11l1Ol === 1'b1) ? wire_nl0liOO_o : wire_nl0l0il_dataout;
	assign		wire_nl0l1ii_dataout = (n11l1Ol === 1'b1) ? wire_nl0ll0i_o : wire_nl0l0lO_dataout;
	assign		wire_nl0l1il_dataout = (n11l1Ol === 1'b1) ? wire_nl0ll0l_o : wire_nl0l0Oi_dataout;
	assign		wire_nl0l1iO_dataout = (n11l1Ol === 1'b1) ? wire_nl0ll0O_o : wire_nl0l0Ol_dataout;
	assign		wire_nl0l1li_dataout = (n11l1Ol === 1'b1) ? wire_nl0llii_o : wire_nl0l0OO_dataout;
	assign		wire_nl0l1ll_dataout = (n11l1Ol === 1'b1) ? wire_nl0llil_o : wire_nl0li1i_dataout;
	and(wire_nl0l1lO_dataout, wire_nl0li1l_dataout, ~(n11l1Ol));
	and(wire_nl0l1Oi_dataout, wire_nl0li1O_dataout, ~(n11l1Ol));
	and(wire_nl0l1Ol_dataout, wire_nl0li0i_dataout, ~(n11l1Ol));
	and(wire_nl0l1OO_dataout, wire_nl0li0l_dataout, ~(n11l1Ol));
	assign		wire_nl0li_dataout = (nO === 1'b1) ? (~ pudr[15]) : pudr[15];
	and(wire_nl0li0i_dataout, wire_nl0lOOl_o, (~ comp_pat_size[0]));
	and(wire_nl0li0l_dataout, wire_nl0liii_o, (~ comp_pat_size[0]));
	assign		wire_nl0li1i_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0lOll_o : wire_nl0li0O_o;
	and(wire_nl0li1l_dataout, wire_nl0lOlO_o, (~ comp_pat_size[0]));
	and(wire_nl0li1O_dataout, wire_nl0lOOi_o, (~ comp_pat_size[0]));
	assign		wire_nl0ll_dataout = (nO === 1'b1) ? (~ pudr[16]) : pudr[16];
	assign		wire_nl0llO_dataout = (autobytealign_dis === 1'b1) ? nl010l : nl0i0O;
	assign		wire_nl0lO_dataout = (nO === 1'b1) ? (~ pudr[17]) : pudr[17];
	assign		wire_nl0lOi_dataout = (autobytealign_dis === 1'b1) ? nl01ii : nl0iii;
	assign		wire_nl0lOl_dataout = (autobytealign_dis === 1'b1) ? nl01il : nl0iil;
	assign		wire_nl0lOO_dataout = (autobytealign_dis === 1'b1) ? nl01li : nl0ili;
	and(wire_nl0O_dataout, nl00lOl, wa_6g_en);
	assign		wire_nl0O00O_dataout = (nllO10i === 1'b1) ? wire_nl0O0ll_dataout : nl0i10l;
	assign		wire_nl0O0ii_dataout = (nllO10i === 1'b1) ? wire_nl0O0lO_dataout : nl0i10O;
	assign		wire_nl0O0il_dataout = (nllO10i === 1'b1) ? wire_nl0O0Oi_dataout : nl0i1ii;
	assign		wire_nl0O0iO_dataout = (nllO10i === 1'b1) ? wire_nl0O0Ol_dataout : nl0i1il;
	assign		wire_nl0O0l_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl00il) & (n1iO10i & nlOOl0i)) | (nl00il & (n1iO10i & (nlOO1ll & (~ nlOO1li))))) : (n1iO10l | n1iO10i);
	assign		wire_nl0O0li_dataout = (nllO10i === 1'b1) ? wire_nl0O0OO_dataout : nl0i1iO;
	and(wire_nl0O0ll_dataout, wire_nl0Oi1i_o[0], ~(wire_nl0Oi1l_o));
	and(wire_nl0O0lO_dataout, wire_nl0Oi1i_o[1], ~(wire_nl0Oi1l_o));
	and(wire_nl0O0Oi_dataout, wire_nl0Oi1i_o[2], ~(wire_nl0Oi1l_o));
	and(wire_nl0O0Ol_dataout, wire_nl0Oi1i_o[3], ~(wire_nl0Oi1l_o));
	and(wire_nl0O0OO_dataout, wire_nl0Oi1i_o[4], ~(wire_nl0Oi1l_o));
	assign		wire_nl0O10i_dataout = (n11l01O === 1'b1) ? n11lOlO : wire_nl0O1iO_dataout;
	assign		wire_nl0O10l_dataout = (n11l01O === 1'b1) ? n11lOOi : wire_nl0O1li_dataout;
	assign		wire_nl0O10O_dataout = (n11l01l === 1'b1) ? wire_nl0O1ll_dataout : nl0i10l;
	assign		wire_nl0O11i_dataout = (n11l01O === 1'b1) ? (~ n11lOiO) : wire_nl0O10O_dataout;
	assign		wire_nl0O11l_dataout = (n11l01O === 1'b1) ? (~ n11lOli) : wire_nl0O1ii_dataout;
	assign		wire_nl0O11O_dataout = (n11l01O === 1'b1) ? n11lOll : wire_nl0O1il_dataout;
	and(wire_nl0O1i_dataout, (n1iO11i | n1ilOOO), ~((~ pmadwidth[0])));
	assign		wire_nl0O1ii_dataout = (n11l01l === 1'b1) ? wire_nl0O1lO_dataout : nl0i10O;
	assign		wire_nl0O1il_dataout = (n11l01l === 1'b1) ? wire_nl0O1Oi_dataout : nl0i1ii;
	assign		wire_nl0O1iO_dataout = (n11l01l === 1'b1) ? wire_nl0O1Ol_dataout : nl0i1il;
	assign		wire_nl0O1li_dataout = (n11l01l === 1'b1) ? wire_nl0O1OO_dataout : nl0i1iO;
	and(wire_nl0O1ll_dataout, wire_nl0O01i_o, ~(n11l01i));
	and(wire_nl0O1lO_dataout, wire_nl0O01l_o, ~(n11l01i));
	and(wire_nl0O1O_dataout, (n1iO11O | n1iO11l), ~((~ pmadwidth[0])));
	and(wire_nl0O1Oi_dataout, wire_nl0O01O_o, ~(n11l01i));
	and(wire_nl0O1Ol_dataout, wire_nl0O00i_o, ~(n11l01i));
	and(wire_nl0O1OO_dataout, wire_nl0O00l_o, ~(n11l01i));
	assign		wire_nl0Oi_dataout = (nO === 1'b1) ? (~ pudr[18]) : pudr[18];
	assign		wire_nl0Oi0i_dataout = (nllO10i === 1'b1) ? wire_nl0OiiO_dataout : nl0i10O;
	assign		wire_nl0Oi0l_dataout = (nllO10i === 1'b1) ? wire_nl0Oili_dataout : nl0i1ii;
	assign		wire_nl0Oi0O_dataout = (nllO10i === 1'b1) ? wire_nl0Oill_dataout : nl0i1il;
	assign		wire_nl0Oi1O_dataout = (nllO10i === 1'b1) ? wire_nl0Oiil_dataout : nl0i10l;
	assign		wire_nl0Oiii_dataout = (nllO10i === 1'b1) ? wire_nl0OilO_dataout : nl0i1iO;
	and(wire_nl0Oiil_dataout, wire_nl0Oi1i_o[0], ~(wire_nl0OiOi_o));
	and(wire_nl0OiiO_dataout, wire_nl0Oi1i_o[1], ~(wire_nl0OiOi_o));
	assign		wire_nl0Oil_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl00il) & (n1iO10O & nlOOl1O)) | (nl00il & (n1iO10O & (nlOO1Oi & (~ nlOO1lO))))) : (n1iO1ii | n1iO10O);
	and(wire_nl0Oili_dataout, wire_nl0Oi1i_o[2], ~(wire_nl0OiOi_o));
	and(wire_nl0Oill_dataout, wire_nl0Oi1i_o[3], ~(wire_nl0OiOi_o));
	and(wire_nl0OilO_dataout, wire_nl0Oi1i_o[4], ~(wire_nl0OiOi_o));
	assign		wire_nl0OiOl_dataout = (nllO10i === 1'b1) ? wire_nl0Ol0i_dataout : nl0i10l;
	assign		wire_nl0OiOO_dataout = (nllO10i === 1'b1) ? wire_nl0Ol0l_dataout : nl0i10O;
	assign		wire_nl0Ol_dataout = (nO === 1'b1) ? (~ pudr[19]) : pudr[19];
	and(wire_nl0Ol0i_dataout, wire_nl0Oi1i_o[0], ~(wire_nl0OliO_o));
	and(wire_nl0Ol0l_dataout, wire_nl0Oi1i_o[1], ~(wire_nl0OliO_o));
	and(wire_nl0Ol0O_dataout, wire_nl0Oi1i_o[2], ~(wire_nl0OliO_o));
	assign		wire_nl0Ol1i_dataout = (nllO10i === 1'b1) ? wire_nl0Ol0O_dataout : nl0i1ii;
	assign		wire_nl0Ol1l_dataout = (nllO10i === 1'b1) ? wire_nl0Olii_dataout : nl0i1il;
	assign		wire_nl0Ol1O_dataout = (nllO10i === 1'b1) ? wire_nl0Olil_dataout : nl0i1iO;
	and(wire_nl0Olii_dataout, wire_nl0Oi1i_o[3], ~(wire_nl0OliO_o));
	and(wire_nl0Olil_dataout, wire_nl0Oi1i_o[4], ~(wire_nl0OliO_o));
	assign		wire_nl0Oll_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl00il) & (n1iO1il & nlOOl1l)) | (nl00il & (n1iO1il & (nlOO1OO & (~ nlOO1Ol))))) : (n1iO1iO | n1iO1il);
	assign		wire_nl0Olli_dataout = (nllO10i === 1'b1) ? wire_nl0OlOO_dataout : nl0i10l;
	assign		wire_nl0Olll_dataout = (nllO10i === 1'b1) ? wire_nl0OO1i_dataout : nl0i10O;
	assign		wire_nl0OllO_dataout = (nllO10i === 1'b1) ? wire_nl0OO1l_dataout : nl0i1ii;
	assign		wire_nl0OlOi_dataout = (nllO10i === 1'b1) ? wire_nl0OO1O_dataout : nl0i1il;
	assign		wire_nl0OlOl_dataout = (nllO10i === 1'b1) ? wire_nl0OO0i_dataout : nl0i1iO;
	and(wire_nl0OlOO_dataout, wire_nl0Oi1i_o[0], ~(wire_nl0OO0l_o));
	assign		wire_nl0OO_dataout = (nO === 1'b1) ? (~ pudr[0]) : pudr[0];
	and(wire_nl0OO0i_dataout, wire_nl0Oi1i_o[4], ~(wire_nl0OO0l_o));
	and(wire_nl0OO1i_dataout, wire_nl0Oi1i_o[1], ~(wire_nl0OO0l_o));
	and(wire_nl0OO1l_dataout, wire_nl0Oi1i_o[2], ~(wire_nl0OO0l_o));
	and(wire_nl0OO1O_dataout, wire_nl0Oi1i_o[3], ~(wire_nl0OO0l_o));
	assign		wire_nl0OOiO_dataout = (sync_sm_dis === 1'b1) ? wire_nl0OOli_dataout : wire_nli110O_dataout;
	assign		wire_nl0OOl_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl00il) & (n1iO1li & nlOOl1i)) | (nl00il & (n1iO1li & (nlOO01l & (~ nlOO01i))))) : (n1iO1ll | n1iO1li);
	and(wire_nl0OOli_dataout, nl0000l, ((n11lOil | n11lOii) | n11lO0O));
	assign		wire_nl0OOOl_dataout = (comp_pat_size[0] === 1'b1) ? ((n11llOl | nl00i0O) | (dwidth & nl000Oi)) : n11liii;
	assign		wire_nl0OOOO_dataout = (comp_pat_size[0] === 1'b1) ? ((n11llil | nl00i0i) | (dwidth & nl000ll)) : wire_nli111i_dataout;
	assign		wire_nl100i_dataout = (n1ill0l === 1'b1) ? niOliO : wire_nl1l0l_o;
	assign		wire_nl100l_dataout = (n1ill0l === 1'b1) ? niOlli : wire_nl1l0O_dataout;
	and(wire_nl100O_dataout, wire_nl1lii_dataout, ~(n1ill0l));
	assign		wire_nl101i_dataout = (n1ill0l === 1'b1) ? niOl0O : wire_nl1l1l_o;
	assign		wire_nl101l_dataout = (n1ill0l === 1'b1) ? niOlii : wire_nl1l1O_o;
	assign		wire_nl101O_dataout = (n1ill0l === 1'b1) ? niOlil : wire_nl1l0i_o;
	assign		wire_nl10i_dataout = (n1iOO0l === 1'b1) ? wire_nliOl_dataout : wire_nl0iO_dataout;
	assign		wire_nl10l_dataout = (n1iOO0l === 1'b1) ? wire_nliOO_dataout : wire_nl0li_dataout;
	assign		wire_nl10ll_dataout = (n1illii === 1'b1) ? comp_pat[0] : niOlll;
	assign		wire_nl10lO_dataout = (n1illii === 1'b1) ? comp_pat[1] : niOllO;
	and(wire_nl10O_dataout, wire_nl0ll_dataout, ~(n1iOO0l));
	assign		wire_nl10Oi_dataout = (n1illii === 1'b1) ? comp_pat[2] : niOlOi;
	assign		wire_nl10Ol_dataout = (n1illii === 1'b1) ? comp_pat[3] : niOlOl;
	assign		wire_nl10OO_dataout = (n1illii === 1'b1) ? comp_pat[4] : niOlOO;
	assign		wire_nl110i_dataout = (n1ill0O === 1'b1) ? comp_pat[2] : wire_nl11Ol_dataout;
	assign		wire_nl110l_dataout = (n1ill0O === 1'b1) ? comp_pat[3] : wire_nl11OO_dataout;
	assign		wire_nl110O_dataout = (n1ill0O === 1'b1) ? comp_pat[4] : wire_nl101i_dataout;
	assign		wire_nl111l_dataout = (n1ill0O === 1'b1) ? comp_pat[0] : wire_nl11lO_dataout;
	assign		wire_nl111O_dataout = (n1ill0O === 1'b1) ? comp_pat[1] : wire_nl11Oi_dataout;
	assign		wire_nl11i_dataout = (n1iOO0l === 1'b1) ? wire_nlill_dataout : wire_nl00O_dataout;
	assign		wire_nl11ii_dataout = (n1ill0O === 1'b1) ? comp_pat[5] : wire_nl101l_dataout;
	assign		wire_nl11il_dataout = (n1ill0O === 1'b1) ? comp_pat[6] : wire_nl101O_dataout;
	assign		wire_nl11iO_dataout = (n1ill0O === 1'b1) ? comp_pat[7] : wire_nl100i_dataout;
	assign		wire_nl11l_dataout = (n1iOO0l === 1'b1) ? wire_nlilO_dataout : wire_nl0ii_dataout;
	assign		wire_nl11li_dataout = (n1ill0O === 1'b1) ? niOlli : wire_nl100l_dataout;
	and(wire_nl11ll_dataout, wire_nl100O_dataout, ~(n1ill0O));
	assign		wire_nl11lO_dataout = (n1ill0l === 1'b1) ? niOl1l : wire_nl1iOi_o;
	assign		wire_nl11O_dataout = (n1iOO0l === 1'b1) ? wire_nliOi_dataout : wire_nl0il_dataout;
	assign		wire_nl11Oi_dataout = (n1ill0l === 1'b1) ? niOl1O : wire_nl1iOl_o;
	assign		wire_nl11Ol_dataout = (n1ill0l === 1'b1) ? niOl0i : wire_nl1iOO_o;
	assign		wire_nl11OO_dataout = (n1ill0l === 1'b1) ? niOl0l : wire_nl1l1i_o;
	and(wire_nl1i_dataout, nl00liO, wa_6g_en);
	assign		wire_nl1i1i_dataout = (n1illii === 1'b1) ? comp_pat[5] : niOO1i;
	assign		wire_nl1i1l_dataout = (n1illii === 1'b1) ? comp_pat[6] : niOO1l;
	assign		wire_nl1i1O_dataout = (n1illii === 1'b1) ? comp_pat[7] : niOO1O;
	and(wire_nl1ii_dataout, wire_nl0lO_dataout, ~(n1iOO0l));
	and(wire_nl1il_dataout, wire_nl0Oi_dataout, ~(n1iOO0l));
	and(wire_nl1iO_dataout, wire_nl0Ol_dataout, ~(n1iOO0l));
	and(wire_nl1l_dataout, nl00lli, wa_6g_en);
	assign		wire_nl1l0O_dataout = (n1illlO === 1'b1) ? nl1llO : nl1O0i;
	assign		wire_nl1li_dataout = (nO === 1'b1) ? (~ pudr[0]) : pudr[0];
	assign		wire_nl1lii_dataout = (n1illlO === 1'b1) ? nl1lli : nl1O0l;
	assign		wire_nl1ll_dataout = (nO === 1'b1) ? (~ pudr[1]) : pudr[1];
	assign		wire_nl1lO_dataout = (nO === 1'b1) ? (~ pudr[2]) : pudr[2];
	and(wire_nl1O_dataout, nl00lll, wa_6g_en);
	assign		wire_nl1Oi_dataout = (nO === 1'b1) ? (~ pudr[3]) : pudr[3];
	assign		wire_nl1Ol_dataout = (nO === 1'b1) ? (~ pudr[4]) : pudr[4];
	assign		wire_nl1OO_dataout = (nO === 1'b1) ? (~ pudr[5]) : pudr[5];
	assign		wire_nli_dataout = (wa_6g_en === 1'b1) ? nl0i10O : nl0iil;
	assign		wire_nli00i_dataout = (n1iOilO === 1'b1) ? nlll0O : wire_nli0Ol_dataout;
	assign		wire_nli00l_dataout = (n1iOilO === 1'b1) ? nlllii : wire_nli0OO_dataout;
	and(wire_nli00O_dataout, wire_nlii1i_dataout, ~(n1iOilO));
	assign		wire_nli01i_dataout = (n1iOilO === 1'b1) ? nlll1O : wire_nli0ll_dataout;
	assign		wire_nli01l_dataout = (n1iOilO === 1'b1) ? nlll0i : wire_nli0lO_dataout;
	assign		wire_nli01O_dataout = (n1iOilO === 1'b1) ? nlll0l : wire_nli0Oi_dataout;
	assign		wire_nli0i_dataout = (nO === 1'b1) ? (~ pudr[4]) : pudr[4];
	and(wire_nli0ii_dataout, wire_nlii1l_dataout, ~(n1iOilO));
	and(wire_nli0il_dataout, wire_nlii1O_dataout, ~(n1iOilO));
	and(wire_nli0iO_dataout, nlll1i, ~(n1iOiOi));
	assign		wire_nli0l_dataout = (nO === 1'b1) ? (~ pudr[5]) : pudr[5];
	and(wire_nli0li_dataout, nlll1l, ~(n1iOiOi));
	and(wire_nli0ll_dataout, nlll1O, ~(n1iOiOi));
	and(wire_nli0lO_dataout, nlll0i, ~(n1iOiOi));
	assign		wire_nli0O_dataout = (nO === 1'b1) ? (~ pudr[6]) : pudr[6];
	and(wire_nli0Oi_dataout, nlll0l, ~(n1iOiOi));
	and(wire_nli0Ol_dataout, nlll0O, ~(n1iOiOi));
	and(wire_nli0OO_dataout, nlllii, ~(n1iOiOi));
	assign		wire_nli10l_dataout = ((~ pmadwidth[0]) === 1'b1) ? ((((~ nl00il) & (n1iO0iO & nlOOiOl)) | (nl00il & ((n1iO0iO & ((nlOO00O & (~ nlOO00l)) & (n1iO0ii40 ^ n1iO0ii39))) & (n1iO00l42 ^ n1iO00l41)))) | (~ (n1iO01O44 ^ n1iO01O43))) : (n1iO0li | n1iO0iO);
	and(wire_nli110i_dataout, nl0100i, n11l00i);
	assign		wire_nli110O_dataout = (n11l00i === 1'b1) ? nl0000O : nl0il0l;
	assign		wire_nli111i_dataout = (n11l00l === 1'b1) ? n11liii : ((n11lill | nl000OO) | (dwidth & nl000ii));
	assign		wire_nli111l_dataout = (sync_sm_dis === 1'b1) ? wire_nli111O_dataout : wire_nli110O_dataout;
	assign		wire_nli111O_dataout = ((n11lO0l | n11lO0i) === 1'b1) ? nl0000l : wire_nli110i_dataout;
	assign		wire_nli11iO_dataout = (comp_pat_size[0] === 1'b1) ? ((n11llll | nl00iii) | (dwidth & nl000Ol)) : n11li0O;
	assign		wire_nli11l_dataout = ((~ pmadwidth[0]) === 1'b1) ? ((((~ nl00il) & (n1iO01i & nlOOiOO)) | ((nl00il & (n1iO01i & (nlOO00i & (~ nlOO01O)))) & (n1iO1Ol46 ^ n1iO1Ol45))) | (~ (n1iO1lO48 ^ n1iO1lO47))) : (n1iO01l | n1iO01i);
	assign		wire_nli11li_dataout = (comp_pat_size[0] === 1'b1) ? ((n11ll0l | nl00i0l) | (dwidth & nl000lO)) : wire_nli11ll_dataout;
	assign		wire_nli11ll_dataout = (n11l00l === 1'b1) ? n11li0O : ((n11liil | nl00i1i) | (dwidth & nl000il));
	and(wire_nli11Oi_dataout, nl0il0l, ~(wire_nlliiOl_dataout));
	and(wire_nli11Ol_dataout, nl0000l, ~(wire_nlliiOl_dataout));
	assign		wire_nli1i_dataout = (nO === 1'b1) ? (~ pudr[1]) : pudr[1];
	assign		wire_nli1il_dataout = ((~ pmadwidth[0]) === 1'b1) ? ((((~ nl00il) & ((n1iOi0i & nlOOiOi) & (n1iO0OO34 ^ n1iO0OO33))) & (n1iO0Oi36 ^ n1iO0Oi35)) | ((nl00il & (n1iOi0i & (nlOO0il & (~ nlOO0ii)))) & (n1iO0ll38 ^ n1iO0ll37))) : ((n1iOi0l | n1iOi0i) | (~ (n1iOi1l32 ^ n1iOi1l31)));
	assign		wire_nli1l_dataout = (nO === 1'b1) ? (~ pudr[2]) : pudr[2];
	assign		wire_nli1ll_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl00il) & (n1iOili & nlOO0ll)) | ((nl00il & (n1iOili & (nlOO0li & (~ nlOO0iO)))) & (n1iOi0O30 ^ n1iOi0O29))) : ((n1iOill | n1iOili) | (~ (n1iOiil28 ^ n1iOiil27)));
	assign		wire_nli1O_dataout = (nO === 1'b1) ? (~ pudr[3]) : pudr[3];
	assign		wire_nli1Ol_dataout = (n1iOilO === 1'b1) ? nlll1i : wire_nli0iO_dataout;
	assign		wire_nli1OO_dataout = (n1iOilO === 1'b1) ? nlll1l : wire_nli0li_dataout;
	and(wire_nlii_dataout, nl00lOO, wa_6g_en);
	assign		wire_nlii0i_dataout = (n1iOilO === 1'b1) ? nlll1l : wire_nli0li_dataout;
	assign		wire_nlii0l_dataout = (n1iOilO === 1'b1) ? nlll1O : wire_nli0ll_dataout;
	assign		wire_nlii0O_dataout = (n1iOilO === 1'b1) ? nlll0i : wire_nli0lO_dataout;
	and(wire_nlii1i_dataout, nlllil, ~(n1iOiOi));
	and(wire_nlii1l_dataout, nllliO, ~(n1iOiOi));
	and(wire_nlii1O_dataout, nlllli, ~(n1iOiOi));
	assign		wire_nliii_dataout = (nO === 1'b1) ? (~ pudr[7]) : pudr[7];
	assign		wire_nliiii_dataout = (n1iOilO === 1'b1) ? nlll0l : wire_nli0Oi_dataout;
	assign		wire_nliiil_dataout = (n1iOilO === 1'b1) ? nlll0O : wire_nli0Ol_dataout;
	assign		wire_nliiiO_dataout = (n1iOilO === 1'b1) ? nlllii : wire_nli0OO_dataout;
	assign		wire_nliil_dataout = (nO === 1'b1) ? (~ pudr[10]) : pudr[10];
	assign		wire_nliili_dataout = (n1iOilO === 1'b1) ? nlllil : wire_nlii1i_dataout;
	and(wire_nliill_dataout, wire_nlii1l_dataout, ~(n1iOilO));
	and(wire_nliilO_dataout, wire_nlii1O_dataout, ~(n1iOilO));
	assign		wire_nliiO_dataout = (nO === 1'b1) ? (~ pudr[11]) : pudr[11];
	and(wire_nliiOi_dataout, wire_nliiOl_dataout, ~(n1iOilO));
	and(wire_nliiOl_dataout, nlllll, ~(n1iOiOi));
	and(wire_nliiOO_dataout, nlllli, ~(n1iOilO));
	and(wire_nlil_dataout, nl00O1i, wa_6g_en);
	and(wire_nlil0i_dataout, nlllll, ~(n1iOilO));
	and(wire_nlil0l_dataout, wire_nlil1O_dataout, ~(n1iOilO));
	and(wire_nlil0O_dataout, wire_nlilii_dataout, ~(n1iOilO));
	and(wire_nlil1i_dataout, wire_nliiOl_dataout, ~(n1iOilO));
	and(wire_nlil1l_dataout, wire_nlil1O_dataout, ~(n1iOilO));
	and(wire_nlil1O_dataout, nllllO, ~(n1iOiOi));
	assign		wire_nlili_dataout = (nO === 1'b1) ? (~ pudr[12]) : pudr[12];
	and(wire_nlilii_dataout, nlllOi, ~(n1iOiOi));
	and(wire_nlilil_dataout, nllllO, ~(n1iOilO));
	and(wire_nliliO_dataout, wire_nlilii_dataout, ~(n1iOilO));
	assign		wire_nlill_dataout = (nO === 1'b1) ? (~ pudr[13]) : pudr[13];
	and(wire_nlilli_dataout, wire_nlilll_dataout, ~(n1iOilO));
	and(wire_nlilll_dataout, nlllOl, ~(n1iOiOi));
	and(wire_nlillO_dataout, nlllOi, ~(n1iOilO));
	assign		wire_nlilO_dataout = (nO === 1'b1) ? (~ pudr[14]) : pudr[14];
	and(wire_nlilOi_dataout, wire_nlilll_dataout, ~(n1iOilO));
	and(wire_nlilOl_dataout, wire_nlilOO_dataout, ~(n1iOilO));
	and(wire_nlilOO_dataout, nlllOO, ~(n1iOiOi));
	and(wire_nliO_dataout, nl00O1l, wa_6g_en);
	and(wire_nliO0i_dataout, nllO1i, ~(n1iOiOi));
	and(wire_nliO0l_dataout, nlllOO, ~(n1iOilO));
	and(wire_nliO0O_dataout, wire_nliO0i_dataout, ~(n1iOilO));
	and(wire_nliO1i_dataout, nlllOl, ~(n1iOilO));
	and(wire_nliO1l_dataout, wire_nlilOO_dataout, ~(n1iOilO));
	and(wire_nliO1O_dataout, wire_nliO0i_dataout, ~(n1iOilO));
	assign		wire_nliOi_dataout = (nO === 1'b1) ? (~ pudr[15]) : pudr[15];
	and(wire_nliOii_dataout, wire_nliOil_dataout, ~(n1iOilO));
	and(wire_nliOil_dataout, nllO1l, ~(n1iOiOi));
	and(wire_nliOiO_dataout, nllO1i, ~(n1iOilO));
	assign		wire_nliOl_dataout = (nO === 1'b1) ? (~ pudr[16]) : pudr[16];
	and(wire_nliOli_dataout, wire_nliOil_dataout, ~(n1iOilO));
	and(wire_nliOll_dataout, wire_nliOlO_dataout, ~(n1iOilO));
	and(wire_nliOlO_dataout, nllO1O, ~(n1iOiOi));
	assign		wire_nliOO_dataout = (nO === 1'b1) ? (~ pudr[17]) : pudr[17];
	and(wire_nliOOi_dataout, nllO1l, ~(n1iOilO));
	and(wire_nliOOl_dataout, wire_nliOlO_dataout, ~(n1iOilO));
	and(wire_nliOOO_dataout, wire_nll11i_dataout, ~(n1iOilO));
	assign		wire_nll_dataout = (wa_6g_en === 1'b1) ? nl0i1ii : nl0ili;
	assign		wire_nll00i_dataout = (n1iOiOi === 1'b1) ? comp_pat[15] : (~ comp_pat[7]);
	and(wire_nll00l_dataout, (~ comp_pat[8]), ~(n1iOiOi));
	and(wire_nll00O_dataout, (~ comp_pat[9]), ~(n1iOiOi));
	assign		wire_nll01i_dataout = (n1iOiOi === 1'b1) ? comp_pat[12] : (~ comp_pat[4]);
	assign		wire_nll01l_dataout = (n1iOiOi === 1'b1) ? comp_pat[13] : (~ comp_pat[5]);
	assign		wire_nll01O_dataout = (n1iOiOi === 1'b1) ? comp_pat[14] : (~ comp_pat[6]);
	assign		wire_nll0i_dataout = (n1iOO0O === 1'b1) ? wire_n1Ol_dataout : wire_nlOiO_dataout;
	and(wire_nll0ii_dataout, comp_pat[7], ~(n1iOilO));
	and(wire_nll0il_dataout, wire_nll0li_dataout, ~(n1iOilO));
	and(wire_nll0iO_dataout, wire_nll0ll_dataout, ~(n1iOilO));
	assign		wire_nll0l_dataout = (n1iOO0O === 1'b1) ? wire_n1OO_dataout : wire_nlOli_dataout;
	and(wire_nll0li_dataout, comp_pat[8], ~(n1iOiOi));
	and(wire_nll0ll_dataout, comp_pat[9], ~(n1iOiOi));
	assign		wire_nll0O_dataout = (n1iOO0O === 1'b1) ? wire_n01i_dataout : wire_nlOll_dataout;
	assign		wire_nll10i_dataout = (n1iOilO === 1'b1) ? (~ comp_pat[2]) : wire_nll1Ol_dataout;
	assign		wire_nll10l_dataout = (n1iOilO === 1'b1) ? (~ comp_pat[3]) : wire_nll1OO_dataout;
	assign		wire_nll10O_dataout = (n1iOilO === 1'b1) ? (~ comp_pat[4]) : wire_nll01i_dataout;
	and(wire_nll11i_dataout, nllO0l, ~(n1iOiOi));
	assign		wire_nll11l_dataout = (n1iOilO === 1'b1) ? (~ comp_pat[0]) : wire_nll1lO_dataout;
	assign		wire_nll11O_dataout = (n1iOilO === 1'b1) ? (~ comp_pat[1]) : wire_nll1Oi_dataout;
	assign		wire_nll1i_dataout = (n1iOO0O === 1'b1) ? wire_n1ll_dataout : wire_nlO0O_dataout;
	assign		wire_nll1ii_dataout = (n1iOilO === 1'b1) ? (~ comp_pat[5]) : wire_nll01l_dataout;
	assign		wire_nll1il_dataout = (n1iOilO === 1'b1) ? (~ comp_pat[6]) : wire_nll01O_dataout;
	and(wire_nll1iO_dataout, wire_nll00i_dataout, ~(n1iOilO));
	assign		wire_nll1l_dataout = (n1iOO0O === 1'b1) ? wire_n1lO_dataout : wire_nlOii_dataout;
	and(wire_nll1li_dataout, wire_nll00l_dataout, ~(n1iOilO));
	and(wire_nll1ll_dataout, wire_nll00O_dataout, ~(n1iOilO));
	assign		wire_nll1lO_dataout = (n1iOiOi === 1'b1) ? comp_pat[8] : (~ comp_pat[0]);
	assign		wire_nll1O_dataout = (n1iOO0O === 1'b1) ? wire_n1Oi_dataout : wire_nlOil_dataout;
	assign		wire_nll1Oi_dataout = (n1iOiOi === 1'b1) ? comp_pat[9] : (~ comp_pat[1]);
	assign		wire_nll1Ol_dataout = (n1iOiOi === 1'b1) ? comp_pat[10] : (~ comp_pat[2]);
	assign		wire_nll1OO_dataout = (n1iOiOi === 1'b1) ? comp_pat[11] : (~ comp_pat[3]);
	and(wire_nlli_dataout, nl00O1O, wa_6g_en);
	assign		wire_nllii_dataout = (n1iOO0O === 1'b1) ? wire_n01l_dataout : wire_nlOlO_dataout;
	and(wire_nlliiOl_dataout, wire_nllil0O_dataout, n1i1i1l);
	and(wire_nlliiOO_dataout, n1i1iiO, n1i1i1O);
	assign		wire_nllil_dataout = (n1iOO0O === 1'b1) ? wire_n01O_dataout : wire_nlOOi_dataout;
	and(wire_nllil0l_dataout, (~ n1i1i0i), ~(n1i1iil));
	or(wire_nllil0O_dataout, n1i1i0i, n1i1iil);
	and(wire_nllil1i_dataout, wire_nllil0l_dataout, n1i1i1l);
	assign		wire_nlliO_dataout = (n1iOO0O === 1'b1) ? wire_n00i_dataout : wire_nlOOl_dataout;
	and(wire_nlll_dataout, nl00O0i, wa_6g_en);
	assign		wire_nllli_dataout = (n1iOO0O === 1'b1) ? wire_n00l_dataout : wire_nlOOO_dataout;
	assign		wire_nllll_dataout = (n1iOO0O === 1'b1) ? wire_n00O_dataout : wire_n11i_dataout;
	assign		wire_nlllO_dataout = (n1iOO0O === 1'b1) ? wire_n0ii_dataout : wire_n11l_dataout;
	and(wire_nllO_dataout, nl00O0l, wa_6g_en);
	assign		wire_nllO00O_dataout = (lpbk_en === 1'b1) ? wire_niO0l_dataout : wire_nll1i_dataout;
	assign		wire_nllO0ii_dataout = (lpbk_en === 1'b1) ? wire_niO0O_dataout : wire_nll1l_dataout;
	assign		wire_nllO0il_dataout = (lpbk_en === 1'b1) ? wire_niOii_dataout : wire_nll1O_dataout;
	assign		wire_nllO0iO_dataout = (lpbk_en === 1'b1) ? wire_niOil_dataout : wire_nll0i_dataout;
	assign		wire_nllO0li_dataout = (lpbk_en === 1'b1) ? wire_niOiO_dataout : wire_nll0l_dataout;
	assign		wire_nllO0ll_dataout = (lpbk_en === 1'b1) ? wire_niOli_dataout : wire_nll0O_dataout;
	assign		wire_nllO0lO_dataout = (lpbk_en === 1'b1) ? wire_niOll_dataout : wire_nllii_dataout;
	assign		wire_nllO0O_dataout = (pmadwidth[0] === 1'b1) ? nlll0i : nlll1l;
	assign		wire_nllO0Oi_dataout = (lpbk_en === 1'b1) ? wire_niOlO_dataout : wire_nllil_dataout;
	assign		wire_nllO0Ol_dataout = (lpbk_en === 1'b1) ? wire_niOOi_dataout : wire_nlliO_dataout;
	assign		wire_nllO0OO_dataout = (lpbk_en === 1'b1) ? wire_niOOl_dataout : wire_nllli_dataout;
	assign		wire_nllOi_dataout = (n1iOO0O === 1'b1) ? wire_n0il_dataout : wire_n11O_dataout;
	assign		wire_nllOi0i_dataout = (lpbk_en === 1'b1) ? wire_nl11O_dataout : wire_nllOl_dataout;
	assign		wire_nllOi0l_dataout = (lpbk_en === 1'b1) ? wire_nl10i_dataout : wire_nllOO_dataout;
	assign		wire_nllOi0O_dataout = (lpbk_en === 1'b1) ? wire_nl10l_dataout : wire_nlO1i_dataout;
	assign		wire_nllOi1i_dataout = (lpbk_en === 1'b1) ? wire_niOOO_dataout : wire_nllll_dataout;
	assign		wire_nllOi1l_dataout = (lpbk_en === 1'b1) ? wire_nl11i_dataout : wire_nlllO_dataout;
	assign		wire_nllOi1O_dataout = (lpbk_en === 1'b1) ? wire_nl11l_dataout : wire_nllOi_dataout;
	assign		wire_nllOii_dataout = (pmadwidth[0] === 1'b1) ? nlll0l : nlll1O;
	assign		wire_nllOiii_dataout = (lpbk_en === 1'b1) ? wire_nl10O_dataout : wire_nlO1l_dataout;
	assign		wire_nllOiil_dataout = (lpbk_en === 1'b1) ? wire_nl1ii_dataout : wire_nlO1O_dataout;
	assign		wire_nllOiiO_dataout = (lpbk_en === 1'b1) ? wire_nl1il_dataout : wire_nlO0i_dataout;
	assign		wire_nllOil_dataout = (pmadwidth[0] === 1'b1) ? nlll0O : nlll0i;
	assign		wire_nllOili_dataout = (lpbk_en === 1'b1) ? wire_nl1iO_dataout : wire_nlO0l_dataout;
	assign		wire_nllOiO_dataout = (pmadwidth[0] === 1'b1) ? nlllii : nlll0l;
	or(wire_nllOiOO_dataout, wire_nllOl1i_dataout, (nllO00l & (~ nllO00i)));
	assign		wire_nllOl_dataout = (n1iOO0O === 1'b1) ? wire_n0iO_dataout : wire_n10i_dataout;
	and(wire_nllOl1i_dataout, nllO1OO, ~(nllO01i));
	assign		wire_nllOli_dataout = (pmadwidth[0] === 1'b1) ? nlllil : nlll0O;
	assign		wire_nllOll_dataout = (pmadwidth[0] === 1'b1) ? nllliO : nlllii;
	assign		wire_nllOlO_dataout = (pmadwidth[0] === 1'b1) ? nlllli : nlllil;
	assign		wire_nllOO_dataout = (n1iOO0O === 1'b1) ? wire_n0li_dataout : wire_n10l_dataout;
	assign		wire_nllOOi_dataout = (pmadwidth[0] === 1'b1) ? nlllll : nllliO;
	assign		wire_nllOOl_dataout = (pmadwidth[0] === 1'b1) ? nllllO : nlllli;
	assign		wire_nllOOO_dataout = (pmadwidth[0] === 1'b1) ? nlllOi : nlllll;
	assign		wire_nlO_dataout = (wa_6g_en === 1'b1) ? nl0i1il : niO11l;
	and(wire_nlO000l_dataout, wire_nlO00ll_dataout, ~(n1i1liO));
	and(wire_nlO000O_dataout, wire_nlO00lO_dataout, ~(n1i1liO));
	and(wire_nlO001l_dataout, n1i1l1l, ~((~ n1i1OiO)));
	and(wire_nlO001O_dataout, (~ n1i1l1l), ~((~ n1i1OiO)));
	and(wire_nlO00ii_dataout, wire_nlO00Oi_dataout, ~(n1i1liO));
	and(wire_nlO00il_dataout, n1i1lii, ~(n1i1liO));
	and(wire_nlO00iO_dataout, wire_nlO00Ol_dataout, ~(n1i1liO));
	and(wire_nlO00li_dataout, wire_nlO00OO_dataout, ~(n1i1liO));
	and(wire_nlO00ll_dataout, wire_nlO0i1i_dataout, ~(n1i1lii));
	and(wire_nlO00lO_dataout, wire_nlO0i1l_dataout, ~(n1i1lii));
	or(wire_nlO00O_dataout, n1iOliO, n1iOl0i);
	and(wire_nlO00Oi_dataout, wire_nlO0i1O_dataout, ~(n1i1lii));
	and(wire_nlO00Ol_dataout, n1i1l0O, ~(n1i1lii));
	and(wire_nlO00OO_dataout, wire_nlO0i0i_dataout, ~(n1i1lii));
	and(wire_nlO010i_dataout, wire_nlO01lO_o, ~((~ nlOiO0l)));
	and(wire_nlO010l_dataout, wire_nlO01Oi_o, ~((~ nlOiO0l)));
	and(wire_nlO010O_dataout, wire_nlO01Ol_o, ~((~ nlOiO0l)));
	and(wire_nlO011i_dataout, wire_nlO01iO_o, ~((~ nlOiO0l)));
	and(wire_nlO011l_dataout, wire_nlO01li_o, ~((~ nlOiO0l)));
	and(wire_nlO011O_dataout, wire_nlO01ll_o, ~((~ nlOiO0l)));
	assign		wire_nlO01i_dataout = (lpbk_en === 1'b1) ? wire_niliO_dataout : wire_niO0i_dataout;
	and(wire_nlO01ii_dataout, wire_nlO01OO_o, ~((~ nlOiO0l)));
	or(wire_nlO01il_dataout, wire_nlO001i_o, (~ nlOiO0l));
	and(wire_nlO0i_dataout, wire_n1iO_dataout, ~(n1iOO0O));
	and(wire_nlO0i0i_dataout, wire_nlO0iii_dataout, ~(n1i1l0O));
	and(wire_nlO0i0l_dataout, n1i1l0i, ~(n1i1l0l));
	and(wire_nlO0i0O_dataout, wire_nlO0iil_dataout, ~(n1i1l0l));
	and(wire_nlO0i1i_dataout, wire_nlO0i0l_dataout, ~(n1i1l0O));
	and(wire_nlO0i1l_dataout, n1i1l0l, ~(n1i1l0O));
	and(wire_nlO0i1O_dataout, wire_nlO0i0O_dataout, ~(n1i1l0O));
	and(wire_nlO0ii_dataout, n1iOliO, ~(n1iOl0i));
	and(wire_nlO0iii_dataout, wire_nlO0iiO_dataout, ~(n1i1l0l));
	and(wire_nlO0iil_dataout, n1i1l1O, ~(n1i1l0i));
	and(wire_nlO0iiO_dataout, (~ n1i1l1O), ~(n1i1l0i));
	and(wire_nlO0il_dataout, (~ n1iOliO), ~(n1iOl0i));
	or(wire_nlO0iO_dataout, n1iOl0i, n1iOliO);
	and(wire_nlO0l_dataout, wire_n1li_dataout, ~(n1iOO0O));
	and(wire_nlO0l0O_dataout, wire_nlO0lli_dataout, ~(n1i1lOO));
	and(wire_nlO0li_dataout, n1iOl0i, ~(n1iOliO));
	and(wire_nlO0lii_dataout, wire_nlO0lll_dataout, ~(n1i1lOO));
	and(wire_nlO0lil_dataout, wire_nlO0llO_dataout, ~(n1i1lOO));
	and(wire_nlO0liO_dataout, n1i1O1l, ~(n1i1lOO));
	and(wire_nlO0ll_dataout, (~ n1iOl0i), ~(n1iOliO));
	and(wire_nlO0lli_dataout, wire_nlO0lOi_dataout, ~(n1i1O1l));
	and(wire_nlO0lll_dataout, n1i1O1i, ~(n1i1O1l));
	and(wire_nlO0llO_dataout, wire_nlO0lOl_dataout, ~(n1i1O1l));
	and(wire_nlO0lOi_dataout, wire_nlO0lOO_dataout, ~(n1i1O1i));
	and(wire_nlO0lOl_dataout, n1i1O0O, ~(n1i1O1i));
	and(wire_nlO0lOO_dataout, (~ n1i1O1O), ~(n1i1O0O));
	assign		wire_nlO0O_dataout = (nO === 1'b1) ? (~ pudi[0]) : pudi[0];
	and(wire_nlO0O0O_dataout, wire_nlO0Oll_dataout, ~(n1i1lOi));
	and(wire_nlO0Oii_dataout, wire_nlO0OlO_dataout, ~(n1i1lOi));
	and(wire_nlO0Oil_dataout, n1i1llO, ~(n1i1lOi));
	and(wire_nlO0OiO_dataout, wire_nlO0OOi_dataout, ~(n1i1lOi));
	and(wire_nlO0Oli_dataout, wire_nlO0OOl_dataout, ~(n1i1lOi));
	and(wire_nlO0Oll_dataout, wire_nlO0OOO_dataout, ~(n1i1llO));
	and(wire_nlO0OlO_dataout, wire_nlOi11i_dataout, ~(n1i1llO));
	and(wire_nlO0OOi_dataout, n1i1lli, ~(n1i1llO));
	and(wire_nlO0OOl_dataout, wire_nlOi11l_dataout, ~(n1i1llO));
	and(wire_nlO0OOO_dataout, wire_nlOi11O_dataout, ~(n1i1lli));
	assign		wire_nlO10i_dataout = (pmadwidth[0] === 1'b1) ? nllO1l : nlllOO;
	assign		wire_nlO10il_dataout = (nlOl0lO === 1'b1) ? encdet_prbs : wire_nlO10iO_dataout;
	assign		wire_nlO10iO_dataout = (sync_sm_dis === 1'b1) ? wire_nlO10li_dataout : nlOiO0O;
	assign		wire_nlO10l_dataout = (pmadwidth[0] === 1'b1) ? nllO1O : nllO1i;
	assign		wire_nlO10li_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_nlO01l_o : nlOli1l;
	and(wire_nlO10ll_dataout, wire_nlOli0i_o[0], ~(n1i1ili));
	and(wire_nlO10lO_dataout, wire_nlOli0i_o[1], ~(n1i1ili));
	assign		wire_nlO10O_dataout = (pmadwidth[0] === 1'b1) ? nllO0l : nllO1l;
	and(wire_nlO10Oi_dataout, wire_nlOli0i_o[2], ~(n1i1ili));
	and(wire_nlO10Ol_dataout, wire_nlOli0i_o[3], ~(n1i1ili));
	assign		wire_nlO11i_dataout = (pmadwidth[0] === 1'b1) ? nlllOl : nllllO;
	assign		wire_nlO11l_dataout = (pmadwidth[0] === 1'b1) ? nlllOO : nlllOi;
	assign		wire_nlO11O_dataout = (pmadwidth[0] === 1'b1) ? nllO1i : nlllOl;
	assign		wire_nlO1i_dataout = (n1iOO0O === 1'b1) ? wire_n0ll_dataout : wire_n10O_dataout;
	assign		wire_nlO1ii_dataout = (lpbk_en === 1'b1) ? wire_niiOO_dataout : wire_nilli_dataout;
	assign		wire_nlO1il_dataout = (lpbk_en === 1'b1) ? wire_nil1i_dataout : wire_nilll_dataout;
	assign		wire_nlO1iO_dataout = (lpbk_en === 1'b1) ? wire_nil1l_dataout : wire_nillO_dataout;
	and(wire_nlO1l_dataout, wire_n1ii_dataout, ~(n1iOO0O));
	assign		wire_nlO1li_dataout = (lpbk_en === 1'b1) ? wire_nil1O_dataout : wire_nilOi_dataout;
	assign		wire_nlO1ll_dataout = (lpbk_en === 1'b1) ? wire_nil0i_dataout : wire_nilOl_dataout;
	assign		wire_nlO1lO_dataout = (lpbk_en === 1'b1) ? wire_nil0l_dataout : wire_nilOO_dataout;
	and(wire_nlO1O_dataout, wire_n1il_dataout, ~(n1iOO0O));
	assign		wire_nlO1Oi_dataout = (lpbk_en === 1'b1) ? wire_nil0O_dataout : wire_niO1i_dataout;
	assign		wire_nlO1Ol_dataout = (lpbk_en === 1'b1) ? wire_nilii_dataout : wire_niO1l_dataout;
	assign		wire_nlO1OO_dataout = (lpbk_en === 1'b1) ? wire_nilil_dataout : wire_niO1O_dataout;
	and(wire_nlOi_dataout, nl00O0O, wa_6g_en);
	and(wire_nlOi00i_dataout, wire_nlOi0iO_dataout, ~(n1i1O0i));
	and(wire_nlOi00l_dataout, n1i1Oil, ~(n1i1O0i));
	and(wire_nlOi00O_dataout, wire_nlOi0li_dataout, ~(n1i1Oil));
	and(wire_nlOi01i_dataout, wire_nlOi00O_dataout, ~(n1i1O0i));
	and(wire_nlOi01l_dataout, wire_nlOi0ii_dataout, ~(n1i1O0i));
	and(wire_nlOi01O_dataout, wire_nlOi0il_dataout, ~(n1i1O0i));
	and(wire_nlOi0ii_dataout, wire_nlOi0ll_dataout, ~(n1i1Oil));
	and(wire_nlOi0il_dataout, n1i1lOO, ~(n1i1Oil));
	and(wire_nlOi0iO_dataout, wire_nlOi0lO_dataout, ~(n1i1Oil));
	and(wire_nlOi0li_dataout, wire_nlOi0Oi_dataout, ~(n1i1lOO));
	and(wire_nlOi0ll_dataout, n1i1O1i, ~(n1i1lOO));
	and(wire_nlOi0lO_dataout, wire_nlOi0Ol_dataout, ~(n1i1lOO));
	and(wire_nlOi0Oi_dataout, wire_nlOi0OO_dataout, ~(n1i1O1i));
	and(wire_nlOi0Ol_dataout, n1i1O1l, ~(n1i1O1i));
	and(wire_nlOi0OO_dataout, (~ n1i1O1O), ~(n1i1O1l));
	and(wire_nlOi10i_dataout, n1i1O0i, ~(n1i1Oil));
	and(wire_nlOi10l_dataout, (~ n1i1O1O), ~(n1i1O0i));
	and(wire_nlOi11i_dataout, wire_nlOi10i_dataout, ~(n1i1lli));
	and(wire_nlOi11l_dataout, n1i1Oil, ~(n1i1lli));
	and(wire_nlOi11O_dataout, wire_nlOi10l_dataout, ~(n1i1Oil));
	assign		wire_nlOii_dataout = (nO === 1'b1) ? (~ pudi[1]) : pudi[1];
	and(wire_nlOii0i_dataout, n1i1Oil, ~(n1i1Oii));
	and(wire_nlOii0l_dataout, wire_nlOiiil_dataout, ~(n1i011O));
	and(wire_nlOii0O_dataout, wire_nlOiiiO_dataout, ~(n1i011O));
	and(wire_nlOii1l_dataout, wire_nlOi11O_dataout, ~(n1i1Oii));
	and(wire_nlOii1O_dataout, wire_nlOi10i_dataout, ~(n1i1Oii));
	and(wire_nlOiiii_dataout, n1i1Oli, ~(n1i011O));
	and(wire_nlOiiil_dataout, (~ n1i1Oll), ~(n1i1Oli));
	and(wire_nlOiiiO_dataout, n1i1Oll, ~(n1i1Oli));
	assign		wire_nlOil_dataout = (nO === 1'b1) ? (~ pudi[2]) : pudi[2];
	and(wire_nlOil0i_dataout, n1i1OlO, ~(n1i1OOO));
	and(wire_nlOil0l_dataout, (~ n1i1Oll), ~(n1i1OlO));
	and(wire_nlOil0O_dataout, n1i1Oll, ~(n1i1OlO));
	and(wire_nlOil1l_dataout, wire_nlOil0l_dataout, ~(n1i1OOO));
	and(wire_nlOil1O_dataout, wire_nlOil0O_dataout, ~(n1i1OOO));
	and(wire_nlOilll_dataout, n1i011i, ~((~ niO11l)));
	and(wire_nlOillO_dataout, (~ n1i011i), ~((~ niO11l)));
	assign		wire_nlOiO_dataout = (nO === 1'b1) ? (~ pudi[3]) : pudi[3];
	and(wire_nlOl_dataout, nl00Oii, wa_6g_en);
	assign		wire_nlOli_dataout = (nO === 1'b1) ? (~ pudi[4]) : pudi[4];
	assign		wire_nlOll_dataout = (nO === 1'b1) ? (~ pudi[5]) : pudi[5];
	or(wire_nlOll0i_dataout, n1iOili, n1iOill);
	or(wire_nlOlliO_dataout, n1iOi0i, n1iOi0l);
	or(wire_nlOllOl_dataout, n1iO0iO, n1iO0li);
	assign		wire_nlOlO_dataout = (nO === 1'b1) ? (~ pudi[6]) : pudi[6];
	or(wire_nlOlO0i_dataout, n1iO01i, n1iO01l);
	or(wire_nlOlOiO_dataout, n1iO1li, n1iO1ll);
	or(wire_nlOlOOl_dataout, n1iO1il, n1iO1iO);
	and(wire_nlOO_dataout, nl00Oil, wa_6g_en);
	or(wire_nlOO10i_dataout, n1iO10O, n1iO1ii);
	or(wire_nlOO1iO_dataout, n1iO10i, n1iO10l);
	assign		wire_nlOOi_dataout = (nO === 1'b1) ? (~ pudi[7]) : pudi[7];
	assign		wire_nlOOl_dataout = (nO === 1'b1) ? (~ pudi[8]) : pudi[8];
	assign		wire_nlOOO_dataout = (nO === 1'b1) ? (~ pudi[9]) : pudi[9];
	oper_add   n001ll
	( 
	.a({{2{1'b0}}, (~ n1i0liO), max_rlv_sel[4:2]}),
	.b({(~ n1i0liO), max_rlv_sel[4:0]}),
	.cin(1'b0),
	.cout(),
	.o(wire_n001ll_o));
	defparam
		n001ll.sgate_representation = 0,
		n001ll.width_a = 6,
		n001ll.width_b = 6,
		n001ll.width_o = 6;
	oper_add   n0101l
	( 
	.a({wire_n010il_dataout, wire_n010ii_dataout, wire_n0100l_dataout, wire_n0100i_dataout}),
	.b({{3{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n0101l_o));
	defparam
		n0101l.sgate_representation = 0,
		n0101l.width_a = 4,
		n0101l.width_b = 4,
		n0101l.width_o = 4;
	oper_add   n0101O
	( 
	.a({1'b0, wire_n01i1l_o, wire_n01i1i_o, wire_n010OO_o, wire_n010Ol_o}),
	.b({1'b0, wire_n010lO_o, wire_n010ll_o, wire_n010li_o, wire_n010iO_o}),
	.cin(1'b0),
	.cout(),
	.o(wire_n0101O_o));
	defparam
		n0101O.sgate_representation = 0,
		n0101O.width_a = 5,
		n0101O.width_b = 5,
		n0101O.width_o = 5;
	oper_add   n011llO
	( 
	.a({wire_n011O0i_dataout, wire_n011O1O_dataout, wire_n011O1i_dataout, wire_n011lOO_dataout, wire_n011lOl_dataout}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_n011llO_o));
	defparam
		n011llO.sgate_representation = 0,
		n011llO.width_a = 5,
		n011llO.width_b = 5,
		n011llO.width_o = 5;
	oper_add   n011lOi
	( 
	.a({1'b0, wire_n011OOO_o, wire_n011OOl_o, wire_n011OOi_o, wire_n011OlO_o, wire_n011Oll_o}),
	.b({1'b0, wire_n011OiO_o, wire_n011Oil_o, wire_n011Oii_o, wire_n011O0O_o, wire_n011O0l_o}),
	.cin(1'b0),
	.cout(),
	.o(wire_n011lOi_o));
	defparam
		n011lOi.sgate_representation = 0,
		n011lOi.width_a = 6,
		n011lOi.width_b = 6,
		n011lOi.width_o = 6;
	oper_add   n01iO0O
	( 
	.a({max_rlv_sel[5:0]}),
	.b({{2{1'b0}}, max_rlv_sel[5:2]}),
	.cin(1'b0),
	.cout(),
	.o(wire_n01iO0O_o));
	defparam
		n01iO0O.sgate_representation = 0,
		n01iO0O.width_a = 6,
		n01iO0O.width_b = 6,
		n01iO0O.width_o = 6;
	oper_add   nl000l
	( 
	.a({nl01li, nl01il, nl01ii, nl010l, 1'b1}),
	.b({{3{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nl000l_o));
	defparam
		nl000l.sgate_representation = 0,
		nl000l.width_a = 5,
		nl000l.width_b = 5,
		nl000l.width_o = 5;
	oper_add   nl0Oi1i
	( 
	.a({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}),
	.b({{4{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nl0Oi1i_o));
	defparam
		nl0Oi1i.sgate_representation = 0,
		nl0Oi1i.width_a = 5,
		nl0Oi1i.width_b = 5,
		nl0Oi1i.width_o = 5;
	oper_add   nlO1OlO
	( 
	.a({nlOl01i, nlOl1OO, nlOl1Ol, nlOl1Oi, nlOl1lO, nlOl1ll, nlOl1li, nlOl1iO, nlOl1il, nlOl1ii, 1'b1}),
	.b({{9{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlO1OlO_o));
	defparam
		nlO1OlO.sgate_representation = 0,
		nlO1OlO.width_a = 11,
		nlO1OlO.width_b = 11,
		nlO1OlO.width_o = 11;
	oper_add   nlO1OOi
	( 
	.a({nlOl10O, nlOl10l, nlOl10i, nlOl11O, nlOl11l, nlOl11i, nlOiOOO, nlOiOOl, nlOiOOi, nlOiOlO}),
	.b({{9{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlO1OOi_o));
	defparam
		nlO1OOi.sgate_representation = 0,
		nlO1OOi.width_a = 10,
		nlO1OOi.width_b = 10,
		nlO1OOi.width_o = 10;
	oper_add   nlO1OOl
	( 
	.a({nlOl01i, nlOl1OO, nlOl1Ol, nlOl1Oi, nlOl1lO, nlOl1ll, nlOl1li, nlOl1iO, nlOl1il, nlOl1ii}),
	.b({{9{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlO1OOl_o));
	defparam
		nlO1OOl.sgate_representation = 0,
		nlO1OOl.width_a = 10,
		nlO1OOl.width_b = 10,
		nlO1OOl.width_o = 10;
	oper_add   nlO1OOO
	( 
	.a({nlOl0ll, nlOl0li, nlOl0iO, nlOl0il, nlOl0ii, nlOl00O, nlOl00l, nlOl00i, nlOl01O, nlOl01l}),
	.b({{9{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlO1OOO_o));
	defparam
		nlO1OOO.sgate_representation = 0,
		nlO1OOO.width_a = 10,
		nlO1OOO.width_b = 10,
		nlO1OOO.width_o = 10;
	oper_add   nlOli0i
	( 
	.a({nlOiOll, nlOiOli, nlOiOiO, nlOiOil}),
	.b({{3{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nlOli0i_o));
	defparam
		nlOli0i.sgate_representation = 0,
		nlOli0i.width_a = 4,
		nlOli0i.width_b = 4,
		nlOli0i.width_o = 4;
	oper_less_than   n000li
	( 
	.a({wire_n001li_dataout, wire_n001iO_dataout, wire_n001il_dataout, wire_n001ii_dataout, wire_n0010O_dataout, wire_n0010l_dataout, wire_n0010i_dataout, wire_n0011O_dataout}),
	.b({n011ll, n011li, n011iO, n011il, n011ii, n0110O, n0110l, n0100O}),
	.cin(1'b0),
	.o(wire_n000li_o));
	defparam
		n000li.sgate_representation = 0,
		n000li.width_a = 8,
		n000li.width_b = 8;
	oper_less_than   n010lOO
	( 
	.a({nlOOOiOO, wire_n01ilOl_dataout, wire_n01ilOi_dataout, wire_n01illO_dataout, wire_n01illl_dataout, wire_n01illi_dataout, wire_n01iliO_dataout, wire_n01ilil_dataout, wire_n01ilii_dataout, 1'b0}),
	.b({n011l0l, n011l0i, n011l1O, n011l1l, n011l1i, n011iOO, n011iOl, n011iOi, n011ilO, n011O1l}),
	.cin(1'b0),
	.o(wire_n010lOO_o));
	defparam
		n010lOO.sgate_representation = 0,
		n010lOO.width_a = 10,
		n010lOO.width_b = 10;
	oper_less_than   nl0Oi1l
	( 
	.a({1'b1, {2{1'b0}}, {2{1'b1}}}),
	.b({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}),
	.cin(1'b1),
	.o(wire_nl0Oi1l_o));
	defparam
		nl0Oi1l.sgate_representation = 0,
		nl0Oi1l.width_a = 5,
		nl0Oi1l.width_b = 5;
	oper_less_than   nl0OiOi
	( 
	.a({1'b0, {4{1'b1}}}),
	.b({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}),
	.cin(1'b1),
	.o(wire_nl0OiOi_o));
	defparam
		nl0OiOi.sgate_representation = 0,
		nl0OiOi.width_a = 5,
		nl0OiOi.width_b = 5;
	oper_less_than   nl0OliO
	( 
	.a({1'b0, 1'b1, {2{1'b0}}, 1'b1}),
	.b({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}),
	.cin(1'b1),
	.o(wire_nl0OliO_o));
	defparam
		nl0OliO.sgate_representation = 0,
		nl0OliO.width_a = 5,
		nl0OliO.width_b = 5;
	oper_less_than   nl0OO0l
	( 
	.a({{2{1'b0}}, {3{1'b1}}}),
	.b({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}),
	.cin(1'b1),
	.o(wire_nl0OO0l_o));
	defparam
		nl0OO0l.sgate_representation = 0,
		nl0OO0l.width_a = 5,
		nl0OO0l.width_b = 5;
	oper_less_than   nlO0l1l
	( 
	.a({nlOl01i, nlOl1OO, nlOl1Ol, nlOl1Oi, nlOl1lO, nlOl1ll, nlOl1li, nlOl1iO, nlOl1il, nlOl1ii}),
	.b({{9{1'b0}}, 1'b1}),
	.cin(1'b1),
	.o(wire_nlO0l1l_o));
	defparam
		nlO0l1l.sgate_representation = 0,
		nlO0l1l.width_a = 10,
		nlO0l1l.width_b = 10;
	oper_less_than   nlOi1Ol
	( 
	.a({{9{1'b0}}, 1'b1}),
	.b({nlOl01i, nlOl1OO, nlOl1Ol, nlOl1Oi, nlOl1lO, nlOl1ll, nlOl1li, nlOl1iO, nlOl1il, nlOl1ii}),
	.cin(1'b0),
	.o(wire_nlOi1Ol_o));
	defparam
		nlOi1Ol.sgate_representation = 0,
		nlOi1Ol.width_a = 10,
		nlOi1Ol.width_b = 10;
	oper_mux   nl0011i
	( 
	.data({nl0iiil, nl0i0OO, nl0iiii, nl0iiOO}),
	.o(wire_nl0011i_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl0011i.width_data = 4,
		nl0011i.width_sel = 2;
	oper_mux   nl0100l
	( 
	.data({wire_nl01ili_o, wire_nl01O1i_o, wire_nl0011l_dataout, wire_nl001lO_dataout}),
	.o(wire_nl0100l_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl0100l.width_data = 4,
		nl0100l.width_sel = 2;
	oper_mux   nl0100O
	( 
	.data({wire_nl01ill_o, wire_nl01O1l_o, wire_nl0011O_dataout, wire_nl001Oi_dataout}),
	.o(wire_nl0100O_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl0100O.width_data = 4,
		nl0100O.width_sel = 2;
	oper_mux   nl010ii
	( 
	.data({wire_nl01ilO_o, wire_nl01O1O_o, wire_nl0010i_dataout, wire_nl001Ol_dataout}),
	.o(wire_nl010ii_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010ii.width_data = 4,
		nl010ii.width_sel = 2;
	oper_mux   nl010il
	( 
	.data({wire_nl01iOi_o, wire_nl01O0i_o, wire_nl0010l_dataout, wire_nl001OO_dataout}),
	.o(wire_nl010il_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010il.width_data = 4,
		nl010il.width_sel = 2;
	oper_mux   nl010iO
	( 
	.data({wire_nl01iOl_o, wire_nl01O0l_o, wire_nl0010O_dataout, wire_nl0001i_dataout}),
	.o(wire_nl010iO_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010iO.width_data = 4,
		nl010iO.width_sel = 2;
	oper_mux   nl010li
	( 
	.data({wire_nl01iOO_o, wire_nl01O0O_o, wire_nl001ii_dataout, wire_nl0001l_dataout}),
	.o(wire_nl010li_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010li.width_data = 4,
		nl010li.width_sel = 2;
	oper_mux   nl010ll
	( 
	.data({wire_nl01l1i_o, wire_nl01Oii_o, wire_nl001il_dataout, wire_nl0001O_dataout}),
	.o(wire_nl010ll_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010ll.width_data = 4,
		nl010ll.width_sel = 2;
	oper_mux   nl010lO
	( 
	.data({wire_nl01l1l_o, wire_nl01Oil_o, wire_nl001iO_dataout, wire_nl0000i_dataout}),
	.o(wire_nl010lO_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010lO.width_data = 4,
		nl010lO.width_sel = 2;
	oper_mux   nl010Oi
	( 
	.data({wire_nl01l1O_o, 1'b0, wire_nl001li_dataout, 1'b0}),
	.o(wire_nl010Oi_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010Oi.width_data = 4,
		nl010Oi.width_sel = 2;
	oper_mux   nl010Ol
	( 
	.data({wire_nl01l0i_o, 1'b0, wire_nl001ll_dataout, 1'b0}),
	.o(wire_nl010Ol_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010Ol.width_data = 4,
		nl010Ol.width_sel = 2;
	oper_mux   nl010OO
	( 
	.data({wire_nl01l0l_o, wire_nl01OiO_o, nl0iili, nl0iiil}),
	.o(wire_nl010OO_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl010OO.width_data = 4,
		nl010OO.width_sel = 2;
	oper_mux   nl011i
	( 
	.data({{6{nllliO}}, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i, nlll0l, nlll0O, nlllii, nlllil, {9{nllliO}}, {8{nl1O0l}}}),
	.o(wire_nl011i_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl011i.width_data = 32,
		nl011i.width_sel = 5;
	oper_mux   nl01i0i
	( 
	.data({wire_nl01liO_o, wire_nl01OOi_o, nl0iiOl, nl0iilO}),
	.o(wire_nl01i0i_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01i0i.width_data = 4,
		nl01i0i.width_sel = 2;
	oper_mux   nl01i0l
	( 
	.data({wire_nl01lli_o, wire_nl01OOl_o, nl0iiOO, nl0iiOi}),
	.o(wire_nl01i0l_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01i0l.width_data = 4,
		nl01i0l.width_sel = 2;
	oper_mux   nl01i0O
	( 
	.data({wire_nl01lll_o, wire_nl01OOO_o, nl0il1i, nl0iiOl}),
	.o(wire_nl01i0O_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01i0O.width_data = 4,
		nl01i0O.width_sel = 2;
	oper_mux   nl01i1i
	( 
	.data({wire_nl01l0O_o, wire_nl01Oli_o, nl0iill, nl0iiiO}),
	.o(wire_nl01i1i_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01i1i.width_data = 4,
		nl01i1i.width_sel = 2;
	oper_mux   nl01i1l
	( 
	.data({wire_nl01lii_o, wire_nl01Oll_o, nl0iilO, nl0iili}),
	.o(wire_nl01i1l_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01i1l.width_data = 4,
		nl01i1l.width_sel = 2;
	oper_mux   nl01i1O
	( 
	.data({wire_nl01lil_o, wire_nl01OlO_o, nl0iiOi, nl0iill}),
	.o(wire_nl01i1O_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01i1O.width_data = 4,
		nl01i1O.width_sel = 2;
	oper_mux   nl01iii
	( 
	.data({wire_nl01llO_o, wire_nl0011i_o, nl0il1l, nl0iiOO}),
	.o(wire_nl01iii_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01iii.width_data = 4,
		nl01iii.width_sel = 2;
	oper_mux   nl01iil
	( 
	.data({wire_nl01lOi_o, 1'b0, nl0il1O, 1'b0}),
	.o(wire_nl01iil_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01iil.width_data = 4,
		nl01iil.width_sel = 2;
	oper_mux   nl01iiO
	( 
	.data({wire_nl01lOl_o, 1'b0, nl0il0i, 1'b0}),
	.o(wire_nl01iiO_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl01iiO.width_data = 4,
		nl01iiO.width_sel = 2;
	oper_mux   nl01ili
	( 
	.data({nl0iiiO, nl0il0i, nl0iili, nl0i0OO}),
	.o(wire_nl01ili_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01ili.width_data = 4,
		nl01ili.width_sel = 2;
	oper_mux   nl01ill
	( 
	.data({nl0iiil, nl0il1O, nl0iill, nl0ii1i}),
	.o(wire_nl01ill_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01ill.width_data = 4,
		nl01ill.width_sel = 2;
	oper_mux   nl01ilO
	( 
	.data({nl0iiii, nl0il1l, nl0iilO, nl0ii1l}),
	.o(wire_nl01ilO_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01ilO.width_data = 4,
		nl01ilO.width_sel = 2;
	oper_mux   nl01iOi
	( 
	.data({nl0ii0O, nl0il1i, nl0iiOi, nl0ii1O}),
	.o(wire_nl01iOi_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01iOi.width_data = 4,
		nl01iOi.width_sel = 2;
	oper_mux   nl01iOl
	( 
	.data({nl0ii0l, nl0iiOO, nl0iiOl, nl0ii0i}),
	.o(wire_nl01iOl_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01iOl.width_data = 4,
		nl01iOl.width_sel = 2;
	oper_mux   nl01iOO
	( 
	.data({nl0ii0i, nl0iiOl, nl0iiOO, nl0ii0l}),
	.o(wire_nl01iOO_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01iOO.width_data = 4,
		nl01iOO.width_sel = 2;
	oper_mux   nl01l0i
	( 
	.data({nl0i0OO, nl0iili, nl0il0i, nl0iiiO}),
	.o(wire_nl01l0i_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01l0i.width_data = 4,
		nl01l0i.width_sel = 2;
	oper_mux   nl01l0l
	( 
	.data({nl0il0i, nl0iiiO, nl0i0OO, nl0iili}),
	.o(wire_nl01l0l_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01l0l.width_data = 4,
		nl01l0l.width_sel = 2;
	oper_mux   nl01l0O
	( 
	.data({nl0il1O, nl0iiil, nl0ii1i, nl0iill}),
	.o(wire_nl01l0O_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01l0O.width_data = 4,
		nl01l0O.width_sel = 2;
	oper_mux   nl01l1i
	( 
	.data({nl0ii1O, nl0iiOi, nl0il1i, nl0ii0O}),
	.o(wire_nl01l1i_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01l1i.width_data = 4,
		nl01l1i.width_sel = 2;
	oper_mux   nl01l1l
	( 
	.data({nl0ii1l, nl0iilO, nl0il1l, nl0iiii}),
	.o(wire_nl01l1l_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01l1l.width_data = 4,
		nl01l1l.width_sel = 2;
	oper_mux   nl01l1O
	( 
	.data({nl0ii1i, nl0iill, nl0il1O, nl0iiil}),
	.o(wire_nl01l1O_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01l1O.width_data = 4,
		nl01l1O.width_sel = 2;
	oper_mux   nl01lii
	( 
	.data({nl0il1l, nl0iiii, nl0ii1l, nl0iilO}),
	.o(wire_nl01lii_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01lii.width_data = 4,
		nl01lii.width_sel = 2;
	oper_mux   nl01lil
	( 
	.data({nl0il1i, nl0ii0O, nl0ii1O, nl0iiOi}),
	.o(wire_nl01lil_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01lil.width_data = 4,
		nl01lil.width_sel = 2;
	oper_mux   nl01liO
	( 
	.data({nl0iiOO, nl0ii0l, nl0ii0i, nl0iiOl}),
	.o(wire_nl01liO_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01liO.width_data = 4,
		nl01liO.width_sel = 2;
	oper_mux   nl01lli
	( 
	.data({nl0iiOl, nl0ii0i, nl0ii0l, nl0iiOO}),
	.o(wire_nl01lli_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01lli.width_data = 4,
		nl01lli.width_sel = 2;
	oper_mux   nl01lll
	( 
	.data({nl0iiOi, nl0ii1O, nl0ii0O, nl0il1i}),
	.o(wire_nl01lll_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01lll.width_data = 4,
		nl01lll.width_sel = 2;
	oper_mux   nl01llO
	( 
	.data({nl0iilO, nl0ii1l, nl0iiii, nl0il1l}),
	.o(wire_nl01llO_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01llO.width_data = 4,
		nl01llO.width_sel = 2;
	oper_mux   nl01lOi
	( 
	.data({nl0iill, nl0ii1i, nl0iiil, nl0il1O}),
	.o(wire_nl01lOi_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01lOi.width_data = 4,
		nl01lOi.width_sel = 2;
	oper_mux   nl01lOl
	( 
	.data({nl0iili, nl0i0OO, nl0iiiO, nl0il0i}),
	.o(wire_nl01lOl_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01lOl.width_data = 4,
		nl01lOl.width_sel = 2;
	oper_mux   nl01O0i
	( 
	.data({nl0ii0i, nl0iilO, nl0iill, nl0ii1O}),
	.o(wire_nl01O0i_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01O0i.width_data = 4,
		nl01O0i.width_sel = 2;
	oper_mux   nl01O0l
	( 
	.data({nl0ii1O, nl0iill, nl0iilO, nl0ii0i}),
	.o(wire_nl01O0l_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01O0l.width_data = 4,
		nl01O0l.width_sel = 2;
	oper_mux   nl01O0O
	( 
	.data({nl0ii1l, nl0iili, nl0iiOi, nl0ii0l}),
	.o(wire_nl01O0O_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01O0O.width_data = 4,
		nl01O0O.width_sel = 2;
	oper_mux   nl01O1i
	( 
	.data({nl0iiii, nl0iiOO, nl0iiil, nl0i0OO}),
	.o(wire_nl01O1i_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01O1i.width_data = 4,
		nl01O1i.width_sel = 2;
	oper_mux   nl01O1l
	( 
	.data({nl0ii0O, nl0iiOl, nl0iiiO, nl0ii1i}),
	.o(wire_nl01O1l_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01O1l.width_data = 4,
		nl01O1l.width_sel = 2;
	oper_mux   nl01O1O
	( 
	.data({nl0ii0l, nl0iiOi, nl0iili, nl0ii1l}),
	.o(wire_nl01O1O_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01O1O.width_data = 4,
		nl01O1O.width_sel = 2;
	oper_mux   nl01Oii
	( 
	.data({nl0ii1i, nl0iiiO, nl0iiOl, nl0ii0O}),
	.o(wire_nl01Oii_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01Oii.width_data = 4,
		nl01Oii.width_sel = 2;
	oper_mux   nl01Oil
	( 
	.data({nl0i0OO, nl0iiil, nl0iiOO, nl0iiii}),
	.o(wire_nl01Oil_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01Oil.width_data = 4,
		nl01Oil.width_sel = 2;
	oper_mux   nl01OiO
	( 
	.data({nl0iiOO, nl0iiii, nl0i0OO, nl0iiil}),
	.o(wire_nl01OiO_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01OiO.width_data = 4,
		nl01OiO.width_sel = 2;
	oper_mux   nl01Oli
	( 
	.data({nl0iiOl, nl0ii0O, nl0ii1i, nl0iiiO}),
	.o(wire_nl01Oli_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01Oli.width_data = 4,
		nl01Oli.width_sel = 2;
	oper_mux   nl01Oll
	( 
	.data({nl0iiOi, nl0ii0l, nl0ii1l, nl0iili}),
	.o(wire_nl01Oll_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01Oll.width_data = 4,
		nl01Oll.width_sel = 2;
	oper_mux   nl01OlO
	( 
	.data({nl0iilO, nl0ii0i, nl0ii1O, nl0iill}),
	.o(wire_nl01OlO_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01OlO.width_data = 4,
		nl01OlO.width_sel = 2;
	oper_mux   nl01OOi
	( 
	.data({nl0iill, nl0ii1O, nl0ii0i, nl0iilO}),
	.o(wire_nl01OOi_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01OOi.width_data = 4,
		nl01OOi.width_sel = 2;
	oper_mux   nl01OOl
	( 
	.data({nl0iili, nl0ii1l, nl0ii0l, nl0iiOi}),
	.o(wire_nl01OOl_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01OOl.width_data = 4,
		nl01OOl.width_sel = 2;
	oper_mux   nl01OOO
	( 
	.data({nl0iiiO, nl0ii1i, nl0ii0O, nl0iiOl}),
	.o(wire_nl01OOO_o),
	.sel({nllO1li, nllO1il}));
	defparam
		nl01OOO.width_data = 4,
		nl01OOO.width_sel = 2;
	oper_mux   nl0li0O
	( 
	.data({{16{nlll00i}}, nllli0i, nllli1O, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i}),
	.o(wire_nl0li0O_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0li0O.width_data = 32,
		nl0li0O.width_sel = 5;
	oper_mux   nl0liii
	( 
	.data({{12{nlll00i}}, nllliil, nllliii, nllli0O, nllli0l, nllli0i, nllli1O, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i}),
	.o(wire_nl0liii_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0liii.width_data = 32,
		nl0liii.width_sel = 5;
	oper_mux   nl0liil
	( 
	.data({{16{nlliOOl}}, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O, nlll11l, nlll11i, nlliOOO, nlliOOl}),
	.o(wire_nl0liil_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0liil.width_data = 32,
		nl0liil.width_sel = 5;
	oper_mux   nl0liiO
	( 
	.data({{16{nlliOOO}}, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O, nlll11l, nlll11i, nlliOOO}),
	.o(wire_nl0liiO_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0liiO.width_data = 32,
		nl0liiO.width_sel = 5;
	oper_mux   nl0lili
	( 
	.data({{16{nlll11i}}, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O, nlll11l, nlll11i}),
	.o(wire_nl0lili_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lili.width_data = 32,
		nl0lili.width_sel = 5;
	oper_mux   nl0lill
	( 
	.data({{16{nlll11l}}, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O, nlll11l}),
	.o(wire_nl0lill_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lill.width_data = 32,
		nl0lill.width_sel = 5;
	oper_mux   nl0lilO
	( 
	.data({{16{nlll11O}}, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O}),
	.o(wire_nl0lilO_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lilO.width_data = 32,
		nl0lilO.width_sel = 5;
	oper_mux   nl0liOi
	( 
	.data({{16{nlll10i}}, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i}),
	.o(wire_nl0liOi_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0liOi.width_data = 32,
		nl0liOi.width_sel = 5;
	oper_mux   nl0liOl
	( 
	.data({{16{nlll10l}}, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l}),
	.o(wire_nl0liOl_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0liOl.width_data = 32,
		nl0liOl.width_sel = 5;
	oper_mux   nl0liOO
	( 
	.data({{16{nlll10O}}, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O}),
	.o(wire_nl0liOO_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0liOO.width_data = 32,
		nl0liOO.width_sel = 5;
	oper_mux   nl0ll0i
	( 
	.data({{16{nlll1li}}, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li}),
	.o(wire_nl0ll0i_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0ll0i.width_data = 32,
		nl0ll0i.width_sel = 5;
	oper_mux   nl0ll0l
	( 
	.data({{16{nlll1ll}}, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll}),
	.o(wire_nl0ll0l_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0ll0l.width_data = 32,
		nl0ll0l.width_sel = 5;
	oper_mux   nl0ll0O
	( 
	.data({{16{nlll1lO}}, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO}),
	.o(wire_nl0ll0O_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0ll0O.width_data = 32,
		nl0ll0O.width_sel = 5;
	oper_mux   nl0ll1i
	( 
	.data({{16{nlll1ii}}, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii}),
	.o(wire_nl0ll1i_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0ll1i.width_data = 32,
		nl0ll1i.width_sel = 5;
	oper_mux   nl0ll1l
	( 
	.data({{16{nlll1il}}, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il}),
	.o(wire_nl0ll1l_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0ll1l.width_data = 32,
		nl0ll1l.width_sel = 5;
	oper_mux   nl0ll1O
	( 
	.data({{16{nlll1iO}}, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO}),
	.o(wire_nl0ll1O_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0ll1O.width_data = 32,
		nl0ll1O.width_sel = 5;
	oper_mux   nl0llii
	( 
	.data({{16{nlll1Oi}}, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol, nlll1Oi}),
	.o(wire_nl0llii_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0llii.width_data = 32,
		nl0llii.width_sel = 5;
	oper_mux   nl0llil
	( 
	.data({{16{nlll1Ol}}, nllli1O, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll1Ol}),
	.o(wire_nl0llil_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0llil.width_data = 32,
		nl0llil.width_sel = 5;
	oper_mux   nl0llli
	( 
	.data({{12{nlliOOl}}, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O, nlll11l, nlll11i, nlliOOO, nlliOOl}),
	.o(wire_nl0llli_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0llli.width_data = 32,
		nl0llli.width_sel = 5;
	oper_mux   nl0llll
	( 
	.data({{12{nlliOOO}}, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O, nlll11l, nlll11i, nlliOOO}),
	.o(wire_nl0llll_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0llll.width_data = 32,
		nl0llll.width_sel = 5;
	oper_mux   nl0lllO
	( 
	.data({{12{nlll11i}}, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O, nlll11l, nlll11i}),
	.o(wire_nl0lllO_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lllO.width_data = 32,
		nl0lllO.width_sel = 5;
	oper_mux   nl0llOi
	( 
	.data({{12{nlll11l}}, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O, nlll11l}),
	.o(wire_nl0llOi_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0llOi.width_data = 32,
		nl0llOi.width_sel = 5;
	oper_mux   nl0llOl
	( 
	.data({{12{nlll11O}}, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i, nlll11O}),
	.o(wire_nl0llOl_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0llOl.width_data = 32,
		nl0llOl.width_sel = 5;
	oper_mux   nl0llOO
	( 
	.data({{12{nlll10i}}, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, nlll10i}),
	.o(wire_nl0llOO_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0llOO.width_data = 32,
		nl0llOO.width_sel = 5;
	oper_mux   nl0lO0i
	( 
	.data({{12{nlll1il}}, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il}),
	.o(wire_nl0lO0i_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lO0i.width_data = 32,
		nl0lO0i.width_sel = 5;
	oper_mux   nl0lO0l
	( 
	.data({{12{nlll1iO}}, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO}),
	.o(wire_nl0lO0l_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lO0l.width_data = 32,
		nl0lO0l.width_sel = 5;
	oper_mux   nl0lO0O
	( 
	.data({{12{nlll1li}}, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li}),
	.o(wire_nl0lO0O_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lO0O.width_data = 32,
		nl0lO0O.width_sel = 5;
	oper_mux   nl0lO1i
	( 
	.data({{12{nlll10l}}, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l}),
	.o(wire_nl0lO1i_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lO1i.width_data = 32,
		nl0lO1i.width_sel = 5;
	oper_mux   nl0lO1l
	( 
	.data({{12{nlll10O}}, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii, nlll10O}),
	.o(wire_nl0lO1l_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lO1l.width_data = 32,
		nl0lO1l.width_sel = 5;
	oper_mux   nl0lO1O
	( 
	.data({{12{nlll1ii}}, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll, nlll1li, nlll1iO, nlll1il, nlll1ii}),
	.o(wire_nl0lO1O_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lO1O.width_data = 32,
		nl0lO1O.width_sel = 5;
	oper_mux   nl0lOii
	( 
	.data({{12{nlll1ll}}, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO, nlll1ll}),
	.o(wire_nl0lOii_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lOii.width_data = 32,
		nl0lOii.width_sel = 5;
	oper_mux   nl0lOil
	( 
	.data({{12{nlll1lO}}, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi, nlll1lO}),
	.o(wire_nl0lOil_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lOil.width_data = 32,
		nl0lOil.width_sel = 5;
	oper_mux   nl0lOiO
	( 
	.data({{12{nlll1Oi}}, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol, nlll1Oi}),
	.o(wire_nl0lOiO_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lOiO.width_data = 32,
		nl0lOiO.width_sel = 5;
	oper_mux   nl0lOli
	( 
	.data({{12{nlll1Ol}}, nllli1O, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO, nlll1Ol}),
	.o(wire_nl0lOli_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lOli.width_data = 32,
		nl0lOli.width_sel = 5;
	oper_mux   nl0lOll
	( 
	.data({{12{nlll1OO}}, nllli0i, nllli1O, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i, nlll1OO}),
	.o(wire_nl0lOll_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lOll.width_data = 32,
		nl0lOll.width_sel = 5;
	oper_mux   nl0lOlO
	( 
	.data({{12{nlll01i}}, nllli0l, nllli0i, nllli1O, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l, nlll01i}),
	.o(wire_nl0lOlO_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lOlO.width_data = 32,
		nl0lOlO.width_sel = 5;
	oper_mux   nl0lOOi
	( 
	.data({{12{nlll01l}}, nllli0O, nllli0l, nllli0i, nllli1O, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O, nlll01l}),
	.o(wire_nl0lOOi_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lOOi.width_data = 32,
		nl0lOOi.width_sel = 5;
	oper_mux   nl0lOOl
	( 
	.data({{12{nlll01O}}, nllliii, nllli0O, nllli0l, nllli0i, nllli1O, nllli1l, nllli1i, nlll0OO, nlll0Ol, nlll0Oi, nlll0lO, nlll0ll, nlll0li, nlll0iO, nlll0il, nlll0ii, nlll00O, nlll00l, nlll00i, nlll01O}),
	.o(wire_nl0lOOl_o),
	.sel({nl0i1iO, nl0i1il, nl0i1ii, nl0i10O, nl0i10l}));
	defparam
		nl0lOOl.width_data = 32,
		nl0lOOl.width_sel = 5;
	oper_mux   nl0O00i
	( 
	.data({wire_nl0O0iO_dataout, wire_nl0Oi0O_dataout, wire_nl0Ol1l_dataout, wire_nl0OlOi_dataout}),
	.o(wire_nl0O00i_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl0O00i.width_data = 4,
		nl0O00i.width_sel = 2;
	oper_mux   nl0O00l
	( 
	.data({wire_nl0O0li_dataout, wire_nl0Oiii_dataout, wire_nl0Ol1O_dataout, wire_nl0OlOl_dataout}),
	.o(wire_nl0O00l_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl0O00l.width_data = 4,
		nl0O00l.width_sel = 2;
	oper_mux   nl0O01i
	( 
	.data({wire_nl0O00O_dataout, wire_nl0Oi1O_dataout, wire_nl0OiOl_dataout, wire_nl0Olli_dataout}),
	.o(wire_nl0O01i_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl0O01i.width_data = 4,
		nl0O01i.width_sel = 2;
	oper_mux   nl0O01l
	( 
	.data({wire_nl0O0ii_dataout, wire_nl0Oi0i_dataout, wire_nl0OiOO_dataout, wire_nl0Olll_dataout}),
	.o(wire_nl0O01l_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl0O01l.width_data = 4,
		nl0O01l.width_sel = 2;
	oper_mux   nl0O01O
	( 
	.data({wire_nl0O0il_dataout, wire_nl0Oi0l_dataout, wire_nl0Ol1i_dataout, wire_nl0OllO_dataout}),
	.o(wire_nl0O01O_o),
	.sel({pmadwidth[1:0]}));
	defparam
		nl0O01O.width_data = 4,
		nl0O01O.width_sel = 2;
	oper_mux   nl1Oii
	( 
	.data({{6{nlliOO}}, nlli0O, nlliii, nlliil, nlliiO, nllili, nllill, nllilO, nlliOi, nlliOl, {9{nlliOO}}, nllili, nllill, nllilO, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l}),
	.o(wire_nl1Oii_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1Oii.width_data = 32,
		nl1Oii.width_sel = 5;
	oper_mux   nl1Oil
	( 
	.data({{6{nlll1i}}, nlliii, nlliil, nlliiO, nllili, nllill, nllilO, nlliOi, nlliOl, nlliOO, {9{nlll1i}}, nllill, nllilO, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O}),
	.o(wire_nl1Oil_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1Oil.width_data = 32,
		nl1Oil.width_sel = 5;
	oper_mux   nl1OiO
	( 
	.data({{6{nlll1l}}, nlliil, nlliiO, nllili, nllill, nllilO, nlliOi, nlliOl, nlliOO, nlll1i, {9{nlll1l}}, nllilO, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i}),
	.o(wire_nl1OiO_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1OiO.width_data = 32,
		nl1OiO.width_sel = 5;
	oper_mux   nl1Oli
	( 
	.data({{6{nlll1O}}, nlliiO, nllili, nllill, nllilO, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l, {9{nlll1O}}, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i, nlll0l}),
	.o(wire_nl1Oli_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1Oli.width_data = 32,
		nl1Oli.width_sel = 5;
	oper_mux   nl1Oll
	( 
	.data({{6{nlll0i}}, nllili, nllill, nllilO, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O, {9{nlll0i}}, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i, nlll0l, nlll0O}),
	.o(wire_nl1Oll_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1Oll.width_data = 32,
		nl1Oll.width_sel = 5;
	oper_mux   nl1OlO
	( 
	.data({{6{nlll0l}}, nllill, nllilO, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i, {9{nlll0l}}, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i, nlll0l, nlll0O, nlllii}),
	.o(wire_nl1OlO_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1OlO.width_data = 32,
		nl1OlO.width_sel = 5;
	oper_mux   nl1OOi
	( 
	.data({{6{nlll0O}}, nllilO, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i, nlll0l, {9{nlll0O}}, nlll1i, nlll1l, nlll1O, nlll0i, nlll0l, nlll0O, nlllii, nlllil}),
	.o(wire_nl1OOi_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1OOi.width_data = 32,
		nl1OOi.width_sel = 5;
	oper_mux   nl1OOl
	( 
	.data({{6{nlllii}}, nlliOi, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i, nlll0l, nlll0O, {9{nlllii}}, nlll1l, nlll1O, nlll0i, nlll0l, nlll0O, nlllii, nlllil, nllliO}),
	.o(wire_nl1OOl_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1OOl.width_data = 32,
		nl1OOl.width_sel = 5;
	oper_mux   nl1OOO
	( 
	.data({{6{nlllil}}, nlliOl, nlliOO, nlll1i, nlll1l, nlll1O, nlll0i, nlll0l, nlll0O, nlllii, {9{nlllil}}, {8{nl1O0i}}}),
	.o(wire_nl1OOO_o),
	.sel({pmadwidth[0], wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout}));
	defparam
		nl1OOO.width_data = 32,
		nl1OOO.width_sel = 5;
	oper_mux   nli0i0i
	( 
	.data({n1i100i, n10ilil, n10110i, n10ll1l, n101O1i, n10Oi1O, n100i0l, n1i100i}),
	.o(wire_nli0i0i_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0i0i.width_data = 8,
		nli0i0i.width_sel = 3;
	oper_mux   nli0i0l
	( 
	.data({n1i101i, n10il1O, n11OOOl, n10liOl, n101lOi, n10O0OO, n100i1l, n1i101i}),
	.o(wire_nli0i0l_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0i0l.width_data = 8,
		nli0i0l.width_sel = 3;
	oper_mux   nli0i0O
	( 
	.data({n1i11Oi, n10iiOi, n11OOiO, n10lill, n101lli, n10O0lO, n1000Ol, n1i11Oi}),
	.o(wire_nli0i0O_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0i0O.width_data = 8,
		nli0i0O.width_sel = 3;
	oper_mux   nli0i1i
	( 
	.data({n1i10Oi, n10iOil, n10100i, n10llll, n101Oli, n10OilO, n100iOl, n1i10Oi}),
	.o(wire_nli0i1i_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0i1i.width_data = 8,
		nli0i1i.width_sel = 3;
	oper_mux   nli0i1l
	( 
	.data({n1i10li, n10iO1O, n1011Ol, n10llil, n101Oii, n10OiiO, n100ill, n1i10li}),
	.o(wire_nli0i1l_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0i1l.width_data = 8,
		nli0i1l.width_sel = 3;
	oper_mux   nli0i1O
	( 
	.data({n1i10ii, n10ilOi, n1011iO, n10ll0l, n101O0i, n10Oi0O, n100iil, n1i10ii}),
	.o(wire_nli0i1O_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0i1O.width_data = 8,
		nli0i1O.width_sel = 3;
	oper_mux   nli0iii
	( 
	.data({n1i11li, n10iiil, n11OO0i, n10liil, n101lii, n10O0iO, n1000ll, n1i11li}),
	.o(wire_nli0iii_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0iii.width_data = 8,
		nli0iii.width_sel = 3;
	oper_mux   nli0iil
	( 
	.data({n1i11ii, n10ii1O, n11OlOl, n10li0l, n101l0i, n10O00O, n1000il, n1i11ii}),
	.o(wire_nli0iil_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0iil.width_data = 8,
		nli0iil.width_sel = 3;
	oper_mux   nli0iiO
	( 
	.data({n1i110i, n10i0Oi, n11OliO, n10li1l, n101l1i, n10O01O, n10000l, n1i110i}),
	.o(wire_nli0iiO_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0iiO.width_data = 8,
		nli0iiO.width_sel = 3;
	oper_mux   nli0ili
	( 
	.data({n1i111i, n10i0il, n11Ol0i, n10l0Ol, n101iOi, n10O1OO, n10001l, n1i111i}),
	.o(wire_nli0ili_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0ili.width_data = 8,
		nli0ili.width_sel = 3;
	oper_mux   nli0ill
	( 
	.data({n10OOOi, n10i01O, n11OiOl, n10l0ll, n101ili, n10O1lO, n1001Ol, n10OOOi}),
	.o(wire_nli0ill_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0ill.width_data = 8,
		nli0ill.width_sel = 3;
	oper_mux   nli0ilO
	( 
	.data({n10OOli, n10i1Oi, n11OiiO, n10l0il, n101iii, n10O1iO, n1001ll, n10OOli}),
	.o(wire_nli0ilO_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0ilO.width_data = 8,
		nli0ilO.width_sel = 3;
	oper_mux   nli0iOi
	( 
	.data({n10OOii, n10i1il, n11Oi0i, n10l00l, n101i0i, n10O10O, n1001il, n10OOii}),
	.o(wire_nli0iOi_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0iOi.width_data = 8,
		nli0iOi.width_sel = 3;
	oper_mux   nli0iOl
	( 
	.data({n10OO0i, n10i11O, n11O0Ol, n10l01l, n101i1i, n10O11O, n10010l, n10OO0i}),
	.o(wire_nli0iOl_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0iOl.width_data = 8,
		nli0iOl.width_sel = 3;
	oper_mux   nli0iOO
	( 
	.data({n10OO1i, n100OOi, n11O0iO, n10l1Ol, n1010Oi, n10lOOO, n10011l, n10OO1i}),
	.o(wire_nli0iOO_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0iOO.width_data = 8,
		nli0iOO.width_sel = 3;
	oper_mux   nli0l0i
	( 
	.data({n10Ol0i, n100lil, 1'b0, n10l11l, 1'b0, n10lO1O, 1'b0, n10Ol0i}),
	.o(wire_nli0l0i_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0l0i.width_data = 8,
		nli0l0i.width_sel = 3;
	oper_mux   nli0l0l
	( 
	.data({n10Ol1i, n100l1O, 1'b0, n10iOOl, 1'b0, n10llOO, 1'b0, n10Ol1i}),
	.o(wire_nli0l0l_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0l0l.width_data = 8,
		nli0l0l.width_sel = 3;
	oper_mux   nli0l1i
	( 
	.data({n10OlOi, n100Oil, n11O00i, n10l1ll, n1010li, n10lOlO, n101OOl, n10OlOi}),
	.o(wire_nli0l1i_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0l1i.width_data = 8,
		nli0l1i.width_sel = 3;
	oper_mux   nli0l1l
	( 
	.data({n10Olli, n100O1O, 1'b0, n10l1il, 1'b0, n10lOiO, 1'b0, n10Olli}),
	.o(wire_nli0l1l_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0l1l.width_data = 8,
		nli0l1l.width_sel = 3;
	oper_mux   nli0l1O
	( 
	.data({n10Olii, n100lOi, 1'b0, n10l10l, 1'b0, n10lO0O, 1'b0, n10Olii}),
	.o(wire_nli0l1O_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli0l1O.width_data = 8,
		nli0l1O.width_sel = 3;
	oper_mux   nli101l
	( 
	.data({{2{n11l0OO}}, n11l00O, n11l0OO, n11l00O, n11l0OO, n11l00O, ((comp_pat_porn & n11l0il) | n11l0ii)}),
	.o(wire_nli101l_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli101l.width_data = 8,
		nli101l.width_sel = 3;
	oper_mux   nli101O
	( 
	.data({{2{n11li1O}}, n11l0iO, n11li1O, n11l0iO, ((comp_pat_porn & n11l0ll) | n11l0li), n11l0lO, ((comp_pat_porn & n11l0Ol) | n11l0Oi)}),
	.o(wire_nli101O_o),
	.sel({comp_pat_size[2:0]}));
	defparam
		nli101O.width_data = 8,
		nli101O.width_sel = 3;
	oper_mux   nlO001i
	( 
	.data({{3{1'b1}}, wire_nlO001O_dataout, {4{1'b1}}, wire_nlO0Oli_dataout, wire_nlOi00l_dataout, 1'b0, wire_nlO00li_dataout, n1i011O, wire_nlOii0i_dataout, n1i1OOO, (~ niO11l)}),
	.o(wire_nlO001i_o),
	.sel({nlOiO1O, nlOiO1l, nlOiO1i, nlO1i1i}));
	defparam
		nlO001i.width_data = 16,
		nlO001i.width_sel = 4;
	oper_mux   nlO01iO
	( 
	.data({{3{1'b0}}, (~ n1i1OiO), {4{1'b0}}, wire_nlO0O0O_dataout, wire_nlOi01i_dataout, wire_nlO0l0O_dataout, wire_nlO000l_dataout, 1'b0, wire_nlOii1l_dataout, {2{1'b0}}}),
	.o(wire_nlO01iO_o),
	.sel({nlOiO1O, nlOiO1l, nlOiO1i, nlO1i1i}));
	defparam
		nlO01iO.width_data = 16,
		nlO01iO.width_sel = 4;
	oper_mux   nlO01li
	( 
	.data({{8{1'b0}}, n1i1lOi, wire_nlOi01l_dataout, wire_nlO0lii_dataout, wire_nlO000O_dataout, {4{1'b0}}}),
	.o(wire_nlO01li_o),
	.sel({nlOiO1O, nlOiO1l, nlOiO1i, nlO1i1i}));
	defparam
		nlO01li.width_data = 16,
		nlO01li.width_sel = 4;
	oper_mux   nlO01ll
	( 
	.data({{3{1'b0}}, wire_nlO001l_dataout, {4{1'b0}}, wire_nlO0Oii_dataout, n1i1O0i, wire_nlO0lil_dataout, wire_nlO00ii_dataout, 1'b0, wire_nlOii1O_dataout, {2{1'b0}}}),
	.o(wire_nlO01ll_o),
	.sel({nlOiO1O, nlOiO1l, nlOiO1i, nlO1i1i}));
	defparam
		nlO01ll.width_data = 16,
		nlO01ll.width_sel = 4;
	oper_mux   nlO01lO
	( 
	.data({{8{1'b0}}, wire_nlO0Oil_dataout, wire_nlOi01O_dataout, n1i1lOO, wire_nlO00il_dataout, {4{1'b0}}}),
	.o(wire_nlO01lO_o),
	.sel({nlOiO1O, nlOiO1l, nlOiO1i, nlO1i1i}));
	defparam
		nlO01lO.width_data = 16,
		nlO01lO.width_sel = 4;
	oper_mux   nlO01Oi
	( 
	.data({{12{1'b0}}, wire_nlOii0l_dataout, 1'b0, wire_nlOil1l_dataout, 1'b0}),
	.o(wire_nlO01Oi_o),
	.sel({nlOiO1O, nlOiO1l, nlOiO1i, nlO1i1i}));
	defparam
		nlO01Oi.width_data = 16,
		nlO01Oi.width_sel = 4;
	oper_mux   nlO01Ol
	( 
	.data({{8{1'b0}}, wire_nlO0OiO_dataout, wire_nlOi00i_dataout, wire_nlO0liO_dataout, wire_nlO00iO_dataout, wire_nlOii0O_dataout, n1i1Oii, wire_nlOil1O_dataout, wire_nlOilll_dataout}),
	.o(wire_nlO01Ol_o),
	.sel({nlOiO1O, nlOiO1l, nlOiO1i, nlO1i1i}));
	defparam
		nlO01Ol.width_data = 16,
		nlO01Ol.width_sel = 4;
	oper_mux   nlO01OO
	( 
	.data({{12{1'b0}}, wire_nlOiiii_dataout, 1'b0, wire_nlOil0i_dataout, wire_nlOillO_dataout}),
	.o(wire_nlO01OO_o),
	.sel({nlOiO1O, nlOiO1l, nlOiO1i, nlO1i1i}));
	defparam
		nlO01OO.width_data = 16,
		nlO01OO.width_sel = 4;
	oper_mux   nlOll1O
	( 
	.data({wire_nlOll0i_dataout, 1'b0, n1iOill, 1'b0}),
	.o(wire_nlOll1O_o),
	.sel({nlOO0li, nlOO0iO}));
	defparam
		nlOll1O.width_data = 4,
		nlOll1O.width_sel = 2;
	oper_mux   nlOllil
	( 
	.data({wire_nlOlliO_dataout, 1'b0, n1iOi0l, 1'b0}),
	.o(wire_nlOllil_o),
	.sel({nlOO0il, nlOO0ii}));
	defparam
		nlOllil.width_data = 4,
		nlOllil.width_sel = 2;
	oper_mux   nlOllOi
	( 
	.data({wire_nlOllOl_dataout, 1'b0, n1iO0li, 1'b0}),
	.o(wire_nlOllOi_o),
	.sel({nlOO00O, nlOO00l}));
	defparam
		nlOllOi.width_data = 4,
		nlOllOi.width_sel = 2;
	oper_mux   nlOlO1O
	( 
	.data({wire_nlOlO0i_dataout, 1'b0, n1iO01l, 1'b0}),
	.o(wire_nlOlO1O_o),
	.sel({nlOO00i, nlOO01O}));
	defparam
		nlOlO1O.width_data = 4,
		nlOlO1O.width_sel = 2;
	oper_mux   nlOlOil
	( 
	.data({wire_nlOlOiO_dataout, 1'b0, n1iO1ll, 1'b0}),
	.o(wire_nlOlOil_o),
	.sel({nlOO01l, nlOO01i}));
	defparam
		nlOlOil.width_data = 4,
		nlOlOil.width_sel = 2;
	oper_mux   nlOlOOi
	( 
	.data({wire_nlOlOOl_dataout, 1'b0, n1iO1iO, 1'b0}),
	.o(wire_nlOlOOi_o),
	.sel({nlOO1OO, nlOO1Ol}));
	defparam
		nlOlOOi.width_data = 4,
		nlOlOOi.width_sel = 2;
	oper_mux   nlOO11O
	( 
	.data({wire_nlOO10i_dataout, 1'b0, n1iO1ii, 1'b0}),
	.o(wire_nlOO11O_o),
	.sel({nlOO1Oi, nlOO1lO}));
	defparam
		nlOO11O.width_data = 4,
		nlOO11O.width_sel = 2;
	oper_mux   nlOO1il
	( 
	.data({wire_nlOO1iO_dataout, 1'b0, n1iO10l, 1'b0}),
	.o(wire_nlOO1il_o),
	.sel({nlOO1ll, nlOO1li}));
	defparam
		nlOO1il.width_data = 4,
		nlOO1il.width_sel = 2;
	oper_selector   n01010l
	( 
	.data({1'b0, {3{wire_n010i1i_dataout}}, {3{wire_n01000i_dataout}}}),
	.o(wire_n01010l_o),
	.sel({nlOOOiii, n010iOl, n010iOi, n010ilO, n010ill, n010ili, n011l0O}));
	defparam
		n01010l.width_data = 7,
		n01010l.width_sel = 7;
	oper_selector   n01011O
	( 
	.data({1'b0, wire_n01001O_dataout}),
	.o(wire_n01011O_o),
	.sel({nlOOOi0l, (~ nlOOOi0l)}));
	defparam
		n01011O.width_data = 2,
		n01011O.width_sel = 2;
	oper_selector   n0101ii
	( 
	.data({1'b0, wire_n010i1l_dataout}),
	.o(wire_n0101ii_o),
	.sel({nlOOOi0O, (~ nlOOOi0O)}));
	defparam
		n0101ii.width_data = 2,
		n0101ii.width_sel = 2;
	oper_selector   n0101iO
	( 
	.data({1'b0, {3{wire_n010i1O_dataout}}, {3{wire_n01000l_dataout}}}),
	.o(wire_n0101iO_o),
	.sel({nlOOOiii, n010iOl, n010iOi, n010ilO, n010ill, n010ili, n011l0O}));
	defparam
		n0101iO.width_data = 7,
		n0101iO.width_sel = 7;
	oper_selector   n010iO
	( 
	.data({1'b0, n0i01O, n0100O, n00O0i}),
	.o(wire_n010iO_o),
	.sel({n1i0l1O, n1i0iOO, n1i0iOi, n1i0iOl}));
	defparam
		n010iO.width_data = 4,
		n010iO.width_sel = 4;
	oper_selector   n010li
	( 
	.data({1'b0, n0i00i, n0110l, n00O0l}),
	.o(wire_n010li_o),
	.sel({n1i0l1O, n1i0iOO, n1i0iOi, n1i0iOl}));
	defparam
		n010li.width_data = 4,
		n010li.width_sel = 4;
	oper_selector   n010ll
	( 
	.data({1'b0, n0i00l, n0110O, n00O0O}),
	.o(wire_n010ll_o),
	.sel({n1i0l1O, n1i0iOO, n1i0iOi, n1i0iOl}));
	defparam
		n010ll.width_data = 4,
		n010ll.width_sel = 4;
	oper_selector   n010lO
	( 
	.data({1'b0, n0i00O, n011ii, n00Oii}),
	.o(wire_n010lO_o),
	.sel({n1i0l1O, n1i0iOO, n1i0iOi, n1i0iOl}));
	defparam
		n010lO.width_data = 4,
		n010lO.width_sel = 4;
	oper_selector   n010Ol
	( 
	.data({1'b0, n0i1Ol, wire_n01lll_dataout, n00lOO, wire_n01iOO_dataout}),
	.o(wire_n010Ol_o),
	.sel({n1i0l1O, n1i0iOO, n01OlO, n1i0iOl, n011lO}));
	defparam
		n010Ol.width_data = 5,
		n010Ol.width_sel = 5;
	oper_selector   n010OO
	( 
	.data({1'b0, n0i1OO, wire_n01llO_dataout, n00O1i, wire_n01l1i_dataout}),
	.o(wire_n010OO_o),
	.sel({n1i0l1O, n1i0iOO, n01OlO, n1i0iOl, n011lO}));
	defparam
		n010OO.width_data = 5,
		n010OO.width_sel = 5;
	oper_selector   n011O0l
	( 
	.data({1'b0, n01lili, n011O1l, n01l10l}),
	.o(wire_n011O0l_o),
	.sel({nlOOOiii, nlOOOi0i, nlOOOi1l, nlOOOi1O}));
	defparam
		n011O0l.width_data = 4,
		n011O0l.width_sel = 4;
	oper_selector   n011O0O
	( 
	.data({1'b0, n01lill, n011ilO, n01l10O}),
	.o(wire_n011O0O_o),
	.sel({nlOOOiii, nlOOOi0i, nlOOOi1l, nlOOOi1O}));
	defparam
		n011O0O.width_data = 4,
		n011O0O.width_sel = 4;
	oper_selector   n011Oii
	( 
	.data({1'b0, n01lilO, n011iOi, n01l1ii}),
	.o(wire_n011Oii_o),
	.sel({nlOOOiii, nlOOOi0i, nlOOOi1l, nlOOOi1O}));
	defparam
		n011Oii.width_data = 4,
		n011Oii.width_sel = 4;
	oper_selector   n011Oil
	( 
	.data({1'b0, n01liOi, n011iOl, n01l1il}),
	.o(wire_n011Oil_o),
	.sel({nlOOOiii, nlOOOi0i, nlOOOi1l, nlOOOi1O}));
	defparam
		n011Oil.width_data = 4,
		n011Oil.width_sel = 4;
	oper_selector   n011OiO
	( 
	.data({1'b0, n01liOl, n011iOO, n01l1iO}),
	.o(wire_n011OiO_o),
	.sel({nlOOOiii, nlOOOi0i, nlOOOi1l, nlOOOi1O}));
	defparam
		n011OiO.width_data = 4,
		n011OiO.width_sel = 4;
	oper_selector   n011Oll
	( 
	.data({1'b0, n01li0l, wire_n0100li_dataout, n01iOOO, wire_n0101Oi_dataout}),
	.o(wire_n011Oll_o),
	.sel({nlOOOiii, nlOOOi0i, n010ilO, nlOOOi1O, n011l0O}));
	defparam
		n011Oll.width_data = 5,
		n011Oll.width_sel = 5;
	oper_selector   n011OlO
	( 
	.data({1'b0, n01li0O, wire_n0100ll_dataout, n01l11i, wire_n0101Ol_dataout}),
	.o(wire_n011OlO_o),
	.sel({nlOOOiii, nlOOOi0i, n010ilO, nlOOOi1O, n011l0O}));
	defparam
		n011OlO.width_data = 5,
		n011OlO.width_sel = 5;
	oper_selector   n011OOi
	( 
	.data({1'b0, n01liii, wire_n0100lO_dataout, n01l11l, wire_n0101OO_dataout}),
	.o(wire_n011OOi_o),
	.sel({nlOOOiii, nlOOOi0i, n010ilO, nlOOOi1O, n011l0O}));
	defparam
		n011OOi.width_data = 5,
		n011OOi.width_sel = 5;
	oper_selector   n011OOl
	( 
	.data({1'b0, n01liil, wire_n0100Oi_dataout, n01l11O, wire_n01001i_dataout}),
	.o(wire_n011OOl_o),
	.sel({nlOOOiii, nlOOOi0i, n010ilO, nlOOOi1O, n011l0O}));
	defparam
		n011OOl.width_data = 5,
		n011OOl.width_sel = 5;
	oper_selector   n011OOO
	( 
	.data({1'b0, n01liiO, wire_n0100Ol_dataout, n01l10i, wire_n01001l_dataout}),
	.o(wire_n011OOO_o),
	.sel({nlOOOiii, nlOOOi0i, n010ilO, nlOOOi1O, n011l0O}));
	defparam
		n011OOO.width_data = 5,
		n011OOO.width_sel = 5;
	oper_selector   n01i0l
	( 
	.data({1'b0, wire_n01l0i_dataout}),
	.o(wire_n01i0l_o),
	.sel({n1i0l1i, (~ n1i0l1i)}));
	defparam
		n01i0l.width_data = 2,
		n01i0l.width_sel = 2;
	oper_selector   n01i1i
	( 
	.data({1'b0, n0i01i, wire_n01lOi_dataout, n00O1l, wire_n01l1l_dataout}),
	.o(wire_n01i1i_o),
	.sel({n1i0l1O, n1i0iOO, n01OlO, n1i0iOl, n011lO}));
	defparam
		n01i1i.width_data = 5,
		n01i1i.width_sel = 5;
	oper_selector   n01i1l
	( 
	.data({1'b0, n0i01l, wire_n01lOl_dataout, n00O1O, wire_n01l1O_dataout}),
	.o(wire_n01i1l_o),
	.sel({n1i0l1O, n1i0iOO, n01OlO, n1i0iOl, n011lO}));
	defparam
		n01i1l.width_data = 5,
		n01i1l.width_sel = 5;
	oper_selector   n01iii
	( 
	.data({1'b0, {3{wire_n01O1i_dataout}}, {3{wire_n01l0l_dataout}}}),
	.o(wire_n01iii_o),
	.sel({n1i0l1O, n01OOl, n01OOi, n01OlO, n01Oll, n01Oli, n011lO}));
	defparam
		n01iii.width_data = 7,
		n01iii.width_sel = 7;
	oper_selector   n01iiO
	( 
	.data({1'b0, wire_n01O1l_dataout}),
	.o(wire_n01iiO_o),
	.sel({n1i0l1l, (~ n1i0l1l)}));
	defparam
		n01iiO.width_data = 2,
		n01iiO.width_sel = 2;
	oper_selector   n01ill
	( 
	.data({1'b0, {3{wire_n01O1O_dataout}}, {3{wire_n01l0O_dataout}}}),
	.o(wire_n01ill_o),
	.sel({n1i0l1O, n01OOl, n01OOi, n01OlO, n01Oll, n01Oli, n011lO}));
	defparam
		n01ill.width_data = 7,
		n01ill.width_sel = 7;
	oper_selector   nl1i0i
	( 
	.data({comp_pat[8], comp_pat[0], wire_nl1iOi_o}),
	.o(wire_nl1i0i_o),
	.sel({n1illli, n1illiO, (~ n1illil)}));
	defparam
		nl1i0i.width_data = 3,
		nl1i0i.width_sel = 3;
	oper_selector   nl1i0l
	( 
	.data({comp_pat[9], comp_pat[1], wire_nl1iOl_o}),
	.o(wire_nl1i0l_o),
	.sel({n1illli, n1illiO, (~ n1illil)}));
	defparam
		nl1i0l.width_data = 3,
		nl1i0l.width_sel = 3;
	oper_selector   nl1i0O
	( 
	.data({comp_pat[10], comp_pat[2], wire_nl1iOO_o}),
	.o(wire_nl1i0O_o),
	.sel({n1illli, n1illiO, (~ n1illil)}));
	defparam
		nl1i0O.width_data = 3,
		nl1i0O.width_sel = 3;
	oper_selector   nl1iii
	( 
	.data({comp_pat[11], comp_pat[3], wire_nl1l1i_o}),
	.o(wire_nl1iii_o),
	.sel({n1illli, n1illiO, (~ n1illil)}));
	defparam
		nl1iii.width_data = 3,
		nl1iii.width_sel = 3;
	oper_selector   nl1iil
	( 
	.data({comp_pat[12], comp_pat[4], wire_nl1l1l_o}),
	.o(wire_nl1iil_o),
	.sel({n1illli, n1illiO, (~ n1illil)}));
	defparam
		nl1iil.width_data = 3,
		nl1iil.width_sel = 3;
	oper_selector   nl1iiO
	( 
	.data({comp_pat[13], comp_pat[5], wire_nl1l1O_o}),
	.o(wire_nl1iiO_o),
	.sel({n1illli, n1illiO, (~ n1illil)}));
	defparam
		nl1iiO.width_data = 3,
		nl1iiO.width_sel = 3;
	oper_selector   nl1ili
	( 
	.data({comp_pat[14], comp_pat[6], wire_nl1l0i_o}),
	.o(wire_nl1ili_o),
	.sel({n1illli, n1illiO, (~ n1illil)}));
	defparam
		nl1ili.width_data = 3,
		nl1ili.width_sel = 3;
	oper_selector   nl1ill
	( 
	.data({comp_pat[15], comp_pat[7], wire_nl1l0l_o}),
	.o(wire_nl1ill_o),
	.sel({n1illli, n1illiO, (~ n1illil)}));
	defparam
		nl1ill.width_data = 3,
		nl1ill.width_sel = 3;
	oper_selector   nl1iOi
	( 
	.data({nl1O1O, nl1O0l, nl1lli}),
	.o(wire_nl1iOi_o),
	.sel({n1illOi, n1illlO, (~ n1illll)}));
	defparam
		nl1iOi.width_data = 3,
		nl1iOi.width_sel = 3;
	oper_selector   nl1iOl
	( 
	.data({nl1O1l, nl1O0i, nl1llO}),
	.o(wire_nl1iOl_o),
	.sel({n1illOi, n1illlO, (~ n1illll)}));
	defparam
		nl1iOl.width_data = 3,
		nl1iOl.width_sel = 3;
	oper_selector   nl1iOO
	( 
	.data({nl1O1i, nl1O1O, nl1lOi}),
	.o(wire_nl1iOO_o),
	.sel({n1illOi, n1illlO, (~ n1illll)}));
	defparam
		nl1iOO.width_data = 3,
		nl1iOO.width_sel = 3;
	oper_selector   nl1l0i
	( 
	.data({nl1llO, nl1lOl, nl1O1l}),
	.o(wire_nl1l0i_o),
	.sel({n1illOi, n1illlO, (~ n1illll)}));
	defparam
		nl1l0i.width_data = 3,
		nl1l0i.width_sel = 3;
	oper_selector   nl1l0l
	( 
	.data({nl1lli, nl1lOi, nl1O1O}),
	.o(wire_nl1l0l_o),
	.sel({n1illOi, n1illlO, (~ n1illll)}));
	defparam
		nl1l0l.width_data = 3,
		nl1l0l.width_sel = 3;
	oper_selector   nl1l1i
	( 
	.data({nl1lOO, nl1O1l, nl1lOl}),
	.o(wire_nl1l1i_o),
	.sel({n1illOi, n1illlO, (~ n1illll)}));
	defparam
		nl1l1i.width_data = 3,
		nl1l1i.width_sel = 3;
	oper_selector   nl1l1l
	( 
	.data({nl1lOl, nl1O1i, nl1lOO}),
	.o(wire_nl1l1l_o),
	.sel({n1illOi, n1illlO, (~ n1illll)}));
	defparam
		nl1l1l.width_data = 3,
		nl1l1l.width_sel = 3;
	oper_selector   nl1l1O
	( 
	.data({nl1lOi, nl1lOO, nl1O1i}),
	.o(wire_nl1l1O_o),
	.sel({n1illOi, n1illlO, (~ n1illll)}));
	defparam
		nl1l1O.width_data = 3,
		nl1l1O.width_sel = 3;
	oper_selector   nllil1l
	( 
	.data({(~ n1i1iiO), wire_nllil0O_dataout, 1'b1}),
	.o(wire_nllil1l_o),
	.sel({n1i1i1O, n1i1i1l, (~ n1i1i1i)}));
	defparam
		nllil1l.width_data = 3,
		nllil1l.width_sel = 3;
	oper_selector   nllil1O
	( 
	.data({n1i1iiO, wire_nllil0l_dataout, 1'b0}),
	.o(wire_nllil1O_o),
	.sel({n1i1i1O, n1i1i1l, (~ n1i1i1i)}));
	defparam
		nllil1O.width_data = 3,
		nllil1O.width_sel = 3;
	oper_selector   nlO00i
	( 
	.data({n1iOliO, wire_nlO0ii_dataout, 1'b0}),
	.o(wire_nlO00i_o),
	.sel({((n1iOl1i22 ^ n1iOl1i21) & nlOi1O), ((n1iOl1l20 ^ n1iOl1l19) & nlOi1i), nlO0OO}));
	defparam
		nlO00i.width_data = 3,
		nlO00i.width_sel = 3;
	oper_selector   nlO00l
	( 
	.data({wire_nlO0ll_dataout, wire_nlO0il_dataout, ((n1iOl1O18 ^ n1iOl1O17) & (~ nlOli1l))}),
	.o(wire_nlO00l_o),
	.sel({nlOi1O, nlOi1i, nlO0OO}));
	defparam
		nlO00l.width_data = 3,
		nlO00l.width_sel = 3;
	oper_selector   nlO01l
	( 
	.data({wire_nlO0iO_dataout, wire_nlO00O_dataout, 1'b0}),
	.o(wire_nlO01l_o),
	.sel({nlOi1O, nlOi1i, nlO0OO}));
	defparam
		nlO01l.width_data = 3,
		nlO01l.width_sel = 3;
	oper_selector   nlO01O
	( 
	.data({wire_nlO0li_dataout, ((n1iOiOO24 ^ n1iOiOO23) & n1iOl0i), nlOli1l}),
	.o(wire_nlO01O_o),
	.sel({nlOi1O, nlOi1i, nlO0OO}));
	defparam
		nlO01O.width_data = 3,
		nlO01O.width_sel = 3;
	oper_selector   nlO1i0i
	( 
	.data({nlOiOOl, gnumber[2], 1'b0, wire_nlO1OOi_o[2]}),
	.o(wire_nlO1i0i_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1i0i.width_data = 4,
		nlO1i0i.width_sel = 4;
	oper_selector   nlO1i0l
	( 
	.data({nlOiOOO, gnumber[3], 1'b0, wire_nlO1OOi_o[3]}),
	.o(wire_nlO1i0l_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1i0l.width_data = 4,
		nlO1i0l.width_sel = 4;
	oper_selector   nlO1i0O
	( 
	.data({nlOl11i, gnumber[4], 1'b0, wire_nlO1OOi_o[4]}),
	.o(wire_nlO1i0O_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1i0O.width_data = 4,
		nlO1i0O.width_sel = 4;
	oper_selector   nlO1i1l
	( 
	.data({nlOiOlO, gnumber[0], 1'b0, wire_nlO1OOi_o[0]}),
	.o(wire_nlO1i1l_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1i1l.width_data = 4,
		nlO1i1l.width_sel = 4;
	oper_selector   nlO1i1O
	( 
	.data({nlOiOOi, gnumber[1], 1'b0, wire_nlO1OOi_o[1]}),
	.o(wire_nlO1i1O_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1i1O.width_data = 4,
		nlO1i1O.width_sel = 4;
	oper_selector   nlO1iii
	( 
	.data({nlOl11l, gnumber[5], 1'b0, wire_nlO1OOi_o[5]}),
	.o(wire_nlO1iii_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1iii.width_data = 4,
		nlO1iii.width_sel = 4;
	oper_selector   nlO1iil
	( 
	.data({nlOl11O, gnumber[6], 1'b0, wire_nlO1OOi_o[6]}),
	.o(wire_nlO1iil_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1iil.width_data = 4,
		nlO1iil.width_sel = 4;
	oper_selector   nlO1iiO
	( 
	.data({nlOl10i, gnumber[7], 1'b0, wire_nlO1OOi_o[7]}),
	.o(wire_nlO1iiO_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1iiO.width_data = 4,
		nlO1iiO.width_sel = 4;
	oper_selector   nlO1ili
	( 
	.data({nlOl10l, gnumber[8], 1'b0, wire_nlO1OOi_o[8]}),
	.o(wire_nlO1ili_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1ili.width_data = 4,
		nlO1ili.width_sel = 4;
	oper_selector   nlO1ill
	( 
	.data({nlOl10O, gnumber[9], 1'b0, wire_nlO1OOi_o[9]}),
	.o(wire_nlO1ill_o),
	.sel({n1i1ilO, wire_nlO010O_dataout, n1i1ill, wire_nlO011l_dataout}));
	defparam
		nlO1ill.width_data = 4,
		nlO1ill.width_sel = 4;
	oper_selector   nlO1iOl
	( 
	.data({nlOl1ii, 1'b0, wire_nlO1OOl_o[0], wire_nlO1OlO_o[1]}),
	.o(wire_nlO1iOl_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1iOl.width_data = 4,
		nlO1iOl.width_sel = 4;
	oper_selector   nlO1iOO
	( 
	.data({nlOl1il, 1'b0, wire_nlO1OOl_o[1], wire_nlO1OlO_o[2]}),
	.o(wire_nlO1iOO_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1iOO.width_data = 4,
		nlO1iOO.width_sel = 4;
	oper_selector   nlO1l0i
	( 
	.data({nlOl1lO, 1'b0, wire_nlO1OOl_o[5], wire_nlO1OlO_o[6]}),
	.o(wire_nlO1l0i_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1l0i.width_data = 4,
		nlO1l0i.width_sel = 4;
	oper_selector   nlO1l0l
	( 
	.data({nlOl1Oi, 1'b0, wire_nlO1OOl_o[6], wire_nlO1OlO_o[7]}),
	.o(wire_nlO1l0l_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1l0l.width_data = 4,
		nlO1l0l.width_sel = 4;
	oper_selector   nlO1l0O
	( 
	.data({nlOl1Ol, 1'b0, wire_nlO1OOl_o[7], wire_nlO1OlO_o[8]}),
	.o(wire_nlO1l0O_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1l0O.width_data = 4,
		nlO1l0O.width_sel = 4;
	oper_selector   nlO1l1i
	( 
	.data({nlOl1iO, 1'b0, wire_nlO1OOl_o[2], wire_nlO1OlO_o[3]}),
	.o(wire_nlO1l1i_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1l1i.width_data = 4,
		nlO1l1i.width_sel = 4;
	oper_selector   nlO1l1l
	( 
	.data({nlOl1li, 1'b0, wire_nlO1OOl_o[3], wire_nlO1OlO_o[4]}),
	.o(wire_nlO1l1l_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1l1l.width_data = 4,
		nlO1l1l.width_sel = 4;
	oper_selector   nlO1l1O
	( 
	.data({nlOl1ll, 1'b0, wire_nlO1OOl_o[4], wire_nlO1OlO_o[5]}),
	.o(wire_nlO1l1O_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1l1O.width_data = 4,
		nlO1l1O.width_sel = 4;
	oper_selector   nlO1lii
	( 
	.data({nlOl1OO, 1'b0, wire_nlO1OOl_o[8], wire_nlO1OlO_o[9]}),
	.o(wire_nlO1lii_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1lii.width_data = 4,
		nlO1lii.width_sel = 4;
	oper_selector   nlO1lil
	( 
	.data({nlOl01i, 1'b0, wire_nlO1OOl_o[9], wire_nlO1OlO_o[10]}),
	.o(wire_nlO1lil_o),
	.sel({n1i1iOi, wire_nlO010O_dataout, wire_nlO011O_dataout, wire_nlO010i_dataout}));
	defparam
		nlO1lil.width_data = 4,
		nlO1lil.width_sel = 4;
	oper_selector   nlO1lli
	( 
	.data({1'b1, 1'b0, nlOiO0O}),
	.o(wire_nlO1lli_o),
	.sel({wire_nlO01il_dataout, (wire_nlO01ii_dataout | wire_nlO010O_dataout), (((wire_nlO010i_dataout | wire_nlO011O_dataout) | wire_nlO011l_dataout) | (~ n1i1l1i))}));
	defparam
		nlO1lli.width_data = 3,
		nlO1lli.width_sel = 3;
	oper_selector   nlO1lOi
	( 
	.data({1'b0, wire_nlO1OOO_o[0], nlOl01l}),
	.o(wire_nlO1lOi_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1lOi.width_data = 3,
		nlO1lOi.width_sel = 3;
	oper_selector   nlO1lOl
	( 
	.data({1'b0, wire_nlO1OOO_o[1], nlOl01O}),
	.o(wire_nlO1lOl_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1lOl.width_data = 3,
		nlO1lOl.width_sel = 3;
	oper_selector   nlO1lOO
	( 
	.data({1'b0, wire_nlO1OOO_o[2], nlOl00i}),
	.o(wire_nlO1lOO_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1lOO.width_data = 3,
		nlO1lOO.width_sel = 3;
	oper_selector   nlO1O0i
	( 
	.data({1'b0, wire_nlO1OOO_o[6], nlOl0il}),
	.o(wire_nlO1O0i_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1O0i.width_data = 3,
		nlO1O0i.width_sel = 3;
	oper_selector   nlO1O0l
	( 
	.data({1'b0, wire_nlO1OOO_o[7], nlOl0iO}),
	.o(wire_nlO1O0l_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1O0l.width_data = 3,
		nlO1O0l.width_sel = 3;
	oper_selector   nlO1O0O
	( 
	.data({1'b0, wire_nlO1OOO_o[8], nlOl0li}),
	.o(wire_nlO1O0O_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1O0O.width_data = 3,
		nlO1O0O.width_sel = 3;
	oper_selector   nlO1O1i
	( 
	.data({1'b0, wire_nlO1OOO_o[3], nlOl00l}),
	.o(wire_nlO1O1i_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1O1i.width_data = 3,
		nlO1O1i.width_sel = 3;
	oper_selector   nlO1O1l
	( 
	.data({1'b0, wire_nlO1OOO_o[4], nlOl00O}),
	.o(wire_nlO1O1l_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1O1l.width_data = 3,
		nlO1O1l.width_sel = 3;
	oper_selector   nlO1O1O
	( 
	.data({1'b0, wire_nlO1OOO_o[5], nlOl0ii}),
	.o(wire_nlO1O1O_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1O1O.width_data = 3,
		nlO1O1O.width_sel = 3;
	oper_selector   nlO1Oii
	( 
	.data({1'b0, wire_nlO1OOO_o[9], nlOl0ll}),
	.o(wire_nlO1Oii_o),
	.sel({wire_nlO01il_dataout, wire_nlO01ii_dataout, n1i1iOl}));
	defparam
		nlO1Oii.width_data = 3,
		nlO1Oii.width_sel = 3;
	oper_selector   nlO1OiO
	( 
	.data({1'b0, nlOiOii, 1'b1}),
	.o(wire_nlO1OiO_o),
	.sel({wire_nlO01il_dataout, n1i1iOO, wire_nlO010O_dataout}));
	defparam
		nlO1OiO.width_data = 3,
		nlO1OiO.width_sel = 3;
	assign
		a1a2_k1k2_flag = {wire_niiOl_dataout, wire_niiOi_dataout, wire_niilO_dataout, wire_niill_dataout},
		cg_syncpat = {wire_n1O_dataout, wire_n1l_dataout},
		n10000i = ((((((((~ ((~ comp_pat[0]) ^ nlll0Ol)) & (~ ((~ comp_pat[1]) ^ nlll0OO))) & (~ ((~ comp_pat[2]) ^ nllli1i))) & (~ ((~ comp_pat[3]) ^ nllli1l))) & (~ ((~ comp_pat[4]) ^ nllli1O))) & (~ ((~ comp_pat[5]) ^ nllli0i))) & (~ ((~ comp_pat[6]) ^ nllliiO))) & (~ ((~ comp_pat[7]) ^ nlllili))),
		n10000l = ((comp_pat_porn & n1000ii) | n10000O),
		n10000O = ((((((((~ (comp_pat[0] ^ nlll0Oi)) & (~ (comp_pat[1] ^ nlll0Ol))) & (~ (comp_pat[2] ^ nlll0OO))) & (~ (comp_pat[3] ^ nllli1i))) & (~ (comp_pat[4] ^ nllli1l))) & (~ (comp_pat[5] ^ nllli1O))) & (~ (comp_pat[6] ^ nllli0i))) & (~ (comp_pat[7] ^ nllliiO))),
		n10001i = ((((((((~ ((~ comp_pat[0]) ^ nlll0OO)) & (~ ((~ comp_pat[1]) ^ nllli1i))) & (~ ((~ comp_pat[2]) ^ nllli1l))) & (~ ((~ comp_pat[3]) ^ nllli1O))) & (~ ((~ comp_pat[4]) ^ nllli0i))) & (~ ((~ comp_pat[5]) ^ nllliiO))) & (~ ((~ comp_pat[6]) ^ nlllili))) & (~ ((~ comp_pat[7]) ^ nlllill))),
		n10001l = ((comp_pat_porn & n10000i) | n10001O),
		n10001O = ((((((((~ (comp_pat[0] ^ nlll0Ol)) & (~ (comp_pat[1] ^ nlll0OO))) & (~ (comp_pat[2] ^ nllli1i))) & (~ (comp_pat[3] ^ nllli1l))) & (~ (comp_pat[4] ^ nllli1O))) & (~ (comp_pat[5] ^ nllli0i))) & (~ (comp_pat[6] ^ nllliiO))) & (~ (comp_pat[7] ^ nlllili))),
		n1000ii = ((((((((~ ((~ comp_pat[0]) ^ nlll0Oi)) & (~ ((~ comp_pat[1]) ^ nlll0Ol))) & (~ ((~ comp_pat[2]) ^ nlll0OO))) & (~ ((~ comp_pat[3]) ^ nllli1i))) & (~ ((~ comp_pat[4]) ^ nllli1l))) & (~ ((~ comp_pat[5]) ^ nllli1O))) & (~ ((~ comp_pat[6]) ^ nllli0i))) & (~ ((~ comp_pat[7]) ^ nllliiO))),
		n1000il = ((comp_pat_porn & n1000li) | n1000iO),
		n1000iO = ((((((((~ (comp_pat[0] ^ nlll0lO)) & (~ (comp_pat[1] ^ nlll0Oi))) & (~ (comp_pat[2] ^ nlll0Ol))) & (~ (comp_pat[3] ^ nlll0OO))) & (~ (comp_pat[4] ^ nllli1i))) & (~ (comp_pat[5] ^ nllli1l))) & (~ (comp_pat[6] ^ nllli1O))) & (~ (comp_pat[7] ^ nllli0i))),
		n1000li = ((((((((~ ((~ comp_pat[0]) ^ nlll0lO)) & (~ ((~ comp_pat[1]) ^ nlll0Oi))) & (~ ((~ comp_pat[2]) ^ nlll0Ol))) & (~ ((~ comp_pat[3]) ^ nlll0OO))) & (~ ((~ comp_pat[4]) ^ nllli1i))) & (~ ((~ comp_pat[5]) ^ nllli1l))) & (~ ((~ comp_pat[6]) ^ nllli1O))) & (~ ((~ comp_pat[7]) ^ nllli0i))),
		n1000ll = ((comp_pat_porn & n1000Oi) | n1000lO),
		n1000lO = ((((((((~ (comp_pat[0] ^ nlll0ll)) & (~ (comp_pat[1] ^ nlll0lO))) & (~ (comp_pat[2] ^ nlll0Oi))) & (~ (comp_pat[3] ^ nlll0Ol))) & (~ (comp_pat[4] ^ nlll0OO))) & (~ (comp_pat[5] ^ nllli1i))) & (~ (comp_pat[6] ^ nllli1l))) & (~ (comp_pat[7] ^ nllli1O))),
		n1000Oi = ((((((((~ ((~ comp_pat[0]) ^ nlll0ll)) & (~ ((~ comp_pat[1]) ^ nlll0lO))) & (~ ((~ comp_pat[2]) ^ nlll0Oi))) & (~ ((~ comp_pat[3]) ^ nlll0Ol))) & (~ ((~ comp_pat[4]) ^ nlll0OO))) & (~ ((~ comp_pat[5]) ^ nllli1i))) & (~ ((~ comp_pat[6]) ^ nllli1l))) & (~ ((~ comp_pat[7]) ^ nllli1O))),
		n1000Ol = ((comp_pat_porn & n100i1i) | n1000OO),
		n1000OO = ((((((((~ (comp_pat[0] ^ nlll0li)) & (~ (comp_pat[1] ^ nlll0ll))) & (~ (comp_pat[2] ^ nlll0lO))) & (~ (comp_pat[3] ^ nlll0Oi))) & (~ (comp_pat[4] ^ nlll0Ol))) & (~ (comp_pat[5] ^ nlll0OO))) & (~ (comp_pat[6] ^ nllli1i))) & (~ (comp_pat[7] ^ nllli1l))),
		n10010i = ((((((((~ ((~ comp_pat[0]) ^ nllli0i)) & (~ ((~ comp_pat[1]) ^ nllliiO))) & (~ ((~ comp_pat[2]) ^ nlllili))) & (~ ((~ comp_pat[3]) ^ nlllill))) & (~ ((~ comp_pat[4]) ^ nlllilO))) & (~ ((~ comp_pat[5]) ^ nllliOi))) & (~ ((~ comp_pat[6]) ^ nllliOl))) & (~ ((~ comp_pat[7]) ^ nllliOO))),
		n10010l = ((comp_pat_porn & n1001ii) | n10010O),
		n10010O = ((((((((~ (comp_pat[0] ^ nllli1O)) & (~ (comp_pat[1] ^ nllli0i))) & (~ (comp_pat[2] ^ nllliiO))) & (~ (comp_pat[3] ^ nlllili))) & (~ (comp_pat[4] ^ nlllill))) & (~ (comp_pat[5] ^ nlllilO))) & (~ (comp_pat[6] ^ nllliOi))) & (~ (comp_pat[7] ^ nllliOl))),
		n10011i = ((((((((~ ((~ comp_pat[0]) ^ nllliiO)) & (~ ((~ comp_pat[1]) ^ nlllili))) & (~ ((~ comp_pat[2]) ^ nlllill))) & (~ ((~ comp_pat[3]) ^ nlllilO))) & (~ ((~ comp_pat[4]) ^ nllliOi))) & (~ ((~ comp_pat[5]) ^ nllliOl))) & (~ ((~ comp_pat[6]) ^ nllliOO))) & (~ ((~ comp_pat[7]) ^ nllll1i))),
		n10011l = ((comp_pat_porn & n10010i) | n10011O),
		n10011O = ((((((((~ (comp_pat[0] ^ nllli0i)) & (~ (comp_pat[1] ^ nllliiO))) & (~ (comp_pat[2] ^ nlllili))) & (~ (comp_pat[3] ^ nlllill))) & (~ (comp_pat[4] ^ nlllilO))) & (~ (comp_pat[5] ^ nllliOi))) & (~ (comp_pat[6] ^ nllliOl))) & (~ (comp_pat[7] ^ nllliOO))),
		n1001ii = ((((((((~ ((~ comp_pat[0]) ^ nllli1O)) & (~ ((~ comp_pat[1]) ^ nllli0i))) & (~ ((~ comp_pat[2]) ^ nllliiO))) & (~ ((~ comp_pat[3]) ^ nlllili))) & (~ ((~ comp_pat[4]) ^ nlllill))) & (~ ((~ comp_pat[5]) ^ nlllilO))) & (~ ((~ comp_pat[6]) ^ nllliOi))) & (~ ((~ comp_pat[7]) ^ nllliOl))),
		n1001il = ((comp_pat_porn & n1001li) | n1001iO),
		n1001iO = ((((((((~ (comp_pat[0] ^ nllli1l)) & (~ (comp_pat[1] ^ nllli1O))) & (~ (comp_pat[2] ^ nllli0i))) & (~ (comp_pat[3] ^ nllliiO))) & (~ (comp_pat[4] ^ nlllili))) & (~ (comp_pat[5] ^ nlllill))) & (~ (comp_pat[6] ^ nlllilO))) & (~ (comp_pat[7] ^ nllliOi))),
		n1001li = ((((((((~ ((~ comp_pat[0]) ^ nllli1l)) & (~ ((~ comp_pat[1]) ^ nllli1O))) & (~ ((~ comp_pat[2]) ^ nllli0i))) & (~ ((~ comp_pat[3]) ^ nllliiO))) & (~ ((~ comp_pat[4]) ^ nlllili))) & (~ ((~ comp_pat[5]) ^ nlllill))) & (~ ((~ comp_pat[6]) ^ nlllilO))) & (~ ((~ comp_pat[7]) ^ nllliOi))),
		n1001ll = ((comp_pat_porn & n1001Oi) | n1001lO),
		n1001lO = ((((((((~ (comp_pat[0] ^ nllli1i)) & (~ (comp_pat[1] ^ nllli1l))) & (~ (comp_pat[2] ^ nllli1O))) & (~ (comp_pat[3] ^ nllli0i))) & (~ (comp_pat[4] ^ nllliiO))) & (~ (comp_pat[5] ^ nlllili))) & (~ (comp_pat[6] ^ nlllill))) & (~ (comp_pat[7] ^ nlllilO))),
		n1001Oi = ((((((((~ ((~ comp_pat[0]) ^ nllli1i)) & (~ ((~ comp_pat[1]) ^ nllli1l))) & (~ ((~ comp_pat[2]) ^ nllli1O))) & (~ ((~ comp_pat[3]) ^ nllli0i))) & (~ ((~ comp_pat[4]) ^ nllliiO))) & (~ ((~ comp_pat[5]) ^ nlllili))) & (~ ((~ comp_pat[6]) ^ nlllill))) & (~ ((~ comp_pat[7]) ^ nlllilO))),
		n1001Ol = ((comp_pat_porn & n10001i) | n1001OO),
		n1001OO = ((((((((~ (comp_pat[0] ^ nlll0OO)) & (~ (comp_pat[1] ^ nllli1i))) & (~ (comp_pat[2] ^ nllli1l))) & (~ (comp_pat[3] ^ nllli1O))) & (~ (comp_pat[4] ^ nllli0i))) & (~ (comp_pat[5] ^ nllliiO))) & (~ (comp_pat[6] ^ nlllili))) & (~ (comp_pat[7] ^ nlllill))),
		n100i0i = ((((((((~ ((~ comp_pat[0]) ^ nlll0iO)) & (~ ((~ comp_pat[1]) ^ nlll0li))) & (~ ((~ comp_pat[2]) ^ nlll0ll))) & (~ ((~ comp_pat[3]) ^ nlll0lO))) & (~ ((~ comp_pat[4]) ^ nlll0Oi))) & (~ ((~ comp_pat[5]) ^ nlll0Ol))) & (~ ((~ comp_pat[6]) ^ nlll0OO))) & (~ ((~ comp_pat[7]) ^ nllli1i))),
		n100i0l = ((comp_pat_porn & n100iii) | n100i0O),
		n100i0O = ((((((((~ (comp_pat[0] ^ nlll0il)) & (~ (comp_pat[1] ^ nlll0iO))) & (~ (comp_pat[2] ^ nlll0li))) & (~ (comp_pat[3] ^ nlll0ll))) & (~ (comp_pat[4] ^ nlll0lO))) & (~ (comp_pat[5] ^ nlll0Oi))) & (~ (comp_pat[6] ^ nlll0Ol))) & (~ (comp_pat[7] ^ nlll0OO))),
		n100i1i = ((((((((~ ((~ comp_pat[0]) ^ nlll0li)) & (~ ((~ comp_pat[1]) ^ nlll0ll))) & (~ ((~ comp_pat[2]) ^ nlll0lO))) & (~ ((~ comp_pat[3]) ^ nlll0Oi))) & (~ ((~ comp_pat[4]) ^ nlll0Ol))) & (~ ((~ comp_pat[5]) ^ nlll0OO))) & (~ ((~ comp_pat[6]) ^ nllli1i))) & (~ ((~ comp_pat[7]) ^ nllli1l))),
		n100i1l = ((comp_pat_porn & n100i0i) | n100i1O),
		n100i1O = ((((((((~ (comp_pat[0] ^ nlll0iO)) & (~ (comp_pat[1] ^ nlll0li))) & (~ (comp_pat[2] ^ nlll0ll))) & (~ (comp_pat[3] ^ nlll0lO))) & (~ (comp_pat[4] ^ nlll0Oi))) & (~ (comp_pat[5] ^ nlll0Ol))) & (~ (comp_pat[6] ^ nlll0OO))) & (~ (comp_pat[7] ^ nllli1i))),
		n100iii = ((((((((~ ((~ comp_pat[0]) ^ nlll0il)) & (~ ((~ comp_pat[1]) ^ nlll0iO))) & (~ ((~ comp_pat[2]) ^ nlll0li))) & (~ ((~ comp_pat[3]) ^ nlll0ll))) & (~ ((~ comp_pat[4]) ^ nlll0lO))) & (~ ((~ comp_pat[5]) ^ nlll0Oi))) & (~ ((~ comp_pat[6]) ^ nlll0Ol))) & (~ ((~ comp_pat[7]) ^ nlll0OO))),
		n100iil = ((comp_pat_porn & n100ili) | n100iiO),
		n100iiO = ((((((((~ (comp_pat[0] ^ nlll0ii)) & (~ (comp_pat[1] ^ nlll0il))) & (~ (comp_pat[2] ^ nlll0iO))) & (~ (comp_pat[3] ^ nlll0li))) & (~ (comp_pat[4] ^ nlll0ll))) & (~ (comp_pat[5] ^ nlll0lO))) & (~ (comp_pat[6] ^ nlll0Oi))) & (~ (comp_pat[7] ^ nlll0Ol))),
		n100ili = ((((((((~ ((~ comp_pat[0]) ^ nlll0ii)) & (~ ((~ comp_pat[1]) ^ nlll0il))) & (~ ((~ comp_pat[2]) ^ nlll0iO))) & (~ ((~ comp_pat[3]) ^ nlll0li))) & (~ ((~ comp_pat[4]) ^ nlll0ll))) & (~ ((~ comp_pat[5]) ^ nlll0lO))) & (~ ((~ comp_pat[6]) ^ nlll0Oi))) & (~ ((~ comp_pat[7]) ^ nlll0Ol))),
		n100ill = ((comp_pat_porn & n100iOi) | n100ilO),
		n100ilO = ((((((((~ (comp_pat[0] ^ nlll00O)) & (~ (comp_pat[1] ^ nlll0ii))) & (~ (comp_pat[2] ^ nlll0il))) & (~ (comp_pat[3] ^ nlll0iO))) & (~ (comp_pat[4] ^ nlll0li))) & (~ (comp_pat[5] ^ nlll0ll))) & (~ (comp_pat[6] ^ nlll0lO))) & (~ (comp_pat[7] ^ nlll0Oi))),
		n100iOi = ((((((((~ ((~ comp_pat[0]) ^ nlll00O)) & (~ ((~ comp_pat[1]) ^ nlll0ii))) & (~ ((~ comp_pat[2]) ^ nlll0il))) & (~ ((~ comp_pat[3]) ^ nlll0iO))) & (~ ((~ comp_pat[4]) ^ nlll0li))) & (~ ((~ comp_pat[5]) ^ nlll0ll))) & (~ ((~ comp_pat[6]) ^ nlll0lO))) & (~ ((~ comp_pat[7]) ^ nlll0Oi))),
		n100iOl = ((comp_pat_porn & n100l1i) | n100iOO),
		n100iOO = ((((((((~ (comp_pat[0] ^ nlll00l)) & (~ (comp_pat[1] ^ nlll00O))) & (~ (comp_pat[2] ^ nlll0ii))) & (~ (comp_pat[3] ^ nlll0il))) & (~ (comp_pat[4] ^ nlll0iO))) & (~ (comp_pat[5] ^ nlll0li))) & (~ (comp_pat[6] ^ nlll0ll))) & (~ (comp_pat[7] ^ nlll0lO))),
		n100l0i = ((((((((((~ (comp_pat[20] ^ nllllOl)) & (~ (comp_pat[21] ^ nllllOO))) & (~ (comp_pat[22] ^ nlllO1i))) & (~ (comp_pat[23] ^ nlllO1l))) & (~ (comp_pat[24] ^ nlllO1O))) & (~ (comp_pat[25] ^ nlllO0i))) & (~ (comp_pat[26] ^ nlllO0l))) & (~ (comp_pat[27] ^ nlllO0O))) & (~ (comp_pat[28] ^ nlllOii))) & (~ (comp_pat[29] ^ nlllOil))),
		n100l0l = ((((((((((~ ((~ comp_pat[20]) ^ nllllOl)) & (~ ((~ comp_pat[21]) ^ nllllOO))) & (~ ((~ comp_pat[22]) ^ nlllO1i))) & (~ ((~ comp_pat[23]) ^ nlllO1l))) & (~ ((~ comp_pat[24]) ^ nlllO1O))) & (~ ((~ comp_pat[25]) ^ nlllO0i))) & (~ ((~ comp_pat[26]) ^ nlllO0l))) & (~ ((~ comp_pat[27]) ^ nlllO0O))) & (~ ((~ comp_pat[28]) ^ nlllOii))) & (~ ((~ comp_pat[29]) ^ nlllOil))),
		n100l0O = ((((((((((~ (comp_pat[30] ^ nlllOiO)) & (~ (comp_pat[31] ^ nlllOli))) & (~ (comp_pat[32] ^ nlllOll))) & (~ (comp_pat[33] ^ nlllOlO))) & (~ (comp_pat[34] ^ nlllOOi))) & (~ (comp_pat[35] ^ nlllOOl))) & (~ (comp_pat[36] ^ nlllOOO))) & (~ (comp_pat[37] ^ nllO11i))) & (~ (comp_pat[38] ^ nllO11l))) & (~ (comp_pat[39] ^ nllO11O))),
		n100l1i = ((((((((~ ((~ comp_pat[0]) ^ nlll00l)) & (~ ((~ comp_pat[1]) ^ nlll00O))) & (~ ((~ comp_pat[2]) ^ nlll0ii))) & (~ ((~ comp_pat[3]) ^ nlll0il))) & (~ ((~ comp_pat[4]) ^ nlll0iO))) & (~ ((~ comp_pat[5]) ^ nlll0li))) & (~ ((~ comp_pat[6]) ^ nlll0ll))) & (~ ((~ comp_pat[7]) ^ nlll0lO))),
		n100l1l = (((((((((((((((((((n10iOil | n10iO1O) | n10ilOi) | n10ilil) | n10il1O) | n10iiOi) | n10iiil) | n10ii1O) | n10i0Oi) | n10i0il) | n10i01O) | n10i1Oi) | n10i1il) | n10i11O) | n100OOi) | n100Oil) | n100O1O) | n100lOi) | n100lil) | n100l1O),
		n100l1O = (n10iOOl & (((comp_pat_porn & n100lii) | n100l0O) & ((comp_pat_porn & n100l0l) | n100l0i))),
		n100lii = ((((((((((~ ((~ comp_pat[30]) ^ nlllOiO)) & (~ ((~ comp_pat[31]) ^ nlllOli))) & (~ ((~ comp_pat[32]) ^ nlllOll))) & (~ ((~ comp_pat[33]) ^ nlllOlO))) & (~ ((~ comp_pat[34]) ^ nlllOOi))) & (~ ((~ comp_pat[35]) ^ nlllOOl))) & (~ ((~ comp_pat[36]) ^ nlllOOO))) & (~ ((~ comp_pat[37]) ^ nllO11i))) & (~ ((~ comp_pat[38]) ^ nllO11l))) & (~ ((~ comp_pat[39]) ^ nllO11O))),
		n100lil = (n10l11l & (((comp_pat_porn & n100llO) | n100lll) & ((comp_pat_porn & n100lli) | n100liO))),
		n100liO = ((((((((((~ (comp_pat[20] ^ nllllOi)) & (~ (comp_pat[21] ^ nllllOl))) & (~ (comp_pat[22] ^ nllllOO))) & (~ (comp_pat[23] ^ nlllO1i))) & (~ (comp_pat[24] ^ nlllO1l))) & (~ (comp_pat[25] ^ nlllO1O))) & (~ (comp_pat[26] ^ nlllO0i))) & (~ (comp_pat[27] ^ nlllO0l))) & (~ (comp_pat[28] ^ nlllO0O))) & (~ (comp_pat[29] ^ nlllOii))),
		n100lli = ((((((((((~ ((~ comp_pat[20]) ^ nllllOi)) & (~ ((~ comp_pat[21]) ^ nllllOl))) & (~ ((~ comp_pat[22]) ^ nllllOO))) & (~ ((~ comp_pat[23]) ^ nlllO1i))) & (~ ((~ comp_pat[24]) ^ nlllO1l))) & (~ ((~ comp_pat[25]) ^ nlllO1O))) & (~ ((~ comp_pat[26]) ^ nlllO0i))) & (~ ((~ comp_pat[27]) ^ nlllO0l))) & (~ ((~ comp_pat[28]) ^ nlllO0O))) & (~ ((~ comp_pat[29]) ^ nlllOii))),
		n100lll = ((((((((((~ (comp_pat[30] ^ nlllOil)) & (~ (comp_pat[31] ^ nlllOiO))) & (~ (comp_pat[32] ^ nlllOli))) & (~ (comp_pat[33] ^ nlllOll))) & (~ (comp_pat[34] ^ nlllOlO))) & (~ (comp_pat[35] ^ nlllOOi))) & (~ (comp_pat[36] ^ nlllOOl))) & (~ (comp_pat[37] ^ nlllOOO))) & (~ (comp_pat[38] ^ nllO11i))) & (~ (comp_pat[39] ^ nllO11l))),
		n100llO = ((((((((((~ ((~ comp_pat[30]) ^ nlllOil)) & (~ ((~ comp_pat[31]) ^ nlllOiO))) & (~ ((~ comp_pat[32]) ^ nlllOli))) & (~ ((~ comp_pat[33]) ^ nlllOll))) & (~ ((~ comp_pat[34]) ^ nlllOlO))) & (~ ((~ comp_pat[35]) ^ nlllOOi))) & (~ ((~ comp_pat[36]) ^ nlllOOl))) & (~ ((~ comp_pat[37]) ^ nlllOOO))) & (~ ((~ comp_pat[38]) ^ nllO11i))) & (~ ((~ comp_pat[39]) ^ nllO11l))),
		n100lOi = (n10l10l & (((comp_pat_porn & n100O1l) | n100O1i) & ((comp_pat_porn & n100lOO) | n100lOl))),
		n100lOl = ((((((((((~ (comp_pat[20] ^ nlllllO)) & (~ (comp_pat[21] ^ nllllOi))) & (~ (comp_pat[22] ^ nllllOl))) & (~ (comp_pat[23] ^ nllllOO))) & (~ (comp_pat[24] ^ nlllO1i))) & (~ (comp_pat[25] ^ nlllO1l))) & (~ (comp_pat[26] ^ nlllO1O))) & (~ (comp_pat[27] ^ nlllO0i))) & (~ (comp_pat[28] ^ nlllO0l))) & (~ (comp_pat[29] ^ nlllO0O))),
		n100lOO = ((((((((((~ ((~ comp_pat[20]) ^ nlllllO)) & (~ ((~ comp_pat[21]) ^ nllllOi))) & (~ ((~ comp_pat[22]) ^ nllllOl))) & (~ ((~ comp_pat[23]) ^ nllllOO))) & (~ ((~ comp_pat[24]) ^ nlllO1i))) & (~ ((~ comp_pat[25]) ^ nlllO1l))) & (~ ((~ comp_pat[26]) ^ nlllO1O))) & (~ ((~ comp_pat[27]) ^ nlllO0i))) & (~ ((~ comp_pat[28]) ^ nlllO0l))) & (~ ((~ comp_pat[29]) ^ nlllO0O))),
		n100O0i = ((((((((((~ (comp_pat[20] ^ nllllll)) & (~ (comp_pat[21] ^ nlllllO))) & (~ (comp_pat[22] ^ nllllOi))) & (~ (comp_pat[23] ^ nllllOl))) & (~ (comp_pat[24] ^ nllllOO))) & (~ (comp_pat[25] ^ nlllO1i))) & (~ (comp_pat[26] ^ nlllO1l))) & (~ (comp_pat[27] ^ nlllO1O))) & (~ (comp_pat[28] ^ nlllO0i))) & (~ (comp_pat[29] ^ nlllO0l))),
		n100O0l = ((((((((((~ ((~ comp_pat[20]) ^ nllllll)) & (~ ((~ comp_pat[21]) ^ nlllllO))) & (~ ((~ comp_pat[22]) ^ nllllOi))) & (~ ((~ comp_pat[23]) ^ nllllOl))) & (~ ((~ comp_pat[24]) ^ nllllOO))) & (~ ((~ comp_pat[25]) ^ nlllO1i))) & (~ ((~ comp_pat[26]) ^ nlllO1l))) & (~ ((~ comp_pat[27]) ^ nlllO1O))) & (~ ((~ comp_pat[28]) ^ nlllO0i))) & (~ ((~ comp_pat[29]) ^ nlllO0l))),
		n100O0O = ((((((((((~ (comp_pat[30] ^ nlllO0O)) & (~ (comp_pat[31] ^ nlllOii))) & (~ (comp_pat[32] ^ nlllOil))) & (~ (comp_pat[33] ^ nlllOiO))) & (~ (comp_pat[34] ^ nlllOli))) & (~ (comp_pat[35] ^ nlllOll))) & (~ (comp_pat[36] ^ nlllOlO))) & (~ (comp_pat[37] ^ nlllOOi))) & (~ (comp_pat[38] ^ nlllOOl))) & (~ (comp_pat[39] ^ nlllOOO))),
		n100O1i = ((((((((((~ (comp_pat[30] ^ nlllOii)) & (~ (comp_pat[31] ^ nlllOil))) & (~ (comp_pat[32] ^ nlllOiO))) & (~ (comp_pat[33] ^ nlllOli))) & (~ (comp_pat[34] ^ nlllOll))) & (~ (comp_pat[35] ^ nlllOlO))) & (~ (comp_pat[36] ^ nlllOOi))) & (~ (comp_pat[37] ^ nlllOOl))) & (~ (comp_pat[38] ^ nlllOOO))) & (~ (comp_pat[39] ^ nllO11i))),
		n100O1l = ((((((((((~ ((~ comp_pat[30]) ^ nlllOii)) & (~ ((~ comp_pat[31]) ^ nlllOil))) & (~ ((~ comp_pat[32]) ^ nlllOiO))) & (~ ((~ comp_pat[33]) ^ nlllOli))) & (~ ((~ comp_pat[34]) ^ nlllOll))) & (~ ((~ comp_pat[35]) ^ nlllOlO))) & (~ ((~ comp_pat[36]) ^ nlllOOi))) & (~ ((~ comp_pat[37]) ^ nlllOOl))) & (~ ((~ comp_pat[38]) ^ nlllOOO))) & (~ ((~ comp_pat[39]) ^ nllO11i))),
		n100O1O = (n10l1il & (((comp_pat_porn & n100Oii) | n100O0O) & ((comp_pat_porn & n100O0l) | n100O0i))),
		n100Oii = ((((((((((~ ((~ comp_pat[30]) ^ nlllO0O)) & (~ ((~ comp_pat[31]) ^ nlllOii))) & (~ ((~ comp_pat[32]) ^ nlllOil))) & (~ ((~ comp_pat[33]) ^ nlllOiO))) & (~ ((~ comp_pat[34]) ^ nlllOli))) & (~ ((~ comp_pat[35]) ^ nlllOll))) & (~ ((~ comp_pat[36]) ^ nlllOlO))) & (~ ((~ comp_pat[37]) ^ nlllOOi))) & (~ ((~ comp_pat[38]) ^ nlllOOl))) & (~ ((~ comp_pat[39]) ^ nlllOOO))),
		n100Oil = (n10l1ll & (((comp_pat_porn & n100OlO) | n100Oll) & ((comp_pat_porn & n100Oli) | n100OiO))),
		n100OiO = ((((((((((~ (comp_pat[20] ^ nllllli)) & (~ (comp_pat[21] ^ nllllll))) & (~ (comp_pat[22] ^ nlllllO))) & (~ (comp_pat[23] ^ nllllOi))) & (~ (comp_pat[24] ^ nllllOl))) & (~ (comp_pat[25] ^ nllllOO))) & (~ (comp_pat[26] ^ nlllO1i))) & (~ (comp_pat[27] ^ nlllO1l))) & (~ (comp_pat[28] ^ nlllO1O))) & (~ (comp_pat[29] ^ nlllO0i))),
		n100Oli = ((((((((((~ ((~ comp_pat[20]) ^ nllllli)) & (~ ((~ comp_pat[21]) ^ nllllll))) & (~ ((~ comp_pat[22]) ^ nlllllO))) & (~ ((~ comp_pat[23]) ^ nllllOi))) & (~ ((~ comp_pat[24]) ^ nllllOl))) & (~ ((~ comp_pat[25]) ^ nllllOO))) & (~ ((~ comp_pat[26]) ^ nlllO1i))) & (~ ((~ comp_pat[27]) ^ nlllO1l))) & (~ ((~ comp_pat[28]) ^ nlllO1O))) & (~ ((~ comp_pat[29]) ^ nlllO0i))),
		n100Oll = ((((((((((~ (comp_pat[30] ^ nlllO0l)) & (~ (comp_pat[31] ^ nlllO0O))) & (~ (comp_pat[32] ^ nlllOii))) & (~ (comp_pat[33] ^ nlllOil))) & (~ (comp_pat[34] ^ nlllOiO))) & (~ (comp_pat[35] ^ nlllOli))) & (~ (comp_pat[36] ^ nlllOll))) & (~ (comp_pat[37] ^ nlllOlO))) & (~ (comp_pat[38] ^ nlllOOi))) & (~ (comp_pat[39] ^ nlllOOl))),
		n100OlO = ((((((((((~ ((~ comp_pat[30]) ^ nlllO0l)) & (~ ((~ comp_pat[31]) ^ nlllO0O))) & (~ ((~ comp_pat[32]) ^ nlllOii))) & (~ ((~ comp_pat[33]) ^ nlllOil))) & (~ ((~ comp_pat[34]) ^ nlllOiO))) & (~ ((~ comp_pat[35]) ^ nlllOli))) & (~ ((~ comp_pat[36]) ^ nlllOll))) & (~ ((~ comp_pat[37]) ^ nlllOlO))) & (~ ((~ comp_pat[38]) ^ nlllOOi))) & (~ ((~ comp_pat[39]) ^ nlllOOl))),
		n100OOi = (n10l1Ol & (((comp_pat_porn & n10i11l) | n10i11i) & ((comp_pat_porn & n100OOO) | n100OOl))),
		n100OOl = ((((((((((~ (comp_pat[20] ^ nlllliO)) & (~ (comp_pat[21] ^ nllllli))) & (~ (comp_pat[22] ^ nllllll))) & (~ (comp_pat[23] ^ nlllllO))) & (~ (comp_pat[24] ^ nllllOi))) & (~ (comp_pat[25] ^ nllllOl))) & (~ (comp_pat[26] ^ nllllOO))) & (~ (comp_pat[27] ^ nlllO1i))) & (~ (comp_pat[28] ^ nlllO1l))) & (~ (comp_pat[29] ^ nlllO1O))),
		n100OOO = ((((((((((~ ((~ comp_pat[20]) ^ nlllliO)) & (~ ((~ comp_pat[21]) ^ nllllli))) & (~ ((~ comp_pat[22]) ^ nllllll))) & (~ ((~ comp_pat[23]) ^ nlllllO))) & (~ ((~ comp_pat[24]) ^ nllllOi))) & (~ ((~ comp_pat[25]) ^ nllllOl))) & (~ ((~ comp_pat[26]) ^ nllllOO))) & (~ ((~ comp_pat[27]) ^ nlllO1i))) & (~ ((~ comp_pat[28]) ^ nlllO1l))) & (~ ((~ comp_pat[29]) ^ nlllO1O))),
		n10100i = (n101Oli & (((comp_pat_porn & n1010il) | n1010ii) & ((comp_pat_porn & n10100O) | n10100l))),
		n10100l = ((((((((~ (comp_pat[16] ^ nlllili)) & (~ (comp_pat[17] ^ nlllill))) & (~ (comp_pat[18] ^ nlllilO))) & (~ (comp_pat[19] ^ nllliOi))) & (~ (comp_pat[20] ^ nllliOl))) & (~ (comp_pat[21] ^ nllliOO))) & (~ (comp_pat[22] ^ nllll1i))) & (~ (comp_pat[23] ^ nllll1l))),
		n10100O = ((((((((~ ((~ comp_pat[16]) ^ nlllili)) & (~ ((~ comp_pat[17]) ^ nlllill))) & (~ ((~ comp_pat[18]) ^ nlllilO))) & (~ ((~ comp_pat[19]) ^ nllliOi))) & (~ ((~ comp_pat[20]) ^ nllliOl))) & (~ ((~ comp_pat[21]) ^ nllliOO))) & (~ ((~ comp_pat[22]) ^ nllll1i))) & (~ ((~ comp_pat[23]) ^ nllll1l))),
		n10101i = ((((((((~ ((~ comp_pat[16]) ^ nlllill)) & (~ ((~ comp_pat[17]) ^ nlllilO))) & (~ ((~ comp_pat[18]) ^ nllliOi))) & (~ ((~ comp_pat[19]) ^ nllliOl))) & (~ ((~ comp_pat[20]) ^ nllliOO))) & (~ ((~ comp_pat[21]) ^ nllll1i))) & (~ ((~ comp_pat[22]) ^ nllll1l))) & (~ ((~ comp_pat[23]) ^ nllll1O))),
		n10101l = ((((((((~ (comp_pat[24] ^ nllll0i)) & (~ (comp_pat[25] ^ nllll0l))) & (~ (comp_pat[26] ^ nllll0O))) & (~ (comp_pat[27] ^ nllllii))) & (~ (comp_pat[28] ^ nllllil))) & (~ (comp_pat[29] ^ nlllliO))) & (~ (comp_pat[30] ^ nllllOl))) & (~ (comp_pat[31] ^ nllllOO))),
		n10101O = ((((((((~ ((~ comp_pat[24]) ^ nllll0i)) & (~ ((~ comp_pat[25]) ^ nllll0l))) & (~ ((~ comp_pat[26]) ^ nllll0O))) & (~ ((~ comp_pat[27]) ^ nllllii))) & (~ ((~ comp_pat[28]) ^ nllllil))) & (~ ((~ comp_pat[29]) ^ nlllliO))) & (~ ((~ comp_pat[30]) ^ nllllOl))) & (~ ((~ comp_pat[31]) ^ nllllOO))),
		n1010ii = ((((((((~ (comp_pat[24] ^ nllll1O)) & (~ (comp_pat[25] ^ nllll0i))) & (~ (comp_pat[26] ^ nllll0l))) & (~ (comp_pat[27] ^ nllll0O))) & (~ (comp_pat[28] ^ nllllii))) & (~ (comp_pat[29] ^ nllllil))) & (~ (comp_pat[30] ^ nlllliO))) & (~ (comp_pat[31] ^ nllllOl))),
		n1010il = ((((((((~ ((~ comp_pat[24]) ^ nllll1O)) & (~ ((~ comp_pat[25]) ^ nllll0i))) & (~ ((~ comp_pat[26]) ^ nllll0l))) & (~ ((~ comp_pat[27]) ^ nllll0O))) & (~ ((~ comp_pat[28]) ^ nllllii))) & (~ ((~ comp_pat[29]) ^ nllllil))) & (~ ((~ comp_pat[30]) ^ nlllliO))) & (~ ((~ comp_pat[31]) ^ nllllOl))),
		n1010iO = (((((((((((((((n101Oli | n101Oii) | n101O0i) | n101O1i) | n101lOi) | n101lli) | n101lii) | n101l0i) | n101l1i) | n101iOi) | n101ili) | n101iii) | n101i0i) | n101i1i) | n1010Oi) | n1010li),
		n1010li = (n101OOl & ((comp_pat_porn & n1010lO) | n1010ll)),
		n1010ll = ((((((((~ (comp_pat[8] ^ nllll1l)) & (~ (comp_pat[9] ^ nllll1O))) & (~ (comp_pat[10] ^ nllll0i))) & (~ (comp_pat[11] ^ nllll0l))) & (~ (comp_pat[12] ^ nllll0O))) & (~ (comp_pat[13] ^ nllllii))) & (~ (comp_pat[14] ^ nllllil))) & (~ (comp_pat[15] ^ nlllliO))),
		n1010lO = ((((((((~ ((~ comp_pat[8]) ^ nllll1l)) & (~ ((~ comp_pat[9]) ^ nllll1O))) & (~ ((~ comp_pat[10]) ^ nllll0i))) & (~ ((~ comp_pat[11]) ^ nllll0l))) & (~ ((~ comp_pat[12]) ^ nllll0O))) & (~ ((~ comp_pat[13]) ^ nllllii))) & (~ ((~ comp_pat[14]) ^ nllllil))) & (~ ((~ comp_pat[15]) ^ nlllliO))),
		n1010Oi = (n10011l & ((comp_pat_porn & n1010OO) | n1010Ol)),
		n1010Ol = ((((((((~ (comp_pat[8] ^ nllll1i)) & (~ (comp_pat[9] ^ nllll1l))) & (~ (comp_pat[10] ^ nllll1O))) & (~ (comp_pat[11] ^ nllll0i))) & (~ (comp_pat[12] ^ nllll0l))) & (~ (comp_pat[13] ^ nllll0O))) & (~ (comp_pat[14] ^ nllllii))) & (~ (comp_pat[15] ^ nllllil))),
		n1010OO = ((((((((~ ((~ comp_pat[8]) ^ nllll1i)) & (~ ((~ comp_pat[9]) ^ nllll1l))) & (~ ((~ comp_pat[10]) ^ nllll1O))) & (~ ((~ comp_pat[11]) ^ nllll0i))) & (~ ((~ comp_pat[12]) ^ nllll0l))) & (~ ((~ comp_pat[13]) ^ nllll0O))) & (~ ((~ comp_pat[14]) ^ nllllii))) & (~ ((~ comp_pat[15]) ^ nllllil))),
		n10110i = (n101O1i & (((comp_pat_porn & n1011il) | n1011ii) & ((comp_pat_porn & n10110O) | n10110l))),
		n10110l = ((((((((~ (comp_pat[16] ^ nllliOi)) & (~ (comp_pat[17] ^ nllliOl))) & (~ (comp_pat[18] ^ nllliOO))) & (~ (comp_pat[19] ^ nllll1i))) & (~ (comp_pat[20] ^ nllll1l))) & (~ (comp_pat[21] ^ nllll1O))) & (~ (comp_pat[22] ^ nllll0i))) & (~ (comp_pat[23] ^ nllll0l))),
		n10110O = ((((((((~ ((~ comp_pat[16]) ^ nllliOi)) & (~ ((~ comp_pat[17]) ^ nllliOl))) & (~ ((~ comp_pat[18]) ^ nllliOO))) & (~ ((~ comp_pat[19]) ^ nllll1i))) & (~ ((~ comp_pat[20]) ^ nllll1l))) & (~ ((~ comp_pat[21]) ^ nllll1O))) & (~ ((~ comp_pat[22]) ^ nllll0i))) & (~ ((~ comp_pat[23]) ^ nllll0l))),
		n10111i = ((((((((~ ((~ comp_pat[16]) ^ nllliOl)) & (~ ((~ comp_pat[17]) ^ nllliOO))) & (~ ((~ comp_pat[18]) ^ nllll1i))) & (~ ((~ comp_pat[19]) ^ nllll1l))) & (~ ((~ comp_pat[20]) ^ nllll1O))) & (~ ((~ comp_pat[21]) ^ nllll0i))) & (~ ((~ comp_pat[22]) ^ nllll0l))) & (~ ((~ comp_pat[23]) ^ nllll0O))),
		n10111l = ((((((((~ (comp_pat[24] ^ nllllii)) & (~ (comp_pat[25] ^ nllllil))) & (~ (comp_pat[26] ^ nlllliO))) & (~ (comp_pat[27] ^ nllllOl))) & (~ (comp_pat[28] ^ nllllOO))) & (~ (comp_pat[29] ^ nlllO1i))) & (~ (comp_pat[30] ^ nlllO1l))) & (~ (comp_pat[31] ^ nlllO1O))),
		n10111O = ((((((((~ ((~ comp_pat[24]) ^ nllllii)) & (~ ((~ comp_pat[25]) ^ nllllil))) & (~ ((~ comp_pat[26]) ^ nlllliO))) & (~ ((~ comp_pat[27]) ^ nllllOl))) & (~ ((~ comp_pat[28]) ^ nllllOO))) & (~ ((~ comp_pat[29]) ^ nlllO1i))) & (~ ((~ comp_pat[30]) ^ nlllO1l))) & (~ ((~ comp_pat[31]) ^ nlllO1O))),
		n1011ii = ((((((((~ (comp_pat[24] ^ nllll0O)) & (~ (comp_pat[25] ^ nllllii))) & (~ (comp_pat[26] ^ nllllil))) & (~ (comp_pat[27] ^ nlllliO))) & (~ (comp_pat[28] ^ nllllOl))) & (~ (comp_pat[29] ^ nllllOO))) & (~ (comp_pat[30] ^ nlllO1i))) & (~ (comp_pat[31] ^ nlllO1l))),
		n1011il = ((((((((~ ((~ comp_pat[24]) ^ nllll0O)) & (~ ((~ comp_pat[25]) ^ nllllii))) & (~ ((~ comp_pat[26]) ^ nllllil))) & (~ ((~ comp_pat[27]) ^ nlllliO))) & (~ ((~ comp_pat[28]) ^ nllllOl))) & (~ ((~ comp_pat[29]) ^ nllllOO))) & (~ ((~ comp_pat[30]) ^ nlllO1i))) & (~ ((~ comp_pat[31]) ^ nlllO1l))),
		n1011iO = (n101O0i & (((comp_pat_porn & n1011Oi) | n1011lO) & ((comp_pat_porn & n1011ll) | n1011li))),
		n1011li = ((((((((~ (comp_pat[16] ^ nlllilO)) & (~ (comp_pat[17] ^ nllliOi))) & (~ (comp_pat[18] ^ nllliOl))) & (~ (comp_pat[19] ^ nllliOO))) & (~ (comp_pat[20] ^ nllll1i))) & (~ (comp_pat[21] ^ nllll1l))) & (~ (comp_pat[22] ^ nllll1O))) & (~ (comp_pat[23] ^ nllll0i))),
		n1011ll = ((((((((~ ((~ comp_pat[16]) ^ nlllilO)) & (~ ((~ comp_pat[17]) ^ nllliOi))) & (~ ((~ comp_pat[18]) ^ nllliOl))) & (~ ((~ comp_pat[19]) ^ nllliOO))) & (~ ((~ comp_pat[20]) ^ nllll1i))) & (~ ((~ comp_pat[21]) ^ nllll1l))) & (~ ((~ comp_pat[22]) ^ nllll1O))) & (~ ((~ comp_pat[23]) ^ nllll0i))),
		n1011lO = ((((((((~ (comp_pat[24] ^ nllll0l)) & (~ (comp_pat[25] ^ nllll0O))) & (~ (comp_pat[26] ^ nllllii))) & (~ (comp_pat[27] ^ nllllil))) & (~ (comp_pat[28] ^ nlllliO))) & (~ (comp_pat[29] ^ nllllOl))) & (~ (comp_pat[30] ^ nllllOO))) & (~ (comp_pat[31] ^ nlllO1i))),
		n1011Oi = ((((((((~ ((~ comp_pat[24]) ^ nllll0l)) & (~ ((~ comp_pat[25]) ^ nllll0O))) & (~ ((~ comp_pat[26]) ^ nllllii))) & (~ ((~ comp_pat[27]) ^ nllllil))) & (~ ((~ comp_pat[28]) ^ nlllliO))) & (~ ((~ comp_pat[29]) ^ nllllOl))) & (~ ((~ comp_pat[30]) ^ nllllOO))) & (~ ((~ comp_pat[31]) ^ nlllO1i))),
		n1011Ol = (n101Oii & (((comp_pat_porn & n10101O) | n10101l) & ((comp_pat_porn & n10101i) | n1011OO))),
		n1011OO = ((((((((~ (comp_pat[16] ^ nlllill)) & (~ (comp_pat[17] ^ nlllilO))) & (~ (comp_pat[18] ^ nllliOi))) & (~ (comp_pat[19] ^ nllliOl))) & (~ (comp_pat[20] ^ nllliOO))) & (~ (comp_pat[21] ^ nllll1i))) & (~ (comp_pat[22] ^ nllll1l))) & (~ (comp_pat[23] ^ nllll1O))),
		n101i0i = (n1001il & ((comp_pat_porn & n101i0O) | n101i0l)),
		n101i0l = ((((((((~ (comp_pat[8] ^ nllliOl)) & (~ (comp_pat[9] ^ nllliOO))) & (~ (comp_pat[10] ^ nllll1i))) & (~ (comp_pat[11] ^ nllll1l))) & (~ (comp_pat[12] ^ nllll1O))) & (~ (comp_pat[13] ^ nllll0i))) & (~ (comp_pat[14] ^ nllll0l))) & (~ (comp_pat[15] ^ nllll0O))),
		n101i0O = ((((((((~ ((~ comp_pat[8]) ^ nllliOl)) & (~ ((~ comp_pat[9]) ^ nllliOO))) & (~ ((~ comp_pat[10]) ^ nllll1i))) & (~ ((~ comp_pat[11]) ^ nllll1l))) & (~ ((~ comp_pat[12]) ^ nllll1O))) & (~ ((~ comp_pat[13]) ^ nllll0i))) & (~ ((~ comp_pat[14]) ^ nllll0l))) & (~ ((~ comp_pat[15]) ^ nllll0O))),
		n101i1i = (n10010l & ((comp_pat_porn & n101i1O) | n101i1l)),
		n101i1l = ((((((((~ (comp_pat[8] ^ nllliOO)) & (~ (comp_pat[9] ^ nllll1i))) & (~ (comp_pat[10] ^ nllll1l))) & (~ (comp_pat[11] ^ nllll1O))) & (~ (comp_pat[12] ^ nllll0i))) & (~ (comp_pat[13] ^ nllll0l))) & (~ (comp_pat[14] ^ nllll0O))) & (~ (comp_pat[15] ^ nllllii))),
		n101i1O = ((((((((~ ((~ comp_pat[8]) ^ nllliOO)) & (~ ((~ comp_pat[9]) ^ nllll1i))) & (~ ((~ comp_pat[10]) ^ nllll1l))) & (~ ((~ comp_pat[11]) ^ nllll1O))) & (~ ((~ comp_pat[12]) ^ nllll0i))) & (~ ((~ comp_pat[13]) ^ nllll0l))) & (~ ((~ comp_pat[14]) ^ nllll0O))) & (~ ((~ comp_pat[15]) ^ nllllii))),
		n101iii = (n1001ll & ((comp_pat_porn & n101iiO) | n101iil)),
		n101iil = ((((((((~ (comp_pat[8] ^ nllliOi)) & (~ (comp_pat[9] ^ nllliOl))) & (~ (comp_pat[10] ^ nllliOO))) & (~ (comp_pat[11] ^ nllll1i))) & (~ (comp_pat[12] ^ nllll1l))) & (~ (comp_pat[13] ^ nllll1O))) & (~ (comp_pat[14] ^ nllll0i))) & (~ (comp_pat[15] ^ nllll0l))),
		n101iiO = ((((((((~ ((~ comp_pat[8]) ^ nllliOi)) & (~ ((~ comp_pat[9]) ^ nllliOl))) & (~ ((~ comp_pat[10]) ^ nllliOO))) & (~ ((~ comp_pat[11]) ^ nllll1i))) & (~ ((~ comp_pat[12]) ^ nllll1l))) & (~ ((~ comp_pat[13]) ^ nllll1O))) & (~ ((~ comp_pat[14]) ^ nllll0i))) & (~ ((~ comp_pat[15]) ^ nllll0l))),
		n101ili = (n1001Ol & ((comp_pat_porn & n101ilO) | n101ill)),
		n101ill = ((((((((~ (comp_pat[8] ^ nlllilO)) & (~ (comp_pat[9] ^ nllliOi))) & (~ (comp_pat[10] ^ nllliOl))) & (~ (comp_pat[11] ^ nllliOO))) & (~ (comp_pat[12] ^ nllll1i))) & (~ (comp_pat[13] ^ nllll1l))) & (~ (comp_pat[14] ^ nllll1O))) & (~ (comp_pat[15] ^ nllll0i))),
		n101ilO = ((((((((~ ((~ comp_pat[8]) ^ nlllilO)) & (~ ((~ comp_pat[9]) ^ nllliOi))) & (~ ((~ comp_pat[10]) ^ nllliOl))) & (~ ((~ comp_pat[11]) ^ nllliOO))) & (~ ((~ comp_pat[12]) ^ nllll1i))) & (~ ((~ comp_pat[13]) ^ nllll1l))) & (~ ((~ comp_pat[14]) ^ nllll1O))) & (~ ((~ comp_pat[15]) ^ nllll0i))),
		n101iOi = (n10001l & ((comp_pat_porn & n101iOO) | n101iOl)),
		n101iOl = ((((((((~ (comp_pat[8] ^ nlllill)) & (~ (comp_pat[9] ^ nlllilO))) & (~ (comp_pat[10] ^ nllliOi))) & (~ (comp_pat[11] ^ nllliOl))) & (~ (comp_pat[12] ^ nllliOO))) & (~ (comp_pat[13] ^ nllll1i))) & (~ (comp_pat[14] ^ nllll1l))) & (~ (comp_pat[15] ^ nllll1O))),
		n101iOO = ((((((((~ ((~ comp_pat[8]) ^ nlllill)) & (~ ((~ comp_pat[9]) ^ nlllilO))) & (~ ((~ comp_pat[10]) ^ nllliOi))) & (~ ((~ comp_pat[11]) ^ nllliOl))) & (~ ((~ comp_pat[12]) ^ nllliOO))) & (~ ((~ comp_pat[13]) ^ nllll1i))) & (~ ((~ comp_pat[14]) ^ nllll1l))) & (~ ((~ comp_pat[15]) ^ nllll1O))),
		n101l0i = (n1000il & ((comp_pat_porn & n101l0O) | n101l0l)),
		n101l0l = ((((((((~ (comp_pat[8] ^ nllliiO)) & (~ (comp_pat[9] ^ nlllili))) & (~ (comp_pat[10] ^ nlllill))) & (~ (comp_pat[11] ^ nlllilO))) & (~ (comp_pat[12] ^ nllliOi))) & (~ (comp_pat[13] ^ nllliOl))) & (~ (comp_pat[14] ^ nllliOO))) & (~ (comp_pat[15] ^ nllll1i))),
		n101l0O = ((((((((~ ((~ comp_pat[8]) ^ nllliiO)) & (~ ((~ comp_pat[9]) ^ nlllili))) & (~ ((~ comp_pat[10]) ^ nlllill))) & (~ ((~ comp_pat[11]) ^ nlllilO))) & (~ ((~ comp_pat[12]) ^ nllliOi))) & (~ ((~ comp_pat[13]) ^ nllliOl))) & (~ ((~ comp_pat[14]) ^ nllliOO))) & (~ ((~ comp_pat[15]) ^ nllll1i))),
		n101l1i = (n10000l & ((comp_pat_porn & n101l1O) | n101l1l)),
		n101l1l = ((((((((~ (comp_pat[8] ^ nlllili)) & (~ (comp_pat[9] ^ nlllill))) & (~ (comp_pat[10] ^ nlllilO))) & (~ (comp_pat[11] ^ nllliOi))) & (~ (comp_pat[12] ^ nllliOl))) & (~ (comp_pat[13] ^ nllliOO))) & (~ (comp_pat[14] ^ nllll1i))) & (~ (comp_pat[15] ^ nllll1l))),
		n101l1O = ((((((((~ ((~ comp_pat[8]) ^ nlllili)) & (~ ((~ comp_pat[9]) ^ nlllill))) & (~ ((~ comp_pat[10]) ^ nlllilO))) & (~ ((~ comp_pat[11]) ^ nllliOi))) & (~ ((~ comp_pat[12]) ^ nllliOl))) & (~ ((~ comp_pat[13]) ^ nllliOO))) & (~ ((~ comp_pat[14]) ^ nllll1i))) & (~ ((~ comp_pat[15]) ^ nllll1l))),
		n101lii = (n1000ll & ((comp_pat_porn & n101liO) | n101lil)),
		n101lil = ((((((((~ (comp_pat[8] ^ nllli0i)) & (~ (comp_pat[9] ^ nllliiO))) & (~ (comp_pat[10] ^ nlllili))) & (~ (comp_pat[11] ^ nlllill))) & (~ (comp_pat[12] ^ nlllilO))) & (~ (comp_pat[13] ^ nllliOi))) & (~ (comp_pat[14] ^ nllliOl))) & (~ (comp_pat[15] ^ nllliOO))),
		n101liO = ((((((((~ ((~ comp_pat[8]) ^ nllli0i)) & (~ ((~ comp_pat[9]) ^ nllliiO))) & (~ ((~ comp_pat[10]) ^ nlllili))) & (~ ((~ comp_pat[11]) ^ nlllill))) & (~ ((~ comp_pat[12]) ^ nlllilO))) & (~ ((~ comp_pat[13]) ^ nllliOi))) & (~ ((~ comp_pat[14]) ^ nllliOl))) & (~ ((~ comp_pat[15]) ^ nllliOO))),
		n101lli = (n1000Ol & ((comp_pat_porn & n101llO) | n101lll)),
		n101lll = ((((((((~ (comp_pat[8] ^ nllli1O)) & (~ (comp_pat[9] ^ nllli0i))) & (~ (comp_pat[10] ^ nllliiO))) & (~ (comp_pat[11] ^ nlllili))) & (~ (comp_pat[12] ^ nlllill))) & (~ (comp_pat[13] ^ nlllilO))) & (~ (comp_pat[14] ^ nllliOi))) & (~ (comp_pat[15] ^ nllliOl))),
		n101llO = ((((((((~ ((~ comp_pat[8]) ^ nllli1O)) & (~ ((~ comp_pat[9]) ^ nllli0i))) & (~ ((~ comp_pat[10]) ^ nllliiO))) & (~ ((~ comp_pat[11]) ^ nlllili))) & (~ ((~ comp_pat[12]) ^ nlllill))) & (~ ((~ comp_pat[13]) ^ nlllilO))) & (~ ((~ comp_pat[14]) ^ nllliOi))) & (~ ((~ comp_pat[15]) ^ nllliOl))),
		n101lOi = (n100i1l & ((comp_pat_porn & n101lOO) | n101lOl)),
		n101lOl = ((((((((~ (comp_pat[8] ^ nllli1l)) & (~ (comp_pat[9] ^ nllli1O))) & (~ (comp_pat[10] ^ nllli0i))) & (~ (comp_pat[11] ^ nllliiO))) & (~ (comp_pat[12] ^ nlllili))) & (~ (comp_pat[13] ^ nlllill))) & (~ (comp_pat[14] ^ nlllilO))) & (~ (comp_pat[15] ^ nllliOi))),
		n101lOO = ((((((((~ ((~ comp_pat[8]) ^ nllli1l)) & (~ ((~ comp_pat[9]) ^ nllli1O))) & (~ ((~ comp_pat[10]) ^ nllli0i))) & (~ ((~ comp_pat[11]) ^ nllliiO))) & (~ ((~ comp_pat[12]) ^ nlllili))) & (~ ((~ comp_pat[13]) ^ nlllill))) & (~ ((~ comp_pat[14]) ^ nlllilO))) & (~ ((~ comp_pat[15]) ^ nllliOi))),
		n101O0i = (n100iil & ((comp_pat_porn & n101O0O) | n101O0l)),
		n101O0l = ((((((((~ (comp_pat[8] ^ nlll0OO)) & (~ (comp_pat[9] ^ nllli1i))) & (~ (comp_pat[10] ^ nllli1l))) & (~ (comp_pat[11] ^ nllli1O))) & (~ (comp_pat[12] ^ nllli0i))) & (~ (comp_pat[13] ^ nllliiO))) & (~ (comp_pat[14] ^ nlllili))) & (~ (comp_pat[15] ^ nlllill))),
		n101O0O = ((((((((~ ((~ comp_pat[8]) ^ nlll0OO)) & (~ ((~ comp_pat[9]) ^ nllli1i))) & (~ ((~ comp_pat[10]) ^ nllli1l))) & (~ ((~ comp_pat[11]) ^ nllli1O))) & (~ ((~ comp_pat[12]) ^ nllli0i))) & (~ ((~ comp_pat[13]) ^ nllliiO))) & (~ ((~ comp_pat[14]) ^ nlllili))) & (~ ((~ comp_pat[15]) ^ nlllill))),
		n101O1i = (n100i0l & ((comp_pat_porn & n101O1O) | n101O1l)),
		n101O1l = ((((((((~ (comp_pat[8] ^ nllli1i)) & (~ (comp_pat[9] ^ nllli1l))) & (~ (comp_pat[10] ^ nllli1O))) & (~ (comp_pat[11] ^ nllli0i))) & (~ (comp_pat[12] ^ nllliiO))) & (~ (comp_pat[13] ^ nlllili))) & (~ (comp_pat[14] ^ nlllill))) & (~ (comp_pat[15] ^ nlllilO))),
		n101O1O = ((((((((~ ((~ comp_pat[8]) ^ nllli1i)) & (~ ((~ comp_pat[9]) ^ nllli1l))) & (~ ((~ comp_pat[10]) ^ nllli1O))) & (~ ((~ comp_pat[11]) ^ nllli0i))) & (~ ((~ comp_pat[12]) ^ nllliiO))) & (~ ((~ comp_pat[13]) ^ nlllili))) & (~ ((~ comp_pat[14]) ^ nlllill))) & (~ ((~ comp_pat[15]) ^ nlllilO))),
		n101Oii = (n100ill & ((comp_pat_porn & n101OiO) | n101Oil)),
		n101Oil = ((((((((~ (comp_pat[8] ^ nlll0Ol)) & (~ (comp_pat[9] ^ nlll0OO))) & (~ (comp_pat[10] ^ nllli1i))) & (~ (comp_pat[11] ^ nllli1l))) & (~ (comp_pat[12] ^ nllli1O))) & (~ (comp_pat[13] ^ nllli0i))) & (~ (comp_pat[14] ^ nllliiO))) & (~ (comp_pat[15] ^ nlllili))),
		n101OiO = ((((((((~ ((~ comp_pat[8]) ^ nlll0Ol)) & (~ ((~ comp_pat[9]) ^ nlll0OO))) & (~ ((~ comp_pat[10]) ^ nllli1i))) & (~ ((~ comp_pat[11]) ^ nllli1l))) & (~ ((~ comp_pat[12]) ^ nllli1O))) & (~ ((~ comp_pat[13]) ^ nllli0i))) & (~ ((~ comp_pat[14]) ^ nllliiO))) & (~ ((~ comp_pat[15]) ^ nlllili))),
		n101Oli = (n100iOl & ((comp_pat_porn & n101OlO) | n101Oll)),
		n101Oll = ((((((((~ (comp_pat[8] ^ nlll0Oi)) & (~ (comp_pat[9] ^ nlll0Ol))) & (~ (comp_pat[10] ^ nlll0OO))) & (~ (comp_pat[11] ^ nllli1i))) & (~ (comp_pat[12] ^ nllli1l))) & (~ (comp_pat[13] ^ nllli1O))) & (~ (comp_pat[14] ^ nllli0i))) & (~ (comp_pat[15] ^ nllliiO))),
		n101OlO = ((((((((~ ((~ comp_pat[8]) ^ nlll0Oi)) & (~ ((~ comp_pat[9]) ^ nlll0Ol))) & (~ ((~ comp_pat[10]) ^ nlll0OO))) & (~ ((~ comp_pat[11]) ^ nllli1i))) & (~ ((~ comp_pat[12]) ^ nllli1l))) & (~ ((~ comp_pat[13]) ^ nllli1O))) & (~ ((~ comp_pat[14]) ^ nllli0i))) & (~ ((~ comp_pat[15]) ^ nllliiO))),
		n101OOi = (((((((((((((((n100iOl | n100ill) | n100iil) | n100i0l) | n100i1l) | n1000Ol) | n1000ll) | n1000il) | n10000l) | n10001l) | n1001Ol) | n1001ll) | n1001il) | n10010l) | n10011l) | n101OOl),
		n101OOl = ((comp_pat_porn & n10011i) | n101OOO),
		n101OOO = ((((((((~ (comp_pat[0] ^ nllliiO)) & (~ (comp_pat[1] ^ nlllili))) & (~ (comp_pat[2] ^ nlllill))) & (~ (comp_pat[3] ^ nlllilO))) & (~ (comp_pat[4] ^ nllliOi))) & (~ (comp_pat[5] ^ nllliOl))) & (~ (comp_pat[6] ^ nllliOO))) & (~ (comp_pat[7] ^ nllll1i))),
		n10i00i = ((((((((((~ (comp_pat[20] ^ nllll0l)) & (~ (comp_pat[21] ^ nllll0O))) & (~ (comp_pat[22] ^ nllllii))) & (~ (comp_pat[23] ^ nllllil))) & (~ (comp_pat[24] ^ nlllliO))) & (~ (comp_pat[25] ^ nllllli))) & (~ (comp_pat[26] ^ nllllll))) & (~ (comp_pat[27] ^ nlllllO))) & (~ (comp_pat[28] ^ nllllOi))) & (~ (comp_pat[29] ^ nllllOl))),
		n10i00l = ((((((((((~ ((~ comp_pat[20]) ^ nllll0l)) & (~ ((~ comp_pat[21]) ^ nllll0O))) & (~ ((~ comp_pat[22]) ^ nllllii))) & (~ ((~ comp_pat[23]) ^ nllllil))) & (~ ((~ comp_pat[24]) ^ nlllliO))) & (~ ((~ comp_pat[25]) ^ nllllli))) & (~ ((~ comp_pat[26]) ^ nllllll))) & (~ ((~ comp_pat[27]) ^ nlllllO))) & (~ ((~ comp_pat[28]) ^ nllllOi))) & (~ ((~ comp_pat[29]) ^ nllllOl))),
		n10i00O = ((((((((((~ (comp_pat[30] ^ nllllOO)) & (~ (comp_pat[31] ^ nlllO1i))) & (~ (comp_pat[32] ^ nlllO1l))) & (~ (comp_pat[33] ^ nlllO1O))) & (~ (comp_pat[34] ^ nlllO0i))) & (~ (comp_pat[35] ^ nlllO0l))) & (~ (comp_pat[36] ^ nlllO0O))) & (~ (comp_pat[37] ^ nlllOii))) & (~ (comp_pat[38] ^ nlllOil))) & (~ (comp_pat[39] ^ nlllOiO))),
		n10i01i = ((((((((((~ (comp_pat[30] ^ nlllO1i)) & (~ (comp_pat[31] ^ nlllO1l))) & (~ (comp_pat[32] ^ nlllO1O))) & (~ (comp_pat[33] ^ nlllO0i))) & (~ (comp_pat[34] ^ nlllO0l))) & (~ (comp_pat[35] ^ nlllO0O))) & (~ (comp_pat[36] ^ nlllOii))) & (~ (comp_pat[37] ^ nlllOil))) & (~ (comp_pat[38] ^ nlllOiO))) & (~ (comp_pat[39] ^ nlllOli))),
		n10i01l = ((((((((((~ ((~ comp_pat[30]) ^ nlllO1i)) & (~ ((~ comp_pat[31]) ^ nlllO1l))) & (~ ((~ comp_pat[32]) ^ nlllO1O))) & (~ ((~ comp_pat[33]) ^ nlllO0i))) & (~ ((~ comp_pat[34]) ^ nlllO0l))) & (~ ((~ comp_pat[35]) ^ nlllO0O))) & (~ ((~ comp_pat[36]) ^ nlllOii))) & (~ ((~ comp_pat[37]) ^ nlllOil))) & (~ ((~ comp_pat[38]) ^ nlllOiO))) & (~ ((~ comp_pat[39]) ^ nlllOli))),
		n10i01O = (n10l0ll & (((comp_pat_porn & n10i0ii) | n10i00O) & ((comp_pat_porn & n10i00l) | n10i00i))),
		n10i0ii = ((((((((((~ ((~ comp_pat[30]) ^ nllllOO)) & (~ ((~ comp_pat[31]) ^ nlllO1i))) & (~ ((~ comp_pat[32]) ^ nlllO1l))) & (~ ((~ comp_pat[33]) ^ nlllO1O))) & (~ ((~ comp_pat[34]) ^ nlllO0i))) & (~ ((~ comp_pat[35]) ^ nlllO0l))) & (~ ((~ comp_pat[36]) ^ nlllO0O))) & (~ ((~ comp_pat[37]) ^ nlllOii))) & (~ ((~ comp_pat[38]) ^ nlllOil))) & (~ ((~ comp_pat[39]) ^ nlllOiO))),
		n10i0il = (n10l0Ol & (((comp_pat_porn & n10i0lO) | n10i0ll) & ((comp_pat_porn & n10i0li) | n10i0iO))),
		n10i0iO = ((((((((((~ (comp_pat[20] ^ nllll0i)) & (~ (comp_pat[21] ^ nllll0l))) & (~ (comp_pat[22] ^ nllll0O))) & (~ (comp_pat[23] ^ nllllii))) & (~ (comp_pat[24] ^ nllllil))) & (~ (comp_pat[25] ^ nlllliO))) & (~ (comp_pat[26] ^ nllllli))) & (~ (comp_pat[27] ^ nllllll))) & (~ (comp_pat[28] ^ nlllllO))) & (~ (comp_pat[29] ^ nllllOi))),
		n10i0li = ((((((((((~ ((~ comp_pat[20]) ^ nllll0i)) & (~ ((~ comp_pat[21]) ^ nllll0l))) & (~ ((~ comp_pat[22]) ^ nllll0O))) & (~ ((~ comp_pat[23]) ^ nllllii))) & (~ ((~ comp_pat[24]) ^ nllllil))) & (~ ((~ comp_pat[25]) ^ nlllliO))) & (~ ((~ comp_pat[26]) ^ nllllli))) & (~ ((~ comp_pat[27]) ^ nllllll))) & (~ ((~ comp_pat[28]) ^ nlllllO))) & (~ ((~ comp_pat[29]) ^ nllllOi))),
		n10i0ll = ((((((((((~ (comp_pat[30] ^ nllllOl)) & (~ (comp_pat[31] ^ nllllOO))) & (~ (comp_pat[32] ^ nlllO1i))) & (~ (comp_pat[33] ^ nlllO1l))) & (~ (comp_pat[34] ^ nlllO1O))) & (~ (comp_pat[35] ^ nlllO0i))) & (~ (comp_pat[36] ^ nlllO0l))) & (~ (comp_pat[37] ^ nlllO0O))) & (~ (comp_pat[38] ^ nlllOii))) & (~ (comp_pat[39] ^ nlllOil))),
		n10i0lO = ((((((((((~ ((~ comp_pat[30]) ^ nllllOl)) & (~ ((~ comp_pat[31]) ^ nllllOO))) & (~ ((~ comp_pat[32]) ^ nlllO1i))) & (~ ((~ comp_pat[33]) ^ nlllO1l))) & (~ ((~ comp_pat[34]) ^ nlllO1O))) & (~ ((~ comp_pat[35]) ^ nlllO0i))) & (~ ((~ comp_pat[36]) ^ nlllO0l))) & (~ ((~ comp_pat[37]) ^ nlllO0O))) & (~ ((~ comp_pat[38]) ^ nlllOii))) & (~ ((~ comp_pat[39]) ^ nlllOil))),
		n10i0Oi = (n10li1l & (((comp_pat_porn & n10ii1l) | n10ii1i) & ((comp_pat_porn & n10i0OO) | n10i0Ol))),
		n10i0Ol = ((((((((((~ (comp_pat[20] ^ nllll1O)) & (~ (comp_pat[21] ^ nllll0i))) & (~ (comp_pat[22] ^ nllll0l))) & (~ (comp_pat[23] ^ nllll0O))) & (~ (comp_pat[24] ^ nllllii))) & (~ (comp_pat[25] ^ nllllil))) & (~ (comp_pat[26] ^ nlllliO))) & (~ (comp_pat[27] ^ nllllli))) & (~ (comp_pat[28] ^ nllllll))) & (~ (comp_pat[29] ^ nlllllO))),
		n10i0OO = ((((((((((~ ((~ comp_pat[20]) ^ nllll1O)) & (~ ((~ comp_pat[21]) ^ nllll0i))) & (~ ((~ comp_pat[22]) ^ nllll0l))) & (~ ((~ comp_pat[23]) ^ nllll0O))) & (~ ((~ comp_pat[24]) ^ nllllii))) & (~ ((~ comp_pat[25]) ^ nllllil))) & (~ ((~ comp_pat[26]) ^ nlllliO))) & (~ ((~ comp_pat[27]) ^ nllllli))) & (~ ((~ comp_pat[28]) ^ nllllll))) & (~ ((~ comp_pat[29]) ^ nlllllO))),
		n10i10i = ((((((((((~ (comp_pat[20] ^ nllllil)) & (~ (comp_pat[21] ^ nlllliO))) & (~ (comp_pat[22] ^ nllllli))) & (~ (comp_pat[23] ^ nllllll))) & (~ (comp_pat[24] ^ nlllllO))) & (~ (comp_pat[25] ^ nllllOi))) & (~ (comp_pat[26] ^ nllllOl))) & (~ (comp_pat[27] ^ nllllOO))) & (~ (comp_pat[28] ^ nlllO1i))) & (~ (comp_pat[29] ^ nlllO1l))),
		n10i10l = ((((((((((~ ((~ comp_pat[20]) ^ nllllil)) & (~ ((~ comp_pat[21]) ^ nlllliO))) & (~ ((~ comp_pat[22]) ^ nllllli))) & (~ ((~ comp_pat[23]) ^ nllllll))) & (~ ((~ comp_pat[24]) ^ nlllllO))) & (~ ((~ comp_pat[25]) ^ nllllOi))) & (~ ((~ comp_pat[26]) ^ nllllOl))) & (~ ((~ comp_pat[27]) ^ nllllOO))) & (~ ((~ comp_pat[28]) ^ nlllO1i))) & (~ ((~ comp_pat[29]) ^ nlllO1l))),
		n10i10O = ((((((((((~ (comp_pat[30] ^ nlllO1O)) & (~ (comp_pat[31] ^ nlllO0i))) & (~ (comp_pat[32] ^ nlllO0l))) & (~ (comp_pat[33] ^ nlllO0O))) & (~ (comp_pat[34] ^ nlllOii))) & (~ (comp_pat[35] ^ nlllOil))) & (~ (comp_pat[36] ^ nlllOiO))) & (~ (comp_pat[37] ^ nlllOli))) & (~ (comp_pat[38] ^ nlllOll))) & (~ (comp_pat[39] ^ nlllOlO))),
		n10i11i = ((((((((((~ (comp_pat[30] ^ nlllO0i)) & (~ (comp_pat[31] ^ nlllO0l))) & (~ (comp_pat[32] ^ nlllO0O))) & (~ (comp_pat[33] ^ nlllOii))) & (~ (comp_pat[34] ^ nlllOil))) & (~ (comp_pat[35] ^ nlllOiO))) & (~ (comp_pat[36] ^ nlllOli))) & (~ (comp_pat[37] ^ nlllOll))) & (~ (comp_pat[38] ^ nlllOlO))) & (~ (comp_pat[39] ^ nlllOOi))),
		n10i11l = ((((((((((~ ((~ comp_pat[30]) ^ nlllO0i)) & (~ ((~ comp_pat[31]) ^ nlllO0l))) & (~ ((~ comp_pat[32]) ^ nlllO0O))) & (~ ((~ comp_pat[33]) ^ nlllOii))) & (~ ((~ comp_pat[34]) ^ nlllOil))) & (~ ((~ comp_pat[35]) ^ nlllOiO))) & (~ ((~ comp_pat[36]) ^ nlllOli))) & (~ ((~ comp_pat[37]) ^ nlllOll))) & (~ ((~ comp_pat[38]) ^ nlllOlO))) & (~ ((~ comp_pat[39]) ^ nlllOOi))),
		n10i11O = (n10l01l & (((comp_pat_porn & n10i1ii) | n10i10O) & ((comp_pat_porn & n10i10l) | n10i10i))),
		n10i1ii = ((((((((((~ ((~ comp_pat[30]) ^ nlllO1O)) & (~ ((~ comp_pat[31]) ^ nlllO0i))) & (~ ((~ comp_pat[32]) ^ nlllO0l))) & (~ ((~ comp_pat[33]) ^ nlllO0O))) & (~ ((~ comp_pat[34]) ^ nlllOii))) & (~ ((~ comp_pat[35]) ^ nlllOil))) & (~ ((~ comp_pat[36]) ^ nlllOiO))) & (~ ((~ comp_pat[37]) ^ nlllOli))) & (~ ((~ comp_pat[38]) ^ nlllOll))) & (~ ((~ comp_pat[39]) ^ nlllOlO))),
		n10i1il = (n10l00l & (((comp_pat_porn & n10i1lO) | n10i1ll) & ((comp_pat_porn & n10i1li) | n10i1iO))),
		n10i1iO = ((((((((((~ (comp_pat[20] ^ nllllii)) & (~ (comp_pat[21] ^ nllllil))) & (~ (comp_pat[22] ^ nlllliO))) & (~ (comp_pat[23] ^ nllllli))) & (~ (comp_pat[24] ^ nllllll))) & (~ (comp_pat[25] ^ nlllllO))) & (~ (comp_pat[26] ^ nllllOi))) & (~ (comp_pat[27] ^ nllllOl))) & (~ (comp_pat[28] ^ nllllOO))) & (~ (comp_pat[29] ^ nlllO1i))),
		n10i1li = ((((((((((~ ((~ comp_pat[20]) ^ nllllii)) & (~ ((~ comp_pat[21]) ^ nllllil))) & (~ ((~ comp_pat[22]) ^ nlllliO))) & (~ ((~ comp_pat[23]) ^ nllllli))) & (~ ((~ comp_pat[24]) ^ nllllll))) & (~ ((~ comp_pat[25]) ^ nlllllO))) & (~ ((~ comp_pat[26]) ^ nllllOi))) & (~ ((~ comp_pat[27]) ^ nllllOl))) & (~ ((~ comp_pat[28]) ^ nllllOO))) & (~ ((~ comp_pat[29]) ^ nlllO1i))),
		n10i1ll = ((((((((((~ (comp_pat[30] ^ nlllO1l)) & (~ (comp_pat[31] ^ nlllO1O))) & (~ (comp_pat[32] ^ nlllO0i))) & (~ (comp_pat[33] ^ nlllO0l))) & (~ (comp_pat[34] ^ nlllO0O))) & (~ (comp_pat[35] ^ nlllOii))) & (~ (comp_pat[36] ^ nlllOil))) & (~ (comp_pat[37] ^ nlllOiO))) & (~ (comp_pat[38] ^ nlllOli))) & (~ (comp_pat[39] ^ nlllOll))),
		n10i1lO = ((((((((((~ ((~ comp_pat[30]) ^ nlllO1l)) & (~ ((~ comp_pat[31]) ^ nlllO1O))) & (~ ((~ comp_pat[32]) ^ nlllO0i))) & (~ ((~ comp_pat[33]) ^ nlllO0l))) & (~ ((~ comp_pat[34]) ^ nlllO0O))) & (~ ((~ comp_pat[35]) ^ nlllOii))) & (~ ((~ comp_pat[36]) ^ nlllOil))) & (~ ((~ comp_pat[37]) ^ nlllOiO))) & (~ ((~ comp_pat[38]) ^ nlllOli))) & (~ ((~ comp_pat[39]) ^ nlllOll))),
		n10i1Oi = (n10l0il & (((comp_pat_porn & n10i01l) | n10i01i) & ((comp_pat_porn & n10i1OO) | n10i1Ol))),
		n10i1Ol = ((((((((((~ (comp_pat[20] ^ nllll0O)) & (~ (comp_pat[21] ^ nllllii))) & (~ (comp_pat[22] ^ nllllil))) & (~ (comp_pat[23] ^ nlllliO))) & (~ (comp_pat[24] ^ nllllli))) & (~ (comp_pat[25] ^ nllllll))) & (~ (comp_pat[26] ^ nlllllO))) & (~ (comp_pat[27] ^ nllllOi))) & (~ (comp_pat[28] ^ nllllOl))) & (~ (comp_pat[29] ^ nllllOO))),
		n10i1OO = ((((((((((~ ((~ comp_pat[20]) ^ nllll0O)) & (~ ((~ comp_pat[21]) ^ nllllii))) & (~ ((~ comp_pat[22]) ^ nllllil))) & (~ ((~ comp_pat[23]) ^ nlllliO))) & (~ ((~ comp_pat[24]) ^ nllllli))) & (~ ((~ comp_pat[25]) ^ nllllll))) & (~ ((~ comp_pat[26]) ^ nlllllO))) & (~ ((~ comp_pat[27]) ^ nllllOi))) & (~ ((~ comp_pat[28]) ^ nllllOl))) & (~ ((~ comp_pat[29]) ^ nllllOO))),
		n10ii0i = ((((((((((~ (comp_pat[20] ^ nllll1l)) & (~ (comp_pat[21] ^ nllll1O))) & (~ (comp_pat[22] ^ nllll0i))) & (~ (comp_pat[23] ^ nllll0l))) & (~ (comp_pat[24] ^ nllll0O))) & (~ (comp_pat[25] ^ nllllii))) & (~ (comp_pat[26] ^ nllllil))) & (~ (comp_pat[27] ^ nlllliO))) & (~ (comp_pat[28] ^ nllllli))) & (~ (comp_pat[29] ^ nllllll))),
		n10ii0l = ((((((((((~ ((~ comp_pat[20]) ^ nllll1l)) & (~ ((~ comp_pat[21]) ^ nllll1O))) & (~ ((~ comp_pat[22]) ^ nllll0i))) & (~ ((~ comp_pat[23]) ^ nllll0l))) & (~ ((~ comp_pat[24]) ^ nllll0O))) & (~ ((~ comp_pat[25]) ^ nllllii))) & (~ ((~ comp_pat[26]) ^ nllllil))) & (~ ((~ comp_pat[27]) ^ nlllliO))) & (~ ((~ comp_pat[28]) ^ nllllli))) & (~ ((~ comp_pat[29]) ^ nllllll))),
		n10ii0O = ((((((((((~ (comp_pat[30] ^ nlllllO)) & (~ (comp_pat[31] ^ nllllOi))) & (~ (comp_pat[32] ^ nllllOl))) & (~ (comp_pat[33] ^ nllllOO))) & (~ (comp_pat[34] ^ nlllO1i))) & (~ (comp_pat[35] ^ nlllO1l))) & (~ (comp_pat[36] ^ nlllO1O))) & (~ (comp_pat[37] ^ nlllO0i))) & (~ (comp_pat[38] ^ nlllO0l))) & (~ (comp_pat[39] ^ nlllO0O))),
		n10ii1i = ((((((((((~ (comp_pat[30] ^ nllllOi)) & (~ (comp_pat[31] ^ nllllOl))) & (~ (comp_pat[32] ^ nllllOO))) & (~ (comp_pat[33] ^ nlllO1i))) & (~ (comp_pat[34] ^ nlllO1l))) & (~ (comp_pat[35] ^ nlllO1O))) & (~ (comp_pat[36] ^ nlllO0i))) & (~ (comp_pat[37] ^ nlllO0l))) & (~ (comp_pat[38] ^ nlllO0O))) & (~ (comp_pat[39] ^ nlllOii))),
		n10ii1l = ((((((((((~ ((~ comp_pat[30]) ^ nllllOi)) & (~ ((~ comp_pat[31]) ^ nllllOl))) & (~ ((~ comp_pat[32]) ^ nllllOO))) & (~ ((~ comp_pat[33]) ^ nlllO1i))) & (~ ((~ comp_pat[34]) ^ nlllO1l))) & (~ ((~ comp_pat[35]) ^ nlllO1O))) & (~ ((~ comp_pat[36]) ^ nlllO0i))) & (~ ((~ comp_pat[37]) ^ nlllO0l))) & (~ ((~ comp_pat[38]) ^ nlllO0O))) & (~ ((~ comp_pat[39]) ^ nlllOii))),
		n10ii1O = (n10li0l & (((comp_pat_porn & n10iiii) | n10ii0O) & ((comp_pat_porn & n10ii0l) | n10ii0i))),
		n10iiii = ((((((((((~ ((~ comp_pat[30]) ^ nlllllO)) & (~ ((~ comp_pat[31]) ^ nllllOi))) & (~ ((~ comp_pat[32]) ^ nllllOl))) & (~ ((~ comp_pat[33]) ^ nllllOO))) & (~ ((~ comp_pat[34]) ^ nlllO1i))) & (~ ((~ comp_pat[35]) ^ nlllO1l))) & (~ ((~ comp_pat[36]) ^ nlllO1O))) & (~ ((~ comp_pat[37]) ^ nlllO0i))) & (~ ((~ comp_pat[38]) ^ nlllO0l))) & (~ ((~ comp_pat[39]) ^ nlllO0O))),
		n10iiil = (n10liil & (((comp_pat_porn & n10iilO) | n10iill) & ((comp_pat_porn & n10iili) | n10iiiO))),
		n10iiiO = ((((((((((~ (comp_pat[20] ^ nllll1i)) & (~ (comp_pat[21] ^ nllll1l))) & (~ (comp_pat[22] ^ nllll1O))) & (~ (comp_pat[23] ^ nllll0i))) & (~ (comp_pat[24] ^ nllll0l))) & (~ (comp_pat[25] ^ nllll0O))) & (~ (comp_pat[26] ^ nllllii))) & (~ (comp_pat[27] ^ nllllil))) & (~ (comp_pat[28] ^ nlllliO))) & (~ (comp_pat[29] ^ nllllli))),
		n10iili = ((((((((((~ ((~ comp_pat[20]) ^ nllll1i)) & (~ ((~ comp_pat[21]) ^ nllll1l))) & (~ ((~ comp_pat[22]) ^ nllll1O))) & (~ ((~ comp_pat[23]) ^ nllll0i))) & (~ ((~ comp_pat[24]) ^ nllll0l))) & (~ ((~ comp_pat[25]) ^ nllll0O))) & (~ ((~ comp_pat[26]) ^ nllllii))) & (~ ((~ comp_pat[27]) ^ nllllil))) & (~ ((~ comp_pat[28]) ^ nlllliO))) & (~ ((~ comp_pat[29]) ^ nllllli))),
		n10iill = ((((((((((~ (comp_pat[30] ^ nllllll)) & (~ (comp_pat[31] ^ nlllllO))) & (~ (comp_pat[32] ^ nllllOi))) & (~ (comp_pat[33] ^ nllllOl))) & (~ (comp_pat[34] ^ nllllOO))) & (~ (comp_pat[35] ^ nlllO1i))) & (~ (comp_pat[36] ^ nlllO1l))) & (~ (comp_pat[37] ^ nlllO1O))) & (~ (comp_pat[38] ^ nlllO0i))) & (~ (comp_pat[39] ^ nlllO0l))),
		n10iilO = ((((((((((~ ((~ comp_pat[30]) ^ nllllll)) & (~ ((~ comp_pat[31]) ^ nlllllO))) & (~ ((~ comp_pat[32]) ^ nllllOi))) & (~ ((~ comp_pat[33]) ^ nllllOl))) & (~ ((~ comp_pat[34]) ^ nllllOO))) & (~ ((~ comp_pat[35]) ^ nlllO1i))) & (~ ((~ comp_pat[36]) ^ nlllO1l))) & (~ ((~ comp_pat[37]) ^ nlllO1O))) & (~ ((~ comp_pat[38]) ^ nlllO0i))) & (~ ((~ comp_pat[39]) ^ nlllO0l))),
		n10iiOi = (n10lill & (((comp_pat_porn & n10il1l) | n10il1i) & ((comp_pat_porn & n10iiOO) | n10iiOl))),
		n10iiOl = ((((((((((~ (comp_pat[20] ^ nllliOO)) & (~ (comp_pat[21] ^ nllll1i))) & (~ (comp_pat[22] ^ nllll1l))) & (~ (comp_pat[23] ^ nllll1O))) & (~ (comp_pat[24] ^ nllll0i))) & (~ (comp_pat[25] ^ nllll0l))) & (~ (comp_pat[26] ^ nllll0O))) & (~ (comp_pat[27] ^ nllllii))) & (~ (comp_pat[28] ^ nllllil))) & (~ (comp_pat[29] ^ nlllliO))),
		n10iiOO = ((((((((((~ ((~ comp_pat[20]) ^ nllliOO)) & (~ ((~ comp_pat[21]) ^ nllll1i))) & (~ ((~ comp_pat[22]) ^ nllll1l))) & (~ ((~ comp_pat[23]) ^ nllll1O))) & (~ ((~ comp_pat[24]) ^ nllll0i))) & (~ ((~ comp_pat[25]) ^ nllll0l))) & (~ ((~ comp_pat[26]) ^ nllll0O))) & (~ ((~ comp_pat[27]) ^ nllllii))) & (~ ((~ comp_pat[28]) ^ nllllil))) & (~ ((~ comp_pat[29]) ^ nlllliO))),
		n10il0i = ((((((((((~ (comp_pat[20] ^ nllliOl)) & (~ (comp_pat[21] ^ nllliOO))) & (~ (comp_pat[22] ^ nllll1i))) & (~ (comp_pat[23] ^ nllll1l))) & (~ (comp_pat[24] ^ nllll1O))) & (~ (comp_pat[25] ^ nllll0i))) & (~ (comp_pat[26] ^ nllll0l))) & (~ (comp_pat[27] ^ nllll0O))) & (~ (comp_pat[28] ^ nllllii))) & (~ (comp_pat[29] ^ nllllil))),
		n10il0l = ((((((((((~ ((~ comp_pat[20]) ^ nllliOl)) & (~ ((~ comp_pat[21]) ^ nllliOO))) & (~ ((~ comp_pat[22]) ^ nllll1i))) & (~ ((~ comp_pat[23]) ^ nllll1l))) & (~ ((~ comp_pat[24]) ^ nllll1O))) & (~ ((~ comp_pat[25]) ^ nllll0i))) & (~ ((~ comp_pat[26]) ^ nllll0l))) & (~ ((~ comp_pat[27]) ^ nllll0O))) & (~ ((~ comp_pat[28]) ^ nllllii))) & (~ ((~ comp_pat[29]) ^ nllllil))),
		n10il0O = ((((((((((~ (comp_pat[30] ^ nlllliO)) & (~ (comp_pat[31] ^ nllllli))) & (~ (comp_pat[32] ^ nllllll))) & (~ (comp_pat[33] ^ nlllllO))) & (~ (comp_pat[34] ^ nllllOi))) & (~ (comp_pat[35] ^ nllllOl))) & (~ (comp_pat[36] ^ nllllOO))) & (~ (comp_pat[37] ^ nlllO1i))) & (~ (comp_pat[38] ^ nlllO1l))) & (~ (comp_pat[39] ^ nlllO1O))),
		n10il1i = ((((((((((~ (comp_pat[30] ^ nllllli)) & (~ (comp_pat[31] ^ nllllll))) & (~ (comp_pat[32] ^ nlllllO))) & (~ (comp_pat[33] ^ nllllOi))) & (~ (comp_pat[34] ^ nllllOl))) & (~ (comp_pat[35] ^ nllllOO))) & (~ (comp_pat[36] ^ nlllO1i))) & (~ (comp_pat[37] ^ nlllO1l))) & (~ (comp_pat[38] ^ nlllO1O))) & (~ (comp_pat[39] ^ nlllO0i))),
		n10il1l = ((((((((((~ ((~ comp_pat[30]) ^ nllllli)) & (~ ((~ comp_pat[31]) ^ nllllll))) & (~ ((~ comp_pat[32]) ^ nlllllO))) & (~ ((~ comp_pat[33]) ^ nllllOi))) & (~ ((~ comp_pat[34]) ^ nllllOl))) & (~ ((~ comp_pat[35]) ^ nllllOO))) & (~ ((~ comp_pat[36]) ^ nlllO1i))) & (~ ((~ comp_pat[37]) ^ nlllO1l))) & (~ ((~ comp_pat[38]) ^ nlllO1O))) & (~ ((~ comp_pat[39]) ^ nlllO0i))),
		n10il1O = (n10liOl & (((comp_pat_porn & n10ilii) | n10il0O) & ((comp_pat_porn & n10il0l) | n10il0i))),
		n10ilii = ((((((((((~ ((~ comp_pat[30]) ^ nlllliO)) & (~ ((~ comp_pat[31]) ^ nllllli))) & (~ ((~ comp_pat[32]) ^ nllllll))) & (~ ((~ comp_pat[33]) ^ nlllllO))) & (~ ((~ comp_pat[34]) ^ nllllOi))) & (~ ((~ comp_pat[35]) ^ nllllOl))) & (~ ((~ comp_pat[36]) ^ nllllOO))) & (~ ((~ comp_pat[37]) ^ nlllO1i))) & (~ ((~ comp_pat[38]) ^ nlllO1l))) & (~ ((~ comp_pat[39]) ^ nlllO1O))),
		n10ilil = (n10ll1l & (((comp_pat_porn & n10illO) | n10illl) & ((comp_pat_porn & n10illi) | n10iliO))),
		n10iliO = ((((((((((~ (comp_pat[20] ^ nllliOi)) & (~ (comp_pat[21] ^ nllliOl))) & (~ (comp_pat[22] ^ nllliOO))) & (~ (comp_pat[23] ^ nllll1i))) & (~ (comp_pat[24] ^ nllll1l))) & (~ (comp_pat[25] ^ nllll1O))) & (~ (comp_pat[26] ^ nllll0i))) & (~ (comp_pat[27] ^ nllll0l))) & (~ (comp_pat[28] ^ nllll0O))) & (~ (comp_pat[29] ^ nllllii))),
		n10illi = ((((((((((~ ((~ comp_pat[20]) ^ nllliOi)) & (~ ((~ comp_pat[21]) ^ nllliOl))) & (~ ((~ comp_pat[22]) ^ nllliOO))) & (~ ((~ comp_pat[23]) ^ nllll1i))) & (~ ((~ comp_pat[24]) ^ nllll1l))) & (~ ((~ comp_pat[25]) ^ nllll1O))) & (~ ((~ comp_pat[26]) ^ nllll0i))) & (~ ((~ comp_pat[27]) ^ nllll0l))) & (~ ((~ comp_pat[28]) ^ nllll0O))) & (~ ((~ comp_pat[29]) ^ nllllii))),
		n10illl = ((((((((((~ (comp_pat[30] ^ nllllil)) & (~ (comp_pat[31] ^ nlllliO))) & (~ (comp_pat[32] ^ nllllli))) & (~ (comp_pat[33] ^ nllllll))) & (~ (comp_pat[34] ^ nlllllO))) & (~ (comp_pat[35] ^ nllllOi))) & (~ (comp_pat[36] ^ nllllOl))) & (~ (comp_pat[37] ^ nllllOO))) & (~ (comp_pat[38] ^ nlllO1i))) & (~ (comp_pat[39] ^ nlllO1l))),
		n10illO = ((((((((((~ ((~ comp_pat[30]) ^ nllllil)) & (~ ((~ comp_pat[31]) ^ nlllliO))) & (~ ((~ comp_pat[32]) ^ nllllli))) & (~ ((~ comp_pat[33]) ^ nllllll))) & (~ ((~ comp_pat[34]) ^ nlllllO))) & (~ ((~ comp_pat[35]) ^ nllllOi))) & (~ ((~ comp_pat[36]) ^ nllllOl))) & (~ ((~ comp_pat[37]) ^ nllllOO))) & (~ ((~ comp_pat[38]) ^ nlllO1i))) & (~ ((~ comp_pat[39]) ^ nlllO1l))),
		n10ilOi = (n10ll0l & (((comp_pat_porn & n10iO1l) | n10iO1i) & ((comp_pat_porn & n10ilOO) | n10ilOl))),
		n10ilOl = ((((((((((~ (comp_pat[20] ^ nlllilO)) & (~ (comp_pat[21] ^ nllliOi))) & (~ (comp_pat[22] ^ nllliOl))) & (~ (comp_pat[23] ^ nllliOO))) & (~ (comp_pat[24] ^ nllll1i))) & (~ (comp_pat[25] ^ nllll1l))) & (~ (comp_pat[26] ^ nllll1O))) & (~ (comp_pat[27] ^ nllll0i))) & (~ (comp_pat[28] ^ nllll0l))) & (~ (comp_pat[29] ^ nllll0O))),
		n10ilOO = ((((((((((~ ((~ comp_pat[20]) ^ nlllilO)) & (~ ((~ comp_pat[21]) ^ nllliOi))) & (~ ((~ comp_pat[22]) ^ nllliOl))) & (~ ((~ comp_pat[23]) ^ nllliOO))) & (~ ((~ comp_pat[24]) ^ nllll1i))) & (~ ((~ comp_pat[25]) ^ nllll1l))) & (~ ((~ comp_pat[26]) ^ nllll1O))) & (~ ((~ comp_pat[27]) ^ nllll0i))) & (~ ((~ comp_pat[28]) ^ nllll0l))) & (~ ((~ comp_pat[29]) ^ nllll0O))),
		n10iO0i = ((((((((((~ (comp_pat[20] ^ nlllill)) & (~ (comp_pat[21] ^ nlllilO))) & (~ (comp_pat[22] ^ nllliOi))) & (~ (comp_pat[23] ^ nllliOl))) & (~ (comp_pat[24] ^ nllliOO))) & (~ (comp_pat[25] ^ nllll1i))) & (~ (comp_pat[26] ^ nllll1l))) & (~ (comp_pat[27] ^ nllll1O))) & (~ (comp_pat[28] ^ nllll0i))) & (~ (comp_pat[29] ^ nllll0l))),
		n10iO0l = ((((((((((~ ((~ comp_pat[20]) ^ nlllill)) & (~ ((~ comp_pat[21]) ^ nlllilO))) & (~ ((~ comp_pat[22]) ^ nllliOi))) & (~ ((~ comp_pat[23]) ^ nllliOl))) & (~ ((~ comp_pat[24]) ^ nllliOO))) & (~ ((~ comp_pat[25]) ^ nllll1i))) & (~ ((~ comp_pat[26]) ^ nllll1l))) & (~ ((~ comp_pat[27]) ^ nllll1O))) & (~ ((~ comp_pat[28]) ^ nllll0i))) & (~ ((~ comp_pat[29]) ^ nllll0l))),
		n10iO0O = ((((((((((~ (comp_pat[30] ^ nllll0O)) & (~ (comp_pat[31] ^ nllllii))) & (~ (comp_pat[32] ^ nllllil))) & (~ (comp_pat[33] ^ nlllliO))) & (~ (comp_pat[34] ^ nllllli))) & (~ (comp_pat[35] ^ nllllll))) & (~ (comp_pat[36] ^ nlllllO))) & (~ (comp_pat[37] ^ nllllOi))) & (~ (comp_pat[38] ^ nllllOl))) & (~ (comp_pat[39] ^ nllllOO))),
		n10iO1i = ((((((((((~ (comp_pat[30] ^ nllllii)) & (~ (comp_pat[31] ^ nllllil))) & (~ (comp_pat[32] ^ nlllliO))) & (~ (comp_pat[33] ^ nllllli))) & (~ (comp_pat[34] ^ nllllll))) & (~ (comp_pat[35] ^ nlllllO))) & (~ (comp_pat[36] ^ nllllOi))) & (~ (comp_pat[37] ^ nllllOl))) & (~ (comp_pat[38] ^ nllllOO))) & (~ (comp_pat[39] ^ nlllO1i))),
		n10iO1l = ((((((((((~ ((~ comp_pat[30]) ^ nllllii)) & (~ ((~ comp_pat[31]) ^ nllllil))) & (~ ((~ comp_pat[32]) ^ nlllliO))) & (~ ((~ comp_pat[33]) ^ nllllli))) & (~ ((~ comp_pat[34]) ^ nllllll))) & (~ ((~ comp_pat[35]) ^ nlllllO))) & (~ ((~ comp_pat[36]) ^ nllllOi))) & (~ ((~ comp_pat[37]) ^ nllllOl))) & (~ ((~ comp_pat[38]) ^ nllllOO))) & (~ ((~ comp_pat[39]) ^ nlllO1i))),
		n10iO1O = (n10llil & (((comp_pat_porn & n10iOii) | n10iO0O) & ((comp_pat_porn & n10iO0l) | n10iO0i))),
		n10iOii = ((((((((((~ ((~ comp_pat[30]) ^ nllll0O)) & (~ ((~ comp_pat[31]) ^ nllllii))) & (~ ((~ comp_pat[32]) ^ nllllil))) & (~ ((~ comp_pat[33]) ^ nlllliO))) & (~ ((~ comp_pat[34]) ^ nllllli))) & (~ ((~ comp_pat[35]) ^ nllllll))) & (~ ((~ comp_pat[36]) ^ nlllllO))) & (~ ((~ comp_pat[37]) ^ nllllOi))) & (~ ((~ comp_pat[38]) ^ nllllOl))) & (~ ((~ comp_pat[39]) ^ nllllOO))),
		n10iOil = (n10llll & (((comp_pat_porn & n10iOlO) | n10iOll) & ((comp_pat_porn & n10iOli) | n10iOiO))),
		n10iOiO = ((((((((((~ (comp_pat[20] ^ nlllili)) & (~ (comp_pat[21] ^ nlllill))) & (~ (comp_pat[22] ^ nlllilO))) & (~ (comp_pat[23] ^ nllliOi))) & (~ (comp_pat[24] ^ nllliOl))) & (~ (comp_pat[25] ^ nllliOO))) & (~ (comp_pat[26] ^ nllll1i))) & (~ (comp_pat[27] ^ nllll1l))) & (~ (comp_pat[28] ^ nllll1O))) & (~ (comp_pat[29] ^ nllll0i))),
		n10iOli = ((((((((((~ ((~ comp_pat[20]) ^ nlllili)) & (~ ((~ comp_pat[21]) ^ nlllill))) & (~ ((~ comp_pat[22]) ^ nlllilO))) & (~ ((~ comp_pat[23]) ^ nllliOi))) & (~ ((~ comp_pat[24]) ^ nllliOl))) & (~ ((~ comp_pat[25]) ^ nllliOO))) & (~ ((~ comp_pat[26]) ^ nllll1i))) & (~ ((~ comp_pat[27]) ^ nllll1l))) & (~ ((~ comp_pat[28]) ^ nllll1O))) & (~ ((~ comp_pat[29]) ^ nllll0i))),
		n10iOll = ((((((((((~ (comp_pat[30] ^ nllll0l)) & (~ (comp_pat[31] ^ nllll0O))) & (~ (comp_pat[32] ^ nllllii))) & (~ (comp_pat[33] ^ nllllil))) & (~ (comp_pat[34] ^ nlllliO))) & (~ (comp_pat[35] ^ nllllli))) & (~ (comp_pat[36] ^ nllllll))) & (~ (comp_pat[37] ^ nlllllO))) & (~ (comp_pat[38] ^ nllllOi))) & (~ (comp_pat[39] ^ nllllOl))),
		n10iOlO = ((((((((((~ ((~ comp_pat[30]) ^ nllll0l)) & (~ ((~ comp_pat[31]) ^ nllll0O))) & (~ ((~ comp_pat[32]) ^ nllllii))) & (~ ((~ comp_pat[33]) ^ nllllil))) & (~ ((~ comp_pat[34]) ^ nlllliO))) & (~ ((~ comp_pat[35]) ^ nllllli))) & (~ ((~ comp_pat[36]) ^ nllllll))) & (~ ((~ comp_pat[37]) ^ nlllllO))) & (~ ((~ comp_pat[38]) ^ nllllOi))) & (~ ((~ comp_pat[39]) ^ nllllOl))),
		n10iOOi = (((((((((((((((((((n10llll | n10llil) | n10ll0l) | n10ll1l) | n10liOl) | n10lill) | n10liil) | n10li0l) | n10li1l) | n10l0Ol) | n10l0ll) | n10l0il) | n10l00l) | n10l01l) | n10l1Ol) | n10l1ll) | n10l1il) | n10l10l) | n10l11l) | n10iOOl),
		n10iOOl = (n10llOO & ((comp_pat_porn & n10l11i) | n10iOOO)),
		n10iOOO = ((((((((((~ (comp_pat[10] ^ nllll0i)) & (~ (comp_pat[11] ^ nllll0l))) & (~ (comp_pat[12] ^ nllll0O))) & (~ (comp_pat[13] ^ nllllii))) & (~ (comp_pat[14] ^ nllllil))) & (~ (comp_pat[15] ^ nlllliO))) & (~ (comp_pat[16] ^ nllllli))) & (~ (comp_pat[17] ^ nllllll))) & (~ (comp_pat[18] ^ nlllllO))) & (~ (comp_pat[19] ^ nllllOi))),
		n10l00i = ((((((((((~ ((~ comp_pat[10]) ^ nllliOi)) & (~ ((~ comp_pat[11]) ^ nllliOl))) & (~ ((~ comp_pat[12]) ^ nllliOO))) & (~ ((~ comp_pat[13]) ^ nllll1i))) & (~ ((~ comp_pat[14]) ^ nllll1l))) & (~ ((~ comp_pat[15]) ^ nllll1O))) & (~ ((~ comp_pat[16]) ^ nllll0i))) & (~ ((~ comp_pat[17]) ^ nllll0l))) & (~ ((~ comp_pat[18]) ^ nllll0O))) & (~ ((~ comp_pat[19]) ^ nllllii))),
		n10l00l = (n10O10O & ((comp_pat_porn & n10l0ii) | n10l00O)),
		n10l00O = ((((((((((~ (comp_pat[10] ^ nlllilO)) & (~ (comp_pat[11] ^ nllliOi))) & (~ (comp_pat[12] ^ nllliOl))) & (~ (comp_pat[13] ^ nllliOO))) & (~ (comp_pat[14] ^ nllll1i))) & (~ (comp_pat[15] ^ nllll1l))) & (~ (comp_pat[16] ^ nllll1O))) & (~ (comp_pat[17] ^ nllll0i))) & (~ (comp_pat[18] ^ nllll0l))) & (~ (comp_pat[19] ^ nllll0O))),
		n10l01i = ((((((((((~ ((~ comp_pat[10]) ^ nllliOl)) & (~ ((~ comp_pat[11]) ^ nllliOO))) & (~ ((~ comp_pat[12]) ^ nllll1i))) & (~ ((~ comp_pat[13]) ^ nllll1l))) & (~ ((~ comp_pat[14]) ^ nllll1O))) & (~ ((~ comp_pat[15]) ^ nllll0i))) & (~ ((~ comp_pat[16]) ^ nllll0l))) & (~ ((~ comp_pat[17]) ^ nllll0O))) & (~ ((~ comp_pat[18]) ^ nllllii))) & (~ ((~ comp_pat[19]) ^ nllllil))),
		n10l01l = (n10O11O & ((comp_pat_porn & n10l00i) | n10l01O)),
		n10l01O = ((((((((((~ (comp_pat[10] ^ nllliOi)) & (~ (comp_pat[11] ^ nllliOl))) & (~ (comp_pat[12] ^ nllliOO))) & (~ (comp_pat[13] ^ nllll1i))) & (~ (comp_pat[14] ^ nllll1l))) & (~ (comp_pat[15] ^ nllll1O))) & (~ (comp_pat[16] ^ nllll0i))) & (~ (comp_pat[17] ^ nllll0l))) & (~ (comp_pat[18] ^ nllll0O))) & (~ (comp_pat[19] ^ nllllii))),
		n10l0ii = ((((((((((~ ((~ comp_pat[10]) ^ nlllilO)) & (~ ((~ comp_pat[11]) ^ nllliOi))) & (~ ((~ comp_pat[12]) ^ nllliOl))) & (~ ((~ comp_pat[13]) ^ nllliOO))) & (~ ((~ comp_pat[14]) ^ nllll1i))) & (~ ((~ comp_pat[15]) ^ nllll1l))) & (~ ((~ comp_pat[16]) ^ nllll1O))) & (~ ((~ comp_pat[17]) ^ nllll0i))) & (~ ((~ comp_pat[18]) ^ nllll0l))) & (~ ((~ comp_pat[19]) ^ nllll0O))),
		n10l0il = (n10O1iO & ((comp_pat_porn & n10l0li) | n10l0iO)),
		n10l0iO = ((((((((((~ (comp_pat[10] ^ nlllill)) & (~ (comp_pat[11] ^ nlllilO))) & (~ (comp_pat[12] ^ nllliOi))) & (~ (comp_pat[13] ^ nllliOl))) & (~ (comp_pat[14] ^ nllliOO))) & (~ (comp_pat[15] ^ nllll1i))) & (~ (comp_pat[16] ^ nllll1l))) & (~ (comp_pat[17] ^ nllll1O))) & (~ (comp_pat[18] ^ nllll0i))) & (~ (comp_pat[19] ^ nllll0l))),
		n10l0li = ((((((((((~ ((~ comp_pat[10]) ^ nlllill)) & (~ ((~ comp_pat[11]) ^ nlllilO))) & (~ ((~ comp_pat[12]) ^ nllliOi))) & (~ ((~ comp_pat[13]) ^ nllliOl))) & (~ ((~ comp_pat[14]) ^ nllliOO))) & (~ ((~ comp_pat[15]) ^ nllll1i))) & (~ ((~ comp_pat[16]) ^ nllll1l))) & (~ ((~ comp_pat[17]) ^ nllll1O))) & (~ ((~ comp_pat[18]) ^ nllll0i))) & (~ ((~ comp_pat[19]) ^ nllll0l))),
		n10l0ll = (n10O1lO & ((comp_pat_porn & n10l0Oi) | n10l0lO)),
		n10l0lO = ((((((((((~ (comp_pat[10] ^ nlllili)) & (~ (comp_pat[11] ^ nlllill))) & (~ (comp_pat[12] ^ nlllilO))) & (~ (comp_pat[13] ^ nllliOi))) & (~ (comp_pat[14] ^ nllliOl))) & (~ (comp_pat[15] ^ nllliOO))) & (~ (comp_pat[16] ^ nllll1i))) & (~ (comp_pat[17] ^ nllll1l))) & (~ (comp_pat[18] ^ nllll1O))) & (~ (comp_pat[19] ^ nllll0i))),
		n10l0Oi = ((((((((((~ ((~ comp_pat[10]) ^ nlllili)) & (~ ((~ comp_pat[11]) ^ nlllill))) & (~ ((~ comp_pat[12]) ^ nlllilO))) & (~ ((~ comp_pat[13]) ^ nllliOi))) & (~ ((~ comp_pat[14]) ^ nllliOl))) & (~ ((~ comp_pat[15]) ^ nllliOO))) & (~ ((~ comp_pat[16]) ^ nllll1i))) & (~ ((~ comp_pat[17]) ^ nllll1l))) & (~ ((~ comp_pat[18]) ^ nllll1O))) & (~ ((~ comp_pat[19]) ^ nllll0i))),
		n10l0Ol = (n10O1OO & ((comp_pat_porn & n10li1i) | n10l0OO)),
		n10l0OO = ((((((((((~ (comp_pat[10] ^ nllliiO)) & (~ (comp_pat[11] ^ nlllili))) & (~ (comp_pat[12] ^ nlllill))) & (~ (comp_pat[13] ^ nlllilO))) & (~ (comp_pat[14] ^ nllliOi))) & (~ (comp_pat[15] ^ nllliOl))) & (~ (comp_pat[16] ^ nllliOO))) & (~ (comp_pat[17] ^ nllll1i))) & (~ (comp_pat[18] ^ nllll1l))) & (~ (comp_pat[19] ^ nllll1O))),
		n10l10i = ((((((((((~ ((~ comp_pat[10]) ^ nllll1O)) & (~ ((~ comp_pat[11]) ^ nllll0i))) & (~ ((~ comp_pat[12]) ^ nllll0l))) & (~ ((~ comp_pat[13]) ^ nllll0O))) & (~ ((~ comp_pat[14]) ^ nllllii))) & (~ ((~ comp_pat[15]) ^ nllllil))) & (~ ((~ comp_pat[16]) ^ nlllliO))) & (~ ((~ comp_pat[17]) ^ nllllli))) & (~ ((~ comp_pat[18]) ^ nllllll))) & (~ ((~ comp_pat[19]) ^ nlllllO))),
		n10l10l = (n10lO0O & ((comp_pat_porn & n10l1ii) | n10l10O)),
		n10l10O = ((((((((((~ (comp_pat[10] ^ nllll1l)) & (~ (comp_pat[11] ^ nllll1O))) & (~ (comp_pat[12] ^ nllll0i))) & (~ (comp_pat[13] ^ nllll0l))) & (~ (comp_pat[14] ^ nllll0O))) & (~ (comp_pat[15] ^ nllllii))) & (~ (comp_pat[16] ^ nllllil))) & (~ (comp_pat[17] ^ nlllliO))) & (~ (comp_pat[18] ^ nllllli))) & (~ (comp_pat[19] ^ nllllll))),
		n10l11i = ((((((((((~ ((~ comp_pat[10]) ^ nllll0i)) & (~ ((~ comp_pat[11]) ^ nllll0l))) & (~ ((~ comp_pat[12]) ^ nllll0O))) & (~ ((~ comp_pat[13]) ^ nllllii))) & (~ ((~ comp_pat[14]) ^ nllllil))) & (~ ((~ comp_pat[15]) ^ nlllliO))) & (~ ((~ comp_pat[16]) ^ nllllli))) & (~ ((~ comp_pat[17]) ^ nllllll))) & (~ ((~ comp_pat[18]) ^ nlllllO))) & (~ ((~ comp_pat[19]) ^ nllllOi))),
		n10l11l = (n10lO1O & ((comp_pat_porn & n10l10i) | n10l11O)),
		n10l11O = ((((((((((~ (comp_pat[10] ^ nllll1O)) & (~ (comp_pat[11] ^ nllll0i))) & (~ (comp_pat[12] ^ nllll0l))) & (~ (comp_pat[13] ^ nllll0O))) & (~ (comp_pat[14] ^ nllllii))) & (~ (comp_pat[15] ^ nllllil))) & (~ (comp_pat[16] ^ nlllliO))) & (~ (comp_pat[17] ^ nllllli))) & (~ (comp_pat[18] ^ nllllll))) & (~ (comp_pat[19] ^ nlllllO))),
		n10l1ii = ((((((((((~ ((~ comp_pat[10]) ^ nllll1l)) & (~ ((~ comp_pat[11]) ^ nllll1O))) & (~ ((~ comp_pat[12]) ^ nllll0i))) & (~ ((~ comp_pat[13]) ^ nllll0l))) & (~ ((~ comp_pat[14]) ^ nllll0O))) & (~ ((~ comp_pat[15]) ^ nllllii))) & (~ ((~ comp_pat[16]) ^ nllllil))) & (~ ((~ comp_pat[17]) ^ nlllliO))) & (~ ((~ comp_pat[18]) ^ nllllli))) & (~ ((~ comp_pat[19]) ^ nllllll))),
		n10l1il = (n10lOiO & ((comp_pat_porn & n10l1li) | n10l1iO)),
		n10l1iO = ((((((((((~ (comp_pat[10] ^ nllll1i)) & (~ (comp_pat[11] ^ nllll1l))) & (~ (comp_pat[12] ^ nllll1O))) & (~ (comp_pat[13] ^ nllll0i))) & (~ (comp_pat[14] ^ nllll0l))) & (~ (comp_pat[15] ^ nllll0O))) & (~ (comp_pat[16] ^ nllllii))) & (~ (comp_pat[17] ^ nllllil))) & (~ (comp_pat[18] ^ nlllliO))) & (~ (comp_pat[19] ^ nllllli))),
		n10l1li = ((((((((((~ ((~ comp_pat[10]) ^ nllll1i)) & (~ ((~ comp_pat[11]) ^ nllll1l))) & (~ ((~ comp_pat[12]) ^ nllll1O))) & (~ ((~ comp_pat[13]) ^ nllll0i))) & (~ ((~ comp_pat[14]) ^ nllll0l))) & (~ ((~ comp_pat[15]) ^ nllll0O))) & (~ ((~ comp_pat[16]) ^ nllllii))) & (~ ((~ comp_pat[17]) ^ nllllil))) & (~ ((~ comp_pat[18]) ^ nlllliO))) & (~ ((~ comp_pat[19]) ^ nllllli))),
		n10l1ll = (n10lOlO & ((comp_pat_porn & n10l1Oi) | n10l1lO)),
		n10l1lO = ((((((((((~ (comp_pat[10] ^ nllliOO)) & (~ (comp_pat[11] ^ nllll1i))) & (~ (comp_pat[12] ^ nllll1l))) & (~ (comp_pat[13] ^ nllll1O))) & (~ (comp_pat[14] ^ nllll0i))) & (~ (comp_pat[15] ^ nllll0l))) & (~ (comp_pat[16] ^ nllll0O))) & (~ (comp_pat[17] ^ nllllii))) & (~ (comp_pat[18] ^ nllllil))) & (~ (comp_pat[19] ^ nlllliO))),
		n10l1Oi = ((((((((((~ ((~ comp_pat[10]) ^ nllliOO)) & (~ ((~ comp_pat[11]) ^ nllll1i))) & (~ ((~ comp_pat[12]) ^ nllll1l))) & (~ ((~ comp_pat[13]) ^ nllll1O))) & (~ ((~ comp_pat[14]) ^ nllll0i))) & (~ ((~ comp_pat[15]) ^ nllll0l))) & (~ ((~ comp_pat[16]) ^ nllll0O))) & (~ ((~ comp_pat[17]) ^ nllllii))) & (~ ((~ comp_pat[18]) ^ nllllil))) & (~ ((~ comp_pat[19]) ^ nlllliO))),
		n10l1Ol = (n10lOOO & ((comp_pat_porn & n10l01i) | n10l1OO)),
		n10l1OO = ((((((((((~ (comp_pat[10] ^ nllliOl)) & (~ (comp_pat[11] ^ nllliOO))) & (~ (comp_pat[12] ^ nllll1i))) & (~ (comp_pat[13] ^ nllll1l))) & (~ (comp_pat[14] ^ nllll1O))) & (~ (comp_pat[15] ^ nllll0i))) & (~ (comp_pat[16] ^ nllll0l))) & (~ (comp_pat[17] ^ nllll0O))) & (~ (comp_pat[18] ^ nllllii))) & (~ (comp_pat[19] ^ nllllil))),
		n10li0i = ((((((((((~ ((~ comp_pat[10]) ^ nllliil)) & (~ ((~ comp_pat[11]) ^ nllliiO))) & (~ ((~ comp_pat[12]) ^ nlllili))) & (~ ((~ comp_pat[13]) ^ nlllill))) & (~ ((~ comp_pat[14]) ^ nlllilO))) & (~ ((~ comp_pat[15]) ^ nllliOi))) & (~ ((~ comp_pat[16]) ^ nllliOl))) & (~ ((~ comp_pat[17]) ^ nllliOO))) & (~ ((~ comp_pat[18]) ^ nllll1i))) & (~ ((~ comp_pat[19]) ^ nllll1l))),
		n10li0l = (n10O00O & ((comp_pat_porn & n10liii) | n10li0O)),
		n10li0O = ((((((((((~ (comp_pat[10] ^ nllliii)) & (~ (comp_pat[11] ^ nllliil))) & (~ (comp_pat[12] ^ nllliiO))) & (~ (comp_pat[13] ^ nlllili))) & (~ (comp_pat[14] ^ nlllill))) & (~ (comp_pat[15] ^ nlllilO))) & (~ (comp_pat[16] ^ nllliOi))) & (~ (comp_pat[17] ^ nllliOl))) & (~ (comp_pat[18] ^ nllliOO))) & (~ (comp_pat[19] ^ nllll1i))),
		n10li1i = ((((((((((~ ((~ comp_pat[10]) ^ nllliiO)) & (~ ((~ comp_pat[11]) ^ nlllili))) & (~ ((~ comp_pat[12]) ^ nlllill))) & (~ ((~ comp_pat[13]) ^ nlllilO))) & (~ ((~ comp_pat[14]) ^ nllliOi))) & (~ ((~ comp_pat[15]) ^ nllliOl))) & (~ ((~ comp_pat[16]) ^ nllliOO))) & (~ ((~ comp_pat[17]) ^ nllll1i))) & (~ ((~ comp_pat[18]) ^ nllll1l))) & (~ ((~ comp_pat[19]) ^ nllll1O))),
		n10li1l = (n10O01O & ((comp_pat_porn & n10li0i) | n10li1O)),
		n10li1O = ((((((((((~ (comp_pat[10] ^ nllliil)) & (~ (comp_pat[11] ^ nllliiO))) & (~ (comp_pat[12] ^ nlllili))) & (~ (comp_pat[13] ^ nlllill))) & (~ (comp_pat[14] ^ nlllilO))) & (~ (comp_pat[15] ^ nllliOi))) & (~ (comp_pat[16] ^ nllliOl))) & (~ (comp_pat[17] ^ nllliOO))) & (~ (comp_pat[18] ^ nllll1i))) & (~ (comp_pat[19] ^ nllll1l))),
		n10liii = ((((((((((~ ((~ comp_pat[10]) ^ nllliii)) & (~ ((~ comp_pat[11]) ^ nllliil))) & (~ ((~ comp_pat[12]) ^ nllliiO))) & (~ ((~ comp_pat[13]) ^ nlllili))) & (~ ((~ comp_pat[14]) ^ nlllill))) & (~ ((~ comp_pat[15]) ^ nlllilO))) & (~ ((~ comp_pat[16]) ^ nllliOi))) & (~ ((~ comp_pat[17]) ^ nllliOl))) & (~ ((~ comp_pat[18]) ^ nllliOO))) & (~ ((~ comp_pat[19]) ^ nllll1i))),
		n10liil = (n10O0iO & ((comp_pat_porn & n10lili) | n10liiO)),
		n10liiO = ((((((((((~ (comp_pat[10] ^ nllli0O)) & (~ (comp_pat[11] ^ nllliii))) & (~ (comp_pat[12] ^ nllliil))) & (~ (comp_pat[13] ^ nllliiO))) & (~ (comp_pat[14] ^ nlllili))) & (~ (comp_pat[15] ^ nlllill))) & (~ (comp_pat[16] ^ nlllilO))) & (~ (comp_pat[17] ^ nllliOi))) & (~ (comp_pat[18] ^ nllliOl))) & (~ (comp_pat[19] ^ nllliOO))),
		n10lili = ((((((((((~ ((~ comp_pat[10]) ^ nllli0O)) & (~ ((~ comp_pat[11]) ^ nllliii))) & (~ ((~ comp_pat[12]) ^ nllliil))) & (~ ((~ comp_pat[13]) ^ nllliiO))) & (~ ((~ comp_pat[14]) ^ nlllili))) & (~ ((~ comp_pat[15]) ^ nlllill))) & (~ ((~ comp_pat[16]) ^ nlllilO))) & (~ ((~ comp_pat[17]) ^ nllliOi))) & (~ ((~ comp_pat[18]) ^ nllliOl))) & (~ ((~ comp_pat[19]) ^ nllliOO))),
		n10lill = (n10O0lO & ((comp_pat_porn & n10liOi) | n10lilO)),
		n10lilO = ((((((((((~ (comp_pat[10] ^ nllli0l)) & (~ (comp_pat[11] ^ nllli0O))) & (~ (comp_pat[12] ^ nllliii))) & (~ (comp_pat[13] ^ nllliil))) & (~ (comp_pat[14] ^ nllliiO))) & (~ (comp_pat[15] ^ nlllili))) & (~ (comp_pat[16] ^ nlllill))) & (~ (comp_pat[17] ^ nlllilO))) & (~ (comp_pat[18] ^ nllliOi))) & (~ (comp_pat[19] ^ nllliOl))),
		n10liOi = ((((((((((~ ((~ comp_pat[10]) ^ nllli0l)) & (~ ((~ comp_pat[11]) ^ nllli0O))) & (~ ((~ comp_pat[12]) ^ nllliii))) & (~ ((~ comp_pat[13]) ^ nllliil))) & (~ ((~ comp_pat[14]) ^ nllliiO))) & (~ ((~ comp_pat[15]) ^ nlllili))) & (~ ((~ comp_pat[16]) ^ nlllill))) & (~ ((~ comp_pat[17]) ^ nlllilO))) & (~ ((~ comp_pat[18]) ^ nllliOi))) & (~ ((~ comp_pat[19]) ^ nllliOl))),
		n10liOl = (n10O0OO & ((comp_pat_porn & n10ll1i) | n10liOO)),
		n10liOO = ((((((((((~ (comp_pat[10] ^ nllli0i)) & (~ (comp_pat[11] ^ nllli0l))) & (~ (comp_pat[12] ^ nllli0O))) & (~ (comp_pat[13] ^ nllliii))) & (~ (comp_pat[14] ^ nllliil))) & (~ (comp_pat[15] ^ nllliiO))) & (~ (comp_pat[16] ^ nlllili))) & (~ (comp_pat[17] ^ nlllill))) & (~ (comp_pat[18] ^ nlllilO))) & (~ (comp_pat[19] ^ nllliOi))),
		n10ll0i = ((((((((((~ ((~ comp_pat[10]) ^ nllli1O)) & (~ ((~ comp_pat[11]) ^ nllli0i))) & (~ ((~ comp_pat[12]) ^ nllli0l))) & (~ ((~ comp_pat[13]) ^ nllli0O))) & (~ ((~ comp_pat[14]) ^ nllliii))) & (~ ((~ comp_pat[15]) ^ nllliil))) & (~ ((~ comp_pat[16]) ^ nllliiO))) & (~ ((~ comp_pat[17]) ^ nlllili))) & (~ ((~ comp_pat[18]) ^ nlllill))) & (~ ((~ comp_pat[19]) ^ nlllilO))),
		n10ll0l = (n10Oi0O & ((comp_pat_porn & n10llii) | n10ll0O)),
		n10ll0O = ((((((((((~ (comp_pat[10] ^ nllli1l)) & (~ (comp_pat[11] ^ nllli1O))) & (~ (comp_pat[12] ^ nllli0i))) & (~ (comp_pat[13] ^ nllli0l))) & (~ (comp_pat[14] ^ nllli0O))) & (~ (comp_pat[15] ^ nllliii))) & (~ (comp_pat[16] ^ nllliil))) & (~ (comp_pat[17] ^ nllliiO))) & (~ (comp_pat[18] ^ nlllili))) & (~ (comp_pat[19] ^ nlllill))),
		n10ll1i = ((((((((((~ ((~ comp_pat[10]) ^ nllli0i)) & (~ ((~ comp_pat[11]) ^ nllli0l))) & (~ ((~ comp_pat[12]) ^ nllli0O))) & (~ ((~ comp_pat[13]) ^ nllliii))) & (~ ((~ comp_pat[14]) ^ nllliil))) & (~ ((~ comp_pat[15]) ^ nllliiO))) & (~ ((~ comp_pat[16]) ^ nlllili))) & (~ ((~ comp_pat[17]) ^ nlllill))) & (~ ((~ comp_pat[18]) ^ nlllilO))) & (~ ((~ comp_pat[19]) ^ nllliOi))),
		n10ll1l = (n10Oi1O & ((comp_pat_porn & n10ll0i) | n10ll1O)),
		n10ll1O = ((((((((((~ (comp_pat[10] ^ nllli1O)) & (~ (comp_pat[11] ^ nllli0i))) & (~ (comp_pat[12] ^ nllli0l))) & (~ (comp_pat[13] ^ nllli0O))) & (~ (comp_pat[14] ^ nllliii))) & (~ (comp_pat[15] ^ nllliil))) & (~ (comp_pat[16] ^ nllliiO))) & (~ (comp_pat[17] ^ nlllili))) & (~ (comp_pat[18] ^ nlllill))) & (~ (comp_pat[19] ^ nlllilO))),
		n10llii = ((((((((((~ ((~ comp_pat[10]) ^ nllli1l)) & (~ ((~ comp_pat[11]) ^ nllli1O))) & (~ ((~ comp_pat[12]) ^ nllli0i))) & (~ ((~ comp_pat[13]) ^ nllli0l))) & (~ ((~ comp_pat[14]) ^ nllli0O))) & (~ ((~ comp_pat[15]) ^ nllliii))) & (~ ((~ comp_pat[16]) ^ nllliil))) & (~ ((~ comp_pat[17]) ^ nllliiO))) & (~ ((~ comp_pat[18]) ^ nlllili))) & (~ ((~ comp_pat[19]) ^ nlllill))),
		n10llil = (n10OiiO & ((comp_pat_porn & n10llli) | n10lliO)),
		n10lliO = ((((((((((~ (comp_pat[10] ^ nllli1i)) & (~ (comp_pat[11] ^ nllli1l))) & (~ (comp_pat[12] ^ nllli1O))) & (~ (comp_pat[13] ^ nllli0i))) & (~ (comp_pat[14] ^ nllli0l))) & (~ (comp_pat[15] ^ nllli0O))) & (~ (comp_pat[16] ^ nllliii))) & (~ (comp_pat[17] ^ nllliil))) & (~ (comp_pat[18] ^ nllliiO))) & (~ (comp_pat[19] ^ nlllili))),
		n10llli = ((((((((((~ ((~ comp_pat[10]) ^ nllli1i)) & (~ ((~ comp_pat[11]) ^ nllli1l))) & (~ ((~ comp_pat[12]) ^ nllli1O))) & (~ ((~ comp_pat[13]) ^ nllli0i))) & (~ ((~ comp_pat[14]) ^ nllli0l))) & (~ ((~ comp_pat[15]) ^ nllli0O))) & (~ ((~ comp_pat[16]) ^ nllliii))) & (~ ((~ comp_pat[17]) ^ nllliil))) & (~ ((~ comp_pat[18]) ^ nllliiO))) & (~ ((~ comp_pat[19]) ^ nlllili))),
		n10llll = (n10OilO & ((comp_pat_porn & n10llOi) | n10lllO)),
		n10lllO = ((((((((((~ (comp_pat[10] ^ nlll0OO)) & (~ (comp_pat[11] ^ nllli1i))) & (~ (comp_pat[12] ^ nllli1l))) & (~ (comp_pat[13] ^ nllli1O))) & (~ (comp_pat[14] ^ nllli0i))) & (~ (comp_pat[15] ^ nllli0l))) & (~ (comp_pat[16] ^ nllli0O))) & (~ (comp_pat[17] ^ nllliii))) & (~ (comp_pat[18] ^ nllliil))) & (~ (comp_pat[19] ^ nllliiO))),
		n10llOi = ((((((((((~ ((~ comp_pat[10]) ^ nlll0OO)) & (~ ((~ comp_pat[11]) ^ nllli1i))) & (~ ((~ comp_pat[12]) ^ nllli1l))) & (~ ((~ comp_pat[13]) ^ nllli1O))) & (~ ((~ comp_pat[14]) ^ nllli0i))) & (~ ((~ comp_pat[15]) ^ nllli0l))) & (~ ((~ comp_pat[16]) ^ nllli0O))) & (~ ((~ comp_pat[17]) ^ nllliii))) & (~ ((~ comp_pat[18]) ^ nllliil))) & (~ ((~ comp_pat[19]) ^ nllliiO))),
		n10llOl = (((((((((((((((((((n10OilO | n10OiiO) | n10Oi0O) | n10Oi1O) | n10O0OO) | n10O0lO) | n10O0iO) | n10O00O) | n10O01O) | n10O1OO) | n10O1lO) | n10O1iO) | n10O10O) | n10O11O) | n10lOOO) | n10lOlO) | n10lOiO) | n10lO0O) | n10lO1O) | n10llOO),
		n10llOO = ((comp_pat_porn & n10lO1l) | n10lO1i),
		n10lO0i = ((((((((((~ (comp_pat[0] ^ nllliil)) & (~ (comp_pat[1] ^ nllliiO))) & (~ (comp_pat[2] ^ nlllili))) & (~ (comp_pat[3] ^ nlllill))) & (~ (comp_pat[4] ^ nlllilO))) & (~ (comp_pat[5] ^ nllliOi))) & (~ (comp_pat[6] ^ nllliOl))) & (~ (comp_pat[7] ^ nllliOO))) & (~ (comp_pat[8] ^ nllll1i))) & (~ (comp_pat[9] ^ nllll1l))),
		n10lO0l = ((((((((((~ ((~ comp_pat[0]) ^ nllliil)) & (~ ((~ comp_pat[1]) ^ nllliiO))) & (~ ((~ comp_pat[2]) ^ nlllili))) & (~ ((~ comp_pat[3]) ^ nlllill))) & (~ ((~ comp_pat[4]) ^ nlllilO))) & (~ ((~ comp_pat[5]) ^ nllliOi))) & (~ ((~ comp_pat[6]) ^ nllliOl))) & (~ ((~ comp_pat[7]) ^ nllliOO))) & (~ ((~ comp_pat[8]) ^ nllll1i))) & (~ ((~ comp_pat[9]) ^ nllll1l))),
		n10lO0O = ((comp_pat_porn & n10lOil) | n10lOii),
		n10lO1i = ((((((((((~ (comp_pat[0] ^ nllliiO)) & (~ (comp_pat[1] ^ nlllili))) & (~ (comp_pat[2] ^ nlllill))) & (~ (comp_pat[3] ^ nlllilO))) & (~ (comp_pat[4] ^ nllliOi))) & (~ (comp_pat[5] ^ nllliOl))) & (~ (comp_pat[6] ^ nllliOO))) & (~ (comp_pat[7] ^ nllll1i))) & (~ (comp_pat[8] ^ nllll1l))) & (~ (comp_pat[9] ^ nllll1O))),
		n10lO1l = ((((((((((~ ((~ comp_pat[0]) ^ nllliiO)) & (~ ((~ comp_pat[1]) ^ nlllili))) & (~ ((~ comp_pat[2]) ^ nlllill))) & (~ ((~ comp_pat[3]) ^ nlllilO))) & (~ ((~ comp_pat[4]) ^ nllliOi))) & (~ ((~ comp_pat[5]) ^ nllliOl))) & (~ ((~ comp_pat[6]) ^ nllliOO))) & (~ ((~ comp_pat[7]) ^ nllll1i))) & (~ ((~ comp_pat[8]) ^ nllll1l))) & (~ ((~ comp_pat[9]) ^ nllll1O))),
		n10lO1O = ((comp_pat_porn & n10lO0l) | n10lO0i),
		n10lOii = ((((((((((~ (comp_pat[0] ^ nllliii)) & (~ (comp_pat[1] ^ nllliil))) & (~ (comp_pat[2] ^ nllliiO))) & (~ (comp_pat[3] ^ nlllili))) & (~ (comp_pat[4] ^ nlllill))) & (~ (comp_pat[5] ^ nlllilO))) & (~ (comp_pat[6] ^ nllliOi))) & (~ (comp_pat[7] ^ nllliOl))) & (~ (comp_pat[8] ^ nllliOO))) & (~ (comp_pat[9] ^ nllll1i))),
		n10lOil = ((((((((((~ ((~ comp_pat[0]) ^ nllliii)) & (~ ((~ comp_pat[1]) ^ nllliil))) & (~ ((~ comp_pat[2]) ^ nllliiO))) & (~ ((~ comp_pat[3]) ^ nlllili))) & (~ ((~ comp_pat[4]) ^ nlllill))) & (~ ((~ comp_pat[5]) ^ nlllilO))) & (~ ((~ comp_pat[6]) ^ nllliOi))) & (~ ((~ comp_pat[7]) ^ nllliOl))) & (~ ((~ comp_pat[8]) ^ nllliOO))) & (~ ((~ comp_pat[9]) ^ nllll1i))),
		n10lOiO = ((comp_pat_porn & n10lOll) | n10lOli),
		n10lOli = ((((((((((~ (comp_pat[0] ^ nllli0O)) & (~ (comp_pat[1] ^ nllliii))) & (~ (comp_pat[2] ^ nllliil))) & (~ (comp_pat[3] ^ nllliiO))) & (~ (comp_pat[4] ^ nlllili))) & (~ (comp_pat[5] ^ nlllill))) & (~ (comp_pat[6] ^ nlllilO))) & (~ (comp_pat[7] ^ nllliOi))) & (~ (comp_pat[8] ^ nllliOl))) & (~ (comp_pat[9] ^ nllliOO))),
		n10lOll = ((((((((((~ ((~ comp_pat[0]) ^ nllli0O)) & (~ ((~ comp_pat[1]) ^ nllliii))) & (~ ((~ comp_pat[2]) ^ nllliil))) & (~ ((~ comp_pat[3]) ^ nllliiO))) & (~ ((~ comp_pat[4]) ^ nlllili))) & (~ ((~ comp_pat[5]) ^ nlllill))) & (~ ((~ comp_pat[6]) ^ nlllilO))) & (~ ((~ comp_pat[7]) ^ nllliOi))) & (~ ((~ comp_pat[8]) ^ nllliOl))) & (~ ((~ comp_pat[9]) ^ nllliOO))),
		n10lOlO = ((comp_pat_porn & n10lOOl) | n10lOOi),
		n10lOOi = ((((((((((~ (comp_pat[0] ^ nllli0l)) & (~ (comp_pat[1] ^ nllli0O))) & (~ (comp_pat[2] ^ nllliii))) & (~ (comp_pat[3] ^ nllliil))) & (~ (comp_pat[4] ^ nllliiO))) & (~ (comp_pat[5] ^ nlllili))) & (~ (comp_pat[6] ^ nlllill))) & (~ (comp_pat[7] ^ nlllilO))) & (~ (comp_pat[8] ^ nllliOi))) & (~ (comp_pat[9] ^ nllliOl))),
		n10lOOl = ((((((((((~ ((~ comp_pat[0]) ^ nllli0l)) & (~ ((~ comp_pat[1]) ^ nllli0O))) & (~ ((~ comp_pat[2]) ^ nllliii))) & (~ ((~ comp_pat[3]) ^ nllliil))) & (~ ((~ comp_pat[4]) ^ nllliiO))) & (~ ((~ comp_pat[5]) ^ nlllili))) & (~ ((~ comp_pat[6]) ^ nlllill))) & (~ ((~ comp_pat[7]) ^ nlllilO))) & (~ ((~ comp_pat[8]) ^ nllliOi))) & (~ ((~ comp_pat[9]) ^ nllliOl))),
		n10lOOO = ((comp_pat_porn & n10O11l) | n10O11i),
		n10O00i = ((((((((((~ (comp_pat[0] ^ nlll0Oi)) & (~ (comp_pat[1] ^ nlll0Ol))) & (~ (comp_pat[2] ^ nlll0OO))) & (~ (comp_pat[3] ^ nllli1i))) & (~ (comp_pat[4] ^ nllli1l))) & (~ (comp_pat[5] ^ nllli1O))) & (~ (comp_pat[6] ^ nllli0i))) & (~ (comp_pat[7] ^ nllli0l))) & (~ (comp_pat[8] ^ nllli0O))) & (~ (comp_pat[9] ^ nllliii))),
		n10O00l = ((((((((((~ ((~ comp_pat[0]) ^ nlll0Oi)) & (~ ((~ comp_pat[1]) ^ nlll0Ol))) & (~ ((~ comp_pat[2]) ^ nlll0OO))) & (~ ((~ comp_pat[3]) ^ nllli1i))) & (~ ((~ comp_pat[4]) ^ nllli1l))) & (~ ((~ comp_pat[5]) ^ nllli1O))) & (~ ((~ comp_pat[6]) ^ nllli0i))) & (~ ((~ comp_pat[7]) ^ nllli0l))) & (~ ((~ comp_pat[8]) ^ nllli0O))) & (~ ((~ comp_pat[9]) ^ nllliii))),
		n10O00O = ((comp_pat_porn & n10O0il) | n10O0ii),
		n10O01i = ((((((((((~ (comp_pat[0] ^ nlll0Ol)) & (~ (comp_pat[1] ^ nlll0OO))) & (~ (comp_pat[2] ^ nllli1i))) & (~ (comp_pat[3] ^ nllli1l))) & (~ (comp_pat[4] ^ nllli1O))) & (~ (comp_pat[5] ^ nllli0i))) & (~ (comp_pat[6] ^ nllli0l))) & (~ (comp_pat[7] ^ nllli0O))) & (~ (comp_pat[8] ^ nllliii))) & (~ (comp_pat[9] ^ nllliil))),
		n10O01l = ((((((((((~ ((~ comp_pat[0]) ^ nlll0Ol)) & (~ ((~ comp_pat[1]) ^ nlll0OO))) & (~ ((~ comp_pat[2]) ^ nllli1i))) & (~ ((~ comp_pat[3]) ^ nllli1l))) & (~ ((~ comp_pat[4]) ^ nllli1O))) & (~ ((~ comp_pat[5]) ^ nllli0i))) & (~ ((~ comp_pat[6]) ^ nllli0l))) & (~ ((~ comp_pat[7]) ^ nllli0O))) & (~ ((~ comp_pat[8]) ^ nllliii))) & (~ ((~ comp_pat[9]) ^ nllliil))),
		n10O01O = ((comp_pat_porn & n10O00l) | n10O00i),
		n10O0ii = ((((((((((~ (comp_pat[0] ^ nlll0lO)) & (~ (comp_pat[1] ^ nlll0Oi))) & (~ (comp_pat[2] ^ nlll0Ol))) & (~ (comp_pat[3] ^ nlll0OO))) & (~ (comp_pat[4] ^ nllli1i))) & (~ (comp_pat[5] ^ nllli1l))) & (~ (comp_pat[6] ^ nllli1O))) & (~ (comp_pat[7] ^ nllli0i))) & (~ (comp_pat[8] ^ nllli0l))) & (~ (comp_pat[9] ^ nllli0O))),
		n10O0il = ((((((((((~ ((~ comp_pat[0]) ^ nlll0lO)) & (~ ((~ comp_pat[1]) ^ nlll0Oi))) & (~ ((~ comp_pat[2]) ^ nlll0Ol))) & (~ ((~ comp_pat[3]) ^ nlll0OO))) & (~ ((~ comp_pat[4]) ^ nllli1i))) & (~ ((~ comp_pat[5]) ^ nllli1l))) & (~ ((~ comp_pat[6]) ^ nllli1O))) & (~ ((~ comp_pat[7]) ^ nllli0i))) & (~ ((~ comp_pat[8]) ^ nllli0l))) & (~ ((~ comp_pat[9]) ^ nllli0O))),
		n10O0iO = ((comp_pat_porn & n10O0ll) | n10O0li),
		n10O0li = ((((((((((~ (comp_pat[0] ^ nlll0ll)) & (~ (comp_pat[1] ^ nlll0lO))) & (~ (comp_pat[2] ^ nlll0Oi))) & (~ (comp_pat[3] ^ nlll0Ol))) & (~ (comp_pat[4] ^ nlll0OO))) & (~ (comp_pat[5] ^ nllli1i))) & (~ (comp_pat[6] ^ nllli1l))) & (~ (comp_pat[7] ^ nllli1O))) & (~ (comp_pat[8] ^ nllli0i))) & (~ (comp_pat[9] ^ nllli0l))),
		n10O0ll = ((((((((((~ ((~ comp_pat[0]) ^ nlll0ll)) & (~ ((~ comp_pat[1]) ^ nlll0lO))) & (~ ((~ comp_pat[2]) ^ nlll0Oi))) & (~ ((~ comp_pat[3]) ^ nlll0Ol))) & (~ ((~ comp_pat[4]) ^ nlll0OO))) & (~ ((~ comp_pat[5]) ^ nllli1i))) & (~ ((~ comp_pat[6]) ^ nllli1l))) & (~ ((~ comp_pat[7]) ^ nllli1O))) & (~ ((~ comp_pat[8]) ^ nllli0i))) & (~ ((~ comp_pat[9]) ^ nllli0l))),
		n10O0lO = ((comp_pat_porn & n10O0Ol) | n10O0Oi),
		n10O0Oi = ((((((((((~ (comp_pat[0] ^ nlll0li)) & (~ (comp_pat[1] ^ nlll0ll))) & (~ (comp_pat[2] ^ nlll0lO))) & (~ (comp_pat[3] ^ nlll0Oi))) & (~ (comp_pat[4] ^ nlll0Ol))) & (~ (comp_pat[5] ^ nlll0OO))) & (~ (comp_pat[6] ^ nllli1i))) & (~ (comp_pat[7] ^ nllli1l))) & (~ (comp_pat[8] ^ nllli1O))) & (~ (comp_pat[9] ^ nllli0i))),
		n10O0Ol = ((((((((((~ ((~ comp_pat[0]) ^ nlll0li)) & (~ ((~ comp_pat[1]) ^ nlll0ll))) & (~ ((~ comp_pat[2]) ^ nlll0lO))) & (~ ((~ comp_pat[3]) ^ nlll0Oi))) & (~ ((~ comp_pat[4]) ^ nlll0Ol))) & (~ ((~ comp_pat[5]) ^ nlll0OO))) & (~ ((~ comp_pat[6]) ^ nllli1i))) & (~ ((~ comp_pat[7]) ^ nllli1l))) & (~ ((~ comp_pat[8]) ^ nllli1O))) & (~ ((~ comp_pat[9]) ^ nllli0i))),
		n10O0OO = ((comp_pat_porn & n10Oi1l) | n10Oi1i),
		n10O10i = ((((((((((~ (comp_pat[0] ^ nllli1O)) & (~ (comp_pat[1] ^ nllli0i))) & (~ (comp_pat[2] ^ nllli0l))) & (~ (comp_pat[3] ^ nllli0O))) & (~ (comp_pat[4] ^ nllliii))) & (~ (comp_pat[5] ^ nllliil))) & (~ (comp_pat[6] ^ nllliiO))) & (~ (comp_pat[7] ^ nlllili))) & (~ (comp_pat[8] ^ nlllill))) & (~ (comp_pat[9] ^ nlllilO))),
		n10O10l = ((((((((((~ ((~ comp_pat[0]) ^ nllli1O)) & (~ ((~ comp_pat[1]) ^ nllli0i))) & (~ ((~ comp_pat[2]) ^ nllli0l))) & (~ ((~ comp_pat[3]) ^ nllli0O))) & (~ ((~ comp_pat[4]) ^ nllliii))) & (~ ((~ comp_pat[5]) ^ nllliil))) & (~ ((~ comp_pat[6]) ^ nllliiO))) & (~ ((~ comp_pat[7]) ^ nlllili))) & (~ ((~ comp_pat[8]) ^ nlllill))) & (~ ((~ comp_pat[9]) ^ nlllilO))),
		n10O10O = ((comp_pat_porn & n10O1il) | n10O1ii),
		n10O11i = ((((((((((~ (comp_pat[0] ^ nllli0i)) & (~ (comp_pat[1] ^ nllli0l))) & (~ (comp_pat[2] ^ nllli0O))) & (~ (comp_pat[3] ^ nllliii))) & (~ (comp_pat[4] ^ nllliil))) & (~ (comp_pat[5] ^ nllliiO))) & (~ (comp_pat[6] ^ nlllili))) & (~ (comp_pat[7] ^ nlllill))) & (~ (comp_pat[8] ^ nlllilO))) & (~ (comp_pat[9] ^ nllliOi))),
		n10O11l = ((((((((((~ ((~ comp_pat[0]) ^ nllli0i)) & (~ ((~ comp_pat[1]) ^ nllli0l))) & (~ ((~ comp_pat[2]) ^ nllli0O))) & (~ ((~ comp_pat[3]) ^ nllliii))) & (~ ((~ comp_pat[4]) ^ nllliil))) & (~ ((~ comp_pat[5]) ^ nllliiO))) & (~ ((~ comp_pat[6]) ^ nlllili))) & (~ ((~ comp_pat[7]) ^ nlllill))) & (~ ((~ comp_pat[8]) ^ nlllilO))) & (~ ((~ comp_pat[9]) ^ nllliOi))),
		n10O11O = ((comp_pat_porn & n10O10l) | n10O10i),
		n10O1ii = ((((((((((~ (comp_pat[0] ^ nllli1l)) & (~ (comp_pat[1] ^ nllli1O))) & (~ (comp_pat[2] ^ nllli0i))) & (~ (comp_pat[3] ^ nllli0l))) & (~ (comp_pat[4] ^ nllli0O))) & (~ (comp_pat[5] ^ nllliii))) & (~ (comp_pat[6] ^ nllliil))) & (~ (comp_pat[7] ^ nllliiO))) & (~ (comp_pat[8] ^ nlllili))) & (~ (comp_pat[9] ^ nlllill))),
		n10O1il = ((((((((((~ ((~ comp_pat[0]) ^ nllli1l)) & (~ ((~ comp_pat[1]) ^ nllli1O))) & (~ ((~ comp_pat[2]) ^ nllli0i))) & (~ ((~ comp_pat[3]) ^ nllli0l))) & (~ ((~ comp_pat[4]) ^ nllli0O))) & (~ ((~ comp_pat[5]) ^ nllliii))) & (~ ((~ comp_pat[6]) ^ nllliil))) & (~ ((~ comp_pat[7]) ^ nllliiO))) & (~ ((~ comp_pat[8]) ^ nlllili))) & (~ ((~ comp_pat[9]) ^ nlllill))),
		n10O1iO = ((comp_pat_porn & n10O1ll) | n10O1li),
		n10O1li = ((((((((((~ (comp_pat[0] ^ nllli1i)) & (~ (comp_pat[1] ^ nllli1l))) & (~ (comp_pat[2] ^ nllli1O))) & (~ (comp_pat[3] ^ nllli0i))) & (~ (comp_pat[4] ^ nllli0l))) & (~ (comp_pat[5] ^ nllli0O))) & (~ (comp_pat[6] ^ nllliii))) & (~ (comp_pat[7] ^ nllliil))) & (~ (comp_pat[8] ^ nllliiO))) & (~ (comp_pat[9] ^ nlllili))),
		n10O1ll = ((((((((((~ ((~ comp_pat[0]) ^ nllli1i)) & (~ ((~ comp_pat[1]) ^ nllli1l))) & (~ ((~ comp_pat[2]) ^ nllli1O))) & (~ ((~ comp_pat[3]) ^ nllli0i))) & (~ ((~ comp_pat[4]) ^ nllli0l))) & (~ ((~ comp_pat[5]) ^ nllli0O))) & (~ ((~ comp_pat[6]) ^ nllliii))) & (~ ((~ comp_pat[7]) ^ nllliil))) & (~ ((~ comp_pat[8]) ^ nllliiO))) & (~ ((~ comp_pat[9]) ^ nlllili))),
		n10O1lO = ((comp_pat_porn & n10O1Ol) | n10O1Oi),
		n10O1Oi = ((((((((((~ (comp_pat[0] ^ nlll0OO)) & (~ (comp_pat[1] ^ nllli1i))) & (~ (comp_pat[2] ^ nllli1l))) & (~ (comp_pat[3] ^ nllli1O))) & (~ (comp_pat[4] ^ nllli0i))) & (~ (comp_pat[5] ^ nllli0l))) & (~ (comp_pat[6] ^ nllli0O))) & (~ (comp_pat[7] ^ nllliii))) & (~ (comp_pat[8] ^ nllliil))) & (~ (comp_pat[9] ^ nllliiO))),
		n10O1Ol = ((((((((((~ ((~ comp_pat[0]) ^ nlll0OO)) & (~ ((~ comp_pat[1]) ^ nllli1i))) & (~ ((~ comp_pat[2]) ^ nllli1l))) & (~ ((~ comp_pat[3]) ^ nllli1O))) & (~ ((~ comp_pat[4]) ^ nllli0i))) & (~ ((~ comp_pat[5]) ^ nllli0l))) & (~ ((~ comp_pat[6]) ^ nllli0O))) & (~ ((~ comp_pat[7]) ^ nllliii))) & (~ ((~ comp_pat[8]) ^ nllliil))) & (~ ((~ comp_pat[9]) ^ nllliiO))),
		n10O1OO = ((comp_pat_porn & n10O01l) | n10O01i),
		n10Oi0i = ((((((((((~ (comp_pat[0] ^ nlll0il)) & (~ (comp_pat[1] ^ nlll0iO))) & (~ (comp_pat[2] ^ nlll0li))) & (~ (comp_pat[3] ^ nlll0ll))) & (~ (comp_pat[4] ^ nlll0lO))) & (~ (comp_pat[5] ^ nlll0Oi))) & (~ (comp_pat[6] ^ nlll0Ol))) & (~ (comp_pat[7] ^ nlll0OO))) & (~ (comp_pat[8] ^ nllli1i))) & (~ (comp_pat[9] ^ nllli1l))),
		n10Oi0l = ((((((((((~ ((~ comp_pat[0]) ^ nlll0il)) & (~ ((~ comp_pat[1]) ^ nlll0iO))) & (~ ((~ comp_pat[2]) ^ nlll0li))) & (~ ((~ comp_pat[3]) ^ nlll0ll))) & (~ ((~ comp_pat[4]) ^ nlll0lO))) & (~ ((~ comp_pat[5]) ^ nlll0Oi))) & (~ ((~ comp_pat[6]) ^ nlll0Ol))) & (~ ((~ comp_pat[7]) ^ nlll0OO))) & (~ ((~ comp_pat[8]) ^ nllli1i))) & (~ ((~ comp_pat[9]) ^ nllli1l))),
		n10Oi0O = ((comp_pat_porn & n10Oiil) | n10Oiii),
		n10Oi1i = ((((((((((~ (comp_pat[0] ^ nlll0iO)) & (~ (comp_pat[1] ^ nlll0li))) & (~ (comp_pat[2] ^ nlll0ll))) & (~ (comp_pat[3] ^ nlll0lO))) & (~ (comp_pat[4] ^ nlll0Oi))) & (~ (comp_pat[5] ^ nlll0Ol))) & (~ (comp_pat[6] ^ nlll0OO))) & (~ (comp_pat[7] ^ nllli1i))) & (~ (comp_pat[8] ^ nllli1l))) & (~ (comp_pat[9] ^ nllli1O))),
		n10Oi1l = ((((((((((~ ((~ comp_pat[0]) ^ nlll0iO)) & (~ ((~ comp_pat[1]) ^ nlll0li))) & (~ ((~ comp_pat[2]) ^ nlll0ll))) & (~ ((~ comp_pat[3]) ^ nlll0lO))) & (~ ((~ comp_pat[4]) ^ nlll0Oi))) & (~ ((~ comp_pat[5]) ^ nlll0Ol))) & (~ ((~ comp_pat[6]) ^ nlll0OO))) & (~ ((~ comp_pat[7]) ^ nllli1i))) & (~ ((~ comp_pat[8]) ^ nllli1l))) & (~ ((~ comp_pat[9]) ^ nllli1O))),
		n10Oi1O = ((comp_pat_porn & n10Oi0l) | n10Oi0i),
		n10Oiii = ((((((((((~ (comp_pat[0] ^ nlll0ii)) & (~ (comp_pat[1] ^ nlll0il))) & (~ (comp_pat[2] ^ nlll0iO))) & (~ (comp_pat[3] ^ nlll0li))) & (~ (comp_pat[4] ^ nlll0ll))) & (~ (comp_pat[5] ^ nlll0lO))) & (~ (comp_pat[6] ^ nlll0Oi))) & (~ (comp_pat[7] ^ nlll0Ol))) & (~ (comp_pat[8] ^ nlll0OO))) & (~ (comp_pat[9] ^ nllli1i))),
		n10Oiil = ((((((((((~ ((~ comp_pat[0]) ^ nlll0ii)) & (~ ((~ comp_pat[1]) ^ nlll0il))) & (~ ((~ comp_pat[2]) ^ nlll0iO))) & (~ ((~ comp_pat[3]) ^ nlll0li))) & (~ ((~ comp_pat[4]) ^ nlll0ll))) & (~ ((~ comp_pat[5]) ^ nlll0lO))) & (~ ((~ comp_pat[6]) ^ nlll0Oi))) & (~ ((~ comp_pat[7]) ^ nlll0Ol))) & (~ ((~ comp_pat[8]) ^ nlll0OO))) & (~ ((~ comp_pat[9]) ^ nllli1i))),
		n10OiiO = ((comp_pat_porn & n10Oill) | n10Oili),
		n10Oili = ((((((((((~ (comp_pat[0] ^ nlll00O)) & (~ (comp_pat[1] ^ nlll0ii))) & (~ (comp_pat[2] ^ nlll0il))) & (~ (comp_pat[3] ^ nlll0iO))) & (~ (comp_pat[4] ^ nlll0li))) & (~ (comp_pat[5] ^ nlll0ll))) & (~ (comp_pat[6] ^ nlll0lO))) & (~ (comp_pat[7] ^ nlll0Oi))) & (~ (comp_pat[8] ^ nlll0Ol))) & (~ (comp_pat[9] ^ nlll0OO))),
		n10Oill = ((((((((((~ ((~ comp_pat[0]) ^ nlll00O)) & (~ ((~ comp_pat[1]) ^ nlll0ii))) & (~ ((~ comp_pat[2]) ^ nlll0il))) & (~ ((~ comp_pat[3]) ^ nlll0iO))) & (~ ((~ comp_pat[4]) ^ nlll0li))) & (~ ((~ comp_pat[5]) ^ nlll0ll))) & (~ ((~ comp_pat[6]) ^ nlll0lO))) & (~ ((~ comp_pat[7]) ^ nlll0Oi))) & (~ ((~ comp_pat[8]) ^ nlll0Ol))) & (~ ((~ comp_pat[9]) ^ nlll0OO))),
		n10OilO = ((comp_pat_porn & n10OiOl) | n10OiOi),
		n10OiOi = ((((((((((~ (comp_pat[0] ^ nlll00l)) & (~ (comp_pat[1] ^ nlll00O))) & (~ (comp_pat[2] ^ nlll0ii))) & (~ (comp_pat[3] ^ nlll0il))) & (~ (comp_pat[4] ^ nlll0iO))) & (~ (comp_pat[5] ^ nlll0li))) & (~ (comp_pat[6] ^ nlll0ll))) & (~ (comp_pat[7] ^ nlll0lO))) & (~ (comp_pat[8] ^ nlll0Oi))) & (~ (comp_pat[9] ^ nlll0Ol))),
		n10OiOl = ((((((((((~ ((~ comp_pat[0]) ^ nlll00l)) & (~ ((~ comp_pat[1]) ^ nlll00O))) & (~ ((~ comp_pat[2]) ^ nlll0ii))) & (~ ((~ comp_pat[3]) ^ nlll0il))) & (~ ((~ comp_pat[4]) ^ nlll0iO))) & (~ ((~ comp_pat[5]) ^ nlll0li))) & (~ ((~ comp_pat[6]) ^ nlll0ll))) & (~ ((~ comp_pat[7]) ^ nlll0lO))) & (~ ((~ comp_pat[8]) ^ nlll0Oi))) & (~ ((~ comp_pat[9]) ^ nlll0Ol))),
		n10OiOO = (((((((((((((((((((n1i10Oi | n1i10li) | n1i10ii) | n1i100i) | n1i101i) | n1i11Oi) | n1i11li) | n1i11ii) | n1i110i) | n1i111i) | n10OOOi) | n10OOli) | n10OOii) | n10OO0i) | n10OO1i) | n10OlOi) | n10Olli) | n10Olii) | n10Ol0i) | n10Ol1i),
		n10Ol0i = ((comp_pat_porn & n10Ol0O) | n10Ol0l),
		n10Ol0l = (((((((~ (comp_pat[0] ^ nllliil)) & (~ (comp_pat[1] ^ nllliiO))) & (~ (comp_pat[2] ^ nlllili))) & (~ (comp_pat[3] ^ nlllill))) & (~ (comp_pat[4] ^ nlllilO))) & (~ (comp_pat[5] ^ nllliOi))) & (~ (comp_pat[6] ^ nllliOl))),
		n10Ol0O = (((((((~ ((~ comp_pat[0]) ^ nllliil)) & (~ ((~ comp_pat[1]) ^ nllliiO))) & (~ ((~ comp_pat[2]) ^ nlllili))) & (~ ((~ comp_pat[3]) ^ nlllill))) & (~ ((~ comp_pat[4]) ^ nlllilO))) & (~ ((~ comp_pat[5]) ^ nllliOi))) & (~ ((~ comp_pat[6]) ^ nllliOl))),
		n10Ol1i = ((comp_pat_porn & n10Ol1O) | n10Ol1l),
		n10Ol1l = (((((((~ (comp_pat[0] ^ nllliiO)) & (~ (comp_pat[1] ^ nlllili))) & (~ (comp_pat[2] ^ nlllill))) & (~ (comp_pat[3] ^ nlllilO))) & (~ (comp_pat[4] ^ nllliOi))) & (~ (comp_pat[5] ^ nllliOl))) & (~ (comp_pat[6] ^ nllliOO))),
		n10Ol1O = (((((((~ ((~ comp_pat[0]) ^ nllliiO)) & (~ ((~ comp_pat[1]) ^ nlllili))) & (~ ((~ comp_pat[2]) ^ nlllill))) & (~ ((~ comp_pat[3]) ^ nlllilO))) & (~ ((~ comp_pat[4]) ^ nllliOi))) & (~ ((~ comp_pat[5]) ^ nllliOl))) & (~ ((~ comp_pat[6]) ^ nllliOO))),
		n10Olii = ((comp_pat_porn & n10OliO) | n10Olil),
		n10Olil = (((((((~ (comp_pat[0] ^ nllliii)) & (~ (comp_pat[1] ^ nllliil))) & (~ (comp_pat[2] ^ nllliiO))) & (~ (comp_pat[3] ^ nlllili))) & (~ (comp_pat[4] ^ nlllill))) & (~ (comp_pat[5] ^ nlllilO))) & (~ (comp_pat[6] ^ nllliOi))),
		n10OliO = (((((((~ ((~ comp_pat[0]) ^ nllliii)) & (~ ((~ comp_pat[1]) ^ nllliil))) & (~ ((~ comp_pat[2]) ^ nllliiO))) & (~ ((~ comp_pat[3]) ^ nlllili))) & (~ ((~ comp_pat[4]) ^ nlllill))) & (~ ((~ comp_pat[5]) ^ nlllilO))) & (~ ((~ comp_pat[6]) ^ nllliOi))),
		n10Olli = ((comp_pat_porn & n10OllO) | n10Olll),
		n10Olll = (((((((~ (comp_pat[0] ^ nllli0O)) & (~ (comp_pat[1] ^ nllliii))) & (~ (comp_pat[2] ^ nllliil))) & (~ (comp_pat[3] ^ nllliiO))) & (~ (comp_pat[4] ^ nlllili))) & (~ (comp_pat[5] ^ nlllill))) & (~ (comp_pat[6] ^ nlllilO))),
		n10OllO = (((((((~ ((~ comp_pat[0]) ^ nllli0O)) & (~ ((~ comp_pat[1]) ^ nllliii))) & (~ ((~ comp_pat[2]) ^ nllliil))) & (~ ((~ comp_pat[3]) ^ nllliiO))) & (~ ((~ comp_pat[4]) ^ nlllili))) & (~ ((~ comp_pat[5]) ^ nlllill))) & (~ ((~ comp_pat[6]) ^ nlllilO))),
		n10OlOi = ((comp_pat_porn & n10OlOO) | n10OlOl),
		n10OlOl = (((((((~ (comp_pat[0] ^ nllli0l)) & (~ (comp_pat[1] ^ nllli0O))) & (~ (comp_pat[2] ^ nllliii))) & (~ (comp_pat[3] ^ nllliil))) & (~ (comp_pat[4] ^ nllliiO))) & (~ (comp_pat[5] ^ nlllili))) & (~ (comp_pat[6] ^ nlllill))),
		n10OlOO = (((((((~ ((~ comp_pat[0]) ^ nllli0l)) & (~ ((~ comp_pat[1]) ^ nllli0O))) & (~ ((~ comp_pat[2]) ^ nllliii))) & (~ ((~ comp_pat[3]) ^ nllliil))) & (~ ((~ comp_pat[4]) ^ nllliiO))) & (~ ((~ comp_pat[5]) ^ nlllili))) & (~ ((~ comp_pat[6]) ^ nlllill))),
		n10OO0i = ((comp_pat_porn & n10OO0O) | n10OO0l),
		n10OO0l = (((((((~ (comp_pat[0] ^ nllli1O)) & (~ (comp_pat[1] ^ nllli0i))) & (~ (comp_pat[2] ^ nllli0l))) & (~ (comp_pat[3] ^ nllli0O))) & (~ (comp_pat[4] ^ nllliii))) & (~ (comp_pat[5] ^ nllliil))) & (~ (comp_pat[6] ^ nllliiO))),
		n10OO0O = (((((((~ ((~ comp_pat[0]) ^ nllli1O)) & (~ ((~ comp_pat[1]) ^ nllli0i))) & (~ ((~ comp_pat[2]) ^ nllli0l))) & (~ ((~ comp_pat[3]) ^ nllli0O))) & (~ ((~ comp_pat[4]) ^ nllliii))) & (~ ((~ comp_pat[5]) ^ nllliil))) & (~ ((~ comp_pat[6]) ^ nllliiO))),
		n10OO1i = ((comp_pat_porn & n10OO1O) | n10OO1l),
		n10OO1l = (((((((~ (comp_pat[0] ^ nllli0i)) & (~ (comp_pat[1] ^ nllli0l))) & (~ (comp_pat[2] ^ nllli0O))) & (~ (comp_pat[3] ^ nllliii))) & (~ (comp_pat[4] ^ nllliil))) & (~ (comp_pat[5] ^ nllliiO))) & (~ (comp_pat[6] ^ nlllili))),
		n10OO1O = (((((((~ ((~ comp_pat[0]) ^ nllli0i)) & (~ ((~ comp_pat[1]) ^ nllli0l))) & (~ ((~ comp_pat[2]) ^ nllli0O))) & (~ ((~ comp_pat[3]) ^ nllliii))) & (~ ((~ comp_pat[4]) ^ nllliil))) & (~ ((~ comp_pat[5]) ^ nllliiO))) & (~ ((~ comp_pat[6]) ^ nlllili))),
		n10OOii = ((comp_pat_porn & n10OOiO) | n10OOil),
		n10OOil = (((((((~ (comp_pat[0] ^ nllli1l)) & (~ (comp_pat[1] ^ nllli1O))) & (~ (comp_pat[2] ^ nllli0i))) & (~ (comp_pat[3] ^ nllli0l))) & (~ (comp_pat[4] ^ nllli0O))) & (~ (comp_pat[5] ^ nllliii))) & (~ (comp_pat[6] ^ nllliil))),
		n10OOiO = (((((((~ ((~ comp_pat[0]) ^ nllli1l)) & (~ ((~ comp_pat[1]) ^ nllli1O))) & (~ ((~ comp_pat[2]) ^ nllli0i))) & (~ ((~ comp_pat[3]) ^ nllli0l))) & (~ ((~ comp_pat[4]) ^ nllli0O))) & (~ ((~ comp_pat[5]) ^ nllliii))) & (~ ((~ comp_pat[6]) ^ nllliil))),
		n10OOli = ((comp_pat_porn & n10OOlO) | n10OOll),
		n10OOll = (((((((~ (comp_pat[0] ^ nllli1i)) & (~ (comp_pat[1] ^ nllli1l))) & (~ (comp_pat[2] ^ nllli1O))) & (~ (comp_pat[3] ^ nllli0i))) & (~ (comp_pat[4] ^ nllli0l))) & (~ (comp_pat[5] ^ nllli0O))) & (~ (comp_pat[6] ^ nllliii))),
		n10OOlO = (((((((~ ((~ comp_pat[0]) ^ nllli1i)) & (~ ((~ comp_pat[1]) ^ nllli1l))) & (~ ((~ comp_pat[2]) ^ nllli1O))) & (~ ((~ comp_pat[3]) ^ nllli0i))) & (~ ((~ comp_pat[4]) ^ nllli0l))) & (~ ((~ comp_pat[5]) ^ nllli0O))) & (~ ((~ comp_pat[6]) ^ nllliii))),
		n10OOOi = ((comp_pat_porn & n10OOOO) | n10OOOl),
		n10OOOl = (((((((~ (comp_pat[0] ^ nlll0OO)) & (~ (comp_pat[1] ^ nllli1i))) & (~ (comp_pat[2] ^ nllli1l))) & (~ (comp_pat[3] ^ nllli1O))) & (~ (comp_pat[4] ^ nllli0i))) & (~ (comp_pat[5] ^ nllli0l))) & (~ (comp_pat[6] ^ nllli0O))),
		n10OOOO = (((((((~ ((~ comp_pat[0]) ^ nlll0OO)) & (~ ((~ comp_pat[1]) ^ nllli1i))) & (~ ((~ comp_pat[2]) ^ nllli1l))) & (~ ((~ comp_pat[3]) ^ nllli1O))) & (~ ((~ comp_pat[4]) ^ nllli0i))) & (~ ((~ comp_pat[5]) ^ nllli0l))) & (~ ((~ comp_pat[6]) ^ nllli0O))),
		n11000i = ((((((~ n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n11000l = (((((~ n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n11000O = ((((~ n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n11001i = (((((((((~ n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n11001l = ((((((((~ n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n11001O = (((((((~ n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1100ii = (((~ n11iiOl) | n11iilO) | n11iili),
		n1100il = ((~ n11iilO) | n11iili),
		n1100iO = (pmadwidth[0] & n110l1i),
		n1100li = (pmadwidth[0] & n1100ll),
		n1100ll = ((((((((((((((((((nllO11l & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n1100lO = (pmadwidth[0] & n1100Oi),
		n1100Oi = (((((((((((((((((nllO11i & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n1100Ol = (pmadwidth[0] & n1100OO),
		n1100OO = ((((((((((((((((nlllOOO & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n11010i = ((((((((~ n11000i) | (~ n11001O)) | (~ n11001l)) | (~ n11001i)) | (~ n1101OO)) | (~ n1101Ol)) | (~ n1101Oi)) | (~ n1101lO)),
		n11010l = ((((n11iili | (~ n1100il)) | (~ n1100ii)) | (~ n11000O)) | (~ n11000l)),
		n11010O = (((((((((((((((((((~ n11l1ll) | n11l1li) | n11l1iO) | n11l10O) | n11l11O) | n11iOOO) | n11iOlO) | n11iOiO) | n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n11011i = (((((((((((((((((((((pmadwidth[0] & (~ nllO11O)) | ((~ pmadwidth[0]) & (~ nlllOOl))) & (~ n11l1ll)) & (~ n11l1li)) & (~ n11l1iO)) & (~ n11l10O)) & (~ n11l11O)) & (~ n11iOOO)) & (~ n11iOlO)) & (~ n11iOiO)) & (~ n11iO0O)) & (~ n11iO1O)) & (~ n11ilOO)) & (~ n11illO)) & (~ n11iliO)) & (~ n11il0O)) & (~ n11il1O)) & (~ n11il1i)) & (~ n11iiOl)) & (~ n11iilO)) & (~ n11iili)),
		n11011l = ((((((((((~ n1100il) | (~ n1100ii)) | (~ n11000i)) | (~ n11001O)) | (~ n1101OO)) | (~ n1101Ol)) | (~ n1101ll)) | (~ n1101li)) | (~ n1101ii)) | (~ n11010O)),
		n11011O = ((((((((n11iili | (~ n11000i)) | (~ n11001O)) | (~ n11001l)) | (~ n11001i)) | (~ n1101ll)) | (~ n1101li)) | (~ n1101iO)) | (~ n1101il)),
		n1101ii = ((((((((((((((((((~ n11l1li) | n11l1iO) | n11l10O) | n11l11O) | n11iOOO) | n11iOlO) | n11iOiO) | n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1101il = (((((((((((((((((~ n11l1iO) | n11l10O) | n11l11O) | n11iOOO) | n11iOlO) | n11iOiO) | n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1101iO = ((((((((((((((((~ n11l10O) | n11l11O) | n11iOOO) | n11iOlO) | n11iOiO) | n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1101li = (((((((((((((((~ n11l11O) | n11iOOO) | n11iOlO) | n11iOiO) | n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1101ll = ((((((((((((((~ n11iOOO) | n11iOlO) | n11iOiO) | n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1101lO = (((((((((((((~ n11iOlO) | n11iOiO) | n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1101Oi = ((((((((((((~ n11iOiO) | n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1101Ol = (((((((((((~ n11iO0O) | n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n1101OO = ((((((((((~ n11iO1O) | n11ilOO) | n11illO) | n11iliO) | n11il0O) | n11il1O) | n11il1i) | n11iiOl) | n11iilO) | n11iili),
		n110i0i = (((((((((((nlllOli & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110i0l = ((((((((((nlllOiO & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110i0O = (((((((((nlllOil & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110i1i = ((((((((((((((nlllOOi & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110i1l = (((((((((((((nlllOlO & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110i1O = ((((((((((((nlllOll & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110iii = ((((((((nlllOii & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110iil = (((((((nlllO0O & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110iiO = ((((((nlllO0l & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110ili = (((((nlllO0i & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110ill = ((((nlllO1O & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110ilO = (((nlllO1l & nlllO1i) & nllllOO) & nllllOl),
		n110iOi = ((nlllO1i & nllllOO) & nllllOl),
		n110iOl = (nllllOO & nllllOl),
		n110iOO = (pmadwidth[0] & n110l1i),
		n110l0i = (pmadwidth[0] & n110l0l),
		n110l0l = (((((((((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i),
		n110l0O = (pmadwidth[0] & n110lii),
		n110l1i = (((((((((((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110l1l = (pmadwidth[0] & n110l1O),
		n110l1O = ((((((((((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO),
		n110lii = ((((((((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l),
		n110lil = ((pmadwidth[0] & n110lli) | ((~ pmadwidth[0]) & n110liO)),
		n110liO = (((((((((((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO) & nllllOl),
		n110lli = (((((((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O),
		n110lll = ((pmadwidth[0] & n110lOi) | ((~ pmadwidth[0]) & n110llO)),
		n110llO = ((((((((((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i) & nllllOO),
		n110lOi = ((((((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i),
		n110lOl = ((pmadwidth[0] & n110O1i) | ((~ pmadwidth[0]) & n110lOO)),
		n110lOO = (((((((((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l) & nlllO1i),
		n110O0i = ((((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O),
		n110O0l = ((pmadwidth[0] & n110Oii) | ((~ pmadwidth[0]) & n110O0O)),
		n110O0O = (((((((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O),
		n110O1i = (((((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l),
		n110O1l = ((pmadwidth[0] & n110O0i) | ((~ pmadwidth[0]) & n110O1O)),
		n110O1O = ((((((((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i) & nlllO1O) & nlllO1l),
		n110Oii = (((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii),
		n110Oil = ((pmadwidth[0] & n110Oli) | ((~ pmadwidth[0]) & n110OiO)),
		n110OiO = ((((((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l) & nlllO0i),
		n110Oli = ((((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil),
		n110Oll = ((pmadwidth[0] & n110OOi) | ((~ pmadwidth[0]) & n110OlO)),
		n110OlO = (((((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O) & nlllO0l),
		n110OOi = (((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO),
		n110OOl = ((pmadwidth[0] & n11i11i) | ((~ pmadwidth[0]) & n110OOO)),
		n110OOO = ((((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii) & nlllO0O),
		n11100i = ((((((((n110liO | (~ n110i0i)) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n11100l = (((((((n110liO | (~ n110i1O)) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n11100O = ((((((n110liO | (~ n110i1l)) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n11101i = (((((((((((n110liO | (~ n110iii)) | n110i0O) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n11101l = ((((((((((n110liO | (~ n110i0O)) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n11101O = (((((((((n110liO | (~ n110i0l)) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1110ii = (((((n110liO | (~ n110i1i)) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1110il = (((((~ n110liO) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1110iO = ((((~ n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1110li = (((~ n1100lO) | n1100li) | n1100iO),
		n1110ll = ((~ n1100li) | n1100iO),
		n1110lO = ((((((((((~ n111l0l) | (~ n111l1O)) | (~ n111l1i)) | (~ n111iOl)) | (~ n111ilO)) | (~ n111ili)) | (~ n111iil)) | (~ n111i0O)) | (~ n111i0i)) | n1110Oi),
		n1110Oi = ((((((((((((((((((((n11i01O | n11i01l) & (~ n11i01i)) & (~ n11i1OO)) & (~ n11i1Ol)) & (~ n11i1ll)) & (~ n11i1il)) & (~ n11i10l)) & (~ n11i11l)) & (~ n110OOl)) & (~ n110Oll)) & (~ n110Oil)) & (~ n110O0l)) & (~ n110O1l)) & (~ n110lOl)) & (~ n110lll)) & (~ n110lil)) & (~ n110l0O)) & (~ n110l0i)) & (~ n110l1l)) & (~ n110iOO)),
		n1110Ol = ((((((((((~ n111l0l) | (~ n111l0i)) | (~ n111l1i)) | (~ n111iOO)) | (~ n111ilO)) | (~ n111ill)) | (~ n111iil)) | (~ n111iii)) | (~ n111i0i)) | (~ n111i1O)),
		n1110OO = ((((((((n110iOO | (~ n111l1i)) | (~ n111iOO)) | (~ n111iOl)) | (~ n111iOi)) | (~ n111iil)) | (~ n111iii)) | (~ n111i0O)) | (~ n111i0l)),
		n11110i = (((((((((((((((((((nllllOl & (~ n110liO)) & (~ n110iOl)) & (~ n110iOi)) & (~ n110ilO)) & (~ n110ill)) & (~ n110ili)) & (~ n110iiO)) & (~ n110iil)) & (~ n110iii)) & (~ n110i0O)) & (~ n110i0l)) & (~ n110i0i)) & (~ n110i1O)) & (~ n110i1l)) & (~ n110i1i)) & (~ n1100Ol)) & (~ n1100lO)) & (~ n1100li)) & (~ n1100iO)),
		n11110l = ((((((((((~ n1110ll) | (~ n1110li)) | (~ n1110ii)) | (~ n11100O)) | (~ n11101O)) | (~ n11101l)) | (~ n1111Ol)) | (~ n1111Oi)) | (~ n1111li)) | (~ n1111iO)),
		n11110O = ((((((((n1100iO | (~ n1110ii)) | (~ n11100O)) | (~ n11100l)) | (~ n11100i)) | (~ n1111Ol)) | (~ n1111Oi)) | (~ n1111lO)) | (~ n1111ll)),
		n11111i = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | (~ wire_n01il0O_dataout)),
		n11111l = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl) | (~ wire_n01il0O_dataout)),
		n11111O = ((((((((((~ n1110ll) | (~ n1110iO)) | (~ n1110ii)) | (~ n11100l)) | (~ n11101O)) | (~ n11101i)) | (~ n1111Ol)) | (~ n1111lO)) | (~ n1111li)) | n11110i),
		n1111ii = ((((((((~ n1110ii) | (~ n11100O)) | (~ n11100l)) | (~ n11100i)) | (~ n11101O)) | (~ n11101l)) | (~ n11101i)) | (~ n1111OO)),
		n1111il = ((((n1100iO | (~ n1110ll)) | (~ n1110li)) | (~ n1110iO)) | (~ n1110il)),
		n1111iO = ((((((((((((((((((n110liO | (~ n110iOl)) | n110iOi) | n110ilO) | n110ill) | n110ili) | n110iiO) | n110iil) | n110iii) | n110i0O) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1111li = (((((((((((((((((n110liO | (~ n110iOi)) | n110ilO) | n110ill) | n110ili) | n110iiO) | n110iil) | n110iii) | n110i0O) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1111ll = ((((((((((((((((n110liO | (~ n110ilO)) | n110ill) | n110ili) | n110iiO) | n110iil) | n110iii) | n110i0O) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1111lO = (((((((((((((((n110liO | (~ n110ill)) | n110ili) | n110iiO) | n110iil) | n110iii) | n110i0O) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1111Oi = ((((((((((((((n110liO | (~ n110ili)) | n110iiO) | n110iil) | n110iii) | n110i0O) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1111Ol = (((((((((((((n110liO | (~ n110iiO)) | n110iil) | n110iii) | n110i0O) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n1111OO = ((((((((((((n110liO | (~ n110iil)) | n110iii) | n110i0O) | n110i0l) | n110i0i) | n110i1O) | n110i1l) | n110i1i) | n1100Ol) | n1100lO) | n1100li) | n1100iO),
		n111i0i = ((((((((((((((((((~ n11i1OO) | n11i1Ol) | n11i1ll) | n11i1il) | n11i10l) | n11i11l) | n110OOl) | n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111i0l = (((((((((((((((((~ n11i1Ol) | n11i1ll) | n11i1il) | n11i10l) | n11i11l) | n110OOl) | n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111i0O = ((((((((((((((((~ n11i1ll) | n11i1il) | n11i10l) | n11i11l) | n110OOl) | n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111i1i = ((((((((~ n111l1i) | (~ n111iOO)) | (~ n111iOl)) | (~ n111iOi)) | (~ n111ilO)) | (~ n111ill)) | (~ n111ili)) | (~ n111iiO)),
		n111i1l = ((((n110iOO | (~ n111l0l)) | (~ n111l0i)) | (~ n111l1O)) | (~ n111l1l)),
		n111i1O = (((((((((((((((((((~ n11i01i) | n11i1OO) | n11i1Ol) | n11i1ll) | n11i1il) | n11i10l) | n11i11l) | n110OOl) | n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111iii = (((((((((((((((~ n11i1il) | n11i10l) | n11i11l) | n110OOl) | n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111iil = ((((((((((((((~ n11i10l) | n11i11l) | n110OOl) | n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111iiO = (((((((((((((~ n11i11l) | n110OOl) | n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111ili = ((((((((((((~ n110OOl) | n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111ill = (((((((((((~ n110Oll) | n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111ilO = ((((((((((~ n110Oil) | n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111iOi = (((((((((~ n110O0l) | n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111iOl = ((((((((~ n110O1l) | n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111iOO = (((((((~ n110lOl) | n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111l0i = (((~ n110l0i) | n110l1l) | n110iOO),
		n111l0l = ((~ n110l1l) | n110iOO),
		n111l0O = ((((((((((~ n111OOl) | (~ n111OlO)) | (~ n111Oli)) | (~ n111Oil)) | (~ n111O0O)) | (~ n111O0i)) | (~ n111O1l)) | (~ n111lOO)) | (~ n111lOi)) | n111lii),
		n111l1i = ((((((~ n110lll) | n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111l1l = (((((~ n110lil) | n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111l1O = ((((~ n110l0O) | n110l0i) | n110l1l) | n110iOO),
		n111lii = ((((((((((((((((((((~ nllllOl) & n11il0i) & n11iiiO) & n11iiil) & n11iiii) & n11ii0O) & n11ii0l) & n11ii0i) & n11ii1O) & n11ii1l) & n11ii1i) & n11i0OO) & n11i0Ol) & n11i0Oi) & n11i0lO) & n11i0ll) & (~ n11i0iO)) & (~ n11i0ii)) & (~ n11i00l)) & (~ n11i00i)),
		n111lil = ((((((((((~ n111OOl) | (~ n111OOi)) | (~ n111Oli)) | (~ n111OiO)) | (~ n111O0O)) | (~ n111O0l)) | (~ n111O1l)) | (~ n111O1i)) | (~ n111lOi)) | (~ n111llO)),
		n111liO = ((((((((n11i00i | (~ n111Oli)) | (~ n111OiO)) | (~ n111Oil)) | (~ n111Oii)) | (~ n111O1l)) | (~ n111O1i)) | (~ n111lOO)) | (~ n111lOl)),
		n111lli = ((((((((~ n111Oli) | (~ n111OiO)) | (~ n111Oil)) | (~ n111Oii)) | (~ n111O0O)) | (~ n111O0l)) | (~ n111O0i)) | (~ n111O1O)),
		n111lll = ((((n11i00i | (~ n111OOl)) | (~ n111OOi)) | (~ n111OlO)) | (~ n111Oll)),
		n111llO = (((((((((((((((((((~ n11il0i) | n11iiiO) | (~ n11iiil)) | (~ n11iiii)) | (~ n11ii0O)) | (~ n11ii0l)) | (~ n11ii0i)) | (~ n11ii1O)) | (~ n11ii1l)) | (~ n11ii1i)) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111lOi = ((((((((((((((((((~ n11il0i) | n11iiil) | (~ n11iiii)) | (~ n11ii0O)) | (~ n11ii0l)) | (~ n11ii0i)) | (~ n11ii1O)) | (~ n11ii1l)) | (~ n11ii1i)) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111lOl = (((((((((((((((((~ n11il0i) | n11iiii) | (~ n11ii0O)) | (~ n11ii0l)) | (~ n11ii0i)) | (~ n11ii1O)) | (~ n11ii1l)) | (~ n11ii1i)) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111lOO = ((((((((((((((((~ n11il0i) | n11ii0O) | (~ n11ii0l)) | (~ n11ii0i)) | (~ n11ii1O)) | (~ n11ii1l)) | (~ n11ii1i)) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111O0i = ((((((((((((~ n11il0i) | n11ii1l) | (~ n11ii1i)) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111O0l = (((((((((((~ n11il0i) | n11ii1i) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111O0O = ((((((((((~ n11il0i) | n11i0OO) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111O1i = (((((((((((((((~ n11il0i) | n11ii0l) | (~ n11ii0i)) | (~ n11ii1O)) | (~ n11ii1l)) | (~ n11ii1i)) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111O1l = ((((((((((((((~ n11il0i) | n11ii0i) | (~ n11ii1O)) | (~ n11ii1l)) | (~ n11ii1i)) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111O1O = (((((((((((((~ n11il0i) | n11ii1O) | (~ n11ii1l)) | (~ n11ii1i)) | (~ n11i0OO)) | (~ n11i0Ol)) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111Oii = (((((((((~ n11il0i) | n11i0Ol) | (~ n11i0Oi)) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111Oil = ((((((((~ n11il0i) | n11i0Oi) | (~ n11i0lO)) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111OiO = (((((((~ n11il0i) | n11i0lO) | (~ n11i0ll)) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111Oli = ((((((~ n11il0i) | n11i0ll) | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111Oll = ((((n11il0i | n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111OlO = ((((~ n11i0iO) | n11i0ii) | n11i00l) | n11i00i),
		n111OOi = (((~ n11i0ii) | n11i00l) | n11i00i),
		n111OOl = ((~ n11i00l) | n11i00i),
		n111OOO = ((((((((((~ n1100il) | (~ n11000O)) | (~ n11000i)) | (~ n11001l)) | (~ n1101OO)) | (~ n1101Oi)) | (~ n1101ll)) | (~ n1101iO)) | (~ n1101ii)) | n11011i),
		n11i00i = (pmadwidth[0] & (~ n11iill)),
		n11i00l = (pmadwidth[0] & (~ n11i00O)),
		n11i00O = ((((((((((((((((((nllO11l | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11i01i = ((pmadwidth[0] & (nllO11O & nllO11l)) | ((~ pmadwidth[0]) & (nlllOOl & nlllOOi))),
		n11i01l = ((~ pmadwidth[0]) & nlllOOl),
		n11i01O = (pmadwidth[0] & nllO11O),
		n11i0ii = (pmadwidth[0] & (~ n11i0il)),
		n11i0il = (((((((((((((((((nllO11i | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11i0iO = (pmadwidth[0] & (~ n11i0li)),
		n11i0li = ((((((((((((((((nlllOOO | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11i0ll = ((((((((((((((nlllOOi | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11i0lO = (((((((((((((nlllOlO | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11i0Oi = ((((((((((((nlllOll | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11i0Ol = (((((((((((nlllOli | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11i0OO = ((((((((((nlllOiO | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11i10i = (((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll),
		n11i10l = ((pmadwidth[0] & n11i1ii) | ((~ pmadwidth[0]) & n11i10O)),
		n11i10O = ((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil),
		n11i11i = ((((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO) & nlllOll) & nlllOli),
		n11i11l = ((pmadwidth[0] & n11i10i) | ((~ pmadwidth[0]) & n11i11O)),
		n11i11O = (((((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO) & nlllOil) & nlllOii),
		n11i1ii = ((((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi) & nlllOlO),
		n11i1il = ((pmadwidth[0] & n11i1li) | ((~ pmadwidth[0]) & n11i1iO)),
		n11i1iO = (((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli) & nlllOiO),
		n11i1li = (((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl) & nlllOOi),
		n11i1ll = ((pmadwidth[0] & n11i1Oi) | ((~ pmadwidth[0]) & n11i1lO)),
		n11i1lO = ((((nlllOOl & nlllOOi) & nlllOlO) & nlllOll) & nlllOli),
		n11i1Oi = ((((nllO11O & nllO11l) & nllO11i) & nlllOOO) & nlllOOl),
		n11i1Ol = ((pmadwidth[0] & (((nllO11O & nllO11l) & nllO11i) & nlllOOO)) | ((~ pmadwidth[0]) & (((nlllOOl & nlllOOi) & nlllOlO) & nlllOll))),
		n11i1OO = ((pmadwidth[0] & ((nllO11O & nllO11l) & nllO11i)) | ((~ pmadwidth[0]) & ((nlllOOl & nlllOOi) & nlllOlO))),
		n11ii0i = ((((((nlllO0l | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11ii0l = (((((nlllO0i | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11ii0O = ((((nlllO1O | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11ii1i = (((((((((nlllOil | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11ii1l = ((((((((nlllOii | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11ii1O = (((((((nlllO0O | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11iiii = (((nlllO1l | nlllO1i) | nllllOO) | nllllOl),
		n11iiil = ((nlllO1i | nllllOO) | nllllOl),
		n11iiiO = (nllllOO | nllllOl),
		n11iili = (pmadwidth[0] & (~ n11iill)),
		n11iill = (((((((((((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11iilO = (pmadwidth[0] & (~ n11iiOi)),
		n11iiOi = ((((((((((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO),
		n11iiOl = (pmadwidth[0] & (~ n11iiOO)),
		n11iiOO = (((((((((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i),
		n11il0i = (((((((((((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl),
		n11il0l = (((((((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O),
		n11il0O = ((pmadwidth[0] & (~ n11ilil)) | ((~ pmadwidth[0]) & (~ n11ilii))),
		n11il1i = (pmadwidth[0] & (~ n11il1l)),
		n11il1l = ((((((((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l),
		n11il1O = ((pmadwidth[0] & (~ n11il0l)) | ((~ pmadwidth[0]) & (~ n11il0i))),
		n11ilii = ((((((((((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO),
		n11ilil = ((((((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i),
		n11iliO = ((pmadwidth[0] & (~ n11illl)) | ((~ pmadwidth[0]) & (~ n11illi))),
		n11illi = (((((((((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i),
		n11illl = (((((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l),
		n11illO = ((pmadwidth[0] & (~ n11ilOl)) | ((~ pmadwidth[0]) & (~ n11ilOi))),
		n11ilOi = ((((((((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l),
		n11ilOl = ((((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O),
		n11ilOO = ((pmadwidth[0] & (~ n11iO1l)) | ((~ pmadwidth[0]) & (~ n11iO1i))),
		n11iO0i = ((((((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i),
		n11iO0l = ((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil),
		n11iO0O = ((pmadwidth[0] & (~ n11iOil)) | ((~ pmadwidth[0]) & (~ n11iOii))),
		n11iO1i = (((((((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O),
		n11iO1l = (((((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii),
		n11iO1O = ((pmadwidth[0] & (~ n11iO0l)) | ((~ pmadwidth[0]) & (~ n11iO0i))),
		n11iOii = (((((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l),
		n11iOil = (((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO),
		n11iOiO = ((pmadwidth[0] & (~ n11iOll)) | ((~ pmadwidth[0]) & (~ n11iOli))),
		n11iOli = ((((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O),
		n11iOll = ((((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli),
		n11iOlO = ((pmadwidth[0] & (~ n11iOOl)) | ((~ pmadwidth[0]) & (~ n11iOOi))),
		n11iOOi = (((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii),
		n11iOOl = (((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll),
		n11iOOO = ((pmadwidth[0] & (~ n11l11l)) | ((~ pmadwidth[0]) & (~ n11l11i))),
		n11l00i = (n11lO1O | n11lO1l),
		n11l00l = (n11lOil | n11lO0O),
		n11l00O = ((((((((~ (comp_pat[0] ^ nl0i1li)) & (~ (comp_pat[1] ^ nl0i1ll))) & (~ (comp_pat[2] ^ nl0i1lO))) & (~ (comp_pat[3] ^ nl0i1Oi))) & (~ (comp_pat[4] ^ nl0i1Ol))) & (~ (comp_pat[5] ^ nl0i1OO))) & (~ (comp_pat[6] ^ nl0i01i))) & (~ (comp_pat[7] ^ nl0i01l))),
		n11l01i = ((((nl0i1iO & nl0i1il) & nl0i1ii) & nl0i10O) & nl0i10l),
		n11l01l = (wa_6g_en & autobytealign_dis),
		n11l01O = (wire_nlliiOO_dataout & ((~ autobytealign_dis) & n1iOOOO)),
		n11l0ii = (((((((~ (comp_pat[0] ^ nl0i1li)) & (~ (comp_pat[1] ^ nl0i1ll))) & (~ (comp_pat[2] ^ nl0i1lO))) & (~ (comp_pat[3] ^ nl0i1Oi))) & (~ (comp_pat[4] ^ nl0i1Ol))) & (~ (comp_pat[5] ^ nl0i1OO))) & (~ (comp_pat[6] ^ nl0i01i))),
		n11l0il = (((((((~ ((~ comp_pat[0]) ^ nl0i1li)) & (~ ((~ comp_pat[1]) ^ nl0i1ll))) & (~ ((~ comp_pat[2]) ^ nl0i1lO))) & (~ ((~ comp_pat[3]) ^ nl0i1Oi))) & (~ ((~ comp_pat[4]) ^ nl0i1Ol))) & (~ ((~ comp_pat[5]) ^ nl0i1OO))) & (~ ((~ comp_pat[6]) ^ nl0i01i))),
		n11l0iO = ((((((((~ (comp_pat[8] ^ nl0i01O)) & (~ (comp_pat[9] ^ nl0i00i))) & (~ (comp_pat[10] ^ nl0i00l))) & (~ (comp_pat[11] ^ nl0i00O))) & (~ (comp_pat[12] ^ nl0i0ii))) & (~ (comp_pat[13] ^ nl0i0il))) & (~ (comp_pat[14] ^ nl0i0iO))) & (~ (comp_pat[15] ^ nl0i0li))),
		n11l0li = ((((((((((~ (comp_pat[0] ^ nl0i00l)) & (~ (comp_pat[1] ^ nl0i00O))) & (~ (comp_pat[2] ^ nl0i0ii))) & (~ (comp_pat[3] ^ nl0i0il))) & (~ (comp_pat[4] ^ nl0i0iO))) & (~ (comp_pat[5] ^ nl0i0li))) & (~ (comp_pat[6] ^ nl0i0ll))) & (~ (comp_pat[7] ^ nl0i0lO))) & (~ (comp_pat[8] ^ nl0i0Oi))) & (~ (comp_pat[9] ^ nl0i0Ol))),
		n11l0ll = ((((((((((~ ((~ comp_pat[0]) ^ nl0i00l)) & (~ ((~ comp_pat[1]) ^ nl0i00O))) & (~ ((~ comp_pat[2]) ^ nl0i0ii))) & (~ ((~ comp_pat[3]) ^ nl0i0il))) & (~ ((~ comp_pat[4]) ^ nl0i0iO))) & (~ ((~ comp_pat[5]) ^ nl0i0li))) & (~ ((~ comp_pat[6]) ^ nl0i0ll))) & (~ ((~ comp_pat[7]) ^ nl0i0lO))) & (~ ((~ comp_pat[8]) ^ nl0i0Oi))) & (~ ((~ comp_pat[9]) ^ nl0i0Ol))),
		n11l0lO = ((((((((~ (comp_pat[0] ^ nl0i01O)) & (~ (comp_pat[1] ^ nl0i00i))) & (~ (comp_pat[2] ^ nl0i00l))) & (~ (comp_pat[3] ^ nl0i00O))) & (~ (comp_pat[4] ^ nl0i0ii))) & (~ (comp_pat[5] ^ nl0i0il))) & (~ (comp_pat[6] ^ nl0i0iO))) & (~ (comp_pat[7] ^ nl0i0li))),
		n11l0Oi = (((((((~ (comp_pat[0] ^ nl0i00l)) & (~ (comp_pat[1] ^ nl0i00O))) & (~ (comp_pat[2] ^ nl0i0ii))) & (~ (comp_pat[3] ^ nl0i0il))) & (~ (comp_pat[4] ^ nl0i0iO))) & (~ (comp_pat[5] ^ nl0i0li))) & (~ (comp_pat[6] ^ nl0i0ll))),
		n11l0Ol = (((((((~ ((~ comp_pat[0]) ^ nl0i00l)) & (~ ((~ comp_pat[1]) ^ nl0i00O))) & (~ ((~ comp_pat[2]) ^ nl0i0ii))) & (~ ((~ comp_pat[3]) ^ nl0i0il))) & (~ ((~ comp_pat[4]) ^ nl0i0iO))) & (~ ((~ comp_pat[5]) ^ nl0i0li))) & (~ ((~ comp_pat[6]) ^ nl0i0ll))),
		n11l0OO = ((comp_pat_porn & n11li1l) | n11li1i),
		n11l10i = (((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO),
		n11l10l = (((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi),
		n11l10O = ((pmadwidth[0] & (~ n11l1il)) | ((~ pmadwidth[0]) & (~ n11l1ii))),
		n11l11i = ((((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil),
		n11l11l = ((((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO),
		n11l11O = ((pmadwidth[0] & (~ n11l10l)) | ((~ pmadwidth[0]) & (~ n11l10i))),
		n11l1ii = ((((nlllOOl | nlllOOi) | nlllOlO) | nlllOll) | nlllOli),
		n11l1il = ((((nllO11O | nllO11l) | nllO11i) | nlllOOO) | nlllOOl),
		n11l1iO = ((pmadwidth[0] & (~ (((nllO11O | nllO11l) | nllO11i) | nlllOOO))) | ((~ pmadwidth[0]) & (~ (((nlllOOl | nlllOOi) | nlllOlO) | nlllOll)))),
		n11l1li = ((pmadwidth[0] & (~ ((nllO11O | nllO11l) | nllO11i))) | ((~ pmadwidth[0]) & (~ ((nlllOOl | nlllOOi) | nlllOlO)))),
		n11l1ll = ((pmadwidth[0] & (~ (nllO11O | nllO11l))) | ((~ pmadwidth[0]) & (~ (nlllOOl | nlllOOi)))),
		n11l1lO = (((((~ (nl00OOO ^ nl00Oli)) & (~ (nl0i11i ^ nl00Oll))) & (~ (nl0i11l ^ nl00OlO))) & (~ (nl0i11O ^ nl00OOi))) & (~ (nl0i10i ^ nl00OOl))),
		n11l1Oi = ((((nl00OOl & nl00OOi) & nl00OlO) & nl00Oll) & nl00Oli),
		n11l1Ol = (comp_pat_size[0] & autobytealign_dis),
		n11l1OO = ((~ comp_pat_size[0]) & autobytealign_dis),
		n11li0i = ((((((((((~ (comp_pat[10] ^ nl0i00l)) & (~ (comp_pat[11] ^ nl0i00O))) & (~ (comp_pat[12] ^ nl0i0ii))) & (~ (comp_pat[13] ^ nl0i0il))) & (~ (comp_pat[14] ^ nl0i0iO))) & (~ (comp_pat[15] ^ nl0i0li))) & (~ (comp_pat[16] ^ nl0i0ll))) & (~ (comp_pat[17] ^ nl0i0lO))) & (~ (comp_pat[18] ^ nl0i0Oi))) & (~ (comp_pat[19] ^ nl0i0Ol))),
		n11li0l = ((((((((((~ ((~ comp_pat[10]) ^ nl0i00l)) & (~ ((~ comp_pat[11]) ^ nl0i00O))) & (~ ((~ comp_pat[12]) ^ nl0i0ii))) & (~ ((~ comp_pat[13]) ^ nl0i0il))) & (~ ((~ comp_pat[14]) ^ nl0i0iO))) & (~ ((~ comp_pat[15]) ^ nl0i0li))) & (~ ((~ comp_pat[16]) ^ nl0i0ll))) & (~ ((~ comp_pat[17]) ^ nl0i0lO))) & (~ ((~ comp_pat[18]) ^ nl0i0Oi))) & (~ ((~ comp_pat[19]) ^ nl0i0Ol))),
		n11li0O = ((n11liOl | nl00i1O) | (dwidth & nl000li)),
		n11li1i = ((((((((((~ (comp_pat[0] ^ nl0i1li)) & (~ (comp_pat[1] ^ nl0i1ll))) & (~ (comp_pat[2] ^ nl0i1lO))) & (~ (comp_pat[3] ^ nl0i1Oi))) & (~ (comp_pat[4] ^ nl0i1Ol))) & (~ (comp_pat[5] ^ nl0i1OO))) & (~ (comp_pat[6] ^ nl0i01i))) & (~ (comp_pat[7] ^ nl0i01l))) & (~ (comp_pat[8] ^ nl0i01O))) & (~ (comp_pat[9] ^ nl0i00i))),
		n11li1l = ((((((((((~ ((~ comp_pat[0]) ^ nl0i1li)) & (~ ((~ comp_pat[1]) ^ nl0i1ll))) & (~ ((~ comp_pat[2]) ^ nl0i1lO))) & (~ ((~ comp_pat[3]) ^ nl0i1Oi))) & (~ ((~ comp_pat[4]) ^ nl0i1Ol))) & (~ ((~ comp_pat[5]) ^ nl0i1OO))) & (~ ((~ comp_pat[6]) ^ nl0i01i))) & (~ ((~ comp_pat[7]) ^ nl0i01l))) & (~ ((~ comp_pat[8]) ^ nl0i01O))) & (~ ((~ comp_pat[9]) ^ nl0i00i))),
		n11li1O = ((comp_pat_porn & n11li0l) | n11li0i),
		n11liii = ((n11ll1l | nl00i1l) | (dwidth & nl000iO)),
		n11liil = ((comp_pat_porn & n11lili) | n11liiO),
		n11liiO = ((((((((((~ (comp_pat[10] ^ nl0iili)) & (~ (comp_pat[11] ^ nl0iill))) & (~ (comp_pat[12] ^ nl0iilO))) & (~ (comp_pat[13] ^ nl0iiOi))) & (~ (comp_pat[14] ^ nl0iiOl))) & (~ (comp_pat[15] ^ nl0iiOO))) & (~ (comp_pat[16] ^ nl0il1i))) & (~ (comp_pat[17] ^ nl0il1l))) & (~ (comp_pat[18] ^ nl0il1O))) & (~ (comp_pat[19] ^ nl0il0i))),
		n11lili = ((((((((((~ ((~ comp_pat[10]) ^ nl0iili)) & (~ ((~ comp_pat[11]) ^ nl0iill))) & (~ ((~ comp_pat[12]) ^ nl0iilO))) & (~ ((~ comp_pat[13]) ^ nl0iiOi))) & (~ ((~ comp_pat[14]) ^ nl0iiOl))) & (~ ((~ comp_pat[15]) ^ nl0iiOO))) & (~ ((~ comp_pat[16]) ^ nl0il1i))) & (~ ((~ comp_pat[17]) ^ nl0il1l))) & (~ ((~ comp_pat[18]) ^ nl0il1O))) & (~ ((~ comp_pat[19]) ^ nl0il0i))),
		n11lill = ((comp_pat_porn & n11liOi) | n11lilO),
		n11lilO = ((((((((((~ (comp_pat[10] ^ nl0i0OO)) & (~ (comp_pat[11] ^ nl0ii1i))) & (~ (comp_pat[12] ^ nl0ii1l))) & (~ (comp_pat[13] ^ nl0ii1O))) & (~ (comp_pat[14] ^ nl0ii0i))) & (~ (comp_pat[15] ^ nl0ii0l))) & (~ (comp_pat[16] ^ nl0ii0O))) & (~ (comp_pat[17] ^ nl0iiii))) & (~ (comp_pat[18] ^ nl0iiil))) & (~ (comp_pat[19] ^ nl0iiiO))),
		n11liOi = ((((((((((~ ((~ comp_pat[10]) ^ nl0i0OO)) & (~ ((~ comp_pat[11]) ^ nl0ii1i))) & (~ ((~ comp_pat[12]) ^ nl0ii1l))) & (~ ((~ comp_pat[13]) ^ nl0ii1O))) & (~ ((~ comp_pat[14]) ^ nl0ii0i))) & (~ ((~ comp_pat[15]) ^ nl0ii0l))) & (~ ((~ comp_pat[16]) ^ nl0ii0O))) & (~ ((~ comp_pat[17]) ^ nl0iiii))) & (~ ((~ comp_pat[18]) ^ nl0iiil))) & (~ ((~ comp_pat[19]) ^ nl0iiiO))),
		n11liOl = ((comp_pat_porn & n11ll1i) | n11liOO),
		n11liOO = ((((((((((~ (comp_pat[0] ^ nl0iili)) & (~ (comp_pat[1] ^ nl0iill))) & (~ (comp_pat[2] ^ nl0iilO))) & (~ (comp_pat[3] ^ nl0iiOi))) & (~ (comp_pat[4] ^ nl0iiOl))) & (~ (comp_pat[5] ^ nl0iiOO))) & (~ (comp_pat[6] ^ nl0il1i))) & (~ (comp_pat[7] ^ nl0il1l))) & (~ (comp_pat[8] ^ nl0il1O))) & (~ (comp_pat[9] ^ nl0il0i))),
		n11ll0i = ((((((((((~ ((~ comp_pat[0]) ^ nl0i0OO)) & (~ ((~ comp_pat[1]) ^ nl0ii1i))) & (~ ((~ comp_pat[2]) ^ nl0ii1l))) & (~ ((~ comp_pat[3]) ^ nl0ii1O))) & (~ ((~ comp_pat[4]) ^ nl0ii0i))) & (~ ((~ comp_pat[5]) ^ nl0ii0l))) & (~ ((~ comp_pat[6]) ^ nl0ii0O))) & (~ ((~ comp_pat[7]) ^ nl0iiii))) & (~ ((~ comp_pat[8]) ^ nl0iiil))) & (~ ((~ comp_pat[9]) ^ nl0iiiO))),
		n11ll0l = ((comp_pat_porn & n11llii) | n11ll0O),
		n11ll0O = ((((((((~ (comp_pat[8] ^ nl0iiil)) & (~ (comp_pat[9] ^ nl0iiiO))) & (~ (comp_pat[10] ^ nl0iili))) & (~ (comp_pat[11] ^ nl0iill))) & (~ (comp_pat[12] ^ nl0iilO))) & (~ (comp_pat[13] ^ nl0iiOi))) & (~ (comp_pat[14] ^ nl0iiOl))) & (~ (comp_pat[15] ^ nl0iiOO))),
		n11ll1i = ((((((((((~ ((~ comp_pat[0]) ^ nl0iili)) & (~ ((~ comp_pat[1]) ^ nl0iill))) & (~ ((~ comp_pat[2]) ^ nl0iilO))) & (~ ((~ comp_pat[3]) ^ nl0iiOi))) & (~ ((~ comp_pat[4]) ^ nl0iiOl))) & (~ ((~ comp_pat[5]) ^ nl0iiOO))) & (~ ((~ comp_pat[6]) ^ nl0il1i))) & (~ ((~ comp_pat[7]) ^ nl0il1l))) & (~ ((~ comp_pat[8]) ^ nl0il1O))) & (~ ((~ comp_pat[9]) ^ nl0il0i))),
		n11ll1l = ((comp_pat_porn & n11ll0i) | n11ll1O),
		n11ll1O = ((((((((((~ (comp_pat[0] ^ nl0i0OO)) & (~ (comp_pat[1] ^ nl0ii1i))) & (~ (comp_pat[2] ^ nl0ii1l))) & (~ (comp_pat[3] ^ nl0ii1O))) & (~ (comp_pat[4] ^ nl0ii0i))) & (~ (comp_pat[5] ^ nl0ii0l))) & (~ (comp_pat[6] ^ nl0ii0O))) & (~ (comp_pat[7] ^ nl0iiii))) & (~ (comp_pat[8] ^ nl0iiil))) & (~ (comp_pat[9] ^ nl0iiiO))),
		n11llii = ((((((((~ ((~ comp_pat[8]) ^ nl0iiil)) & (~ ((~ comp_pat[9]) ^ nl0iiiO))) & (~ ((~ comp_pat[10]) ^ nl0iili))) & (~ ((~ comp_pat[11]) ^ nl0iill))) & (~ ((~ comp_pat[12]) ^ nl0iilO))) & (~ ((~ comp_pat[13]) ^ nl0iiOi))) & (~ ((~ comp_pat[14]) ^ nl0iiOl))) & (~ ((~ comp_pat[15]) ^ nl0iiOO))),
		n11llil = ((comp_pat_porn & n11llli) | n11lliO),
		n11lliO = ((((((((~ (comp_pat[8] ^ nl0i0OO)) & (~ (comp_pat[9] ^ nl0ii1i))) & (~ (comp_pat[10] ^ nl0ii1l))) & (~ (comp_pat[11] ^ nl0ii1O))) & (~ (comp_pat[12] ^ nl0ii0i))) & (~ (comp_pat[13] ^ nl0ii0l))) & (~ (comp_pat[14] ^ nl0ii0O))) & (~ (comp_pat[15] ^ nl0iiii))),
		n11llli = ((((((((~ ((~ comp_pat[8]) ^ nl0i0OO)) & (~ ((~ comp_pat[9]) ^ nl0ii1i))) & (~ ((~ comp_pat[10]) ^ nl0ii1l))) & (~ ((~ comp_pat[11]) ^ nl0ii1O))) & (~ ((~ comp_pat[12]) ^ nl0ii0i))) & (~ ((~ comp_pat[13]) ^ nl0ii0l))) & (~ ((~ comp_pat[14]) ^ nl0ii0O))) & (~ ((~ comp_pat[15]) ^ nl0iiii))),
		n11llll = ((comp_pat_porn & n11llOi) | n11lllO),
		n11lllO = ((((((((~ (comp_pat[0] ^ nl0iiil)) & (~ (comp_pat[1] ^ nl0iiiO))) & (~ (comp_pat[2] ^ nl0iili))) & (~ (comp_pat[3] ^ nl0iill))) & (~ (comp_pat[4] ^ nl0iilO))) & (~ (comp_pat[5] ^ nl0iiOi))) & (~ (comp_pat[6] ^ nl0iiOl))) & (~ (comp_pat[7] ^ nl0iiOO))),
		n11llOi = ((((((((~ ((~ comp_pat[0]) ^ nl0iiil)) & (~ ((~ comp_pat[1]) ^ nl0iiiO))) & (~ ((~ comp_pat[2]) ^ nl0iili))) & (~ ((~ comp_pat[3]) ^ nl0iill))) & (~ ((~ comp_pat[4]) ^ nl0iilO))) & (~ ((~ comp_pat[5]) ^ nl0iiOi))) & (~ ((~ comp_pat[6]) ^ nl0iiOl))) & (~ ((~ comp_pat[7]) ^ nl0iiOO))),
		n11llOl = ((comp_pat_porn & n11lO1i) | n11llOO),
		n11llOO = ((((((((~ (comp_pat[0] ^ nl0i0OO)) & (~ (comp_pat[1] ^ nl0ii1i))) & (~ (comp_pat[2] ^ nl0ii1l))) & (~ (comp_pat[3] ^ nl0ii1O))) & (~ (comp_pat[4] ^ nl0ii0i))) & (~ (comp_pat[5] ^ nl0ii0l))) & (~ (comp_pat[6] ^ nl0ii0O))) & (~ (comp_pat[7] ^ nl0iiii))),
		n11lO0i = (((~ comp_pat_size[0]) & (~ comp_pat_size[1])) & comp_pat_size[2]),
		n11lO0l = ((comp_pat_size[0] & comp_pat_size[1]) & (~ comp_pat_size[2])),
		n11lO0O = (((~ comp_pat_size[0]) & comp_pat_size[1]) & (~ comp_pat_size[2])),
		n11lO1i = ((((((((~ ((~ comp_pat[0]) ^ nl0i0OO)) & (~ ((~ comp_pat[1]) ^ nl0ii1i))) & (~ ((~ comp_pat[2]) ^ nl0ii1l))) & (~ ((~ comp_pat[3]) ^ nl0ii1O))) & (~ ((~ comp_pat[4]) ^ nl0ii0i))) & (~ ((~ comp_pat[5]) ^ nl0ii0l))) & (~ ((~ comp_pat[6]) ^ nl0ii0O))) & (~ ((~ comp_pat[7]) ^ nl0iiii))),
		n11lO1l = (((~ comp_pat_size[0]) & comp_pat_size[1]) & comp_pat_size[2]),
		n11lO1O = ((comp_pat_size[0] & (~ comp_pat_size[1])) & comp_pat_size[2]),
		n11lOii = ((comp_pat_size[0] & (~ comp_pat_size[1])) & (~ comp_pat_size[2])),
		n11lOil = (((~ comp_pat_size[0]) & (~ comp_pat_size[1])) & (~ comp_pat_size[2])),
		n11lOiO = (((((((((wire_nli0i1i_o | (~ n11O01i)) | (~ n11O1OO)) | (~ n11O1Oi)) | (~ n11O1ll)) | (~ n11O1iO)) | (~ n11O1ii)) | (~ n11O10l)) | (~ n11O11O)) | (~ n11O11i)),
		n11lOli = (((((((((wire_nli0i1i_o | (~ n11O01l)) | (~ n11O1OO)) | (~ n11O1Ol)) | (~ n11O1ll)) | (~ n11O1li)) | (~ n11O1ii)) | (~ n11O10O)) | (~ n11O11O)) | (~ n11O11l)),
		n11lOll = (((((((((~ n11O1OO) | (~ n11O1Ol)) | (~ n11O1Oi)) | (~ n11O1lO)) | (~ n11O1ii)) | (~ n11O10O)) | (~ n11O10l)) | (~ n11O10i)) | (~ n11lOOl)),
		n11lOlO = (((((((((~ n11O1ll) | (~ n11O1li)) | (~ n11O1iO)) | (~ n11O1il)) | (~ n11O1ii)) | (~ n11O10O)) | (~ n11O10l)) | (~ n11O10i)) | (~ n11lOOl)),
		n11lOOi = (((((~ n11O11O) | (~ n11O11l)) | (~ n11O11i)) | (~ n11lOOl)) | n11lOOO),
		n11lOOl = (((((((((((((((((((wire_nli0i1i_o | (~ n11O01l)) | (~ n11O01i)) | (~ ((((~ wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o))) | (~ n11O1OO)) | (~ n11O1Ol)) | (~ n11O1Oi)) | (~ n11O1lO)) | (~ n11O1ll)) | (~ n11O1li)) | (~ n11O1iO)) | (~ n11O1il)) | (~ n11O1ii)) | (~ n11O10O)) | (~ n11O10l)) | (~ n11O10i)) | (~ n11O11O)) | (~ n11O11l)) | (~ n11O11i)) | n11lOOO),
		n11lOOO = (((((((((((((((((((wire_nli0l0l_o & (~ wire_nli0l0i_o)) & (~ wire_nli0l1O_o)) & (~ wire_nli0l1l_o)) & (~ wire_nli0l1i_o)) & (~ wire_nli0iOO_o)) & (~ wire_nli0iOl_o)) & (~ wire_nli0iOi_o)) & (~ wire_nli0ilO_o)) & (~ wire_nli0ill_o)) & (~ wire_nli0ili_o)) & (~ wire_nli0iiO_o)) & (~ wire_nli0iil_o)) & (~ wire_nli0iii_o)) & (~ wire_nli0i0O_o)) & (~ wire_nli0i0l_o)) & (~ wire_nli0i0i_o)) & (~ wire_nli0i1O_o)) & (~ wire_nli0i1l_o)) & (~ wire_nli0i1i_o)),
		n11O00i = (n1010li & (((comp_pat_porn & n11O0il) | n11O0ii) & ((comp_pat_porn & n11O00O) | n11O00l))),
		n11O00l = ((((((((~ (comp_pat[16] ^ nllllOl)) & (~ (comp_pat[17] ^ nllllOO))) & (~ (comp_pat[18] ^ nlllO1i))) & (~ (comp_pat[19] ^ nlllO1l))) & (~ (comp_pat[20] ^ nlllO1O))) & (~ (comp_pat[21] ^ nlllO0i))) & (~ (comp_pat[22] ^ nlllO0l))) & (~ (comp_pat[23] ^ nlllO0O))),
		n11O00O = ((((((((~ ((~ comp_pat[16]) ^ nllllOl)) & (~ ((~ comp_pat[17]) ^ nllllOO))) & (~ ((~ comp_pat[18]) ^ nlllO1i))) & (~ ((~ comp_pat[19]) ^ nlllO1l))) & (~ ((~ comp_pat[20]) ^ nlllO1O))) & (~ ((~ comp_pat[21]) ^ nlllO0i))) & (~ ((~ comp_pat[22]) ^ nlllO0l))) & (~ ((~ comp_pat[23]) ^ nlllO0O))),
		n11O01i = (((~ wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O01l = ((~ wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O01O = (((((((((((((((n10100i | n1011Ol) | n1011iO) | n10110i) | n11OOOl) | n11OOiO) | n11OO0i) | n11OlOl) | n11OliO) | n11Ol0i) | n11OiOl) | n11OiiO) | n11Oi0i) | n11O0Ol) | n11O0iO) | n11O00i),
		n11O0ii = ((((((((~ (comp_pat[24] ^ nlllOii)) & (~ (comp_pat[25] ^ nlllOil))) & (~ (comp_pat[26] ^ nlllOiO))) & (~ (comp_pat[27] ^ nlllOli))) & (~ (comp_pat[28] ^ nlllOll))) & (~ (comp_pat[29] ^ nlllOlO))) & (~ (comp_pat[30] ^ nlllOOi))) & (~ (comp_pat[31] ^ nlllOOl))),
		n11O0il = ((((((((~ ((~ comp_pat[24]) ^ nlllOii)) & (~ ((~ comp_pat[25]) ^ nlllOil))) & (~ ((~ comp_pat[26]) ^ nlllOiO))) & (~ ((~ comp_pat[27]) ^ nlllOli))) & (~ ((~ comp_pat[28]) ^ nlllOll))) & (~ ((~ comp_pat[29]) ^ nlllOlO))) & (~ ((~ comp_pat[30]) ^ nlllOOi))) & (~ ((~ comp_pat[31]) ^ nlllOOl))),
		n11O0iO = (n1010Oi & (((comp_pat_porn & n11O0Oi) | n11O0lO) & ((comp_pat_porn & n11O0ll) | n11O0li))),
		n11O0li = ((((((((~ (comp_pat[16] ^ nlllliO)) & (~ (comp_pat[17] ^ nllllOl))) & (~ (comp_pat[18] ^ nllllOO))) & (~ (comp_pat[19] ^ nlllO1i))) & (~ (comp_pat[20] ^ nlllO1l))) & (~ (comp_pat[21] ^ nlllO1O))) & (~ (comp_pat[22] ^ nlllO0i))) & (~ (comp_pat[23] ^ nlllO0l))),
		n11O0ll = ((((((((~ ((~ comp_pat[16]) ^ nlllliO)) & (~ ((~ comp_pat[17]) ^ nllllOl))) & (~ ((~ comp_pat[18]) ^ nllllOO))) & (~ ((~ comp_pat[19]) ^ nlllO1i))) & (~ ((~ comp_pat[20]) ^ nlllO1l))) & (~ ((~ comp_pat[21]) ^ nlllO1O))) & (~ ((~ comp_pat[22]) ^ nlllO0i))) & (~ ((~ comp_pat[23]) ^ nlllO0l))),
		n11O0lO = ((((((((~ (comp_pat[24] ^ nlllO0O)) & (~ (comp_pat[25] ^ nlllOii))) & (~ (comp_pat[26] ^ nlllOil))) & (~ (comp_pat[27] ^ nlllOiO))) & (~ (comp_pat[28] ^ nlllOli))) & (~ (comp_pat[29] ^ nlllOll))) & (~ (comp_pat[30] ^ nlllOlO))) & (~ (comp_pat[31] ^ nlllOOi))),
		n11O0Oi = ((((((((~ ((~ comp_pat[24]) ^ nlllO0O)) & (~ ((~ comp_pat[25]) ^ nlllOii))) & (~ ((~ comp_pat[26]) ^ nlllOil))) & (~ ((~ comp_pat[27]) ^ nlllOiO))) & (~ ((~ comp_pat[28]) ^ nlllOli))) & (~ ((~ comp_pat[29]) ^ nlllOll))) & (~ ((~ comp_pat[30]) ^ nlllOlO))) & (~ ((~ comp_pat[31]) ^ nlllOOi))),
		n11O0Ol = (n101i1i & (((comp_pat_porn & n11Oi1O) | n11Oi1l) & ((comp_pat_porn & n11Oi1i) | n11O0OO))),
		n11O0OO = ((((((((~ (comp_pat[16] ^ nllllil)) & (~ (comp_pat[17] ^ nlllliO))) & (~ (comp_pat[18] ^ nllllOl))) & (~ (comp_pat[19] ^ nllllOO))) & (~ (comp_pat[20] ^ nlllO1i))) & (~ (comp_pat[21] ^ nlllO1l))) & (~ (comp_pat[22] ^ nlllO1O))) & (~ (comp_pat[23] ^ nlllO0i))),
		n11O10i = ((((((((((((((((~ wire_nli0l1i_o) | wire_nli0iOO_o) | wire_nli0iOl_o) | wire_nli0iOi_o) | wire_nli0ilO_o) | wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O10l = (((((((((((((((~ wire_nli0iOO_o) | wire_nli0iOl_o) | wire_nli0iOi_o) | wire_nli0ilO_o) | wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O10O = ((((((((((((((~ wire_nli0iOl_o) | wire_nli0iOi_o) | wire_nli0ilO_o) | wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O11i = (((((((((((((((((((~ wire_nli0l0i_o) | wire_nli0l1O_o) | wire_nli0l1l_o) | wire_nli0l1i_o) | wire_nli0iOO_o) | wire_nli0iOl_o) | wire_nli0iOi_o) | wire_nli0ilO_o) | wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O11l = ((((((((((((((((((~ wire_nli0l1O_o) | wire_nli0l1l_o) | wire_nli0l1i_o) | wire_nli0iOO_o) | wire_nli0iOl_o) | wire_nli0iOi_o) | wire_nli0ilO_o) | wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O11O = (((((((((((((((((~ wire_nli0l1l_o) | wire_nli0l1i_o) | wire_nli0iOO_o) | wire_nli0iOl_o) | wire_nli0iOi_o) | wire_nli0ilO_o) | wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1ii = (((((((((((((~ wire_nli0iOi_o) | wire_nli0ilO_o) | wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1il = ((((((((((((~ wire_nli0ilO_o) | wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1iO = (((((((((((~ wire_nli0ill_o) | wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1li = ((((((((((~ wire_nli0ili_o) | wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1ll = (((((((((~ wire_nli0iiO_o) | wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1lO = ((((((((~ wire_nli0iil_o) | wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1Oi = (((((((~ wire_nli0iii_o) | wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1Ol = ((((((~ wire_nli0i0O_o) | wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11O1OO = (((((~ wire_nli0i0l_o) | wire_nli0i0i_o) | wire_nli0i1O_o) | wire_nli0i1l_o) | wire_nli0i1i_o),
		n11Oi0i = (n101i0i & (((comp_pat_porn & n11Oiil) | n11Oiii) & ((comp_pat_porn & n11Oi0O) | n11Oi0l))),
		n11Oi0l = ((((((((~ (comp_pat[16] ^ nllllii)) & (~ (comp_pat[17] ^ nllllil))) & (~ (comp_pat[18] ^ nlllliO))) & (~ (comp_pat[19] ^ nllllOl))) & (~ (comp_pat[20] ^ nllllOO))) & (~ (comp_pat[21] ^ nlllO1i))) & (~ (comp_pat[22] ^ nlllO1l))) & (~ (comp_pat[23] ^ nlllO1O))),
		n11Oi0O = ((((((((~ ((~ comp_pat[16]) ^ nllllii)) & (~ ((~ comp_pat[17]) ^ nllllil))) & (~ ((~ comp_pat[18]) ^ nlllliO))) & (~ ((~ comp_pat[19]) ^ nllllOl))) & (~ ((~ comp_pat[20]) ^ nllllOO))) & (~ ((~ comp_pat[21]) ^ nlllO1i))) & (~ ((~ comp_pat[22]) ^ nlllO1l))) & (~ ((~ comp_pat[23]) ^ nlllO1O))),
		n11Oi1i = ((((((((~ ((~ comp_pat[16]) ^ nllllil)) & (~ ((~ comp_pat[17]) ^ nlllliO))) & (~ ((~ comp_pat[18]) ^ nllllOl))) & (~ ((~ comp_pat[19]) ^ nllllOO))) & (~ ((~ comp_pat[20]) ^ nlllO1i))) & (~ ((~ comp_pat[21]) ^ nlllO1l))) & (~ ((~ comp_pat[22]) ^ nlllO1O))) & (~ ((~ comp_pat[23]) ^ nlllO0i))),
		n11Oi1l = ((((((((~ (comp_pat[24] ^ nlllO0l)) & (~ (comp_pat[25] ^ nlllO0O))) & (~ (comp_pat[26] ^ nlllOii))) & (~ (comp_pat[27] ^ nlllOil))) & (~ (comp_pat[28] ^ nlllOiO))) & (~ (comp_pat[29] ^ nlllOli))) & (~ (comp_pat[30] ^ nlllOll))) & (~ (comp_pat[31] ^ nlllOlO))),
		n11Oi1O = ((((((((~ ((~ comp_pat[24]) ^ nlllO0l)) & (~ ((~ comp_pat[25]) ^ nlllO0O))) & (~ ((~ comp_pat[26]) ^ nlllOii))) & (~ ((~ comp_pat[27]) ^ nlllOil))) & (~ ((~ comp_pat[28]) ^ nlllOiO))) & (~ ((~ comp_pat[29]) ^ nlllOli))) & (~ ((~ comp_pat[30]) ^ nlllOll))) & (~ ((~ comp_pat[31]) ^ nlllOlO))),
		n11Oiii = ((((((((~ (comp_pat[24] ^ nlllO0i)) & (~ (comp_pat[25] ^ nlllO0l))) & (~ (comp_pat[26] ^ nlllO0O))) & (~ (comp_pat[27] ^ nlllOii))) & (~ (comp_pat[28] ^ nlllOil))) & (~ (comp_pat[29] ^ nlllOiO))) & (~ (comp_pat[30] ^ nlllOli))) & (~ (comp_pat[31] ^ nlllOll))),
		n11Oiil = ((((((((~ ((~ comp_pat[24]) ^ nlllO0i)) & (~ ((~ comp_pat[25]) ^ nlllO0l))) & (~ ((~ comp_pat[26]) ^ nlllO0O))) & (~ ((~ comp_pat[27]) ^ nlllOii))) & (~ ((~ comp_pat[28]) ^ nlllOil))) & (~ ((~ comp_pat[29]) ^ nlllOiO))) & (~ ((~ comp_pat[30]) ^ nlllOli))) & (~ ((~ comp_pat[31]) ^ nlllOll))),
		n11OiiO = (n101iii & (((comp_pat_porn & n11OiOi) | n11OilO) & ((comp_pat_porn & n11Oill) | n11Oili))),
		n11Oili = ((((((((~ (comp_pat[16] ^ nllll0O)) & (~ (comp_pat[17] ^ nllllii))) & (~ (comp_pat[18] ^ nllllil))) & (~ (comp_pat[19] ^ nlllliO))) & (~ (comp_pat[20] ^ nllllOl))) & (~ (comp_pat[21] ^ nllllOO))) & (~ (comp_pat[22] ^ nlllO1i))) & (~ (comp_pat[23] ^ nlllO1l))),
		n11Oill = ((((((((~ ((~ comp_pat[16]) ^ nllll0O)) & (~ ((~ comp_pat[17]) ^ nllllii))) & (~ ((~ comp_pat[18]) ^ nllllil))) & (~ ((~ comp_pat[19]) ^ nlllliO))) & (~ ((~ comp_pat[20]) ^ nllllOl))) & (~ ((~ comp_pat[21]) ^ nllllOO))) & (~ ((~ comp_pat[22]) ^ nlllO1i))) & (~ ((~ comp_pat[23]) ^ nlllO1l))),
		n11OilO = ((((((((~ (comp_pat[24] ^ nlllO1O)) & (~ (comp_pat[25] ^ nlllO0i))) & (~ (comp_pat[26] ^ nlllO0l))) & (~ (comp_pat[27] ^ nlllO0O))) & (~ (comp_pat[28] ^ nlllOii))) & (~ (comp_pat[29] ^ nlllOil))) & (~ (comp_pat[30] ^ nlllOiO))) & (~ (comp_pat[31] ^ nlllOli))),
		n11OiOi = ((((((((~ ((~ comp_pat[24]) ^ nlllO1O)) & (~ ((~ comp_pat[25]) ^ nlllO0i))) & (~ ((~ comp_pat[26]) ^ nlllO0l))) & (~ ((~ comp_pat[27]) ^ nlllO0O))) & (~ ((~ comp_pat[28]) ^ nlllOii))) & (~ ((~ comp_pat[29]) ^ nlllOil))) & (~ ((~ comp_pat[30]) ^ nlllOiO))) & (~ ((~ comp_pat[31]) ^ nlllOli))),
		n11OiOl = (n101ili & (((comp_pat_porn & n11Ol1O) | n11Ol1l) & ((comp_pat_porn & n11Ol1i) | n11OiOO))),
		n11OiOO = ((((((((~ (comp_pat[16] ^ nllll0l)) & (~ (comp_pat[17] ^ nllll0O))) & (~ (comp_pat[18] ^ nllllii))) & (~ (comp_pat[19] ^ nllllil))) & (~ (comp_pat[20] ^ nlllliO))) & (~ (comp_pat[21] ^ nllllOl))) & (~ (comp_pat[22] ^ nllllOO))) & (~ (comp_pat[23] ^ nlllO1i))),
		n11Ol0i = (n101iOi & (((comp_pat_porn & n11Olil) | n11Olii) & ((comp_pat_porn & n11Ol0O) | n11Ol0l))),
		n11Ol0l = ((((((((~ (comp_pat[16] ^ nllll0i)) & (~ (comp_pat[17] ^ nllll0l))) & (~ (comp_pat[18] ^ nllll0O))) & (~ (comp_pat[19] ^ nllllii))) & (~ (comp_pat[20] ^ nllllil))) & (~ (comp_pat[21] ^ nlllliO))) & (~ (comp_pat[22] ^ nllllOl))) & (~ (comp_pat[23] ^ nllllOO))),
		n11Ol0O = ((((((((~ ((~ comp_pat[16]) ^ nllll0i)) & (~ ((~ comp_pat[17]) ^ nllll0l))) & (~ ((~ comp_pat[18]) ^ nllll0O))) & (~ ((~ comp_pat[19]) ^ nllllii))) & (~ ((~ comp_pat[20]) ^ nllllil))) & (~ ((~ comp_pat[21]) ^ nlllliO))) & (~ ((~ comp_pat[22]) ^ nllllOl))) & (~ ((~ comp_pat[23]) ^ nllllOO))),
		n11Ol1i = ((((((((~ ((~ comp_pat[16]) ^ nllll0l)) & (~ ((~ comp_pat[17]) ^ nllll0O))) & (~ ((~ comp_pat[18]) ^ nllllii))) & (~ ((~ comp_pat[19]) ^ nllllil))) & (~ ((~ comp_pat[20]) ^ nlllliO))) & (~ ((~ comp_pat[21]) ^ nllllOl))) & (~ ((~ comp_pat[22]) ^ nllllOO))) & (~ ((~ comp_pat[23]) ^ nlllO1i))),
		n11Ol1l = ((((((((~ (comp_pat[24] ^ nlllO1l)) & (~ (comp_pat[25] ^ nlllO1O))) & (~ (comp_pat[26] ^ nlllO0i))) & (~ (comp_pat[27] ^ nlllO0l))) & (~ (comp_pat[28] ^ nlllO0O))) & (~ (comp_pat[29] ^ nlllOii))) & (~ (comp_pat[30] ^ nlllOil))) & (~ (comp_pat[31] ^ nlllOiO))),
		n11Ol1O = ((((((((~ ((~ comp_pat[24]) ^ nlllO1l)) & (~ ((~ comp_pat[25]) ^ nlllO1O))) & (~ ((~ comp_pat[26]) ^ nlllO0i))) & (~ ((~ comp_pat[27]) ^ nlllO0l))) & (~ ((~ comp_pat[28]) ^ nlllO0O))) & (~ ((~ comp_pat[29]) ^ nlllOii))) & (~ ((~ comp_pat[30]) ^ nlllOil))) & (~ ((~ comp_pat[31]) ^ nlllOiO))),
		n11Olii = ((((((((~ (comp_pat[24] ^ nlllO1i)) & (~ (comp_pat[25] ^ nlllO1l))) & (~ (comp_pat[26] ^ nlllO1O))) & (~ (comp_pat[27] ^ nlllO0i))) & (~ (comp_pat[28] ^ nlllO0l))) & (~ (comp_pat[29] ^ nlllO0O))) & (~ (comp_pat[30] ^ nlllOii))) & (~ (comp_pat[31] ^ nlllOil))),
		n11Olil = ((((((((~ ((~ comp_pat[24]) ^ nlllO1i)) & (~ ((~ comp_pat[25]) ^ nlllO1l))) & (~ ((~ comp_pat[26]) ^ nlllO1O))) & (~ ((~ comp_pat[27]) ^ nlllO0i))) & (~ ((~ comp_pat[28]) ^ nlllO0l))) & (~ ((~ comp_pat[29]) ^ nlllO0O))) & (~ ((~ comp_pat[30]) ^ nlllOii))) & (~ ((~ comp_pat[31]) ^ nlllOil))),
		n11OliO = (n101l1i & (((comp_pat_porn & n11OlOi) | n11OllO) & ((comp_pat_porn & n11Olll) | n11Olli))),
		n11Olli = ((((((((~ (comp_pat[16] ^ nllll1O)) & (~ (comp_pat[17] ^ nllll0i))) & (~ (comp_pat[18] ^ nllll0l))) & (~ (comp_pat[19] ^ nllll0O))) & (~ (comp_pat[20] ^ nllllii))) & (~ (comp_pat[21] ^ nllllil))) & (~ (comp_pat[22] ^ nlllliO))) & (~ (comp_pat[23] ^ nllllOl))),
		n11Olll = ((((((((~ ((~ comp_pat[16]) ^ nllll1O)) & (~ ((~ comp_pat[17]) ^ nllll0i))) & (~ ((~ comp_pat[18]) ^ nllll0l))) & (~ ((~ comp_pat[19]) ^ nllll0O))) & (~ ((~ comp_pat[20]) ^ nllllii))) & (~ ((~ comp_pat[21]) ^ nllllil))) & (~ ((~ comp_pat[22]) ^ nlllliO))) & (~ ((~ comp_pat[23]) ^ nllllOl))),
		n11OllO = ((((((((~ (comp_pat[24] ^ nllllOO)) & (~ (comp_pat[25] ^ nlllO1i))) & (~ (comp_pat[26] ^ nlllO1l))) & (~ (comp_pat[27] ^ nlllO1O))) & (~ (comp_pat[28] ^ nlllO0i))) & (~ (comp_pat[29] ^ nlllO0l))) & (~ (comp_pat[30] ^ nlllO0O))) & (~ (comp_pat[31] ^ nlllOii))),
		n11OlOi = ((((((((~ ((~ comp_pat[24]) ^ nllllOO)) & (~ ((~ comp_pat[25]) ^ nlllO1i))) & (~ ((~ comp_pat[26]) ^ nlllO1l))) & (~ ((~ comp_pat[27]) ^ nlllO1O))) & (~ ((~ comp_pat[28]) ^ nlllO0i))) & (~ ((~ comp_pat[29]) ^ nlllO0l))) & (~ ((~ comp_pat[30]) ^ nlllO0O))) & (~ ((~ comp_pat[31]) ^ nlllOii))),
		n11OlOl = (n101l0i & (((comp_pat_porn & n11OO1O) | n11OO1l) & ((comp_pat_porn & n11OO1i) | n11OlOO))),
		n11OlOO = ((((((((~ (comp_pat[16] ^ nllll1l)) & (~ (comp_pat[17] ^ nllll1O))) & (~ (comp_pat[18] ^ nllll0i))) & (~ (comp_pat[19] ^ nllll0l))) & (~ (comp_pat[20] ^ nllll0O))) & (~ (comp_pat[21] ^ nllllii))) & (~ (comp_pat[22] ^ nllllil))) & (~ (comp_pat[23] ^ nlllliO))),
		n11OO0i = (n101lii & (((comp_pat_porn & n11OOil) | n11OOii) & ((comp_pat_porn & n11OO0O) | n11OO0l))),
		n11OO0l = ((((((((~ (comp_pat[16] ^ nllll1i)) & (~ (comp_pat[17] ^ nllll1l))) & (~ (comp_pat[18] ^ nllll1O))) & (~ (comp_pat[19] ^ nllll0i))) & (~ (comp_pat[20] ^ nllll0l))) & (~ (comp_pat[21] ^ nllll0O))) & (~ (comp_pat[22] ^ nllllii))) & (~ (comp_pat[23] ^ nllllil))),
		n11OO0O = ((((((((~ ((~ comp_pat[16]) ^ nllll1i)) & (~ ((~ comp_pat[17]) ^ nllll1l))) & (~ ((~ comp_pat[18]) ^ nllll1O))) & (~ ((~ comp_pat[19]) ^ nllll0i))) & (~ ((~ comp_pat[20]) ^ nllll0l))) & (~ ((~ comp_pat[21]) ^ nllll0O))) & (~ ((~ comp_pat[22]) ^ nllllii))) & (~ ((~ comp_pat[23]) ^ nllllil))),
		n11OO1i = ((((((((~ ((~ comp_pat[16]) ^ nllll1l)) & (~ ((~ comp_pat[17]) ^ nllll1O))) & (~ ((~ comp_pat[18]) ^ nllll0i))) & (~ ((~ comp_pat[19]) ^ nllll0l))) & (~ ((~ comp_pat[20]) ^ nllll0O))) & (~ ((~ comp_pat[21]) ^ nllllii))) & (~ ((~ comp_pat[22]) ^ nllllil))) & (~ ((~ comp_pat[23]) ^ nlllliO))),
		n11OO1l = ((((((((~ (comp_pat[24] ^ nllllOl)) & (~ (comp_pat[25] ^ nllllOO))) & (~ (comp_pat[26] ^ nlllO1i))) & (~ (comp_pat[27] ^ nlllO1l))) & (~ (comp_pat[28] ^ nlllO1O))) & (~ (comp_pat[29] ^ nlllO0i))) & (~ (comp_pat[30] ^ nlllO0l))) & (~ (comp_pat[31] ^ nlllO0O))),
		n11OO1O = ((((((((~ ((~ comp_pat[24]) ^ nllllOl)) & (~ ((~ comp_pat[25]) ^ nllllOO))) & (~ ((~ comp_pat[26]) ^ nlllO1i))) & (~ ((~ comp_pat[27]) ^ nlllO1l))) & (~ ((~ comp_pat[28]) ^ nlllO1O))) & (~ ((~ comp_pat[29]) ^ nlllO0i))) & (~ ((~ comp_pat[30]) ^ nlllO0l))) & (~ ((~ comp_pat[31]) ^ nlllO0O))),
		n11OOii = ((((((((~ (comp_pat[24] ^ nlllliO)) & (~ (comp_pat[25] ^ nllllOl))) & (~ (comp_pat[26] ^ nllllOO))) & (~ (comp_pat[27] ^ nlllO1i))) & (~ (comp_pat[28] ^ nlllO1l))) & (~ (comp_pat[29] ^ nlllO1O))) & (~ (comp_pat[30] ^ nlllO0i))) & (~ (comp_pat[31] ^ nlllO0l))),
		n11OOil = ((((((((~ ((~ comp_pat[24]) ^ nlllliO)) & (~ ((~ comp_pat[25]) ^ nllllOl))) & (~ ((~ comp_pat[26]) ^ nllllOO))) & (~ ((~ comp_pat[27]) ^ nlllO1i))) & (~ ((~ comp_pat[28]) ^ nlllO1l))) & (~ ((~ comp_pat[29]) ^ nlllO1O))) & (~ ((~ comp_pat[30]) ^ nlllO0i))) & (~ ((~ comp_pat[31]) ^ nlllO0l))),
		n11OOiO = (n101lli & (((comp_pat_porn & n11OOOi) | n11OOlO) & ((comp_pat_porn & n11OOll) | n11OOli))),
		n11OOli = ((((((((~ (comp_pat[16] ^ nllliOO)) & (~ (comp_pat[17] ^ nllll1i))) & (~ (comp_pat[18] ^ nllll1l))) & (~ (comp_pat[19] ^ nllll1O))) & (~ (comp_pat[20] ^ nllll0i))) & (~ (comp_pat[21] ^ nllll0l))) & (~ (comp_pat[22] ^ nllll0O))) & (~ (comp_pat[23] ^ nllllii))),
		n11OOll = ((((((((~ ((~ comp_pat[16]) ^ nllliOO)) & (~ ((~ comp_pat[17]) ^ nllll1i))) & (~ ((~ comp_pat[18]) ^ nllll1l))) & (~ ((~ comp_pat[19]) ^ nllll1O))) & (~ ((~ comp_pat[20]) ^ nllll0i))) & (~ ((~ comp_pat[21]) ^ nllll0l))) & (~ ((~ comp_pat[22]) ^ nllll0O))) & (~ ((~ comp_pat[23]) ^ nllllii))),
		n11OOlO = ((((((((~ (comp_pat[24] ^ nllllil)) & (~ (comp_pat[25] ^ nlllliO))) & (~ (comp_pat[26] ^ nllllOl))) & (~ (comp_pat[27] ^ nllllOO))) & (~ (comp_pat[28] ^ nlllO1i))) & (~ (comp_pat[29] ^ nlllO1l))) & (~ (comp_pat[30] ^ nlllO1O))) & (~ (comp_pat[31] ^ nlllO0i))),
		n11OOOi = ((((((((~ ((~ comp_pat[24]) ^ nllllil)) & (~ ((~ comp_pat[25]) ^ nlllliO))) & (~ ((~ comp_pat[26]) ^ nllllOl))) & (~ ((~ comp_pat[27]) ^ nllllOO))) & (~ ((~ comp_pat[28]) ^ nlllO1i))) & (~ ((~ comp_pat[29]) ^ nlllO1l))) & (~ ((~ comp_pat[30]) ^ nlllO1O))) & (~ ((~ comp_pat[31]) ^ nlllO0i))),
		n11OOOl = (n101lOi & (((comp_pat_porn & n10111O) | n10111l) & ((comp_pat_porn & n10111i) | n11OOOO))),
		n11OOOO = ((((((((~ (comp_pat[16] ^ nllliOl)) & (~ (comp_pat[17] ^ nllliOO))) & (~ (comp_pat[18] ^ nllll1i))) & (~ (comp_pat[19] ^ nllll1l))) & (~ (comp_pat[20] ^ nllll1O))) & (~ (comp_pat[21] ^ nllll0i))) & (~ (comp_pat[22] ^ nllll0l))) & (~ (comp_pat[23] ^ nllll0O))),
		n1i000i = ((~ wire_nl1l0l_o) & wire_nl1l0i_o),
		n1i000l = (wire_nl1l0O_dataout ^ wire_nl1l0i_o),
		n1i000O = (wire_nl1iOl_o & wire_nl1iOi_o),
		n1i001i = (wire_nl1l0l_o & wire_nl1l0i_o),
		n1i001l = ((~ wire_nl1l0l_o) & (~ wire_nl1l0i_o)),
		n1i001O = (wire_nl1l0l_o & (~ wire_nl1l0i_o)),
		n1i00ii = ((~ wire_nl1iOl_o) & (~ wire_nl1iOi_o)),
		n1i00il = (wire_nl1iOl_o & (~ wire_nl1iOi_o)),
		n1i00iO = ((~ wire_nl1iOl_o) & wire_nl1iOi_o),
		n1i00li = (((((~ wire_nl1lii_dataout) & (wire_nl1l0O_dataout & n1i001i)) | (wire_nl1lii_dataout & ((~ wire_nl1l0O_dataout) & n1i001i))) | (wire_nl1lii_dataout & (wire_nl1l0O_dataout & ((~ wire_nl1l0l_o) & wire_nl1l0i_o)))) | (wire_nl1lii_dataout & (wire_nl1l0O_dataout & (wire_nl1l0l_o & (~ wire_nl1l0i_o))))),
		n1i00ll = (((~ wire_n11i0l_dataout) & n1i01Oi) | (wire_n11i0l_dataout & n1iliOO)),
		n1i00lO = (wire_nl1lii_dataout & (wire_nl1l0O_dataout & (wire_nl1l0l_o & wire_nl1l0i_o))),
		n1i00Oi = (n1i01Ol & n1iliOi),
		n1i00Ol = ((n1i01Ol & n1i01Oi) | (n1i01OO & n1i01Oi)),
		n1i00OO = (n1i01Ol & n1iliOO),
		n1i010i = ((((~ (rosnumber[0] ^ nlOiOil)) & (~ (rosnumber[1] ^ nlOiOiO))) & (~ (rosnumber[2] ^ nlOiOli))) & (~ (rosnumber[3] ^ nlOiOll))),
		n1i010l = (((rosnumber[0] | rosnumber[1]) | rosnumber[2]) | rosnumber[3]),
		n1i010O = ((~ niO0Oi) & (~ niO1il)),
		n1i011i = ((~ n1i010l) & ((~ n1i011l) & niO11l)),
		n1i011l = (((((((((knumber[0] | knumber[1]) | knumber[2]) | knumber[3]) | knumber[4]) | knumber[5]) | knumber[6]) | knumber[7]) | knumber[8]) | knumber[9]),
		n1i011O = ((n1i010l & (((rkchar & niO1il) | ((~ rkchar) & niO11l)) & (~ n1i010i))) | niO0Oi),
		n1i01ii = (wire_nl1iOl_o & wire_nl1iOi_o),
		n1i01il = ((~ wire_nl1iOl_o) & (~ wire_nl1iOi_o)),
		n1i01iO = (wire_nl1iOl_o & (~ wire_nl1iOi_o)),
		n1i01li = ((~ wire_nl1iOl_o) & wire_nl1iOi_o),
		n1i01ll = (n1iliOl & n1i01Oi),
		n1i01lO = ((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & ((~ wire_nl1iOl_o) & (~ wire_nl1iOi_o)))),
		n1i01Oi = (wire_nl1l1O_o & wire_nl1l1l_o),
		n1i01Ol = (wire_nl1l1i_o & (wire_nl1iOO_o & (wire_nl1iOl_o & wire_nl1iOi_o))),
		n1i01OO = (((((~ wire_nl1l1i_o) & (wire_nl1iOO_o & n1i01ii)) | (wire_nl1l1i_o & ((~ wire_nl1iOO_o) & n1i01ii))) | (wire_nl1l1i_o & (wire_nl1iOO_o & ((~ wire_nl1iOl_o) & wire_nl1iOi_o)))) | (wire_nl1l1i_o & (wire_nl1iOO_o & (wire_nl1iOl_o & (~ wire_nl1iOi_o))))),
		n1i0i0i = (wire_nl1l0l_o & wire_nl1l0i_o),
		n1i0i0l = ((wire_nl1l1O_o & (wire_nl1l1l_o & (wire_nl1l1i_o & wire_nl1iOO_o))) | ((~ wire_nl1l1O_o) & ((~ wire_nl1l1l_o) & ((~ wire_nl1l1i_o) & (~ wire_nl1iOO_o))))),
		n1i0i0O = ((~ wire_nl1l1O_o) & wire_nl1l1l_o),
		n1i0i1i = ((~ wire_nl1lii_dataout) & (~ wire_nl1l0O_dataout)),
		n1i0i1l = (((((((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & (wire_nl1iOl_o & wire_nl1iOi_o))) | ((~ wire_nl1l1i_o) & (wire_nl1iOO_o & n1i00iO))) | ((~ wire_nl1l1i_o) & (wire_nl1iOO_o & n1i00il))) | (wire_nl1l1i_o & ((~ wire_nl1iOO_o) & n1i00iO))) | (wire_nl1l1i_o & ((~ wire_nl1iOO_o) & n1i00il))) | (wire_nl1l1i_o & (wire_nl1iOO_o & ((~ wire_nl1iOl_o) & (~ wire_nl1iOi_o))))),
		n1i0i1O = ((~ wire_nl1l0l_o) & (~ wire_nl1l0i_o)),
		n1i0iii = (wire_nl1l1O_o & (~ wire_nl1l1l_o)),
		n1i0iil = (((((~ wire_nl1l1i_o) & (wire_nl1iOO_o & n1i000O)) | (wire_nl1l1i_o & ((~ wire_nl1iOO_o) & n1i000O))) | (wire_nl1l1i_o & (wire_nl1iOO_o & ((~ wire_nl1iOl_o) & wire_nl1iOi_o)))) | (wire_nl1l1i_o & (wire_nl1iOO_o & (wire_nl1iOl_o & (~ wire_nl1iOi_o))))),
		n1i0iiO = (((((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & ((~ wire_nl1iOl_o) & wire_nl1iOi_o))) | ((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & (wire_nl1iOl_o & (~ wire_nl1iOi_o))))) | ((~ wire_nl1l1i_o) & (wire_nl1iOO_o & n1i00ii))) | (wire_nl1l1i_o & ((~ wire_nl1iOO_o) & n1i00ii))),
		n1i0ili = ((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & ((~ wire_nl1iOl_o) & (~ wire_nl1iOi_o)))),
		n1i0ill = (wire_nl1l1i_o & (wire_nl1iOO_o & (wire_nl1iOl_o & wire_nl1iOi_o))),
		n1i0ilO = ((ib_invalid_code[0] & ((((~ wire_nl1l0l_o) & n1il0ll) & n1i000l) | ((wire_nl1l0l_o & n1il0li) & n1i000l))) | (ib_invalid_code[1] & ((wire_nl1l0O_dataout & (wire_nl1l0l_o & (n1il0ll & n1ili0i))) | ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & (n1il0li & n1ili0i)))))),
		n1i0iOi = (n01OlO | n011lO),
		n1i0iOl = (n01Oll | n01Oli),
		n1i0iOO = (n01OOl | n01OOi),
		n1i0l0i = ((~ n00lOl) & (~ n00lOi)),
		n1i0l0l = ((~ n00lOl) & n00lOi),
		n1i0l0O = (n011ll & n011li),
		n1i0l1i = ((((n0011i | n01OOO) | n01OOl) | n01OOi) | n01OlO),
		n1i0l1l = ((((n0011i | n01OOO) | n01Oll) | n01Oli) | n011lO),
		n1i0l1O = (n0011i | n01OOO),
		n1i0lii = ((~ n0i1Oi) & (~ n00lOi)),
		n1i0lil = ((~ n0i1Oi) & n00lOi),
		n1i0liO = ((((max_rlv_sel[0] | max_rlv_sel[1]) | max_rlv_sel[2]) | max_rlv_sel[3]) | max_rlv_sel[4]),
		n1i0lli = ((((((((~ wire_n001li_dataout) & (~ wire_n001iO_dataout)) & (~ wire_n001il_dataout)) & (~ wire_n001ii_dataout)) & (~ wire_n0010O_dataout)) & wire_n0010l_dataout) & (~ wire_n0010i_dataout)) & (~ wire_n0011O_dataout)),
		n1i0lll = ((((((((~ wire_n001li_dataout) & (~ wire_n001iO_dataout)) & (~ wire_n001il_dataout)) & (~ wire_n001ii_dataout)) & (~ wire_n0010O_dataout)) & wire_n0010l_dataout) & (~ wire_n0010i_dataout)) & wire_n0011O_dataout),
		n1i0llO = (((((((pmadwidth[0] | (~ nlli1i)) | (~ nll0OO)) | (~ nll0Ol)) | (~ nll0Oi)) | (~ nll0lO)) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0lOi = (((((((pmadwidth[0] | (~ nlli1l)) | (~ nlli1i)) | (~ nll0OO)) | (~ nll0Ol)) | (~ nll0Oi)) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0lOl = (((((((pmadwidth[0] | (~ nll0OO)) | (~ nll0Ol)) | (~ nll0Oi)) | (~ nll0lO)) | (~ nl0ill)) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0lOO = (((((((((~ pmadwidth[0]) | (~ nlli0i)) | (~ nlli1O)) | (~ nlli1l)) | (~ nlli1i)) | (~ nll0OO)) | (~ nll0Ol)) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0O0i = (((((((pmadwidth[0] | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0O0l = (((((((pmadwidth[0] | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0O0O = (((((((pmadwidth[0] | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | nl0ill) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0O1i = (((((((((~ pmadwidth[0]) | (~ nlli1O)) | (~ nlli1l)) | (~ nlli1i)) | (~ nll0OO)) | (~ nll0Ol)) | (~ nll0Oi)) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0O1l = (((((((((~ pmadwidth[0]) | (~ nlli1l)) | (~ nlli1i)) | (~ nll0OO)) | (~ nll0Ol)) | (~ nll0Oi)) | (~ nll0lO)) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0O1O = (((((((((~ pmadwidth[0]) | (~ nlli1i)) | (~ nll0OO)) | (~ nll0Ol)) | (~ nll0Oi)) | (~ nll0lO)) | (~ nl0ill)) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0Oii = (((((((((~ pmadwidth[0]) | nlli0i) | nlli1O) | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0Oil = (((((((((~ pmadwidth[0]) | nlli1O) | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0OiO = (((((((((~ pmadwidth[0]) | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0Oli = (((((((((~ pmadwidth[0]) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | nl0ill) | (~ wire_n00llO_dataout)) | (~ n000lO)),
		n1i0Oll = (((((~ n1ii10l) | (~ n1ii10i)) | (~ n1ii11l)) | (~ n1i0OOO)) | n1i0OlO),
		n1i0OlO = (((((((((nl0ill & (~ n1iil0l)) & (~ n1iiiOl)) & (~ n1iiiOi)) & (~ n1iiilO)) & (~ n1iiill)) & (~ n1iiili)) & (~ n1iiiiO)) & (~ n1iiiii)) & (~ n1iii0O)),
		n1i0OOi = ((((n1iii0O | (~ n1ii10i)) | (~ n1ii11O)) | (~ n1i0OOO)) | (~ n1i0OOl)),
		n1i0OOl = ((((((((n1iil0l | (~ n1iiiOl)) | n1iiiOi) | n1iiilO) | n1iiill) | n1iiili) | n1iiiiO) | n1iiiii) | n1iii0O),
		n1i0OOO = (((((((n1iil0l | (~ n1iiiOi)) | n1iiilO) | n1iiill) | n1iiili) | n1iiiiO) | n1iiiii) | n1iii0O),
		n1i100i = ((comp_pat_porn & n1i100O) | n1i100l),
		n1i100l = (((((((~ (comp_pat[0] ^ nlll0il)) & (~ (comp_pat[1] ^ nlll0iO))) & (~ (comp_pat[2] ^ nlll0li))) & (~ (comp_pat[3] ^ nlll0ll))) & (~ (comp_pat[4] ^ nlll0lO))) & (~ (comp_pat[5] ^ nlll0Oi))) & (~ (comp_pat[6] ^ nlll0Ol))),
		n1i100O = (((((((~ ((~ comp_pat[0]) ^ nlll0il)) & (~ ((~ comp_pat[1]) ^ nlll0iO))) & (~ ((~ comp_pat[2]) ^ nlll0li))) & (~ ((~ comp_pat[3]) ^ nlll0ll))) & (~ ((~ comp_pat[4]) ^ nlll0lO))) & (~ ((~ comp_pat[5]) ^ nlll0Oi))) & (~ ((~ comp_pat[6]) ^ nlll0Ol))),
		n1i101i = ((comp_pat_porn & n1i101O) | n1i101l),
		n1i101l = (((((((~ (comp_pat[0] ^ nlll0iO)) & (~ (comp_pat[1] ^ nlll0li))) & (~ (comp_pat[2] ^ nlll0ll))) & (~ (comp_pat[3] ^ nlll0lO))) & (~ (comp_pat[4] ^ nlll0Oi))) & (~ (comp_pat[5] ^ nlll0Ol))) & (~ (comp_pat[6] ^ nlll0OO))),
		n1i101O = (((((((~ ((~ comp_pat[0]) ^ nlll0iO)) & (~ ((~ comp_pat[1]) ^ nlll0li))) & (~ ((~ comp_pat[2]) ^ nlll0ll))) & (~ ((~ comp_pat[3]) ^ nlll0lO))) & (~ ((~ comp_pat[4]) ^ nlll0Oi))) & (~ ((~ comp_pat[5]) ^ nlll0Ol))) & (~ ((~ comp_pat[6]) ^ nlll0OO))),
		n1i10ii = ((comp_pat_porn & n1i10iO) | n1i10il),
		n1i10il = (((((((~ (comp_pat[0] ^ nlll0ii)) & (~ (comp_pat[1] ^ nlll0il))) & (~ (comp_pat[2] ^ nlll0iO))) & (~ (comp_pat[3] ^ nlll0li))) & (~ (comp_pat[4] ^ nlll0ll))) & (~ (comp_pat[5] ^ nlll0lO))) & (~ (comp_pat[6] ^ nlll0Oi))),
		n1i10iO = (((((((~ ((~ comp_pat[0]) ^ nlll0ii)) & (~ ((~ comp_pat[1]) ^ nlll0il))) & (~ ((~ comp_pat[2]) ^ nlll0iO))) & (~ ((~ comp_pat[3]) ^ nlll0li))) & (~ ((~ comp_pat[4]) ^ nlll0ll))) & (~ ((~ comp_pat[5]) ^ nlll0lO))) & (~ ((~ comp_pat[6]) ^ nlll0Oi))),
		n1i10li = ((comp_pat_porn & n1i10lO) | n1i10ll),
		n1i10ll = (((((((~ (comp_pat[0] ^ nlll00O)) & (~ (comp_pat[1] ^ nlll0ii))) & (~ (comp_pat[2] ^ nlll0il))) & (~ (comp_pat[3] ^ nlll0iO))) & (~ (comp_pat[4] ^ nlll0li))) & (~ (comp_pat[5] ^ nlll0ll))) & (~ (comp_pat[6] ^ nlll0lO))),
		n1i10lO = (((((((~ ((~ comp_pat[0]) ^ nlll00O)) & (~ ((~ comp_pat[1]) ^ nlll0ii))) & (~ ((~ comp_pat[2]) ^ nlll0il))) & (~ ((~ comp_pat[3]) ^ nlll0iO))) & (~ ((~ comp_pat[4]) ^ nlll0li))) & (~ ((~ comp_pat[5]) ^ nlll0ll))) & (~ ((~ comp_pat[6]) ^ nlll0lO))),
		n1i10Oi = ((comp_pat_porn & n1i10OO) | n1i10Ol),
		n1i10Ol = (((((((~ (comp_pat[0] ^ nlll00l)) & (~ (comp_pat[1] ^ nlll00O))) & (~ (comp_pat[2] ^ nlll0ii))) & (~ (comp_pat[3] ^ nlll0il))) & (~ (comp_pat[4] ^ nlll0iO))) & (~ (comp_pat[5] ^ nlll0li))) & (~ (comp_pat[6] ^ nlll0ll))),
		n1i10OO = (((((((~ ((~ comp_pat[0]) ^ nlll00l)) & (~ ((~ comp_pat[1]) ^ nlll00O))) & (~ ((~ comp_pat[2]) ^ nlll0ii))) & (~ ((~ comp_pat[3]) ^ nlll0il))) & (~ ((~ comp_pat[4]) ^ nlll0iO))) & (~ ((~ comp_pat[5]) ^ nlll0li))) & (~ ((~ comp_pat[6]) ^ nlll0ll))),
		n1i110i = ((comp_pat_porn & n1i110O) | n1i110l),
		n1i110l = (((((((~ (comp_pat[0] ^ nlll0Oi)) & (~ (comp_pat[1] ^ nlll0Ol))) & (~ (comp_pat[2] ^ nlll0OO))) & (~ (comp_pat[3] ^ nllli1i))) & (~ (comp_pat[4] ^ nllli1l))) & (~ (comp_pat[5] ^ nllli1O))) & (~ (comp_pat[6] ^ nllli0i))),
		n1i110O = (((((((~ ((~ comp_pat[0]) ^ nlll0Oi)) & (~ ((~ comp_pat[1]) ^ nlll0Ol))) & (~ ((~ comp_pat[2]) ^ nlll0OO))) & (~ ((~ comp_pat[3]) ^ nllli1i))) & (~ ((~ comp_pat[4]) ^ nllli1l))) & (~ ((~ comp_pat[5]) ^ nllli1O))) & (~ ((~ comp_pat[6]) ^ nllli0i))),
		n1i111i = ((comp_pat_porn & n1i111O) | n1i111l),
		n1i111l = (((((((~ (comp_pat[0] ^ nlll0Ol)) & (~ (comp_pat[1] ^ nlll0OO))) & (~ (comp_pat[2] ^ nllli1i))) & (~ (comp_pat[3] ^ nllli1l))) & (~ (comp_pat[4] ^ nllli1O))) & (~ (comp_pat[5] ^ nllli0i))) & (~ (comp_pat[6] ^ nllli0l))),
		n1i111O = (((((((~ ((~ comp_pat[0]) ^ nlll0Ol)) & (~ ((~ comp_pat[1]) ^ nlll0OO))) & (~ ((~ comp_pat[2]) ^ nllli1i))) & (~ ((~ comp_pat[3]) ^ nllli1l))) & (~ ((~ comp_pat[4]) ^ nllli1O))) & (~ ((~ comp_pat[5]) ^ nllli0i))) & (~ ((~ comp_pat[6]) ^ nllli0l))),
		n1i11ii = ((comp_pat_porn & n1i11iO) | n1i11il),
		n1i11il = (((((((~ (comp_pat[0] ^ nlll0lO)) & (~ (comp_pat[1] ^ nlll0Oi))) & (~ (comp_pat[2] ^ nlll0Ol))) & (~ (comp_pat[3] ^ nlll0OO))) & (~ (comp_pat[4] ^ nllli1i))) & (~ (comp_pat[5] ^ nllli1l))) & (~ (comp_pat[6] ^ nllli1O))),
		n1i11iO = (((((((~ ((~ comp_pat[0]) ^ nlll0lO)) & (~ ((~ comp_pat[1]) ^ nlll0Oi))) & (~ ((~ comp_pat[2]) ^ nlll0Ol))) & (~ ((~ comp_pat[3]) ^ nlll0OO))) & (~ ((~ comp_pat[4]) ^ nllli1i))) & (~ ((~ comp_pat[5]) ^ nllli1l))) & (~ ((~ comp_pat[6]) ^ nllli1O))),
		n1i11li = ((comp_pat_porn & n1i11lO) | n1i11ll),
		n1i11ll = (((((((~ (comp_pat[0] ^ nlll0ll)) & (~ (comp_pat[1] ^ nlll0lO))) & (~ (comp_pat[2] ^ nlll0Oi))) & (~ (comp_pat[3] ^ nlll0Ol))) & (~ (comp_pat[4] ^ nlll0OO))) & (~ (comp_pat[5] ^ nllli1i))) & (~ (comp_pat[6] ^ nllli1l))),
		n1i11lO = (((((((~ ((~ comp_pat[0]) ^ nlll0ll)) & (~ ((~ comp_pat[1]) ^ nlll0lO))) & (~ ((~ comp_pat[2]) ^ nlll0Oi))) & (~ ((~ comp_pat[3]) ^ nlll0Ol))) & (~ ((~ comp_pat[4]) ^ nlll0OO))) & (~ ((~ comp_pat[5]) ^ nllli1i))) & (~ ((~ comp_pat[6]) ^ nllli1l))),
		n1i11Oi = ((comp_pat_porn & n1i11OO) | n1i11Ol),
		n1i11Ol = (((((((~ (comp_pat[0] ^ nlll0li)) & (~ (comp_pat[1] ^ nlll0ll))) & (~ (comp_pat[2] ^ nlll0lO))) & (~ (comp_pat[3] ^ nlll0Oi))) & (~ (comp_pat[4] ^ nlll0Ol))) & (~ (comp_pat[5] ^ nlll0OO))) & (~ (comp_pat[6] ^ nllli1i))),
		n1i11OO = (((((((~ ((~ comp_pat[0]) ^ nlll0li)) & (~ ((~ comp_pat[1]) ^ nlll0ll))) & (~ ((~ comp_pat[2]) ^ nlll0lO))) & (~ ((~ comp_pat[3]) ^ nlll0Oi))) & (~ ((~ comp_pat[4]) ^ nlll0Ol))) & (~ ((~ comp_pat[5]) ^ nlll0OO))) & (~ ((~ comp_pat[6]) ^ nllli1i))),
		n1i1i0i = ((((~ rencdt_rising) & nllO00i) | (rencdt_rising & nllO1Ol)) & (((((~ resync_badcg_en[0]) & (~ resync_badcg_en[1])) | (resync_badcg_en[0] & resync_badcg_en[1])) | (n1i1iii & (resync_badcg_en[0] & (~ resync_badcg_en[1])))) | ((n1i1iii | (n1i1i0O | n1i1i0l)) & ((~ resync_badcg_en[0]) & resync_badcg_en[1])))),
		n1i1i0l = (((((~ wire_n1liili_dataout) & ((((((nlOOO1Ol | nlOOO1OO) | nlOOO1Oi) | (nlOOlO0O & nlOOlO0l)) | (nlOOO1il & nlOOlO0i)) | nlOOO01i) | nlOOlO1O)) | (wire_n1liili_dataout & (nlOOlO1l | ((~ wire_nl01i1O_o) & nlOOlO1i)))) | ((nlOOlOlO | (nlOOO10i | nlOOO1ll)) & (~ wire_n1O010l_dataout))) | ((nlOOlOOl | (wire_nl01iii_o & (wire_nl01i0O_o & nlOOlOOi))) & wire_n1O010l_dataout)),
		n1i1i0O = (((((~ nl01lOO) & ((((((nlOOli0l | nlOOli0O) | nlOOli0i) | (nlOOl1lO & nlOOl1ll)) | (nlOOl0Ol & nlOOl1li)) | nlOOliii) | nlOOl1iO)) | (nl01lOO & (nlOOl1il | ((~ wire_nl010il_o) & nlOOl1ii)))) | ((nlOOl01O | (nlOOl0li | nlOOli1l)) & (~ wire_n1l1O0l_dataout))) | ((nlOOl00l | (wire_nl010lO_o & (wire_nl010ll_o & nlOOl00i))) & wire_n1l1O0l_dataout)),
		n1i1i1i = (n1i1i1O | n1i1i1l),
		n1i1i1l = (nlliOll & (~ nlliOli)),
		n1i1i1O = ((~ nlliOll) & nlliOli),
		n1i1iii = ((~ wire_n1O100i_dataout) | (~ wire_n011i0i_dataout)),
		n1i1iil = ((~ wa_6g_en) | ((~ lpbk_en) & (~ nlliOlO))),
		n1i1iiO = (((~ nllO1OO) & (wa_6g_en & (lpbk_en | nlliOlO))) & n1iOOOO),
		n1i1ili = (wire_nlO01ii_dataout | ((((~ (rosnumber[0] ^ nlOiOil)) & (~ (rosnumber[1] ^ nlOiOiO))) & (~ (rosnumber[2] ^ nlOiOli))) & (~ (rosnumber[3] ^ nlOiOll)))),
		n1i1ill = (wire_nlO010i_dataout | wire_nlO011O_dataout),
		n1i1ilO = ((wire_nlO01il_dataout | wire_nlO01ii_dataout) | (~ n1i1l1i)),
		n1i1iOi = (((wire_nlO01il_dataout | wire_nlO01ii_dataout) | wire_nlO011l_dataout) | (~ n1i1l1i)),
		n1i1iOl = ((((wire_nlO010O_dataout | wire_nlO010i_dataout) | wire_nlO011O_dataout) | wire_nlO011l_dataout) | (~ n1i1l1i)),
		n1i1iOO = ((((wire_nlO01ii_dataout | wire_nlO010i_dataout) | wire_nlO011O_dataout) | wire_nlO011l_dataout) | (~ n1i1l1i)),
		n1i1l0i = (n1i011O & (~ n1i1OiO)),
		n1i1l0l = (n1i1lil & (~ n1i1lOl)),
		n1i1l0O = ((wire_nlO0l1l_o & n1i1lil) & n1i1lOl),
		n1i1l1i = (((((wire_nlO01il_dataout | wire_nlO01ii_dataout) | wire_nlO010O_dataout) | wire_nlO010i_dataout) | wire_nlO011O_dataout) | wire_nlO011l_dataout),
		n1i1l1l = (n1i1OiO & (~ n1i1O0l)),
		n1i1l1O = ((n1i011O & n1i1OiO) & (~ n1i1O0l)),
		n1i1lii = ((wire_nlOi1Ol_o & n1i1lil) & n1i1lOl),
		n1i1lil = ((~ n1i011O) & n1i1OiO),
		n1i1liO = ((~ n1i011O) & (~ n1i1OiO)),
		n1i1lli = ((n1i1Oii & n1i1lll) & n1i1lOl),
		n1i1lll = ((((((((((~ nlOl01i) & (~ nlOl1OO)) & (~ nlOl1Ol)) & (~ nlOl1Oi)) & (~ nlOl1lO)) & (~ nlOl1ll)) & (~ nlOl1li)) & (~ nlOl1iO)) & (~ nlOl1il)) & nlOl1ii),
		n1i1llO = ((wire_nlOi1Ol_o & n1i1Oii) & n1i1lOl),
		n1i1lOi = (n1i1Oii & (~ n1i1lOl)),
		n1i1lOl = ((((((((((~ (gnumber[0] ^ nlOiOlO)) & (~ (gnumber[1] ^ nlOiOOi))) & (~ (gnumber[2] ^ nlOiOOl))) & (~ (gnumber[3] ^ nlOiOOO))) & (~ (gnumber[4] ^ nlOl11i))) & (~ (gnumber[5] ^ nlOl11l))) & (~ (gnumber[6] ^ nlOl11O))) & (~ (gnumber[7] ^ nlOl10i))) & (~ (gnumber[8] ^ nlOl10l))) & (~ (gnumber[9] ^ nlOl10O))),
		n1i1lOO = ((wire_nlOi1Ol_o & n1i1Oii) & n1i1lOl),
		n1i1O0i = (n1i1O0O & (~ n1i1O0l)),
		n1i1O0l = ((((((((((~ (enumber[0] ^ nlOl1ii)) & (~ (enumber[1] ^ nlOl1il))) & (~ (enumber[2] ^ nlOl1iO))) & (~ (enumber[3] ^ nlOl1li))) & (~ (enumber[4] ^ nlOl1ll))) & (~ (enumber[5] ^ nlOl1lO))) & (~ (enumber[6] ^ nlOl1Oi))) & (~ (enumber[7] ^ nlOl1Ol))) & (~ (enumber[8] ^ nlOl1OO))) & (~ (enumber[9] ^ nlOl01i))),
		n1i1O0O = ((~ rosbased) & n1i011O),
		n1i1O1i = (n1i1Oii & (~ n1i1lOl)),
		n1i1O1l = ((n1i1Oii & n1i1lll) & n1i1lOl),
		n1i1O1O = (rosbased & (~ n1i011O)),
		n1i1Oii = ((~ rosbased) & (~ n1i011O)),
		n1i1Oil = (n1i1O0O & n1i1O0l),
		n1i1OiO = ((((~ (rosnumber[0] ^ wire_nlOli0i_o[0])) & (~ (rosnumber[1] ^ wire_nlOli0i_o[1]))) & (~ (rosnumber[2] ^ wire_nlOli0i_o[2]))) & (~ (rosnumber[3] ^ wire_nlOli0i_o[3]))),
		n1i1Oli = (((~ n1i1OOi) & niO11l) & ((~ n1i010l) | n1i010i)),
		n1i1Oll = ((n1i1OOl | (n1i010O & (n1i010l & n1i1OiO))) & n1i1OOi),
		n1i1OlO = (n1i1OOl & (~ n1i1OOi)),
		n1i1OOi = ((((((((((~ (knumber[0] ^ nlOl01l)) & (~ (knumber[1] ^ nlOl01O))) & (~ (knumber[2] ^ nlOl00i))) & (~ (knumber[3] ^ nlOl00l))) & (~ (knumber[4] ^ nlOl00O))) & (~ (knumber[5] ^ nlOl0ii))) & (~ (knumber[6] ^ nlOl0il))) & (~ (knumber[7] ^ nlOl0iO))) & (~ (knumber[8] ^ nlOl0li))) & (~ (knumber[9] ^ nlOl0ll))),
		n1i1OOl = ((~ n1i010l) & niO11l),
		n1i1OOO = (((~ n1i010O) & n1i010l) | niO0Oi),
		n1ii00i = (((((((((~ n1il10l) | n1iiOOl) | (~ n1iiOOi)) | (~ n1iiOlO)) | (~ n1iiOll)) | (~ n1iiOli)) | (~ n1iiOiO)) | n1iiOii) | n1iiO0O),
		n1ii00l = ((((((((~ n1il10l) | n1iiOOi) | (~ n1iiOlO)) | (~ n1iiOll)) | (~ n1iiOli)) | (~ n1iiOiO)) | n1iiOii) | n1iiO0O),
		n1ii00O = (((((((~ n1il10l) | n1iiOlO) | (~ n1iiOll)) | (~ n1iiOli)) | (~ n1iiOiO)) | n1iiOii) | n1iiO0O),
		n1ii01i = (((((~ n1ii0li) | (~ n1ii0iO)) | (~ n1ii0ii)) | (~ n1ii00l)) | n1ii01l),
		n1ii01l = ((((((((((~ nl0ill) & n1il10l) & n1iiOOl) & n1iiOOi) & n1iiOlO) & n1iiOll) & n1iiOli) & n1iiOiO) & (~ n1iiOii)) & (~ n1iiO0O)),
		n1ii01O = ((((n1iiO0O | (~ n1ii0iO)) | (~ n1ii0il)) | (~ n1ii00l)) | (~ n1ii00i)),
		n1ii0ii = ((((((~ n1il10l) | n1iiOll) | (~ n1iiOli)) | (~ n1iiOiO)) | n1iiOii) | n1iiO0O),
		n1ii0il = (((((~ n1il10l) | n1iiOli) | (~ n1iiOiO)) | n1iiOii) | n1iiO0O),
		n1ii0iO = ((((~ n1il10l) | n1iiOiO) | n1iiOii) | n1iiO0O),
		n1ii0li = ((~ n1iiOii) | n1iiO0O),
		n1ii0ll = (((((~ n1iii0l) | (~ n1iii0i)) | (~ n1iii1l)) | (~ n1ii0OO)) | n1ii0lO),
		n1ii0lO = (((((((((((pmadwidth[0] & (~ nlli0l)) | ((~ pmadwidth[0]) & (~ nlli1O))) & (~ n1il01O)) & (~ n1il01l)) & (~ n1il01i)) & (~ n1il1Oi)) & (~ n1il1li)) & (~ n1il1ii)) & (~ n1il10i)) & (~ n1il11l)) & (~ n1iiOOO)),
		n1ii0Oi = ((((n1iiOOO | (~ n1iii0i)) | (~ n1iii1O)) | (~ n1ii0OO)) | (~ n1ii0Ol)),
		n1ii0Ol = (((((((((~ n1il01O) | n1il01l) | n1il01i) | n1il1Oi) | n1il1li) | n1il1ii) | n1il10i) | n1il11l) | n1iiOOO),
		n1ii0OO = ((((((((~ n1il01l) | n1il01i) | n1il1Oi) | n1il1li) | n1il1ii) | n1il10i) | n1il11l) | n1iiOOO),
		n1ii10i = (((n1iil0l | (~ n1iiiiO)) | n1iiiii) | n1iii0O),
		n1ii10l = ((~ n1iiiii) | n1iii0O),
		n1ii10O = (((((~ n1ii1OO) | (~ n1ii1Ol)) | (~ n1ii1lO)) | (~ n1ii1li)) | n1ii1ii),
		n1ii11i = ((((((n1iil0l | (~ n1iiilO)) | n1iiill) | n1iiili) | n1iiiiO) | n1iiiii) | n1iii0O),
		n1ii11l = (((((n1iil0l | (~ n1iiill)) | n1iiili) | n1iiiiO) | n1iiiii) | n1iii0O),
		n1ii11O = ((((n1iil0l | (~ n1iiili)) | n1iiiiO) | n1iiiii) | n1iii0O),
		n1ii1ii = ((((((((((n1iiO0l | n1iiO0i) & (~ n1iiO1O)) & (~ n1iiO1l)) & (~ n1iiO1i)) & (~ n1iilOi)) & (~ n1iilli)) & (~ n1iilii)) & (~ n1iil0i)) & (~ n1iil1l)) & (~ n1iiiOO)),
		n1ii1il = ((((n1iiiOO | (~ n1ii1Ol)) | (~ n1ii1Oi)) | (~ n1ii1li)) | (~ n1ii1iO)),
		n1ii1iO = (((((((((~ n1iiO1O) | n1iiO1l) | n1iiO1i) | n1iilOi) | n1iilli) | n1iilii) | n1iil0i) | n1iil1l) | n1iiiOO),
		n1ii1li = ((((((((~ n1iiO1l) | n1iiO1i) | n1iilOi) | n1iilli) | n1iilii) | n1iil0i) | n1iil1l) | n1iiiOO),
		n1ii1ll = (((((((~ n1iiO1i) | n1iilOi) | n1iilli) | n1iilii) | n1iil0i) | n1iil1l) | n1iiiOO),
		n1ii1lO = ((((((~ n1iilOi) | n1iilli) | n1iilii) | n1iil0i) | n1iil1l) | n1iiiOO),
		n1ii1Oi = (((((~ n1iilli) | n1iilii) | n1iil0i) | n1iil1l) | n1iiiOO),
		n1ii1Ol = ((((~ n1iilii) | n1iil0i) | n1iil1l) | n1iiiOO),
		n1ii1OO = ((~ n1iil1l) | n1iiiOO),
		n1iii0i = ((((~ n1il1ii) | n1il10i) | n1il11l) | n1iiOOO),
		n1iii0l = ((~ n1il11l) | n1iiOOO),
		n1iii0O = (pmadwidth[0] & n1iil1i),
		n1iii1i = (((((((~ n1il01i) | n1il1Oi) | n1il1li) | n1il1ii) | n1il10i) | n1il11l) | n1iiOOO),
		n1iii1l = ((((((~ n1il1Oi) | n1il1li) | n1il1ii) | n1il10i) | n1il11l) | n1iiOOO),
		n1iii1O = (((((~ n1il1li) | n1il1ii) | n1il10i) | n1il11l) | n1iiOOO),
		n1iiiii = (pmadwidth[0] & n1iiiil),
		n1iiiil = ((((((((nlli0i & nlli1O) & nlli1l) & nlli1i) & nll0OO) & nll0Ol) & nll0Oi) & nll0lO) & nl0ill),
		n1iiiiO = ((((((nlli1l & nlli1i) & nll0OO) & nll0Ol) & nll0Oi) & nll0lO) & nl0ill),
		n1iiili = (((((nlli1i & nll0OO) & nll0Ol) & nll0Oi) & nll0lO) & nl0ill),
		n1iiill = ((((nll0OO & nll0Ol) & nll0Oi) & nll0lO) & nl0ill),
		n1iiilO = (((nll0Ol & nll0Oi) & nll0lO) & nl0ill),
		n1iiiOi = ((nll0Oi & nll0lO) & nl0ill),
		n1iiiOl = (nll0lO & nl0ill),
		n1iiiOO = (pmadwidth[0] & n1iil1i),
		n1iil0i = ((pmadwidth[0] & n1iil0O) | ((~ pmadwidth[0]) & n1iil0l)),
		n1iil0l = (((((((nlli1O & nlli1l) & nlli1i) & nll0OO) & nll0Ol) & nll0Oi) & nll0lO) & nl0ill),
		n1iil0O = (((((((nlli0l & nlli0i) & nlli1O) & nlli1l) & nlli1i) & nll0OO) & nll0Ol) & nll0Oi),
		n1iil1i = (((((((((nlli0l & nlli0i) & nlli1O) & nlli1l) & nlli1i) & nll0OO) & nll0Ol) & nll0Oi) & nll0lO) & nl0ill),
		n1iil1l = (pmadwidth[0] & n1iil1O),
		n1iil1O = ((((((((nlli0l & nlli0i) & nlli1O) & nlli1l) & nlli1i) & nll0OO) & nll0Ol) & nll0Oi) & nll0lO),
		n1iilii = ((pmadwidth[0] & n1iiliO) | ((~ pmadwidth[0]) & n1iilil)),
		n1iilil = ((((((nlli1O & nlli1l) & nlli1i) & nll0OO) & nll0Ol) & nll0Oi) & nll0lO),
		n1iiliO = ((((((nlli0l & nlli0i) & nlli1O) & nlli1l) & nlli1i) & nll0OO) & nll0Ol),
		n1iilli = ((pmadwidth[0] & n1iillO) | ((~ pmadwidth[0]) & n1iilll)),
		n1iilll = (((((nlli1O & nlli1l) & nlli1i) & nll0OO) & nll0Ol) & nll0Oi),
		n1iillO = (((((nlli0l & nlli0i) & nlli1O) & nlli1l) & nlli1i) & nll0OO),
		n1iilOi = ((pmadwidth[0] & n1iilOO) | ((~ pmadwidth[0]) & n1iilOl)),
		n1iilOl = ((((nlli1O & nlli1l) & nlli1i) & nll0OO) & nll0Ol),
		n1iilOO = ((((nlli0l & nlli0i) & nlli1O) & nlli1l) & nlli1i),
		n1iiO0i = ((~ pmadwidth[0]) & nlli1O),
		n1iiO0l = (pmadwidth[0] & nlli0l),
		n1iiO0O = (pmadwidth[0] & (~ n1il11i)),
		n1iiO1i = ((pmadwidth[0] & (((nlli0l & nlli0i) & nlli1O) & nlli1l)) | ((~ pmadwidth[0]) & (((nlli1O & nlli1l) & nlli1i) & nll0OO))),
		n1iiO1l = ((pmadwidth[0] & ((nlli0l & nlli0i) & nlli1O)) | ((~ pmadwidth[0]) & ((nlli1O & nlli1l) & nlli1i))),
		n1iiO1O = ((pmadwidth[0] & (nlli0l & nlli0i)) | ((~ pmadwidth[0]) & (nlli1O & nlli1l))),
		n1iiOii = (pmadwidth[0] & (~ n1iiOil)),
		n1iiOil = ((((((((nlli0i | nlli1O) | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | nl0ill),
		n1iiOiO = ((((((nlli1l | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | nl0ill),
		n1iiOli = (((((nlli1i | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | nl0ill),
		n1iiOll = ((((nll0OO | nll0Ol) | nll0Oi) | nll0lO) | nl0ill),
		n1iiOlO = (((nll0Ol | nll0Oi) | nll0lO) | nl0ill),
		n1iiOOi = ((nll0Oi | nll0lO) | nl0ill),
		n1iiOOl = (nll0lO | nl0ill),
		n1iiOOO = (pmadwidth[0] & (~ n1il11i)),
		n1il00i = (((((((~ ((~ comp_pat[0]) ^ wire_nl1iOi_o)) & (~ ((~ comp_pat[1]) ^ wire_nl1iOl_o))) & (~ ((~ comp_pat[2]) ^ wire_nl1iOO_o))) & (~ ((~ comp_pat[3]) ^ wire_nl1l1i_o))) & (~ ((~ comp_pat[4]) ^ wire_nl1l1l_o))) & (~ ((~ comp_pat[5]) ^ wire_nl1l1O_o))) & (~ ((~ comp_pat[6]) ^ wire_nl1l0i_o))),
		n1il00l = (((((((~ (comp_pat[0] ^ wire_nl1iOi_o)) & (~ (comp_pat[1] ^ wire_nl1iOl_o))) & (~ (comp_pat[2] ^ wire_nl1iOO_o))) & (~ (comp_pat[3] ^ wire_nl1l1i_o))) & (~ (comp_pat[4] ^ wire_nl1l1l_o))) & (~ (comp_pat[5] ^ wire_nl1l1O_o))) & (~ (comp_pat[6] ^ wire_nl1l0i_o))),
		n1il00O = ((((((((((~ ((~ comp_pat[0]) ^ wire_nl1iOi_o)) & (~ ((~ comp_pat[1]) ^ wire_nl1iOl_o))) & (~ ((~ comp_pat[2]) ^ wire_nl1iOO_o))) & (~ ((~ comp_pat[3]) ^ wire_nl1l1i_o))) & (~ ((~ comp_pat[4]) ^ wire_nl1l1l_o))) & (~ ((~ comp_pat[5]) ^ wire_nl1l1O_o))) & (~ ((~ comp_pat[6]) ^ wire_nl1l0i_o))) & (~ ((~ comp_pat[7]) ^ wire_nl1l0l_o))) & (~ ((~ comp_pat[8]) ^ wire_nl1l0O_dataout))) & (~ ((~ comp_pat[9]) ^ wire_nl1lii_dataout))),
		n1il01i = ((pmadwidth[0] & (~ (((nlli0l | nlli0i) | nlli1O) | nlli1l))) | ((~ pmadwidth[0]) & (~ (((nlli1O | nlli1l) | nlli1i) | nll0OO)))),
		n1il01l = ((pmadwidth[0] & (~ ((nlli0l | nlli0i) | nlli1O))) | ((~ pmadwidth[0]) & (~ ((nlli1O | nlli1l) | nlli1i)))),
		n1il01O = ((pmadwidth[0] & (~ (nlli0l | nlli0i))) | ((~ pmadwidth[0]) & (~ (nlli1O | nlli1l)))),
		n1il0ii = ((((((((((~ (comp_pat[0] ^ wire_nl1iOi_o)) & (~ (comp_pat[1] ^ wire_nl1iOl_o))) & (~ (comp_pat[2] ^ wire_nl1iOO_o))) & (~ (comp_pat[3] ^ wire_nl1l1i_o))) & (~ (comp_pat[4] ^ wire_nl1l1l_o))) & (~ (comp_pat[5] ^ wire_nl1l1O_o))) & (~ (comp_pat[6] ^ wire_nl1l0i_o))) & (~ (comp_pat[7] ^ wire_nl1l0l_o))) & (~ (comp_pat[8] ^ wire_nl1l0O_dataout))) & (~ (comp_pat[9] ^ wire_nl1lii_dataout))),
		n1il0il = (wire_nl1l1O_o & ((~ wire_nl1l1l_o) & n1iliOl)),
		n1il0iO = ((~ wire_nl1l1O_o) & (wire_nl1l1l_o & n1i01OO)),
		n1il0li = ((~ wire_nl1l1O_o) & ((~ wire_nl1l1l_o) & ((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & (wire_nl1iOl_o & wire_nl1iOi_o))))),
		n1il0ll = (wire_nl1l1O_o & (wire_nl1l1l_o & (wire_nl1l1i_o & (wire_nl1iOO_o & ((~ wire_nl1iOl_o) & (~ wire_nl1iOi_o)))))),
		n1il0lO = ((~ comp_pat_size[0]) & comp_pat_size[1]),
		n1il0Oi = ((((((((((~ ((~ comp_pat[0]) ^ wire_nl111l_dataout)) & (~ ((~ comp_pat[1]) ^ wire_nl111O_dataout))) & (~ ((~ comp_pat[2]) ^ wire_nl110i_dataout))) & (~ ((~ comp_pat[3]) ^ wire_nl110l_dataout))) & (~ ((~ comp_pat[4]) ^ wire_nl110O_dataout))) & (~ ((~ comp_pat[5]) ^ wire_nl11ii_dataout))) & (~ ((~ comp_pat[6]) ^ wire_nl11il_dataout))) & (~ ((~ comp_pat[7]) ^ wire_nl11iO_dataout))) & (~ ((~ comp_pat[8]) ^ wire_nl11li_dataout))) & (~ ((~ comp_pat[9]) ^ wire_nl11ll_dataout))),
		n1il0Ol = ((((((((((~ (comp_pat[0] ^ wire_nl111l_dataout)) & (~ (comp_pat[1] ^ wire_nl111O_dataout))) & (~ (comp_pat[2] ^ wire_nl110i_dataout))) & (~ (comp_pat[3] ^ wire_nl110l_dataout))) & (~ (comp_pat[4] ^ wire_nl110O_dataout))) & (~ (comp_pat[5] ^ wire_nl11ii_dataout))) & (~ (comp_pat[6] ^ wire_nl11il_dataout))) & (~ (comp_pat[7] ^ wire_nl11iO_dataout))) & (~ (comp_pat[8] ^ wire_nl11li_dataout))) & (~ (comp_pat[9] ^ wire_nl11ll_dataout))),
		n1il0OO = (((((((~ ((~ comp_pat[0]) ^ wire_nl111l_dataout)) & (~ ((~ comp_pat[1]) ^ wire_nl111O_dataout))) & (~ ((~ comp_pat[2]) ^ wire_nl110i_dataout))) & (~ ((~ comp_pat[3]) ^ wire_nl110l_dataout))) & (~ ((~ comp_pat[4]) ^ wire_nl110O_dataout))) & (~ ((~ comp_pat[5]) ^ wire_nl11ii_dataout))) & (~ ((~ comp_pat[6]) ^ wire_nl11il_dataout))),
		n1il10i = ((pmadwidth[0] & (~ n1il10O)) | ((~ pmadwidth[0]) & (~ n1il10l))),
		n1il10l = (((((((nlli1O | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | nl0ill),
		n1il10O = (((((((nlli0l | nlli0i) | nlli1O) | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi),
		n1il11i = (((((((((nlli0l | nlli0i) | nlli1O) | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO) | nl0ill),
		n1il11l = (pmadwidth[0] & (~ n1il11O)),
		n1il11O = ((((((((nlli0l | nlli0i) | nlli1O) | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO),
		n1il1ii = ((pmadwidth[0] & (~ n1il1iO)) | ((~ pmadwidth[0]) & (~ n1il1il))),
		n1il1il = ((((((nlli1O | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi) | nll0lO),
		n1il1iO = ((((((nlli0l | nlli0i) | nlli1O) | nlli1l) | nlli1i) | nll0OO) | nll0Ol),
		n1il1li = ((pmadwidth[0] & (~ n1il1lO)) | ((~ pmadwidth[0]) & (~ n1il1ll))),
		n1il1ll = (((((nlli1O | nlli1l) | nlli1i) | nll0OO) | nll0Ol) | nll0Oi),
		n1il1lO = (((((nlli0l | nlli0i) | nlli1O) | nlli1l) | nlli1i) | nll0OO),
		n1il1Oi = ((pmadwidth[0] & (~ n1il1OO)) | ((~ pmadwidth[0]) & (~ n1il1Ol))),
		n1il1Ol = ((((nlli1O | nlli1l) | nlli1i) | nll0OO) | nll0Ol),
		n1il1OO = ((((nlli0l | nlli0i) | nlli1O) | nlli1l) | nlli1i),
		n1ili0i = (((((((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & (wire_nl1l0l_o & wire_nl1l0i_o))) | ((~ wire_nl1lii_dataout) & (wire_nl1l0O_dataout & n1i000i))) | ((~ wire_nl1lii_dataout) & (wire_nl1l0O_dataout & n1i001O))) | (wire_nl1lii_dataout & ((~ wire_nl1l0O_dataout) & n1i000i))) | (wire_nl1lii_dataout & ((~ wire_nl1l0O_dataout) & n1i001O))) | (wire_nl1lii_dataout & (wire_nl1l0O_dataout & ((~ wire_nl1l0l_o) & (~ wire_nl1l0i_o))))),
		n1ili0l = (n1i00li | n1i00lO),
		n1ili0O = ((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & (~ wire_nl1l0i_o)))),
		n1ili1i = (((((((~ (comp_pat[0] ^ wire_nl111l_dataout)) & (~ (comp_pat[1] ^ wire_nl111O_dataout))) & (~ (comp_pat[2] ^ wire_nl110i_dataout))) & (~ (comp_pat[3] ^ wire_nl110l_dataout))) & (~ (comp_pat[4] ^ wire_nl110O_dataout))) & (~ (comp_pat[5] ^ wire_nl11ii_dataout))) & (~ (comp_pat[6] ^ wire_nl11il_dataout))),
		n1ili1l = ((((((((~ (comp_pat[8] ^ wire_nl111l_dataout)) & (~ (comp_pat[9] ^ wire_nl111O_dataout))) & (~ (comp_pat[10] ^ wire_nl110i_dataout))) & (~ (comp_pat[11] ^ wire_nl110l_dataout))) & (~ (comp_pat[12] ^ wire_nl110O_dataout))) & (~ (comp_pat[13] ^ wire_nl11ii_dataout))) & (~ (comp_pat[14] ^ wire_nl11il_dataout))) & (~ (comp_pat[15] ^ wire_nl11iO_dataout))),
		n1ili1O = ((((((((~ (comp_pat[0] ^ wire_nl111l_dataout)) & (~ (comp_pat[1] ^ wire_nl111O_dataout))) & (~ (comp_pat[2] ^ wire_nl110i_dataout))) & (~ (comp_pat[3] ^ wire_nl110l_dataout))) & (~ (comp_pat[4] ^ wire_nl110O_dataout))) & (~ (comp_pat[5] ^ wire_nl11ii_dataout))) & (~ (comp_pat[6] ^ wire_nl11il_dataout))) & (~ (comp_pat[7] ^ wire_nl11iO_dataout))),
		n1iliii = (((((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & ((~ wire_nl1l0l_o) & wire_nl1l0i_o))) | ((~ wire_nl1lii_dataout) & ((~ wire_nl1l0O_dataout) & (wire_nl1l0l_o & (~ wire_nl1l0i_o))))) | ((~ wire_nl1lii_dataout) & (wire_nl1l0O_dataout & n1i001l))) | (wire_nl1lii_dataout & ((~ wire_nl1l0O_dataout) & n1i001l))),
		n1iliil = ((~ wire_nl1l0l_o) & ((~ wire_nl1l0i_o) & n1ili0i)),
		n1iliiO = (n1i01OO & n1iliOO),
		n1ilili = ((((n1i00Ol | (n1ill1i & n1i01Oi)) | (n1i01OO & n1iliOi)) | n1i00Oi) | n1i00OO),
		n1ilill = (wire_nl1l1i_o & n1i01ll),
		n1ililO = (n1i01lO & n1i01Oi),
		n1iliOi = (((~ wire_nl1l1O_o) & wire_nl1l1l_o) | (wire_nl1l1O_o & (~ wire_nl1l1l_o))),
		n1iliOl = (((((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & ((~ wire_nl1iOl_o) & wire_nl1iOi_o))) | ((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & (wire_nl1iOl_o & (~ wire_nl1iOi_o))))) | ((~ wire_nl1l1i_o) & (wire_nl1iOO_o & n1i01il))) | (wire_nl1l1i_o & ((~ wire_nl1iOO_o) & n1i01il))),
		n1iliOO = ((~ wire_nl1l1O_o) & (~ wire_nl1l1l_o)),
		n1ill0i = (n1i01lO & n1iliOO),
		n1ill0l = ((~ pmadwidth[0]) & (~ n1illii)),
		n1ill0O = (nl0i0i & ((~ pmadwidth[0]) & nl0i0l)),
		n1ill1i = (((((((~ wire_nl1l1i_o) & ((~ wire_nl1iOO_o) & (wire_nl1iOl_o & wire_nl1iOi_o))) | ((~ wire_nl1l1i_o) & (wire_nl1iOO_o & n1i01li))) | ((~ wire_nl1l1i_o) & (wire_nl1iOO_o & n1i01iO))) | (wire_nl1l1i_o & ((~ wire_nl1iOO_o) & n1i01li))) | (wire_nl1l1i_o & ((~ wire_nl1iOO_o) & n1i01iO))) | (wire_nl1l1i_o & (wire_nl1iOO_o & ((~ wire_nl1iOl_o) & (~ wire_nl1iOi_o))))),
		n1ill1l = (n1iliOl & n1iliOO),
		n1ill1O = (n1i01lO & n1iliOi),
		n1illii = (nl0i0l & nl0i0i),
		n1illil = (n1illli | n1illiO),
		n1illiO = (nl0i0l & (~ nl0i0i)),
		n1illli = (nl0i0l & nl0i0i),
		n1illll = (n1illOi | n1illlO),
		n1illlO = (pmadwidth[0] & niOO0l),
		n1illOi = ((~ pmadwidth[0]) & niOO0l),
		n1illOl = ((~ pmadwidth[0]) & n1ilO1i),
		n1illOO = (pmadwidth[0] & n1ilO1i),
		n1ilO0i = (wire_nlO10il_dataout & (~ (((n1iOlil & n1iOlii) & n1iOl0O) & (~ n1iOl0l)))),
		n1ilO0l = (((((((((wire_nl0O1i_dataout | (~ n1ilOOl)) | (~ n1ilOOi)) | (~ n1ilOlO)) | (~ n1ilOll)) | (~ n1ilOli)) | (~ n1ilOiO)) | (~ n1ilOil)) | (~ n1ilOii)) | n1ilO0O),
		n1ilO0O = (((((((((wire_nli1ll_dataout & (~ wire_nli1il_dataout)) & (~ wire_nli10l_dataout)) & (~ wire_nli11l_dataout)) & (~ wire_nl0OOl_dataout)) & (~ wire_nl0Oll_dataout)) & (~ wire_nl0Oil_dataout)) & (~ wire_nl0O0l_dataout)) & (~ wire_nl0O1O_dataout)) & (~ wire_nl0O1i_dataout)),
		n1ilO1i = ((((~ nl01li) & (~ nl01il)) & (~ nl01ii)) & (~ nl010l)),
		n1ilOii = (((((((((~ wire_nli1il_dataout) | wire_nli10l_dataout) | wire_nli11l_dataout) | wire_nl0OOl_dataout) | wire_nl0Oll_dataout) | wire_nl0Oil_dataout) | wire_nl0O0l_dataout) | wire_nl0O1O_dataout) | wire_nl0O1i_dataout),
		n1ilOil = ((((((((~ wire_nli10l_dataout) | wire_nli11l_dataout) | wire_nl0OOl_dataout) | wire_nl0Oll_dataout) | wire_nl0Oil_dataout) | wire_nl0O0l_dataout) | wire_nl0O1O_dataout) | wire_nl0O1i_dataout),
		n1ilOiO = (((((((~ wire_nli11l_dataout) | wire_nl0OOl_dataout) | wire_nl0Oll_dataout) | wire_nl0Oil_dataout) | wire_nl0O0l_dataout) | wire_nl0O1O_dataout) | wire_nl0O1i_dataout),
		n1ilOli = ((((((~ wire_nl0OOl_dataout) | wire_nl0Oll_dataout) | wire_nl0Oil_dataout) | wire_nl0O0l_dataout) | wire_nl0O1O_dataout) | wire_nl0O1i_dataout),
		n1ilOll = (((((~ wire_nl0Oll_dataout) | wire_nl0Oil_dataout) | wire_nl0O0l_dataout) | wire_nl0O1O_dataout) | wire_nl0O1i_dataout),
		n1ilOlO = ((((~ wire_nl0Oil_dataout) | wire_nl0O0l_dataout) | wire_nl0O1O_dataout) | wire_nl0O1i_dataout),
		n1ilOOi = (((~ wire_nl0O0l_dataout) | wire_nl0O1O_dataout) | wire_nl0O1i_dataout),
		n1ilOOl = ((~ wire_nl0O1O_dataout) | wire_nl0O1i_dataout),
		n1ilOOO = ((((((((((~ (wire_nll11l_dataout ^ wire_nli1Ol_dataout)) & (~ (wire_nll11O_dataout ^ wire_nli1OO_dataout))) & (~ (wire_nll10i_dataout ^ wire_nli01i_dataout))) & (~ (wire_nll10l_dataout ^ wire_nli01l_dataout))) & (~ (wire_nll10O_dataout ^ wire_nli01O_dataout))) & (~ (wire_nll1ii_dataout ^ wire_nli00i_dataout))) & (~ (wire_nll1il_dataout ^ wire_nli00l_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nli00O_dataout))) & (~ (wire_nll1li_dataout ^ wire_nli0ii_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nli0il_dataout))),
		n1iO01i = ((((((((((~ (nlllii ^ wire_nll11l_dataout)) & (~ (nlllil ^ wire_nll11O_dataout))) & (~ (nllliO ^ wire_nll10i_dataout))) & (~ (nlllli ^ wire_nll10l_dataout))) & (~ (nlllll ^ wire_nll10O_dataout))) & (~ (nllllO ^ wire_nll1ii_dataout))) & (~ (nlllOi ^ wire_nll1il_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nliO1i_dataout))) & (~ (wire_nll1li_dataout ^ wire_nliO1l_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nliO1O_dataout))),
		n1iO01l = ((((((((((~ (comp_pat[0] ^ nlllii)) & (~ (comp_pat[1] ^ nlllil))) & (~ (comp_pat[2] ^ nllliO))) & (~ (comp_pat[3] ^ nlllli))) & (~ (comp_pat[4] ^ nlllll))) & (~ (comp_pat[5] ^ nllllO))) & (~ (comp_pat[6] ^ nlllOi))) & (~ (wire_nll0ii_dataout ^ wire_nliO1i_dataout))) & (~ (wire_nll0il_dataout ^ wire_nliO1l_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nliO1O_dataout))),
		n1iO0iO = ((((((((((~ (nlllil ^ wire_nll11l_dataout)) & (~ (nllliO ^ wire_nll11O_dataout))) & (~ (nlllli ^ wire_nll10i_dataout))) & (~ (nlllll ^ wire_nll10l_dataout))) & (~ (nllllO ^ wire_nll10O_dataout))) & (~ (nlllOi ^ wire_nll1ii_dataout))) & (~ (nlllOl ^ wire_nll1il_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nliO0l_dataout))) & (~ (wire_nll1li_dataout ^ wire_nliO0O_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nliOii_dataout))),
		n1iO0li = ((((((((((~ (comp_pat[0] ^ nlllil)) & (~ (comp_pat[1] ^ nllliO))) & (~ (comp_pat[2] ^ nlllli))) & (~ (comp_pat[3] ^ nlllll))) & (~ (comp_pat[4] ^ nllllO))) & (~ (comp_pat[5] ^ nlllOi))) & (~ (comp_pat[6] ^ nlllOl))) & (~ (wire_nll0ii_dataout ^ wire_nliO0l_dataout))) & (~ (wire_nll0il_dataout ^ wire_nliO0O_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nliOii_dataout))),
		n1iO10i = ((((((((((~ (nlll1O ^ wire_nll11l_dataout)) & (~ (nlll0i ^ wire_nll11O_dataout))) & (~ (nlll0l ^ wire_nll10i_dataout))) & (~ (nlll0O ^ wire_nll10l_dataout))) & (~ (nlllii ^ wire_nll10O_dataout))) & (~ (nlllil ^ wire_nll1ii_dataout))) & (~ (nllliO ^ wire_nll1il_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nliiOO_dataout))) & (~ (wire_nll1li_dataout ^ wire_nlil1i_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nlil1l_dataout))),
		n1iO10l = ((((((((((~ (comp_pat[0] ^ nlll1O)) & (~ (comp_pat[1] ^ nlll0i))) & (~ (comp_pat[2] ^ nlll0l))) & (~ (comp_pat[3] ^ nlll0O))) & (~ (comp_pat[4] ^ nlllii))) & (~ (comp_pat[5] ^ nlllil))) & (~ (comp_pat[6] ^ nllliO))) & (~ (wire_nll0ii_dataout ^ wire_nliiOO_dataout))) & (~ (wire_nll0il_dataout ^ wire_nlil1i_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nlil1l_dataout))),
		n1iO10O = ((((((((((~ (nlll0i ^ wire_nll11l_dataout)) & (~ (nlll0l ^ wire_nll11O_dataout))) & (~ (nlll0O ^ wire_nll10i_dataout))) & (~ (nlllii ^ wire_nll10l_dataout))) & (~ (nlllil ^ wire_nll10O_dataout))) & (~ (nllliO ^ wire_nll1ii_dataout))) & (~ (nlllli ^ wire_nll1il_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nlil0i_dataout))) & (~ (wire_nll1li_dataout ^ wire_nlil0l_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nlil0O_dataout))),
		n1iO11i = ((((((((((~ (comp_pat[0] ^ wire_nli1Ol_dataout)) & (~ (comp_pat[1] ^ wire_nli1OO_dataout))) & (~ (comp_pat[2] ^ wire_nli01i_dataout))) & (~ (comp_pat[3] ^ wire_nli01l_dataout))) & (~ (comp_pat[4] ^ wire_nli01O_dataout))) & (~ (comp_pat[5] ^ wire_nli00i_dataout))) & (~ (comp_pat[6] ^ wire_nli00l_dataout))) & (~ (wire_nll0ii_dataout ^ wire_nli00O_dataout))) & (~ (wire_nll0il_dataout ^ wire_nli0ii_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nli0il_dataout))),
		n1iO11l = ((((((((((~ (wire_nll11l_dataout ^ wire_nlii0i_dataout)) & (~ (wire_nll11O_dataout ^ wire_nlii0l_dataout))) & (~ (wire_nll10i_dataout ^ wire_nlii0O_dataout))) & (~ (wire_nll10l_dataout ^ wire_nliiii_dataout))) & (~ (wire_nll10O_dataout ^ wire_nliiil_dataout))) & (~ (wire_nll1ii_dataout ^ wire_nliiiO_dataout))) & (~ (wire_nll1il_dataout ^ wire_nliili_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nliill_dataout))) & (~ (wire_nll1li_dataout ^ wire_nliilO_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nliiOi_dataout))),
		n1iO11O = ((((((((((~ (comp_pat[0] ^ wire_nlii0i_dataout)) & (~ (comp_pat[1] ^ wire_nlii0l_dataout))) & (~ (comp_pat[2] ^ wire_nlii0O_dataout))) & (~ (comp_pat[3] ^ wire_nliiii_dataout))) & (~ (comp_pat[4] ^ wire_nliiil_dataout))) & (~ (comp_pat[5] ^ wire_nliiiO_dataout))) & (~ (comp_pat[6] ^ wire_nliili_dataout))) & (~ (wire_nll0ii_dataout ^ wire_nliill_dataout))) & (~ (wire_nll0il_dataout ^ wire_nliilO_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nliiOi_dataout))),
		n1iO1ii = ((((((((((~ (comp_pat[0] ^ nlll0i)) & (~ (comp_pat[1] ^ nlll0l))) & (~ (comp_pat[2] ^ nlll0O))) & (~ (comp_pat[3] ^ nlllii))) & (~ (comp_pat[4] ^ nlllil))) & (~ (comp_pat[5] ^ nllliO))) & (~ (comp_pat[6] ^ nlllli))) & (~ (wire_nll0ii_dataout ^ wire_nlil0i_dataout))) & (~ (wire_nll0il_dataout ^ wire_nlil0l_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nlil0O_dataout))),
		n1iO1il = ((((((((((~ (nlll0l ^ wire_nll11l_dataout)) & (~ (nlll0O ^ wire_nll11O_dataout))) & (~ (nlllii ^ wire_nll10i_dataout))) & (~ (nlllil ^ wire_nll10l_dataout))) & (~ (nllliO ^ wire_nll10O_dataout))) & (~ (nlllli ^ wire_nll1ii_dataout))) & (~ (nlllll ^ wire_nll1il_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nlilil_dataout))) & (~ (wire_nll1li_dataout ^ wire_nliliO_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nlilli_dataout))),
		n1iO1iO = ((((((((((~ (comp_pat[0] ^ nlll0l)) & (~ (comp_pat[1] ^ nlll0O))) & (~ (comp_pat[2] ^ nlllii))) & (~ (comp_pat[3] ^ nlllil))) & (~ (comp_pat[4] ^ nllliO))) & (~ (comp_pat[5] ^ nlllli))) & (~ (comp_pat[6] ^ nlllll))) & (~ (wire_nll0ii_dataout ^ wire_nlilil_dataout))) & (~ (wire_nll0il_dataout ^ wire_nliliO_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nlilli_dataout))),
		n1iO1li = ((((((((((~ (nlll0O ^ wire_nll11l_dataout)) & (~ (nlllii ^ wire_nll11O_dataout))) & (~ (nlllil ^ wire_nll10i_dataout))) & (~ (nllliO ^ wire_nll10l_dataout))) & (~ (nlllli ^ wire_nll10O_dataout))) & (~ (nlllll ^ wire_nll1ii_dataout))) & (~ (nllllO ^ wire_nll1il_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nlillO_dataout))) & (~ (wire_nll1li_dataout ^ wire_nlilOi_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nlilOl_dataout))),
		n1iO1ll = ((((((((((~ (comp_pat[0] ^ nlll0O)) & (~ (comp_pat[1] ^ nlllii))) & (~ (comp_pat[2] ^ nlllil))) & (~ (comp_pat[3] ^ nllliO))) & (~ (comp_pat[4] ^ nlllli))) & (~ (comp_pat[5] ^ nlllll))) & (~ (comp_pat[6] ^ nllllO))) & (~ (wire_nll0ii_dataout ^ wire_nlillO_dataout))) & (~ (wire_nll0il_dataout ^ wire_nlilOi_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nlilOl_dataout))),
		n1iOi0i = ((((((((((~ (nllliO ^ wire_nll11l_dataout)) & (~ (nlllli ^ wire_nll11O_dataout))) & (~ (nlllll ^ wire_nll10i_dataout))) & (~ (nllllO ^ wire_nll10l_dataout))) & (~ (nlllOi ^ wire_nll10O_dataout))) & (~ (nlllOl ^ wire_nll1ii_dataout))) & (~ (nlllOO ^ wire_nll1il_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nliOiO_dataout))) & (~ (wire_nll1li_dataout ^ wire_nliOli_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nliOll_dataout))),
		n1iOi0l = ((((((((((~ (comp_pat[0] ^ nllliO)) & (~ (comp_pat[1] ^ nlllli))) & (~ (comp_pat[2] ^ nlllll))) & (~ (comp_pat[3] ^ nllllO))) & (~ (comp_pat[4] ^ nlllOi))) & (~ (comp_pat[5] ^ nlllOl))) & (~ (comp_pat[6] ^ nlllOO))) & (~ (wire_nll0ii_dataout ^ wire_nliOiO_dataout))) & (~ (wire_nll0il_dataout ^ wire_nliOli_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nliOll_dataout))),
		n1iOili = ((((((((((~ (nlllli ^ wire_nll11l_dataout)) & (~ (nlllll ^ wire_nll11O_dataout))) & (~ (nllllO ^ wire_nll10i_dataout))) & (~ (nlllOi ^ wire_nll10l_dataout))) & (~ (nlllOl ^ wire_nll10O_dataout))) & (~ (nlllOO ^ wire_nll1ii_dataout))) & (~ (nllO1i ^ wire_nll1il_dataout))) & (~ (wire_nll1iO_dataout ^ wire_nliOOi_dataout))) & (~ (wire_nll1li_dataout ^ wire_nliOOl_dataout))) & (~ (wire_nll1ll_dataout ^ wire_nliOOO_dataout))),
		n1iOill = ((((((((((~ (comp_pat[0] ^ nlllli)) & (~ (comp_pat[1] ^ nlllll))) & (~ (comp_pat[2] ^ nllllO))) & (~ (comp_pat[3] ^ nlllOi))) & (~ (comp_pat[4] ^ nlllOl))) & (~ (comp_pat[5] ^ nlllOO))) & (~ (comp_pat[6] ^ nllO1i))) & (~ (wire_nll0ii_dataout ^ wire_nliOOi_dataout))) & (~ (wire_nll0il_dataout ^ wire_nliOOl_dataout))) & (~ (wire_nll0iO_dataout ^ wire_nliOOO_dataout))),
		n1iOilO = ((~ comp_pat_size[0]) & (~ comp_pat_size[1])),
		n1iOiOi = (comp_pat_size[0] & (~ comp_pat_size[1])),
		n1iOl0i = (nlOli1l & (~ n1iOllO)),
		n1iOl0l = (((((~ n1ilOOl) | (~ n1ilOlO)) | (~ n1ilOli)) | (~ n1ilOil)) | n1ilO0O),
		n1iOl0O = (((((~ n1ilOOi) | (~ n1ilOlO)) | (~ n1ilOiO)) | (~ n1ilOil)) | (~ n1ilO0l)),
		n1iOlii = (((((~ n1ilOOi) | (~ n1ilOlO)) | (~ n1ilOll)) | (~ n1ilOli)) | (~ n1ilO0l)),
		n1iOlil = ((wire_nl0O1i_dataout | (~ n1ilOOl)) | (~ n1ilO0l)),
		n1iOliO = ((nlOli1l & n1iOllO) & (n1iOlli16 ^ n1iOlli15)),
		n1iOllO = (((n1iOlil & n1iOlii) & n1iOl0O) & (~ n1iOl0l)),
		n1iOlOO = ((~ disable_rx_disp) & (((((~ niO11i) & ((((((n1ill0i | n1ill1O) | n1ill1l) | (n1ill1i & n1iliOO)) | (n1iliOl & n1iliOi)) | n1ililO) | n1ilill)) | (niO11i & (n1ilili | ((~ wire_nl1l1i_o) & n1iliiO)))) | ((n1iliil | (n1iliii | n1ili0O)) & (~ wire_n11i0l_dataout))) | ((n1ili0l | (wire_nl1l0l_o & (wire_nl1l0i_o & n1ili0i))) & wire_n11i0l_dataout))),
		n1iOO0i = 1'b0,
		n1iOO0l = ((~ pmadwidth[0]) & pmadwidth[1]),
		n1iOO0O = (((~ pmadwidth[0]) & pmadwidth[1]) & (n1iOlOi14 ^ n1iOlOi13)),
		n1iOO1i = (((pmadwidth[0] & (sync_sm_dis & nl01ll)) | ((~ pmadwidth[0]) & (sync_sm_dis & niO0Ol))) | ((~ sync_sm_dis) & nlOiOii)),
		n1iOOOi = (n010lli | n010liO),
		n1iOOOl = (n0000l | n0000i),
		n1iOOOO = (((((((n10OiOO & n11lOil) | (n101OOi & n11lOii)) | (n10llOl & n11lO0O)) | (n1010iO & n11lO0l)) | (n10iOOi & n11lO0i)) | (n11O01O & n11lO1O)) | (n100l1l & n11lO1l)),
		n1l111l = 1'b1,
		nlOOiOOl = (wire_nl0100O_o & wire_nl0100l_o),
		nlOOiOOO = ((~ wire_nl0100O_o) & (~ wire_nl0100l_o)),
		nlOOl00i = (((((((~ wire_nl010Ol_o) & ((~ wire_nl010Oi_o) & (wire_nl010lO_o & wire_nl010ll_o))) | ((~ wire_nl010Ol_o) & (wire_nl010Oi_o & nlOOl01i))) | ((~ wire_nl010Ol_o) & (wire_nl010Oi_o & nlOOl1OO))) | (wire_nl010Ol_o & ((~ wire_nl010Oi_o) & nlOOl01i))) | (wire_nl010Ol_o & ((~ wire_nl010Oi_o) & nlOOl1OO))) | (wire_nl010Ol_o & (wire_nl010Oi_o & ((~ wire_nl010lO_o) & (~ wire_nl010ll_o))))),
		nlOOl00l = (nlOOl0ll | nlOOli1O),
		nlOOl00O = (wire_nl0100O_o & wire_nl0100l_o),
		nlOOl01i = ((~ wire_nl010lO_o) & wire_nl010ll_o),
		nlOOl01l = (wire_nl010Oi_o ^ wire_nl010ll_o),
		nlOOl01O = ((~ wire_nl010lO_o) & ((~ wire_nl010ll_o) & nlOOl00i)),
		nlOOl0ii = ((~ wire_nl0100O_o) & (~ wire_nl0100l_o)),
		nlOOl0il = (wire_nl0100O_o & (~ wire_nl0100l_o)),
		nlOOl0iO = ((~ wire_nl0100O_o) & wire_nl0100l_o),
		nlOOl0li = (((((~ wire_nl010Ol_o) & ((~ wire_nl010Oi_o) & ((~ wire_nl010lO_o) & wire_nl010ll_o))) | ((~ wire_nl010Ol_o) & ((~ wire_nl010Oi_o) & (wire_nl010lO_o & (~ wire_nl010ll_o))))) | ((~ wire_nl010Ol_o) & (wire_nl010Oi_o & nlOOl1Ol))) | (wire_nl010Ol_o & ((~ wire_nl010Oi_o) & nlOOl1Ol))),
		nlOOl0ll = (((((~ wire_nl010Ol_o) & (wire_nl010Oi_o & nlOOl1Oi)) | (wire_nl010Ol_o & ((~ wire_nl010Oi_o) & nlOOl1Oi))) | (wire_nl010Ol_o & (wire_nl010Oi_o & ((~ wire_nl010lO_o) & wire_nl010ll_o)))) | (wire_nl010Ol_o & (wire_nl010Oi_o & (wire_nl010lO_o & (~ wire_nl010ll_o))))),
		nlOOl0lO = (((~ wire_n1l1O0l_dataout) & nlOOl10l) | (wire_n1l1O0l_dataout & nlOOl1ll)),
		nlOOl0Oi = (((((~ wire_nl010il_o) & (wire_nl010ii_o & nlOOiOOl)) | (wire_nl010il_o & ((~ wire_nl010ii_o) & nlOOiOOl))) | (wire_nl010il_o & (wire_nl010ii_o & ((~ wire_nl0100O_o) & wire_nl0100l_o)))) | (wire_nl010il_o & (wire_nl010ii_o & (wire_nl0100O_o & (~ wire_nl0100l_o))))),
		nlOOl0Ol = (((((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & ((~ wire_nl0100O_o) & wire_nl0100l_o))) | ((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & (wire_nl0100O_o & (~ wire_nl0100l_o))))) | ((~ wire_nl010il_o) & (wire_nl010ii_o & nlOOiOOO))) | (wire_nl010il_o & ((~ wire_nl010ii_o) & nlOOiOOO))),
		nlOOl0OO = ((~ wire_nl010li_o) & ((~ wire_nl010iO_o) & ((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & (wire_nl0100O_o & wire_nl0100l_o))))),
		nlOOl10i = ((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & ((~ wire_nl0100O_o) & (~ wire_nl0100l_o)))),
		nlOOl10l = (wire_nl010li_o & wire_nl010iO_o),
		nlOOl10O = (wire_nl010il_o & (wire_nl010ii_o & (wire_nl0100O_o & wire_nl0100l_o))),
		nlOOl11i = (wire_nl0100O_o & (~ wire_nl0100l_o)),
		nlOOl11l = ((~ wire_nl0100O_o) & wire_nl0100l_o),
		nlOOl11O = (nlOOl0Ol & nlOOl10l),
		nlOOl1ii = (nlOOl0Oi & nlOOl1ll),
		nlOOl1il = ((((nlOOliiO | (nlOOl1lO & nlOOl10l)) | (nlOOl0Oi & nlOOl1li)) | nlOOliil) | nlOOlili),
		nlOOl1iO = (wire_nl010il_o & nlOOl11O),
		nlOOl1li = (((~ wire_nl010li_o) & wire_nl010iO_o) | (wire_nl010li_o & (~ wire_nl010iO_o))),
		nlOOl1ll = ((~ wire_nl010li_o) & (~ wire_nl010iO_o)),
		nlOOl1lO = (((((((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & (wire_nl0100O_o & wire_nl0100l_o))) | ((~ wire_nl010il_o) & (wire_nl010ii_o & nlOOl11l))) | ((~ wire_nl010il_o) & (wire_nl010ii_o & nlOOl11i))) | (wire_nl010il_o & ((~ wire_nl010ii_o) & nlOOl11l))) | (wire_nl010il_o & ((~ wire_nl010ii_o) & nlOOl11i))) | (wire_nl010il_o & (wire_nl010ii_o & ((~ wire_nl0100O_o) & (~ wire_nl0100l_o))))),
		nlOOl1Oi = (wire_nl010lO_o & wire_nl010ll_o),
		nlOOl1Ol = ((~ wire_nl010lO_o) & (~ wire_nl010ll_o)),
		nlOOl1OO = (wire_nl010lO_o & (~ wire_nl010ll_o)),
		nlOOli0i = (nlOOl0Ol & nlOOl1ll),
		nlOOli0l = (nlOOl10i & nlOOl1ll),
		nlOOli0O = (nlOOl10i & nlOOl1li),
		nlOOli1i = (wire_nl010li_o & (wire_nl010iO_o & (wire_nl010il_o & (wire_nl010ii_o & ((~ wire_nl0100O_o) & (~ wire_nl0100l_o)))))),
		nlOOli1l = ((~ wire_nl010Ol_o) & ((~ wire_nl010Oi_o) & ((~ wire_nl010lO_o) & (~ wire_nl010ll_o)))),
		nlOOli1O = (wire_nl010Ol_o & (wire_nl010Oi_o & (wire_nl010lO_o & wire_nl010ll_o))),
		nlOOliii = (nlOOl10i & nlOOl10l),
		nlOOliil = (nlOOl10O & nlOOl1li),
		nlOOliiO = ((nlOOl10O & nlOOl10l) | (nlOOl0Oi & nlOOl10l)),
		nlOOlili = (nlOOl10O & nlOOl1ll),
		nlOOlill = ((~ wire_nl010Ol_o) & (~ wire_nl010Oi_o)),
		nlOOlilO = (((((((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & (wire_nl0100O_o & wire_nl0100l_o))) | ((~ wire_nl010il_o) & (wire_nl010ii_o & nlOOl0iO))) | ((~ wire_nl010il_o) & (wire_nl010ii_o & nlOOl0il))) | (wire_nl010il_o & ((~ wire_nl010ii_o) & nlOOl0iO))) | (wire_nl010il_o & ((~ wire_nl010ii_o) & nlOOl0il))) | (wire_nl010il_o & (wire_nl010ii_o & ((~ wire_nl0100O_o) & (~ wire_nl0100l_o))))),
		nlOOliOi = ((~ wire_nl010lO_o) & (~ wire_nl010ll_o)),
		nlOOliOl = (wire_nl010lO_o & wire_nl010ll_o),
		nlOOliOO = ((wire_nl010li_o & (wire_nl010iO_o & (wire_nl010il_o & wire_nl010ii_o))) | ((~ wire_nl010li_o) & ((~ wire_nl010iO_o) & ((~ wire_nl010il_o) & (~ wire_nl010ii_o))))),
		nlOOll0i = (((((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & ((~ wire_nl0100O_o) & wire_nl0100l_o))) | ((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & (wire_nl0100O_o & (~ wire_nl0100l_o))))) | ((~ wire_nl010il_o) & (wire_nl010ii_o & nlOOl0ii))) | (wire_nl010il_o & ((~ wire_nl010ii_o) & nlOOl0ii))),
		nlOOll0l = ((~ wire_nl010il_o) & ((~ wire_nl010ii_o) & ((~ wire_nl0100O_o) & (~ wire_nl0100l_o)))),
		nlOOll0O = (wire_nl010il_o & (wire_nl010ii_o & (wire_nl0100O_o & wire_nl0100l_o))),
		nlOOll1i = ((~ wire_nl010li_o) & wire_nl010iO_o),
		nlOOll1l = (wire_nl010li_o & (~ wire_nl010iO_o)),
		nlOOll1O = (((((~ wire_nl010il_o) & (wire_nl010ii_o & nlOOl00O)) | (wire_nl010il_o & ((~ wire_nl010ii_o) & nlOOl00O))) | (wire_nl010il_o & (wire_nl010ii_o & ((~ wire_nl0100O_o) & wire_nl0100l_o)))) | (wire_nl010il_o & (wire_nl010ii_o & (wire_nl0100O_o & (~ wire_nl0100l_o))))),
		nlOOllii = ((ib_invalid_code[0] & ((((~ wire_nl010lO_o) & nlOOli1i) & nlOOl01l) | ((wire_nl010lO_o & nlOOl0OO) & nlOOl01l))) | (ib_invalid_code[1] & ((wire_nl010Oi_o & (wire_nl010lO_o & (nlOOli1i & nlOOl00i))) | ((~ wire_nl010Oi_o) & ((~ wire_nl010lO_o) & (nlOOl0OO & nlOOl00i)))))),
		nlOOllil = (wire_nl01i1i_o & wire_nl010OO_o),
		nlOOlliO = ((~ wire_nl01i1i_o) & (~ wire_nl010OO_o)),
		nlOOllli = (wire_nl01i1i_o & (~ wire_nl010OO_o)),
		nlOOllll = ((~ wire_nl01i1i_o) & wire_nl010OO_o),
		nlOOlllO = (nlOOO1il & nlOOllOl),
		nlOOllOi = ((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & ((~ wire_nl01i1i_o) & (~ wire_nl010OO_o)))),
		nlOOllOl = (wire_nl01i0l_o & wire_nl01i0i_o),
		nlOOllOO = (wire_nl01i1O_o & (wire_nl01i1l_o & (wire_nl01i1i_o & wire_nl010OO_o))),
		nlOOlO0i = (((~ wire_nl01i0l_o) & wire_nl01i0i_o) | (wire_nl01i0l_o & (~ wire_nl01i0i_o))),
		nlOOlO0l = ((~ wire_nl01i0l_o) & (~ wire_nl01i0i_o)),
		nlOOlO0O = (((((((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & (wire_nl01i1i_o & wire_nl010OO_o))) | ((~ wire_nl01i1O_o) & (wire_nl01i1l_o & nlOOllll))) | ((~ wire_nl01i1O_o) & (wire_nl01i1l_o & nlOOllli))) | (wire_nl01i1O_o & ((~ wire_nl01i1l_o) & nlOOllll))) | (wire_nl01i1O_o & ((~ wire_nl01i1l_o) & nlOOllli))) | (wire_nl01i1O_o & (wire_nl01i1l_o & ((~ wire_nl01i1i_o) & (~ wire_nl010OO_o))))),
		nlOOlO1i = (nlOOO1ii & nlOOlO0l),
		nlOOlO1l = ((((nlOOO01O | (nlOOlO0O & nlOOllOl)) | (nlOOO1ii & nlOOlO0i)) | nlOOO01l) | nlOOO00i),
		nlOOlO1O = (wire_nl01i1O_o & nlOOlllO),
		nlOOlOii = (wire_nl01iii_o & wire_nl01i0O_o),
		nlOOlOil = ((~ wire_nl01iii_o) & (~ wire_nl01i0O_o)),
		nlOOlOiO = (wire_nl01iii_o & (~ wire_nl01i0O_o)),
		nlOOlOli = ((~ wire_nl01iii_o) & wire_nl01i0O_o),
		nlOOlOll = (wire_nl01iil_o ^ wire_nl01i0O_o),
		nlOOlOlO = ((~ wire_nl01iii_o) & ((~ wire_nl01i0O_o) & nlOOlOOi)),
		nlOOlOOi = (((((((~ wire_nl01iiO_o) & ((~ wire_nl01iil_o) & (wire_nl01iii_o & wire_nl01i0O_o))) | ((~ wire_nl01iiO_o) & (wire_nl01iil_o & nlOOlOli))) | ((~ wire_nl01iiO_o) & (wire_nl01iil_o & nlOOlOiO))) | (wire_nl01iiO_o & ((~ wire_nl01iil_o) & nlOOlOli))) | (wire_nl01iiO_o & ((~ wire_nl01iil_o) & nlOOlOiO))) | (wire_nl01iiO_o & (wire_nl01iil_o & ((~ wire_nl01iii_o) & (~ wire_nl01i0O_o))))),
		nlOOlOOl = (nlOOO10l | nlOOO1lO),
		nlOOlOOO = (wire_nl01i1i_o & wire_nl010OO_o),
		nlOOO00i = (nlOOllOO & nlOOlO0l),
		nlOOO00l = ((~ wire_nl01iiO_o) & (~ wire_nl01iil_o)),
		nlOOO00O = (((((((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & (wire_nl01i1i_o & wire_nl010OO_o))) | ((~ wire_nl01i1O_o) & (wire_nl01i1l_o & nlOOO11O))) | ((~ wire_nl01i1O_o) & (wire_nl01i1l_o & nlOOO11l))) | (wire_nl01i1O_o & ((~ wire_nl01i1l_o) & nlOOO11O))) | (wire_nl01i1O_o & ((~ wire_nl01i1l_o) & nlOOO11l))) | (wire_nl01i1O_o & (wire_nl01i1l_o & ((~ wire_nl01i1i_o) & (~ wire_nl010OO_o))))),
		nlOOO01i = (nlOOllOi & nlOOllOl),
		nlOOO01l = (nlOOllOO & nlOOlO0i),
		nlOOO01O = ((nlOOllOO & nlOOllOl) | (nlOOO1ii & nlOOllOl)),
		nlOOO0ii = ((~ wire_nl01iii_o) & (~ wire_nl01i0O_o)),
		nlOOO0il = (wire_nl01iii_o & wire_nl01i0O_o),
		nlOOO0iO = ((wire_nl01i0l_o & (wire_nl01i0i_o & (wire_nl01i1O_o & wire_nl01i1l_o))) | ((~ wire_nl01i0l_o) & ((~ wire_nl01i0i_o) & ((~ wire_nl01i1O_o) & (~ wire_nl01i1l_o))))),
		nlOOO0li = ((~ wire_nl01i0l_o) & wire_nl01i0i_o),
		nlOOO0ll = (wire_nl01i0l_o & (~ wire_nl01i0i_o)),
		nlOOO0lO = (((((~ wire_nl01i1O_o) & (wire_nl01i1l_o & nlOOlOOO)) | (wire_nl01i1O_o & ((~ wire_nl01i1l_o) & nlOOlOOO))) | (wire_nl01i1O_o & (wire_nl01i1l_o & ((~ wire_nl01i1i_o) & wire_nl010OO_o)))) | (wire_nl01i1O_o & (wire_nl01i1l_o & (wire_nl01i1i_o & (~ wire_nl010OO_o))))),
		nlOOO0Oi = (((((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & ((~ wire_nl01i1i_o) & wire_nl010OO_o))) | ((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & (wire_nl01i1i_o & (~ wire_nl010OO_o))))) | ((~ wire_nl01i1O_o) & (wire_nl01i1l_o & nlOOO11i))) | (wire_nl01i1O_o & ((~ wire_nl01i1l_o) & nlOOO11i))),
		nlOOO0Ol = ((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & ((~ wire_nl01i1i_o) & (~ wire_nl010OO_o)))),
		nlOOO0OO = (wire_nl01i1O_o & (wire_nl01i1l_o & (wire_nl01i1i_o & wire_nl010OO_o))),
		nlOOO10i = (((((~ wire_nl01iiO_o) & ((~ wire_nl01iil_o) & ((~ wire_nl01iii_o) & wire_nl01i0O_o))) | ((~ wire_nl01iiO_o) & ((~ wire_nl01iil_o) & (wire_nl01iii_o & (~ wire_nl01i0O_o))))) | ((~ wire_nl01iiO_o) & (wire_nl01iil_o & nlOOlOil))) | (wire_nl01iiO_o & ((~ wire_nl01iil_o) & nlOOlOil))),
		nlOOO10l = (((((~ wire_nl01iiO_o) & (wire_nl01iil_o & nlOOlOii)) | (wire_nl01iiO_o & ((~ wire_nl01iil_o) & nlOOlOii))) | (wire_nl01iiO_o & (wire_nl01iil_o & ((~ wire_nl01iii_o) & wire_nl01i0O_o)))) | (wire_nl01iiO_o & (wire_nl01iil_o & (wire_nl01iii_o & (~ wire_nl01i0O_o))))),
		nlOOO10O = (((~ wire_n1O010l_dataout) & nlOOllOl) | (wire_n1O010l_dataout & nlOOlO0l)),
		nlOOO11i = ((~ wire_nl01i1i_o) & (~ wire_nl010OO_o)),
		nlOOO11l = (wire_nl01i1i_o & (~ wire_nl010OO_o)),
		nlOOO11O = ((~ wire_nl01i1i_o) & wire_nl010OO_o),
		nlOOO1ii = (((((~ wire_nl01i1O_o) & (wire_nl01i1l_o & nlOOllil)) | (wire_nl01i1O_o & ((~ wire_nl01i1l_o) & nlOOllil))) | (wire_nl01i1O_o & (wire_nl01i1l_o & ((~ wire_nl01i1i_o) & wire_nl010OO_o)))) | (wire_nl01i1O_o & (wire_nl01i1l_o & (wire_nl01i1i_o & (~ wire_nl010OO_o))))),
		nlOOO1il = (((((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & ((~ wire_nl01i1i_o) & wire_nl010OO_o))) | ((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & (wire_nl01i1i_o & (~ wire_nl010OO_o))))) | ((~ wire_nl01i1O_o) & (wire_nl01i1l_o & nlOOlliO))) | (wire_nl01i1O_o & ((~ wire_nl01i1l_o) & nlOOlliO))),
		nlOOO1iO = ((~ wire_nl01i0l_o) & ((~ wire_nl01i0i_o) & ((~ wire_nl01i1O_o) & ((~ wire_nl01i1l_o) & (wire_nl01i1i_o & wire_nl010OO_o))))),
		nlOOO1li = (wire_nl01i0l_o & (wire_nl01i0i_o & (wire_nl01i1O_o & (wire_nl01i1l_o & ((~ wire_nl01i1i_o) & (~ wire_nl010OO_o)))))),
		nlOOO1ll = ((~ wire_nl01iiO_o) & ((~ wire_nl01iil_o) & ((~ wire_nl01iii_o) & (~ wire_nl01i0O_o)))),
		nlOOO1lO = (wire_nl01iiO_o & (wire_nl01iil_o & (wire_nl01iii_o & wire_nl01i0O_o))),
		nlOOO1Oi = (nlOOO1il & nlOOlO0l),
		nlOOO1Ol = (nlOOllOi & nlOOlO0l),
		nlOOO1OO = (nlOOllOi & nlOOlO0i),
		nlOOOi0i = (n010iOl | n010iOi),
		nlOOOi0l = ((((n010l1i | n010iOO) | n010iOl) | n010iOi) | n010ilO),
		nlOOOi0O = ((((n010l1i | n010iOO) | n010ill) | n010ili) | n011l0O),
		nlOOOi1i = ((ib_invalid_code[0] & ((((~ wire_nl01iii_o) & nlOOO1li) & nlOOlOll) | ((wire_nl01iii_o & nlOOO1iO) & nlOOlOll))) | (ib_invalid_code[1] & ((wire_nl01iil_o & (wire_nl01iii_o & (nlOOO1li & nlOOlOOi))) | ((~ wire_nl01iil_o) & ((~ wire_nl01iii_o) & (nlOOO1iO & nlOOlOOi)))))),
		nlOOOi1l = (n010ilO | n011l0O),
		nlOOOi1O = (n010ill | n010ili),
		nlOOOiii = (n010l1i | n010iOO),
		nlOOOiil = ((~ n01iOOl) & (~ n01iOOi)),
		nlOOOiiO = ((~ n01iOOl) & n01iOOi),
		nlOOOili = (n011l0l & n011l0i),
		nlOOOill = ((~ n01li0i) & (~ n01iOOi)),
		nlOOOilO = ((~ n01li0i) & n01iOOi),
		nlOOOiOi = (((((((((~ wire_n01ilOl_dataout) & (~ wire_n01ilOi_dataout)) & (~ wire_n01illO_dataout)) & (~ wire_n01illl_dataout)) & (~ wire_n01illi_dataout)) & wire_n01iliO_dataout) & (~ wire_n01ilil_dataout)) & (~ wire_n01ilii_dataout)) & (~ nlOOOiOO)),
		nlOOOiOl = (((((((((~ wire_n01ilOl_dataout) & (~ wire_n01ilOi_dataout)) & (~ wire_n01illO_dataout)) & (~ wire_n01illl_dataout)) & (~ wire_n01illi_dataout)) & wire_n01iliO_dataout) & (~ wire_n01ilil_dataout)) & wire_n01ilii_dataout) & (~ nlOOOiOO)),
		nlOOOiOO = ((((((~ max_rlv_sel[0]) & (~ max_rlv_sel[1])) & (~ max_rlv_sel[2])) & (~ max_rlv_sel[3])) & (~ max_rlv_sel[4])) & (~ max_rlv_sel[5])),
		nlOOOl0i = (((((((((((pmadwidth[0] | (~ nllO1lO)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ nlllO1l)) | (~ wire_n01il0O_dataout)),
		nlOOOl0l = (((((((((((pmadwidth[0] | (~ nllO1lO)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ nlllO1l)) | (~ nlllO1i)) | (~ wire_n01il0O_dataout)),
		nlOOOl0O = (((((((((((pmadwidth[0] | (~ nllO1lO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ nlllO1l)) | (~ nlllO1i)) | (~ nllllOO)) | (~ wire_n01il0O_dataout)),
		nlOOOl1i = (((((((((((pmadwidth[0] | (~ nllO1lO)) | (~ nlllOlO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ wire_n01il0O_dataout)),
		nlOOOl1l = (((((((((((pmadwidth[0] | (~ nllO1lO)) | (~ nlllOOi)) | (~ nlllOlO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ wire_n01il0O_dataout)),
		nlOOOl1O = (((((((((((pmadwidth[0] | (~ nllO1lO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ wire_n01il0O_dataout)),
		nlOOOlii = (((((((((((pmadwidth[0] | (~ nllO1lO)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ nlllO1l)) | (~ nlllO1i)) | (~ nllllOO)) | (~ nllllOl)) | (~ wire_n01il0O_dataout)),
		nlOOOlil = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nllO11l)) | (~ nllO11i)) | (~ nlllOOO)) | (~ nlllOOl)) | (~ nlllOOi)) | (~ nlllOlO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ wire_n01il0O_dataout)),
		nlOOOliO = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nllO11i)) | (~ nlllOOO)) | (~ nlllOOl)) | (~ nlllOOi)) | (~ nlllOlO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ wire_n01il0O_dataout)),
		nlOOOlli = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nlllOOO)) | (~ nlllOOl)) | (~ nlllOOi)) | (~ nlllOlO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ wire_n01il0O_dataout)),
		nlOOOlll = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nlllOOl)) | (~ nlllOOi)) | (~ nlllOlO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ wire_n01il0O_dataout)),
		nlOOOllO = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nlllOOi)) | (~ nlllOlO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ wire_n01il0O_dataout)),
		nlOOOlOi = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nlllOlO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ nlllO1l)) | (~ wire_n01il0O_dataout)),
		nlOOOlOl = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nlllOll)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ nlllO1l)) | (~ nlllO1i)) | (~ wire_n01il0O_dataout)),
		nlOOOlOO = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nlllOli)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ nlllO1l)) | (~ nlllO1i)) | (~ nllllOO)) | (~ wire_n01il0O_dataout)),
		nlOOOO0i = (((((((((((pmadwidth[0] | (~ nllO1lO)) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | (~ wire_n01il0O_dataout)),
		nlOOOO0l = (((((((((((pmadwidth[0] | (~ nllO1lO)) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | (~ wire_n01il0O_dataout)),
		nlOOOO0O = (((((((((((pmadwidth[0] | (~ nllO1lO)) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | (~ wire_n01il0O_dataout)),
		nlOOOO1i = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | (~ nlllOiO)) | (~ nlllOil)) | (~ nlllOii)) | (~ nlllO0O)) | (~ nlllO0l)) | (~ nlllO0i)) | (~ nlllO1O)) | (~ nlllO1l)) | (~ nlllO1i)) | (~ nllllOO)) | (~ nllllOl)) | (~ wire_n01il0O_dataout)),
		nlOOOO1l = (((((((((((pmadwidth[0] | (~ nllO1lO)) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | (~ wire_n01il0O_dataout)),
		nlOOOO1O = (((((((((((pmadwidth[0] | (~ nllO1lO)) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | (~ wire_n01il0O_dataout)),
		nlOOOOii = (((((((((((pmadwidth[0] | (~ nllO1lO)) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | (~ wire_n01il0O_dataout)),
		nlOOOOil = (((((((((((pmadwidth[0] | (~ nllO1lO)) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | nllllOO) | nllllOl) | (~ wire_n01il0O_dataout)),
		nlOOOOiO = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nllO11l) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | (~ wire_n01il0O_dataout)),
		nlOOOOli = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nllO11i) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | (~ wire_n01il0O_dataout)),
		nlOOOOll = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nlllOOO) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | (~ wire_n01il0O_dataout)),
		nlOOOOlO = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nlllOOl) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | (~ wire_n01il0O_dataout)),
		nlOOOOOi = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nlllOOi) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | (~ wire_n01il0O_dataout)),
		nlOOOOOl = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nlllOlO) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | (~ wire_n01il0O_dataout)),
		nlOOOOOO = ((((((((((((((~ pmadwidth[0]) | (~ nllO1lO)) | nlllOll) | nlllOli) | nlllOiO) | nlllOil) | nlllOii) | nlllO0O) | nlllO0l) | nlllO0i) | nlllO1O) | nlllO1l) | nlllO1i) | (~ wire_n01il0O_dataout)),
		rlv = wire_n0Oi_dataout,
		rlv_lt = wire_n0lO_dataout,
		signal_detect_rcvdclk = signal_detect,
		sudi = {wire_n1i_dataout, wire_nlOO_dataout, wire_nlOl_dataout, wire_nlOi_dataout, wire_nllO_dataout, wire_nlll_dataout, wire_nlli_dataout, wire_nliO_dataout, wire_nlil_dataout, wire_nlii_dataout, wire_nl0O_dataout, wire_nl0l_dataout, wire_nl0i_dataout, wire_nl1O_dataout, wire_nl1l_dataout, wire_nl1i_dataout, wire_niOO_dataout, wire_niOl_dataout, wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout},
		sudi_pre = {wire_n1i1li_dataout, n1iOlOO, n1iOO1i, (~ wire_n1OOOi_dataout), wire_nl1lii_dataout, wire_nl1l0O_dataout, wire_nl1l0l_o, wire_nl1l0i_o, wire_nl1l1O_o, wire_nl1l1l_o, wire_nl1l1i_o, wire_nl1iOO_o, wire_nl1iOl_o, wire_nl1iOi_o},
		sync_status = wire_n0Ol_dataout,
		testbus = {wire_ni_dataout, wire_nlO_dataout, wire_nll_dataout, wire_nli_dataout, wire_niO_dataout, wire_nil_dataout, wire_nii_dataout, wire_n0O_dataout, wire_n0l_dataout, wire_n0i_dataout};
endmodule //arriagx_hssi_rx_wordalign
//synopsys translate_on
//VALID FILE

`timescale 1 ps /1 ps

module arriagx_hssi_rx_rxclk_ctl (pld_rx_clk, rcvd_clk_pma, rcvd_clk0_pma, tx_pma_clk, refclk_pma,
                  rxrst, rindv_rx, rx_div2_sync_in_ch0, rx_div2_sync_in_q0_ch0,
                  rdwidth_rx, rfreerun_rx, scan_mode, rphfifo_master_sel_rx,
                  rrcvd_clk_sel, rclk_1_sel, rclk_2_sel, rrx_rd_clk_sel, 
		  clk_1_b, clk_2_b, rx_rd_clk, rx_wr_clk, rx_clk, rcvd_clk, rcvd_clk_pma_b, rx_div2_sync_out
                );

input          pld_rx_clk;	       // PLD clock from clock trees
input          rcvd_clk_pma;	       // local recovered clock
input	       rcvd_clk0_pma;          // channel zero recovered clock
input          tx_pma_clk;	       // local TX PMA clock
input  [1:0]   rrcvd_clk_sel;
input  [1:0]   rclk_1_sel;
input  [1:0]   rclk_2_sel;
input          rrx_rd_clk_sel;         // Select clock for rx ph comp fifo read side
input          refclk_pma;             // Quad based clk from TXPLL
input          rxrst;                  // This is the soft_reset for the RX_PCS
input          rindv_rx;               // Select between XAUI mode or indiv  channel mode
input          rx_div2_sync_in_ch0;    // Connect from channel zero rx_div2_sync_out
input          rx_div2_sync_in_q0_ch0; // Connect from channel zero rx_div2_sync_out of Master Quad
input  	       rdwidth_rx;             // divide by 1 or 2 before feeding to FIFO write clock
input          rfreerun_rx;            // Select whether divider is permamently enabled (free -running) or
			               // divider should be enabled / reset by RX PCS reset
input          scan_mode;              // Scan mode enable signal			         
input          rphfifo_master_sel_rx;  // RX Phase comp. FIFO rx_div2_sync selection CRAM

output         rx_div2_sync_out;       // synchronizes div by 2 clock
				       // rx_div2_sync_out is a data line that drives across four channels
				       // and synchronizes the divided by two clocks across all four channels
output         rcvd_clk;
output         clk_1_b;
output         clk_2_b;
output         rx_wr_clk;              // drives the rx ph comp fifo write clock tree
output         rx_rd_clk;              // drives the rx ph comp fifo read clock tree
output         rx_clk;                 // drives the PLD clock tree
output         rcvd_clk_pma_b;

reg rx_clk_2_by2;
wire rx_div2_sync, wr_clk_before_div, rx_div2_sync_out, rx_rst_n;
wire [1:0] rrcvd_clk_sel_int, rclk_1_sel_int, rclk_2_sel_int;

// initial begin ------
initial begin
		rx_clk_2_by2 = 1'b1;
end             
// initial end   ------

// Select between the local synchronization signal or the global synchronization signal
//assign rx_div2_sync = rindv_rx ? rx_div2_sync_out : rx_div2_sync_in;
assign rx_div2_sync = (rphfifo_master_sel_rx == 1'b0) ? rx_div2_sync_in_q0_ch0 :
                      (rindv_rx == 1'b0) ? rx_div2_sync_in_ch0 : rx_div2_sync_out;

assign wr_clk_before_div = clk_2_b;

assign rx_div2_sync_out = ~rx_clk_2_by2;

// This register is used to generate divided by two clock. Div by 2 clock starts off high after reset
always @(negedge rx_rst_n or posedge clk_2_b)
begin
	if (~rx_rst_n)
		rx_clk_2_by2 <= 1'b1;
	else if (clk_2_b) 
		rx_clk_2_by2 <= rx_div2_sync;
end

// Reset for Divide-by-2
assign rx_rst_n = (rfreerun_rx) ? 1'b1 : ~rxrst;

// clocks are assigned below in the order in which they appear in the out flowing data path
// RCVD_CLK selection
assign rrcvd_clk_sel_int = (scan_mode) ? 2'b01 : rrcvd_clk_sel;
assign rcvd_clk = 	(rrcvd_clk_sel_int == 2'b00) ? rcvd_clk_pma  : 
			(rrcvd_clk_sel_int == 2'b01) ? refclk_pma : 
			(rrcvd_clk_sel_int == 2'b10) ? tx_pma_clk : 
			(rrcvd_clk_sel_int == 2'b11) ? rcvd_clk_pma : rcvd_clk_pma; 

// CLK_1 seleciton
assign rclk_1_sel_int = (scan_mode) ? 2'b01 : rclk_1_sel;
assign clk_1_b = 	(rclk_1_sel_int == 2'b00) ? rcvd_clk_pma  : 
			(rclk_1_sel_int == 2'b01) ? refclk_pma : 
			(rclk_1_sel_int == 2'b10) ? tx_pma_clk : 
			(rclk_1_sel_int == 2'b11) ? rcvd_clk0_pma : rcvd_clk_pma; 

// CLK_2 selection
assign rclk_2_sel_int = (scan_mode) ? 2'b10 : rclk_2_sel;
assign clk_2_b = 	(rclk_2_sel_int == 2'b00) ? rcvd_clk_pma : 
			(rclk_2_sel_int == 2'b01) ? tx_pma_clk : 
			(rclk_2_sel_int == 2'b10) ? refclk_pma : 
			(rclk_2_sel_int == 2'b11) ? pld_rx_clk : rcvd_clk_pma; 

// RX FIFO write clock: could be fast or divided by 2
assign rx_wr_clk = ((rdwidth_rx == 1'b0) || scan_mode) ? wr_clk_before_div : rx_clk_2_by2;

// RX FIFO read clock
assign rx_rd_clk = ((rrx_rd_clk_sel == 1'b0) || scan_mode) ? rx_wr_clk : pld_rx_clk;

// RX clock out
assign rx_clk = rx_wr_clk; // drives PLD clock tree

// Recovered clock for debugging
assign rcvd_clk_pma_b = rcvd_clk_pma; // Goes out to PLD as debug clock. This clock may or may 
				      // not be routed out to PLD fabric. TBD

endmodule

`timescale 1 ps / 1 ps

module arriagx_hssi_rx_digi ( hard_reset, rxpcs_rst, rxpma_rst, cmpfifourst, phfifourst_rx,  
		 scan_mode, encdt, a1a2_size, bitslip,   
                 rdenable_rmf, wrenable_rmf, pld_rx_clk, 
                 polinv_rx, bitloc_rev_en, byte_rev_en,
                 rcvd_clk_pma, pudi, 
                 sigdetni, fifo_rst_rd_qd, fifo_rst_rd_gp, en_dskw_qd, 
                 en_dskw_gp, is_lane0, align_status,
                 align_status_sync_0, align_status_sync_2, 
                 disable_fifo_rd_0, disable_fifo_rd_2,  
                 disable_fifo_wr_0, disable_fifo_wr_2,
                 rx_data_rs, rx_control_rs, rcvd_clk0_pma,
                 fifo_rd_in_comp_0, fifo_rd_in_comp_2,
                 txlp20b, refclk_pma, tx_pma_clk,
                 fref, clklow,
                 bytordpld, wrdisable_rx, rdenable_rx,
                 pma_testbus, encoder_testbus, tx_ctrl_testbus,
                 rxfifo_shared_sig_in_ch0, rxfifo_shared_sig_in_q0_ch0, rx_cru_pdb,
		 rxfifo_shared_sig_out, fifo_rd_out_comp, 
		 rxd, rev_loop_data, rx_clk, bisterr, cg_comma,
                 clk_2_b, rcvd_clk_pma_b, sync_status, disable_fifo_rd, 
                 disable_fifo_wr, align_status_sync,
                 dec_data_valid, dec_data, dec_ctl, running_disp, 
                 selftest_done, selftest_err, err_data,         
                 err_ctl, prbs_done, prbs_err_lt, signal_detect_out, 
                 align_det_sync, rd_align, bistdone, rlv, rlv_lt, 
                 almost_fl_rmf, full_rmf, almost_mt_rmf, empty_rmf, freq_lock,
                 full_rx, empty_rx, a1a2_k1k2_flag, byteord_flag, rx_pipe_clk,
                 chnl_test_bus_out, rx_pipe_soft_reset,
		 rskpsetbased, rtruebac2bac, ralfull, ralempty, rcmpfifourst,
                 rphfifourstrx, 
		 rcomp_size, rcomp_pat, rrundisp,         
                 rib_inv_cd, rrlv_en, rsync_sm_dis, rautobtalg_dis, 
                 rdis_rx_disp, rmatchen,         
                 rgenericfifo, rendec_rx, rdwidth_rx, 
                 rlp20ben, rrxfifo_dis,      
                 rpmadwidth_rx, rpma_doublewidth_rx,
                 renumber, rknumber, renpolinv_rx, rgnumber,
                 rclkcmpsqmd, rclkcmpsq1p, rclkcmpsq1n, rclkcmppos, 
                 rosnumber, rosbased, rkchar, 
                 rcascaded_8b10b_en_rx, resync_badcg_en, rencdt_rising,
                 rcomp_pat_porn,       
		 rprbsen_rx, rprbs_clr_rslt_rx, rbisten_rx, rbist_clr_rx,      
		 rwa_6g_en, rbitslip_size, rbytord_2sym_en, rbysync_polinv_en,   
		 rbitloc_rev_en, rbyte_rev_en, rbyteorden,           
		 rbytordplden, rphfifopldenrx, rautoinsdis, rppmsel, 
                 rforce0_freqdet, rforce1_freqdet,
		 rbytordpat, rbytordpad, rforce_sig_det_pcs,
		 rfreerun_rx, rrcvd_clk_sel, rclk_1_sel, rclk_2_sel, 
                 rrx_rd_clk_sel,   
                 rall_one_dect_only, rtest_bus_sel, r8b10b_dec_ibm_en, 
                 rrxfifo_lowlatency_en, rppm_cnt_reset, sel_gp_md, 
                 rclkcmpinsertpad, rindv_rx, 
                 dskwclksel, rdskposdisp, rdskchrp, rendec_data_sel_rx, 
                 rphfifo_master_sel_rx,
                 rprbs_sel, rbist_sel, rcxpat_chnl_en
               );


// Reset inputs
input  	       hard_reset;	      // From MDIO_REG.V Complex function of NPOR, ENTEST etc.,
input          rxpcs_rst;             // RX PCS resets
input          rxpma_rst;             // RX PMA reset for PPM Detect
input          cmpfifourst;	      // User reset exclusive to comp_chnl_top & below
input          phfifourst_rx;	      // User reset exclusive to rx_ctrl & below

// Scan inputs
input          scan_mode;             // 1'b1 = scan mode active; 
                                      // 1'b0 = normal mode
// RX PCS channel inputs/outputs
input          encdt;                 // Comma Detect enable control signal from PLD
input          a1a2_size;             // A1A2 size control signal for byte sync block
input          bitslip;               // Bitslip control signal from PLD
input          rdenable_rmf;          // Read enable control signal for CompFIFO
input          wrenable_rmf;          // Write enable control signal for CompFIFO
input          pld_rx_clk;            // Parallel receive clock from PLD
input          polinv_rx;             // RX polarity inversion dynamic control signal
input          bitloc_rev_en;         // RX bit reversal dynamic control signal
input          byte_rev_en;           // RX byte swap dynamic control signal
input          rcvd_clk_pma;
input   [19:0] pudi;                  // RX 10-bit code group bus from RX PMA
input          sigdetni;              // rx signal detected from PMA
input          fifo_rst_rd_qd;        // from master deskew sm
input          fifo_rst_rd_gp;        // from grouping deskew sm
input          en_dskw_qd;            // from master deskew sm
input          en_dskw_gp;            // from grouping deskew sm
input          is_lane0;              // This is lane 0 if 1'b1. Hard-wired
                                      // when chnl_top is instantiated
input          align_status;          // Indicate that four lanes are now 
                                      // aligned in dskw_top
input          align_status_sync_0;   // Synced to clk_2 from channel 0
input          align_status_sync_2;   // Synced to clk_2 from channel 2
input          disable_fifo_rd_0;     // disable_fifo_rd from channel 0
input          disable_fifo_rd_2;     // disable_fifo_rd from channel 2
input          disable_fifo_wr_0;     // disable_fifo_wr from channel 0
input          disable_fifo_wr_2;     // disable_fifo_wr from channel 2
input   [7:0]  rx_data_rs;            // rx data from 10G ethernet rx state machine
input          rx_control_rs;         // rx control from 10G ethernet rx state machine
input          rcvd_clk0_pma;         // Recovered clock from PMA channel0
input          fifo_rd_in_comp_0;     // fifo_rd_in_comp from channel 0
input          fifo_rd_in_comp_2;     // fifo_rd_in_comp from channel 2
input   [19:0] txlp20b;               // tx 20-bit code group bus to PMA
input          refclk_pma;            // Global parallel TX PLL clock
input          tx_pma_clk;            // Per channel TX PMA clock
input          fref;     	      // Reference clock for FREQDET module
input          clklow;                // Divided clock for FREQDET module
input          bytordpld;             // Byte ordering dynamic control signal from PLD
input          wrdisable_rx;          // RX phase comp. FIFO write disable control signal
input          rdenable_rx;           // RX phase comp. FIFO read enable control signal
input   [7:0]  pma_testbus;           // PMA digital testbus output
input   [9:0]  encoder_testbus;       // Test bus from 8B10B encoder
input   [9:0]  tx_ctrl_testbus;       // Test bus from TX FIFO
input   [3:0]  rxfifo_shared_sig_in_ch0;    // TX FIFO shared signal from channel 0
input   [3:0]  rxfifo_shared_sig_in_q0_ch0; // TX FIFO shared signal from channel 0 of Quad 0
input          rx_cru_pdb;            // RX CDR PDB signal for FREQDET module

output  [3:0]  rxfifo_shared_sig_out; // TX FIFO shared signal output
output         fifo_rd_out_comp;      
output  [63:0] rxd;                   // XGMII rx data to PLD
output  [19:0] rev_loop_data;	      // 10 bit data from RX rate matching 
                                      // FIFO, reverse loopback
output         rx_clk;                // XGMII rx clock to PLD
output         bisterr;               // BIST or PRBS done status signal
output  [1:0]  cg_comma;              // comma is detected in sync_chnl_top to PMA
output         clk_2_b;               // clk_2 to rcv_sm
output         rcvd_clk_pma_b;
output         sync_status;           // Indicate that this lane is now synchronized
output         disable_fifo_rd;       // disable_fifo_rd from this lane
output         disable_fifo_wr;       // disable_fifo_wr from this lane
output         align_status_sync;     // synced to clk_2
output         dec_data_valid;
output  [7:0]  dec_data;              // decoded 8-bit RX data to XAUI RX SM
output         dec_ctl;               // decoded RX control to XAUI RX SM
output  [1:0]  running_disp;          // indicate that dec_data/dec_ctl is 
                                      // either not valid or having disparity error
output         selftest_done;         // Status shows that the self test checking is done
output         selftest_err;          // Status shows that the selftest is successful
output  [15:0] err_data;              // When the self test fails, this records
                                      // the first byte that error occurs to.
output  [1:0]  err_ctl;               // When the self test fails, this records
                                      // the first byte that error occurs to.
output         prbs_done;             // Indicate that prbs verification is done
output         prbs_err_lt;           // Indicate that prbs verification is OK 
                                      // - latched version, cleared when reset
output         signal_detect_out;     // SIGDET out to PLD
output         align_det_sync;        // Channel is aligned, present for 10 clocks
output         rd_align;              // Read data has an Align code group
output         bistdone;
output         rlv;
output         rlv_lt;                // RLV status signal to PLD
output         almost_fl_rmf;         // Comp FIFO almost full flag
output         full_rmf;              // Comp FIFO full flag
output         almost_mt_rmf;         // Comp FIFO almost empty flag
output         empty_rmf;             // Comp FIFO empty flag
output         freq_lock;             // Frequency lock output flag for PMA
output         full_rx;               // RX Phase comp. FIFO full flag
output         empty_rx;              // RX Phase comp. FIFO empty flag
output  [3:0]  a1a2_k1k2_flag;        // A1A2K1K2 output flag
output         byteord_flag;          // Byte ordering successfull output flag
output         rx_pipe_clk;           // Output clock for RX PIPE interface
output  [9:0]  chnl_test_bus_out;     // Channel digital testbus output
output         rx_pipe_soft_reset;    // RX PIPE soft reset

// RX PCS CRAMs
input 	       rskpsetbased;	      // Enable rate matching for PCI-E/PIPE-or
                                      // other standards based on COMMA DEL DEL..
input	       rtruebac2bac;	      // Should be high for all standards 
                                      // except PIPE. Back to back rate matching enable.
input [3:0]    ralfull;		      // CRAM bits - Program when almost full goes high	
input [3:0]    ralempty;	      // CRAM bits - Program when almost empty goes high
input          rcmpfifourst;          // Enable cmpfifourst
input          rphfifourstrx;         // Enable phfifourst_rx
input   [2:0]  rcomp_size;            // Pattern comparision length CRAMs
input   [39:0] rcomp_pat;             // Sync pattern CRAMs
input   [5:0]  rrundisp;              // Run lengh violation setting CRAMs
input   [1:0]  rib_inv_cd;            // Invalid code setting CRAMs for IB
input          rrlv_en;               // RLV enable CRAM
input          rsync_sm_dis;          // GIGE/XAUI Sync SM disable CRAM
input          rautobtalg_dis;        // BITSLIP mode enable CRAM
input          rdis_rx_disp;          // Receive running disparity calculation disable CRAM
input          rmatchen;              // Clock compensation enable CRAM
input          rgenericfifo;          // GenericFIFO mode enable CRAM
input          rendec_rx;             // 10B/8B decoder enable CRAM
input          rdwidth_rx;            // RX parallel interface data width selection CRAM
input          rlp20ben;              // 20-b loopback enable CRAM
input          rrxfifo_dis;           // RX FIFO bypassing CRAM
input          rpmadwidth_rx;         // RX PMA to RX PCS data width selection CRAM
input          rpma_doublewidth_rx;   // RX PMA/PCS double width (16/20) sel CRAM
input   [2:0]  renumber;              // Number of consecutive errors without
                                      // valid data to goto LOSS_OF_SYNC
input   [7:0]  rknumber;              // Number of consecutive commas to reach 
                                      // SYNC_ACQ from LOSS_OF_SYNC
input          renpolinv_rx;          // Allow polarity inversion
input   [7:0]  rgnumber;              // Number of consecutive good data to approach SYNC_ACQ
input          rclkcmpsqmd;           // How many characters to match
input   [19:0] rclkcmpsq1p;           // Programmable 20-bit encoded comp sequence pos. disp.
input   [19:0] rclkcmpsq1n;           // Programmable 20-bit encoded comp sequence neg. disp.
input          rclkcmppos;            // Match only the pos disp. sequence 
input   [1:0]  rosnumber;             // Length of the ordered set
input          rosbased;              // Enable ordered-set based algorithm
input          rkchar;                // use kchar at cg_bad logic calculation
input          rcascaded_8b10b_en_rx; // Cascaded 8B/10B decoder enable CRAM
input   [1:0]  resync_badcg_en;       //
input          rencdt_rising;         // encdt on rising edge enable CRAM
input          rcomp_pat_porn;        // Positive and negative match enable CRAM
input          rprbsen_rx;            // PRBS Verifier enable CRAM
input          rprbs_clr_rslt_rx;     // PRBS pass/fail flag clear CRAM
input          rbisten_rx;            // BIST Verifier enable CRAM
input          rbist_clr_rx;          // BIST pass/fail flag clear CRAM
input          rwa_6g_en;             // 6G word alignment enable CRAM
input   [1:0]  rbitslip_size;         // BITSLIP size selection CRAM
input          rbytord_2sym_en;       // Enable 2 symbols byte orderring CRAM
input          rbysync_polinv_en;     // Word alignment polarity inversion enable CRAM
input          rbitloc_rev_en;        // Bit reversal enable CRAM
input          rbyte_rev_en;          // Byte swap enable CRAM
input   [1:0]  rbyteorden;            // Byte ordering enable CRAM
input          rbytordplden;          // PLD control signal BYTEORDPLD enable CRAM
input          rphfifopldenrx;        // RX phase comp. FIFO read/write enable CRAM
input          rautoinsdis;           // Disable CRAM for auto insertion of 8'h9C
input   [5:0]  rppmsel;               // Programmable PPM ajustment CRAM
input          rforce0_freqdet;       // Forcing FREQDET signal to low CRAM
input          rforce1_freqdet;       // Forcing FREQDET signal to high CRAM
input   [9:0]  rbytordpat;            // Byte ordering pattern CRAM
input   [9:0]  rbytordpad;            // Byte ordering pad pattern CRAM
input          rforce_sig_det_pcs;    // Forcing sigdet to high in PCS CRAM
input          rfreerun_rx;           // RX_CLK out free running during RX PCS reset enable CRAM
input   [1:0]  rrcvd_clk_sel;         // RCVD_CLK domain selection CRAM
input   [1:0]  rclk_1_sel;            // CLK_1 domain selection CRAM
input   [1:0]  rclk_2_sel;            // CLK_2 domain selection CRAM
input          rrx_rd_clk_sel;        // RX FIFO read clock selection CRAM
input          rall_one_dect_only;    // PRBS Verifier detect all one only  enable CRAM
input   [2:0]  rtest_bus_sel;         // Per channel test bus selection CRAMs
input   [1:0]  r8b10b_dec_ibm_en;     // 8B10B Decoder fix enable CRAM
input          rrxfifo_lowlatency_en; // RX FIFO low latency enable CRAM
input          rppm_cnt_reset;        // PPM counter reset CRAM (latched version on Test bus)
input          sel_gp_md;             // Select Quad or Group Mode
input          rclkcmpinsertpad;      // Rate matching pad insertion enable CRAM

// Common PCS CRAMs
input          rindv_rx;              // RX SM bypassing CRAM
input   [1:0]  dskwclksel;            // Select Deskew Clock
input          rdskposdisp;           // Match the programmed de-skew pattern only
input   [9:0]  rdskchrp;              // Programmable Deskew Char. Pos. Disp.
input          rendec_data_sel_rx;    // RX 8B10B decoder data out selection CRAM
input          rphfifo_master_sel_rx; // TX Phase comp. FIFO pointers selection CRAM

// Common TX RX CRAM for BIST/PRBS
input   [2:0]  rprbs_sel;             // PRBS selection CRAM
input   [1:0]  rbist_sel;             // BIST selection CRAM
input   [1:0]  rcxpat_chnl_en;        // CRPAT or CJPAT selection CRAM

// Wiring Section
wire           clk_2_b;               // to rcv_sm in centrl_macro
wire           rcvd_clk;              // Recovered data clock
wire           rx_rd_clk;
wire    [1:0]  rx_data_9_rc;          // rx data bit 9 from rx_ctrl 
                                      // when 10-bit code-group is passing 
                                      // over XGMII
wire    [1:0]  rx_data_19_rc;         // rx data bit 19 from rx_ctrl 
                                      // when 10-bit code-group is passing 
                                      // over XGMII
wire    [3:0]  rx_control_rc_16;      // XGMII rx control from rx_ctrl
wire           sync_status_st;        // Indicate that this lane is 
                                      // now synchronized
wire    [31:0] sudi;                  // Synchronized code group + parity 
                                      // error status from sync_chnl_top
wire    [13:0] sudi_pre;              // 13-bit data one cycle earlier
wire    [31:0] cudi;                  // Clock-compensated code group 
                                      // + parity
                                      // error status from sync_chnl_top
wire    [15:0] rx_data_dt;            // 2 decoded 8-bit rx data
wire    [1:0]  rx_ctl_dt;             // 2 decoded rx controls
wire    [19:0] tenb_data;             // rx 20-bit code group bus used when 
                                      // ENDEC is 1'b0
wire           signal_detect_sync_st; // sync version of signal_detect from 
                                      // sync_chnl_top
wire    [13:0] audi;                  // Aligned code group + parity error 
                                      // status from dskw_top
wire    [13:0] audi_pre;
wire    [63:0] rxd;
wire    [1:0]  cg_comma;              // comma is detected in sync_chnl_top
wire           disable_fifo_rd;       // disable_fifo_rd from this lane
wire           disable_fifo_wr;       // disable_fifo_wr from this lane
wire           sync_status;           // Indicate that this lane is now 
                                      // synchronized
wire    [7:0]  dec_data;              // decoded 8-bit rx data
wire           dec_ctl;               // decoded rx control
wire    [1:0]  running_disp;          // indicate that dec_data/dec_ctl 
                                      // is either not valid or having 
                                      // disparity error
wire    [1:0]  invalid_code_delay;    // indicate that dec_data/dec_ctl is 
                                      // having diparity error
wire           selftest_done;         // Status shows that the self test 
                                      // checking is done
wire           selftest_err;          // Status shows that the selftest is 
                                      // successful
wire    [15:0] err_data;              // When the self test fails, this 
                                      // records the first byte that error 
                                      // occurs to.
wire    [1:0]  err_ctl;               // When the self test fails, this 
                                      // records the first byte that error 
                                      // occurs to.
wire           prbs_done;             // Indicate that prbs verification is 
                                      // done
wire           prbs_err_lt;           // Indicate that prbs verification is 
                                      // OK - latched version, cleared when 
                                      // ENBIST is cleared.
wire           prbs_err; 
wire           signal_detect_out;     // signal_detect to status pin/bit for
                                      // PMA-only operation
wire	       signal_detect;
wire   [1:0]   disp_err_delay;
wire   [1:0]   disp_val_delay;
wire   [1:0]   sync_resync_delay;
wire           dec_data_valid;
wire           high_dec_data_valid;
wire           soft_reset_int;
wire           cudi_valid;
wire	       encdet_prbs;
wire  [3:0]    ovr_undflow;           // Signals over or underflow
                                      // Merged to save bit in the synchronous 
                                      // datapath
wire           clk_1_b;
wire   [19:0]  rev_loop_data;	      // 10 bit data from RX rate matching 
                                      // FIFO, reverse loopback
wire   [39:0]  rxd_lpbk;
wire           rx_wr_clk;

wire fref_muxed, clklow_muxed;

// Wire for test bus
wire           prbs_verify_on;
wire   [9:0]   word_align_testbus;
wire   [4:0]   bist_cur_state;
wire           wr_enable2;
wire           rd_enable2;
wire   [2:0]   wptr_bin;
wire   [2:0]   rptr_bin;
wire   [4:0]   comp_fifo_cnt;
wire   [6:0]   ppm_cnt;
wire	[1:0]  comp_curr_st;

assign dec_data         = rx_data_dt[7:0];
assign dec_ctl          = rx_ctl_dt[0];
assign sync_status      = sync_status_st;
assign signal_detect	= sigdetni;

//assign soft_reset_int   = (scan_mode) ? 1'b0 : rxpcs_rst ;
assign soft_reset_int   =  rxpcs_rst ;

// RX PIPE interface clock
assign rx_pipe_clk = rx_rd_clk;

// Clock selection module
arriagx_hssi_rx_rxclk_ctl    rxclk_ctl_1 (
                          .pld_rx_clk(pld_rx_clk),	
                          .rcvd_clk_pma(rcvd_clk_pma),	
                          .rcvd_clk0_pma(rcvd_clk0_pma),   
                          .tx_pma_clk(tx_pma_clk),	
                          .rrcvd_clk_sel(rrcvd_clk_sel),
                          .rclk_1_sel(rclk_1_sel),
                          .rclk_2_sel(rclk_2_sel),
                          .rrx_rd_clk_sel(rrx_rd_clk_sel),   
                          .refclk_pma(refclk_pma),      
                          .rxrst(rxpcs_rst),           
                          .rindv_rx(rindv_rx),
                          .rphfifo_master_sel_rx(rphfifo_master_sel_rx),
                          .rx_div2_sync_in_ch0(rxfifo_shared_sig_in_ch0[3]), 
                          .rx_div2_sync_in_q0_ch0(rxfifo_shared_sig_in_q0_ch0[3]), 
                          .rdwidth_rx(rdwidth_rx),     
                          .rfreerun_rx(rfreerun_rx),
                          .scan_mode(scan_mode),
                          .rx_div2_sync_out(rxfifo_shared_sig_out[3]),
                          .rcvd_clk(rcvd_clk),
                          .clk_1_b(clk_1_b),
                          .clk_2_b(clk_2_b),
                          .rx_wr_clk(rx_wr_clk),       
                          .rx_rd_clk(rx_rd_clk),       
                          .rx_clk(rx_clk),          
                          .rcvd_clk_pma_b(rcvd_clk_pma_b)
                         );
                         
// Word alignment module
arriagx_hssi_rx_wordalign wordalign_1 (
                       .rst(soft_reset_int), 
                       .clk(rcvd_clk),
                       .scan_mode(scan_mode),
                       .wa_6g_en(rwa_6g_en), 
                       .signal_detect(signal_detect),
                       .rforce_sig_det_pcs(rforce_sig_det_pcs),
                       .lpbk_en(rlp20ben),
                       .pmadwidth({rpma_doublewidth_rx,rpmadwidth_rx}),
                       .dwidth(rdwidth_rx),
                       .pudi(pudi),
                       .pudr(txlp20b),
                       .rencdt_rising(rencdt_rising),
                       .encdt(encdt),
                       .comp_pat_porn(rcomp_pat_porn),
                       .comp_pat(rcomp_pat),
                       .comp_pat_size(rcomp_size),
                       .resync_badcg_en(resync_badcg_en),
                       .r8b10b_dec_ibm_en(r8b10b_dec_ibm_en),
                       .autobytealign_dis(rautobtalg_dis),
                       .bitslip(bitslip),
                       .rlv_en(rrlv_en),
                       .max_rlv_sel(rrundisp),
                       .disable_rx_disp(rdis_rx_disp),
                       .ib_invalid_code(rib_inv_cd),
                       .rpolinv_en(rbysync_polinv_en),
                       .rbitloc_rev_en(rbitloc_rev_en),
                       .rbyte_rev_en(rbyte_rev_en),
                       .polinv_en(polinv_rx),
                       .bitloc_rev_en(bitloc_rev_en),
                       .byte_rev_en(byte_rev_en),
                       .sync_sm_dis(rsync_sm_dis),
                       .prbs_en(rprbsen_rx),
                       .encdet_prbs(encdet_prbs),
                       .a1a2_size(a1a2_size),
                       .knumber({2'b00,rknumber}),
                       .gnumber({2'b00,rgnumber}),
                       .enumber({5'b00000,rbitslip_size[0],1'b0,renumber}),
                       .rosnumber({2'b00,rosnumber}),
                       .rosbased(rosbased),
                       .rkchar(rkchar),
                       .signal_detect_rcvdclk(signal_detect_sync_st),
                       .sudi(sudi),
                       .sync_status(sync_status_st),
                       .cg_syncpat(cg_comma),
                       .rlv(rlv),
                       .rlv_lt(rlv_lt),
                       .a1a2_k1k2_flag(a1a2_k1k2_flag),                       
                       .sudi_pre(sudi_pre),
                       .testbus(word_align_testbus)
                      );

// De-skew FIFO module
wire        dskw_fifo_rcvdclk;
wire        dskw_fifo_clk1;
wire [13:0] dskw_fifo_sudi;

assign dskw_fifo_rcvdclk = (dskwclksel[1] === 1'b1) ? rcvd_clk   : 1'b0;
assign dskw_fifo_clk1    = (dskwclksel[1] === 1'b1) ? clk_1_b    : 1'b0;
assign dskw_fifo_sudi    = (dskwclksel[1] === 1'b1) ? sudi[13:0] : 14'h0000;

arriagx_hssi_rx_dskw_fifo dskw_fifo_1 ( 
                        .rcvd_clk (dskw_fifo_rcvdclk),
                        //.rcvd_clk (rcvd_clk),
                        .sudi (dskw_fifo_sudi),
                        //.sudi (sudi[13:0]),
                        .soft_reset (soft_reset_int),
                        .fifo_rst_rd_qd (fifo_rst_rd_qd),
                        .fifo_rst_rd_gp (fifo_rst_rd_gp),
                        .clk_1 (dskw_fifo_clk1),
                        //.clk_1 (clk_1_b),
                        .en_dskw_qd (en_dskw_qd),
                        .en_dskw_gp (en_dskw_gp),
                        .sel_gp_md (sel_gp_md),
                        .rdskposdisp (rdskposdisp),
                        .rdskchrp (rdskchrp),
                        .align_det_sync (align_det_sync),
                        .rd_align (rd_align),
                        .audi (audi),
                        .audi_pre (audi_pre)
                      );

// PRBS verifier module
arriagx_hssi_rx_prbs_ver prbs_ver_1 (
                     .rcvd_clk(rcvd_clk), 
                     .soft_reset(soft_reset_int),
                     .scan_mode(scan_mode),
                     .rprbs_clr_rslt_rx(rprbs_clr_rslt_rx), 
                     .rprbs_en_rx(rprbsen_rx), 
                     .rpmadwidth_rx(rpmadwidth_rx),
                     .rpma_doublewidth_rx(rpma_doublewidth_rx),
                     .rprbs_sel(rprbs_sel),
                     .rall_one_dect_only(rall_one_dect_only),
                     .verify_on(prbs_verify_on),
                     .data_in({sudi[25:16],sudi[9:0]}), 
                     .prbs_done(prbs_done),
                     .prbs_err(prbs_err),
                     .encdet_prbs(encdet_prbs),
                     .prbs_err_lt(prbs_err_lt)
                    );
 
// Rate matching module
arriagx_hssi_rx_comp_chnl_top comp_chnl_top_1 (
                             .hard_reset (hard_reset),
                             .soft_reset (soft_reset_int),
                             .cmpfifourst (cmpfifourst),
                             .rcmpfifourst (rcmpfifourst),
                             .scan_mode(scan_mode),
                             .clk_1 (clk_1_b),
                             .clk_2 (clk_2_b),
                             .sudi ({sudi[29:16], sudi[13:0]}),
                             .sudi_pre (sudi_pre),
                             .audi (audi),
                             .audi_pre (audi_pre),
                             .align_status (align_status),
                             .align_status_sync_0 (align_status_sync_0),
                             .align_status_sync_2 (align_status_sync_2),
                             .sync_status (sync_status_st),
                             .disable_fifo_rd_0 (disable_fifo_rd_0),
                             .disable_fifo_rd_2 (disable_fifo_rd_2),
                             .disable_fifo_wr_0 (disable_fifo_wr_0),
                             .disable_fifo_wr_2 (disable_fifo_wr_2),
                             .is_lane0 (is_lane0),
                             .rdfifo_almost_full (almost_fl_rmf),
                             .rdfifo_full (full_rmf),
                             .rdfifo_almost_empty (almost_mt_rmf),
                             .rdfifo_empty (empty_rmf),
                             .dskwclksel (dskwclksel),
                             .rmatchen (rmatchen),
	                     .rwa_6g_en(rwa_6g_en), 
                             .rgenericfifo (rgenericfifo), 
                             .rdenable (rdenable_rmf),
                             .wrenable (wrenable_rmf),
                             .fifo_rd_in_comp_0 (fifo_rd_in_comp_0), 
                             .fifo_rd_in_comp_2 (fifo_rd_in_comp_2), 
                             .rskpsetbased (rskpsetbased),
                             .rtruebac2bac (rtruebac2bac),
                             .ralfull (ralfull),
                             .ralempty (ralempty),
                             .rclkcmpsqmd (rclkcmpsqmd),
                             .rclkcmpsq1p (rclkcmpsq1p),
                             .rclkcmpsq1n (rclkcmpsq1n),
                             .rclkcmppos (rclkcmppos),
                             .rclkcmpinsertpad(rclkcmpinsertpad),
                             .rrx_pipe_enable(rbitslip_size[1]),
                             .rdwidth_rx(rdwidth_rx),
                             .fifo_rd_out_comp(fifo_rd_out_comp),
                             .disable_fifo_rd (disable_fifo_rd),
                             .disable_fifo_wr (disable_fifo_wr),
                             .align_status_sync (align_status_sync),
                             .cudi (cudi),
                             .rev_loop_data (),
		             .comp_curr_st (comp_curr_st),
                             .cudi_valid (cudi_valid),
	                     .fifo_cnt(comp_fifo_cnt)
                            );

// 10B-8B Decoder module
arriagx_hssi_rx_dec_chnl_top dec_chnl_top_1 (
                             .rst(soft_reset_int), 
                             .clk_2(clk_2_b), 
                             .cascaded_8b10b_en(rcascaded_8b10b_en_rx),
                             .r8b10b_dec_ibm_en(r8b10b_dec_ibm_en),
                             .dec_crdchk_flags_sel(1'b0),
                             .data_in(cudi),
                             .data_in_valid({cudi_valid,cudi_valid}),
                             .renpolinv(renpolinv_rx),
                             .polinv(polinv_rx),
                             .dec_data(rx_data_dt), 
                             .disp_err_delay(disp_err_delay),
                             .disp_val_delay(disp_val_delay),
                             .sync_resync_delay(sync_resync_delay),
                             .dec_data_valid({high_dec_data_valid,
                                              dec_data_valid}),
                             .dec_ctl(rx_ctl_dt),
                             .invalid_code_delay(invalid_code_delay),
                             .ovr_undflow(ovr_undflow),
                             .tenb_data(tenb_data),
                             .rlb_data(rev_loop_data)
                            );

// BIST Verifier module
arriagx_hssi_rx_bist_ver selftest_ver_1 (
                         .clk_2(rx_rd_clk),
                         .soft_reset(rx_pipe_soft_reset),
                         .sync_status(sync_status_st),
                         .rbisten_rx(rbisten_rx),
                         .rpmadwidth_rx(rpmadwidth_rx),
                         .rpma_doublewidth_rx(rpma_doublewidth_rx),
                         .rdwidth_rx(rdwidth_rx),
                         .rbist_sel(rbist_sel),
                         .rcxpat_chnl_sel(rcxpat_chnl_en),
                         .rbist_clr_rx(rbist_clr_rx),
                         .rxd(rxd),
                         .rxc(rx_control_rc_16),
                         .prbs_done(prbs_done),
                         .prbs_err(prbs_err),
                         .cur_state(bist_cur_state),
                         .selftest_err(selftest_err),
                         .selftest_done(selftest_done), 
                         .bisterr(bisterr),
                         .bistdone(bistdone),
                         .err_data(err_data),
                         .err_ctl(err_ctl)
                        );

// RX Phase compensation FIFO module        
arriagx_hssi_rx_ctrl           rx_ctrl_1 (
                             .soft_reset (soft_reset_int),
                             .clk_2 (clk_2_b),
                             .rx_wr_clk(rx_wr_clk),
                             .rx_rd_clk (rx_rd_clk),
                             .scan_mode(scan_mode),
                             .rrxfifo_dis (rrxfifo_dis),
                             .rphfifo_master_sel_rx (rphfifo_master_sel_rx),
                             .indv_rx (rindv_rx),
                             .rendec_data_sel_rx (rendec_data_sel_rx),
                             .rwa_6g_en(rwa_6g_en),
                             .rrxfifo_lowlatency_en(rrxfifo_lowlatency_en),
                             .endec_rx (rendec_rx),
                             .rinvalid_code_err_only (rbitslip_size[0]),
                             .rpmadatawidth (rpmadwidth_rx), 
                             .rdwidth (rdwidth_rx),
                             .rautoinsdis(rautoinsdis),
                             .rbytorden(rbyteorden),
                             .rbytord_2sym_en(rbytord_2sym_en),
                             .rbytordpat(rbytordpat),
                             .rbytordpadval(rbytordpad),
                             .rbytordplden(rbytordplden),
                             .bytordplden(bytordpld),
                             .rsync_comp_size (rcomp_size), 
                             .rsync_comp_pat (rcomp_pat), 
                             .rsync_comp_porn(rcomp_pat_porn),
                             .rsync_sm_dis (rsync_sm_dis),
                             .rclkcmpinsertpad(rclkcmpinsertpad),
                             .invalid_code_delay (invalid_code_delay),
                             .signal_detect_sync_st (signal_detect_sync_st),
                             .dec_data_valid_pre({cudi_valid,cudi_valid}),
                             .dec_data_valid ({high_dec_data_valid,
                                               dec_data_valid}),
                             .rx_data_rs (rx_data_rs),
                             .rx_control_rs (rx_control_rs),
                             .rx_data_dt (rx_data_dt),
                             .rx_control_dt (rx_ctl_dt),
                             .tenb_data (tenb_data),
                             .sync_resync_pre({cudi[27],cudi[11]}),
                             .sync_resync_delay (sync_resync_delay),
                             .disp_err_delay (disp_err_delay),
                             .disp_val_delay(disp_val_delay),
                             .ovr_undflow (ovr_undflow),
                             .rrxfifo_urst_en (rphfifourstrx),
                             .rxfifo_urst (phfifourst_rx),
                             .rrxphfifopldctl_en(rphfifopldenrx),
                             .pld_wr_dis(wrdisable_rx),
                             .pld_re(rdenable_rx),
                             .wr_enable_ch0(rxfifo_shared_sig_in_ch0[2]),
                             .rd_enable_ch0(rxfifo_shared_sig_in_ch0[1]),
                             .rx_we_in_ch0(rxfifo_shared_sig_in_ch0[0]),     
                             .wr_enable_q0_ch0(rxfifo_shared_sig_in_q0_ch0[2]),
                             .rd_enable_q0_ch0(rxfifo_shared_sig_in_q0_ch0[1]),
                             .rx_we_in_q0_ch0(rxfifo_shared_sig_in_q0_ch0[0]),
                             .rxd (rxd),
                             .rxd_9 (rx_data_9_rc),
                             .rxd_19 (rx_data_19_rc),
                             .rxc (rx_control_rc_16),
			     .running_disp (running_disp),
                             .signal_detect_out (signal_detect_out),
			     .rxd_lpbk	(rxd_lpbk),
                             .ph_fifo_empty(empty_rx),
                             .ph_fifo_full(full_rx),
                             .wr_enable_out(rxfifo_shared_sig_out[2]),
                             .rd_enable_out(rxfifo_shared_sig_out[1]),
 			     .rx_we_out (rxfifo_shared_sig_out[0]),
                             .bytord_valid_out(byteord_flag),
                             .soft_reset_rclk1(rx_pipe_soft_reset),
                             .wr_enable2(wr_enable2),
                             .wptr_bin(wptr_bin),
                             .rd_enable2(rd_enable2),
                             .rptr_bin(rptr_bin)
                            );

// PCS channel test bus
arriagx_hssi_rx_pcs_channel_testbus pcs_channel_testbus_1 (
                             .test_bus_in0({bistdone,bisterr,bist_cur_state,
                                            prbs_verify_on,encdet_prbs,
                                            prbs_err_lt}), 
                             .test_bus_in1(word_align_testbus), 
                             .test_bus_in2(encoder_testbus), 
                             .test_bus_in3(tx_ctrl_testbus), 
                             .test_bus_in4({1'b0,rxfifo_shared_sig_out[0],
                                            wr_enable2,wptr_bin,rd_enable2,
                                            rptr_bin}), 
                             .test_bus_in5({3'b000,comp_curr_st,
                                            comp_fifo_cnt}),
                             .test_bus_in6({2'b00,freq_lock,ppm_cnt}), 
                             .test_bus_in7({2'b00,pma_testbus}), 
                             .rtest_bus_sel(rtest_bus_sel),
                             .chnl_test_bus_out(chnl_test_bus_out)
                            );

// Frequency detector module
// replaced by behavior model - OPT this block away
wire   freq_lock;
assign freq_lock = 1'b1;
assign ppm_cnt = 7'b0000000;
/*
assign fref_muxed = scan_mode ? refclk_pma : fref;
assign clklow_muxed = scan_mode ? refclk_pma : clklow;

arriagx_hssi_rx_freqdet freq_det_1 (.scan_mode(scan_mode),
                    .ppmsel (rppmsel),
                    .fref(fref_muxed),
                    .fvcobyn (clklow_muxed),
                    .pd (1'b0),
                    .hard_reset(rxpma_rst),
                    .rforcehigh(rforce1_freqdet),
                    .rforcelow(rforce0_freqdet),
                    .freq_lock(freq_lock),
                    .ppm_cnt_latch(ppm_cnt),
                    .ppm_cnt_reset(rppm_cnt_reset)
                   );	
*/	  
endmodule
               
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 46 mux21 24 oper_mux 5 
`timescale 1 ps / 1 ps
module  arriagx_hssi_dskw_sm
	( 
	align_det_sync,
	align_status,
	clk_1,
	curr_state,
	enable_deskew,
	fifo_reset_rd,
	octal_mode,
	rd_align,
	soft_reset,
	sync_status) /* synthesis synthesis_clearbox=1 */;
	input   [7:0]  align_det_sync;
	output   align_status;
	input   clk_1;
	output   [3:0]  curr_state;
	output   enable_deskew;
	output   fifo_reset_rd;
	input   octal_mode;
	input   [7:0]  rd_align;
	input   soft_reset;
	input   [7:0]  sync_status;

	reg	nl0ll35;
	reg	nl0ll36;
	reg	nl0lO33;
	reg	nl0lO34;
	reg	nl0Oi31;
	reg	nl0Oi32;
	reg	nl0Ol29;
	reg	nl0Ol30;
	reg	nl0OO27;
	reg	nl0OO28;
	reg	nli0i19;
	reg	nli0i20;
	reg	nli0l17;
	reg	nli0l18;
	reg	nli1i25;
	reg	nli1i26;
	reg	nli1l23;
	reg	nli1l24;
	reg	nli1O21;
	reg	nli1O22;
	reg	nliii15;
	reg	nliii16;
	reg	nliOi13;
	reg	nliOi14;
	reg	nll0i10;
	reg	nll0i9;
	reg	nll0O7;
	reg	nll0O8;
	reg	nll1i11;
	reg	nll1i12;
	reg	nlliO5;
	reg	nlliO6;
	reg	nllll3;
	reg	nllll4;
	reg	nlO1i1;
	reg	nlO1i2;
	reg	n0il;
	reg	nii;
	reg	nil;
	reg	nli;
	reg	nllO;
	reg	nlOi;
	reg	nlOl;
	wire	wire_niO_CLRN;
	reg	n00O;
	reg	n0ii;
	reg	nO;
	reg	nl_clk_prev;
	wire	wire_nl_CLRN;
	wire	wire_n0i_dataout;
	wire	wire_n0OO_dataout;
	wire	wire_n1i_dataout;
	wire	wire_ni0i_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_ni1i_dataout;
	wire	wire_ni1l_dataout;
	wire	wire_niii_dataout;
	wire	wire_niil_dataout;
	wire	wire_niiO_dataout;
	wire	wire_nili_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nll_dataout;
	wire  wire_n0li_o;
	wire  wire_n0ll_o;
	wire  wire_n0lO_o;
	wire  wire_n0Oi_o;
	wire  wire_n0Ol_o;
	wire  nli0O;
	wire  nliiO;
	wire  nlili;
	wire  nlill;
	wire  nlilO;
	wire  nliOO;
	wire  nll1O;
	wire  nllil;
	wire  nllli;
	wire  nllOl;

	initial
		nl0ll35 = 0;
	always @ ( posedge clk_1)
		  nl0ll35 <= nl0ll36;
	event nl0ll35_event;
	initial
		#1 ->nl0ll35_event;
	always @(nl0ll35_event)
		nl0ll35 <= {1{1'b1}};
	initial
		nl0ll36 = 0;
	always @ ( posedge clk_1)
		  nl0ll36 <= nl0ll35;
	initial
		nl0lO33 = 0;
	always @ ( posedge clk_1)
		  nl0lO33 <= nl0lO34;
	event nl0lO33_event;
	initial
		#1 ->nl0lO33_event;
	always @(nl0lO33_event)
		nl0lO33 <= {1{1'b1}};
	initial
		nl0lO34 = 0;
	always @ ( posedge clk_1)
		  nl0lO34 <= nl0lO33;
	initial
		nl0Oi31 = 0;
	always @ ( posedge clk_1)
		  nl0Oi31 <= nl0Oi32;
	event nl0Oi31_event;
	initial
		#1 ->nl0Oi31_event;
	always @(nl0Oi31_event)
		nl0Oi31 <= {1{1'b1}};
	initial
		nl0Oi32 = 0;
	always @ ( posedge clk_1)
		  nl0Oi32 <= nl0Oi31;
	initial
		nl0Ol29 = 0;
	always @ ( posedge clk_1)
		  nl0Ol29 <= nl0Ol30;
	event nl0Ol29_event;
	initial
		#1 ->nl0Ol29_event;
	always @(nl0Ol29_event)
		nl0Ol29 <= {1{1'b1}};
	initial
		nl0Ol30 = 0;
	always @ ( posedge clk_1)
		  nl0Ol30 <= nl0Ol29;
	initial
		nl0OO27 = 0;
	always @ ( posedge clk_1)
		  nl0OO27 <= nl0OO28;
	event nl0OO27_event;
	initial
		#1 ->nl0OO27_event;
	always @(nl0OO27_event)
		nl0OO27 <= {1{1'b1}};
	initial
		nl0OO28 = 0;
	always @ ( posedge clk_1)
		  nl0OO28 <= nl0OO27;
	initial
		nli0i19 = 0;
	always @ ( posedge clk_1)
		  nli0i19 <= nli0i20;
	event nli0i19_event;
	initial
		#1 ->nli0i19_event;
	always @(nli0i19_event)
		nli0i19 <= {1{1'b1}};
	initial
		nli0i20 = 0;
	always @ ( posedge clk_1)
		  nli0i20 <= nli0i19;
	initial
		nli0l17 = 0;
	always @ ( posedge clk_1)
		  nli0l17 <= nli0l18;
	event nli0l17_event;
	initial
		#1 ->nli0l17_event;
	always @(nli0l17_event)
		nli0l17 <= {1{1'b1}};
	initial
		nli0l18 = 0;
	always @ ( posedge clk_1)
		  nli0l18 <= nli0l17;
	initial
		nli1i25 = 0;
	always @ ( posedge clk_1)
		  nli1i25 <= nli1i26;
	event nli1i25_event;
	initial
		#1 ->nli1i25_event;
	always @(nli1i25_event)
		nli1i25 <= {1{1'b1}};
	initial
		nli1i26 = 0;
	always @ ( posedge clk_1)
		  nli1i26 <= nli1i25;
	initial
		nli1l23 = 0;
	always @ ( posedge clk_1)
		  nli1l23 <= nli1l24;
	event nli1l23_event;
	initial
		#1 ->nli1l23_event;
	always @(nli1l23_event)
		nli1l23 <= {1{1'b1}};
	initial
		nli1l24 = 0;
	always @ ( posedge clk_1)
		  nli1l24 <= nli1l23;
	initial
		nli1O21 = 0;
	always @ ( posedge clk_1)
		  nli1O21 <= nli1O22;
	event nli1O21_event;
	initial
		#1 ->nli1O21_event;
	always @(nli1O21_event)
		nli1O21 <= {1{1'b1}};
	initial
		nli1O22 = 0;
	always @ ( posedge clk_1)
		  nli1O22 <= nli1O21;
	initial
		nliii15 = 0;
	always @ ( posedge clk_1)
		  nliii15 <= nliii16;
	event nliii15_event;
	initial
		#1 ->nliii15_event;
	always @(nliii15_event)
		nliii15 <= {1{1'b1}};
	initial
		nliii16 = 0;
	always @ ( posedge clk_1)
		  nliii16 <= nliii15;
	initial
		nliOi13 = 0;
	always @ ( posedge clk_1)
		  nliOi13 <= nliOi14;
	event nliOi13_event;
	initial
		#1 ->nliOi13_event;
	always @(nliOi13_event)
		nliOi13 <= {1{1'b1}};
	initial
		nliOi14 = 0;
	always @ ( posedge clk_1)
		  nliOi14 <= nliOi13;
	initial
		nll0i10 = 0;
	always @ ( posedge clk_1)
		  nll0i10 <= nll0i9;
	initial
		nll0i9 = 0;
	always @ ( posedge clk_1)
		  nll0i9 <= nll0i10;
	event nll0i9_event;
	initial
		#1 ->nll0i9_event;
	always @(nll0i9_event)
		nll0i9 <= {1{1'b1}};
	initial
		nll0O7 = 0;
	always @ ( posedge clk_1)
		  nll0O7 <= nll0O8;
	event nll0O7_event;
	initial
		#1 ->nll0O7_event;
	always @(nll0O7_event)
		nll0O7 <= {1{1'b1}};
	initial
		nll0O8 = 0;
	always @ ( posedge clk_1)
		  nll0O8 <= nll0O7;
	initial
		nll1i11 = 0;
	always @ ( posedge clk_1)
		  nll1i11 <= nll1i12;
	event nll1i11_event;
	initial
		#1 ->nll1i11_event;
	always @(nll1i11_event)
		nll1i11 <= {1{1'b1}};
	initial
		nll1i12 = 0;
	always @ ( posedge clk_1)
		  nll1i12 <= nll1i11;
	initial
		nlliO5 = 0;
	always @ ( posedge clk_1)
		  nlliO5 <= nlliO6;
	event nlliO5_event;
	initial
		#1 ->nlliO5_event;
	always @(nlliO5_event)
		nlliO5 <= {1{1'b1}};
	initial
		nlliO6 = 0;
	always @ ( posedge clk_1)
		  nlliO6 <= nlliO5;
	initial
		nllll3 = 0;
	always @ ( posedge clk_1)
		  nllll3 <= nllll4;
	event nllll3_event;
	initial
		#1 ->nllll3_event;
	always @(nllll3_event)
		nllll3 <= {1{1'b1}};
	initial
		nllll4 = 0;
	always @ ( posedge clk_1)
		  nllll4 <= nllll3;
	initial
		nlO1i1 = 0;
	always @ ( posedge clk_1)
		  nlO1i1 <= nlO1i2;
	event nlO1i1_event;
	initial
		#1 ->nlO1i1_event;
	always @(nlO1i1_event)
		nlO1i1 <= {1{1'b1}};
	initial
		nlO1i2 = 0;
	always @ ( posedge clk_1)
		  nlO1i2 <= nlO1i1;
	initial
	begin
		n0il = 0;
		nii = 0;
		nil = 0;
		nli = 0;
		nllO = 0;
		nlOi = 0;
		nlOl = 0;
	end
	always @ ( posedge clk_1 or  negedge wire_niO_CLRN)
	begin
		if (wire_niO_CLRN == 1'b0) 
		begin
			n0il <= 0;
			nii <= 0;
			nil <= 0;
			nli <= 0;
			nllO <= 0;
			nlOi <= 0;
			nlOl <= 0;
		end
		else 
		begin
			n0il <= wire_n0lO_o;
			nii <= wire_n0ll_o;
			nil <= nli;
			nli <= wire_nll_dataout;
			nllO <= wire_n0Oi_o;
			nlOi <= wire_n0Ol_o;
			nlOl <= nii;
		end
	end
	assign
		wire_niO_CLRN = ((nlliO6 ^ nlliO5) & (~ soft_reset));
	initial
	begin
		n00O = 0;
		n0ii = 0;
		nO = 0;
	end
	always @ (clk_1 or soft_reset or wire_nl_CLRN)
	begin
		if (soft_reset == 1'b1) 
		begin
			n00O <= 1;
			n0ii <= 1;
			nO <= 1;
		end
		else if  (wire_nl_CLRN == 1'b0) 
		begin
			n00O <= 0;
			n0ii <= 0;
			nO <= 0;
		end
		else 
		if (clk_1 != nl_clk_prev && clk_1 == 1'b1) 
		begin
			n00O <= n0ii;
			n0ii <= wire_n0li_o;
			nO <= n00O;
		end
		nl_clk_prev <= clk_1;
	end
	assign
		wire_nl_CLRN = (nlO1i2 ^ nlO1i1);
	assign		wire_n0i_dataout = (octal_mode === 1'b1) ? nllil : ((((rd_align[0] & rd_align[1]) & rd_align[2]) & rd_align[3]) & (nll0O8 ^ nll0O7));
	or(wire_n0OO_dataout, n0ii, nli0O);
	assign		wire_n1i_dataout = (octal_mode === 1'b1) ? (~ nll1O) : (~ ((((rd_align[0] | rd_align[1]) | rd_align[2]) | rd_align[3]) | (~ (nll1i12 ^ nll1i11))));
	or(wire_ni0i_dataout, n0ii, (~ nil));
	and(wire_ni0l_dataout, nii, ~((~ nil)));
	and(wire_ni0O_dataout, wire_niil_dataout, ~((~ nil)));
	and(wire_ni1i_dataout, nii, ~(nli0O));
	and(wire_ni1l_dataout, (~ wire_n0i_dataout), ~(nli0O));
	and(wire_niii_dataout, wire_niiO_dataout, ~((~ nil)));
	or(wire_niil_dataout, wire_n0i_dataout, nliOO);
	or(wire_niiO_dataout, (~ wire_n0i_dataout), nliOO);
	and(wire_nili_dataout, wire_nilO_dataout, ~((~ nil)));
	and(wire_nill_dataout, nliOO, ~((~ nil)));
	and(wire_nilO_dataout, (~ wire_n0i_dataout), ~(nliOO));
	assign		wire_niOi_dataout = (nliiO === 1'b1) ? nii : wire_nl1l_dataout;
	or(wire_niOl_dataout, n0ii, nliiO);
	and(wire_niOO_dataout, (~ wire_n0i_dataout), ~(nliiO));
	and(wire_nl0i_dataout, (~ nlili), ~(nliiO));
	and(wire_nl0l_dataout, nlili, ~(nliiO));
	and(wire_nl1i_dataout, wire_n0i_dataout, ~(nliiO));
	or(wire_nl1l_dataout, nii, wire_n0i_dataout);
	and(wire_nlii_dataout, n0ii, ~(nlill));
	assign		wire_nliO_dataout = (octal_mode === 1'b1) ? nlilO : (((align_det_sync[0] & align_det_sync[1]) & align_det_sync[2]) & align_det_sync[3]);
	assign		wire_nll_dataout = (octal_mode === 1'b1) ? nllli : (((sync_status[0] & sync_status[1]) & sync_status[2]) & sync_status[3]);
	oper_mux   n0li
	( 
	.data({((nl0ll36 ^ nl0ll35) & wire_n0OO_dataout), {3{wire_ni0i_dataout}}, {3{wire_niOl_dataout}}, wire_nlii_dataout, {8{1'b0}}}),
	.o(wire_n0li_o),
	.sel({1'b1, nlOi, nllO, n0il}));
	defparam
		n0li.width_data = 16,
		n0li.width_sel = 4;
	oper_mux   n0ll
	( 
	.data({wire_ni1i_dataout, {2{wire_ni0l_dataout}}, ((nl0lO34 ^ nl0lO33) & wire_ni0l_dataout), wire_niOi_dataout, nii, ((nl0Oi32 ^ nl0Oi31) & nii), nii, {8{1'b0}}}),
	.o(wire_n0ll_o),
	.sel({1'b1, nlOi, nllO, n0il}));
	defparam
		n0ll.width_data = 16,
		n0ll.width_sel = 4;
	oper_mux   n0lO
	( 
	.data({wire_ni1l_dataout, wire_ni0O_dataout, ((nl0Ol30 ^ nl0Ol29) & wire_nili_dataout), ((nl0OO28 ^ nl0OO27) & wire_nill_dataout), wire_niOO_dataout, wire_nl1i_dataout, wire_nl0i_dataout, nlill, {8{1'b0}}}),
	.o(wire_n0lO_o),
	.sel({1'b1, nlOi, nllO, n0il}));
	defparam
		n0lO.width_data = 16,
		n0lO.width_sel = 4;
	oper_mux   n0Oi
	( 
	.data({((nli1i26 ^ nli1i25) & (~ nli0O)), wire_niii_dataout, wire_nill_dataout, 1'b0, wire_niOO_dataout, (~ nliiO), wire_nl0l_dataout, {9{1'b0}}}),
	.o(wire_n0Oi_o),
	.sel({1'b1, nlOi, ((nli1l24 ^ nli1l23) & nllO), ((nli1O22 ^ nli1O21) & n0il)}));
	defparam
		n0Oi.width_data = 16,
		n0Oi.width_sel = 4;
	oper_mux   n0Ol
	( 
	.data({(~ nli0O), {2{nil}}, ((nli0i20 ^ nli0i19) & nil), wire_nl1i_dataout, {11{1'b0}}}),
	.o(wire_n0Ol_o),
	.sel({1'b1, nlOi, nllO, ((nli0l18 ^ nli0l17) & n0il)}));
	defparam
		n0Ol.width_data = 16,
		n0Ol.width_sel = 4;
	assign
		align_status = nlOl,
		curr_state = {1'b0, nlOi, nllO, n0il},
		enable_deskew = n0ii,
		fifo_reset_rd = (n0ii & (~ n00O)),
		nli0O = ((~ nil) | nliOO),
		nliiO = (((~ nil) | nliOO) | (~ (nliii16 ^ nliii15))),
		nlili = ((~ nO) & wire_n0i_dataout),
		nlill = (nil & wire_nliO_dataout),
		nlilO = ((((((((align_det_sync[0] & align_det_sync[1]) & align_det_sync[2]) & align_det_sync[3]) & align_det_sync[4]) & align_det_sync[5]) & align_det_sync[6]) & align_det_sync[7]) & (nliOi14 ^ nliOi13)),
		nliOO = ((~ wire_n0i_dataout) & (~ wire_n1i_dataout)),
		nll1O = ((((((((rd_align[0] | rd_align[1]) | rd_align[2]) | rd_align[3]) | rd_align[4]) | rd_align[5]) | rd_align[6]) | rd_align[7]) | (~ (nll0i10 ^ nll0i9))),
		nllil = (((((((rd_align[0] & rd_align[1]) & rd_align[2]) & rd_align[3]) & rd_align[4]) & rd_align[5]) & rd_align[6]) & rd_align[7]),
		nllli = ((((((((sync_status[0] & sync_status[1]) & sync_status[2]) & sync_status[3]) & sync_status[4]) & sync_status[5]) & sync_status[6]) & sync_status[7]) & (nllll4 ^ nllll3)),
		nllOl = 1'b1;
endmodule //arriagx_hssi_dskw_sm
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 143 mux21 336 oper_add 1 oper_decoder 1 oper_less_than 1 oper_mux 39 
`timescale 1 ps / 1 ps
module  arriagx_hssi_tx_sm
	( 
	curr_state,
	indv,
	rd_enable_sync,
	sm_ctl,
	sm_data,
	soft_reset,
	tx_clk,
	tx_ctl,
	tx_data,
	tx_local_fault,
	tx_local_fault_clr,
	tx_local_fault_det) /* synthesis synthesis_clearbox=1 */;
	output   [3:0]  curr_state;
	input   indv;
	input   rd_enable_sync;
	output   [3:0]  sm_ctl;
	output   [31:0]  sm_data;
	input   soft_reset;
	input   tx_clk;
	input   [3:0]  tx_ctl;
	input   [31:0]  tx_data;
	output   tx_local_fault;
	input   tx_local_fault_clr;
	output   tx_local_fault_det;

	reg	niOi0O49;
	reg	niOi0O50;
	reg	niOiii47;
	reg	niOiii48;
	reg	niOl0l45;
	reg	niOl0l46;
	reg	niOl0O43;
	reg	niOl0O44;
	reg	niOlil41;
	reg	niOlil42;
	reg	niOlOl39;
	reg	niOlOl40;
	reg	niOO0i37;
	reg	niOO0i38;
	reg	niOOiO35;
	reg	niOOiO36;
	reg	niOOOi33;
	reg	niOOOi34;
	reg	nl100O21;
	reg	nl100O22;
	reg	nl101O23;
	reg	nl101O24;
	reg	nl10lO19;
	reg	nl10lO20;
	reg	nl10OO17;
	reg	nl10OO18;
	reg	nl110l29;
	reg	nl110l30;
	reg	nl111l31;
	reg	nl111l32;
	reg	nl11il27;
	reg	nl11il28;
	reg	nl11lO25;
	reg	nl11lO26;
	reg	nl1i0O15;
	reg	nl1i0O16;
	reg	nl1ilO13;
	reg	nl1ilO14;
	reg	nl1l0l10;
	reg	nl1l0l9;
	reg	nl1l1i11;
	reg	nl1l1i12;
	reg	nl1lil7;
	reg	nl1lil8;
	reg	nl1lOi5;
	reg	nl1lOi6;
	reg	nl1O0O1;
	reg	nl1O0O2;
	reg	nl1O1l3;
	reg	nl1O1l4;
	reg	n000i;
	reg	n000l;
	reg	n001l;
	reg	n001O;
	reg	n00ii;
	reg	n00il;
	reg	n0lO;
	reg	n0Ol;
	reg	n110l;
	reg	n110O;
	reg	n111i;
	reg	n111l;
	reg	n111O;
	reg	nii0i;
	reg	nii0l;
	reg	nii0O;
	reg	niiii;
	reg	niiiO;
	reg	nliO1i;
	reg	nliO1l;
	reg	nll0O;
	reg	nll10l;
	reg	nll10O;
	reg	nll1ii;
	reg	nll1il;
	reg	nll1iO;
	reg	nll1li;
	reg	nlll1l;
	reg	nlllii;
	reg	nlllil;
	reg	nllliO;
	reg	nlllli;
	reg	nllllO;
	reg	nlllOi;
	reg	nlOOOO;
	reg	n0Oi_clk_prev;
	wire	wire_n0Oi_CLRN;
	wire	wire_n0Oi_PRN;
	reg	n000O;
	reg	n001i;
	reg	n01OO;
	reg	n0ll;
	reg	n0OO;
	reg	n110i;
	reg	ni1l;
	reg	nii1l;
	reg	nii1O;
	reg	niiil;
	reg	niili;
	reg	nliiO;
	reg	nlili;
	reg	nlilOi;
	reg	nlilOl;
	reg	nlilOO;
	reg	nliOOi;
	reg	nll0i;
	reg	nll0l;
	reg	nlliO;
	reg	nlll0l;
	reg	nlll0O;
	reg	nlll1i;
	reg	nlllll;
	reg	nlOOOi;
	reg	nlOOOl;
	wire	wire_ni1i_CLRN;
	reg	nll00i;
	reg	nll01i;
	reg	nll1Ol;
	reg	nll1OO;
	reg	nlliil;
	wire	wire_nlliii_PRN;
	reg	nll00l;
	reg	nll00O;
	reg	nll01l;
	reg	nll01O;
	reg	nll0ii;
	reg	nll0il;
	reg	nll0iO;
	reg	nll0li;
	reg	nll0ll;
	reg	nll0lO;
	reg	nll0Oi;
	reg	nll0Ol;
	reg	nll0OO;
	reg	nll1ll;
	reg	nll1Oi;
	reg	nlli0i;
	reg	nlli0l;
	reg	nlli0O;
	reg	nlli1i;
	reg	nlli1l;
	reg	nlli1O;
	reg	nlliiO;
	reg	nllili;
	reg	nllill;
	reg	nllilO;
	reg	nlliOi;
	reg	nlliOO;
	wire	wire_nlliOl_CLRN;
	wire	wire_n00i_dataout;
	wire	wire_n00iO_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00li_dataout;
	wire	wire_n00ll_dataout;
	wire	wire_n00lO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n00Oi_dataout;
	wire	wire_n00Ol_dataout;
	wire	wire_n00OO_dataout;
	wire	wire_n010i_dataout;
	wire	wire_n010l_dataout;
	wire	wire_n010O_dataout;
	wire	wire_n011i_dataout;
	wire	wire_n011l_dataout;
	wire	wire_n011O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01ii_dataout;
	wire	wire_n01il_dataout;
	wire	wire_n01iO_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01li_dataout;
	wire	wire_n01ll_dataout;
	wire	wire_n01lO_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n01Oi_dataout;
	wire	wire_n01Ol_dataout;
	wire	wire_n0i1i_dataout;
	wire	wire_n0i1l_dataout;
	wire	wire_n0ii_dataout;
	wire	wire_n0il_dataout;
	wire	wire_n0ilO_dataout;
	wire	wire_n0iO_dataout;
	wire	wire_n0iOi_dataout;
	wire	wire_n0iOl_dataout;
	wire	wire_n0iOO_dataout;
	wire	wire_n0l0i_dataout;
	wire	wire_n0l0l_dataout;
	wire	wire_n0l0O_dataout;
	wire	wire_n0l1i_dataout;
	wire	wire_n0l1l_dataout;
	wire	wire_n0l1O_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0lii_dataout;
	wire	wire_n0lil_dataout;
	wire	wire_n0liO_dataout;
	wire	wire_n0lli_dataout;
	wire	wire_n0lll_dataout;
	wire	wire_n0llO_dataout;
	wire	wire_n0lOi_dataout;
	wire	wire_n0lOl_dataout;
	wire	wire_n0lOO_dataout;
	wire	wire_n0O0i_dataout;
	wire	wire_n0O0l_dataout;
	wire	wire_n0O0O_dataout;
	wire	wire_n0O1i_dataout;
	wire	wire_n0O1l_dataout;
	wire	wire_n0O1O_dataout;
	wire	wire_n0Oii_dataout;
	wire	wire_n0Oil_dataout;
	wire	wire_n0OiO_dataout;
	wire	wire_n0Oli_dataout;
	wire	wire_n0Oll_dataout;
	wire	wire_n0OlO_dataout;
	wire	wire_n0OOi_dataout;
	wire	wire_n0OOl_dataout;
	wire	wire_n0OOO_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10li_dataout;
	wire	wire_n10ll_dataout;
	wire	wire_n10lO_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n10Oi_dataout;
	wire	wire_n10Ol_dataout;
	wire	wire_n10OO_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11ii_dataout;
	wire	wire_n11il_dataout;
	wire	wire_n11iO_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11li_dataout;
	wire	wire_n11ll_dataout;
	wire	wire_n11lO_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n11Oi_dataout;
	wire	wire_n11Ol_dataout;
	wire	wire_n11OO_dataout;
	wire	wire_n1i0i_dataout;
	wire	wire_n1i0l_dataout;
	wire	wire_n1i0O_dataout;
	wire	wire_n1i1i_dataout;
	wire	wire_n1i1l_dataout;
	wire	wire_n1i1O_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1iii_dataout;
	wire	wire_n1iil_dataout;
	wire	wire_n1iiO_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1ili_dataout;
	wire	wire_n1ill_dataout;
	wire	wire_n1ilO_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1iOi_dataout;
	wire	wire_n1iOl_dataout;
	wire	wire_n1iOO_dataout;
	wire	wire_n1l0i_dataout;
	wire	wire_n1l0l_dataout;
	wire	wire_n1l0O_dataout;
	wire	wire_n1l1i_dataout;
	wire	wire_n1l1l_dataout;
	wire	wire_n1l1O_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1lii_dataout;
	wire	wire_n1lil_dataout;
	wire	wire_n1liO_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lli_dataout;
	wire	wire_n1lll_dataout;
	wire	wire_n1llO_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1lOi_dataout;
	wire	wire_n1lOl_dataout;
	wire	wire_n1lOO_dataout;
	wire	wire_n1O0i_dataout;
	wire	wire_n1O0l_dataout;
	wire	wire_n1O0O_dataout;
	wire	wire_n1O1i_dataout;
	wire	wire_n1O1l_dataout;
	wire	wire_n1O1O_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Oii_dataout;
	wire	wire_n1Oil_dataout;
	wire	wire_n1OiO_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1Oli_dataout;
	wire	wire_n1Oll_dataout;
	wire	wire_n1OlO_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_n1OOi_dataout;
	wire	wire_n1OOl_dataout;
	wire	wire_n1OOO_dataout;
	wire	wire_ni00i_dataout;
	wire	wire_ni00l_dataout;
	wire	wire_ni00O_dataout;
	wire	wire_ni01i_dataout;
	wire	wire_ni01l_dataout;
	wire	wire_ni01O_dataout;
	wire	wire_ni0ii_dataout;
	wire	wire_ni0il_dataout;
	wire	wire_ni0iO_dataout;
	wire	wire_ni0li_dataout;
	wire	wire_ni0ll_dataout;
	wire	wire_ni0lO_dataout;
	wire	wire_ni0Oi_dataout;
	wire	wire_ni0Ol_dataout;
	wire	wire_ni0OO_dataout;
	wire	wire_ni10i_dataout;
	wire	wire_ni10l_dataout;
	wire	wire_ni10O_dataout;
	wire	wire_ni11i_dataout;
	wire	wire_ni11l_dataout;
	wire	wire_ni11O_dataout;
	wire	wire_ni1ii_dataout;
	wire	wire_ni1il_dataout;
	wire	wire_ni1iO_dataout;
	wire	wire_ni1li_dataout;
	wire	wire_ni1ll_dataout;
	wire	wire_ni1lO_dataout;
	wire	wire_ni1Oi_dataout;
	wire	wire_ni1Ol_dataout;
	wire	wire_ni1OO_dataout;
	wire	wire_nii1i_dataout;
	wire	wire_niill_dataout;
	wire	wire_niilO_dataout;
	wire	wire_niiOi_dataout;
	wire	wire_niiOl_dataout;
	wire	wire_niiOO_dataout;
	wire	wire_nil0i_dataout;
	wire	wire_nil1i_dataout;
	wire	wire_nil1l_dataout;
	wire	wire_nil1O_dataout;
	wire	wire_nilOl_dataout;
	wire	wire_nilOO_dataout;
	wire	wire_niO0i_dataout;
	wire	wire_niO0l_dataout;
	wire	wire_niO0O_dataout;
	wire	wire_niO1i_dataout;
	wire	wire_niO1l_dataout;
	wire	wire_niO1O_dataout;
	wire	wire_niOii_dataout;
	wire	wire_niOil_dataout;
	wire	wire_niOiO_dataout;
	wire	wire_niOli_dataout;
	wire	wire_niOll_dataout;
	wire	wire_niOlO_dataout;
	wire	wire_niOOi_dataout;
	wire	wire_niOOl_dataout;
	wire	wire_niOOO_dataout;
	wire	wire_nl00i_dataout;
	wire	wire_nl00l_dataout;
	wire	wire_nl00O_dataout;
	wire	wire_nl01i_dataout;
	wire	wire_nl01l_dataout;
	wire	wire_nl01O_dataout;
	wire	wire_nl0ii_dataout;
	wire	wire_nl0il_dataout;
	wire	wire_nl0iO_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0ll_dataout;
	wire	wire_nl0lO_dataout;
	wire	wire_nl0Oi_dataout;
	wire	wire_nl0Ol_dataout;
	wire	wire_nl0OO_dataout;
	wire	wire_nl10i_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl10O_dataout;
	wire	wire_nl11i_dataout;
	wire	wire_nl11l_dataout;
	wire	wire_nl11O_dataout;
	wire	wire_nl1ii_dataout;
	wire	wire_nl1il_dataout;
	wire	wire_nl1iO_dataout;
	wire	wire_nl1li_dataout;
	wire	wire_nl1ll_dataout;
	wire	wire_nl1lO_dataout;
	wire	wire_nl1Oi_dataout;
	wire	wire_nl1Ol_dataout;
	wire	wire_nl1OO_dataout;
	wire	wire_nli0i_dataout;
	wire	wire_nli0l_dataout;
	wire	wire_nli0O_dataout;
	wire	wire_nli1i_dataout;
	wire	wire_nli1l_dataout;
	wire	wire_nli1O_dataout;
	wire	wire_nliii_dataout;
	wire	wire_nliil_dataout;
	wire	wire_nlill_dataout;
	wire	wire_nlilO_dataout;
	wire	wire_nliO0i_dataout;
	wire	wire_nliO0l_dataout;
	wire	wire_nliO0O_dataout;
	wire	wire_nliO1O_dataout;
	wire	wire_nliOi_dataout;
	wire	wire_nliOii_dataout;
	wire	wire_nliOil_dataout;
	wire	wire_nliOiO_dataout;
	wire	wire_nliOli_dataout;
	wire	wire_nliOll_dataout;
	wire	wire_nliOlO_dataout;
	wire	wire_nllii_dataout;
	wire	wire_nllil_dataout;
	wire	wire_nlll0i_dataout;
	wire	wire_nlll1O_dataout;
	wire	wire_nllli_dataout;
	wire	wire_nllll_dataout;
	wire	wire_nlllOl_dataout;
	wire	wire_nlllOO_dataout;
	wire	wire_nllO0i_dataout;
	wire	wire_nllO0l_dataout;
	wire	wire_nllO0O_dataout;
	wire	wire_nllO1i_dataout;
	wire	wire_nllO1l_dataout;
	wire	wire_nllO1O_dataout;
	wire	wire_nllOii_dataout;
	wire	wire_nlO00i_dataout;
	wire	wire_nlO00l_dataout;
	wire	wire_nlO00O_dataout;
	wire	wire_nlO01i_dataout;
	wire	wire_nlO01l_dataout;
	wire	wire_nlO01O_dataout;
	wire	wire_nlO0ii_dataout;
	wire	wire_nlO0il_dataout;
	wire	wire_nlO0iO_dataout;
	wire	wire_nlO0li_dataout;
	wire	wire_nlO0ll_dataout;
	wire	wire_nlO0lO_dataout;
	wire	wire_nlO0Oi_dataout;
	wire	wire_nlO10i_dataout;
	wire	wire_nlO10l_dataout;
	wire	wire_nlO10O_dataout;
	wire	wire_nlO11l_dataout;
	wire	wire_nlO11O_dataout;
	wire	wire_nlO1ii_dataout;
	wire	wire_nlO1il_dataout;
	wire	wire_nlO1iO_dataout;
	wire	wire_nlO1li_dataout;
	wire	wire_nlO1ll_dataout;
	wire	wire_nlO1lO_dataout;
	wire	wire_nlO1Oi_dataout;
	wire	wire_nlO1Ol_dataout;
	wire	wire_nlO1OO_dataout;
	wire	wire_nlOi0i_dataout;
	wire	wire_nlOi0l_dataout;
	wire	wire_nlOi0O_dataout;
	wire	wire_nlOi1l_dataout;
	wire	wire_nlOi1O_dataout;
	wire	wire_nlOiii_dataout;
	wire	wire_nlOiil_dataout;
	wire	wire_nlOiiO_dataout;
	wire	wire_nlOili_dataout;
	wire	wire_nlOill_dataout;
	wire	wire_nlOilO_dataout;
	wire	wire_nlOiOi_dataout;
	wire	wire_nlOiOl_dataout;
	wire	wire_nlOiOO_dataout;
	wire	wire_nlOl0i_dataout;
	wire	wire_nlOl0l_dataout;
	wire	wire_nlOl0O_dataout;
	wire	wire_nlOl1i_dataout;
	wire	wire_nlOl1l_dataout;
	wire	wire_nlOl1O_dataout;
	wire	wire_nlOlii_dataout;
	wire	wire_nlOlil_dataout;
	wire	wire_nlOliO_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlli_dataout;
	wire	wire_nlOlll_dataout;
	wire	wire_nlOllO_dataout;
	wire	wire_nlOlOi_dataout;
	wire	wire_nlOlOl_dataout;
	wire	wire_nlOlOO_dataout;
	wire	wire_nlOO0i_dataout;
	wire	wire_nlOO0l_dataout;
	wire	wire_nlOO0O_dataout;
	wire	wire_nlOO1i_dataout;
	wire	wire_nlOO1l_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOii_dataout;
	wire	wire_nlOOil_dataout;
	wire	wire_nlOOiO_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOli_dataout;
	wire	wire_nlOOll_dataout;
	wire	wire_nlOOlO_dataout;
	wire	wire_nlOOO_dataout;
	wire  [5:0]   wire_nliOOl_o;
	wire  [15:0]   wire_nlOlO_o;
	wire  wire_nlO0O_o;
	wire  wire_n0i0i_o;
	wire  wire_n0i0l_o;
	wire  wire_n0i0O_o;
	wire  wire_n0i1O_o;
	wire  wire_n0iii_o;
	wire  wire_n0iil_o;
	wire  wire_n0iiO_o;
	wire  wire_n0ili_o;
	wire  wire_n0ill_o;
	wire  wire_n100i_o;
	wire  wire_n100l_o;
	wire  wire_n100O_o;
	wire  wire_n101i_o;
	wire  wire_n101l_o;
	wire  wire_n101O_o;
	wire  wire_n10ii_o;
	wire  wire_n10il_o;
	wire  wire_n10iO_o;
	wire  wire_nil0l_o;
	wire  wire_nil0O_o;
	wire  wire_nilii_o;
	wire  wire_nilil_o;
	wire  wire_niliO_o;
	wire  wire_nilli_o;
	wire  wire_nilll_o;
	wire  wire_nillO_o;
	wire  wire_nilOi_o;
	wire  wire_nllOil_o;
	wire  wire_nllOiO_o;
	wire  wire_nllOli_o;
	wire  wire_nllOll_o;
	wire  wire_nllOlO_o;
	wire  wire_nllOOi_o;
	wire  wire_nllOOl_o;
	wire  wire_nllOOO_o;
	wire  wire_nlO11i_o;
	wire  wire_nlOil_o;
	wire  wire_nlOiO_o;
	wire  wire_nlOli_o;
	wire  niOi0l;
	wire  niOiil;
	wire  niOiiO;
	wire  niOili;
	wire  niOill;
	wire  niOilO;
	wire  niOiOi;
	wire  niOiOl;
	wire  niOiOO;
	wire  niOl0i;
	wire  niOl1i;
	wire  niOl1l;
	wire  niOl1O;
	wire  niOlii;
	wire  niOliO;
	wire  niOlli;
	wire  niOlll;
	wire  niOllO;
	wire  niOlOi;
	wire  niOO0O;
	wire  niOO1i;
	wire  niOO1l;
	wire  niOO1O;
	wire  niOOii;
	wire  niOOil;
	wire  niOOll;
	wire  niOOlO;
	wire  niOOOO;
	wire  nl100l;
	wire  nl101i;
	wire  nl101l;
	wire  nl10il;
	wire  nl10iO;
	wire  nl10li;
	wire  nl10ll;
	wire  nl10Ol;
	wire  nl110i;
	wire  nl111i;
	wire  nl11ii;
	wire  nl11li;
	wire  nl11ll;
	wire  nl11Ol;
	wire  nl11OO;
	wire  nl1i0i;
	wire  nl1i0l;
	wire  nl1i1l;
	wire  nl1i1O;
	wire  nl1iil;
	wire  nl1iiO;
	wire  nl1ili;
	wire  nl1ill;
	wire  nl1iOl;
	wire  nl1iOO;
	wire  nl1l0i;
	wire  nl1l1O;
	wire  nl1lii;
	wire  nl1lli;
	wire  nl1lll;
	wire  nl1llO;
	wire  nl1lOO;
	wire  nl1O0i;
	wire  nl1O0l;
	wire  nl1O1i;
	wire  nl1Oli;

	initial
		niOi0O49 = 0;
	always @ ( posedge tx_clk)
		  niOi0O49 <= niOi0O50;
	event niOi0O49_event;
	initial
		#1 ->niOi0O49_event;
	always @(niOi0O49_event)
		niOi0O49 <= {1{1'b1}};
	initial
		niOi0O50 = 0;
	always @ ( posedge tx_clk)
		  niOi0O50 <= niOi0O49;
	initial
		niOiii47 = 0;
	always @ ( posedge tx_clk)
		  niOiii47 <= niOiii48;
	event niOiii47_event;
	initial
		#1 ->niOiii47_event;
	always @(niOiii47_event)
		niOiii47 <= {1{1'b1}};
	initial
		niOiii48 = 0;
	always @ ( posedge tx_clk)
		  niOiii48 <= niOiii47;
	initial
		niOl0l45 = 0;
	always @ ( posedge tx_clk)
		  niOl0l45 <= niOl0l46;
	event niOl0l45_event;
	initial
		#1 ->niOl0l45_event;
	always @(niOl0l45_event)
		niOl0l45 <= {1{1'b1}};
	initial
		niOl0l46 = 0;
	always @ ( posedge tx_clk)
		  niOl0l46 <= niOl0l45;
	initial
		niOl0O43 = 0;
	always @ ( posedge tx_clk)
		  niOl0O43 <= niOl0O44;
	event niOl0O43_event;
	initial
		#1 ->niOl0O43_event;
	always @(niOl0O43_event)
		niOl0O43 <= {1{1'b1}};
	initial
		niOl0O44 = 0;
	always @ ( posedge tx_clk)
		  niOl0O44 <= niOl0O43;
	initial
		niOlil41 = 0;
	always @ ( posedge tx_clk)
		  niOlil41 <= niOlil42;
	event niOlil41_event;
	initial
		#1 ->niOlil41_event;
	always @(niOlil41_event)
		niOlil41 <= {1{1'b1}};
	initial
		niOlil42 = 0;
	always @ ( posedge tx_clk)
		  niOlil42 <= niOlil41;
	initial
		niOlOl39 = 0;
	always @ ( posedge tx_clk)
		  niOlOl39 <= niOlOl40;
	event niOlOl39_event;
	initial
		#1 ->niOlOl39_event;
	always @(niOlOl39_event)
		niOlOl39 <= {1{1'b1}};
	initial
		niOlOl40 = 0;
	always @ ( posedge tx_clk)
		  niOlOl40 <= niOlOl39;
	initial
		niOO0i37 = 0;
	always @ ( posedge tx_clk)
		  niOO0i37 <= niOO0i38;
	event niOO0i37_event;
	initial
		#1 ->niOO0i37_event;
	always @(niOO0i37_event)
		niOO0i37 <= {1{1'b1}};
	initial
		niOO0i38 = 0;
	always @ ( posedge tx_clk)
		  niOO0i38 <= niOO0i37;
	initial
		niOOiO35 = 0;
	always @ ( posedge tx_clk)
		  niOOiO35 <= niOOiO36;
	event niOOiO35_event;
	initial
		#1 ->niOOiO35_event;
	always @(niOOiO35_event)
		niOOiO35 <= {1{1'b1}};
	initial
		niOOiO36 = 0;
	always @ ( posedge tx_clk)
		  niOOiO36 <= niOOiO35;
	initial
		niOOOi33 = 0;
	always @ ( posedge tx_clk)
		  niOOOi33 <= niOOOi34;
	event niOOOi33_event;
	initial
		#1 ->niOOOi33_event;
	always @(niOOOi33_event)
		niOOOi33 <= {1{1'b1}};
	initial
		niOOOi34 = 0;
	always @ ( posedge tx_clk)
		  niOOOi34 <= niOOOi33;
	initial
		nl100O21 = 0;
	always @ ( posedge tx_clk)
		  nl100O21 <= nl100O22;
	event nl100O21_event;
	initial
		#1 ->nl100O21_event;
	always @(nl100O21_event)
		nl100O21 <= {1{1'b1}};
	initial
		nl100O22 = 0;
	always @ ( posedge tx_clk)
		  nl100O22 <= nl100O21;
	initial
		nl101O23 = 0;
	always @ ( posedge tx_clk)
		  nl101O23 <= nl101O24;
	event nl101O23_event;
	initial
		#1 ->nl101O23_event;
	always @(nl101O23_event)
		nl101O23 <= {1{1'b1}};
	initial
		nl101O24 = 0;
	always @ ( posedge tx_clk)
		  nl101O24 <= nl101O23;
	initial
		nl10lO19 = 0;
	always @ ( posedge tx_clk)
		  nl10lO19 <= nl10lO20;
	event nl10lO19_event;
	initial
		#1 ->nl10lO19_event;
	always @(nl10lO19_event)
		nl10lO19 <= {1{1'b1}};
	initial
		nl10lO20 = 0;
	always @ ( posedge tx_clk)
		  nl10lO20 <= nl10lO19;
	initial
		nl10OO17 = 0;
	always @ ( posedge tx_clk)
		  nl10OO17 <= nl10OO18;
	event nl10OO17_event;
	initial
		#1 ->nl10OO17_event;
	always @(nl10OO17_event)
		nl10OO17 <= {1{1'b1}};
	initial
		nl10OO18 = 0;
	always @ ( posedge tx_clk)
		  nl10OO18 <= nl10OO17;
	initial
		nl110l29 = 0;
	always @ ( posedge tx_clk)
		  nl110l29 <= nl110l30;
	event nl110l29_event;
	initial
		#1 ->nl110l29_event;
	always @(nl110l29_event)
		nl110l29 <= {1{1'b1}};
	initial
		nl110l30 = 0;
	always @ ( posedge tx_clk)
		  nl110l30 <= nl110l29;
	initial
		nl111l31 = 0;
	always @ ( posedge tx_clk)
		  nl111l31 <= nl111l32;
	event nl111l31_event;
	initial
		#1 ->nl111l31_event;
	always @(nl111l31_event)
		nl111l31 <= {1{1'b1}};
	initial
		nl111l32 = 0;
	always @ ( posedge tx_clk)
		  nl111l32 <= nl111l31;
	initial
		nl11il27 = 0;
	always @ ( posedge tx_clk)
		  nl11il27 <= nl11il28;
	event nl11il27_event;
	initial
		#1 ->nl11il27_event;
	always @(nl11il27_event)
		nl11il27 <= {1{1'b1}};
	initial
		nl11il28 = 0;
	always @ ( posedge tx_clk)
		  nl11il28 <= nl11il27;
	initial
		nl11lO25 = 0;
	always @ ( posedge tx_clk)
		  nl11lO25 <= nl11lO26;
	event nl11lO25_event;
	initial
		#1 ->nl11lO25_event;
	always @(nl11lO25_event)
		nl11lO25 <= {1{1'b1}};
	initial
		nl11lO26 = 0;
	always @ ( posedge tx_clk)
		  nl11lO26 <= nl11lO25;
	initial
		nl1i0O15 = 0;
	always @ ( posedge tx_clk)
		  nl1i0O15 <= nl1i0O16;
	event nl1i0O15_event;
	initial
		#1 ->nl1i0O15_event;
	always @(nl1i0O15_event)
		nl1i0O15 <= {1{1'b1}};
	initial
		nl1i0O16 = 0;
	always @ ( posedge tx_clk)
		  nl1i0O16 <= nl1i0O15;
	initial
		nl1ilO13 = 0;
	always @ ( posedge tx_clk)
		  nl1ilO13 <= nl1ilO14;
	event nl1ilO13_event;
	initial
		#1 ->nl1ilO13_event;
	always @(nl1ilO13_event)
		nl1ilO13 <= {1{1'b1}};
	initial
		nl1ilO14 = 0;
	always @ ( posedge tx_clk)
		  nl1ilO14 <= nl1ilO13;
	initial
		nl1l0l10 = 0;
	always @ ( posedge tx_clk)
		  nl1l0l10 <= nl1l0l9;
	initial
		nl1l0l9 = 0;
	always @ ( posedge tx_clk)
		  nl1l0l9 <= nl1l0l10;
	event nl1l0l9_event;
	initial
		#1 ->nl1l0l9_event;
	always @(nl1l0l9_event)
		nl1l0l9 <= {1{1'b1}};
	initial
		nl1l1i11 = 0;
	always @ ( posedge tx_clk)
		  nl1l1i11 <= nl1l1i12;
	event nl1l1i11_event;
	initial
		#1 ->nl1l1i11_event;
	always @(nl1l1i11_event)
		nl1l1i11 <= {1{1'b1}};
	initial
		nl1l1i12 = 0;
	always @ ( posedge tx_clk)
		  nl1l1i12 <= nl1l1i11;
	initial
		nl1lil7 = 0;
	always @ ( posedge tx_clk)
		  nl1lil7 <= nl1lil8;
	event nl1lil7_event;
	initial
		#1 ->nl1lil7_event;
	always @(nl1lil7_event)
		nl1lil7 <= {1{1'b1}};
	initial
		nl1lil8 = 0;
	always @ ( posedge tx_clk)
		  nl1lil8 <= nl1lil7;
	initial
		nl1lOi5 = 0;
	always @ ( posedge tx_clk)
		  nl1lOi5 <= nl1lOi6;
	event nl1lOi5_event;
	initial
		#1 ->nl1lOi5_event;
	always @(nl1lOi5_event)
		nl1lOi5 <= {1{1'b1}};
	initial
		nl1lOi6 = 0;
	always @ ( posedge tx_clk)
		  nl1lOi6 <= nl1lOi5;
	initial
		nl1O0O1 = 0;
	always @ ( posedge tx_clk)
		  nl1O0O1 <= nl1O0O2;
	event nl1O0O1_event;
	initial
		#1 ->nl1O0O1_event;
	always @(nl1O0O1_event)
		nl1O0O1 <= {1{1'b1}};
	initial
		nl1O0O2 = 0;
	always @ ( posedge tx_clk)
		  nl1O0O2 <= nl1O0O1;
	initial
		nl1O1l3 = 0;
	always @ ( posedge tx_clk)
		  nl1O1l3 <= nl1O1l4;
	event nl1O1l3_event;
	initial
		#1 ->nl1O1l3_event;
	always @(nl1O1l3_event)
		nl1O1l3 <= {1{1'b1}};
	initial
		nl1O1l4 = 0;
	always @ ( posedge tx_clk)
		  nl1O1l4 <= nl1O1l3;
	initial
	begin
		n000i = 0;
		n000l = 0;
		n001l = 0;
		n001O = 0;
		n00ii = 0;
		n00il = 0;
		n0lO = 0;
		n0Ol = 0;
		n110l = 0;
		n110O = 0;
		n111i = 0;
		n111l = 0;
		n111O = 0;
		nii0i = 0;
		nii0l = 0;
		nii0O = 0;
		niiii = 0;
		niiiO = 0;
		nliO1i = 0;
		nliO1l = 0;
		nll0O = 0;
		nll10l = 0;
		nll10O = 0;
		nll1ii = 0;
		nll1il = 0;
		nll1iO = 0;
		nll1li = 0;
		nlll1l = 0;
		nlllii = 0;
		nlllil = 0;
		nllliO = 0;
		nlllli = 0;
		nllllO = 0;
		nlllOi = 0;
		nlOOOO = 0;
	end
	always @ (tx_clk or wire_n0Oi_PRN or wire_n0Oi_CLRN)
	begin
		if (wire_n0Oi_PRN == 1'b0) 
		begin
			n000i <= 1;
			n000l <= 1;
			n001l <= 1;
			n001O <= 1;
			n00ii <= 1;
			n00il <= 1;
			n0lO <= 1;
			n0Ol <= 1;
			n110l <= 1;
			n110O <= 1;
			n111i <= 1;
			n111l <= 1;
			n111O <= 1;
			nii0i <= 1;
			nii0l <= 1;
			nii0O <= 1;
			niiii <= 1;
			niiiO <= 1;
			nliO1i <= 1;
			nliO1l <= 1;
			nll0O <= 1;
			nll10l <= 1;
			nll10O <= 1;
			nll1ii <= 1;
			nll1il <= 1;
			nll1iO <= 1;
			nll1li <= 1;
			nlll1l <= 1;
			nlllii <= 1;
			nlllil <= 1;
			nllliO <= 1;
			nlllli <= 1;
			nllllO <= 1;
			nlllOi <= 1;
			nlOOOO <= 1;
		end
		else if  (wire_n0Oi_CLRN == 1'b0) 
		begin
			n000i <= 0;
			n000l <= 0;
			n001l <= 0;
			n001O <= 0;
			n00ii <= 0;
			n00il <= 0;
			n0lO <= 0;
			n0Ol <= 0;
			n110l <= 0;
			n110O <= 0;
			n111i <= 0;
			n111l <= 0;
			n111O <= 0;
			nii0i <= 0;
			nii0l <= 0;
			nii0O <= 0;
			niiii <= 0;
			niiiO <= 0;
			nliO1i <= 0;
			nliO1l <= 0;
			nll0O <= 0;
			nll10l <= 0;
			nll10O <= 0;
			nll1ii <= 0;
			nll1il <= 0;
			nll1iO <= 0;
			nll1li <= 0;
			nlll1l <= 0;
			nlllii <= 0;
			nlllil <= 0;
			nllliO <= 0;
			nlllli <= 0;
			nllllO <= 0;
			nlllOi <= 0;
			nlOOOO <= 0;
		end
		else 
		if (tx_clk != n0Oi_clk_prev && tx_clk == 1'b1) 
		begin
			n000i <= wire_n00Ol_dataout;
			n000l <= wire_n00OO_dataout;
			n001l <= wire_n00lO_dataout;
			n001O <= wire_n00Oi_dataout;
			n00ii <= wire_n0i1l_dataout;
			n00il <= wire_niill_dataout;
			n0lO <= wire_nlOil_o;
			n0Ol <= wire_nlOiO_o;
			n110l <= wire_n11OO_dataout;
			n110O <= wire_n00iO_dataout;
			n111i <= wire_n11ll_dataout;
			n111l <= wire_n11lO_dataout;
			n111O <= wire_n11Oi_dataout;
			nii0i <= wire_niiOl_dataout;
			nii0l <= wire_niiOO_dataout;
			nii0O <= wire_nil1i_dataout;
			niiii <= wire_nil1l_dataout;
			niiiO <= wire_nil0i_dataout;
			nliO1i <= wire_nliOii_dataout;
			nliO1l <= (nll1li ^ nll1iO);
			nll0O <= wire_nllli_dataout;
			nll10l <= nliO1l;
			nll10O <= nll10l;
			nll1ii <= nll10O;
			nll1il <= nll1ii;
			nll1iO <= nll1il;
			nll1li <= nll1iO;
			nlll1l <= wire_nlllOl_dataout;
			nlllii <= wire_nllO1l_dataout;
			nlllil <= wire_nllO1O_dataout;
			nllliO <= wire_nllO0i_dataout;
			nlllli <= wire_nllO0l_dataout;
			nllllO <= wire_nllOii_dataout;
			nlllOi <= wire_n11ii_dataout;
			nlOOOO <= wire_n11li_dataout;
		end
		n0Oi_clk_prev <= tx_clk;
	end
	assign
		wire_n0Oi_CLRN = (niOl0O44 ^ niOl0O43),
		wire_n0Oi_PRN = ((niOl0l46 ^ niOl0l45) & (~ soft_reset));
	initial
	begin
		n000O = 0;
		n001i = 0;
		n01OO = 0;
		n0ll = 0;
		n0OO = 0;
		n110i = 0;
		ni1l = 0;
		nii1l = 0;
		nii1O = 0;
		niiil = 0;
		niili = 0;
		nliiO = 0;
		nlili = 0;
		nlilOi = 0;
		nlilOl = 0;
		nlilOO = 0;
		nliOOi = 0;
		nll0i = 0;
		nll0l = 0;
		nlliO = 0;
		nlll0l = 0;
		nlll0O = 0;
		nlll1i = 0;
		nlllll = 0;
		nlOOOi = 0;
		nlOOOl = 0;
	end
	always @ ( posedge tx_clk or  negedge wire_ni1i_CLRN)
	begin
		if (wire_ni1i_CLRN == 1'b0) 
		begin
			n000O <= 0;
			n001i <= 0;
			n01OO <= 0;
			n0ll <= 0;
			n0OO <= 0;
			n110i <= 0;
			ni1l <= 0;
			nii1l <= 0;
			nii1O <= 0;
			niiil <= 0;
			niili <= 0;
			nliiO <= 0;
			nlili <= 0;
			nlilOi <= 0;
			nlilOl <= 0;
			nlilOO <= 0;
			nliOOi <= 0;
			nll0i <= 0;
			nll0l <= 0;
			nlliO <= 0;
			nlll0l <= 0;
			nlll0O <= 0;
			nlll1i <= 0;
			nlllll <= 0;
			nlOOOi <= 0;
			nlOOOl <= 0;
		end
		else 
		begin
			n000O <= wire_n0i1i_dataout;
			n001i <= wire_n00ll_dataout;
			n01OO <= wire_n00li_dataout;
			n0ll <= indv;
			n0OO <= wire_nlOli_o;
			n110i <= wire_n11Ol_dataout;
			ni1l <= wire_nlOll_dataout;
			nii1l <= wire_niilO_dataout;
			nii1O <= wire_niiOi_dataout;
			niiil <= wire_nil1O_dataout;
			niili <= wire_nlill_dataout;
			nliiO <= wire_nlilO_dataout;
			nlili <= nll0i;
			nlilOi <= wire_nliO0i_dataout;
			nlilOl <= wire_nliO0l_dataout;
			nlilOO <= wire_nliO0O_dataout;
			nliOOi <= wire_nliO1O_dataout;
			nll0i <= tx_local_fault_clr;
			nll0l <= wire_nllii_dataout;
			nlliO <= n0ll;
			nlll0l <= wire_nlllOO_dataout;
			nlll0O <= wire_nllO1i_dataout;
			nlll1i <= wire_nlll1O_dataout;
			nlllll <= wire_nllO0O_dataout;
			nlOOOi <= wire_n11il_dataout;
			nlOOOl <= wire_n11iO_dataout;
		end
	end
	assign
		wire_ni1i_CLRN = ((niOlil42 ^ niOlil41) & (~ soft_reset));
	initial
	begin
		nll00i = 0;
		nll01i = 0;
		nll1Ol = 0;
		nll1OO = 0;
		nlliil = 0;
	end
	always @ ( posedge tx_clk or  negedge wire_nlliii_PRN)
	begin
		if (wire_nlliii_PRN == 1'b0) 
		begin
			nll00i <= 1;
			nll01i <= 1;
			nll1Ol <= 1;
			nll1OO <= 1;
			nlliil <= 1;
		end
		else if  (niOliO == 1'b1) 
		begin
			nll00i <= tx_data[7];
			nll01i <= tx_data[4];
			nll1Ol <= tx_data[2];
			nll1OO <= tx_data[3];
			nlliil <= tx_data[25];
		end
	end
	assign
		wire_nlliii_PRN = ((niOi0O50 ^ niOi0O49) & (~ soft_reset));
	initial
	begin
		nll00l = 0;
		nll00O = 0;
		nll01l = 0;
		nll01O = 0;
		nll0ii = 0;
		nll0il = 0;
		nll0iO = 0;
		nll0li = 0;
		nll0ll = 0;
		nll0lO = 0;
		nll0Oi = 0;
		nll0Ol = 0;
		nll0OO = 0;
		nll1ll = 0;
		nll1Oi = 0;
		nlli0i = 0;
		nlli0l = 0;
		nlli0O = 0;
		nlli1i = 0;
		nlli1l = 0;
		nlli1O = 0;
		nlliiO = 0;
		nllili = 0;
		nllill = 0;
		nllilO = 0;
		nlliOi = 0;
		nlliOO = 0;
	end
	always @ ( posedge tx_clk or  negedge wire_nlliOl_CLRN)
	begin
		if (wire_nlliOl_CLRN == 1'b0) 
		begin
			nll00l <= 0;
			nll00O <= 0;
			nll01l <= 0;
			nll01O <= 0;
			nll0ii <= 0;
			nll0il <= 0;
			nll0iO <= 0;
			nll0li <= 0;
			nll0ll <= 0;
			nll0lO <= 0;
			nll0Oi <= 0;
			nll0Ol <= 0;
			nll0OO <= 0;
			nll1ll <= 0;
			nll1Oi <= 0;
			nlli0i <= 0;
			nlli0l <= 0;
			nlli0O <= 0;
			nlli1i <= 0;
			nlli1l <= 0;
			nlli1O <= 0;
			nlliiO <= 0;
			nllili <= 0;
			nllill <= 0;
			nllilO <= 0;
			nlliOi <= 0;
			nlliOO <= 0;
		end
		else if  (niOliO == 1'b1) 
		begin
			nll00l <= tx_data[8];
			nll00O <= tx_data[9];
			nll01l <= tx_data[5];
			nll01O <= tx_data[6];
			nll0ii <= tx_data[10];
			nll0il <= tx_data[11];
			nll0iO <= tx_data[12];
			nll0li <= tx_data[13];
			nll0ll <= tx_data[14];
			nll0lO <= tx_data[15];
			nll0Oi <= tx_data[16];
			nll0Ol <= tx_data[17];
			nll0OO <= tx_data[18];
			nll1ll <= tx_data[0];
			nll1Oi <= tx_data[1];
			nlli0i <= tx_data[22];
			nlli0l <= tx_data[23];
			nlli0O <= tx_data[24];
			nlli1i <= tx_data[19];
			nlli1l <= tx_data[20];
			nlli1O <= tx_data[21];
			nlliiO <= tx_data[26];
			nllili <= tx_data[27];
			nllill <= tx_data[28];
			nllilO <= tx_data[29];
			nlliOi <= tx_data[30];
			nlliOO <= tx_data[31];
		end
	end
	assign
		wire_nlliOl_CLRN = ((niOiii48 ^ niOiii47) & (~ soft_reset));
	or(wire_n00i_dataout, (~ nlll1i), niOl0i);
	or(wire_n00iO_dataout, wire_n0i1O_o, nl1i1O);
	or(wire_n00l_dataout, wire_n0ii_dataout, nlliO);
	and(wire_n00li_dataout, wire_n0i0i_o, ~(nl1i1O));
	or(wire_n00ll_dataout, wire_n0i0l_o, nl1i1O);
	or(wire_n00lO_dataout, wire_n0i0O_o, nl1i1O);
	or(wire_n00O_dataout, (~ niOl0i), nlliO);
	or(wire_n00Oi_dataout, wire_n0iii_o, nl1i1O);
	or(wire_n00Ol_dataout, wire_n0iil_o, nl1i1O);
	or(wire_n00OO_dataout, wire_n0iiO_o, nl1i1O);
	assign		wire_n010i_dataout = (niOl0i === 1'b1) ? wire_n1ill_dataout : niOl1O;
	assign		wire_n010l_dataout = (niOl0i === 1'b1) ? wire_n1ilO_dataout : (~ niOl1O);
	or(wire_n010O_dataout, wire_n10li_dataout, ~(rd_enable_sync));
	and(wire_n011i_dataout, nlli1O, nlll1i);
	and(wire_n011l_dataout, nlli0l, nlll1i);
	or(wire_n011O_dataout, wire_n1ili_dataout, ~(niOl0i));
	and(wire_n01i_dataout, wire_nlOlii_dataout, ~(niOl0i));
	and(wire_n01ii_dataout, wire_n10ll_dataout, rd_enable_sync);
	and(wire_n01il_dataout, wire_n10lO_dataout, rd_enable_sync);
	or(wire_n01iO_dataout, wire_n10Oi_dataout, ~(rd_enable_sync));
	or(wire_n01l_dataout, nliO1l, (~ niOl1l));
	or(wire_n01li_dataout, wire_n10Ol_dataout, ~(rd_enable_sync));
	or(wire_n01ll_dataout, wire_n10OO_dataout, ~(rd_enable_sync));
	or(wire_n01lO_dataout, wire_n1OlO_dataout, ~(rd_enable_sync));
	or(wire_n01O_dataout, wire_n00i_dataout, nlliO);
	and(wire_n01Oi_dataout, wire_n1i1l_dataout, rd_enable_sync);
	or(wire_n01Ol_dataout, wire_n1OOi_dataout, ~(rd_enable_sync));
	or(wire_n0i1i_dataout, wire_n0ili_o, nl1i1O);
	or(wire_n0i1l_dataout, wire_n0ill_o, nl1i1O);
	or(wire_n0ii_dataout, (~ niOl1O), niOl0i);
	or(wire_n0il_dataout, (~ rd_enable_sync), nlliO);
	or(wire_n0ilO_dataout, wire_n0l0O_dataout, ~(niOl0i));
	and(wire_n0iO_dataout, wire_n0li_dataout, ~(nlliO));
	and(wire_n0iOi_dataout, wire_n0lii_dataout, niOl0i);
	and(wire_n0iOl_dataout, wire_n0lil_dataout, niOl0i);
	or(wire_n0iOO_dataout, wire_n0liO_dataout, ~(niOl0i));
	and(wire_n0l0i_dataout, wire_n0lOi_dataout, niOl0i);
	assign		wire_n0l0l_dataout = (niOl0i === 1'b1) ? wire_n0lOl_dataout : (~ nliO1l);
	or(wire_n0l0O_dataout, wire_n0lOO_dataout, niOO1l);
	or(wire_n0l1i_dataout, wire_n0lli_dataout, ~(niOl0i));
	or(wire_n0l1l_dataout, wire_n0lll_dataout, ~(niOl0i));
	assign		wire_n0l1O_dataout = (niOl0i === 1'b1) ? wire_n0llO_dataout : (~ nliO1l);
	and(wire_n0li_dataout, (~ niOl0i), rd_enable_sync);
	and(wire_n0lii_dataout, wire_n0O1i_dataout, ~(niOO1l));
	and(wire_n0lil_dataout, wire_n0O1l_dataout, ~(niOO1l));
	or(wire_n0liO_dataout, wire_n0O1O_dataout, niOO1l);
	or(wire_n0lli_dataout, wire_n0O0i_dataout, niOO1l);
	or(wire_n0lll_dataout, wire_n0O0l_dataout, niOO1l);
	or(wire_n0llO_dataout, wire_n0O0O_dataout, niOO1l);
	and(wire_n0lOi_dataout, wire_n0Oii_dataout, ~(niOO1l));
	or(wire_n0lOl_dataout, wire_n0Oil_dataout, niOO1l);
	or(wire_n0lOO_dataout, tx_ctl[1], niOlOi);
	or(wire_n0O0i_dataout, tx_data[11], niOlOi);
	or(wire_n0O0l_dataout, tx_data[12], niOlOi);
	or(wire_n0O0O_dataout, tx_data[13], niOlOi);
	or(wire_n0O1i_dataout, tx_data[8], niOlOi);
	and(wire_n0O1l_dataout, tx_data[9], ~(niOlOi));
	or(wire_n0O1O_dataout, tx_data[10], niOlOi);
	or(wire_n0Oii_dataout, tx_data[14], niOlOi);
	or(wire_n0Oil_dataout, tx_data[15], niOlOi);
	assign		wire_n0OiO_dataout = (niOl0i === 1'b1) ? wire_n0l0O_dataout : (~ nlll1i);
	assign		wire_n0Oli_dataout = (niOl0i === 1'b1) ? wire_n0lii_dataout : wire_ni11O_dataout;
	assign		wire_n0Oll_dataout = (niOl0i === 1'b1) ? wire_n0lil_dataout : wire_ni10i_dataout;
	assign		wire_n0OlO_dataout = (niOl0i === 1'b1) ? wire_n0liO_dataout : wire_ni10l_dataout;
	assign		wire_n0OOi_dataout = (niOl0i === 1'b1) ? wire_n0lli_dataout : wire_ni10O_dataout;
	assign		wire_n0OOl_dataout = (niOl0i === 1'b1) ? wire_n0lll_dataout : wire_ni1ii_dataout;
	assign		wire_n0OOO_dataout = (niOl0i === 1'b1) ? wire_n0llO_dataout : wire_ni1il_dataout;
	or(wire_n10i_dataout, wire_n1il_dataout, nlliO);
	and(wire_n10l_dataout, wire_n1iO_dataout, ~(nlliO));
	or(wire_n10li_dataout, wire_n1i0i_dataout, ~(niOl0i));
	and(wire_n10ll_dataout, wire_n1i0l_dataout, niOl0i);
	and(wire_n10lO_dataout, wire_n1i0O_dataout, niOl0i);
	and(wire_n10O_dataout, wire_n1li_dataout, ~(nlliO));
	or(wire_n10Oi_dataout, wire_n1iii_dataout, ~(niOl0i));
	or(wire_n10Ol_dataout, wire_n1iil_dataout, ~(niOl0i));
	or(wire_n10OO_dataout, wire_n1iiO_dataout, ~(niOl0i));
	or(wire_n11i_dataout, nliO1l, niOl0i);
	or(wire_n11ii_dataout, wire_n101i_o, nl11OO);
	and(wire_n11il_dataout, wire_n101l_o, ~(nl11OO));
	or(wire_n11iO_dataout, wire_n101O_o, nl11OO);
	and(wire_n11l_dataout, (~ nliO1l), ~(niOl0i));
	or(wire_n11li_dataout, wire_n100i_o, nl11OO);
	or(wire_n11ll_dataout, wire_n100l_o, nl11OO);
	or(wire_n11lO_dataout, wire_n100O_o, nl11OO);
	or(wire_n11O_dataout, wire_n1ii_dataout, nlliO);
	or(wire_n11Oi_dataout, wire_n10ii_o, nl11OO);
	or(wire_n11Ol_dataout, wire_n10il_o, nl11OO);
	or(wire_n11OO_dataout, wire_n10iO_o, nl11OO);
	or(wire_n1i0i_dataout, wire_n1iOi_dataout, niOiiO);
	and(wire_n1i0l_dataout, wire_n1iOl_dataout, ~(niOiiO));
	and(wire_n1i0O_dataout, wire_n1iOO_dataout, ~(niOiiO));
	assign		wire_n1i1i_dataout = (niOl0i === 1'b1) ? wire_n1ili_dataout : (~ nliO1l);
	and(wire_n1i1l_dataout, wire_n1ill_dataout, niOl0i);
	assign		wire_n1i1O_dataout = (niOl0i === 1'b1) ? wire_n1ilO_dataout : (~ nliO1l);
	or(wire_n1ii_dataout, wire_n1ll_dataout, niOl0i);
	or(wire_n1iii_dataout, wire_n1l1i_dataout, niOiiO);
	or(wire_n1iil_dataout, wire_n1l1l_dataout, niOiiO);
	or(wire_n1iiO_dataout, wire_n1l1O_dataout, niOiiO);
	and(wire_n1il_dataout, wire_n1lO_dataout, ~(niOl0i));
	or(wire_n1ili_dataout, wire_n1l0i_dataout, niOiiO);
	and(wire_n1ill_dataout, wire_n1l0l_dataout, ~(niOiiO));
	or(wire_n1ilO_dataout, wire_n1l0O_dataout, niOiiO);
	and(wire_n1iO_dataout, (~ nlll1i), ~(niOl0i));
	or(wire_n1iOi_dataout, tx_ctl[2], niOlll);
	or(wire_n1iOl_dataout, tx_data[16], niOlll);
	and(wire_n1iOO_dataout, tx_data[17], ~(niOlll));
	or(wire_n1l0i_dataout, tx_data[21], niOlll);
	or(wire_n1l0l_dataout, tx_data[22], niOlll);
	or(wire_n1l0O_dataout, tx_data[23], niOlll);
	or(wire_n1l1i_dataout, tx_data[18], niOlll);
	or(wire_n1l1l_dataout, tx_data[19], niOlll);
	or(wire_n1l1O_dataout, tx_data[20], niOlll);
	and(wire_n1li_dataout, nlll1i, ~(niOl0i));
	assign		wire_n1lii_dataout = (niOl0i === 1'b1) ? wire_n1i0i_dataout : (~ nlll1i);
	assign		wire_n1lil_dataout = (niOl0i === 1'b1) ? wire_n1i0l_dataout : wire_n1O1i_dataout;
	assign		wire_n1liO_dataout = (niOl0i === 1'b1) ? wire_n1i0O_dataout : wire_n1O1l_dataout;
	and(wire_n1ll_dataout, nliO1l, ~(nlll1i));
	assign		wire_n1lli_dataout = (niOl0i === 1'b1) ? wire_n1iii_dataout : wire_n1O1O_dataout;
	assign		wire_n1lll_dataout = (niOl0i === 1'b1) ? wire_n1iil_dataout : wire_n1O0i_dataout;
	assign		wire_n1llO_dataout = (niOl0i === 1'b1) ? wire_n1iiO_dataout : wire_n1O0l_dataout;
	and(wire_n1lO_dataout, (~ nliO1l), ~(nlll1i));
	assign		wire_n1lOi_dataout = (niOl0i === 1'b1) ? wire_n1ili_dataout : wire_n1O0O_dataout;
	assign		wire_n1lOl_dataout = (niOl0i === 1'b1) ? wire_n1ill_dataout : wire_n1Oii_dataout;
	assign		wire_n1lOO_dataout = (niOl0i === 1'b1) ? wire_n1ilO_dataout : wire_n1Oil_dataout;
	or(wire_n1O0i_dataout, nlli1i, ~(nlll1i));
	or(wire_n1O0l_dataout, nlli1l, ~(nlll1i));
	assign		wire_n1O0O_dataout = (nlll1i === 1'b1) ? nlli1O : (~ nliO1l);
	and(wire_n1O1i_dataout, nll0Oi, nlll1i);
	and(wire_n1O1l_dataout, nll0Ol, nlll1i);
	or(wire_n1O1O_dataout, nll0OO, ~(nlll1i));
	or(wire_n1Oi_dataout, wire_n1OO_dataout, nlliO);
	and(wire_n1Oii_dataout, nlli0i, nlll1i);
	assign		wire_n1Oil_dataout = (nlll1i === 1'b1) ? nlli0l : (~ nliO1l);
	assign		wire_n1OiO_dataout = (niOl0i === 1'b1) ? wire_n1ili_dataout : wire_nlOlii_dataout;
	or(wire_n1Ol_dataout, wire_n01i_dataout, nlliO);
	assign		wire_n1Oli_dataout = (niOl0i === 1'b1) ? wire_n1ill_dataout : (~ niOl1l);
	assign		wire_n1Oll_dataout = (niOl0i === 1'b1) ? wire_n1ilO_dataout : wire_nlOlil_dataout;
	and(wire_n1OlO_dataout, wire_n1ili_dataout, niOl0i);
	or(wire_n1OO_dataout, wire_n01l_dataout, niOl0i);
	and(wire_n1OOi_dataout, wire_n1ilO_dataout, niOl0i);
	assign		wire_n1OOl_dataout = (niOl0i === 1'b1) ? wire_n1ili_dataout : wire_n011i_dataout;
	assign		wire_n1OOO_dataout = (niOl0i === 1'b1) ? wire_n1ilO_dataout : wire_n011l_dataout;
	and(wire_ni00i_dataout, nll0lO, nlll1i);
	or(wire_ni00l_dataout, wire_n0llO_dataout, ~(niOl0i));
	assign		wire_ni00O_dataout = (niOl0i === 1'b1) ? wire_n0lOi_dataout : niOl1O;
	assign		wire_ni01i_dataout = (niOl0i === 1'b1) ? wire_n0llO_dataout : wire_ni01O_dataout;
	assign		wire_ni01l_dataout = (niOl0i === 1'b1) ? wire_n0lOl_dataout : wire_ni00i_dataout;
	and(wire_ni01O_dataout, nll0li, nlll1i);
	assign		wire_ni0ii_dataout = (niOl0i === 1'b1) ? wire_n0lOl_dataout : (~ niOl1O);
	or(wire_ni0il_dataout, wire_n0ilO_dataout, ~(rd_enable_sync));
	and(wire_ni0iO_dataout, wire_n0iOi_dataout, rd_enable_sync);
	and(wire_ni0li_dataout, wire_n0iOl_dataout, rd_enable_sync);
	or(wire_ni0ll_dataout, wire_n0iOO_dataout, ~(rd_enable_sync));
	or(wire_ni0lO_dataout, wire_n0l1i_dataout, ~(rd_enable_sync));
	or(wire_ni0Oi_dataout, wire_n0l1l_dataout, ~(rd_enable_sync));
	or(wire_ni0Ol_dataout, wire_ni1Ol_dataout, ~(rd_enable_sync));
	and(wire_ni0OO_dataout, wire_n0l0i_dataout, rd_enable_sync);
	and(wire_ni10i_dataout, nll00O, nlll1i);
	or(wire_ni10l_dataout, nll0ii, ~(nlll1i));
	or(wire_ni10O_dataout, nll0il, ~(nlll1i));
	assign		wire_ni11i_dataout = (niOl0i === 1'b1) ? wire_n0lOi_dataout : wire_ni1iO_dataout;
	assign		wire_ni11l_dataout = (niOl0i === 1'b1) ? wire_n0lOl_dataout : wire_ni1li_dataout;
	and(wire_ni11O_dataout, nll00l, nlll1i);
	or(wire_ni1ii_dataout, nll0iO, ~(nlll1i));
	assign		wire_ni1il_dataout = (nlll1i === 1'b1) ? nll0li : (~ nliO1l);
	and(wire_ni1iO_dataout, nll0ll, nlll1i);
	assign		wire_ni1li_dataout = (nlll1i === 1'b1) ? nll0lO : (~ nliO1l);
	assign		wire_ni1ll_dataout = (niOl0i === 1'b1) ? wire_n0llO_dataout : wire_nlOlii_dataout;
	assign		wire_ni1lO_dataout = (niOl0i === 1'b1) ? wire_n0lOi_dataout : (~ niOl1l);
	assign		wire_ni1Oi_dataout = (niOl0i === 1'b1) ? wire_n0lOl_dataout : wire_nlOlil_dataout;
	and(wire_ni1Ol_dataout, wire_n0llO_dataout, niOl0i);
	and(wire_ni1OO_dataout, wire_n0lOl_dataout, niOl0i);
	or(wire_nii1i_dataout, wire_ni1OO_dataout, ~(rd_enable_sync));
	or(wire_niill_dataout, wire_nil0l_o, nl1l0i);
	and(wire_niilO_dataout, wire_nil0O_o, ~(nl1l0i));
	or(wire_niiOi_dataout, wire_nilii_o, nl1l0i);
	or(wire_niiOl_dataout, wire_nilil_o, nl1l0i);
	or(wire_niiOO_dataout, wire_niliO_o, nl1l0i);
	or(wire_nil0i_dataout, wire_nilOi_o, nl1l0i);
	or(wire_nil1i_dataout, wire_nilli_o, nl1l0i);
	or(wire_nil1l_dataout, wire_nilll_o, nl1l0i);
	or(wire_nil1O_dataout, wire_nillO_o, nl1l0i);
	or(wire_nilOl_dataout, wire_niOil_dataout, ~(niOl0i));
	and(wire_nilOO_dataout, wire_niOiO_dataout, niOl0i);
	or(wire_niO0i_dataout, wire_niOOi_dataout, ~(niOl0i));
	assign		wire_niO0l_dataout = (niOl0i === 1'b1) ? wire_niOOl_dataout : (~ nliO1l);
	and(wire_niO0O_dataout, wire_niOOO_dataout, niOl0i);
	and(wire_niO1i_dataout, wire_niOli_dataout, niOl0i);
	or(wire_niO1l_dataout, wire_niOll_dataout, ~(niOl0i));
	or(wire_niO1O_dataout, wire_niOlO_dataout, ~(niOl0i));
	assign		wire_niOii_dataout = (niOl0i === 1'b1) ? wire_nl11i_dataout : (~ nliO1l);
	or(wire_niOil_dataout, tx_ctl[0], niOO1l);
	or(wire_niOiO_dataout, tx_data[0], niOO1l);
	and(wire_niOli_dataout, tx_data[1], ~(niOO1l));
	or(wire_niOll_dataout, tx_data[2], niOO1l);
	or(wire_niOlO_dataout, tx_data[3], niOO1l);
	or(wire_niOOi_dataout, tx_data[4], niOO1l);
	or(wire_niOOl_dataout, tx_data[5], niOO1l);
	or(wire_niOOO_dataout, tx_data[6], niOO1l);
	assign		wire_nl00i_dataout = (niOl0i === 1'b1) ? wire_niOOO_dataout : (~ niOl1l);
	assign		wire_nl00l_dataout = (niOl0i === 1'b1) ? wire_nl11i_dataout : wire_nlOlil_dataout;
	and(wire_nl00O_dataout, wire_niOOl_dataout, niOl0i);
	and(wire_nl01i_dataout, nll01O, nlll1i);
	assign		wire_nl01l_dataout = (nlll1i === 1'b1) ? nll00i : (~ nliO1l);
	assign		wire_nl01O_dataout = (niOl0i === 1'b1) ? wire_niOOl_dataout : wire_nlOlii_dataout;
	and(wire_nl0ii_dataout, wire_nl11i_dataout, niOl0i);
	assign		wire_nl0il_dataout = (niOl0i === 1'b1) ? wire_niOOl_dataout : wire_nl0li_dataout;
	assign		wire_nl0iO_dataout = (niOl0i === 1'b1) ? wire_nl11i_dataout : wire_nl0ll_dataout;
	and(wire_nl0li_dataout, nll01l, nlll1i);
	and(wire_nl0ll_dataout, nll00i, nlll1i);
	or(wire_nl0lO_dataout, wire_niOOl_dataout, ~(niOl0i));
	assign		wire_nl0Oi_dataout = (niOl0i === 1'b1) ? wire_niOOO_dataout : niOl1O;
	assign		wire_nl0Ol_dataout = (niOl0i === 1'b1) ? wire_nl11i_dataout : (~ niOl1O);
	or(wire_nl0OO_dataout, wire_nilOl_dataout, ~(rd_enable_sync));
	assign		wire_nl10i_dataout = (niOl0i === 1'b1) ? wire_niOll_dataout : wire_nl1lO_dataout;
	assign		wire_nl10l_dataout = (niOl0i === 1'b1) ? wire_niOlO_dataout : wire_nl1Oi_dataout;
	assign		wire_nl10O_dataout = (niOl0i === 1'b1) ? wire_niOOi_dataout : wire_nl1Ol_dataout;
	or(wire_nl11i_dataout, tx_data[7], niOO1l);
	assign		wire_nl11l_dataout = (niOl0i === 1'b1) ? wire_niOiO_dataout : wire_nl1li_dataout;
	assign		wire_nl11O_dataout = (niOl0i === 1'b1) ? wire_niOli_dataout : wire_nl1ll_dataout;
	assign		wire_nl1ii_dataout = (niOl0i === 1'b1) ? wire_niOOl_dataout : wire_nl1OO_dataout;
	assign		wire_nl1il_dataout = (niOl0i === 1'b1) ? wire_niOOO_dataout : wire_nl01i_dataout;
	assign		wire_nl1iO_dataout = (niOl0i === 1'b1) ? wire_nl11i_dataout : wire_nl01l_dataout;
	and(wire_nl1li_dataout, nll1ll, nlll1i);
	and(wire_nl1ll_dataout, nll1Oi, nlll1i);
	or(wire_nl1lO_dataout, nll1Ol, ~(nlll1i));
	or(wire_nl1Oi_dataout, nll1OO, ~(nlll1i));
	or(wire_nl1Ol_dataout, nll01i, ~(nlll1i));
	assign		wire_nl1OO_dataout = (nlll1i === 1'b1) ? nll01l : (~ nliO1l);
	or(wire_nli0i_dataout, wire_niO1O_dataout, ~(rd_enable_sync));
	or(wire_nli0l_dataout, wire_niO0i_dataout, ~(rd_enable_sync));
	or(wire_nli0O_dataout, wire_nl00O_dataout, ~(rd_enable_sync));
	and(wire_nli1i_dataout, wire_nilOO_dataout, rd_enable_sync);
	and(wire_nli1l_dataout, wire_niO1i_dataout, rd_enable_sync);
	or(wire_nli1O_dataout, wire_niO1l_dataout, ~(rd_enable_sync));
	and(wire_nliii_dataout, wire_niO0O_dataout, rd_enable_sync);
	or(wire_nliil_dataout, wire_nl0ii_dataout, ~(rd_enable_sync));
	and(wire_nlill_dataout, wire_nliOi_dataout, niOilO);
	and(wire_nlilO_dataout, niOili, niOilO);
	assign		wire_nliO0i_dataout = (niOi0l === 1'b1) ? nll10l : wire_nliOiO_dataout;
	assign		wire_nliO0l_dataout = (niOi0l === 1'b1) ? nll10O : wire_nliOli_dataout;
	assign		wire_nliO0O_dataout = (niOi0l === 1'b1) ? nll1ii : wire_nliOll_dataout;
	assign		wire_nliO1O_dataout = (niOi0l === 1'b1) ? nliO1l : wire_nliOil_dataout;
	or(wire_nliOi_dataout, (nliiO & niili), niOili);
	or(wire_nliOii_dataout, wire_nliOlO_dataout, niOi0l);
	assign		wire_nliOil_dataout = (niOl1l === 1'b1) ? wire_nliOOl_o[1] : nliOOi;
	assign		wire_nliOiO_dataout = (niOl1l === 1'b1) ? wire_nliOOl_o[2] : nlilOi;
	assign		wire_nliOli_dataout = (niOl1l === 1'b1) ? wire_nliOOl_o[3] : nlilOl;
	assign		wire_nliOll_dataout = (niOl1l === 1'b1) ? wire_nliOOl_o[4] : nlilOO;
	assign		wire_nliOlO_dataout = (niOl1l === 1'b1) ? wire_nliOOl_o[5] : nliO1i;
	and(wire_nllii_dataout, wire_nllil_dataout, ~(nlili));
	or(wire_nllil_dataout, nll0l, nliiO);
	and(wire_nlll0i_dataout, nlll1i, ~(niOilO));
	or(wire_nlll1O_dataout, wire_nlll0i_dataout, niOliO);
	or(wire_nllli_dataout, wire_nllll_dataout, (((((~ rd_enable_sync) & niOiOi) | wire_nlO0O_o) | ((rd_enable_sync & niOiOi) & niOl1i)) | (((~ nll0O) | niOl1l) & niOiOl)));
	and(wire_nllll_dataout, nll0O, ~((niOiOl & niOl1O)));
	or(wire_nlllOl_dataout, wire_nllOil_o, niOOil);
	and(wire_nlllOO_dataout, wire_nllOiO_o, ~(niOOil));
	or(wire_nllO0i_dataout, wire_nllOOi_o, niOOil);
	or(wire_nllO0l_dataout, wire_nllOOl_o, niOOil);
	or(wire_nllO0O_dataout, wire_nllOOO_o, niOOil);
	or(wire_nllO1i_dataout, wire_nllOli_o, niOOil);
	or(wire_nllO1l_dataout, wire_nllOll_o, niOOil);
	or(wire_nllO1O_dataout, wire_nllOlO_o, niOOil);
	or(wire_nllOii_dataout, wire_nlO11i_o, niOOil);
	or(wire_nlO00i_dataout, wire_nlO0Oi_dataout, niOiil);
	or(wire_nlO00l_dataout, tx_ctl[3], niOlli);
	or(wire_nlO00O_dataout, tx_data[24], niOlli);
	or(wire_nlO01i_dataout, wire_nlO0li_dataout, niOiil);
	or(wire_nlO01l_dataout, wire_nlO0ll_dataout, niOiil);
	and(wire_nlO01O_dataout, wire_nlO0lO_dataout, ~(niOiil));
	and(wire_nlO0ii_dataout, tx_data[25], ~(niOlli));
	or(wire_nlO0il_dataout, tx_data[26], niOlli);
	or(wire_nlO0iO_dataout, tx_data[27], niOlli);
	or(wire_nlO0li_dataout, tx_data[28], niOlli);
	or(wire_nlO0ll_dataout, tx_data[29], niOlli);
	or(wire_nlO0lO_dataout, tx_data[30], niOlli);
	or(wire_nlO0Oi_dataout, tx_data[31], niOlli);
	and(wire_nlO10i_dataout, wire_nlO1Oi_dataout, niOl0i);
	or(wire_nlO10l_dataout, wire_nlO1Ol_dataout, ~(niOl0i));
	or(wire_nlO10O_dataout, wire_nlO1OO_dataout, ~(niOl0i));
	or(wire_nlO11l_dataout, wire_nlO1ll_dataout, ~(niOl0i));
	and(wire_nlO11O_dataout, wire_nlO1lO_dataout, niOl0i);
	or(wire_nlO1ii_dataout, wire_nlO01i_dataout, ~(niOl0i));
	assign		wire_nlO1il_dataout = (niOl0i === 1'b1) ? wire_nlO01l_dataout : (~ nliO1l);
	and(wire_nlO1iO_dataout, wire_nlO01O_dataout, niOl0i);
	assign		wire_nlO1li_dataout = (niOl0i === 1'b1) ? wire_nlO00i_dataout : (~ nliO1l);
	or(wire_nlO1ll_dataout, wire_nlO00l_dataout, niOiil);
	and(wire_nlO1lO_dataout, wire_nlO00O_dataout, ~(niOiil));
	and(wire_nlO1Oi_dataout, wire_nlO0ii_dataout, ~(niOiil));
	or(wire_nlO1Ol_dataout, wire_nlO0il_dataout, niOiil);
	or(wire_nlO1OO_dataout, wire_nlO0iO_dataout, niOiil);
	assign		wire_nlOi0i_dataout = (niOl0i === 1'b1) ? wire_nlO1Oi_dataout : wire_nlOilO_dataout;
	assign		wire_nlOi0l_dataout = (niOl0i === 1'b1) ? wire_nlO1Ol_dataout : wire_nlOiOi_dataout;
	assign		wire_nlOi0O_dataout = (niOl0i === 1'b1) ? wire_nlO1OO_dataout : wire_nlOiOl_dataout;
	assign		wire_nlOi1l_dataout = (niOl0i === 1'b1) ? wire_nlO1ll_dataout : (~ nlll1i);
	assign		wire_nlOi1O_dataout = (niOl0i === 1'b1) ? wire_nlO1lO_dataout : wire_nlOill_dataout;
	assign		wire_nlOiii_dataout = (niOl0i === 1'b1) ? wire_nlO01i_dataout : wire_nlOiOO_dataout;
	assign		wire_nlOiil_dataout = (niOl0i === 1'b1) ? wire_nlO01l_dataout : wire_nlOl1i_dataout;
	assign		wire_nlOiiO_dataout = (niOl0i === 1'b1) ? wire_nlO01O_dataout : wire_nlOl1l_dataout;
	assign		wire_nlOili_dataout = (niOl0i === 1'b1) ? wire_nlO00i_dataout : wire_nlOl1O_dataout;
	and(wire_nlOill_dataout, nlli0O, nlll1i);
	and(wire_nlOilO_dataout, nlliil, nlll1i);
	or(wire_nlOiOi_dataout, nlliiO, ~(nlll1i));
	or(wire_nlOiOl_dataout, nllili, ~(nlll1i));
	or(wire_nlOiOO_dataout, nllill, ~(nlll1i));
	assign		wire_nlOl0i_dataout = (niOl0i === 1'b1) ? wire_nlO01l_dataout : wire_nlOlii_dataout;
	assign		wire_nlOl0l_dataout = (niOl0i === 1'b1) ? wire_nlO01O_dataout : (~ niOl1l);
	assign		wire_nlOl0O_dataout = (niOl0i === 1'b1) ? wire_nlO00i_dataout : wire_nlOlil_dataout;
	assign		wire_nlOl1i_dataout = (nlll1i === 1'b1) ? nllilO : (~ nliO1l);
	and(wire_nlOl1l_dataout, nlliOi, nlll1i);
	assign		wire_nlOl1O_dataout = (nlll1i === 1'b1) ? nlliOO : (~ nliO1l);
	or(wire_nlOlii_dataout, (~ nliO1l), (~ niOl1l));
	and(wire_nlOlil_dataout, (~ nliO1l), ~((~ niOl1l)));
	and(wire_nlOliO_dataout, wire_nlO01l_dataout, niOl0i);
	and(wire_nlOll_dataout, wire_n10O_dataout, wire_nlOlO_o[7]);
	and(wire_nlOlli_dataout, wire_nlO00i_dataout, niOl0i);
	assign		wire_nlOlll_dataout = (niOl0i === 1'b1) ? wire_nlO01l_dataout : wire_nlOlOi_dataout;
	assign		wire_nlOllO_dataout = (niOl0i === 1'b1) ? wire_nlO00i_dataout : wire_nlOlOl_dataout;
	and(wire_nlOlOi_dataout, nllilO, nlll1i);
	and(wire_nlOlOl_dataout, nlliOO, nlll1i);
	or(wire_nlOlOO_dataout, wire_nlO01l_dataout, ~(niOl0i));
	or(wire_nlOO0i_dataout, wire_nlO11l_dataout, ~(rd_enable_sync));
	and(wire_nlOO0l_dataout, wire_nlO11O_dataout, rd_enable_sync);
	and(wire_nlOO0O_dataout, wire_nlO10i_dataout, rd_enable_sync);
	assign		wire_nlOO1i_dataout = (niOl0i === 1'b1) ? wire_nlO01O_dataout : niOl1O;
	assign		wire_nlOO1l_dataout = (niOl0i === 1'b1) ? wire_nlO00i_dataout : (~ niOl1O);
	or(wire_nlOOi_dataout, wire_n11i_dataout, nlliO);
	or(wire_nlOOii_dataout, wire_nlO10l_dataout, ~(rd_enable_sync));
	or(wire_nlOOil_dataout, wire_nlO10O_dataout, ~(rd_enable_sync));
	or(wire_nlOOiO_dataout, wire_nlO1ii_dataout, ~(rd_enable_sync));
	or(wire_nlOOl_dataout, wire_n11l_dataout, nlliO);
	or(wire_nlOOli_dataout, wire_nlOliO_dataout, ~(rd_enable_sync));
	and(wire_nlOOll_dataout, wire_nlO1iO_dataout, rd_enable_sync);
	or(wire_nlOOlO_dataout, wire_nlOlli_dataout, ~(rd_enable_sync));
	and(wire_nlOOO_dataout, (~ niOl0i), ~(nlliO));
	oper_add   nliOOl
	( 
	.a({nliO1i, nlilOO, nlilOl, nlilOi, nliOOi, 1'b1}),
	.b({{4{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nliOOl_o));
	defparam
		nliOOl.sgate_representation = 0,
		nliOOl.width_a = 6,
		nliOOl.width_b = 6,
		nliOOl.width_o = 6;
	oper_decoder   nlOlO
	( 
	.i({ni1l, n0OO, n0Ol, n0lO}),
	.o(wire_nlOlO_o));
	defparam
		nlOlO.width_i = 4,
		nlOlO.width_o = 16;
	oper_less_than   nlO0O
	( 
	.a({1'b1, {3{1'b0}}}),
	.b({ni1l, n0OO, n0Ol, n0lO}),
	.cin(1'b0),
	.o(wire_nlO0O_o));
	defparam
		nlO0O.sgate_representation = 0,
		nlO0O.width_a = 4,
		nlO0O.width_b = 4;
	oper_mux   n0i0i
	( 
	.data({{7{1'b0}}, wire_n0iOi_dataout, wire_n0Oli_dataout, {3{wire_n0iOi_dataout}}, wire_ni0iO_dataout, wire_n0Oli_dataout, wire_n0iOi_dataout, 1'b0}),
	.o(wire_n0i0i_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0i0i.width_data = 16,
		n0i0i.width_sel = 4;
	oper_mux   n0i0l
	( 
	.data({{7{1'b0}}, wire_n0iOl_dataout, wire_n0Oll_dataout, {3{wire_n0iOl_dataout}}, wire_ni0li_dataout, wire_n0Oll_dataout, wire_n0iOl_dataout, 1'b0}),
	.o(wire_n0i0l_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0i0l.width_data = 16,
		n0i0l.width_sel = 4;
	oper_mux   n0i0O
	( 
	.data({{7{1'b1}}, wire_n0iOO_dataout, wire_n0OlO_dataout, {3{wire_n0iOO_dataout}}, wire_ni0ll_dataout, wire_n0OlO_dataout, wire_n0iOO_dataout, 1'b1}),
	.o(wire_n0i0O_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0i0O.width_data = 16,
		n0i0O.width_sel = 4;
	oper_mux   n0i1O
	( 
	.data({{7{1'b1}}, wire_n0ilO_dataout, wire_n0OiO_dataout, {3{wire_n0ilO_dataout}}, wire_ni0il_dataout, wire_n0OiO_dataout, wire_n0ilO_dataout, 1'b1}),
	.o(wire_n0i1O_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0i1O.width_data = 16,
		n0i1O.width_sel = 4;
	oper_mux   n0iii
	( 
	.data({{7{1'b1}}, wire_n0l1i_dataout, wire_n0OOi_dataout, {3{wire_n0l1i_dataout}}, wire_ni0lO_dataout, wire_n0OOi_dataout, wire_n0l1i_dataout, 1'b1}),
	.o(wire_n0iii_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0iii.width_data = 16,
		n0iii.width_sel = 4;
	oper_mux   n0iil
	( 
	.data({{7{1'b1}}, wire_n0l1l_dataout, wire_n0OOl_dataout, {3{wire_n0l1l_dataout}}, wire_ni0Oi_dataout, wire_n0OOl_dataout, wire_n0l1l_dataout, 1'b1}),
	.o(wire_n0iil_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0iil.width_data = 16,
		n0iil.width_sel = 4;
	oper_mux   n0iiO
	( 
	.data({{7{1'b1}}, wire_n0l1O_dataout, wire_n0OOO_dataout, {2{wire_ni1ll_dataout}}, wire_ni1Ol_dataout, wire_ni0Ol_dataout, wire_ni01i_dataout, wire_ni00l_dataout, 1'b1}),
	.o(wire_n0iiO_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0iiO.width_data = 16,
		n0iiO.width_sel = 4;
	oper_mux   n0ili
	( 
	.data({{7{1'b0}}, wire_n0l0i_dataout, wire_ni11i_dataout, {2{wire_ni1lO_dataout}}, wire_n0l0i_dataout, wire_ni0OO_dataout, wire_ni11i_dataout, wire_ni00O_dataout, 1'b0}),
	.o(wire_n0ili_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0ili.width_data = 16,
		n0ili.width_sel = 4;
	oper_mux   n0ill
	( 
	.data({{7{1'b1}}, wire_n0l0l_dataout, wire_ni11l_dataout, {2{wire_ni1Oi_dataout}}, wire_ni1OO_dataout, wire_nii1i_dataout, wire_ni01l_dataout, wire_ni0ii_dataout, 1'b1}),
	.o(wire_n0ill_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n0ill.width_data = 16,
		n0ill.width_sel = 4;
	oper_mux   n100i
	( 
	.data({{7{1'b1}}, wire_n10Oi_dataout, wire_n1lli_dataout, {3{wire_n10Oi_dataout}}, wire_n01iO_dataout, wire_n1lli_dataout, wire_n10Oi_dataout, 1'b1}),
	.o(wire_n100i_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n100i.width_data = 16,
		n100i.width_sel = 4;
	oper_mux   n100l
	( 
	.data({{7{1'b1}}, wire_n10Ol_dataout, wire_n1lll_dataout, {3{wire_n10Ol_dataout}}, wire_n01li_dataout, wire_n1lll_dataout, wire_n10Ol_dataout, 1'b1}),
	.o(wire_n100l_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n100l.width_data = 16,
		n100l.width_sel = 4;
	oper_mux   n100O
	( 
	.data({{7{1'b1}}, wire_n10OO_dataout, wire_n1llO_dataout, {3{wire_n10OO_dataout}}, wire_n01ll_dataout, wire_n1llO_dataout, wire_n10OO_dataout, 1'b1}),
	.o(wire_n100O_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n100O.width_data = 16,
		n100O.width_sel = 4;
	oper_mux   n101i
	( 
	.data({{7{1'b1}}, wire_n10li_dataout, wire_n1lii_dataout, {3{wire_n10li_dataout}}, wire_n010O_dataout, wire_n1lii_dataout, wire_n10li_dataout, 1'b1}),
	.o(wire_n101i_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n101i.width_data = 16,
		n101i.width_sel = 4;
	oper_mux   n101l
	( 
	.data({{7{1'b0}}, wire_n10ll_dataout, wire_n1lil_dataout, {3{wire_n10ll_dataout}}, wire_n01ii_dataout, wire_n1lil_dataout, wire_n10ll_dataout, 1'b0}),
	.o(wire_n101l_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n101l.width_data = 16,
		n101l.width_sel = 4;
	oper_mux   n101O
	( 
	.data({{7{1'b0}}, wire_n10lO_dataout, wire_n1liO_dataout, {3{wire_n10lO_dataout}}, wire_n01il_dataout, wire_n1liO_dataout, wire_n10lO_dataout, 1'b0}),
	.o(wire_n101O_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n101O.width_data = 16,
		n101O.width_sel = 4;
	oper_mux   n10ii
	( 
	.data({{7{1'b1}}, wire_n1i1i_dataout, wire_n1lOi_dataout, {2{wire_n1OiO_dataout}}, wire_n1OlO_dataout, wire_n01lO_dataout, wire_n1OOl_dataout, wire_n011O_dataout, 1'b1}),
	.o(wire_n10ii_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n10ii.width_data = 16,
		n10ii.width_sel = 4;
	oper_mux   n10il
	( 
	.data({{7{1'b0}}, wire_n1i1l_dataout, wire_n1lOl_dataout, {2{wire_n1Oli_dataout}}, wire_n1i1l_dataout, wire_n01Oi_dataout, wire_n1lOl_dataout, wire_n010i_dataout, 1'b0}),
	.o(wire_n10il_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n10il.width_data = 16,
		n10il.width_sel = 4;
	oper_mux   n10iO
	( 
	.data({{7{1'b1}}, wire_n1i1O_dataout, wire_n1lOO_dataout, {2{wire_n1Oll_dataout}}, wire_n1OOi_dataout, wire_n01Ol_dataout, wire_n1OOO_dataout, wire_n010l_dataout, 1'b1}),
	.o(wire_n10iO_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		n10iO.width_data = 16,
		n10iO.width_sel = 4;
	oper_mux   nil0l
	( 
	.data({{7{1'b1}}, {5{wire_nilOl_dataout}}, wire_nl0OO_dataout, {2{wire_nilOl_dataout}}, 1'b1}),
	.o(wire_nil0l_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nil0l.width_data = 16,
		nil0l.width_sel = 4;
	oper_mux   nil0O
	( 
	.data({{7{1'b0}}, wire_nilOO_dataout, wire_nl11l_dataout, {3{wire_nilOO_dataout}}, wire_nli1i_dataout, wire_nl11l_dataout, wire_nilOO_dataout, 1'b0}),
	.o(wire_nil0O_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nil0O.width_data = 16,
		nil0O.width_sel = 4;
	oper_mux   nilii
	( 
	.data({{7{1'b0}}, wire_niO1i_dataout, wire_nl11O_dataout, {3{wire_niO1i_dataout}}, wire_nli1l_dataout, wire_nl11O_dataout, wire_niO1i_dataout, 1'b0}),
	.o(wire_nilii_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nilii.width_data = 16,
		nilii.width_sel = 4;
	oper_mux   nilil
	( 
	.data({{7{1'b1}}, wire_niO1l_dataout, wire_nl10i_dataout, {3{wire_niO1l_dataout}}, wire_nli1O_dataout, wire_nl10i_dataout, wire_niO1l_dataout, 1'b1}),
	.o(wire_nilil_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nilil.width_data = 16,
		nilil.width_sel = 4;
	oper_mux   niliO
	( 
	.data({{7{1'b1}}, wire_niO1O_dataout, wire_nl10l_dataout, {3{wire_niO1O_dataout}}, wire_nli0i_dataout, wire_nl10l_dataout, wire_niO1O_dataout, 1'b1}),
	.o(wire_niliO_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		niliO.width_data = 16,
		niliO.width_sel = 4;
	oper_mux   nilli
	( 
	.data({{7{1'b1}}, wire_niO0i_dataout, wire_nl10O_dataout, {3{wire_niO0i_dataout}}, wire_nli0l_dataout, wire_nl10O_dataout, wire_niO0i_dataout, 1'b1}),
	.o(wire_nilli_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nilli.width_data = 16,
		nilli.width_sel = 4;
	oper_mux   nilll
	( 
	.data({{7{1'b1}}, wire_niO0l_dataout, wire_nl1ii_dataout, {2{wire_nl01O_dataout}}, wire_nl00O_dataout, wire_nli0O_dataout, wire_nl0il_dataout, wire_nl0lO_dataout, 1'b1}),
	.o(wire_nilll_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nilll.width_data = 16,
		nilll.width_sel = 4;
	oper_mux   nillO
	( 
	.data({{7{1'b0}}, wire_niO0O_dataout, wire_nl1il_dataout, {2{wire_nl00i_dataout}}, wire_niO0O_dataout, wire_nliii_dataout, wire_nl1il_dataout, wire_nl0Oi_dataout, 1'b0}),
	.o(wire_nillO_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nillO.width_data = 16,
		nillO.width_sel = 4;
	oper_mux   nilOi
	( 
	.data({{7{1'b1}}, wire_niOii_dataout, wire_nl1iO_dataout, {2{wire_nl00l_dataout}}, wire_nl0ii_dataout, wire_nliil_dataout, wire_nl0iO_dataout, wire_nl0Ol_dataout, 1'b1}),
	.o(wire_nilOi_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nilOi.width_data = 16,
		nilOi.width_sel = 4;
	oper_mux   nllOil
	( 
	.data({{7{1'b1}}, wire_nlO11l_dataout, wire_nlOi1l_dataout, {3{wire_nlO11l_dataout}}, wire_nlOO0i_dataout, wire_nlOi1l_dataout, wire_nlO11l_dataout, 1'b1}),
	.o(wire_nllOil_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nllOil.width_data = 16,
		nllOil.width_sel = 4;
	oper_mux   nllOiO
	( 
	.data({{7{1'b0}}, wire_nlO11O_dataout, wire_nlOi1O_dataout, {3{wire_nlO11O_dataout}}, wire_nlOO0l_dataout, wire_nlOi1O_dataout, wire_nlO11O_dataout, 1'b0}),
	.o(wire_nllOiO_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nllOiO.width_data = 16,
		nllOiO.width_sel = 4;
	oper_mux   nllOli
	( 
	.data({{7{1'b0}}, wire_nlO10i_dataout, wire_nlOi0i_dataout, {3{wire_nlO10i_dataout}}, wire_nlOO0O_dataout, wire_nlOi0i_dataout, wire_nlO10i_dataout, 1'b0}),
	.o(wire_nllOli_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nllOli.width_data = 16,
		nllOli.width_sel = 4;
	oper_mux   nllOll
	( 
	.data({{7{1'b1}}, wire_nlO10l_dataout, wire_nlOi0l_dataout, {3{wire_nlO10l_dataout}}, wire_nlOOii_dataout, wire_nlOi0l_dataout, wire_nlO10l_dataout, 1'b1}),
	.o(wire_nllOll_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nllOll.width_data = 16,
		nllOll.width_sel = 4;
	oper_mux   nllOlO
	( 
	.data({{7{1'b1}}, wire_nlO10O_dataout, wire_nlOi0O_dataout, {3{wire_nlO10O_dataout}}, wire_nlOOil_dataout, wire_nlOi0O_dataout, wire_nlO10O_dataout, 1'b1}),
	.o(wire_nllOlO_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nllOlO.width_data = 16,
		nllOlO.width_sel = 4;
	oper_mux   nllOOi
	( 
	.data({{7{1'b1}}, wire_nlO1ii_dataout, wire_nlOiii_dataout, {3{wire_nlO1ii_dataout}}, wire_nlOOiO_dataout, wire_nlOiii_dataout, wire_nlO1ii_dataout, 1'b1}),
	.o(wire_nllOOi_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nllOOi.width_data = 16,
		nllOOi.width_sel = 4;
	oper_mux   nllOOl
	( 
	.data({{7{1'b1}}, wire_nlO1il_dataout, wire_nlOiil_dataout, {2{wire_nlOl0i_dataout}}, wire_nlOliO_dataout, wire_nlOOli_dataout, wire_nlOlll_dataout, wire_nlOlOO_dataout, 1'b1}),
	.o(wire_nllOOl_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nllOOl.width_data = 16,
		nllOOl.width_sel = 4;
	oper_mux   nllOOO
	( 
	.data({{7{1'b0}}, wire_nlO1iO_dataout, wire_nlOiiO_dataout, {2{wire_nlOl0l_dataout}}, wire_nlO1iO_dataout, wire_nlOOll_dataout, wire_nlOiiO_dataout, wire_nlOO1i_dataout, 1'b0}),
	.o(wire_nllOOO_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nllOOO.width_data = 16,
		nllOOO.width_sel = 4;
	oper_mux   nlO11i
	( 
	.data({{7{1'b1}}, wire_nlO1li_dataout, wire_nlOili_dataout, {2{wire_nlOl0O_dataout}}, wire_nlOlli_dataout, wire_nlOOlO_dataout, wire_nlOllO_dataout, wire_nlOO1l_dataout, 1'b1}),
	.o(wire_nlO11i_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nlO11i.width_data = 16,
		nlO11i.width_sel = 4;
	oper_mux   nlOil
	( 
	.data({{7{1'b1}}, wire_nlOOi_dataout, wire_n11O_dataout, {2{wire_n1Oi_dataout}}, {2{1'b1}}, wire_n01O_dataout, wire_n00l_dataout, 1'b1}),
	.o(wire_nlOil_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nlOil.width_data = 16,
		nlOil.width_sel = 4;
	oper_mux   nlOiO
	( 
	.data({{7{1'b1}}, wire_nlOOl_dataout, wire_n10i_dataout, {2{wire_n1Ol_dataout}}, nlliO, wire_n0il_dataout, nlliO, wire_n00O_dataout, 1'b1}),
	.o(wire_nlOiO_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nlOiO.width_data = 16,
		nlOiO.width_sel = 4;
	oper_mux   nlOli
	( 
	.data({{7{1'b0}}, wire_nlOOO_dataout, wire_n10l_dataout, {3{wire_nlOOO_dataout}}, wire_n0iO_dataout, wire_nlOOO_dataout, {2{1'b0}}}),
	.o(wire_nlOli_o),
	.sel({ni1l, n0OO, n0Ol, n0lO}));
	defparam
		nlOli.width_data = 16,
		nlOli.width_sel = 4;
	assign
		curr_state = {ni1l, n0OO, n0Ol, n0lO},
		niOi0l = ((niOl1i & (~ niOl1l)) & ((((((~ ni1l) & n0OO) & n0Ol) & (~ n0lO)) | ((((~ ni1l) & n0OO) & (~ n0Ol)) & n0lO)) | (nll0O & niOiOO))),
		niOiil = (niOlll | niOiiO),
		niOiiO = (niOO1l | niOlOi),
		niOili = (niOill & ((~ nliiO) & (~ niili))),
		niOill = ((((((((((((((((((((((((~ nlliOO) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & (~ nlliil)) & nlli0O) & (~ nlli0l)) & (~ nlli0i)) & (~ nlli1O)) & (~ nlli1l)) & (~ nlli1i)) & (~ nll0OO)) & (~ nll0Ol)) & (~ nll0Oi)) & (~ nll0lO)) & (~ nll0ll)) & (~ nll0li)) & (~ nll0iO)) & (~ nll0il)) & (~ nll0ii)) & (~ nll00O)) & (~ nll00l)),
		niOilO = (((((((~ ni1l) & (~ n0OO)) & n0Ol) & (~ n0lO)) | ((((~ ni1l) & n0OO) & n0Ol) & n0lO)) & niOl1i) & nlll1i),
		niOiOi = ((((~ ni1l) & (~ n0OO)) & n0Ol) & n0lO),
		niOiOl = (niOl1i & niOiOO),
		niOiOO = ((((~ ni1l) & (~ n0OO)) & (~ n0Ol)) & n0lO),
		niOl0i = ((~ niOO0O) & (~ niOliO)),
		niOl1i = (niOO0O | niOliO),
		niOl1l = ((((nliOOi | nliO1i) | nlilOO) | nlilOl) | nlilOi),
		niOl1O = (nll0O & (~ niOl1l)),
		niOlii = 1'b1,
		niOliO = ((((tx_ctl[0] & (~ tx_ctl[1])) & (~ tx_ctl[2])) & (~ tx_ctl[3])) & nl1O0l),
		niOlli = (tx_ctl[3] & nl11ii),
		niOlll = ((tx_ctl[2] & tx_ctl[3]) & niOllO),
		niOllO = (((((((((((((((tx_data[16] & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]) & tx_data[24]) & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])),
		niOlOi = ((((tx_ctl[1] & tx_ctl[2]) & tx_ctl[3]) & niOO1i) & (niOlOl40 ^ niOlOl39)),
		niOO0O = ((((tx_ctl[0] & tx_ctl[1]) & tx_ctl[2]) & tx_ctl[3]) & niOOii),
		niOO1i = (((((((((((((((((((((((tx_data[8] & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]) & tx_data[16]) & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & (~ tx_data[20])) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])) & tx_data[24]) & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])),
		niOO1l = (((((tx_ctl[0] & tx_ctl[1]) & tx_ctl[2]) & tx_ctl[3]) & (niOO0i38 ^ niOO0i37)) & niOO1O),
		niOO1O = (((((((((((((((((((((((((((((((tx_data[0] & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]) & tx_data[8]) & tx_data[9]) & tx_data[10]) & (~ tx_data[11])) & (~ tx_data[12])) & (~ tx_data[13])) & (~ tx_data[14])) & (~ tx_data[15])) & tx_data[16]) & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & (~ tx_data[20])) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])) & tx_data[24]) & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])),
		niOOii = (((((((((((((((((((((((((((((((tx_data[0] & tx_data[1]) & tx_data[2]) & (~ tx_data[3])) & (~ tx_data[4])) & (~ tx_data[5])) & (~ tx_data[6])) & (~ tx_data[7])) & tx_data[8]) & tx_data[9]) & tx_data[10]) & (~ tx_data[11])) & (~ tx_data[12])) & (~ tx_data[13])) & (~ tx_data[14])) & (~ tx_data[15])) & tx_data[16]) & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & (~ tx_data[20])) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])) & tx_data[24]) & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])),
		niOOil = (((((((((((((((tx_ctl[3] & (~ nl11Ol)) & (nl11lO26 ^ nl11lO25)) & (~ nl11ll)) & (~ nl11li)) & (nl11il28 ^ nl11il27)) & (~ nl11ii)) & (nl110l30 ^ nl110l29)) & (~ nl110i)) & (nl111l32 ^ nl111l31)) & (~ nl111i)) & (~ niOOOO)) & (niOOOi34 ^ niOOOi33)) & (~ niOOlO)) & (~ niOOll)) & (niOOiO36 ^ niOOiO35)),
		niOOll = (((((((tx_data[24] & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & tx_data[28]) & tx_data[29]) & tx_data[30]) & tx_data[31]),
		niOOlO = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & tx_data[29]) & tx_data[30]) & tx_data[31]),
		niOOOO = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & (~ tx_data[29])) & tx_data[30]) & tx_data[31]),
		nl100l = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & (~ tx_data[21])) & tx_data[22]) & tx_data[23]),
		nl101i = (((((((tx_data[16] & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]),
		nl101l = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]),
		nl10il = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & (~ tx_data[21])) & tx_data[22]) & (~ tx_data[23])),
		nl10iO = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & (~ tx_data[22])) & (~ tx_data[23])),
		nl10li = (((((((tx_data[16] & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]),
		nl10ll = (((((((tx_data[16] & tx_data[17]) & (~ tx_data[18])) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]),
		nl10Ol = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & (~ tx_data[21])) & (~ tx_data[22])) & tx_data[23]),
		nl110i = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & tx_data[29]) & (~ tx_data[30])) & (~ tx_data[31])),
		nl111i = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & (~ tx_data[29])) & tx_data[30]) & (~ tx_data[31])),
		nl11ii = (((((((tx_data[24] & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & tx_data[29]) & tx_data[30]) & tx_data[31]),
		nl11li = (((((((tx_data[24] & tx_data[25]) & (~ tx_data[26])) & tx_data[27]) & tx_data[28]) & tx_data[29]) & tx_data[30]) & tx_data[31]),
		nl11ll = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & (~ tx_data[29])) & (~ tx_data[30])) & tx_data[31]),
		nl11Ol = (((((((tx_data[24] & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])),
		nl11OO = (((((((((((((tx_ctl[2] & (~ nl1i1l)) & (nl10OO18 ^ nl10OO17)) & (~ nl10Ol)) & (nl10lO20 ^ nl10lO19)) & (~ nl10ll)) & (~ nl10li)) & (~ nl10iO)) & (~ nl10il)) & (nl100O22 ^ nl100O21)) & (~ nl100l)) & (nl101O24 ^ nl101O23)) & (~ nl101l)) & (~ nl101i)),
		nl1i0i = (((((((tx_data[8] & tx_data[9]) & tx_data[10]) & (~ tx_data[11])) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]),
		nl1i0l = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]),
		nl1i1l = (((((((tx_data[16] & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & (~ tx_data[20])) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])),
		nl1i1O = ((((((((((((tx_ctl[1] & (~ nl1l1O)) & (nl1l1i12 ^ nl1l1i11)) & (~ nl1iOO)) & (~ nl1iOl)) & (nl1ilO14 ^ nl1ilO13)) & (~ nl1ill)) & (~ nl1ili)) & (~ nl1iiO)) & (~ nl1iil)) & (nl1i0O16 ^ nl1i0O15)) & (~ nl1i0l)) & (~ nl1i0i)),
		nl1iil = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & (~ tx_data[13])) & tx_data[14]) & tx_data[15]),
		nl1iiO = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & (~ tx_data[13])) & tx_data[14]) & (~ tx_data[15])),
		nl1ili = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & (~ tx_data[14])) & (~ tx_data[15])),
		nl1ill = (((((((tx_data[8] & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]),
		nl1iOl = (((((((tx_data[8] & tx_data[9]) & (~ tx_data[10])) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]),
		nl1iOO = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & (~ tx_data[13])) & (~ tx_data[14])) & tx_data[15]),
		nl1l0i = ((((((((((((((tx_ctl[0] & (~ nl1Oli)) & (nl1O0O2 ^ nl1O0O1)) & (~ nl1O0l)) & (~ nl1O0i)) & (nl1O1l4 ^ nl1O1l3)) & (~ nl1O1i)) & (~ nl1lOO)) & (nl1lOi6 ^ nl1lOi5)) & (~ nl1llO)) & (~ nl1lll)) & (~ nl1lli)) & (nl1lil8 ^ nl1lil7)) & (~ nl1lii)) & (nl1l0l10 ^ nl1l0l9)),
		nl1l1O = (((((((tx_data[8] & tx_data[9]) & tx_data[10]) & (~ tx_data[11])) & (~ tx_data[12])) & (~ tx_data[13])) & (~ tx_data[14])) & (~ tx_data[15])),
		nl1lii = (((((((tx_data[0] & tx_data[1]) & tx_data[2]) & (~ tx_data[3])) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]),
		nl1lli = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]),
		nl1lll = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & (~ tx_data[5])) & tx_data[6]) & tx_data[7]),
		nl1llO = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & (~ tx_data[5])) & tx_data[6]) & (~ tx_data[7])),
		nl1lOO = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & (~ tx_data[6])) & (~ tx_data[7])),
		nl1O0i = (((((((tx_data[0] & tx_data[1]) & (~ tx_data[2])) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]),
		nl1O0l = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & (~ tx_data[5])) & (~ tx_data[6])) & tx_data[7]),
		nl1O1i = (((((((tx_data[0] & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]),
		nl1Oli = (((((((tx_data[0] & tx_data[1]) & tx_data[2]) & (~ tx_data[3])) & (~ tx_data[4])) & (~ tx_data[5])) & (~ tx_data[6])) & (~ tx_data[7])),
		sm_ctl = {nlll1l, nlllOi, n110O, n00il},
		sm_data = {nllllO, nlllll, nlllli, nllliO, nlllil, nlllii, nlll0O, nlll0l, n110l, n110i, n111O, n111l, n111i, nlOOOO, nlOOOl, nlOOOi, n00ii, n000O, n000l, n000i, n001O, n001l, n001i, n01OO, niiiO, niiil, niiii, nii0O, nii0l, nii0i, nii1O, nii1l},
		tx_local_fault = nll0l,
		tx_local_fault_det = niili;
endmodule //arriagx_hssi_tx_sm
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 131 mux21 352 oper_mux 3 
`timescale 1 ps / 1 ps
module  arriagx_hssi_rcv_sm
	( 
	clk_2,
	curr_state,
	dec_ctl,
	dec_data,
	dec_data_valid,
	indv,
	running_disp,
	rx_ctl_rs,
	rx_data_rs,
	rx_local_fault,
	rx_local_fault_clr,
	soft_reset,
	tx_local_fault_det,
	xs_link_status,
	xs_link_status_set) /* synthesis synthesis_clearbox=1 */;
	input   clk_2;
	output   [1:0]  curr_state;
	input   [3:0]  dec_ctl;
	input   [31:0]  dec_data;
	input   [3:0]  dec_data_valid;
	input   indv;
	input   [3:0]  running_disp;
	output   [3:0]  rx_ctl_rs;
	output   [31:0]  rx_data_rs;
	output   rx_local_fault;
	input   rx_local_fault_clr;
	input   soft_reset;
	input   tx_local_fault_det;
	output   xs_link_status;
	input   xs_link_status_set;

	reg	nl000i31;
	reg	nl000i32;
	reg	nl000l29;
	reg	nl000l30;
	reg	nl001O33;
	reg	nl001O34;
	reg	nl00ii27;
	reg	nl00ii28;
	reg	nl00iO25;
	reg	nl00iO26;
	reg	nl00ll23;
	reg	nl00ll24;
	reg	nl00Oi21;
	reg	nl00Oi22;
	reg	nl010l41;
	reg	nl010l42;
	reg	nl011i43;
	reg	nl011i44;
	reg	nl01il39;
	reg	nl01il40;
	reg	nl01li37;
	reg	nl01li38;
	reg	nl01Ol35;
	reg	nl01Ol36;
	reg	nl0i0l17;
	reg	nl0i0l18;
	reg	nl0i1l19;
	reg	nl0i1l20;
	reg	nl0iiO15;
	reg	nl0iiO16;
	reg	nl0iOO13;
	reg	nl0iOO14;
	reg	nl0l0O11;
	reg	nl0l0O12;
	reg	nl0lli10;
	reg	nl0lli9;
	reg	nl0lOl7;
	reg	nl0lOl8;
	reg	nl0O0l5;
	reg	nl0O0l6;
	reg	nl0OiO3;
	reg	nl0OiO4;
	reg	nl0OOi1;
	reg	nl0OOi2;
	reg	n001i;
	reg	n01il;
	reg	n01lO;
	reg	n01Oi;
	reg	n0l0i;
	reg	n0l0l;
	reg	n0l0O;
	reg	n0l1O;
	reg	n0lii;
	reg	n0lil;
	reg	n0liO;
	reg	n0lli;
	reg	n0lll;
	reg	n0Oi;
	reg	n0Ol;
	reg	n0OO;
	reg	n100i;
	reg	n100l;
	reg	n100O;
	reg	n101i;
	reg	n101l;
	reg	n101O;
	reg	n10ii;
	reg	n10il;
	reg	n10iO;
	reg	n10li;
	reg	ni0i;
	reg	ni0l;
	reg	ni0O;
	reg	ni1i;
	reg	ni1l;
	reg	ni1O;
	reg	nii0i;
	reg	nii0l;
	reg	nii0O;
	reg	nii1i;
	reg	nii1l;
	reg	nii1O;
	reg	niiii;
	reg	niiil;
	reg	nill;
	reg	nl00i;
	reg	nl00l;
	reg	nl01i;
	reg	nl01l;
	reg	nl01O;
	reg	nl1Oi;
	reg	nl1Ol;
	reg	nl1OO;
	reg	nllii;
	reg	nlliii;
	reg	nlliil;
	reg	nlliiO;
	reg	nllil;
	reg	nllili;
	reg	nllill;
	reg	nllilO;
	reg	nlliOi;
	reg	nlliOl;
	reg	nlliOO;
	reg	nlll1i;
	reg	nlll1l;
	reg	nlll1O;
	reg	nlllO;
	reg	nllOi;
	reg	nllOO;
	reg	nlO0Oi;
	reg	nlO0Ol;
	reg	nlO0OO;
	reg	nlOi0i;
	reg	nlOi0l;
	reg	nlOi1i;
	reg	nlOi1l;
	reg	nlOi1O;
	reg	nili_clk_prev;
	wire	wire_nili_PRN;
	reg	n01iO;
	reg	n01li;
	reg	n01ll;
	reg	n01Ol;
	reg	n01OO;
	reg	niiiO;
	reg	niOi;
	reg	nl00O;
	reg	nlliO;
	reg	nllli;
	reg	nllll;
	reg	nllOl;
	reg	nlOi0O;
	reg	nilO_clk_prev;
	wire	wire_nilO_CLRN;
	wire	wire_n000i_dataout;
	wire	wire_n000l_dataout;
	wire	wire_n000O_dataout;
	wire	wire_n001l_dataout;
	wire	wire_n001O_dataout;
	wire	wire_n00i_dataout;
	wire	wire_n00ii_dataout;
	wire	wire_n00il_dataout;
	wire	wire_n00iO_dataout;
	wire	wire_n00l_dataout;
	wire	wire_n00li_dataout;
	wire	wire_n00ll_dataout;
	wire	wire_n00lO_dataout;
	wire	wire_n00O_dataout;
	wire	wire_n00Oi_dataout;
	wire	wire_n00Ol_dataout;
	wire	wire_n00OO_dataout;
	wire	wire_n010i_dataout;
	wire	wire_n011i_dataout;
	wire	wire_n011l_dataout;
	wire	wire_n011O_dataout;
	wire	wire_n01i_dataout;
	wire	wire_n01l_dataout;
	wire	wire_n01O_dataout;
	wire	wire_n0i0i_dataout;
	wire	wire_n0i0l_dataout;
	wire	wire_n0i0O_dataout;
	wire	wire_n0i1i_dataout;
	wire	wire_n0i1l_dataout;
	wire	wire_n0i1O_dataout;
	wire	wire_n0iii_dataout;
	wire	wire_n0iil_dataout;
	wire	wire_n0iiO_dataout;
	wire	wire_n0ili_dataout;
	wire	wire_n0ill_dataout;
	wire	wire_n0ilO_dataout;
	wire	wire_n0iOi_dataout;
	wire	wire_n0li_dataout;
	wire	wire_n0ll_dataout;
	wire	wire_n0llO_dataout;
	wire	wire_n0lOi_dataout;
	wire	wire_n0lOl_dataout;
	wire	wire_n0lOO_dataout;
	wire	wire_n0O0i_dataout;
	wire	wire_n0O0l_dataout;
	wire	wire_n0O0O_dataout;
	wire	wire_n0O1i_dataout;
	wire	wire_n0O1l_dataout;
	wire	wire_n0O1O_dataout;
	wire	wire_n0Oii_dataout;
	wire	wire_n0Oil_dataout;
	wire	wire_n0OiO_dataout;
	wire	wire_n0Oli_dataout;
	wire	wire_n0Oll_dataout;
	wire	wire_n0OlO_dataout;
	wire	wire_n0OOi_dataout;
	wire	wire_n0OOl_dataout;
	wire	wire_n0OOO_dataout;
	wire	wire_n10i_dataout;
	wire	wire_n10l_dataout;
	wire	wire_n10ll_dataout;
	wire	wire_n10lO_dataout;
	wire	wire_n10O_dataout;
	wire	wire_n10Oi_dataout;
	wire	wire_n10Ol_dataout;
	wire	wire_n10OO_dataout;
	wire	wire_n110i_dataout;
	wire	wire_n110l_dataout;
	wire	wire_n110O_dataout;
	wire	wire_n111i_dataout;
	wire	wire_n111l_dataout;
	wire	wire_n111O_dataout;
	wire	wire_n11i_dataout;
	wire	wire_n11ii_dataout;
	wire	wire_n11il_dataout;
	wire	wire_n11iO_dataout;
	wire	wire_n11l_dataout;
	wire	wire_n11li_dataout;
	wire	wire_n11ll_dataout;
	wire	wire_n11lO_dataout;
	wire	wire_n11O_dataout;
	wire	wire_n11Oi_dataout;
	wire	wire_n11Ol_dataout;
	wire	wire_n11OO_dataout;
	wire	wire_n1i0i_dataout;
	wire	wire_n1i0l_dataout;
	wire	wire_n1i0O_dataout;
	wire	wire_n1i1i_dataout;
	wire	wire_n1i1l_dataout;
	wire	wire_n1i1O_dataout;
	wire	wire_n1ii_dataout;
	wire	wire_n1iii_dataout;
	wire	wire_n1iil_dataout;
	wire	wire_n1iiO_dataout;
	wire	wire_n1il_dataout;
	wire	wire_n1ili_dataout;
	wire	wire_n1ill_dataout;
	wire	wire_n1ilO_dataout;
	wire	wire_n1iO_dataout;
	wire	wire_n1iOi_dataout;
	wire	wire_n1iOl_dataout;
	wire	wire_n1iOO_dataout;
	wire	wire_n1l0i_dataout;
	wire	wire_n1l0l_dataout;
	wire	wire_n1l0O_dataout;
	wire	wire_n1l1i_dataout;
	wire	wire_n1l1l_dataout;
	wire	wire_n1l1O_dataout;
	wire	wire_n1li_dataout;
	wire	wire_n1lii_dataout;
	wire	wire_n1lil_dataout;
	wire	wire_n1liO_dataout;
	wire	wire_n1ll_dataout;
	wire	wire_n1lli_dataout;
	wire	wire_n1lll_dataout;
	wire	wire_n1llO_dataout;
	wire	wire_n1lO_dataout;
	wire	wire_n1lOi_dataout;
	wire	wire_n1lOl_dataout;
	wire	wire_n1lOO_dataout;
	wire	wire_n1O0i_dataout;
	wire	wire_n1O0l_dataout;
	wire	wire_n1O0O_dataout;
	wire	wire_n1O1i_dataout;
	wire	wire_n1O1l_dataout;
	wire	wire_n1O1O_dataout;
	wire	wire_n1Oi_dataout;
	wire	wire_n1Oii_dataout;
	wire	wire_n1Oil_dataout;
	wire	wire_n1OiO_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1Oli_dataout;
	wire	wire_n1Oll_dataout;
	wire	wire_n1OlO_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_n1OOi_dataout;
	wire	wire_n1OOl_dataout;
	wire	wire_n1OOO_dataout;
	wire	wire_ni_dataout;
	wire	wire_ni00O_dataout;
	wire	wire_ni01i_dataout;
	wire	wire_ni01l_dataout;
	wire	wire_ni0ii_dataout;
	wire	wire_ni0il_dataout;
	wire	wire_ni0iO_dataout;
	wire	wire_ni0li_dataout;
	wire	wire_ni0ll_dataout;
	wire	wire_ni0lO_dataout;
	wire	wire_ni0Oi_dataout;
	wire	wire_ni0Ol_dataout;
	wire	wire_ni10i_dataout;
	wire	wire_ni10l_dataout;
	wire	wire_ni10O_dataout;
	wire	wire_ni11i_dataout;
	wire	wire_ni11l_dataout;
	wire	wire_ni11O_dataout;
	wire	wire_ni1ii_dataout;
	wire	wire_ni1il_dataout;
	wire	wire_ni1iO_dataout;
	wire	wire_ni1li_dataout;
	wire	wire_ni1ll_dataout;
	wire	wire_ni1lO_dataout;
	wire	wire_ni1Oi_dataout;
	wire	wire_ni1Ol_dataout;
	wire	wire_ni1OO_dataout;
	wire	wire_niii_dataout;
	wire	wire_niil_dataout;
	wire	wire_niili_dataout;
	wire	wire_niill_dataout;
	wire	wire_niilO_dataout;
	wire	wire_niiOi_dataout;
	wire	wire_niiOl_dataout;
	wire	wire_niiOO_dataout;
	wire	wire_nil0i_dataout;
	wire	wire_nil0l_dataout;
	wire	wire_nil0O_dataout;
	wire	wire_nil1i_dataout;
	wire	wire_nil1l_dataout;
	wire	wire_nil1O_dataout;
	wire	wire_nilii_dataout;
	wire	wire_nilil_dataout;
	wire	wire_niliO_dataout;
	wire	wire_nilli_dataout;
	wire	wire_nilll_dataout;
	wire	wire_nillO_dataout;
	wire	wire_nilOi_dataout;
	wire	wire_nilOl_dataout;
	wire	wire_nilOO_dataout;
	wire	wire_niO0i_dataout;
	wire	wire_niO0l_dataout;
	wire	wire_niO0O_dataout;
	wire	wire_niO1i_dataout;
	wire	wire_niO1l_dataout;
	wire	wire_niO1O_dataout;
	wire	wire_niOii_dataout;
	wire	wire_niOil_dataout;
	wire	wire_niOiO_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOli_dataout;
	wire	wire_niOll_dataout;
	wire	wire_niOlO_dataout;
	wire	wire_niOO_dataout;
	wire	wire_niOOi_dataout;
	wire	wire_niOOl_dataout;
	wire	wire_niOOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl0ii_dataout;
	wire	wire_nl0il_dataout;
	wire	wire_nl0iO_dataout;
	wire	wire_nl0li_dataout;
	wire	wire_nl0ll_dataout;
	wire	wire_nl0lO_dataout;
	wire	wire_nl0Oi_dataout;
	wire	wire_nl0Ol_dataout;
	wire	wire_nl0OO_dataout;
	wire	wire_nl10i_dataout;
	wire	wire_nl10l_dataout;
	wire	wire_nl10O_dataout;
	wire	wire_nl11O_dataout;
	wire	wire_nl1ii_dataout;
	wire	wire_nl1il_dataout;
	wire	wire_nl1iO_dataout;
	wire	wire_nl1li_dataout;
	wire	wire_nl1ll_dataout;
	wire	wire_nli0i_dataout;
	wire	wire_nli0l_dataout;
	wire	wire_nli0O_dataout;
	wire	wire_nli1i_dataout;
	wire	wire_nli1l_dataout;
	wire	wire_nli1O_dataout;
	wire	wire_nliii_dataout;
	wire	wire_nliil_dataout;
	wire	wire_nliiO_dataout;
	wire	wire_nlili_dataout;
	wire	wire_nlill_dataout;
	wire	wire_nlilO_dataout;
	wire	wire_nliOi_dataout;
	wire	wire_nliOl_dataout;
	wire	wire_nliOO_dataout;
	wire	wire_nll1i_dataout;
	wire	wire_nll1l_dataout;
	wire	wire_nll1O_dataout;
	wire	wire_nlll0i_dataout;
	wire	wire_nlll0l_dataout;
	wire	wire_nlll0O_dataout;
	wire	wire_nlllii_dataout;
	wire	wire_nlllil_dataout;
	wire	wire_nllliO_dataout;
	wire	wire_nlllli_dataout;
	wire	wire_nlllll_dataout;
	wire	wire_nllllO_dataout;
	wire	wire_nlllOi_dataout;
	wire	wire_nlllOl_dataout;
	wire	wire_nlllOO_dataout;
	wire	wire_nllO0i_dataout;
	wire	wire_nllO0l_dataout;
	wire	wire_nllO0O_dataout;
	wire	wire_nllO1i_dataout;
	wire	wire_nllO1l_dataout;
	wire	wire_nllO1O_dataout;
	wire	wire_nllOii_dataout;
	wire	wire_nllOil_dataout;
	wire	wire_nllOiO_dataout;
	wire	wire_nllOli_dataout;
	wire	wire_nllOll_dataout;
	wire	wire_nllOlO_dataout;
	wire	wire_nllOOi_dataout;
	wire	wire_nllOOl_dataout;
	wire	wire_nllOOO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlO00i_dataout;
	wire	wire_nlO00l_dataout;
	wire	wire_nlO00O_dataout;
	wire	wire_nlO01i_dataout;
	wire	wire_nlO01l_dataout;
	wire	wire_nlO01O_dataout;
	wire	wire_nlO0i_dataout;
	wire	wire_nlO0ii_dataout;
	wire	wire_nlO0il_dataout;
	wire	wire_nlO0iO_dataout;
	wire	wire_nlO0l_dataout;
	wire	wire_nlO0li_dataout;
	wire	wire_nlO0ll_dataout;
	wire	wire_nlO0lO_dataout;
	wire	wire_nlO0O_dataout;
	wire	wire_nlO10i_dataout;
	wire	wire_nlO10l_dataout;
	wire	wire_nlO10O_dataout;
	wire	wire_nlO11i_dataout;
	wire	wire_nlO11l_dataout;
	wire	wire_nlO11O_dataout;
	wire	wire_nlO1i_dataout;
	wire	wire_nlO1ii_dataout;
	wire	wire_nlO1il_dataout;
	wire	wire_nlO1iO_dataout;
	wire	wire_nlO1l_dataout;
	wire	wire_nlO1li_dataout;
	wire	wire_nlO1ll_dataout;
	wire	wire_nlO1lO_dataout;
	wire	wire_nlO1O_dataout;
	wire	wire_nlO1Oi_dataout;
	wire	wire_nlO1Ol_dataout;
	wire	wire_nlO1OO_dataout;
	wire	wire_nlOii_dataout;
	wire	wire_nlOiii_dataout;
	wire	wire_nlOiil_dataout;
	wire	wire_nlOiiO_dataout;
	wire	wire_nlOil_dataout;
	wire	wire_nlOili_dataout;
	wire	wire_nlOill_dataout;
	wire	wire_nlOilO_dataout;
	wire	wire_nlOiO_dataout;
	wire	wire_nlOiOi_dataout;
	wire	wire_nlOiOl_dataout;
	wire	wire_nlOiOO_dataout;
	wire	wire_nlOl0i_dataout;
	wire	wire_nlOl0l_dataout;
	wire	wire_nlOl0O_dataout;
	wire	wire_nlOl1i_dataout;
	wire	wire_nlOl1l_dataout;
	wire	wire_nlOl1O_dataout;
	wire	wire_nlOli_dataout;
	wire	wire_nlOlii_dataout;
	wire	wire_nlOlil_dataout;
	wire	wire_nlOliO_dataout;
	wire	wire_nlOll_dataout;
	wire	wire_nlOlli_dataout;
	wire	wire_nlOlll_dataout;
	wire	wire_nlOllO_dataout;
	wire	wire_nlOlO_dataout;
	wire	wire_nlOlOi_dataout;
	wire	wire_nlOlOl_dataout;
	wire	wire_nlOlOO_dataout;
	wire	wire_nlOO0i_dataout;
	wire	wire_nlOO0l_dataout;
	wire	wire_nlOO0O_dataout;
	wire	wire_nlOO1i_dataout;
	wire	wire_nlOO1l_dataout;
	wire	wire_nlOO1O_dataout;
	wire	wire_nlOOi_dataout;
	wire	wire_nlOOii_dataout;
	wire	wire_nlOOil_dataout;
	wire	wire_nlOOiO_dataout;
	wire	wire_nlOOl_dataout;
	wire	wire_nlOOli_dataout;
	wire	wire_nlOOll_dataout;
	wire	wire_nlOOlO_dataout;
	wire	wire_nlOOO_dataout;
	wire	wire_nlOOOi_dataout;
	wire	wire_nlOOOl_dataout;
	wire	wire_nlOOOO_dataout;
	wire	wire_nO_dataout;
	wire  wire_n0ii_o;
	wire  wire_n0il_o;
	wire  wire_n0iO_o;
	wire  nl000O;
	wire  nl001i;
	wire  nl001l;
	wire  nl00li;
	wire  nl00lO;
	wire  nl00OO;
	wire  nl010i;
	wire  nl011O;
	wire  nl01ii;
	wire  nl01lO;
	wire  nl01Oi;
	wire  nl0i0i;
	wire  nl0i1i;
	wire  nl0iii;
	wire  nl0iil;
	wire  nl0ill;
	wire  nl0ilO;
	wire  nl0iOi;
	wire  nl0iOl;
	wire  nl0l0i;
	wire  nl0l0l;
	wire  nl0l1l;
	wire  nl0l1O;
	wire  nl0lil;
	wire  nl0liO;
	wire  nl0llO;
	wire  nl0lOi;
	wire  nl0O0i;
	wire  nl0O1i;
	wire  nl0O1l;
	wire  nl0O1O;
	wire  nl0Oii;
	wire  nl0Oil;
	wire  nl0Oll;
	wire  nl0OlO;
	wire  nl0OOO;
	wire  nl1Oil;
	wire  nl1OiO;
	wire  nl1Oli;
	wire  nl1Oll;
	wire  nl1OlO;
	wire  nl1OOi;
	wire  nl1OOl;
	wire  nl1OOO;
	wire  nli11i;

	initial
		nl000i31 = 0;
	always @ ( posedge clk_2)
		  nl000i31 <= nl000i32;
	event nl000i31_event;
	initial
		#1 ->nl000i31_event;
	always @(nl000i31_event)
		nl000i31 <= {1{1'b1}};
	initial
		nl000i32 = 0;
	always @ ( posedge clk_2)
		  nl000i32 <= nl000i31;
	initial
		nl000l29 = 0;
	always @ ( posedge clk_2)
		  nl000l29 <= nl000l30;
	event nl000l29_event;
	initial
		#1 ->nl000l29_event;
	always @(nl000l29_event)
		nl000l29 <= {1{1'b1}};
	initial
		nl000l30 = 0;
	always @ ( posedge clk_2)
		  nl000l30 <= nl000l29;
	initial
		nl001O33 = 0;
	always @ ( posedge clk_2)
		  nl001O33 <= nl001O34;
	event nl001O33_event;
	initial
		#1 ->nl001O33_event;
	always @(nl001O33_event)
		nl001O33 <= {1{1'b1}};
	initial
		nl001O34 = 0;
	always @ ( posedge clk_2)
		  nl001O34 <= nl001O33;
	initial
		nl00ii27 = 0;
	always @ ( posedge clk_2)
		  nl00ii27 <= nl00ii28;
	event nl00ii27_event;
	initial
		#1 ->nl00ii27_event;
	always @(nl00ii27_event)
		nl00ii27 <= {1{1'b1}};
	initial
		nl00ii28 = 0;
	always @ ( posedge clk_2)
		  nl00ii28 <= nl00ii27;
	initial
		nl00iO25 = 0;
	always @ ( posedge clk_2)
		  nl00iO25 <= nl00iO26;
	event nl00iO25_event;
	initial
		#1 ->nl00iO25_event;
	always @(nl00iO25_event)
		nl00iO25 <= {1{1'b1}};
	initial
		nl00iO26 = 0;
	always @ ( posedge clk_2)
		  nl00iO26 <= nl00iO25;
	initial
		nl00ll23 = 0;
	always @ ( posedge clk_2)
		  nl00ll23 <= nl00ll24;
	event nl00ll23_event;
	initial
		#1 ->nl00ll23_event;
	always @(nl00ll23_event)
		nl00ll23 <= {1{1'b1}};
	initial
		nl00ll24 = 0;
	always @ ( posedge clk_2)
		  nl00ll24 <= nl00ll23;
	initial
		nl00Oi21 = 0;
	always @ ( posedge clk_2)
		  nl00Oi21 <= nl00Oi22;
	event nl00Oi21_event;
	initial
		#1 ->nl00Oi21_event;
	always @(nl00Oi21_event)
		nl00Oi21 <= {1{1'b1}};
	initial
		nl00Oi22 = 0;
	always @ ( posedge clk_2)
		  nl00Oi22 <= nl00Oi21;
	initial
		nl010l41 = 0;
	always @ ( posedge clk_2)
		  nl010l41 <= nl010l42;
	event nl010l41_event;
	initial
		#1 ->nl010l41_event;
	always @(nl010l41_event)
		nl010l41 <= {1{1'b1}};
	initial
		nl010l42 = 0;
	always @ ( posedge clk_2)
		  nl010l42 <= nl010l41;
	initial
		nl011i43 = 0;
	always @ ( posedge clk_2)
		  nl011i43 <= nl011i44;
	event nl011i43_event;
	initial
		#1 ->nl011i43_event;
	always @(nl011i43_event)
		nl011i43 <= {1{1'b1}};
	initial
		nl011i44 = 0;
	always @ ( posedge clk_2)
		  nl011i44 <= nl011i43;
	initial
		nl01il39 = 0;
	always @ ( posedge clk_2)
		  nl01il39 <= nl01il40;
	event nl01il39_event;
	initial
		#1 ->nl01il39_event;
	always @(nl01il39_event)
		nl01il39 <= {1{1'b1}};
	initial
		nl01il40 = 0;
	always @ ( posedge clk_2)
		  nl01il40 <= nl01il39;
	initial
		nl01li37 = 0;
	always @ ( posedge clk_2)
		  nl01li37 <= nl01li38;
	event nl01li37_event;
	initial
		#1 ->nl01li37_event;
	always @(nl01li37_event)
		nl01li37 <= {1{1'b1}};
	initial
		nl01li38 = 0;
	always @ ( posedge clk_2)
		  nl01li38 <= nl01li37;
	initial
		nl01Ol35 = 0;
	always @ ( posedge clk_2)
		  nl01Ol35 <= nl01Ol36;
	event nl01Ol35_event;
	initial
		#1 ->nl01Ol35_event;
	always @(nl01Ol35_event)
		nl01Ol35 <= {1{1'b1}};
	initial
		nl01Ol36 = 0;
	always @ ( posedge clk_2)
		  nl01Ol36 <= nl01Ol35;
	initial
		nl0i0l17 = 0;
	always @ ( posedge clk_2)
		  nl0i0l17 <= nl0i0l18;
	event nl0i0l17_event;
	initial
		#1 ->nl0i0l17_event;
	always @(nl0i0l17_event)
		nl0i0l17 <= {1{1'b1}};
	initial
		nl0i0l18 = 0;
	always @ ( posedge clk_2)
		  nl0i0l18 <= nl0i0l17;
	initial
		nl0i1l19 = 0;
	always @ ( posedge clk_2)
		  nl0i1l19 <= nl0i1l20;
	event nl0i1l19_event;
	initial
		#1 ->nl0i1l19_event;
	always @(nl0i1l19_event)
		nl0i1l19 <= {1{1'b1}};
	initial
		nl0i1l20 = 0;
	always @ ( posedge clk_2)
		  nl0i1l20 <= nl0i1l19;
	initial
		nl0iiO15 = 0;
	always @ ( posedge clk_2)
		  nl0iiO15 <= nl0iiO16;
	event nl0iiO15_event;
	initial
		#1 ->nl0iiO15_event;
	always @(nl0iiO15_event)
		nl0iiO15 <= {1{1'b1}};
	initial
		nl0iiO16 = 0;
	always @ ( posedge clk_2)
		  nl0iiO16 <= nl0iiO15;
	initial
		nl0iOO13 = 0;
	always @ ( posedge clk_2)
		  nl0iOO13 <= nl0iOO14;
	event nl0iOO13_event;
	initial
		#1 ->nl0iOO13_event;
	always @(nl0iOO13_event)
		nl0iOO13 <= {1{1'b1}};
	initial
		nl0iOO14 = 0;
	always @ ( posedge clk_2)
		  nl0iOO14 <= nl0iOO13;
	initial
		nl0l0O11 = 0;
	always @ ( posedge clk_2)
		  nl0l0O11 <= nl0l0O12;
	event nl0l0O11_event;
	initial
		#1 ->nl0l0O11_event;
	always @(nl0l0O11_event)
		nl0l0O11 <= {1{1'b1}};
	initial
		nl0l0O12 = 0;
	always @ ( posedge clk_2)
		  nl0l0O12 <= nl0l0O11;
	initial
		nl0lli10 = 0;
	always @ ( posedge clk_2)
		  nl0lli10 <= nl0lli9;
	initial
		nl0lli9 = 0;
	always @ ( posedge clk_2)
		  nl0lli9 <= nl0lli10;
	event nl0lli9_event;
	initial
		#1 ->nl0lli9_event;
	always @(nl0lli9_event)
		nl0lli9 <= {1{1'b1}};
	initial
		nl0lOl7 = 0;
	always @ ( posedge clk_2)
		  nl0lOl7 <= nl0lOl8;
	event nl0lOl7_event;
	initial
		#1 ->nl0lOl7_event;
	always @(nl0lOl7_event)
		nl0lOl7 <= {1{1'b1}};
	initial
		nl0lOl8 = 0;
	always @ ( posedge clk_2)
		  nl0lOl8 <= nl0lOl7;
	initial
		nl0O0l5 = 0;
	always @ ( posedge clk_2)
		  nl0O0l5 <= nl0O0l6;
	event nl0O0l5_event;
	initial
		#1 ->nl0O0l5_event;
	always @(nl0O0l5_event)
		nl0O0l5 <= {1{1'b1}};
	initial
		nl0O0l6 = 0;
	always @ ( posedge clk_2)
		  nl0O0l6 <= nl0O0l5;
	initial
		nl0OiO3 = 0;
	always @ ( posedge clk_2)
		  nl0OiO3 <= nl0OiO4;
	event nl0OiO3_event;
	initial
		#1 ->nl0OiO3_event;
	always @(nl0OiO3_event)
		nl0OiO3 <= {1{1'b1}};
	initial
		nl0OiO4 = 0;
	always @ ( posedge clk_2)
		  nl0OiO4 <= nl0OiO3;
	initial
		nl0OOi1 = 0;
	always @ ( posedge clk_2)
		  nl0OOi1 <= nl0OOi2;
	event nl0OOi1_event;
	initial
		#1 ->nl0OOi1_event;
	always @(nl0OOi1_event)
		nl0OOi1 <= {1{1'b1}};
	initial
		nl0OOi2 = 0;
	always @ ( posedge clk_2)
		  nl0OOi2 <= nl0OOi1;
	initial
	begin
		n001i = 0;
		n01il = 0;
		n01lO = 0;
		n01Oi = 0;
		n0l0i = 0;
		n0l0l = 0;
		n0l0O = 0;
		n0l1O = 0;
		n0lii = 0;
		n0lil = 0;
		n0liO = 0;
		n0lli = 0;
		n0lll = 0;
		n0Oi = 0;
		n0Ol = 0;
		n0OO = 0;
		n100i = 0;
		n100l = 0;
		n100O = 0;
		n101i = 0;
		n101l = 0;
		n101O = 0;
		n10ii = 0;
		n10il = 0;
		n10iO = 0;
		n10li = 0;
		ni0i = 0;
		ni0l = 0;
		ni0O = 0;
		ni1i = 0;
		ni1l = 0;
		ni1O = 0;
		nii0i = 0;
		nii0l = 0;
		nii0O = 0;
		nii1i = 0;
		nii1l = 0;
		nii1O = 0;
		niiii = 0;
		niiil = 0;
		nill = 0;
		nl00i = 0;
		nl00l = 0;
		nl01i = 0;
		nl01l = 0;
		nl01O = 0;
		nl1Oi = 0;
		nl1Ol = 0;
		nl1OO = 0;
		nllii = 0;
		nlliii = 0;
		nlliil = 0;
		nlliiO = 0;
		nllil = 0;
		nllili = 0;
		nllill = 0;
		nllilO = 0;
		nlliOi = 0;
		nlliOl = 0;
		nlliOO = 0;
		nlll1i = 0;
		nlll1l = 0;
		nlll1O = 0;
		nlllO = 0;
		nllOi = 0;
		nllOO = 0;
		nlO0Oi = 0;
		nlO0Ol = 0;
		nlO0OO = 0;
		nlOi0i = 0;
		nlOi0l = 0;
		nlOi1i = 0;
		nlOi1l = 0;
		nlOi1O = 0;
	end
	always @ (clk_2 or wire_nili_PRN or soft_reset)
	begin
		if (wire_nili_PRN == 1'b0) 
		begin
			n001i <= 1;
			n01il <= 1;
			n01lO <= 1;
			n01Oi <= 1;
			n0l0i <= 1;
			n0l0l <= 1;
			n0l0O <= 1;
			n0l1O <= 1;
			n0lii <= 1;
			n0lil <= 1;
			n0liO <= 1;
			n0lli <= 1;
			n0lll <= 1;
			n0Oi <= 1;
			n0Ol <= 1;
			n0OO <= 1;
			n100i <= 1;
			n100l <= 1;
			n100O <= 1;
			n101i <= 1;
			n101l <= 1;
			n101O <= 1;
			n10ii <= 1;
			n10il <= 1;
			n10iO <= 1;
			n10li <= 1;
			ni0i <= 1;
			ni0l <= 1;
			ni0O <= 1;
			ni1i <= 1;
			ni1l <= 1;
			ni1O <= 1;
			nii0i <= 1;
			nii0l <= 1;
			nii0O <= 1;
			nii1i <= 1;
			nii1l <= 1;
			nii1O <= 1;
			niiii <= 1;
			niiil <= 1;
			nill <= 1;
			nl00i <= 1;
			nl00l <= 1;
			nl01i <= 1;
			nl01l <= 1;
			nl01O <= 1;
			nl1Oi <= 1;
			nl1Ol <= 1;
			nl1OO <= 1;
			nllii <= 1;
			nlliii <= 1;
			nlliil <= 1;
			nlliiO <= 1;
			nllil <= 1;
			nllili <= 1;
			nllill <= 1;
			nllilO <= 1;
			nlliOi <= 1;
			nlliOl <= 1;
			nlliOO <= 1;
			nlll1i <= 1;
			nlll1l <= 1;
			nlll1O <= 1;
			nlllO <= 1;
			nllOi <= 1;
			nllOO <= 1;
			nlO0Oi <= 1;
			nlO0Ol <= 1;
			nlO0OO <= 1;
			nlOi0i <= 1;
			nlOi0l <= 1;
			nlOi1i <= 1;
			nlOi1l <= 1;
			nlOi1O <= 1;
		end
		else if  (soft_reset == 1'b1) 
		begin
			n001i <= 0;
			n01il <= 0;
			n01lO <= 0;
			n01Oi <= 0;
			n0l0i <= 0;
			n0l0l <= 0;
			n0l0O <= 0;
			n0l1O <= 0;
			n0lii <= 0;
			n0lil <= 0;
			n0liO <= 0;
			n0lli <= 0;
			n0lll <= 0;
			n0Oi <= 0;
			n0Ol <= 0;
			n0OO <= 0;
			n100i <= 0;
			n100l <= 0;
			n100O <= 0;
			n101i <= 0;
			n101l <= 0;
			n101O <= 0;
			n10ii <= 0;
			n10il <= 0;
			n10iO <= 0;
			n10li <= 0;
			ni0i <= 0;
			ni0l <= 0;
			ni0O <= 0;
			ni1i <= 0;
			ni1l <= 0;
			ni1O <= 0;
			nii0i <= 0;
			nii0l <= 0;
			nii0O <= 0;
			nii1i <= 0;
			nii1l <= 0;
			nii1O <= 0;
			niiii <= 0;
			niiil <= 0;
			nill <= 0;
			nl00i <= 0;
			nl00l <= 0;
			nl01i <= 0;
			nl01l <= 0;
			nl01O <= 0;
			nl1Oi <= 0;
			nl1Ol <= 0;
			nl1OO <= 0;
			nllii <= 0;
			nlliii <= 0;
			nlliil <= 0;
			nlliiO <= 0;
			nllil <= 0;
			nllili <= 0;
			nllill <= 0;
			nllilO <= 0;
			nlliOi <= 0;
			nlliOl <= 0;
			nlliOO <= 0;
			nlll1i <= 0;
			nlll1l <= 0;
			nlll1O <= 0;
			nlllO <= 0;
			nllOi <= 0;
			nllOO <= 0;
			nlO0Oi <= 0;
			nlO0Ol <= 0;
			nlO0OO <= 0;
			nlOi0i <= 0;
			nlOi0l <= 0;
			nlOi1i <= 0;
			nlOi1l <= 0;
			nlOi1O <= 0;
		end
		else 
		if (clk_2 != nili_clk_prev && clk_2 == 1'b1) 
		begin
			n001i <= wire_n0llO_dataout;
			n01il <= wire_n001O_dataout;
			n01lO <= wire_n00ii_dataout;
			n01Oi <= wire_n00il_dataout;
			n0l0i <= wire_n0lOl_dataout;
			n0l0l <= wire_n0lOO_dataout;
			n0l0O <= wire_n0O1i_dataout;
			n0l1O <= wire_n0lOi_dataout;
			n0lii <= wire_n0O1l_dataout;
			n0lil <= wire_n0O1O_dataout;
			n0liO <= wire_n0O0i_dataout;
			n0lli <= wire_n0O0l_dataout;
			n0lll <= wire_niili_dataout;
			n0Oi <= indv;
			n0Ol <= (~ wire_n0iO_o);
			n0OO <= wire_n0ii_o;
			n100i <= wire_n10Ol_dataout;
			n100l <= wire_n10OO_dataout;
			n100O <= wire_n1i1i_dataout;
			n101i <= nl0O0i;
			n101l <= wire_n10lO_dataout;
			n101O <= wire_n10Oi_dataout;
			n10ii <= wire_n1i1l_dataout;
			n10il <= wire_n1i1O_dataout;
			n10iO <= wire_n1i0i_dataout;
			n10li <= wire_n001l_dataout;
			ni0i <= xs_link_status_set;
			ni0l <= wire_niii_dataout;
			ni0O <= nill;
			ni1i <= ni1l;
			ni1l <= tx_local_fault_det;
			ni1O <= ni0i;
			nii0i <= wire_niiOl_dataout;
			nii0l <= wire_niiOO_dataout;
			nii0O <= wire_nil1i_dataout;
			nii1i <= wire_niill_dataout;
			nii1l <= wire_niilO_dataout;
			nii1O <= wire_niiOi_dataout;
			niiii <= wire_nil1l_dataout;
			niiil <= wire_nil1O_dataout;
			nill <= rx_local_fault_clr;
			nl00i <= wire_nl0Ol_dataout;
			nl00l <= wire_nl0OO_dataout;
			nl01i <= wire_nl0ll_dataout;
			nl01l <= wire_nl0lO_dataout;
			nl01O <= wire_nl0Oi_dataout;
			nl1Oi <= wire_nl0il_dataout;
			nl1Ol <= wire_nl0iO_dataout;
			nl1OO <= wire_nl0li_dataout;
			nllii <= wire_nlO1l_dataout;
			nlliii <= nl0Oil;
			nlliil <= ((~ wire_nO_dataout) & (dec_ctl[3] & nl1Oil));
			nlliiO <= wire_nlll0i_dataout;
			nllil <= wire_nlO1O_dataout;
			nllili <= wire_nlll0l_dataout;
			nllill <= wire_nlll0O_dataout;
			nllilO <= wire_nlllii_dataout;
			nlliOi <= wire_nlllil_dataout;
			nlliOl <= wire_nllliO_dataout;
			nlliOO <= wire_nlllli_dataout;
			nlll1i <= wire_nlllll_dataout;
			nlll1l <= wire_nllllO_dataout;
			nlll1O <= wire_nlOiii_dataout;
			nlllO <= wire_nlOii_dataout;
			nllOi <= wire_nlOil_dataout;
			nllOO <= n0Oi;
			nlO0Oi <= wire_nlOiil_dataout;
			nlO0Ol <= wire_nlOiiO_dataout;
			nlO0OO <= wire_nlOili_dataout;
			nlOi0i <= wire_nlOiOl_dataout;
			nlOi0l <= wire_nlOiOO_dataout;
			nlOi1i <= wire_nlOill_dataout;
			nlOi1l <= wire_nlOilO_dataout;
			nlOi1O <= wire_nlOiOi_dataout;
		end
		nili_clk_prev <= clk_2;
	end
	assign
		wire_nili_PRN = (nl00iO26 ^ nl00iO25);
	initial
	begin
		n01iO = 0;
		n01li = 0;
		n01ll = 0;
		n01Ol = 0;
		n01OO = 0;
		niiiO = 0;
		niOi = 0;
		nl00O = 0;
		nlliO = 0;
		nllli = 0;
		nllll = 0;
		nllOl = 0;
		nlOi0O = 0;
	end
	always @ (clk_2 or soft_reset or wire_nilO_CLRN)
	begin
		if (soft_reset == 1'b1) 
		begin
			n01iO <= 1;
			n01li <= 1;
			n01ll <= 1;
			n01Ol <= 1;
			n01OO <= 1;
			niiiO <= 1;
			niOi <= 1;
			nl00O <= 1;
			nlliO <= 1;
			nllli <= 1;
			nllll <= 1;
			nllOl <= 1;
			nlOi0O <= 1;
		end
		else if  (wire_nilO_CLRN == 1'b0) 
		begin
			n01iO <= 0;
			n01li <= 0;
			n01ll <= 0;
			n01Ol <= 0;
			n01OO <= 0;
			niiiO <= 0;
			niOi <= 0;
			nl00O <= 0;
			nlliO <= 0;
			nllli <= 0;
			nllll <= 0;
			nllOl <= 0;
			nlOi0O <= 0;
		end
		else 
		if (clk_2 != nilO_clk_prev && clk_2 == 1'b1) 
		begin
			n01iO <= wire_n000i_dataout;
			n01li <= wire_n000l_dataout;
			n01ll <= wire_n000O_dataout;
			n01Ol <= wire_n00iO_dataout;
			n01OO <= wire_n00li_dataout;
			niiiO <= wire_nl0ii_dataout;
			niOi <= wire_niOl_dataout;
			nl00O <= wire_nlO1i_dataout;
			nlliO <= wire_nlO0i_dataout;
			nllli <= wire_nlO0l_dataout;
			nllll <= wire_nlO0O_dataout;
			nllOl <= wire_nlOiO_dataout;
			nlOi0O <= wire_n10ll_dataout;
		end
		nilO_clk_prev <= clk_2;
	end
	assign
		wire_nilO_CLRN = (nl00ll24 ^ nl00ll23);
	or(wire_n000i_dataout, wire_n00Oi_dataout, nli11i);
	or(wire_n000l_dataout, wire_n00Ol_dataout, nli11i);
	or(wire_n000O_dataout, wire_n00OO_dataout, nli11i);
	and(wire_n001l_dataout, wire_n00ll_dataout, ~(nli11i));
	and(wire_n001O_dataout, wire_n00lO_dataout, ~(nli11i));
	or(wire_n00i_dataout, dec_data[6], wire_nlO_dataout);
	and(wire_n00ii_dataout, wire_n0i1i_dataout, ~(nli11i));
	and(wire_n00il_dataout, wire_n0i1l_dataout, ~(nli11i));
	or(wire_n00iO_dataout, wire_n0i1O_dataout, nli11i);
	or(wire_n00l_dataout, dec_data[7], wire_nlO_dataout);
	or(wire_n00li_dataout, wire_n0i0i_dataout, nli11i);
	assign		wire_n00ll_dataout = (nl1OOl === 1'b1) ? wire_n0i0l_dataout : nllii;
	assign		wire_n00lO_dataout = (nl1OOl === 1'b1) ? wire_n0i0O_dataout : nllil;
	or(wire_n00O_dataout, dec_ctl[0], wire_nlO_dataout);
	assign		wire_n00Oi_dataout = (nl1OOl === 1'b1) ? wire_n0iii_dataout : nlliO;
	assign		wire_n00Ol_dataout = (nl1OOl === 1'b1) ? wire_n0iil_dataout : nllli;
	assign		wire_n00OO_dataout = (nl1OOl === 1'b1) ? wire_n0iiO_dataout : nllll;
	or(wire_n010i_dataout, wire_n1O1i_dataout, nl1Oli);
	and(wire_n011i_dataout, wire_n1lOi_dataout, ~(nl1Oli));
	and(wire_n011l_dataout, wire_n1lOl_dataout, ~(nl1Oli));
	and(wire_n011O_dataout, wire_n1lOO_dataout, ~(nl1Oli));
	or(wire_n01i_dataout, dec_data[3], wire_nlO_dataout);
	or(wire_n01l_dataout, dec_data[4], wire_nlO_dataout);
	or(wire_n01O_dataout, dec_data[5], wire_nlO_dataout);
	assign		wire_n0i0i_dataout = (nl1OOl === 1'b1) ? wire_n0iOi_dataout : nl00O;
	and(wire_n0i0l_dataout, nllii, ~(nl1OOi));
	or(wire_n0i0O_dataout, nllil, nl1OOi);
	assign		wire_n0i1i_dataout = (nl1OOl === 1'b1) ? wire_n0ili_dataout : nlllO;
	assign		wire_n0i1l_dataout = (nl1OOl === 1'b1) ? wire_n0ill_dataout : nllOi;
	assign		wire_n0i1O_dataout = (nl1OOl === 1'b1) ? wire_n0ilO_dataout : nllOl;
	or(wire_n0iii_dataout, nlliO, nl1OOi);
	or(wire_n0iil_dataout, nllli, nl1OOi);
	or(wire_n0iiO_dataout, nllll, nl1OOi);
	or(wire_n0ili_dataout, nlllO, nl1OOi);
	or(wire_n0ill_dataout, nllOi, nl1OOi);
	or(wire_n0ilO_dataout, nllOl, nl1OOi);
	or(wire_n0iOi_dataout, nl00O, nl1OOi);
	and(wire_n0li_dataout, (~ nl00OO), ~(nl000O));
	and(wire_n0ll_dataout, nl00OO, ~(nl000O));
	and(wire_n0llO_dataout, wire_n0O0O_dataout, ~(nli11i));
	and(wire_n0lOi_dataout, wire_n0Oii_dataout, ~(nli11i));
	and(wire_n0lOl_dataout, wire_n0Oil_dataout, ~(nli11i));
	and(wire_n0lOO_dataout, wire_n0OiO_dataout, ~(nli11i));
	and(wire_n0O0i_dataout, wire_n0OOi_dataout, ~(nli11i));
	and(wire_n0O0l_dataout, wire_n0OOl_dataout, ~(nli11i));
	assign		wire_n0O0O_dataout = (nl0OlO === 1'b1) ? wire_ni00O_dataout : wire_n0OOO_dataout;
	and(wire_n0O1i_dataout, wire_n0Oli_dataout, ~(nli11i));
	and(wire_n0O1l_dataout, wire_n0Oll_dataout, ~(nli11i));
	and(wire_n0O1O_dataout, wire_n0OlO_dataout, ~(nli11i));
	assign		wire_n0Oii_dataout = (nl0OlO === 1'b1) ? wire_ni0ii_dataout : wire_ni11i_dataout;
	assign		wire_n0Oil_dataout = (nl0OlO === 1'b1) ? wire_ni0il_dataout : wire_ni11l_dataout;
	assign		wire_n0OiO_dataout = (nl0OlO === 1'b1) ? wire_ni0iO_dataout : wire_ni11O_dataout;
	assign		wire_n0Oli_dataout = (nl0OlO === 1'b1) ? wire_ni0li_dataout : wire_ni10i_dataout;
	assign		wire_n0Oll_dataout = (nl0OlO === 1'b1) ? wire_ni0ll_dataout : wire_ni10l_dataout;
	assign		wire_n0OlO_dataout = (nl0OlO === 1'b1) ? wire_ni0lO_dataout : wire_ni10O_dataout;
	assign		wire_n0OOi_dataout = (nl0OlO === 1'b1) ? wire_ni0Oi_dataout : wire_ni1ii_dataout;
	assign		wire_n0OOl_dataout = (nl0OlO === 1'b1) ? wire_ni0Ol_dataout : wire_ni1il_dataout;
	assign		wire_n0OOO_dataout = (nl011O === 1'b1) ? wire_ni1iO_dataout : nlliiO;
	assign		wire_n10i_dataout = (nl0OlO === 1'b1) ? dec_ctl[0] : wire_n00O_dataout;
	assign		wire_n10l_dataout = (nl0OlO === 1'b1) ? dec_data[0] : wire_n1Oi_dataout;
	assign		wire_n10ll_dataout = (nl1OiO === 1'b1) ? wire_n1O1l_dataout : wire_n1i0l_dataout;
	assign		wire_n10lO_dataout = (nl1OiO === 1'b1) ? wire_n1O1O_dataout : wire_n1i0O_dataout;
	assign		wire_n10O_dataout = (nl0OlO === 1'b1) ? dec_data[1] : wire_n1Ol_dataout;
	assign		wire_n10Oi_dataout = (nl1OiO === 1'b1) ? wire_n1O0i_dataout : wire_n1iii_dataout;
	assign		wire_n10Ol_dataout = (nl1OiO === 1'b1) ? wire_n1O0l_dataout : wire_n1iil_dataout;
	assign		wire_n10OO_dataout = (nl1OiO === 1'b1) ? wire_n1O0O_dataout : wire_n1iiO_dataout;
	and(wire_n110i_dataout, wire_n11Oi_dataout, ~((~ nl00lO)));
	and(wire_n110l_dataout, wire_n11Ol_dataout, ~((~ nl00lO)));
	and(wire_n110O_dataout, wire_n11OO_dataout, ~((~ nl00lO)));
	and(wire_n111i_dataout, wire_n11li_dataout, ~((~ nl00lO)));
	and(wire_n111l_dataout, wire_n11ll_dataout, ~((~ nl00lO)));
	and(wire_n111O_dataout, wire_n11lO_dataout, ~((~ nl00lO)));
	and(wire_n11i_dataout, wire_n1li_dataout, ~(wire_n0il_o));
	or(wire_n11ii_dataout, wire_nlOO0i_dataout, nl1Oll);
	or(wire_n11il_dataout, wire_nlOO0l_dataout, nl1Oll);
	or(wire_n11iO_dataout, wire_nlOO0O_dataout, nl1Oll);
	and(wire_n11l_dataout, wire_n1ll_dataout, ~(wire_n0il_o));
	and(wire_n11li_dataout, wire_nlOOii_dataout, ~(nl1Oll));
	and(wire_n11ll_dataout, wire_nlOOil_dataout, ~(nl1Oll));
	and(wire_n11lO_dataout, wire_nlOOiO_dataout, ~(nl1Oll));
	and(wire_n11O_dataout, wire_n1lO_dataout, ~(wire_n0il_o));
	and(wire_n11Oi_dataout, wire_nlOOli_dataout, ~(nl1Oll));
	and(wire_n11Ol_dataout, wire_nlOOll_dataout, ~(nl1Oll));
	or(wire_n11OO_dataout, wire_nlOOlO_dataout, nl1Oll);
	assign		wire_n1i0i_dataout = (nl1OiO === 1'b1) ? wire_n1Oli_dataout : wire_n1iOi_dataout;
	or(wire_n1i0l_dataout, wire_n1iOl_dataout, (~ nl00lO));
	and(wire_n1i0O_dataout, wire_n1iOO_dataout, ~((~ nl00lO)));
	assign		wire_n1i1i_dataout = (nl1OiO === 1'b1) ? wire_n1Oii_dataout : wire_n1ili_dataout;
	assign		wire_n1i1l_dataout = (nl1OiO === 1'b1) ? wire_n1Oil_dataout : wire_n1ill_dataout;
	assign		wire_n1i1O_dataout = (nl1OiO === 1'b1) ? wire_n1OiO_dataout : wire_n1ilO_dataout;
	assign		wire_n1ii_dataout = (nl0OlO === 1'b1) ? dec_data[2] : wire_n1OO_dataout;
	and(wire_n1iii_dataout, wire_n1l1i_dataout, ~((~ nl00lO)));
	and(wire_n1iil_dataout, wire_n1l1l_dataout, ~((~ nl00lO)));
	and(wire_n1iiO_dataout, wire_n1l1O_dataout, ~((~ nl00lO)));
	assign		wire_n1il_dataout = (nl0OlO === 1'b1) ? dec_data[3] : wire_n01i_dataout;
	and(wire_n1ili_dataout, wire_n1l0i_dataout, ~((~ nl00lO)));
	and(wire_n1ill_dataout, wire_n1l0l_dataout, ~((~ nl00lO)));
	and(wire_n1ilO_dataout, wire_n1l0O_dataout, ~((~ nl00lO)));
	assign		wire_n1iO_dataout = (nl0OlO === 1'b1) ? dec_data[4] : wire_n01l_dataout;
	and(wire_n1iOi_dataout, wire_n1lii_dataout, ~((~ nl00lO)));
	or(wire_n1iOl_dataout, wire_n1lil_dataout, nl00OO);
	or(wire_n1iOO_dataout, wire_n1liO_dataout, nl00OO);
	and(wire_n1l0i_dataout, wire_n1lOi_dataout, ~(nl00OO));
	and(wire_n1l0l_dataout, wire_n1lOl_dataout, ~(nl00OO));
	and(wire_n1l0O_dataout, wire_n1lOO_dataout, ~(nl00OO));
	or(wire_n1l1i_dataout, wire_n1lli_dataout, nl00OO);
	and(wire_n1l1l_dataout, wire_n1lll_dataout, ~(nl00OO));
	and(wire_n1l1O_dataout, wire_n1llO_dataout, ~(nl00OO));
	assign		wire_n1li_dataout = (nl0OlO === 1'b1) ? dec_data[5] : wire_n01O_dataout;
	or(wire_n1lii_dataout, wire_n1O1i_dataout, nl00OO);
	and(wire_n1lil_dataout, dec_data[24], ~(wire_nO_dataout));
	or(wire_n1liO_dataout, dec_data[25], wire_nO_dataout);
	assign		wire_n1ll_dataout = (nl0OlO === 1'b1) ? dec_data[6] : wire_n00i_dataout;
	or(wire_n1lli_dataout, dec_data[26], wire_nO_dataout);
	or(wire_n1lll_dataout, dec_data[27], wire_nO_dataout);
	or(wire_n1llO_dataout, dec_data[28], wire_nO_dataout);
	assign		wire_n1lO_dataout = (nl0OlO === 1'b1) ? dec_data[7] : wire_n00l_dataout;
	or(wire_n1lOi_dataout, dec_data[29], wire_nO_dataout);
	or(wire_n1lOl_dataout, dec_data[30], wire_nO_dataout);
	or(wire_n1lOO_dataout, dec_data[31], wire_nO_dataout);
	and(wire_n1O0i_dataout, wire_n1OOi_dataout, ~((~ nl00lO)));
	and(wire_n1O0l_dataout, wire_n1OOl_dataout, ~((~ nl00lO)));
	and(wire_n1O0O_dataout, wire_n1OOO_dataout, ~((~ nl00lO)));
	or(wire_n1O1i_dataout, dec_ctl[3], wire_nO_dataout);
	or(wire_n1O1l_dataout, wire_n1Oll_dataout, (~ nl00lO));
	and(wire_n1O1O_dataout, wire_n1OlO_dataout, ~((~ nl00lO)));
	and(wire_n1Oi_dataout, dec_data[0], ~(wire_nlO_dataout));
	and(wire_n1Oii_dataout, wire_n011i_dataout, ~((~ nl00lO)));
	and(wire_n1Oil_dataout, wire_n011l_dataout, ~((~ nl00lO)));
	and(wire_n1OiO_dataout, wire_n011O_dataout, ~((~ nl00lO)));
	or(wire_n1Ol_dataout, dec_data[1], wire_nlO_dataout);
	and(wire_n1Oli_dataout, wire_n010i_dataout, ~((~ nl00lO)));
	or(wire_n1Oll_dataout, wire_n1lil_dataout, nl1Oli);
	or(wire_n1OlO_dataout, wire_n1liO_dataout, nl1Oli);
	or(wire_n1OO_dataout, dec_data[2], wire_nlO_dataout);
	or(wire_n1OOi_dataout, wire_n1lli_dataout, nl1Oli);
	and(wire_n1OOl_dataout, wire_n1lll_dataout, ~(nl1Oli));
	and(wire_n1OOO_dataout, wire_n1llO_dataout, ~(nl1Oli));
	and(wire_ni_dataout, running_disp[1], ~(nli11i));
	and(wire_ni00O_dataout, nlliiO, ~(nl010i));
	or(wire_ni01i_dataout, nlll1i, nl1OOO);
	or(wire_ni01l_dataout, nlll1l, nl1OOO);
	or(wire_ni0ii_dataout, nllili, nl010i);
	or(wire_ni0il_dataout, nllill, nl010i);
	or(wire_ni0iO_dataout, nllilO, nl010i);
	or(wire_ni0li_dataout, nlliOi, nl010i);
	or(wire_ni0ll_dataout, nlliOl, nl010i);
	or(wire_ni0lO_dataout, nlliOO, nl010i);
	or(wire_ni0Oi_dataout, nlll1i, nl010i);
	or(wire_ni0Ol_dataout, nlll1l, nl010i);
	assign		wire_ni10i_dataout = (nl011O === 1'b1) ? wire_ni1Oi_dataout : nlliOi;
	assign		wire_ni10l_dataout = (nl011O === 1'b1) ? wire_ni1Ol_dataout : nlliOl;
	assign		wire_ni10O_dataout = (nl011O === 1'b1) ? wire_ni1OO_dataout : nlliOO;
	assign		wire_ni11i_dataout = (nl011O === 1'b1) ? wire_ni1li_dataout : nllili;
	assign		wire_ni11l_dataout = (nl011O === 1'b1) ? wire_ni1ll_dataout : nllill;
	assign		wire_ni11O_dataout = (nl011O === 1'b1) ? wire_ni1lO_dataout : nllilO;
	assign		wire_ni1ii_dataout = (nl011O === 1'b1) ? wire_ni01i_dataout : nlll1i;
	assign		wire_ni1il_dataout = (nl011O === 1'b1) ? wire_ni01l_dataout : nlll1l;
	and(wire_ni1iO_dataout, nlliiO, ~(nl1OOO));
	or(wire_ni1li_dataout, nllili, nl1OOO);
	or(wire_ni1ll_dataout, nllill, nl1OOO);
	or(wire_ni1lO_dataout, nllilO, nl1OOO);
	or(wire_ni1Oi_dataout, nlliOi, nl1OOO);
	or(wire_ni1Ol_dataout, nlliOl, nl1OOO);
	or(wire_ni1OO_dataout, nlliOO, nl1OOO);
	or(wire_niii_dataout, wire_niil_dataout, ni1O);
	and(wire_niil_dataout, ni0l, ~(((~ nl00lO) | ni1i)));
	and(wire_niili_dataout, wire_nil0i_dataout, ~(nli11i));
	and(wire_niill_dataout, wire_nil0l_dataout, ~(nli11i));
	and(wire_niilO_dataout, wire_nil0O_dataout, ~(nli11i));
	and(wire_niiOi_dataout, wire_nilii_dataout, ~(nli11i));
	and(wire_niiOl_dataout, wire_nilil_dataout, ~(nli11i));
	and(wire_niiOO_dataout, wire_niliO_dataout, ~(nli11i));
	assign		wire_nil0i_dataout = (nl001l === 1'b1) ? wire_nl11O_dataout : wire_nilOi_dataout;
	assign		wire_nil0l_dataout = (nl001l === 1'b1) ? wire_nl10i_dataout : wire_nilOl_dataout;
	assign		wire_nil0O_dataout = (nl001l === 1'b1) ? wire_nl10l_dataout : wire_nilOO_dataout;
	and(wire_nil1i_dataout, wire_nilli_dataout, ~(nli11i));
	and(wire_nil1l_dataout, wire_nilll_dataout, ~(nli11i));
	and(wire_nil1O_dataout, wire_nillO_dataout, ~(nli11i));
	assign		wire_nilii_dataout = (nl001l === 1'b1) ? wire_nl10O_dataout : wire_niO1i_dataout;
	assign		wire_nilil_dataout = (nl001l === 1'b1) ? wire_nl1ii_dataout : wire_niO1l_dataout;
	assign		wire_niliO_dataout = (nl001l === 1'b1) ? wire_nl1il_dataout : wire_niO1O_dataout;
	assign		wire_nilli_dataout = (nl001l === 1'b1) ? wire_nl1iO_dataout : wire_niO0i_dataout;
	assign		wire_nilll_dataout = (nl001l === 1'b1) ? wire_nl1li_dataout : wire_niO0l_dataout;
	assign		wire_nillO_dataout = (nl001l === 1'b1) ? wire_nl1ll_dataout : wire_niO0O_dataout;
	assign		wire_nilOi_dataout = (nlliil === 1'b1) ? wire_niOii_dataout : nlll1O;
	assign		wire_nilOl_dataout = (nlliil === 1'b1) ? wire_niOil_dataout : nlO0Oi;
	assign		wire_nilOO_dataout = (nlliil === 1'b1) ? wire_niOiO_dataout : nlO0Ol;
	assign		wire_niO0i_dataout = (nlliil === 1'b1) ? wire_niOOi_dataout : nlOi1O;
	assign		wire_niO0l_dataout = (nlliil === 1'b1) ? wire_niOOl_dataout : nlOi0i;
	assign		wire_niO0O_dataout = (nlliil === 1'b1) ? wire_niOOO_dataout : nlOi0l;
	assign		wire_niO1i_dataout = (nlliil === 1'b1) ? wire_niOli_dataout : nlO0OO;
	assign		wire_niO1l_dataout = (nlliil === 1'b1) ? wire_niOll_dataout : nlOi1i;
	assign		wire_niO1O_dataout = (nlliil === 1'b1) ? wire_niOlO_dataout : nlOi1l;
	and(wire_niOii_dataout, nlll1O, ~(nl01ii));
	or(wire_niOil_dataout, nlO0Oi, nl01ii);
	or(wire_niOiO_dataout, nlO0Ol, nl01ii);
	and(wire_niOl_dataout, wire_niOO_dataout, ~(ni0O));
	or(wire_niOli_dataout, nlO0OO, nl01ii);
	or(wire_niOll_dataout, nlOi1i, nl01ii);
	or(wire_niOlO_dataout, nlOi1l, nl01ii);
	or(wire_niOO_dataout, niOi, ~(nl00lO));
	or(wire_niOOi_dataout, nlOi1O, nl01ii);
	or(wire_niOOl_dataout, nlOi0i, nl01ii);
	or(wire_niOOO_dataout, nlOi0l, nl01ii);
	and(wire_nl_dataout, running_disp[2], ~(nli11i));
	or(wire_nl0ii_dataout, wire_nli1i_dataout, nli11i);
	and(wire_nl0il_dataout, wire_nli1l_dataout, ~(nli11i));
	and(wire_nl0iO_dataout, wire_nli1O_dataout, ~(nli11i));
	and(wire_nl0li_dataout, wire_nli0i_dataout, ~(nli11i));
	and(wire_nl0ll_dataout, wire_nli0l_dataout, ~(nli11i));
	and(wire_nl0lO_dataout, wire_nli0O_dataout, ~(nli11i));
	and(wire_nl0Oi_dataout, wire_nliii_dataout, ~(nli11i));
	and(wire_nl0Ol_dataout, wire_nliil_dataout, ~(nli11i));
	and(wire_nl0OO_dataout, wire_nliiO_dataout, ~(nli11i));
	or(wire_nl10i_dataout, nlO0Oi, nl01lO);
	or(wire_nl10l_dataout, nlO0Ol, nl01lO);
	or(wire_nl10O_dataout, nlO0OO, nl01lO);
	and(wire_nl11O_dataout, nlll1O, ~(nl01lO));
	or(wire_nl1ii_dataout, nlOi1i, nl01lO);
	or(wire_nl1il_dataout, nlOi1l, nl01lO);
	or(wire_nl1iO_dataout, nlOi1O, nl01lO);
	or(wire_nl1li_dataout, nlOi0i, nl01lO);
	or(wire_nl1ll_dataout, nlOi0l, nl01lO);
	assign		wire_nli0i_dataout = (nl001i === 1'b1) ? wire_nliOi_dataout : n100i;
	assign		wire_nli0l_dataout = (nl001i === 1'b1) ? wire_nliOl_dataout : n100l;
	assign		wire_nli0O_dataout = (nl001i === 1'b1) ? wire_nliOO_dataout : n100O;
	assign		wire_nli1i_dataout = (nl001i === 1'b1) ? wire_nlili_dataout : nlOi0O;
	assign		wire_nli1l_dataout = (nl001i === 1'b1) ? wire_nlill_dataout : n101l;
	assign		wire_nli1O_dataout = (nl001i === 1'b1) ? wire_nlilO_dataout : n101O;
	assign		wire_nliii_dataout = (nl001i === 1'b1) ? wire_nll1i_dataout : n10ii;
	assign		wire_nliil_dataout = (nl001i === 1'b1) ? wire_nll1l_dataout : n10il;
	assign		wire_nliiO_dataout = (nl001i === 1'b1) ? wire_nll1O_dataout : n10iO;
	and(wire_nlili_dataout, nlOi0O, ~(nl01Oi));
	or(wire_nlill_dataout, n101l, nl01Oi);
	or(wire_nlilO_dataout, n101O, nl01Oi);
	or(wire_nliOi_dataout, n100i, nl01Oi);
	or(wire_nliOl_dataout, n100l, nl01Oi);
	or(wire_nliOO_dataout, n100O, nl01Oi);
	or(wire_nll1i_dataout, n10ii, nl01Oi);
	or(wire_nll1l_dataout, n10il, nl01Oi);
	or(wire_nll1O_dataout, n10iO, nl01Oi);
	assign		wire_nlll0i_dataout = (nl1OiO === 1'b1) ? wire_nlO1li_dataout : wire_nlllOi_dataout;
	assign		wire_nlll0l_dataout = (nl1OiO === 1'b1) ? wire_nlO1ll_dataout : wire_nlllOl_dataout;
	assign		wire_nlll0O_dataout = (nl1OiO === 1'b1) ? wire_nlO1lO_dataout : wire_nlllOO_dataout;
	assign		wire_nlllii_dataout = (nl1OiO === 1'b1) ? wire_nlO1Oi_dataout : wire_nllO1i_dataout;
	assign		wire_nlllil_dataout = (nl1OiO === 1'b1) ? wire_nlO1Ol_dataout : wire_nllO1l_dataout;
	assign		wire_nllliO_dataout = (nl1OiO === 1'b1) ? wire_nlO1OO_dataout : wire_nllO1O_dataout;
	assign		wire_nlllli_dataout = (nl1OiO === 1'b1) ? wire_nlO01i_dataout : wire_nllO0i_dataout;
	assign		wire_nlllll_dataout = (nl1OiO === 1'b1) ? wire_nlO01l_dataout : wire_nllO0l_dataout;
	assign		wire_nllllO_dataout = (nl1OiO === 1'b1) ? wire_nlO01O_dataout : wire_nllO0O_dataout;
	and(wire_nlllOi_dataout, wire_nllOii_dataout, ~((~ nl00lO)));
	and(wire_nlllOl_dataout, wire_nllOil_dataout, ~((~ nl00lO)));
	and(wire_nlllOO_dataout, wire_nllOiO_dataout, ~((~ nl00lO)));
	and(wire_nllO0i_dataout, wire_nllOOi_dataout, ~((~ nl00lO)));
	and(wire_nllO0l_dataout, wire_nllOOl_dataout, ~((~ nl00lO)));
	and(wire_nllO0O_dataout, wire_nllOOO_dataout, ~((~ nl00lO)));
	and(wire_nllO1i_dataout, wire_nllOli_dataout, ~((~ nl00lO)));
	and(wire_nllO1l_dataout, wire_nllOll_dataout, ~((~ nl00lO)));
	and(wire_nllO1O_dataout, wire_nllOlO_dataout, ~((~ nl00lO)));
	or(wire_nllOii_dataout, wire_nlO11i_dataout, nl00OO);
	or(wire_nllOil_dataout, wire_nlO11l_dataout, nl00OO);
	or(wire_nllOiO_dataout, wire_nlO11O_dataout, nl00OO);
	and(wire_nllOli_dataout, wire_nlO10i_dataout, ~(nl00OO));
	and(wire_nllOll_dataout, wire_nlO10l_dataout, ~(nl00OO));
	and(wire_nllOlO_dataout, wire_nlO10O_dataout, ~(nl00OO));
	and(wire_nllOOi_dataout, wire_nlO1ii_dataout, ~(nl00OO));
	and(wire_nllOOl_dataout, wire_nlO1il_dataout, ~(nl00OO));
	or(wire_nllOOO_dataout, wire_nlO1iO_dataout, nl00OO);
	and(wire_nlO_dataout, running_disp[0], ~(nli11i));
	or(wire_nlO00i_dataout, wire_nlO11i_dataout, nl1OlO);
	or(wire_nlO00l_dataout, wire_nlO11l_dataout, nl1OlO);
	or(wire_nlO00O_dataout, wire_nlO11O_dataout, nl1OlO);
	and(wire_nlO01i_dataout, wire_nlO0li_dataout, ~((~ nl00lO)));
	and(wire_nlO01l_dataout, wire_nlO0ll_dataout, ~((~ nl00lO)));
	and(wire_nlO01O_dataout, wire_nlO0lO_dataout, ~((~ nl00lO)));
	or(wire_nlO0i_dataout, wire_nlOOi_dataout, wire_n0iO_o);
	and(wire_nlO0ii_dataout, wire_nlO10i_dataout, ~(nl1OlO));
	and(wire_nlO0il_dataout, wire_nlO10l_dataout, ~(nl1OlO));
	and(wire_nlO0iO_dataout, wire_nlO10O_dataout, ~(nl1OlO));
	or(wire_nlO0l_dataout, wire_nlOOl_dataout, wire_n0iO_o);
	and(wire_nlO0li_dataout, wire_nlO1ii_dataout, ~(nl1OlO));
	and(wire_nlO0ll_dataout, wire_nlO1il_dataout, ~(nl1OlO));
	or(wire_nlO0lO_dataout, wire_nlO1iO_dataout, nl1OlO);
	or(wire_nlO0O_dataout, wire_nlOOO_dataout, wire_n0iO_o);
	or(wire_nlO10i_dataout, dec_data[11], wire_ni_dataout);
	or(wire_nlO10l_dataout, dec_data[12], wire_ni_dataout);
	or(wire_nlO10O_dataout, dec_data[13], wire_ni_dataout);
	and(wire_nlO11i_dataout, dec_data[8], ~(wire_ni_dataout));
	or(wire_nlO11l_dataout, dec_data[9], wire_ni_dataout);
	or(wire_nlO11O_dataout, dec_data[10], wire_ni_dataout);
	or(wire_nlO1i_dataout, wire_nlOli_dataout, wire_n0iO_o);
	or(wire_nlO1ii_dataout, dec_data[14], wire_ni_dataout);
	or(wire_nlO1il_dataout, dec_data[15], wire_ni_dataout);
	or(wire_nlO1iO_dataout, dec_ctl[1], wire_ni_dataout);
	and(wire_nlO1l_dataout, wire_nlOll_dataout, ~(wire_n0iO_o));
	and(wire_nlO1li_dataout, wire_nlO00i_dataout, ~((~ nl00lO)));
	and(wire_nlO1ll_dataout, wire_nlO00l_dataout, ~((~ nl00lO)));
	and(wire_nlO1lO_dataout, wire_nlO00O_dataout, ~((~ nl00lO)));
	and(wire_nlO1O_dataout, wire_nlOlO_dataout, ~(wire_n0iO_o));
	and(wire_nlO1Oi_dataout, wire_nlO0ii_dataout, ~((~ nl00lO)));
	and(wire_nlO1Ol_dataout, wire_nlO0il_dataout, ~((~ nl00lO)));
	and(wire_nlO1OO_dataout, wire_nlO0iO_dataout, ~((~ nl00lO)));
	and(wire_nlOii_dataout, wire_n11i_dataout, ~(wire_n0iO_o));
	assign		wire_nlOiii_dataout = (nl1OiO === 1'b1) ? wire_nlOOOi_dataout : wire_nlOl1i_dataout;
	assign		wire_nlOiil_dataout = (nl1OiO === 1'b1) ? wire_nlOOOl_dataout : wire_nlOl1l_dataout;
	assign		wire_nlOiiO_dataout = (nl1OiO === 1'b1) ? wire_nlOOOO_dataout : wire_nlOl1O_dataout;
	and(wire_nlOil_dataout, wire_n11l_dataout, ~(wire_n0iO_o));
	assign		wire_nlOili_dataout = (nl1OiO === 1'b1) ? wire_n111i_dataout : wire_nlOl0i_dataout;
	assign		wire_nlOill_dataout = (nl1OiO === 1'b1) ? wire_n111l_dataout : wire_nlOl0l_dataout;
	assign		wire_nlOilO_dataout = (nl1OiO === 1'b1) ? wire_n111O_dataout : wire_nlOl0O_dataout;
	or(wire_nlOiO_dataout, wire_n11O_dataout, wire_n0iO_o);
	assign		wire_nlOiOi_dataout = (nl1OiO === 1'b1) ? wire_n110i_dataout : wire_nlOlii_dataout;
	assign		wire_nlOiOl_dataout = (nl1OiO === 1'b1) ? wire_n110l_dataout : wire_nlOlil_dataout;
	assign		wire_nlOiOO_dataout = (nl1OiO === 1'b1) ? wire_n110O_dataout : wire_nlOliO_dataout;
	and(wire_nlOl0i_dataout, wire_nlOlOi_dataout, ~((~ nl00lO)));
	and(wire_nlOl0l_dataout, wire_nlOlOl_dataout, ~((~ nl00lO)));
	and(wire_nlOl0O_dataout, wire_nlOlOO_dataout, ~((~ nl00lO)));
	or(wire_nlOl1i_dataout, wire_nlOlli_dataout, (~ nl00lO));
	and(wire_nlOl1l_dataout, wire_nlOlll_dataout, ~((~ nl00lO)));
	and(wire_nlOl1O_dataout, wire_nlOllO_dataout, ~((~ nl00lO)));
	or(wire_nlOli_dataout, wire_n10i_dataout, wire_n0il_o);
	and(wire_nlOlii_dataout, wire_nlOO1i_dataout, ~((~ nl00lO)));
	and(wire_nlOlil_dataout, wire_nlOO1l_dataout, ~((~ nl00lO)));
	and(wire_nlOliO_dataout, wire_nlOO1O_dataout, ~((~ nl00lO)));
	or(wire_nlOll_dataout, wire_n10l_dataout, wire_n0il_o);
	or(wire_nlOlli_dataout, wire_nlOO0i_dataout, nl00OO);
	or(wire_nlOlll_dataout, wire_nlOO0l_dataout, nl00OO);
	or(wire_nlOllO_dataout, wire_nlOO0O_dataout, nl00OO);
	or(wire_nlOlO_dataout, wire_n10O_dataout, wire_n0il_o);
	and(wire_nlOlOi_dataout, wire_nlOOii_dataout, ~(nl00OO));
	and(wire_nlOlOl_dataout, wire_nlOOil_dataout, ~(nl00OO));
	and(wire_nlOlOO_dataout, wire_nlOOiO_dataout, ~(nl00OO));
	and(wire_nlOO0i_dataout, dec_data[16], ~(wire_nl_dataout));
	or(wire_nlOO0l_dataout, dec_data[17], wire_nl_dataout);
	or(wire_nlOO0O_dataout, dec_data[18], wire_nl_dataout);
	and(wire_nlOO1i_dataout, wire_nlOOli_dataout, ~(nl00OO));
	and(wire_nlOO1l_dataout, wire_nlOOll_dataout, ~(nl00OO));
	or(wire_nlOO1O_dataout, wire_nlOOlO_dataout, nl00OO);
	or(wire_nlOOi_dataout, wire_n1ii_dataout, wire_n0il_o);
	or(wire_nlOOii_dataout, dec_data[19], wire_nl_dataout);
	or(wire_nlOOil_dataout, dec_data[20], wire_nl_dataout);
	or(wire_nlOOiO_dataout, dec_data[21], wire_nl_dataout);
	and(wire_nlOOl_dataout, wire_n1il_dataout, ~(wire_n0il_o));
	or(wire_nlOOli_dataout, dec_data[22], wire_nl_dataout);
	or(wire_nlOOll_dataout, dec_data[23], wire_nl_dataout);
	or(wire_nlOOlO_dataout, dec_ctl[2], wire_nl_dataout);
	and(wire_nlOOO_dataout, wire_n1iO_dataout, ~(wire_n0il_o));
	and(wire_nlOOOi_dataout, wire_n11ii_dataout, ~((~ nl00lO)));
	and(wire_nlOOOl_dataout, wire_n11il_dataout, ~((~ nl00lO)));
	and(wire_nlOOOO_dataout, wire_n11iO_dataout, ~((~ nl00lO)));
	and(wire_nO_dataout, running_disp[3], ~(nli11i));
	oper_mux   n0ii
	( 
	.data({wire_n0li_dataout, 1'b0, wire_n0li_dataout, ((nl001O34 ^ nl001O33) & wire_n0li_dataout)}),
	.o(wire_n0ii_o),
	.sel({((nl000i32 ^ nl000i31) & n0OO), n0Ol}));
	defparam
		n0ii.width_data = 4,
		n0ii.width_sel = 2;
	oper_mux   n0il
	( 
	.data({wire_n0ll_dataout, 1'b0, {2{wire_n0ll_dataout}}}),
	.o(wire_n0il_o),
	.sel({n0OO, n0Ol}));
	defparam
		n0il.width_data = 4,
		n0il.width_sel = 2;
	oper_mux   n0iO
	( 
	.data({nl000O, 1'b1, ((nl000l30 ^ nl000l29) & nl000O), nl000O}),
	.o(wire_n0iO_o),
	.sel({n0OO, n0Ol}));
	defparam
		n0iO.width_data = 4,
		n0iO.width_sel = 2;
	assign
		curr_state = {n0OO, n0Ol},
		nl000O = (((~ nl00lO) | nllOO) | (~ (nl00ii28 ^ nl00ii27))),
		nl001i = (nl0O0i | nl001l),
		nl001l = (nl0OlO | nl0Oil),
		nl00li = 1'b1,
		nl00lO = ((((dec_data_valid[0] & dec_data_valid[1]) & dec_data_valid[2]) & dec_data_valid[3]) & (nl00Oi22 ^ nl00Oi21)),
		nl00OO = (((~ (((nl0l1O | nl0iOl) | nl0ilO) | ((~ dec_ctl[3]) | (~ nl0ill)))) | (~ ((((nl0O1l | nl0lOi) | nl0liO) | nl0l0l) | (~ (nl0iiO16 ^ nl0iiO15))))) | (~ (((((~ dec_ctl[0]) | (~ nl0iil)) | (((~ dec_ctl[1]) | (~ nl0iii)) | (~ (nl0i0l18 ^ nl0i0l17)))) | (((~ dec_ctl[2]) | (~ nl0i0i)) | (~ (nl0i1l20 ^ nl0i1l19)))) | ((~ dec_ctl[3]) | (~ nl0i1i))))),
		nl010i = ((wire_ni_dataout | nl0lOi) | (~ (nl010l42 ^ nl010l41))),
		nl011O = (n101i | nlliil),
		nl01ii = ((wire_nl_dataout | ((nl0liO & nl0ilO) & (nl01li38 ^ nl01li37))) | (~ (nl01il40 ^ nl01il39))),
		nl01lO = (wire_nl_dataout | nl0liO),
		nl01Oi = ((wire_nO_dataout | nl0l0l) | (~ (nl01Ol36 ^ nl01Ol35))),
		nl0i0i = ((((((((~ dec_data[16]) & (~ dec_data[17])) & dec_data[18]) & dec_data[19]) & dec_data[20]) & (~ dec_data[21])) & (~ dec_data[22])) & (~ dec_data[23])),
		nl0i1i = ((((((((~ dec_data[24]) & (~ dec_data[25])) & dec_data[26]) & dec_data[27]) & dec_data[28]) & (~ dec_data[29])) & (~ dec_data[30])) & (~ dec_data[31])),
		nl0iii = ((((((((~ dec_data[8]) & (~ dec_data[9])) & dec_data[10]) & dec_data[11]) & dec_data[12]) & (~ dec_data[13])) & (~ dec_data[14])) & (~ dec_data[15])),
		nl0iil = ((((((((~ dec_data[0]) & (~ dec_data[1])) & dec_data[2]) & dec_data[3]) & dec_data[4]) & (~ dec_data[5])) & (~ dec_data[6])) & (~ dec_data[7])),
		nl0ill = ((((((((~ dec_data[24]) & (~ dec_data[25])) & dec_data[26]) & dec_data[27]) & dec_data[28]) & dec_data[29]) & dec_data[30]) & (~ dec_data[31])),
		nl0ilO = ((~ dec_ctl[2]) | (~ nl0iOi)),
		nl0iOi = ((((((((~ dec_data[16]) & (~ dec_data[17])) & dec_data[18]) & dec_data[19]) & dec_data[20]) & dec_data[21]) & dec_data[22]) & (~ dec_data[23])),
		nl0iOl = (((~ dec_ctl[1]) | (~ nl0l1l)) | (~ (nl0iOO14 ^ nl0iOO13))),
		nl0l0i = ((((((((~ dec_data[0]) & (~ dec_data[1])) & dec_data[2]) & dec_data[3]) & dec_data[4]) & dec_data[5]) & dec_data[6]) & (~ dec_data[7])),
		nl0l0l = (((~ dec_ctl[3]) | (~ nl0lil)) | (~ (nl0l0O12 ^ nl0l0O11))),
		nl0l1l = ((((((((~ dec_data[8]) & (~ dec_data[9])) & dec_data[10]) & dec_data[11]) & dec_data[12]) & dec_data[13]) & dec_data[14]) & (~ dec_data[15])),
		nl0l1O = ((~ dec_ctl[0]) | (~ nl0l0i)),
		nl0lil = ((((((((~ dec_data[24]) & (~ dec_data[25])) & dec_data[26]) & dec_data[27]) & dec_data[28]) & dec_data[29]) & (~ dec_data[30])) & dec_data[31]),
		nl0liO = (((~ dec_ctl[2]) | (~ nl0llO)) | (~ (nl0lli10 ^ nl0lli9))),
		nl0llO = ((((((((~ dec_data[16]) & (~ dec_data[17])) & dec_data[18]) & dec_data[19]) & dec_data[20]) & dec_data[21]) & (~ dec_data[22])) & dec_data[23]),
		nl0lOi = (((~ dec_ctl[1]) | (~ nl0O1i)) | (~ (nl0lOl8 ^ nl0lOl7))),
		nl0O0i = ((~ wire_nl_dataout) & ((dec_ctl[2] & nl0Oii) & (nl0O0l6 ^ nl0O0l5))),
		nl0O1i = ((((((((~ dec_data[8]) & (~ dec_data[9])) & dec_data[10]) & dec_data[11]) & dec_data[12]) & dec_data[13]) & (~ dec_data[14])) & dec_data[15]),
		nl0O1l = ((~ dec_ctl[0]) | (~ nl0O1O)),
		nl0O1O = ((((((((~ dec_data[0]) & (~ dec_data[1])) & dec_data[2]) & dec_data[3]) & dec_data[4]) & dec_data[5]) & (~ dec_data[6])) & dec_data[7]),
		nl0Oii = (((((((dec_data[16] & (~ dec_data[17])) & dec_data[18]) & dec_data[19]) & dec_data[20]) & dec_data[21]) & dec_data[22]) & dec_data[23]),
		nl0Oil = ((~ wire_ni_dataout) & ((dec_ctl[1] & nl0Oll) & (nl0OiO4 ^ nl0OiO3))),
		nl0Oll = (((((((dec_data[8] & (~ dec_data[9])) & dec_data[10]) & dec_data[11]) & dec_data[12]) & dec_data[13]) & dec_data[14]) & dec_data[15]),
		nl0OlO = ((~ wire_nlO_dataout) & ((dec_ctl[0] & nl0OOO) & (nl0OOi2 ^ nl0OOi1))),
		nl0OOO = (((((((dec_data[0] & (~ dec_data[1])) & dec_data[2]) & dec_data[3]) & dec_data[4]) & dec_data[5]) & dec_data[6]) & dec_data[7]),
		nl1Oil = (((((((dec_data[24] & (~ dec_data[25])) & dec_data[26]) & dec_data[27]) & dec_data[28]) & dec_data[29]) & dec_data[30]) & dec_data[31]),
		nl1OiO = (n0OO & n0Ol),
		nl1Oli = (nl0O0i | nl1Oll),
		nl1Oll = (nl0Oil | nl1OlO),
		nl1OlO = (nl0OlO | nl00OO),
		nl1OOi = (wire_nlO_dataout | (nl0O1l & nl0l1O)),
		nl1OOl = ((n101i | nlliii) | nlliil),
		nl1OOO = ((wire_ni_dataout | (nl0lOi & nl0iOl)) | (~ (nl011i44 ^ nl011i43))),
		nli11i = ((~ n0OO) & (~ n0Ol)),
		rx_ctl_rs = {nl00l, niiil, n0lli, n01OO},
		rx_data_rs = {nl00i, nl01O, nl01l, nl01i, nl1OO, nl1Ol, nl1Oi, niiiO, niiii, nii0O, nii0l, nii0i, nii1O, nii1l, nii1i, n0lll, n0liO, n0lil, n0lii, n0l0O, n0l0l, n0l0i, n0l1O, n001i, n01Ol, n01Oi, n01lO, n01ll, n01li, n01iO, n01il, n10li},
		rx_local_fault = niOi,
		xs_link_status = ni0l;
endmodule //arriagx_hssi_rcv_sm
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 33 mux21 32 oper_add 1 
`timescale 1 ps / 1 ps
module  arriagx_hssi_mdio_addr
	( 
	incr_addr,
	mdc,
	mdio_in,
	reg_addr,
	reset,
	shift_addr) /* synthesis synthesis_clearbox=1 */;
	input   incr_addr;
	input   mdc;
	input   mdio_in;
	output   [15:0]  reg_addr;
	input   reset;
	input   shift_addr;

	reg	nlO0i15;
	reg	nlO0i16;
	reg	nlO0l13;
	reg	nlO0l14;
	reg	nlO0O11;
	reg	nlO0O12;
	reg	nlOii10;
	reg	nlOii9;
	reg	nlOil7;
	reg	nlOil8;
	reg	nlOiO5;
	reg	nlOiO6;
	reg	nlOli3;
	reg	nlOli4;
	reg	nlOOi1;
	reg	nlOOi2;
	reg	n0il;
	reg	n0iO;
	reg	n0li;
	reg	n0ll;
	reg	n0lO;
	reg	n0Oi;
	reg	n0Ol;
	reg	n0OO;
	reg	ni0i;
	reg	ni0l;
	reg	ni0O;
	reg	ni1i;
	reg	ni1l;
	reg	ni1O;
	reg	niii;
	reg	niil;
	reg	nili;
	reg	niiO_clk_prev;
	wire	wire_niiO_CLRN;
	wire	wire_niiO_PRN;
	wire	wire_n0i_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1O_dataout;
	wire	wire_nii_dataout;
	wire	wire_nil_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilO_dataout;
	wire	wire_niO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nli_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nll_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nlO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOO_dataout;
	wire  [15:0]   wire_ni_o;
	wire  nlO1O;
	wire  nlOll;
	wire  nlOlO;

	initial
		nlO0i15 = 0;
	always @ ( posedge mdc)
		  nlO0i15 <= nlO0i16;
	event nlO0i15_event;
	initial
		#1 ->nlO0i15_event;
	always @(nlO0i15_event)
		nlO0i15 <= {1{1'b1}};
	initial
		nlO0i16 = 0;
	always @ ( posedge mdc)
		  nlO0i16 <= nlO0i15;
	initial
		nlO0l13 = 0;
	always @ ( posedge mdc)
		  nlO0l13 <= nlO0l14;
	event nlO0l13_event;
	initial
		#1 ->nlO0l13_event;
	always @(nlO0l13_event)
		nlO0l13 <= {1{1'b1}};
	initial
		nlO0l14 = 0;
	always @ ( posedge mdc)
		  nlO0l14 <= nlO0l13;
	initial
		nlO0O11 = 0;
	always @ ( posedge mdc)
		  nlO0O11 <= nlO0O12;
	event nlO0O11_event;
	initial
		#1 ->nlO0O11_event;
	always @(nlO0O11_event)
		nlO0O11 <= {1{1'b1}};
	initial
		nlO0O12 = 0;
	always @ ( posedge mdc)
		  nlO0O12 <= nlO0O11;
	initial
		nlOii10 = 0;
	always @ ( posedge mdc)
		  nlOii10 <= nlOii9;
	initial
		nlOii9 = 0;
	always @ ( posedge mdc)
		  nlOii9 <= nlOii10;
	event nlOii9_event;
	initial
		#1 ->nlOii9_event;
	always @(nlOii9_event)
		nlOii9 <= {1{1'b1}};
	initial
		nlOil7 = 0;
	always @ ( posedge mdc)
		  nlOil7 <= nlOil8;
	event nlOil7_event;
	initial
		#1 ->nlOil7_event;
	always @(nlOil7_event)
		nlOil7 <= {1{1'b1}};
	initial
		nlOil8 = 0;
	always @ ( posedge mdc)
		  nlOil8 <= nlOil7;
	initial
		nlOiO5 = 0;
	always @ ( posedge mdc)
		  nlOiO5 <= nlOiO6;
	event nlOiO5_event;
	initial
		#1 ->nlOiO5_event;
	always @(nlOiO5_event)
		nlOiO5 <= {1{1'b1}};
	initial
		nlOiO6 = 0;
	always @ ( posedge mdc)
		  nlOiO6 <= nlOiO5;
	initial
		nlOli3 = 0;
	always @ ( posedge mdc)
		  nlOli3 <= nlOli4;
	event nlOli3_event;
	initial
		#1 ->nlOli3_event;
	always @(nlOli3_event)
		nlOli3 <= {1{1'b1}};
	initial
		nlOli4 = 0;
	always @ ( posedge mdc)
		  nlOli4 <= nlOli3;
	initial
		nlOOi1 = 0;
	always @ ( posedge mdc)
		  nlOOi1 <= nlOOi2;
	event nlOOi1_event;
	initial
		#1 ->nlOOi1_event;
	always @(nlOOi1_event)
		nlOOi1 <= {1{1'b1}};
	initial
		nlOOi2 = 0;
	always @ ( posedge mdc)
		  nlOOi2 <= nlOOi1;
	initial
	begin
		n0il = 0;
		n0iO = 0;
		n0li = 0;
		n0ll = 0;
		n0lO = 0;
		n0Oi = 0;
		n0Ol = 0;
		n0OO = 0;
		ni0i = 0;
		ni0l = 0;
		ni0O = 0;
		ni1i = 0;
		ni1l = 0;
		ni1O = 0;
		niii = 0;
		niil = 0;
		nili = 0;
	end
	always @ (mdc or wire_niiO_PRN or wire_niiO_CLRN)
	begin
		if (wire_niiO_PRN == 1'b0) 
		begin
			n0il <= 1;
			n0iO <= 1;
			n0li <= 1;
			n0ll <= 1;
			n0lO <= 1;
			n0Oi <= 1;
			n0Ol <= 1;
			n0OO <= 1;
			ni0i <= 1;
			ni0l <= 1;
			ni0O <= 1;
			ni1i <= 1;
			ni1l <= 1;
			ni1O <= 1;
			niii <= 1;
			niil <= 1;
			nili <= 1;
		end
		else if  (wire_niiO_CLRN == 1'b0) 
		begin
			n0il <= 0;
			n0iO <= 0;
			n0li <= 0;
			n0ll <= 0;
			n0lO <= 0;
			n0Oi <= 0;
			n0Ol <= 0;
			n0OO <= 0;
			ni0i <= 0;
			ni0l <= 0;
			ni0O <= 0;
			ni1i <= 0;
			ni1l <= 0;
			ni1O <= 0;
			niii <= 0;
			niil <= 0;
			nili <= 0;
		end
		else 
		if (mdc != niiO_clk_prev && mdc == 1'b1) 
		begin
			n0il <= wire_nill_dataout;
			n0iO <= wire_nilO_dataout;
			n0li <= wire_niOi_dataout;
			n0ll <= wire_niOl_dataout;
			n0lO <= wire_niOO_dataout;
			n0Oi <= wire_nl1i_dataout;
			n0Ol <= wire_nl1l_dataout;
			n0OO <= wire_nl1O_dataout;
			ni0i <= wire_nlii_dataout;
			ni0l <= wire_nlil_dataout;
			ni0O <= wire_nliO_dataout;
			ni1i <= wire_nl0i_dataout;
			ni1l <= wire_nl0l_dataout;
			ni1O <= wire_nl0O_dataout;
			niii <= wire_nlli_dataout;
			niil <= wire_nlll_dataout;
			nili <= mdio_in;
		end
		niiO_clk_prev <= mdc;
	end
	assign
		wire_niiO_CLRN = ((nlO0l14 ^ nlO0l13) & (~ reset)),
		wire_niiO_PRN = (nlO0i16 ^ nlO0i15);
	assign		wire_n0i_dataout = (nlOll === 1'b1) ? wire_ni_o[7] : n0OO;
	assign		wire_n0l_dataout = (nlOll === 1'b1) ? wire_ni_o[8] : ni1i;
	assign		wire_n0O_dataout = (nlOll === 1'b1) ? wire_ni_o[9] : ni1l;
	assign		wire_n1i_dataout = (nlOll === 1'b1) ? wire_ni_o[4] : n0lO;
	assign		wire_n1l_dataout = (nlOll === 1'b1) ? wire_ni_o[5] : n0Oi;
	assign		wire_n1O_dataout = (nlOll === 1'b1) ? wire_ni_o[6] : n0Ol;
	assign		wire_nii_dataout = (nlOll === 1'b1) ? wire_ni_o[10] : ni1O;
	assign		wire_nil_dataout = (nlOll === 1'b1) ? wire_ni_o[11] : ni0i;
	assign		wire_nill_dataout = (shift_addr === 1'b1) ? nili : wire_nllO_dataout;
	assign		wire_nilO_dataout = (shift_addr === 1'b1) ? n0il : wire_nlOi_dataout;
	assign		wire_niO_dataout = (nlOll === 1'b1) ? wire_ni_o[12] : ni0l;
	assign		wire_niOi_dataout = (shift_addr === 1'b1) ? n0iO : wire_nlOl_dataout;
	assign		wire_niOl_dataout = (shift_addr === 1'b1) ? n0li : wire_nlOO_dataout;
	assign		wire_niOO_dataout = (shift_addr === 1'b1) ? n0ll : wire_n1i_dataout;
	assign		wire_nl0i_dataout = (shift_addr === 1'b1) ? n0OO : wire_n0l_dataout;
	assign		wire_nl0l_dataout = (shift_addr === 1'b1) ? ni1i : wire_n0O_dataout;
	assign		wire_nl0O_dataout = (shift_addr === 1'b1) ? ni1l : wire_nii_dataout;
	assign		wire_nl1i_dataout = (shift_addr === 1'b1) ? n0lO : wire_n1l_dataout;
	assign		wire_nl1l_dataout = (shift_addr === 1'b1) ? n0Oi : wire_n1O_dataout;
	assign		wire_nl1O_dataout = (shift_addr === 1'b1) ? n0Ol : wire_n0i_dataout;
	assign		wire_nli_dataout = (nlOll === 1'b1) ? wire_ni_o[13] : ni0O;
	assign		wire_nlii_dataout = (shift_addr === 1'b1) ? ni1O : wire_nil_dataout;
	assign		wire_nlil_dataout = (shift_addr === 1'b1) ? ni0i : wire_niO_dataout;
	assign		wire_nliO_dataout = (shift_addr === 1'b1) ? ni0l : wire_nli_dataout;
	assign		wire_nll_dataout = (nlOll === 1'b1) ? wire_ni_o[14] : niii;
	assign		wire_nlli_dataout = (shift_addr === 1'b1) ? ni0O : wire_nll_dataout;
	assign		wire_nlll_dataout = (shift_addr === 1'b1) ? niii : wire_nlO_dataout;
	assign		wire_nllO_dataout = (nlOll === 1'b1) ? wire_ni_o[0] : n0il;
	assign		wire_nlO_dataout = (nlOll === 1'b1) ? wire_ni_o[15] : niil;
	assign		wire_nlOi_dataout = (nlOll === 1'b1) ? wire_ni_o[1] : n0iO;
	assign		wire_nlOl_dataout = (nlOll === 1'b1) ? wire_ni_o[2] : n0li;
	assign		wire_nlOO_dataout = (nlOll === 1'b1) ? wire_ni_o[3] : n0ll;
	oper_add   ni
	( 
	.a({((nlO0O12 ^ nlO0O11) & niil), niii, ni0O, ni0l, ni0i, ni1O, ((nlOii10 ^ nlOii9) & ni1l), ni1i, ((nlOil8 ^ nlOil7) & n0OO), ((nlOiO6 ^ nlOiO5) & n0Ol), n0Oi, n0lO, ((nlOli4 ^ nlOli3) & n0ll), n0li, n0iO, n0il}),
	.b({{15{1'b0}}, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_ni_o));
	defparam
		ni.sgate_representation = 0,
		ni.width_a = 16,
		ni.width_b = 16,
		ni.width_o = 16;
	assign
		nlO1O = 1'b1,
		nlOll = ((~ nlOlO) & incr_addr),
		nlOlO = ((((((((((((((((niil & niii) & ni0O) & ni0l) & ni0i) & ni1O) & ni1l) & ni1i) & n0OO) & n0Ol) & n0Oi) & n0lO) & n0ll) & n0li) & n0iO) & n0il) & (nlOOi2 ^ nlOOi1)),
		reg_addr = {niil, niii, ni0O, ni0l, ni0i, ni1O, ni1l, ni1i, n0OO, n0Ol, n0Oi, n0lO, n0ll, n0li, n0iO, n0il};
endmodule //arriagx_hssi_mdio_addr
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 17 mux21 10 oper_add 1 
`timescale 1 ps / 1 ps
module  arriagx_hssi_mdio_cnt
	( 
	cnt_eq_0,
	cnt_val,
	ld_cnt,
	mdc,
	reset) /* synthesis synthesis_clearbox=1 */;
	output   cnt_eq_0;
	input   [4:0]  cnt_val;
	input   ld_cnt;
	input   mdc;
	input   reset;

	reg	ni0O10;
	reg	ni0O9;
	reg	ni1O11;
	reg	ni1O12;
	reg	niiO7;
	reg	niiO8;
	reg	nili5;
	reg	nili6;
	reg	nill3;
	reg	nill4;
	reg	niOi1;
	reg	niOi2;
	reg	n1i;
	reg	ni;
	reg	nlOi;
	reg	nlOl;
	reg	nlOO;
	reg	nlO_clk_prev;
	wire	wire_nlO_CLRN;
	wire	wire_nlO_PRN;
	wire	wire_n0i_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1O_dataout;
	wire	wire_nii_dataout;
	wire	wire_nil_dataout;
	wire	wire_niO_dataout;
	wire	wire_nli_dataout;
	wire	wire_nll_dataout;
	wire  [5:0]   wire_nl_o;
	wire  ni0l;
	wire  niil;
	wire  nilO;

	initial
		ni0O10 = 0;
	always @ ( posedge mdc)
		  ni0O10 <= ni0O9;
	initial
		ni0O9 = 0;
	always @ ( posedge mdc)
		  ni0O9 <= ni0O10;
	event ni0O9_event;
	initial
		#1 ->ni0O9_event;
	always @(ni0O9_event)
		ni0O9 <= {1{1'b1}};
	initial
		ni1O11 = 0;
	always @ ( posedge mdc)
		  ni1O11 <= ni1O12;
	event ni1O11_event;
	initial
		#1 ->ni1O11_event;
	always @(ni1O11_event)
		ni1O11 <= {1{1'b1}};
	initial
		ni1O12 = 0;
	always @ ( posedge mdc)
		  ni1O12 <= ni1O11;
	initial
		niiO7 = 0;
	always @ ( posedge mdc)
		  niiO7 <= niiO8;
	event niiO7_event;
	initial
		#1 ->niiO7_event;
	always @(niiO7_event)
		niiO7 <= {1{1'b1}};
	initial
		niiO8 = 0;
	always @ ( posedge mdc)
		  niiO8 <= niiO7;
	initial
		nili5 = 0;
	always @ ( posedge mdc)
		  nili5 <= nili6;
	event nili5_event;
	initial
		#1 ->nili5_event;
	always @(nili5_event)
		nili5 <= {1{1'b1}};
	initial
		nili6 = 0;
	always @ ( posedge mdc)
		  nili6 <= nili5;
	initial
		nill3 = 0;
	always @ ( posedge mdc)
		  nill3 <= nill4;
	event nill3_event;
	initial
		#1 ->nill3_event;
	always @(nill3_event)
		nill3 <= {1{1'b1}};
	initial
		nill4 = 0;
	always @ ( posedge mdc)
		  nill4 <= nill3;
	initial
		niOi1 = 0;
	always @ ( posedge mdc)
		  niOi1 <= niOi2;
	event niOi1_event;
	initial
		#1 ->niOi1_event;
	always @(niOi1_event)
		niOi1 <= {1{1'b1}};
	initial
		niOi2 = 0;
	always @ ( posedge mdc)
		  niOi2 <= niOi1;
	initial
	begin
		n1i = 0;
		ni = 0;
		nlOi = 0;
		nlOl = 0;
		nlOO = 0;
	end
	always @ (mdc or wire_nlO_PRN or wire_nlO_CLRN)
	begin
		if (wire_nlO_PRN == 1'b0) 
		begin
			n1i <= 1;
			ni <= 1;
			nlOi <= 1;
			nlOl <= 1;
			nlOO <= 1;
		end
		else if  (wire_nlO_CLRN == 1'b0) 
		begin
			n1i <= 0;
			ni <= 0;
			nlOi <= 0;
			nlOl <= 0;
			nlOO <= 0;
		end
		else 
		if (mdc != nlO_clk_prev && mdc == 1'b1) 
		begin
			n1i <= wire_n0O_dataout;
			ni <= wire_n1l_dataout;
			nlOi <= wire_n1O_dataout;
			nlOl <= wire_n0i_dataout;
			nlOO <= wire_n0l_dataout;
		end
		nlO_clk_prev <= mdc;
	end
	assign
		wire_nlO_CLRN = ((nili6 ^ nili5) & (~ reset)),
		wire_nlO_PRN = (niiO8 ^ niiO7);
	assign		wire_n0i_dataout = (ld_cnt === 1'b1) ? cnt_val[2] : wire_niO_dataout;
	assign		wire_n0l_dataout = (ld_cnt === 1'b1) ? cnt_val[3] : wire_nli_dataout;
	assign		wire_n0O_dataout = (ld_cnt === 1'b1) ? cnt_val[4] : wire_nll_dataout;
	assign		wire_n1l_dataout = (ld_cnt === 1'b1) ? cnt_val[0] : wire_nii_dataout;
	assign		wire_n1O_dataout = (ld_cnt === 1'b1) ? cnt_val[1] : wire_nil_dataout;
	assign		wire_nii_dataout = (nilO === 1'b1) ? wire_nl_o[1] : ni;
	assign		wire_nil_dataout = (nilO === 1'b1) ? wire_nl_o[2] : nlOi;
	assign		wire_niO_dataout = (nilO === 1'b1) ? wire_nl_o[3] : nlOl;
	assign		wire_nli_dataout = (nilO === 1'b1) ? wire_nl_o[4] : nlOO;
	assign		wire_nll_dataout = (nilO === 1'b1) ? wire_nl_o[5] : n1i;
	oper_add   nl
	( 
	.a({((nill4 ^ nill3) & n1i), nlOO, nlOl, nlOi, ni, 1'b1}),
	.b({{4{1'b1}}, 1'b0, 1'b1}),
	.cin(1'b0),
	.cout(),
	.o(wire_nl_o));
	defparam
		nl.sgate_representation = 0,
		nl.width_a = 6,
		nl.width_b = 6,
		nl.width_o = 6;
	assign
		cnt_eq_0 = (((~ ni0l) & (~ ld_cnt)) & (ni1O12 ^ ni1O11)),
		ni0l = (((((ni | n1i) | nlOO) | nlOl) | nlOi) | (~ (ni0O10 ^ ni0O9))),
		niil = 1'b1,
		nilO = (((((ni | n1i) | nlOO) | nlOl) | nlOi) | (~ (niOi2 ^ niOi1)));
endmodule //arriagx_hssi_mdio_cnt
//synopsys translate_on
//VALID FILE
//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 47 mux21 36 
`timescale 1 ps / 1 ps
module  arriagx_hssi_mdio_ctl_data
	( 
	data_enable_n,
	dev_addr,
	latch_ctl,
	ld_data,
	mbus_in,
	mbus_out,
	mdc,
	mdio_in,
	mdio_out,
	opcode,
	port_addr,
	reset,
	shift_in,
	shift_out,
	valid_addr,
	valid_addr_lt) /* synthesis synthesis_clearbox=1 */;
	output   data_enable_n;
	input   [4:0]  dev_addr;
	input   latch_ctl;
	input   ld_data;
	output   [15:0]  mbus_in;
	input   [15:0]  mbus_out;
	input   mdc;
	input   mdio_in;
	output   mdio_out;
	output   [1:0]  opcode;
	input   [4:0]  port_addr;
	input   reset;
	input   shift_in;
	input   shift_out;
	output   valid_addr;
	input   valid_addr_lt;

	reg	nilll25;
	reg	nilll26;
	reg	nilOi23;
	reg	nilOi24;
	reg	nilOO21;
	reg	nilOO22;
	reg	niO0i17;
	reg	niO0i18;
	reg	niO0O15;
	reg	niO0O16;
	reg	niO1l19;
	reg	niO1l20;
	reg	niOil13;
	reg	niOil14;
	reg	niOiO11;
	reg	niOiO12;
	reg	niOlO10;
	reg	niOlO9;
	reg	niOOl7;
	reg	niOOl8;
	reg	nl10l3;
	reg	nl10l4;
	reg	nl11l5;
	reg	nl11l6;
	reg	nl1iO1;
	reg	nl1iO2;
	reg	n1li;
	reg	n1lO;
	reg	n1ll_clk_prev;
	wire	wire_n1ll_PRN;
	reg	n00i;
	reg	n00l;
	reg	n00O;
	reg	n01l;
	reg	n01O;
	reg	n0ii;
	reg	n0il;
	reg	n0iO;
	reg	n0li;
	reg	n0ll;
	reg	n0lO;
	reg	n0Oi;
	reg	n0Ol;
	reg	n0OO;
	reg	n1iO;
	reg	n1Oi;
	reg	ni0i;
	reg	ni1i;
	reg	ni1l;
	wire	wire_ni1O_CLRN;
	wire	wire_n0i_dataout;
	wire	wire_n0l_dataout;
	wire	wire_n0O_dataout;
	wire	wire_n1i_dataout;
	wire	wire_n1l_dataout;
	wire	wire_n1O_dataout;
	wire	wire_n1Ol_dataout;
	wire	wire_n1OO_dataout;
	wire	wire_ni0l_dataout;
	wire	wire_ni0O_dataout;
	wire	wire_niii_dataout;
	wire	wire_niil_dataout;
	wire	wire_niiO_dataout;
	wire	wire_nili_dataout;
	wire	wire_nill_dataout;
	wire	wire_nilO_dataout;
	wire	wire_niOi_dataout;
	wire	wire_niOl_dataout;
	wire	wire_niOO_dataout;
	wire	wire_nl_dataout;
	wire	wire_nl0i_dataout;
	wire	wire_nl0l_dataout;
	wire	wire_nl0O_dataout;
	wire	wire_nl1i_dataout;
	wire	wire_nl1l_dataout;
	wire	wire_nl1O_dataout;
	wire	wire_nlii_dataout;
	wire	wire_nlil_dataout;
	wire	wire_nliO_dataout;
	wire	wire_nlli_dataout;
	wire	wire_nlll_dataout;
	wire	wire_nllO_dataout;
	wire	wire_nlOi_dataout;
	wire	wire_nlOl_dataout;
	wire	wire_nlOO_dataout;
	wire	wire_nO_dataout;
	wire  niOll;
	wire  nl10i;
	wire  nl11i;
	wire  nl11O;
	wire  nl1ii;
	wire  nl1il;

	initial
		nilll25 = 0;
	always @ ( posedge mdc)
		  nilll25 <= nilll26;
	event nilll25_event;
	initial
		#1 ->nilll25_event;
	always @(nilll25_event)
		nilll25 <= {1{1'b1}};
	initial
		nilll26 = 0;
	always @ ( posedge mdc)
		  nilll26 <= nilll25;
	initial
		nilOi23 = 0;
	always @ ( posedge mdc)
		  nilOi23 <= nilOi24;
	event nilOi23_event;
	initial
		#1 ->nilOi23_event;
	always @(nilOi23_event)
		nilOi23 <= {1{1'b1}};
	initial
		nilOi24 = 0;
	always @ ( posedge mdc)
		  nilOi24 <= nilOi23;
	initial
		nilOO21 = 0;
	always @ ( posedge mdc)
		  nilOO21 <= nilOO22;
	event nilOO21_event;
	initial
		#1 ->nilOO21_event;
	always @(nilOO21_event)
		nilOO21 <= {1{1'b1}};
	initial
		nilOO22 = 0;
	always @ ( posedge mdc)
		  nilOO22 <= nilOO21;
	initial
		niO0i17 = 0;
	always @ ( posedge mdc)
		  niO0i17 <= niO0i18;
	event niO0i17_event;
	initial
		#1 ->niO0i17_event;
	always @(niO0i17_event)
		niO0i17 <= {1{1'b1}};
	initial
		niO0i18 = 0;
	always @ ( posedge mdc)
		  niO0i18 <= niO0i17;
	initial
		niO0O15 = 0;
	always @ ( posedge mdc)
		  niO0O15 <= niO0O16;
	event niO0O15_event;
	initial
		#1 ->niO0O15_event;
	always @(niO0O15_event)
		niO0O15 <= {1{1'b1}};
	initial
		niO0O16 = 0;
	always @ ( posedge mdc)
		  niO0O16 <= niO0O15;
	initial
		niO1l19 = 0;
	always @ ( posedge mdc)
		  niO1l19 <= niO1l20;
	event niO1l19_event;
	initial
		#1 ->niO1l19_event;
	always @(niO1l19_event)
		niO1l19 <= {1{1'b1}};
	initial
		niO1l20 = 0;
	always @ ( posedge mdc)
		  niO1l20 <= niO1l19;
	initial
		niOil13 = 0;
	always @ ( posedge mdc)
		  niOil13 <= niOil14;
	event niOil13_event;
	initial
		#1 ->niOil13_event;
	always @(niOil13_event)
		niOil13 <= {1{1'b1}};
	initial
		niOil14 = 0;
	always @ ( posedge mdc)
		  niOil14 <= niOil13;
	initial
		niOiO11 = 0;
	always @ ( posedge mdc)
		  niOiO11 <= niOiO12;
	event niOiO11_event;
	initial
		#1 ->niOiO11_event;
	always @(niOiO11_event)
		niOiO11 <= {1{1'b1}};
	initial
		niOiO12 = 0;
	always @ ( posedge mdc)
		  niOiO12 <= niOiO11;
	initial
		niOlO10 = 0;
	always @ ( posedge mdc)
		  niOlO10 <= niOlO9;
	initial
		niOlO9 = 0;
	always @ ( posedge mdc)
		  niOlO9 <= niOlO10;
	event niOlO9_event;
	initial
		#1 ->niOlO9_event;
	always @(niOlO9_event)
		niOlO9 <= {1{1'b1}};
	initial
		niOOl7 = 0;
	always @ ( posedge mdc)
		  niOOl7 <= niOOl8;
	event niOOl7_event;
	initial
		#1 ->niOOl7_event;
	always @(niOOl7_event)
		niOOl7 <= {1{1'b1}};
	initial
		niOOl8 = 0;
	always @ ( posedge mdc)
		  niOOl8 <= niOOl7;
	initial
		nl10l3 = 0;
	always @ ( posedge mdc)
		  nl10l3 <= nl10l4;
	event nl10l3_event;
	initial
		#1 ->nl10l3_event;
	always @(nl10l3_event)
		nl10l3 <= {1{1'b1}};
	initial
		nl10l4 = 0;
	always @ ( posedge mdc)
		  nl10l4 <= nl10l3;
	initial
		nl11l5 = 0;
	always @ ( posedge mdc)
		  nl11l5 <= nl11l6;
	event nl11l5_event;
	initial
		#1 ->nl11l5_event;
	always @(nl11l5_event)
		nl11l5 <= {1{1'b1}};
	initial
		nl11l6 = 0;
	always @ ( posedge mdc)
		  nl11l6 <= nl11l5;
	initial
		nl1iO1 = 0;
	always @ ( posedge mdc)
		  nl1iO1 <= nl1iO2;
	event nl1iO1_event;
	initial
		#1 ->nl1iO1_event;
	always @(nl1iO1_event)
		nl1iO1 <= {1{1'b1}};
	initial
		nl1iO2 = 0;
	always @ ( posedge mdc)
		  nl1iO2 <= nl1iO1;
	initial
	begin
		n1li = 0;
		n1lO = 0;
	end
	always @ (mdc or wire_n1ll_PRN or reset)
	begin
		if (wire_n1ll_PRN == 1'b0) 
		begin
			n1li <= 1;
			n1lO <= 1;
		end
		else if  (reset == 1'b1) 
		begin
			n1li <= 0;
			n1lO <= 0;
		end
		else if  (latch_ctl == 1'b1) 
		if (mdc != n1ll_clk_prev && mdc == 1'b1) 
		begin
			n1li <= n0lO;
			n1lO <= n0Oi;
		end
		n1ll_clk_prev <= mdc;
	end
	assign
		wire_n1ll_PRN = (niOil14 ^ niOil13);
	initial
	begin
		n00i = 0;
		n00l = 0;
		n00O = 0;
		n01l = 0;
		n01O = 0;
		n0ii = 0;
		n0il = 0;
		n0iO = 0;
		n0li = 0;
		n0ll = 0;
		n0lO = 0;
		n0Oi = 0;
		n0Ol = 0;
		n0OO = 0;
		n1iO = 0;
		n1Oi = 0;
		ni0i = 0;
		ni1i = 0;
		ni1l = 0;
	end
	always @ ( posedge mdc or  negedge wire_ni1O_CLRN)
	begin
		if (wire_ni1O_CLRN == 1'b0) 
		begin
			n00i <= 0;
			n00l <= 0;
			n00O <= 0;
			n01l <= 0;
			n01O <= 0;
			n0ii <= 0;
			n0il <= 0;
			n0iO <= 0;
			n0li <= 0;
			n0ll <= 0;
			n0lO <= 0;
			n0Oi <= 0;
			n0Ol <= 0;
			n0OO <= 0;
			n1iO <= 0;
			n1Oi <= 0;
			ni0i <= 0;
			ni1i <= 0;
			ni1l <= 0;
		end
		else 
		begin
			n00i <= wire_ni0O_dataout;
			n00l <= wire_niii_dataout;
			n00O <= wire_niil_dataout;
			n01l <= wire_n1Ol_dataout;
			n01O <= wire_ni0l_dataout;
			n0ii <= wire_niiO_dataout;
			n0il <= wire_nili_dataout;
			n0iO <= wire_nill_dataout;
			n0li <= wire_nilO_dataout;
			n0ll <= wire_niOi_dataout;
			n0lO <= wire_niOl_dataout;
			n0Oi <= wire_niOO_dataout;
			n0Ol <= wire_nl1i_dataout;
			n0OO <= wire_nl1l_dataout;
			n1iO <= wire_n1OO_dataout;
			n1Oi <= mdio_in;
			ni0i <= wire_nl0l_dataout;
			ni1i <= wire_nl1O_dataout;
			ni1l <= wire_nl0i_dataout;
		end
	end
	assign
		wire_ni1O_CLRN = ((nl11l6 ^ nl11l5) & (~ reset));
	assign		wire_n0i_dataout = (nl11O === 1'b1) ? n0OO : ni1i;
	assign		wire_n0l_dataout = (nl11O === 1'b1) ? ni1i : ni1l;
	assign		wire_n0O_dataout = (nl11O === 1'b1) ? ni1l : ni0i;
	assign		wire_n1i_dataout = (nl11O === 1'b1) ? n0lO : n0Oi;
	assign		wire_n1l_dataout = (nl11O === 1'b1) ? n0Oi : n0Ol;
	assign		wire_n1O_dataout = (nl11O === 1'b1) ? n0Ol : n0OO;
	assign		wire_n1Ol_dataout = (latch_ctl === 1'b1) ? niOll : ((n01l & n1iO) & (niOiO12 ^ niOiO11));
	and(wire_n1OO_dataout, niOll, latch_ctl);
	assign		wire_ni0l_dataout = (ld_data === 1'b1) ? mbus_out[15] : wire_nl0O_dataout;
	assign		wire_ni0O_dataout = (ld_data === 1'b1) ? mbus_out[0] : wire_nlii_dataout;
	assign		wire_niii_dataout = (ld_data === 1'b1) ? mbus_out[1] : wire_nlil_dataout;
	assign		wire_niil_dataout = (ld_data === 1'b1) ? mbus_out[2] : wire_nliO_dataout;
	assign		wire_niiO_dataout = (ld_data === 1'b1) ? mbus_out[3] : wire_nlli_dataout;
	assign		wire_nili_dataout = (ld_data === 1'b1) ? mbus_out[4] : wire_nlll_dataout;
	assign		wire_nill_dataout = (ld_data === 1'b1) ? mbus_out[5] : wire_nllO_dataout;
	assign		wire_nilO_dataout = (ld_data === 1'b1) ? mbus_out[6] : wire_nlOi_dataout;
	assign		wire_niOi_dataout = (ld_data === 1'b1) ? mbus_out[7] : wire_nlOl_dataout;
	assign		wire_niOl_dataout = (ld_data === 1'b1) ? mbus_out[8] : wire_nlOO_dataout;
	assign		wire_niOO_dataout = (ld_data === 1'b1) ? mbus_out[9] : wire_n1i_dataout;
	assign		wire_nl_dataout = (ld_data === 1'b1) ? mbus_out[15] : wire_nO_dataout;
	assign		wire_nl0i_dataout = (ld_data === 1'b1) ? mbus_out[13] : wire_n0l_dataout;
	assign		wire_nl0l_dataout = (ld_data === 1'b1) ? mbus_out[14] : wire_n0O_dataout;
	assign		wire_nl0O_dataout = (nl11O === 1'b1) ? n1Oi : n01O;
	assign		wire_nl1i_dataout = (ld_data === 1'b1) ? mbus_out[10] : wire_n1l_dataout;
	assign		wire_nl1l_dataout = (ld_data === 1'b1) ? mbus_out[11] : wire_n1O_dataout;
	assign		wire_nl1O_dataout = (ld_data === 1'b1) ? mbus_out[12] : wire_n0i_dataout;
	assign		wire_nlii_dataout = (nl11O === 1'b1) ? n01O : n00i;
	assign		wire_nlil_dataout = (nl11O === 1'b1) ? n00i : n00l;
	assign		wire_nliO_dataout = (nl11O === 1'b1) ? n00l : n00O;
	assign		wire_nlli_dataout = (nl11O === 1'b1) ? n00O : n0ii;
	assign		wire_nlll_dataout = (nl11O === 1'b1) ? n0ii : n0il;
	assign		wire_nllO_dataout = (nl11O === 1'b1) ? n0il : n0iO;
	assign		wire_nlOi_dataout = (nl11O === 1'b1) ? n0iO : n0li;
	assign		wire_nlOl_dataout = (nl11O === 1'b1) ? n0li : n0ll;
	assign		wire_nlOO_dataout = (nl11O === 1'b1) ? n0ll : n0lO;
	and(wire_nO_dataout, ni0i, shift_out);
	assign
		data_enable_n = (~ ((((shift_out | ld_data) | n01l) & (nl10i | valid_addr_lt)) & (niO0O16 ^ niO0O15))),
		mbus_in = {ni0i, ni1l, ni1i, n0OO, n0Ol, n0Oi, n0lO, n0ll, n0li, n0iO, n0il, n0ii, n00O, n00l, n00i, n01O},
		mdio_out = wire_nl_dataout,
		niOll = (((n0Oi & n0lO) | ((n0Oi & (~ n0lO)) & (niOOl8 ^ niOOl7))) | (~ (niOlO10 ^ niOlO9))),
		nl10i = ((((((~ ni1i) & (~ n0OO)) & (nl1iO2 ^ nl1iO1)) & nl1il) & nl1ii) & (nl10l4 ^ nl10l3)),
		nl11i = 1'b1,
		nl11O = (shift_in | shift_out),
		nl1ii = ((((((~ (n01O ^ dev_addr[0])) & (~ ((n00i ^ dev_addr[1]) ^ (~ (nilOO22 ^ nilOO21))))) & (~ ((n00l ^ dev_addr[2]) ^ (~ (nilOi24 ^ nilOi23))))) & (~ (n00O ^ dev_addr[3]))) & (~ (n0ii ^ dev_addr[4]))) & (nilll26 ^ nilll25)),
		nl1il = (((((~ (n0il ^ port_addr[0])) & (~ (n0iO ^ port_addr[1]))) & (~ ((n0li ^ port_addr[2]) ^ (~ (niO0i18 ^ niO0i17))))) & (~ ((n0ll ^ port_addr[3]) ^ (~ (niO1l20 ^ niO1l19))))) & (~ (n0lO ^ port_addr[4]))),
		opcode = {n1lO, n1li},
		valid_addr = nl10i;
endmodule //arriagx_hssi_mdio_ctl_data
//synopsys translate_on
//VALID FILE

`timescale 1 ps / 1 ps

module arriagx_hssi_mdio_pcs_bus_out_mux (pcs_ctrl_in1, pcs_ctrl_in2, pcs_ctrl_in3, pcs_ctrl_in4,
                             pcs_ctrl_in5, pcs_ctrl_in6, pcs_ctrl_in7, pcs_ctrl_in8,
                             pcs_ctrl_in9, pcs_ctrl_in10, pcs_ctrl_in11, pcs_ctrl_in12,
                             pcs_ctrl_in13, pcs_ctrl_in14, pcs_ctrl_in15, pcs_ctrl_in16,
                             hw_address_ctrl_in1, hw_address_ctrl_in2, hw_address_ctrl_in3,
                             hw_address_ctrl_in4, hw_address_ctrl_in5, hw_address_ctrl_in6,
                             hw_address_ctrl_in7, hw_address_ctrl_in8, hw_address_ctrl_in9,
                             hw_address_ctrl_in10, hw_address_ctrl_in11, hw_address_ctrl_in12,
                             hw_address_ctrl_in13, hw_address_ctrl_in14, hw_address_ctrl_in15,
                             hw_address_ctrl_in16, reg_addr, pcs_ctrl_out
                            );
                            
input   [15:0] pcs_ctrl_in1;
input   [15:0] pcs_ctrl_in2;
input   [15:0] pcs_ctrl_in3;
input   [15:0] pcs_ctrl_in4;
input   [15:0] pcs_ctrl_in5;
input   [15:0] pcs_ctrl_in6;
input   [15:0] pcs_ctrl_in7;
input   [15:0] pcs_ctrl_in8;
input   [15:0] pcs_ctrl_in9;
input   [15:0] pcs_ctrl_in10;
input   [15:0] pcs_ctrl_in11;
input   [15:0] pcs_ctrl_in12;
input   [15:0] pcs_ctrl_in13;
input   [15:0] pcs_ctrl_in14;
input   [15:0] pcs_ctrl_in15;
input   [15:0] pcs_ctrl_in16;
input   [15:0] hw_address_ctrl_in1;
input   [15:0] hw_address_ctrl_in2;
input   [15:0] hw_address_ctrl_in3;
input   [15:0] hw_address_ctrl_in4;
input   [15:0] hw_address_ctrl_in5;
input   [15:0] hw_address_ctrl_in6;
input   [15:0] hw_address_ctrl_in7;
input   [15:0] hw_address_ctrl_in8;
input   [15:0] hw_address_ctrl_in9;
input   [15:0] hw_address_ctrl_in10;
input   [15:0] hw_address_ctrl_in11;
input   [15:0] hw_address_ctrl_in12;
input   [15:0] hw_address_ctrl_in13;
input   [15:0] hw_address_ctrl_in14;
input   [15:0] hw_address_ctrl_in15;
input   [15:0] hw_address_ctrl_in16;
input   [15:0] reg_addr;

output  [15:0] pcs_ctrl_out;

assign  pcs_ctrl_out = (reg_addr == hw_address_ctrl_in1 ) ?  pcs_ctrl_in1  :
                       (reg_addr == hw_address_ctrl_in2 ) ?  pcs_ctrl_in2  :
                       (reg_addr == hw_address_ctrl_in3 ) ?  pcs_ctrl_in3  :
                       (reg_addr == hw_address_ctrl_in4 ) ?  pcs_ctrl_in4  :
                       (reg_addr == hw_address_ctrl_in5 ) ?  pcs_ctrl_in5  :
                       (reg_addr == hw_address_ctrl_in6 ) ?  pcs_ctrl_in6  :
                       (reg_addr == hw_address_ctrl_in7 ) ?  pcs_ctrl_in7  :
                       (reg_addr == hw_address_ctrl_in8 ) ?  pcs_ctrl_in8  :
                       (reg_addr == hw_address_ctrl_in9 ) ?  pcs_ctrl_in9  :
                       (reg_addr == hw_address_ctrl_in10) ?  pcs_ctrl_in10 :
                       (reg_addr == hw_address_ctrl_in11) ?  pcs_ctrl_in11 :
                       (reg_addr == hw_address_ctrl_in12) ?  pcs_ctrl_in12 :
                       (reg_addr == hw_address_ctrl_in13) ?  pcs_ctrl_in13 :
                       (reg_addr == hw_address_ctrl_in14) ?  pcs_ctrl_in14 :
                       (reg_addr == hw_address_ctrl_in15) ?  pcs_ctrl_in15 :
                       (reg_addr == hw_address_ctrl_in16) ?  pcs_ctrl_in16 :
                       16'h0000;
                       
endmodule


































`timescale 1 ns / 1 ps

module arriagx_hssi_mdio_sm (mdc, mdio_in, reset, opcode, valid_addr,
                cnt_eq_0, shift_in, shift_out, latch_ctl, incr_addr,
                mdio_wr, mdio_rd, shift_addr, ld_data, ld_cnt, cnt_val, 
		valid_addr_lt, curr_state);


input        mdc;         // Clock for MDIO interface
input        mdio_in;     // Signal bit data
input        reset;       // Active high Hard Reset
input  [1:0] opcode;      // 2 bit opcode from mdio_ctl_data module
                          // 00 - Address
                          // 01 - Write
                          // 10 - Read with no post Increment
                          // 11 - Read with post increment
input        valid_addr;  // When set the Port and Dev Address
                          // corresponds to this module
input        cnt_eq_0;    // From mdio_cnt module, down counter is 0
output       shift_in;    // Shift in enable for either data or control
output       shift_out;   // Shift out enable for mdio_ctl_data
output       latch_ctl;   // Latch the Opcode, to mdio_ctl_data
output       incr_addr;   // Increment signal for mdio_addr
output       mdio_wr;     // This is used for writing the mdio registers
output       mdio_rd;     // This is used for clearing the mdio status registers
output       shift_addr;  // Shift in Enable for mdio_addr
output       ld_data;     // When set, the shift register is mdio_ctl_data is parallely
                          // loaded with the data from mdio_reg module
//output       ld_data_d;
output       ld_cnt;      // Load Down counter
output [4:0] cnt_val;     // Value to load the down counter
output	     valid_addr_lt;
output [2:0] curr_state;

reg       shift_in;
reg       shift_out;
reg       latch_ctl;
reg       incr_addr;
reg       mdio_wr;
reg       mdio_rd;
reg       shift_addr;
reg       ld_data;
reg       ld_cnt;
reg [4:0] cnt_val;
//wire      ld_data_d;

// Allowed states for curr_state and next_state

parameter IDLE         = 3'b000;
parameter PREAMBLE     = 3'b001;
parameter CONTROL      = 3'b010;
parameter TURN_ARND_0  = 3'b011;
parameter TURN_ARND_1  = 3'b100;
parameter ADDR_DATA    = 3'b101;


// Decode for opcode

parameter ADDR_OP   = 2'b00;
parameter WR_OP     = 2'b01;
parameter RD_INC_OP = 2'b10;
parameter RD_OP     = 2'b11;


reg [2:0] curr_state;
reg [2:0] next_state;
reg	  valid_addr_lt;

// Latch Curr State

always @(posedge reset or posedge mdc)
begin
   if (reset)
      curr_state <= IDLE;
   else
      curr_state <= next_state;
end


// Next State loic for mdio_sm

always @(curr_state or mdio_in or cnt_eq_0 or valid_addr or opcode)
begin

   case (curr_state)

       IDLE : 
                     if (mdio_in)
                        next_state <= PREAMBLE;
                     else
                        next_state <= IDLE;

       PREAMBLE : 
                     if (~mdio_in && ~cnt_eq_0)
                        next_state <= IDLE;
                     else if (~mdio_in && cnt_eq_0)
                        next_state <= CONTROL;
                     else
                        next_state <= PREAMBLE;
       CONTROL :
                     if (cnt_eq_0)
                        if (~mdio_in)
                           next_state <= IDLE;
                        else
                           next_state <= TURN_ARND_0;
                     else
                        next_state <= CONTROL;
 
       TURN_ARND_0 : 
                     if (mdio_in || ~valid_addr)
                         next_state <= IDLE;
                     else if (opcode == WR_OP || opcode == ADDR_OP)
                         next_state <= TURN_ARND_1;
                     else
                         next_state <= ADDR_DATA;

       TURN_ARND_1 :
//                     if (mdio_in)
//                         next_state <= IDLE;
//                     else
                         next_state <= ADDR_DATA;

       ADDR_DATA :
                    if (cnt_eq_0 && mdio_in && (opcode == WR_OP || opcode == ADDR_OP))
                       next_state <= PREAMBLE;
                    else if (cnt_eq_0)
                       next_state <= IDLE;
                    else
                       next_state <= ADDR_DATA;

       default:     next_state <= IDLE;

   endcase

end

// Valid_addr_lt is used to enable mdio_out

always @(posedge reset or posedge mdc)
begin
   if (reset)
       valid_addr_lt <= 1'b0;
   else
      if (valid_addr && curr_state == TURN_ARND_0)
         valid_addr_lt <= 1'b1;
      else if (curr_state == ADDR_DATA && cnt_eq_0)
         valid_addr_lt <= 1'b0;
end

// Logic for shift_in, This signal is used for shifting in
// control logic, during all commands, and data during
// Write command

always @(posedge reset or posedge mdc)
begin
   if (reset)
       shift_in <= 1'b0;
   else
      if ((curr_state == PREAMBLE && next_state == CONTROL) ||
          (next_state == CONTROL) ||
          (next_state == ADDR_DATA && opcode == WR_OP))
          shift_in <= 1'b1;
      else
          shift_in <= 1'b0;
end


// Shift_out logic, shift_out is set when data is shifted out on
// a RD_OP or RD_INC_OP command

always @(posedge reset or posedge mdc)
begin
   if (reset)
       shift_out <= 1'b0;
   else
      if ((curr_state == TURN_ARND_0 && next_state == ADDR_DATA) ||
          (curr_state == ADDR_DATA && (opcode == RD_OP || 
           opcode == RD_INC_OP) && (~cnt_eq_0)))
          shift_out <= 1'b1;
      else
          shift_out <= 1'b0;
end
            

// Logic for latch_ctl, this signal is used for latching the opcode
// This signal is set when in Control state and moving to TURN_ARND_0
// state

/*
always @(posedge reset or posedge mdc)
begin
   if (reset)
       latch_ctl <= 1'b0;
   else
      if (curr_state == CONTROL && next_state == TURN_ARND_0)
         latch_ctl <= 1'b1;
      else
         latch_ctl <= 1'b0;
end
*/

always @(cnt_eq_0 or curr_state)
    latch_ctl = cnt_eq_0 && (curr_state == CONTROL);
   
// Logic for incr_addr, incr_addr is set for opcode RD_INC_OP and
// after completely shifting out the read data for the current command

always @(posedge reset or posedge mdc)
begin
   if (reset)
       incr_addr <= 1'b0;
   else
      if (curr_state == ADDR_DATA && cnt_eq_0 &&
          opcode == RD_INC_OP)
          incr_addr <= 1'b1;
      else
          incr_addr <= 1'b0;
end


// Logic for shift addr, this bit is set when moving to ADDR_DATA 
// state and when in ADDR_DATA state for ADDR_OP command

always @(posedge reset or posedge mdc)
begin
   if (reset)
       shift_addr <= 1'b0;
   else
      if (next_state == ADDR_DATA && opcode == ADDR_OP)
         shift_addr <= 1'b1;
      else
         shift_addr <= 1'b0;
end

// Logic for mdio_wr, this bit is set when moving from ADDR_DATA to the
// IDLE for a WR_OP command
// Logic for mdio_rd, this bit is set when moving from ADDR_DATA to the
// IDLE for a RD_OP/RD_INC_OP command

always @(posedge reset or posedge mdc)
begin
   if (reset)
      begin
         mdio_wr <= 1'b0;
         mdio_rd <= 1'b0;
      end
   else
      if (curr_state == ADDR_DATA && cnt_eq_0)
         begin
            if (opcode == WR_OP)
               mdio_wr <= 1'b1;
            else
               mdio_wr <= 1'b0;
            if (opcode == RD_OP || opcode == RD_INC_OP)
               mdio_rd <= 1'b1;
            else
               mdio_rd <= 1'b0;
         end
      else
         begin
            mdio_wr <= 1'b0;
            mdio_rd <= 1'b0;
         end
end 


// Logic for ld_data, this signal is used for parallely loading the
// shift register in mdio_ctl_data module with the data from mdio_reg
// module. This set is set for RD_OP and RD_INC_OP commands when the
// SM transitions from TURN_ARND_0 to ADDR_DATA state
// assign ld_data_d = (curr_state == TURN_ARND_0 && (opcode == RD_OP | opcode == RD_INC_OP));

always @(posedge reset or posedge mdc)
begin
   if (reset)
       ld_data <= 1'b0;
   else
       ld_data <= (curr_state == TURN_ARND_0 && next_state == ADDR_DATA);
end


// Logic for ld_cnt, this signal is used for loading the down counter
// with cnt_val signal. This signal is set when going to
// CONTROL state or ADDR_DATA state or PREAMBLE states

always @(posedge reset or posedge mdc)
begin
   if (reset)
       ld_cnt <= 1'b0;
   else
      if ((curr_state == IDLE && next_state == PREAMBLE) ||
          (curr_state == ADDR_DATA && next_state == PREAMBLE) ||
          (curr_state == PREAMBLE && next_state == CONTROL) ||
          (curr_state == TURN_ARND_0 && next_state == ADDR_DATA) ||
          (curr_state == TURN_ARND_1 && next_state == ADDR_DATA) )
          ld_cnt <= 1'b1;
      else
          ld_cnt <= 1'b0;
end


// Logic for cnt_val, this counter value is used for sown counting
// the mdio_cnt, when the counter reaches zero, the cnt_eq_0 is
// set. The counter is loading with 31 for PREAMBLE, 13 for 
// CONTROL, and 15 for ADDR_DATA

always @(posedge reset or posedge mdc)
begin
   if (reset)
       cnt_val <= 5'b00000;
   else
      if ((curr_state == IDLE | curr_state == ADDR_DATA) && 
	 next_state == PREAMBLE)
          cnt_val <= 5'b11110;
      else if (curr_state == PREAMBLE && next_state == CONTROL)
          cnt_val <= 5'b01100;
      else if (curr_state == TURN_ARND_0 && next_state == ADDR_DATA)
          cnt_val <= 5'b01110;
      else if (curr_state == TURN_ARND_1 && next_state == ADDR_DATA)
          cnt_val <= 5'b01110;
      else
          cnt_val <= cnt_val;
end
      

endmodule


`timescale 1 ns / 1 ps

module arriagx_hssi_ctrl_reg (reset, mdio_wr, reg_addr, target_addr, clk, sig_in, 
                 ext_in, jtag_mode, si, shift, mdio_dis, sig_out, so);

input         reset;      // reset
input         mdio_wr;
input  [15:0] reg_addr;
input  [15:0] target_addr;
input         clk;        // clock
input  [15:0] sig_in;     // signal input
input  [15:0] ext_in;     // external port input
input         jtag_mode;  
input         si;         // scan input
input         shift;      // 1'b1=shift in data from si into scan flop
                          // 1'b0=load data from sig_in into scan flop
input         mdio_dis;   
                          // 1'b1=output CRAM
                          // 1'b0=output MDIO control register
output [15:0] sig_out;    // signal output
output        so;         // scan output

wire   [15:0] signal_in_int;
wire   [15:0] sig_out;
wire   [14:0] chain;
wire          so;

assign signal_in_int = (mdio_wr && (reg_addr == target_addr)) ? sig_in : {so, chain};

arriagx_hssi_bsc_in_r  bsc_in_r_0 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[0]), 
                      .ext_in (ext_in[0]), 
                      .jtag_mode (jtag_mode), 
                      .si (si), 
                      .shift (shift),
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[0]), 
                      .so (chain[0]));

arriagx_hssi_bsc_in_r  bsc_in_r_1 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[1]), 
                      .ext_in (ext_in[1]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[0]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[1]), 
                      .so (chain[1]));

arriagx_hssi_bsc_in_r  bsc_in_r_2 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[2]), 
                      .ext_in (ext_in[2]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[1]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[2]), 
                      .so (chain[2]));

arriagx_hssi_bsc_in_r  bsc_in_r_3 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[3]), 
                      .ext_in (ext_in[3]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[2]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[3]), 
                      .so (chain[3]));

arriagx_hssi_bsc_in_r  bsc_in_r_4 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[4]), 
                      .ext_in (ext_in[4]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[3]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[4]), 
                      .so (chain[4]));

arriagx_hssi_bsc_in_r  bsc_in_r_5 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[5]), 
                      .ext_in (ext_in[5]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[4]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[5]), 
                      .so (chain[5]));

arriagx_hssi_bsc_in_r  bsc_in_r_6 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[6]), 
                      .ext_in (ext_in[6]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[5]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[6]), 
                      .so (chain[6]));

arriagx_hssi_bsc_in_r  bsc_in_r_7 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[7]), 
                      .ext_in (ext_in[7]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[6]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[7]), 
                      .so (chain[7]));

arriagx_hssi_bsc_in_r  bsc_in_r_8 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[8]), 
                      .ext_in (ext_in[8]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[7]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[8]), 
                      .so (chain[8]));

arriagx_hssi_bsc_in_r  bsc_in_r_9 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[9]), 
                      .ext_in (ext_in[9]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[8]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[9]), 
                      .so (chain[9]));

arriagx_hssi_bsc_in_r  bsc_in_r_10 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[10]), 
                      .ext_in (ext_in[10]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[9]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[10]), 
                      .so (chain[10]));

arriagx_hssi_bsc_in_r  bsc_in_r_11 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[11]), 
                      .ext_in (ext_in[11]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[10]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[11]), 
                      .so (chain[11]));

arriagx_hssi_bsc_in_r  bsc_in_r_12 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[12]), 
                      .ext_in (ext_in[12]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[11]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[12]), 
                      .so (chain[12]));

arriagx_hssi_bsc_in_r  bsc_in_r_13 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[13]), 
                      .ext_in (ext_in[13]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[12]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[13]), 
                      .so (chain[13]));

arriagx_hssi_bsc_in_r  bsc_in_r_14 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[14]), 
                      .ext_in (ext_in[14]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[13]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[14]), 
                      .so (chain[14]));

arriagx_hssi_bsc_in_r  bsc_in_r_15 (.reset (reset), 
                      .clk (clk), 
                      .sig_in (signal_in_int[15]), 
                      .ext_in (ext_in[15]), 
                      .jtag_mode (jtag_mode), 
                      .si (chain[14]), 
                      .shift (shift), 
                      .mdio_dis (mdio_dis),     
                      .sig_out (sig_out[15]), 
                      .so (so));

endmodule


`timescale 1 ns / 1 ps

module arriagx_hssi_bsc_in_r (reset, clk, sig_in, ext_in, jtag_mode, si, shift, mdio_dis, sig_out, 
                so)/* synthesis ALTERA_ATTRIBUTE="{-to so} POWER_UP_LEVEL=LOW" */;

input        reset;      // reset
input        clk;        // clock
input        sig_in;     // signal input
input        ext_in;     // external input port
input        jtag_mode;  
input        si;         // scan input
input        shift;      // 1'b1=shift in data from si into scan flop
                         // 1'b0=load data from sig_in into scan flop
input        mdio_dis;   // 1'b1=choose ext_in to the sig_out mux
                         // 1'b0=choose so to the sign_out mux
output       sig_out;    // signal output
output       so;         // scan output


wire         sig_out;
wire         cram_int;
wire         set_int;
reg          so;

// select signal output
assign sig_out = (jtag_mode) ? (so & ~shift) : (cram_int);
assign cram_int = (mdio_dis) ? (ext_in) : (so);

// Set signal for the flop
assign set_int = (shift) ? 1'b0 : ext_in;

// scan flop
always @ (posedge reset or posedge set_int or posedge clk)
   if (reset)
      so <= 1'b0;
   else if (set_int)
      so <= 1'b1;
   else if (shift && jtag_mode)
      so <= si;
   else
      so <= sig_in;

endmodule

//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = lut 3 mux21 2 
`timescale 1 ps / 1 ps
module  arriagx_hssi_bsc_out
	( 
	clk,
	jtag_mode,
	reset,
	shift_load,
	si,
	sig_in,
	sig_out,
	so) /* synthesis synthesis_clearbox=1 */;
	input   clk;
	input   jtag_mode;
	input   reset;
	input   shift_load;
	input   si;
	input   sig_in;
	output   sig_out;
	output   so;

	reg	n1i1;
	reg	n1i2;
	reg	ni;
	wire	wire_nlO_CLRN;
	wire	wire_nl_dataout;
	wire	wire_nO_dataout;
	wire  nlOO;

	initial
		n1i1 = 0;
	always @ ( posedge clk)
		  n1i1 <= n1i2;
	event n1i1_event;
	initial
		#1 ->n1i1_event;
	always @(n1i1_event)
		n1i1 <= {1{1'b1}};
	initial
		n1i2 = 0;
	always @ ( posedge clk)
		  n1i2 <= n1i1;
	initial
	begin
		ni = 0;
	end
	always @ ( posedge clk or  negedge wire_nlO_CLRN)
	begin
		if (wire_nlO_CLRN == 1'b0) 
		begin
			ni <= 0;
		end
		else 
		begin
			ni <= wire_nl_dataout;
		end
	end
	assign
		wire_nlO_CLRN = ((n1i2 ^ n1i1) & (~ reset));
	assign		wire_nl_dataout = (shift_load === 1'b1) ? si : sig_in;
	assign		wire_nO_dataout = (jtag_mode === 1'b1) ? ni : sig_in;
	assign
		nlOO = 1'b1,
		sig_out = wire_nO_dataout,
		so = ni;
endmodule //arriagx_hssi_bsc_out
//synopsys translate_on
//VALID FILE

///////////////////////////////////////////////////////////////////////////////
// DPRIO INDEX TABLE --------------------------------------------------------//
///////////////////////////////////////////////////////////////////////////////

// make sure indices with _DP_ in the middle to distiguish from rx/tx

// page 8 - as POF used rclk_2 long ago
// both rx and tx
//assign  pcs_ctrl8_ch0_ext = {rfreerun_tx[0], rtxwrclksel[0], rtxrdclksel[0],
//801d-8020                  rfreerun_rx[0], rrcvd_clk_sel_ch0, 
//                           rclk_1_sel_ch0, rclk_2_sel_ch0, rrx_rd_clk_sel[0], 
//                           renumber_ch0, renpolinv_rx[0], rclkcmpinsertpad[0]};

`define rfreerun_rx_DP_RX_IDX       0    
`define rrx_rd_clk_sel_DP_RX_IDX    1    
`define renumber_DP_RX_IDX_0        2    
`define renumber_DP_RX_IDX_1        3    
`define renumber_DP_RX_IDX_2        4    
`define renpolinv_rx_DP_RX_IDX      5    
`define rclkcmpinsertpad_DP_RX_IDX  6  
  
`define rclk_1_sel_DP_RX_IDX_0      7
`define rclk_1_sel_DP_RX_IDX_1      8
`define rclk_2_sel_DP_RX_IDX_0      9
`define rclk_2_sel_DP_RX_IDX_1     10
`define rrcvd_clk_sel_DP_RX_IDX_0  11
`define rrcvd_clk_sel_DP_RX_IDX_1  12

// pma_ctrl6_ch0_ext = {rrefclk_sel_ch0, rbwctral_rx_ch0, rrx_cru_m_sel_ch0, 
// 8074h                rrx_cru_div2[0], rrx_cru_ctl_ch0, rltr[0], rltd[0]};
`define rrx_cru_m_sel_DP_RX_IDX_0  13
`define rrx_cru_m_sel_DP_RX_IDX_1  14
`define rrx_cru_div2_DP_RX_IDX     15
`define rltr_DP_RX_IDX             16
`define rltd_DP_RX_IDX             17

// pma_ctrl7_ch0_ext = {risel_rx_ch0, riupsel_rx_ch0, ridnsel_rx_ch0,
// 8078h               rtesten_cp_rx[0], rtristate_cp_rx[0], rtestupen_cp_rx[0],
//                     rtestdnen_cp_rx[0], rrx_cru_m_ch0, rrx_cru_l_ch0};
// last two from pma_ctrl4 documented in tx side
// pma_ctrl7_ch0_ext = {risel_rx_ch0, riupsel_rx_ch0, ridnsel_rx_ch0,
// 8078h               rtesten_cp_rx[0], rtristate_cp_rx[0], rtestupen_cp_rx[0],
//                     rtestdnen_cp_rx[0], rrx_cru_m_ch0, rrx_cru_l_ch0};
// last two from pma_ctrl4 documented in tx side
`define rrx_cru_m_DP_RX_IDX_0      18
`define rrx_cru_m_DP_RX_IDX_1      19
`define rrx_cru_m_DP_RX_IDX_2      20
`define rrx_cru_m_DP_RX_IDX_3      21
`define rrx_cru_l_DP_RX_IDX_0      22
`define rrx_cru_l_DP_RX_IDX_1      23
`define rpmadwidth_rx_DP_RX_IDX    24
`define rpma_doublewidth_rx_DP_RX_IDX 25

// next 32 indices are used for RX_PMA prior to 6.1 for backward compatibility
// RX_PMA_ST =                     26
// RX_PMA_ED =                     58

// PMA_2
//assign  pma_ctrl2_ch0_ext = {rtx_term_ch0, r_tx_det_rx_ch0, rrx_term_ch0, rforce_sigdet[0],
//                             rrx_dc_couple[0], rrx_eq_dc_ch0, rrx_vtt_ch0, rrx_sloslv_ch0};
`define rtx_term_DP_RX_IDX_0       26
`define rtx_term_DP_RX_IDX_1       27
`define r_tx_det_rx_DP_RX_IDX_0    28
`define r_tx_det_rx_DP_RX_IDX_1    29
`define rrx_term_DP_RX_IDX_0       30
`define rrx_term_DP_RX_IDX_1       31
`define rforce_sigdet_DP_RX_IDX    32
`define rrx_dc_couple_DP_RX_IDX    33
`define rrx_eq_dc_DP_RX_IDX_0      34
`define rrx_eq_dc_DP_RX_IDX_1      35
`define rrx_vtt_DP_RX_IDX_0        36
`define rrx_vtt_DP_RX_IDX_2        38
`define rrx_sloslv_DP_RX_IDX_0     39
`define rrx_sloslv_DP_RX_IDX_2     41

// PMA_3                             
//assign  pma_ctrl3_ch0_ext = {reqa_ct_ch0, reqb_ct_ch0, reqc_ct_ch0, reqd_ct_ch0, req_ctv_ch0, 1'b0};
`define reqa_ct_DP_RX_IDX_0        42
`define reqa_ct_DP_RX_IDX_2        44
`define reqb_ct_DP_RX_IDX_0        45
`define reqb_ct_DP_RX_IDX_2        47
`define reqc_ct_DP_RX_IDX_0        48
`define reqc_ct_DP_RX_IDX_2        50
`define reqd_ct_DP_RX_IDX_0        51
`define reqd_ct_DP_RX_IDX_2        53
`define req_ctv_DP_RX_IDX_0        54
`define req_ctv_DP_RX_IDX_2        56


// rx - 4
//assign  trunking_mode_ext = {1'b0, rphfifo_master_sel_tx, rphfifo_master_sel_rx, 
// 8000h same for all ch       rendec_data_sel_tx, rendec_data_sel_rx, rnenbpin, rpllurst, 
//                             rreset, rrsvd_cmu, rdeskewen, rindv_tx, rindv_rx};
`define rphfifo_master_sel_rx_DP_RX_IDX    59
`define rendec_data_sel_rx_DP_RX_IDX       60
`define rdeskewen_DP_RX_IDX                61
`define rindv_rx_DP_RX_IDX                 62

// page divided into both rx and tx
// pcs_ctrl1_ch0_ext = {rtx_pipe_enable[0], rrx_pipe_enable[0], rpowdnr[0], rpowdnt[0],
// 8001-8004            rendec_tx[0], rendec_rx[0], r8b10b_enc_ibm_en[0], rmatchen[0],
//                      r8b10b_dec_ibm_en_ch0, rforce_kchar[0], rforce_echar[0],
//                      rlp20ben[0], rgenericfifo[0], rcascaded_8b10b_en_tx[0],
//                      rcascaded_8b10b_en_rx[0]};
`define rrx_pipe_enable_DP_RX_IDX          63
`define rpowdnr_DP_RX_IDX                  64
`define rendec_rx_DP_RX_IDX                65
`define rmatchen_DP_RX_IDX                 66
`define r8b10b_dec_ibm_en_DP_RX_IDX_0      67
`define r8b10b_dec_ibm_en_DP_RX_IDX_1      68
`define rlp20ben_DP_RX_IDX                 69
`define rgenericfifo_DP_RX_IDX             70
`define rcascaded_8b10b_en_rx_DP_RX_IDX    71

// all rx - 14
//assign  pcs_ctrl2_ch0_ext = {resync_badcg_en_ch0, rencdt_rising[0], rdis_rx_disp[0],
// 8005-8008                   rcomp_pat_porn[0], rcomp_size_ch0, rcomp_pat_ch0[39:32]};
`define rencdt_rising_DP_RX_IDX            72
`define rdis_rx_disp_DP_RX_IDX             73
`define rcomp_pat_porn_DP_RX_IDX           74
`define rcomp_size_DP_RX_IDX_0             75
`define rcomp_size_DP_RX_IDX_2             77

// page 3 + 4 - all rx - 32
//assign  pcs_ctrl3_ch0_ext = {rcomp_pat_ch0[31:16]};
// 8009-800c
//assign  pcs_ctrl4_ch0_ext = {rcomp_pat_ch0[15:0]};
// 800d-8010
`define rcomp_pat_DP_RX_IDX_0              78
`define rcomp_pat_DP_RX_IDX_39             117

// rx - 12
//assign  pcs_ctrl5_ch0_ext = {rrxfifo_dis[0], rtxfifo_dis[0], rib_force_disp[0],
//8011-8014                  rrundisp_ch0, rtxfifo_lowlatency_en[0], rrlv_en[0], rautobtalg_dis[0],
//                           rsync_sm_dis[0], rib_inv_cd_ch0, rrxfifo_lowlatency_en[0]};
`define rrxfifo_dis_DP_RX_IDX              118
`define rrundisp_DP_RX_IDX_0               119
`define rrundisp_DP_RX_IDX_5               124
`define rrlv_en_DP_RX_IDX                  125
`define rautobtalg_dis_DP_RX_IDX           126
`define rsync_sm_dis_DP_RX_IDX             127
`define rib_inv_cd_DP_RX_IDX_0             128
`define rib_inv_cd_DP_RX_IDX_1             129
`define rrxfifo_lowlatency_en_DP_RX_IDX    130

// rx - 8
//assign  pcs_ctrl6_ch0_ext = {rdwidth_tx[0], rdwidth_rx[0], rge_xaui_tx[0],
// 8015 - 8018                 rrx_detect_bypass[0], rtxurstpcs[0], rrxurstpcs[0],
//                             rrsvd_tx_ch0, rskpsetbased[0], rtruebac2bac[0],rrsvd_rx_ch0};
//
`define rdwidth_rx_DP_RX_IDX               133         
`define rrx_detect_bypass_DP_RX_IDX        134        
`define rrxurstpcs_DP_RX_IDX               135        
`define rskpsetbased_DP_RX_IDX             136        
`define rtruebac2bac_DP_RX_IDX             137        
`define rrsvd_rx_DP_RX_IDX_0               138        
`define rrsvd_rx_DP_RX_IDX_1               139        
`define rrsvd_rx_DP_RX_IDX_2               140       

// all rx   - 16                          
//assign  pcs_ctrl7_ch0_ext = {rgnumber_ch0, rknumber_ch0};
// 8018 - 801c
`define rgnumber_DP_RX_IDX_0               141
`define rgnumber_DP_RX_IDX_7               148
`define rknumber_DP_RX_IDX_0               149
`define rknumber_DP_RX_IDX_7               156

// page 8 of rx moved to first as POF used rclk_2 long ago
//assign  pcs_ctrl8_ch0_ext = {rfreerun_tx[0], rtxwrclksel[0], rtxrdclksel[0],
//801d-8020                  rfreerun_rx[0], rrcvd_clk_sel_ch0, 
//                           rclk_1_sel_ch0, rclk_2_sel_ch0, rrx_rd_clk_sel[0], 
//                           renumber_ch0, renpolinv_rx[0], rclkcmpinsertpad[0]};

// all rx   - 26
//assign  pcs_ctrl9_ch0_ext = {rppm_cnt_reset[0], rphfifourstrx[0], rcmpfifourst[0], 
// 8025 - 8028                 rtx_idle_delay_ch0, rclkcmpsqmd[0], rclkcmpsq1p_ch0[9:0]};
`define rppm_cnt_reset_DP_RX_IDX           157
`define rphfifourstrx_DP_RX_IDX            158
`define rcmpfifourst_DP_RX_IDX             159
`define rtx_idle_delay_DP_RX_IDX_0         160
`define rtx_idle_delay_DP_RX_IDX_1         161
`define rclkcmpsqmd_DP_RX_IDX              162
`define rclkcmpsq1p_DP_RX_IDX_0            163
`define rclkcmpsq1p_DP_RX_IDX_19           182

// all rx - pages 10 and 11 - 21
// 8029 - 802C
//assign  pcs_ctrl10_ch0_ext = {rclkcmpsq1n_ch0[19:15], rclkcmppos[0], rclkcmpsq1p_ch0[19:10]};
// 802D - 8030
//assign  pcs_ctrl11_ch0_ext = {rclkcmpsq1n_ch0[14:10], 1'b0, rclkcmpsq1n_ch0[9:0]};
`define rclkcmpsq1n_DP_RX_IDX_0           183
`define rclkcmpsq1n_DP_RX_IDX_19          202
`define rclkcmppos_DP_RX_IDX              203

// page 12 - rx: 12
//assign  pcs_ctrl12_ch0_ext = {rrev_loopbk[0], ralempty_ch0, ralfull_ch0, rforce_disp[0], 
//                              rkchar[0], rosbased[0], rensymswap_tx[0], 1'b0, rosnumber_ch0};
`define ralempty_DP_RX_IDX_0              204
`define ralempty_DP_RX_IDX_3              207
`define ralfull_DP_RX_IDX_0               208
`define ralfull_DP_RX_IDX_3               211
`define rkchar_DP_RX_IDX                  212
`define rosbased_DP_RX_IDX                213
`define rosnumber_DP_RX_IDX_0             214
`define rosnumber_DP_RX_IDX_1             215

// page 13 - rx: 12
//assign  pcs_ctrl13_ch0_ext = {rwa_6g_en[0], renpolinv_tx[0], rbitslip_size_ch0, rbytord_2sym_en[0],
//                              rbysync_polinv_en[0], rbitloc_rev_en[0], rbyte_rev_en[0], renbitrev_tx[0],
//                              rbyteorden_ch0, rbytordplden[0], rphfifopldentx[0], rphfifoursttx[0],
//                              rphfifopldenrx[0], rautoinsdis[0]};
`define rwa_6g_en_DP_RX_IDX               216
`define rbitslip_size_DP_RX_IDX_0         217
`define rbitslip_size_DP_RX_IDX_1         218
`define rbytord_2sym_en_DP_RX_IDX         219
`define rbysync_polinv_en_DP_RX_IDX       220
`define rbitloc_rev_en_DP_RX_IDX          221
`define rbyte_rev_en_DP_RX_IDX            222
`define rbyteorden_DP_RX_IDX_0            223
`define rbyteorden_DP_RX_IDX_1            224
`define rbytordplden_DP_RX_IDX            225
`define rphfifopldenrx_DP_RX_IDX          226
`define rautoinsdis_DP_RX_IDX             227


// page 14 - all rx
//assign  pcs_ctrl14_ch0_ext = {rppmsel_ch0, rbytordpat_ch0};
`define rppmsel_DP_RX_IDX_0               228
`define rppmsel_DP_RX_IDX_5               233
`define rbytordpat_DP_RX_IDX_0            234
`define rbytordpat_DP_RX_IDX_9            243

// page 15
//assign  pcs_ctrl15_ch0_ext = {rtest_bus_sel_ch0, rforce_sig_det_pcs[0], rforce0_freqdet[0], 
//                              rforce1_freqdet[0], rbytordpad_ch0};
`define test_bus_sel_DP_RX_IDX_0          244
`define test_bus_sel_DP_RX_IDX_2          246
`define rforce_sig_det_pcs_DP_RX_IDX      247
`define rforce0_freqdet_DP_RX_IDX         248
`define rforce1_freqdet_DP_RX_IDX         249
`define rbytordpad_DP_RX_IDX_0            250
`define rbytordpad_DP_RX_IDX_9            259

// pma_ctrl8: 4.807c-807h - RX portion
//assign  pma_ctrl8_ch0_ext = {rs_lpbk[0], r_rlpbk[0], rs_rdlpbk[0], rrx_revlb_sw[0],
//                             rurx_pdb[0], rtx_cgb_pdb[0], rtx_ob_pdb[0], rrx_cru_pdb[0],
//                             rrx_cru_rst[0], rrx_ib_pdb[0], rrxurstpma[0], radce_adapt[0],
//                             radce_pdb[0], radce_rst[0], rsig_inv_2tap[0], rsig_inv_pre[0]};
`define rs_lpbk_DP_RX_IDX                 260
`define rrx_revlb_sw_DP_RX_IDX            261

// cru_clock_select index - SW twisted
`define cru_clock_select_DP_RX_IDX_0      262
`define cru_clock_select_DP_RX_IDX_1      263
`define cru_clock_select_DP_RX_IDX_2      264
`define cru_clock_select_DP_RX_IDX_3      265

// passing reconfig clock to RX ADCE
`define reconfig_clk_DP_RX_IDX            299

// MAX = 299

// The address covers both rx(pma and dpma widths defined in RX) and tx
// pma_ctrl4_ch0_ext = {rpmadwidth_tx[0], rpma_doublewidth_tx[0], rtx_cmu_sel[0],
// 806Ch                rtx_m_sel_ch0, rtxvcobypass[0], rtx_cgb_1x_en[0], rtx_cgb_4x_en[0],
//                      rtx_4x_sw[0], rpmadwidth_rx[0], rpma_doublewidth_rx[0],
//                      rrxvcobypass[0],rrect_adj_ch0, rrx_piso_bypass_ch0};
`define rtx_cmu_sel_DP_TX_IDX              9
`define rpmadwidth_tx_DP_TX_IDX            10
`define rpma_doublewidth_tx_DP_TX_IDX      11
`define rtx_m_sel_DP_TX_IDX_0              12
`define rtx_m_sel_DP_TX_IDX_1              13
`define rtx_cgb_1x_en_DP_TX_IDX            14
`define rtx_cgb_4x_en_DP_TX_IDX            15
`define rtx_4x_sw_DP_TX_IDX                16


// tx - 3
//assign  trunking_mode_ext = {1'b0, rphfifo_master_sel_tx, rphfifo_master_sel_rx, 
// 8000h same for all ch       rendec_data_sel_tx, rendec_data_sel_rx, rnenbpin, rpllurst, 
//                             rreset, rrsvd_cmu, rdeskewen, rindv_tx, rindv_rx};
`define rphfifo_master_sel_tx_DP_TX_IDX    20
`define rendec_data_sel_tx_DP_TX_IDX       21
`define rindv_tx_DP_TX_IDX                 22

// page divided into both rx and tx
// pcs_ctrl1_ch0_ext = {rtx_pipe_enable[0], rrx_pipe_enable[0], rpowdnr[0], rpowdnt[0],
// 8001-8004            rendec_tx[0], rendec_rx[0], r8b10b_enc_ibm_en[0], rmatchen[0],
//                      r8b10b_dec_ibm_en_ch0, rforce_kchar[0], rforce_echar[0],
//                      rlp20ben[0], rgenericfifo[0], rcascaded_8b10b_en_tx[0],
//                      rcascaded_8b10b_en_rx[0]};
`define rtx_pipe_enable_DP_TX_IDX          25
`define rpowdnt_DP_TX_IDX                  26
`define rendec_tx_DP_TX_IDX                27
`define r8b10b_enc_ibm_en_DP_TX_IDX        28
`define rforce_kchar_DP_TX_IDX             29
`define rforce_echar_DP_TX_IDX             30
`define rcascaded_8b10b_en_tx_DP_TX_IDX    31

// tx - 3
//assign  pcs_ctrl5_ch0_ext = {rrxfifo_dis[0], rtxfifo_dis[0], rib_force_disp[0],
//8011-8014                  rrundisp_ch0, rtxfifo_lowlatency_en[0], rrlv_en[0], rautobtalg_dis[0],
//                           rsync_sm_dis[0], rib_inv_cd_ch0, rrxfifo_lowlatency_en[0]};
`define rtxfifo_dis_DP_TX_IDX              34
`define rib_force_disp_DP_TX_IDX           35
`define rtxfifo_lowlatency_en_DP_TX_IDX    36

//assign  pcs_ctrl6_ch0_ext = {rdwidth_tx[0], rdwidth_rx[0], rge_xaui_tx[0],
// 8015 - 8018                 rrx_detect_bypass[0], rtxurstpcs[0], rrxurstpcs[0],
//                             rrsvd_tx_ch0, rskpsetbased[0], rtruebac2bac[0],rrsvd_rx_ch0};
//
`define rdwidth_tx_DP_TX_IDX               37
`define rge_xaui_tx_DP_TX_IDX              38
`define rtxurstpcs_DP_TX_IDX               39
`define rrsvd_tx_DP_TX_IDX_0               40
`define rrsvd_tx_DP_TX_IDX_4               44

// page 7 PCS - all rx

// page 8 of rx moved to first as POF used rclk_2 long ago
//assign  pcs_ctrl8_ch0_ext = {rfreerun_tx[0], rtxwrclksel[0], rtxrdclksel[0],
//801d-8020                  rfreerun_rx[0], rrcvd_clk_sel_ch0, 
//                           rclk_1_sel_ch0, rclk_2_sel_ch0, rrx_rd_clk_sel[0], 
//                           renumber_ch0, renpolinv_rx[0], rclkcmpinsertpad[0]};
`define rfreerun_tx_DP_TX_IDX              47
`define rtxwrclksel_DP_TX_IDX              48
`define rtxrdclksel_DP_TX_IDX              49

// page 12 - tx: 3
//assign  pcs_ctrl12_ch0_ext = {rrev_loopbk[0], ralempty_ch0, ralfull_ch0, rforce_disp[0], 
//                              rkchar[0], rosbased[0], rensymswap_tx[0], 1'b0, rosnumber_ch0};
`define rrev_loopbk_DP_TX_IDX              50
`define rforce_disp_DP_TX_IDX              51
`define rensymswap_tx_DP_TX_IDX            52

// page 13 - tx: 4
//assign  pcs_ctrl13_ch0_ext = {rwa_6g_en[0], renpolinv_tx[0], rbitslip_size_ch0, rbytord_2sym_en[0],
//                              rbysync_polinv_en[0], rbitloc_rev_en[0], rbyte_rev_en[0], renbitrev_tx[0],
//                              rbyteorden_ch0, rbytordplden[0], rphfifopldentx[0], rphfifoursttx[0],
//                              rphfifopldenrx[0], rautoinsdis[0]};
`define renpolinv_tx_DP_TX_IDX             54
`define renbitrev_tx_DP_TX_IDX             55
`define rphfifopldentx_DP_TX_IDX           56
`define rphfifoursttx_DP_TX_IDX            57

// pma 1 - tx
//assign  pma_ctrl1_ch0_ext = {rtx_vod_sel_ch0, rtx_slewrate[0], rpmphs_2tap_ch0,
//                             rpmphs_1tap_ch0, rtx_vtt_ch0, rpmphs_ptap_ch0};
`define rtx_vod_sel_DP_TX_IDX_0            60
`define rtx_vod_sel_DP_TX_IDX_2            62
`define rtx_slewrate_DP_TX_IDX             63
`define rpmphs_2tap_DP_TX_IDX_0            64
`define rpmphs_2tap_DP_TX_IDX_2            66
`define rpmphs_1tap_DP_TX_IDX_0            67
`define rpmphs_1tap_DP_TX_IDX_3            70
`define rtx_vtt_DP_TX_IDX_0                71
`define rtx_vtt_DP_TX_IDX_1                72
`define rpmphs_ptap_DP_TX_IDX_0            73
`define rpmphs_ptap_DP_TX_IDX_2         75

// pma_ctrl8: 4.807c-807h - TX portion
//assign  pma_ctrl8_ch0_ext = {rs_lpbk[0], r_rlpbk[0], rs_rdlpbk[0], rrx_revlb_sw[0],
//                             rurx_pdb[0], rtx_cgb_pdb[0], rtx_ob_pdb[0], rrx_cru_pdb[0],
//                             rrx_cru_rst[0], rrx_ib_pdb[0], rrxurstpma[0], radce_adapt[0],
//                             radce_pdb[0], radce_rst[0], rsig_inv_2tap[0], rsig_inv_pre[0]};
`define r_rlpbk_DP_TX_IDX                  76
`define rs_rdlpbk_DP_TX_IDX                77
`define rsig_inv_2tap_DP_TX_IDX            78
`define rsig_inv_pre_DP_TX_IDX             79


// tx_max = 149 ------------------------------------------------------------------------

// Global Trunk 
// PMA_GLOBAL_CTRL_4
// assign  pma_global_ctrl4_ext = {rcmu0_m, rcmu1_m, rcmu0_l, rcmu1_l, rcmu0_pdb, rcmu1_pdb,
//                                rcmu0_txpll_rst, rcmu1_txpll_rst};

`define rcmu_m_DP_CMUPLL_IDX_0            0
`define rcmu_m_DP_CMUPLL_IDX_7            7
`define rcmu_l_DP_CMUPLL_IDX_0            8
`define rcmu_l_DP_CMUPLL_IDX_7            15
`define rcmu_pdb_DP_CMUPLL_IDX            16
`define rcmu_txpll_rst_DP_CMUPLL_IDX      17
`define refclk_select_DP_CMUPLL_IDX_0     18
`define refclk_select_DP_CMUPLL_IDX_1     19
`define refclk_select_DP_CMUPLL_IDX_2     20
`define refclk_select_DP_CMUPLL_IDX_3     21

// global to CMU PCS
/*
assign  pcs_global_ctrl0_ext = {9'b000000000, ralgnect, ralgngct, ralgnact};
assign  pcs_global_ctrl1_ext = {rfreerun_centrl, rcentrl_clk_sel, 2'b00, rrefclk_out_div2, rdskposdisp, rdskchrp};
assign  pcs_global_ctrl2_ext = {2'b00, ralgnopt, rtest_bus_centrl_sel, 10'b0000000000};
*/

// make sure indices with _DP_ in the middle to distiguish from rx/tx

// index to the PHYSICAL lines of CRU_CLOCK_SELECT ----------------------------------------
`define CRU_CLOCK_SELECT_NONE              0
`define CRU_CLOCK_SELECT_REFCLK0           1
`define CRU_CLOCK_SELECT_REFCLK1           2
`define CRU_CLOCK_SELECT_IQ0               3
`define CRU_CLOCK_SELECT_IQ1               4
`define CRU_CLOCK_SELECT_IQ2               5
`define CRU_CLOCK_SELECT_IQ3               6
`define CRU_CLOCK_SELECT_IQ4               7
`define CRU_CLOCK_SELECT_PLD_CRU_CLK       8
`define CRU_CLOCK_SELECT_CMU_DIV_CLK       9

// index to the PHYSICAL lines of CMUPLL refclk select ------------------------------------
`define CMUPLL_CLOCK_SELECT_IQ0            0
`define CMUPLL_CLOCK_SELECT_IQ1            1
`define CMUPLL_CLOCK_SELECT_IQ2            2
`define CMUPLL_CLOCK_SELECT_IQ3            3
`define CMUPLL_CLOCK_SELECT_IQ4            4
`define CMUPLL_CLOCK_SELECT_PLD_CLK        5
`define CMUPLL_CLOCK_SELECT_REFCLK0        6
`define CMUPLL_CLOCK_SELECT_REFCLK1        7
`define CMUPLL_CLOCK_SELECT_ERR            8


`timescale 1 ps / 1 ps
module arriagx_hssi_cmu_dprio_reg ( 
    mdc,       
    mdio_rst,
    mdio_dis,
    dprioload,
    align_status,
    sync_status,
    reg_addr,
    mdio_wr,      
    mdio_rd,
    dev_addr_0,
    mbus_in,
                        
    cmudividerdprioin,
    cmuplldprioin,
    cmudprioin,
    refclkdividerdprioin,
    rxdprioin,
    txdprioin,
           
    cmudividerdprioout,
    cmuplldprioout,
    cmudprioout,
    refclkdividerdprioout,
    rxdprioout,
    txdprioout,
            		            
    mbus_out
);            
parameter rx_dprio_width = 800;                     // 6.1
parameter tx_dprio_width = 400;                     // 6.1

input         mdc;                  
input         mdio_rst;   
input         mdio_dis;  // 1'b1=output CRAM (para), 1'b0=output MDIO control register
input         dprioload; // load MDIO control register with CRAM_ext (parameter). SER_SHFIT_LOAD?
input         align_status;
input [3:0]   sync_status;

input [15:0]  reg_addr;
input         mdio_wr;
input         mdio_rd;
input         dev_addr_0;
input [15:0]  mbus_in;

input [29:0]  cmudividerdprioin;
input [119:0] cmuplldprioin;
input [29:0]  cmudprioin;
input [1:0]   refclkdividerdprioin;
input [rx_dprio_width - 1 : 0] rxdprioin;
input [tx_dprio_width - 1 : 0] txdprioin;

output [29:0]  cmudividerdprioout;
output [119:0] cmuplldprioout;
output [29:0]  cmudprioout;
output [1:0]   refclkdividerdprioout;
output [rx_dprio_width - 1 : 0] rxdprioout;
output [tx_dprio_width - 1 : 0] txdprioout;

output [15:0]  mbus_out;

// temporary wire names to break long tinery stats
wire [15:0] mbusout_s1,mbusout_s2;

// external parameters

parameter rx0_phy = 0;
parameter rx1_phy = 1;
parameter rx2_phy = 2;
parameter rx3_phy = 3;

parameter tx0_phy = 0;
parameter tx1_phy = 1;
parameter tx2_phy = 2;
parameter tx3_phy = 3;

parameter rx0_cru_clock0_physical_mapping = "refclk0"; 
parameter rx0_cru_clock1_physical_mapping = "refclk1"; 
parameter rx0_cru_clock2_physical_mapping = "iq0"; 
parameter rx0_cru_clock3_physical_mapping = "iq1"; 
parameter rx0_cru_clock4_physical_mapping = "iq2"; 
parameter rx0_cru_clock5_physical_mapping = "iq3"; 
parameter rx0_cru_clock6_physical_mapping = "iq4"; 
parameter rx0_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx0_cru_clock8_physical_mapping = "cmu_div_clk";
parameter rx1_cru_clock0_physical_mapping = "refclk0"; 
parameter rx1_cru_clock1_physical_mapping = "refclk1"; 
parameter rx1_cru_clock2_physical_mapping = "iq0"; 
parameter rx1_cru_clock3_physical_mapping = "iq1"; 
parameter rx1_cru_clock4_physical_mapping = "iq2"; 
parameter rx1_cru_clock5_physical_mapping = "iq3"; 
parameter rx1_cru_clock6_physical_mapping = "iq4"; 
parameter rx1_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx1_cru_clock8_physical_mapping = "cmu_div_clk";
parameter rx2_cru_clock0_physical_mapping = "refclk0"; 
parameter rx2_cru_clock1_physical_mapping = "refclk1"; 
parameter rx2_cru_clock2_physical_mapping = "iq0"; 
parameter rx2_cru_clock3_physical_mapping = "iq1"; 
parameter rx2_cru_clock4_physical_mapping = "iq2"; 
parameter rx2_cru_clock5_physical_mapping = "iq3"; 
parameter rx2_cru_clock6_physical_mapping = "iq4"; 
parameter rx2_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx2_cru_clock8_physical_mapping = "cmu_div_clk";
parameter rx3_cru_clock0_physical_mapping = "refclk0"; 
parameter rx3_cru_clock1_physical_mapping = "refclk1"; 
parameter rx3_cru_clock2_physical_mapping = "iq0"; 
parameter rx3_cru_clock3_physical_mapping = "iq1"; 
parameter rx3_cru_clock4_physical_mapping = "iq2"; 
parameter rx3_cru_clock5_physical_mapping = "iq3"; 
parameter rx3_cru_clock6_physical_mapping = "iq4"; 
parameter rx3_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx3_cru_clock8_physical_mapping = "cmu_div_clk";

parameter tx0_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx0_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx1_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx1_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx2_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx2_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx3_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx3_pll_fast_clk1_physical_mapping = "pll1"; 

// cmupll
parameter pll0_phy = 0;
parameter pll1_phy = 1;
parameter pll2_phy = 2;

parameter pll0_inclk0_logical_to_physical_mapping = "iq0";
parameter pll0_inclk1_logical_to_physical_mapping = "iq1";
parameter pll0_inclk2_logical_to_physical_mapping = "iq2";
parameter pll0_inclk3_logical_to_physical_mapping = "iq3";
parameter pll0_inclk4_logical_to_physical_mapping = "iq4";
parameter pll0_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll0_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll0_inclk7_logical_to_physical_mapping = "clkrefclk1";
parameter pll1_inclk0_logical_to_physical_mapping = "iq0";
parameter pll1_inclk1_logical_to_physical_mapping = "iq1";
parameter pll1_inclk2_logical_to_physical_mapping = "iq2";
parameter pll1_inclk3_logical_to_physical_mapping = "iq3";
parameter pll1_inclk4_logical_to_physical_mapping = "iq4";
parameter pll1_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll1_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll1_inclk7_logical_to_physical_mapping = "clkrefclk1";
parameter pll2_inclk0_logical_to_physical_mapping = "iq0";
parameter pll2_inclk1_logical_to_physical_mapping = "iq1";
parameter pll2_inclk2_logical_to_physical_mapping = "iq2";
parameter pll2_inclk3_logical_to_physical_mapping = "iq3";
parameter pll2_inclk4_logical_to_physical_mapping = "iq4";
parameter pll2_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll2_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll2_inclk7_logical_to_physical_mapping = "clkrefclk1";

// DEBUG dump
parameter sim_dump_dprio_internal_reg_at_time = 0; // in ps
parameter sim_dump_filename = "sim_dprio_dump.txt";

// begin of CMUPLL
function [3:0] convert_cmupll_m_in_to_cram;
input [7:0] tmp_cmupll_m;
reg   [3:0] res;
begin
    if (tmp_cmupll_m == 8'd25)
        res = 4'b1000;
    else if (tmp_cmupll_m == 8'd20) 
        res = 4'b0111;
    else if (tmp_cmupll_m == 8'd16) 
        res = 4'b0110;
    else if (tmp_cmupll_m == 8'd10) 
        res = 4'b0101;
    else if (tmp_cmupll_m == 8'd8)  
        res = 4'b0100;
    else if (tmp_cmupll_m == 8'd5)  
        res = 4'b0011;
    else if (tmp_cmupll_m == 8'd4)  
        res = 4'b0010;
    else if (tmp_cmupll_m == 8'd1)  
        res = 4'b0000;
    else
        res = 4'b1111;  // illegal value on purpose
                     
    convert_cmupll_m_in_to_cram = res;
end
endfunction

function [1:0] convert_cmupll_l_in_to_cram;
input [7:0] tmp_cmupll_l;
reg   [1:0] res;
begin
    if (tmp_cmupll_l == 8'd1)
        res = 2'b00;
    else if (tmp_cmupll_l == 8'd2) 
        res = 2'b01;
    else if (tmp_cmupll_l == 8'd4) 
        res = 2'b10;
    else
        res = 2'b11;  // illegal value on purpose
                     
    convert_cmupll_l_in_to_cram = res;
end
endfunction

function [7:0] convert_cram_to_cmupll_m_out;
input [3:0] tmp_cmupll_m;
reg   [7:0] res;
begin
    if (tmp_cmupll_m == 4'b1000)
        res = 8'd25;
    else if (tmp_cmupll_m == 4'b0111) 
        res = 8'd20;
    else if (tmp_cmupll_m == 4'b0110) 
        res = 8'd16;
    else if (tmp_cmupll_m == 4'b0101) 
        res = 8'd10;
    else if (tmp_cmupll_m == 4'b0100)  
        res = 8'd8;
    else if (tmp_cmupll_m == 4'b0011)  
        res = 8'd5;
    else if (tmp_cmupll_m == 4'b0010)  
        res = 8'd4;
    else if (tmp_cmupll_m == 4'b0000)  
        res = 8'd1;
    else
        res = 8'd1;
                     
    convert_cram_to_cmupll_m_out = res;
end
endfunction

function [7:0] convert_cram_to_cmupll_l_out;
input [1:0] tmp_cmupll_l;
reg   [7:0] res;
begin
    if (tmp_cmupll_l == 2'b00)
        res = 8'd1;
    else if (tmp_cmupll_l == 2'b01) 
        res = 8'd2;
    else if (tmp_cmupll_l == 2'b10) 
        res = 8'd4;
    else
        res = 8'd1;
                     
    convert_cram_to_cmupll_l_out = res;
end
endfunction

// slight difference of refclk on pll0 and pll1
function [4:0] convert_cmupll0_clock_cram_to_phyport;
input [1:0] rrefclk_sel;
input [2:0] pldiq;
reg [4:0]   res;
begin
    if (rrefclk_sel == 2'b00)
        res = `CMUPLL_CLOCK_SELECT_REFCLK0;
    else if (rrefclk_sel == 2'b01)
        res = `CMUPLL_CLOCK_SELECT_REFCLK1;
    else if (pldiq == 3'b000)
        res = `CMUPLL_CLOCK_SELECT_IQ0;
    else if (pldiq == 3'b001)
        res = `CMUPLL_CLOCK_SELECT_IQ1;
    else if (pldiq == 3'b010)
        res = `CMUPLL_CLOCK_SELECT_IQ2;
    else if (pldiq == 3'b011)
        res = `CMUPLL_CLOCK_SELECT_IQ3;
    else if (pldiq == 3'b100)
        res = `CMUPLL_CLOCK_SELECT_IQ4;
    else if (pldiq == 3'b101)
        res = `CMUPLL_CLOCK_SELECT_PLD_CLK;
    else
        res = `CMUPLL_CLOCK_SELECT_ERR;
    
    convert_cmupll0_clock_cram_to_phyport = res;
end
endfunction

function [4:0] convert_cmupll1_clock_cram_to_phyport;
input [1:0] rrefclk_sel;
input [2:0] pldiq;
reg [4:0]   res;
begin
    if (rrefclk_sel == 2'b00)
        res = `CMUPLL_CLOCK_SELECT_REFCLK1;
    else if (rrefclk_sel == 2'b01)
        res = `CMUPLL_CLOCK_SELECT_REFCLK0;
    else if (pldiq == 3'b000)
        res = `CMUPLL_CLOCK_SELECT_IQ0;
    else if (pldiq == 3'b001)
        res = `CMUPLL_CLOCK_SELECT_IQ1;
    else if (pldiq == 3'b010)
        res = `CMUPLL_CLOCK_SELECT_IQ2;
    else if (pldiq == 3'b011)
        res = `CMUPLL_CLOCK_SELECT_IQ3;
    else if (pldiq == 3'b100)
        res = `CMUPLL_CLOCK_SELECT_IQ4;
    else if (pldiq == 3'b101)
        res = `CMUPLL_CLOCK_SELECT_PLD_CLK;
    else
        res = `CMUPLL_CLOCK_SELECT_ERR;
    
    convert_cmupll1_clock_cram_to_phyport = res;
end
endfunction

// input is at most 15 bit
function integer convert_cmupll_phyport_str_to_phyport_enum;
input          phyport_str;
reg [8*15:1]   phyport_str;
integer        res;

begin
    if (phyport_str == "iq0")
        res = `CMUPLL_CLOCK_SELECT_IQ0;
    else if (phyport_str == "iq1")
        res = `CMUPLL_CLOCK_SELECT_IQ1;
    else if (phyport_str == "iq2")
        res = `CMUPLL_CLOCK_SELECT_IQ2;
    else if (phyport_str == "iq3")
        res = `CMUPLL_CLOCK_SELECT_IQ3;
    else if (phyport_str == "iq4")
        res = `CMUPLL_CLOCK_SELECT_IQ4;
    else if (phyport_str == "refclk0" || phyport_str == "clkrefclk0")
        res = `CMUPLL_CLOCK_SELECT_REFCLK0;
    else if (phyport_str == "refclk1" || phyport_str == "clkrefclk1")
        res = `CMUPLL_CLOCK_SELECT_REFCLK1;
    else if (phyport_str == "pld_clk")
        res = `CMUPLL_CLOCK_SELECT_PLD_CLK;
    else  // like "none"
        res = `CMUPLL_CLOCK_SELECT_ERR;
         
    convert_cmupll_phyport_str_to_phyport_enum = res;
end
endfunction
// end of CMUPLL

// input is at most 15 bit
function integer convert_phyport_str_to_phyport_enum;
input          phyport_str;
reg [8*15:1]   phyport_str;
integer        res;

begin
    if (phyport_str == "none")
        res = `CRU_CLOCK_SELECT_NONE;
    else if (phyport_str == "iq0")
        res = `CRU_CLOCK_SELECT_IQ0;
    else if (phyport_str == "iq1")
        res = `CRU_CLOCK_SELECT_IQ1;
    else if (phyport_str == "iq2")
        res = `CRU_CLOCK_SELECT_IQ2;
    else if (phyport_str == "iq3")
        res = `CRU_CLOCK_SELECT_IQ3;
    else if (phyport_str == "iq4")
        res = `CRU_CLOCK_SELECT_IQ4;
    else if (phyport_str == "pld_cru_clk")
        res = `CRU_CLOCK_SELECT_PLD_CRU_CLK;
    else if (phyport_str == "refclk0" || phyport_str == "clkrefclk0")
        res = `CRU_CLOCK_SELECT_REFCLK0;
    else if (phyport_str == "refclk1" || phyport_str == "clkrefclk1")
        res = `CRU_CLOCK_SELECT_REFCLK1;
    else if (phyport_str == "cmu_div_clk")
        res = `CRU_CLOCK_SELECT_CMU_DIV_CLK;
        
    convert_phyport_str_to_phyport_enum = res;
end
endfunction

function [3:0] convert_cru_clock_cram_to_phyport;
input [2:0] rrefclk_sel;
input [1:0] ser_bypass;
reg [3:0]   res;

begin
    if (ser_bypass == 2'b00)
        res = `CRU_CLOCK_SELECT_REFCLK0;
    else if (ser_bypass == 2'b01)
        res = `CRU_CLOCK_SELECT_REFCLK1;
    else if (ser_bypass == 2'b10)
        res = `CRU_CLOCK_SELECT_CMU_DIV_CLK;
    else if (rrefclk_sel == 3'b000)
        res = `CRU_CLOCK_SELECT_IQ0;
    else if (rrefclk_sel == 3'b001)
        res = `CRU_CLOCK_SELECT_IQ1;
    else if (rrefclk_sel == 3'b010)
        res = `CRU_CLOCK_SELECT_IQ2;
    else if (rrefclk_sel == 3'b011)
        res = `CRU_CLOCK_SELECT_IQ3;
    else if (rrefclk_sel == 3'b100)
        res = `CRU_CLOCK_SELECT_IQ4;
    else if (rrefclk_sel == 3'b101)
        res = `CRU_CLOCK_SELECT_PLD_CRU_CLK;
    else
        res = `CRU_CLOCK_SELECT_NONE;
    
    convert_cru_clock_cram_to_phyport = res;
end
endfunction

// debug dump
reg [31:0] dbg_file;

// CMU PLL reconfiguration ---------------------------------------------------
wire [7:0] tmp_cmupll_m0;
wire [7:0] tmp_cmupll_l0;
wire [7:0] tmp_cmupll_m1;
wire [7:0] tmp_cmupll_l1;
wire [7:0] tmp_cmupll_m2;
wire [7:0] tmp_cmupll_l2;

wire [7:0] tmp_cmupll_m0_int;
wire [7:0] tmp_cmupll_l0_int;
wire [7:0] tmp_cmupll_m1_int;
wire [7:0] tmp_cmupll_l1_int;
wire [7:0] tmp_cmupll_m2_int;
wire [7:0] tmp_cmupll_l2_int;

//rcmu0_ref_sel_int, rcmu1_ref_sel_int
//rcmu_txpll0_iqclkin_sel_int,rcmu_txpll1_iqclkin_sel_int

// local table - refclk_clock_physical_port <--> rcmu0_ref_sel[1:0] and 
//                    rcmu_txpll0_iqclkin_sel[2:0]
//   right hand side of table: 
//                             [5:4] = rcmu0_ref_sel
//                             [2:0] = rcmu_txpll0_iqclkin_sel 
// *** pll number in this table is physical number ***
reg [5:0] cmupll0_clock_phyport_to_cram [0:8];   // include "none" or error string
reg [5:0] cmupll1_clock_phyport_to_cram [0:8];   // include "none" or error string

//  cru_clock_select_physical_mapping strings --> ENUM table
integer cmupll0_clock_index_to_phyport [0:7];
integer cmupll1_clock_index_to_phyport [0:7];

wire [2:0] cmupll0_clock_select,     cmupll0_clock_phyport;
wire [2:0] cmupll0_clock_phyport_phy; // phyport on physical pll0
wire [5:0] cmupll0_clock_cram_phy;
wire [2:0] cmupll1_clock_select,     cmupll1_clock_phyport;
wire [2:0] cmupll1_clock_phyport_phy; // phyport on physical pll1
wire [5:0] cmupll1_clock_cram_phy;
  
// for cmupll_clock_select output
wire [3:0] cmupll0_clock_phyport_out, cmupll0_clock_select_out;
wire [3:0] cmupll1_clock_phyport_out, cmupll1_clock_select_out;

wire [3:0] cmupll0_clock_phyport_out_logic, cmupll0_clock_select_out_logic;
wire [3:0] cmupll1_clock_phyport_out_logic, cmupll1_clock_select_out_logic;

// cru_clock_select ------------------------------------------------------

// local table - cru_clock_physical_port <--> rrefclk_sel_ch0_int[2:0] and 
//                    ser_bypass[1:0] aka rrx_piso_bypass_ch0_int [1:0]
//   right hand side of table: 
//                             [5:3] = rrefclk_sel
//                             [1:0] = rrx_piso_bypass 
reg [5:0] cru_clock_phyport_to_cram [0:9];

//  cru_clock_select_physical_mapping strings --> indexed table
integer rx0_cru_clock_index_to_phyport [0:9];
integer rx1_cru_clock_index_to_phyport [0:9];
integer rx2_cru_clock_index_to_phyport [0:9];
integer rx3_cru_clock_index_to_phyport [0:9];

wire [3:0] rx0_cru_clock_select,     rx0_cru_clock_phyport;
wire [5:0] rx0_cru_clock_cram_logic, rx0_cru_clock_cram_phy;
wire [3:0] rx1_cru_clock_select,     rx1_cru_clock_phyport;
wire [5:0] rx1_cru_clock_cram_logic, rx1_cru_clock_cram_phy;
wire [3:0] rx2_cru_clock_select,     rx2_cru_clock_phyport;
wire [5:0] rx2_cru_clock_cram_logic, rx2_cru_clock_cram_phy;
wire [3:0] rx3_cru_clock_select,     rx3_cru_clock_phyport;
wire [5:0] rx3_cru_clock_cram_logic, rx3_cru_clock_cram_phy;
 
 
// for cru_clock_select output
wire [3:0] rx0_cru_clock_phyport_out, rx0_cru_clock_select_out;
wire [3:0] rx1_cru_clock_phyport_out, rx1_cru_clock_select_out;
wire [3:0] rx2_cru_clock_phyport_out, rx2_cru_clock_select_out;
wire [3:0] rx3_cru_clock_phyport_out, rx3_cru_clock_select_out;

wire [3:0] rx0_cru_clock_phyport_out_logic, rx0_cru_clock_select_out_logic;
wire [3:0] rx1_cru_clock_phyport_out_logic, rx1_cru_clock_select_out_logic;
wire [3:0] rx2_cru_clock_phyport_out_logic, rx2_cru_clock_select_out_logic;
wire [3:0] rx3_cru_clock_phyport_out_logic, rx3_cru_clock_select_out_logic;

// rtx_cmu_sel - tx_clock_divider_refclk_selection
wire [3:0] rtx_cmu_sel_logic;     // phy pll index on logic tx channel
wire [3:0] rtx_cmu_sel_int_logic; // phy pll index on logic tx channel
wire [3:0] tx_refclk_select_out;  // logic pll index
wire [3:0] tx_refclk_select_out_phy;  // physical pll index

// name twists between WYSIWYG and RTL ----------------------------------------
wire     jtag_shift_load;      // in
assign   jtag_shift_load = dprioload;

// un-supported ports - turning into wires ------------------------------------
// inputs get initialized appropriately

// JTAG inputs/outputs
wire          jtag_mode;            // in
wire          jtag_si;              // in

assign   jtag_mode       = 1'b0;
assign   jtag_si          = 1'bx;
     
wire         jtag_so;               // out

// input - status signals generated by PCS
wire          tx_local_fault;        // from tx_sm
wire          rx_local_fault;        // from rcv_sm
wire          xs_link_status;        // from rcv_sm

assign   tx_local_fault = 1'b0;
assign   rx_local_fault = 1'b0;
assign   xs_link_status = 1'b0;

// ouptut
wire         local_fault_ext;       // Status signal wire
wire         xs_link_status_ext;    // Status signal wire
wire         rx_local_fault_ext;    // Status signal wire
wire         tx_local_fault_ext;    // Status signal wire

// Unused CRAMs
wire          rxs_link_status_set;        // in
wire          rtx_rx_local_fault_clr;     // in

wire         rxs_link_status_set_int;     // out
wire         rtx_rx_local_fault_clr_int;  // out

//////////////////////////////////////////////////////////////////////////////////////////////////////
//              Beginning of named CRAMs                                                            //
//////////////////////////////////////////////////////////////////////////////////////////////////////

// TX PCS CRAMs wire from CSR ----------------------------------------------------------------------
wire   [3:0]  rpowdnt;               // TX channel power down CRAM
wire   [3:0]  rtxurstpcs;            // Gated CRAM for TXURSTPCS
wire   [3:0]  rbisten_tx;               // ENBIST CRAM
wire   [3:0]  rrev_loopbk;	      // CRAM - Enable dynamic Reverse, PIPE mode
wire 	[3:0]  rforce_disp;	      // Acting with TXD[9, 19] forces current disparity to 1 or 0
wire   [3:0]  rib_force_disp;        // Disparity force CRAM in IB mode
wire   [3:0]  rforce_echar;          // Force /E/ char CRAM
wire   [3:0]  rforce_kchar;          // Force /K/ char CRAM
wire   [3:0]  rendec_tx;             // Enable 8B/10B encoder CRAM
wire   [3:0]  rge_xaui_tx;           // GIGE Idle test enable CRAM
wire   [3:0]  rdwidth_tx;            // TX parallel interface data width CRAM
wire   [3:0]  rtxfifo_dis;           // TX FIFO disable CRAM
wire   [3:0]  rcascaded_8b10b_en_tx; // Caascaded 8b/10b encoder enable CRAM
wire   [3:0]  rprbsen_tx;            // PRBS generator enable CRAM
wire   [2:0]  rprbs_sel_ch0;         // PRBS selection CRAM
wire   [2:0]  rprbs_sel_ch1;         // PRBS selection CRAM
wire   [2:0]  rprbs_sel_ch2;         // PRBS selection CRAM
wire   [2:0]  rprbs_sel_ch3;         // PRBS selection CRAM
wire   [1:0]  rbist_sel_ch0;         // BIST selection CRAM
wire   [1:0]  rbist_sel_ch1;         // BIST selection CRAM
wire   [1:0]  rbist_sel_ch2;         // BIST selection CRAM
wire   [1:0]  rbist_sel_ch3;         // BIST selection CRAM
wire   [1:0]  rcxpat_chnl_en_ch0;    // CRPAT or CJPAT selection CRAM
wire   [1:0]  rcxpat_chnl_en_ch1;    // CRPAT or CJPAT selection CRAM
wire   [1:0]  rcxpat_chnl_en_ch2;    // CRPAT or CJPAT selection CRAM
wire   [1:0]  rcxpat_chnl_en_ch3;    // CRPAT or CJPAT selection CRAM
wire   [3:0]  renpolinv_tx;          // TX Polarity inversion enable CRAM
wire   [3:0]  rphfifopldentx;        // TX phase comp. FIFO PLD read/write enable CRAM
wire   [3:0]  rphfifoursttx;         // TX phase comp. FIFO user reset enable CRAM
wire   [3:0]  rfreerun_tx;           // TX_CLK out free running during TX PCS reset enable CRAM
wire   [3:0]  rtxwrclksel;           // TX FIFO write clock selection CRAM
wire   [3:0]  rtxrdclksel;           // TX FIFO read clock selection CRAM
wire   [3:0]  rtx_pipe_enable;       // TX PIPE interface enable CRAM
wire   [3:0]  renbitrev_tx;          // TX bit reversal enable CRAM
wire   [3:0]  rensymswap_tx;         // TX symbol swap enable CRAM
wire   [3:0]  r8b10b_enc_ibm_en;     // 8B10B Encoder fix enable CRAM
wire   [3:0]  rtxfifo_lowlatency_en; // TX FIFO low latency enable CRAM
wire   [1:0]  rtx_idle_delay_ch0;    // PIPE TxElecIdle delay value CRAM
wire   [1:0]  rtx_idle_delay_ch1;    // PIPE TxElecIdle delay value CRAM
wire   [1:0]  rtx_idle_delay_ch2;    // PIPE TxElecIdle delay value CRAM
wire   [1:0]  rtx_idle_delay_ch3;    // PIPE TxElecIdle delay value CRAM

// TX PCS CRAMs outputs to TX PCS ----------------------------------------------------------------------
/*
wire  [3:0]  rbisten_tx_int;        // ENBIST CRAM
wire  [3:0]  rrev_loopbk_int;	      // CRAM - Enable dynamic Reverse, PIPE mode
wire  [3:0]  rforce_disp_int;	      // Acting with TXD[9, 19] forces current disparity to 1 or 0
wire  [3:0]  rib_force_disp_int;    // Disparity force CRAM in IB mode
wire  [3:0]  rforce_echar_int;      // Force /E/ char CRAM
wire  [3:0]  rforce_kchar_int;      // Force /K/ char CRAM
wire  [3:0]  rendec_tx_int;         // Enable 8B/10B encoder CRAM
wire  [3:0]  rge_xaui_tx_int;       // GIGE Idle test enable CRAM
wire  [3:0]  rdwidth_tx_int;        // TX parallel interface data width CRAM
wire  [3:0]  rtxfifo_dis_int;       // TX FIFO disable CRAM
wire  [3:0]  rcascaded_8b10b_en_tx_int; // Caascaded 8b/10b encoder enable CRAM
wire  [3:0]  rprbsen_tx_int;            // PRBS generator enable CRAM
wire  [2:0]  rprbs_sel_ch0_int;         // PRBS selection CRAM
wire  [2:0]  rprbs_sel_ch1_int;         // PRBS selection CRAM
wire  [2:0]  rprbs_sel_ch2_int;         // PRBS selection CRAM
wire  [2:0]  rprbs_sel_ch3_int;         // PRBS selection CRAM
wire  [1:0]  rbist_sel_ch0_int;         // BIST selection CRAM
wire  [1:0]  rbist_sel_ch1_int;         // BIST selection CRAM
wire  [1:0]  rbist_sel_ch2_int;         // BIST selection CRAM
wire  [1:0]  rbist_sel_ch3_int;         // BIST selection CRAM
wire  [1:0]  rcxpat_chnl_en_ch0_int;    // CRPAT or CJPAT selection CRAM
wire  [1:0]  rcxpat_chnl_en_ch1_int;    // CRPAT or CJPAT selection CRAM
wire  [1:0]  rcxpat_chnl_en_ch2_int;    // CRPAT or CJPAT selection CRAM
wire  [1:0]  rcxpat_chnl_en_ch3_int;    // CRPAT or CJPAT selection CRAM
wire  [3:0]  renpolinv_tx_int;          // TX Polarity inversion enable CRAM
wire  [3:0]  rphfifopldentx_int;        // TX phase comp. FIFO PLD read/write enable CRAM
wire  [3:0]  rphfifoursttx_int;         // TX phase comp. FIFO user reset enable CRAM
wire  [3:0]  rfreerun_tx_int;           // TX_CLK out free running during TX PCS reset enable CRAM
wire  [3:0]  rtxwrclksel_int;           // TX FIFO write clock selection CRAM
wire  [3:0]  rtxrdclksel_int;           // TX FIFO read clock selection CRAM
wire  [3:0]  rtx_pipe_enable_int;       // TX PIPE interface enable CRAM
wire  [3:0]  renbitrev_tx_int;          // TX bit reversal enable CRAM
wire  [3:0]  rensymswap_tx_int;         // TX symbol swap enable CRAM
wire  [3:0]  r8b10b_enc_ibm_en_int;     // 8B10B Encoder fix enable CRAM
wire  [3:0]  rtxfifo_lowlatency_en_int; // TX FIFO low latency enable CRAM
wire  [1:0]  rtx_idle_delay_ch0_int;    // PIPE TxElecIdle delay value CRAM
wire  [1:0]  rtx_idle_delay_ch1_int;    // PIPE TxElecIdle delay value CRAM
wire  [1:0]  rtx_idle_delay_ch2_int;    // PIPE TxElecIdle delay value CRAM
wire  [1:0]  rtx_idle_delay_ch3_int;    // PIPE TxElecIdle delay value CRAM
*/

// TX PMA CRAMs --------------------------------------------------------------------------------
wire    [3:0]  rpmadwidth_tx;         // TX PCS to TX PMA data width selection CRAM
wire    [3:0]  rpma_doublewidth_tx;   // PCS/PMA double width (16/20) selection CRAM
wire    [1:0]  rtx_term_ch0;          // TX output buffer termination select CRAMs
wire    [1:0]  rtx_term_ch1;          // TX output buffer termination select CRAMs
wire    [1:0]  rtx_term_ch2;          // TX output buffer termination select CRAMs
wire    [1:0]  rtx_term_ch3;          // TX output buffer termination select CRAMs
wire    [2:0]  rtx_vod_sel_ch0;       // TX output buffer Vod switching control CRAMs
wire    [2:0]  rtx_vod_sel_ch1;       // TX output buffer Vod switching control CRAMs
wire    [2:0]  rtx_vod_sel_ch2;       // TX output buffer Vod switching control CRAMs
wire    [2:0]  rtx_vod_sel_ch3;       // TX output buffer Vod switching control CRAMs
wire    [3:0]  rpmphs_1tap_ch0;       // TX output buffer pre-emphasis switching control CRAMs
wire    [3:0]  rpmphs_1tap_ch1;       // TX output buffer pre-emphasis switching control CRAMs
wire    [3:0]  rpmphs_1tap_ch2;       // TX output buffer pre-emphasis switching control CRAMs
wire    [3:0]  rpmphs_1tap_ch3;       // TX output buffer pre-emphasis switching control CRAMs
wire    [3:0]  rtx_slewrate;          // Slew rate control CRAM
wire    [3:0]  rlst_tx_ch0;           // Low speed Test selection CRAMs
wire    [3:0]  rlst_tx_ch1;           // Low speed Test selection CRAMs
wire    [3:0]  rlst_tx_ch2;           // Low speed Test selection CRAMs
wire    [3:0]  rlst_tx_ch3;           // Low speed Test selection CRAMs
wire    [3:0]  rtx_cmu_sel;           // CMU selection CRAM
wire    [1:0]  rtx_m_sel_ch0;         // Division ratio CRAM selection of output clock in CLKGENBUF
wire    [1:0]  rtx_m_sel_ch1;         // Division ratio CRAM selection of output clock in CLKGENBUF
wire    [1:0]  rtx_m_sel_ch2;         // Division ratio CRAM selection of output clock in CLKGENBUF
wire    [1:0]  rtx_m_sel_ch3;         // Division ratio CRAM selection of output clock in CLKGENBUF
wire    [3:0]  rtxvcobypass;          // TX VCO bypass CRAM
wire    [3:0]  rtx_cgb_1x_en;         // Single CLKGENBUF mode enable CRAM
wire    [3:0]  rtx_cgb_4x_en;         // Quad CLKGENBUF mode enable CRAM
wire    [3:0]  rtx_4x_sw;   	      // Xaui mode (CPULSE aligned across 4 channels) selection CRAM
wire    [3:0]  rsig_inv_2tap;         // Pre-emphasis FIR-tap selection CRAM
wire    [2:0]  rpmphs_ptap_ch0;       // Control CRAM
wire    [2:0]  rpmphs_ptap_ch1;       // Control CRAM
wire    [2:0]  rpmphs_ptap_ch2;       // Control CRAM
wire    [2:0]  rpmphs_ptap_ch3;       // Control CRAM
wire    [3:0]  rtx_cgb_pdb;           // Power down (bar) CRAM for CLKGENBUF6G
wire    [3:0]  rtx_ob_pdb;            // Power down (bar) CRAM for output buffer
wire    [1:0]  r_tx_det_rx_ch0;       // RX Detect block CRAMs
wire    [1:0]  r_tx_det_rx_ch1;       // RX Detect block CRAMs
wire    [1:0]  r_tx_det_rx_ch2;       // RX Detect block CRAMs
wire    [1:0]  r_tx_det_rx_ch3;       // RX Detect block CRAMs
wire    [2:0]  rpmphs_2tap_ch0;       // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire    [2:0]  rpmphs_2tap_ch1;       // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire    [2:0]  rpmphs_2tap_ch2;       // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire    [2:0]  rpmphs_2tap_ch3;       // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire    [1:0]  rtx_vtt_ch0;           // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire    [1:0]  rtx_vtt_ch1;           // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire    [1:0]  rtx_vtt_ch2;           // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire    [1:0]  rtx_vtt_ch3;           // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire    [3:0]  rsig_inv_pre;          // Enable CRAM for SIG_INV_PRE dynamic control signal
wire    [4:0]  rrsvd_tx_ch0;          // Rerserved CRAMs for both TX PCS and TX PMA
wire    [4:0]  rrsvd_tx_ch1;          // Rerserved CRAMs for both TX PCS and TX PMA
wire    [4:0]  rrsvd_tx_ch2;          // Rerserved CRAMs for both TX PCS and TX PMA
wire    [4:0]  rrsvd_tx_ch3;          // Rerserved CRAMs for both TX PCS and TX PMA

// TX PMA CRAMs outputs to TX PMAs ----------------------------------------------------------------------
/*
wire     [3:0]  rpmadwidth_tx_int;     // TX PCS to TX PMA data width selection CRAM
wire     [3:0]  rpma_doublewidth_tx_int;// PCS/PMA double width (16/20) selection CRAM
wire     [1:0]  rtx_term_ch0_int;      // TX output buffer termination select CRAMs
wire     [1:0]  rtx_term_ch1_int;      // TX output buffer termination select CRAMs
wire     [1:0]  rtx_term_ch2_int;      // TX output buffer termination select CRAMs
wire     [1:0]  rtx_term_ch3_int;      // TX output buffer termination select CRAMs
wire     [2:0]  rtx_vod_sel_ch0_int;   // TX output buffer Vod switching control CRAMs
wire     [2:0]  rtx_vod_sel_ch1_int;   // TX output buffer Vod switching control CRAMs
wire     [2:0]  rtx_vod_sel_ch2_int;   // TX output buffer Vod switching control CRAMs
wire     [2:0]  rtx_vod_sel_ch3_int;   // TX output buffer Vod switching control CRAMs
wire     [3:0]  rpmphs_1tap_ch0_int;   // TX output buffer pre-emphasis switching control CRAMs
wire     [3:0]  rpmphs_1tap_ch1_int;   // TX output buffer pre-emphasis switching control CRAMs
wire     [3:0]  rpmphs_1tap_ch2_int;   // TX output buffer pre-emphasis switching control CRAMs
wire     [3:0]  rpmphs_1tap_ch3_int;   // TX output buffer pre-emphasis switching control CRAMs
wire     [3:0]  rtx_slewrate_int;     // Slew rate control CRAM
wire     [3:0]  rlst_tx_ch0_int;       // Low speed Test selection CRAMs
wire     [3:0]  rlst_tx_ch1_int;       // Low speed Test selection CRAMs
wire     [3:0]  rlst_tx_ch2_int;       // Low speed Test selection CRAMs
wire     [3:0]  rlst_tx_ch3_int;       // Low speed Test selection CRAMs
wire     [3:0]  rtx_cmu_sel_int;       // CMU selection CRAM
wire     [1:0]  rtx_m_sel_ch0_int;     // Division ratio CRAM selection of output clock in CLKGENBUF
wire     [1:0]  rtx_m_sel_ch1_int;     // Division ratio CRAM selection of output clock in CLKGENBUF
wire     [1:0]  rtx_m_sel_ch2_int;     // Division ratio CRAM selection of output clock in CLKGENBUF
wire     [1:0]  rtx_m_sel_ch3_int;     // Division ratio CRAM selection of output clock in CLKGENBUF
wire     [3:0]  rtxvcobypass_int;      // TX VCO bypass CRAM
wire     [3:0]  rtx_cgb_1x_en_int;     // Single CLKGENBUF mode enable CRAM
wire     [3:0]  rtx_cgb_4x_en_int;     // Quad CLKGENBUF mode enable CRAM
wire     [3:0]  rtx_4x_sw_int;         // Xaui mode (CPULSE aligned across 4 channels) selection CRAM
wire     [3:0]  rsig_inv_2tap_int;     // Pre-emphasis FIR-tap selection CRAM
wire     [2:0]  rpmphs_ptap_ch0_int;   // Control CRAM
wire     [2:0]  rpmphs_ptap_ch1_int;   // Control CRAM
wire     [2:0]  rpmphs_ptap_ch2_int;   // Control CRAM
wire     [2:0]  rpmphs_ptap_ch3_int;   // Control CRAM
wire     [3:0]  rtx_cgb_pdb_int;       // Power down (bar) CRAM for CLKGENBUF6G
wire     [3:0]  rtx_ob_pdb_int;        // Power down (bar) CRAM for output buffer
wire     [1:0]  r_tx_det_rx_ch0_int;   // RX Detect block CRAMs
wire     [1:0]  r_tx_det_rx_ch1_int;   // RX Detect block CRAMs
wire     [1:0]  r_tx_det_rx_ch2_int;   // RX Detect block CRAMs
wire     [1:0]  r_tx_det_rx_ch3_int;   // RX Detect block CRAMs
wire     [2:0]  rpmphs_2tap_ch0_int;   // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire     [2:0]  rpmphs_2tap_ch1_int;   // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire     [2:0]  rpmphs_2tap_ch2_int;   // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire     [2:0]  rpmphs_2tap_ch3_int;   // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire     [1:0]  rtx_vtt_ch0_int;       // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire     [1:0]  rtx_vtt_ch1_int;       // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire     [1:0]  rtx_vtt_ch2_int;       // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire     [1:0]  rtx_vtt_ch3_int;       // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire     [3:0]  rsig_inv_pre_int;      // Enable CRAM for SIG_INV_PRE dynamic control signal
wire     [4:0]  rrsvd_tx_ch0_int;      // Rerserved CRAMs for both TX PCS and TX PMA
wire     [4:0]  rrsvd_tx_ch1_int;      // Rerserved CRAMs for both TX PCS and TX PMA
wire     [4:0]  rrsvd_tx_ch2_int;      // Rerserved CRAMs for both TX PCS and TX PMA
wire     [4:0]  rrsvd_tx_ch3_int;      // Rerserved CRAMs for both TX PCS and TX PMA
*/

// RX PCS CRAMs -------------------------------------------------------------------------------------------------------
wire 	[3:0]  rskpsetbased;          // Enable rate matching for PCI-E/PIPE, other standards based on COMMA DEL DEL..
wire	[3:0]  rtruebac2bac;          // Enabled (high) for all standards except PIPE. Back to back rate match enable.
wire    [3:0]  ralfull_ch0;	      // CRAM bits - Program when almost full goes high	
wire    [3:0]  ralempty_ch0;	      // CRAM bits - Program when almost empty goes high
wire    [3:0]  ralfull_ch1;	      // CRAM bits - Program when almost full goes high	
wire    [3:0]  ralempty_ch1;	      // CRAM bits - Program when almost empty goes high
wire    [3:0]  ralfull_ch2;	      // CRAM bits - Program when almost full goes high	
wire    [3:0]  ralempty_ch2;	      // CRAM bits - Program when almost empty goes high
wire    [3:0]  ralfull_ch3;	      // CRAM bits - Program when almost full goes high	
wire    [3:0]  ralempty_ch3;	      // CRAM bits - Program when almost empty goes high
wire    [3:0]  rcmpfifourst;          // Enable cmpfifourst
wire    [3:0]  rphfifourstrx;         // Enable phfifourst_rx
wire    [3:0]  rpowdnr;               // RX channel power down CRAM
wire    [3:0]  rrxurstpcs;            // Gated CRAM for RXURSTPCS
wire    [2:0]  rcomp_size_ch0;        // Pattern comparision length CRAMs
wire    [2:0]  rcomp_size_ch1;        // Pattern comparision length CRAMs
wire    [2:0]  rcomp_size_ch2;        // Pattern comparision length CRAMs
wire    [2:0]  rcomp_size_ch3;        // Pattern comparision length CRAMs
wire    [39:0] rcomp_pat_ch0;         // Sync pattern CRAMs
wire    [39:0] rcomp_pat_ch1;         // Sync pattern CRAMs
wire    [39:0] rcomp_pat_ch2;         // Sync pattern CRAMs
wire    [39:0] rcomp_pat_ch3;         // Sync pattern CRAMs
wire    [5:0]  rrundisp_ch0;          // Run lengh violation setting CRAMs
wire    [5:0]  rrundisp_ch1;          // Run lengh violation setting CRAMs
wire    [5:0]  rrundisp_ch2;          // Run lengh violation setting CRAMs
wire    [5:0]  rrundisp_ch3;          // Run lengh violation setting CRAMs
wire    [1:0]  rib_inv_cd_ch0;        // Invalid code setting CRAMs for IB
wire    [1:0]  rib_inv_cd_ch1;        // Invalid code setting CRAMs for IB
wire    [1:0]  rib_inv_cd_ch2;        // Invalid code setting CRAMs for IB
wire    [1:0]  rib_inv_cd_ch3;        // Invalid code setting CRAMs for IB
wire    [3:0]  rrlv_en;               // RLV enable CRAM
wire    [3:0]  rsync_sm_dis;          // GIGE/XAUI Sync SM disable CRAM
wire    [3:0]  rautobtalg_dis;        // BITSLIP mode enable CRAM
wire    [3:0]  rdis_rx_disp;          // Receive running disparity calculation disable CRAM
wire    [3:0]  rmatchen;              // Clock compensation enable CRAM
wire    [3:0]  rgenericfifo;          // GenericFIFO mode enable CRAM
wire    [3:0]  rendec_rx;             // 10B/8B decoder enable CRAM
wire    [3:0]  rdwidth_rx;            // RX parallel interface data width selection CRAM
wire    [3:0]  rlp20ben;              // 20-b loopback enable CRAM
wire    [3:0]  rrxfifo_dis;           // RX FIFO bypassing CRAM
wire    [2:0]  renumber_ch0;          // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire    [2:0]  renumber_ch1;          // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire    [2:0]  renumber_ch2;          // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire    [2:0]  renumber_ch3;          // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire    [7:0]  rknumber_ch0;          // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire    [7:0]  rknumber_ch1;          // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire    [7:0]  rknumber_ch2;          // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire    [7:0]  rknumber_ch3;          // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire    [3:0]  renpolinv_rx;          // Allow polarity inversion
wire    [7:0]  rgnumber_ch0;          // Number of consecutive good data to approach SYNC_ACQ
wire    [7:0]  rgnumber_ch1;          // Number of consecutive good data to approach SYNC_ACQ
wire    [7:0]  rgnumber_ch2;          // Number of consecutive good data to approach SYNC_ACQ
wire    [7:0]  rgnumber_ch3;          // Number of consecutive good data to approach SYNC_ACQ
wire    [3:0]  rclkcmpsqmd;           // How many characters to match
wire    [19:0] rclkcmpsq1p_ch0;       // Programmable 20-bit encoded comp sequence pos. disp.
wire    [19:0] rclkcmpsq1p_ch1;       // Programmable 20-bit encoded comp sequence pos. disp.
wire    [19:0] rclkcmpsq1p_ch2;       // Programmable 20-bit encoded comp sequence pos. disp.
wire    [19:0] rclkcmpsq1p_ch3;       // Programmable 20-bit encoded comp sequence pos. disp.
wire    [19:0] rclkcmpsq1n_ch0;       // Programmable 20-bit encoded comp sequence neg. disp.
wire    [19:0] rclkcmpsq1n_ch1;       // Programmable 20-bit encoded comp sequence neg. disp.
wire    [19:0] rclkcmpsq1n_ch2;       // Programmable 20-bit encoded comp sequence neg. disp.
wire    [19:0] rclkcmpsq1n_ch3;       // Programmable 20-bit encoded comp sequence neg. disp.
wire    [3:0]  rclkcmppos;            // Match only the pos disp. sequence 
wire    [1:0]  rosnumber_ch0;         // Length of the ordered set
wire    [1:0]  rosnumber_ch1;         // Length of the ordered set
wire    [1:0]  rosnumber_ch2;         // Length of the ordered set
wire    [1:0]  rosnumber_ch3;         // Length of the ordered set
wire    [3:0]  rosbased;              // Enable ordered-set based algorithm
wire    [3:0]  rkchar;                // use kchar at cg_bad logic calculation
wire    [3:0]  rcascaded_8b10b_en_rx; // Cascaded 8B/10B decoder enable CRAM
wire    [1:0]  resync_badcg_en_ch0;   //
wire    [1:0]  resync_badcg_en_ch1;   //
wire    [1:0]  resync_badcg_en_ch2;   //
wire    [1:0]  resync_badcg_en_ch3;   //
wire    [3:0]  rencdt_rising;         // encdt on rising edge enable CRAM
wire    [3:0]  rcomp_pat_porn;        // Positive and negative match enable CRAM
wire    [3:0]  rprbsen_rx;            // PRBS Verifier enable CRAM
wire    [3:0]  rprbs_clr_rslt_rx;     // PRBS pass/fail flag clear CRAM
wire    [3:0]  rbisten_rx;            // BIST Verifier enable CRAM
wire    [3:0]  rbist_clr_rx;          // BIST pass/fail flag clear CRAM
wire    [3:0]  rwa_6g_en;             // 6G word alignment enable CRAM
wire    [1:0]  rbitslip_size_ch0;     // BITSLIP size selection CRAM
wire    [1:0]  rbitslip_size_ch1;     // BITSLIP size selection CRAM
wire    [1:0]  rbitslip_size_ch2;     // BITSLIP size selection CRAM
wire    [1:0]  rbitslip_size_ch3;     // BITSLIP size selection CRAM
wire    [3:0]  rbytord_2sym_en;       // Enable 2 symbols byte orderring CRAM
wire    [3:0]  rbysync_polinv_en;     // Word alignment polarity inversion enable CRAM
wire    [3:0]  rbitloc_rev_en;        // Bit reversal enable CRAM
wire    [3:0]  rbyte_rev_en;          // Byte swap enable CRAM
wire    [1:0]  rbyteorden_ch0;        // Byte ordering enable CRAM
wire    [1:0]  rbyteorden_ch1;        // Byte ordering enable CRAM
wire    [1:0]  rbyteorden_ch2;        // Byte ordering enable CRAM
wire    [1:0]  rbyteorden_ch3;        // Byte ordering enable CRAM
wire    [3:0]  rbytordplden;          // PLD control signal BYTEORDPLD enable CRAM
wire    [3:0]  rphfifopldenrx;        // RX phase comp. FIFO read/write enable CRAM
wire    [3:0]  rautoinsdis;           // Disable CRAM for auto insertion of 8'h9C
wire    [5:0]  rppmsel_ch0;           // Programmable PPM ajustment CRAM
wire    [5:0]  rppmsel_ch1;           // Programmable PPM ajustment CRAM
wire    [5:0]  rppmsel_ch2;           // Programmable PPM ajustment CRAM
wire    [5:0]  rppmsel_ch3;           // Programmable PPM ajustment CRAM
wire    [3:0]  rforce0_freqdet;       // Forcing FREQDET signal to low CRAM
wire    [3:0]  rforce1_freqdet;       // Forcing FREQDET signal to high CRAM
wire    [9:0]  rbytordpat_ch0;        // Byte ordering pattern CRAM
wire    [9:0]  rbytordpat_ch1;        // Byte ordering pattern CRAM
wire    [9:0]  rbytordpat_ch2;        // Byte ordering pattern CRAM
wire    [9:0]  rbytordpat_ch3;        // Byte ordering pattern CRAM
wire    [9:0]  rbytordpad_ch0;        // Byte ordering pad pattern CRAM
wire    [9:0]  rbytordpad_ch1;        // Byte ordering pad pattern CRAM
wire    [9:0]  rbytordpad_ch2;        // Byte ordering pad pattern CRAM
wire    [9:0]  rbytordpad_ch3;        // Byte ordering pad pattern CRAM
wire    [3:0]  rforce_sig_det_pcs;    // Forcing sigdet to high in PCS CRAM
wire    [3:0]  rfreerun_rx;           // RX_CLK out free running during RX PCS reset enable CRAM
wire    [1:0]  rrcvd_clk_sel_ch0;     // RCVD_CLK domain selection CRAM
wire    [1:0]  rrcvd_clk_sel_ch1;     // RCVD_CLK domain selection CRAM
wire    [1:0]  rrcvd_clk_sel_ch2;     // RCVD_CLK domain selection CRAM
wire    [1:0]  rrcvd_clk_sel_ch3;     // RCVD_CLK domain selection CRAM
wire    [1:0]  rclk_1_sel_ch0;        // CLK_1 domain selection CRAM
wire    [1:0]  rclk_1_sel_ch1;        // CLK_1 domain selection CRAM
wire    [1:0]  rclk_1_sel_ch2;        // CLK_1 domain selection CRAM
wire    [1:0]  rclk_1_sel_ch3;        // CLK_1 domain selection CRAM
wire    [1:0]  rclk_2_sel_ch0;        // CLK_2 domain selection CRAM
wire    [1:0]  rclk_2_sel_ch1;        // CLK_2 domain selection CRAM
wire    [1:0]  rclk_2_sel_ch2;        // CLK_2 domain selection CRAM
wire    [1:0]  rclk_2_sel_ch3;        // CLK_2 domain selection CRAM
wire    [3:0]  rrx_rd_clk_sel;        // RX FIFO read clock selection CRAM
wire    [3:0]  rrx_pipe_enable;       // RX PIPE interface enable CRAM
wire    [3:0]  rall_one_dect_only;    // PRBS Verifier detect all one only enable CRAM
wire    [2:0]  rtest_bus_sel_ch0;     // Per channel test bus selection CRAMs
wire    [2:0]  rtest_bus_sel_ch1;     // Per channel test bus selection CRAMs
wire    [2:0]  rtest_bus_sel_ch2;     // Per channel test bus selection CRAMs
wire    [2:0]  rtest_bus_sel_ch3;     // Per channel test bus selection CRAMs
wire    [1:0]  r8b10b_dec_ibm_en_ch0; // 8B10B Decoder fix enable CRAM
wire    [1:0]  r8b10b_dec_ibm_en_ch1; // 8B10B Decoder fix enable CRAM
wire    [1:0]  r8b10b_dec_ibm_en_ch2; // 8B10B Decoder fix enable CRAM
wire    [1:0]  r8b10b_dec_ibm_en_ch3; // 8B10B Decoder fix enable CRAM
wire    [3:0]  rrxfifo_lowlatency_en; // RX FIFO low latency enable CRAM
wire    [3:0]  rppm_cnt_reset;        // PPM counter reset CRAM (latched version on Test bus)
wire    [3:0]  rrx_detect_bypass;     // PMA RX detection bypass enable CRAM
wire    [3:0]  rclkcmpinsertpad;      // Rate matching pad insertion enable CRAM

// RX PCS CRAMs outputs to RX PCS -------------------------------------------------------------------------------------
/*
wire     [3:0]  rskpsetbased_int;      // Enable rate matching for PCI-E/PIPE, other standards based on COMMA DEL DEL..
wire     [3:0]  rtruebac2bac_int;      // Enabled (high) for all standards except PIPE. Back to back rate match enable.
wire     [3:0]  ralfull_ch0_int;       // Program when almost full goes high	
wire     [3:0]  ralempty_ch0_int;      // Program when almost empty goes high
wire     [3:0]  ralfull_ch1_int;       // Program when almost full goes high	
wire     [3:0]  ralempty_ch1_int;      // Program when almost empty goes high
wire     [3:0]  ralfull_ch2_int;       // Program when almost full goes high	
wire     [3:0]  ralempty_ch2_int;      // Program when almost empty goes high
wire     [3:0]  ralfull_ch3_int;       // Program when almost full goes high	
wire     [3:0]  ralempty_ch3_int;      // Program when almost empty goes high
wire     [3:0]  rcmpfifourst_int;      // Enable cmpfifourst
wire     [3:0]  rphfifourstrx_int;     // Enable phfifourst
wire     [2:0]  rcomp_size_ch0_int;    // Pattern comparision length CRAMs
wire     [2:0]  rcomp_size_ch1_int;    // Pattern comparision length CRAMs
wire     [2:0]  rcomp_size_ch2_int;    // Pattern comparision length CRAMs
wire     [2:0]  rcomp_size_ch3_int;    // Pattern comparision length CRAMs
wire     [39:0] rcomp_pat_ch0_int;     // Sync pattern CRAMs
wire     [39:0] rcomp_pat_ch1_int;     // Sync pattern CRAMs
wire     [39:0] rcomp_pat_ch2_int;     // Sync pattern CRAMs
wire     [39:0] rcomp_pat_ch3_int;     // Sync pattern CRAMs
wire     [5:0]  rrundisp_ch0_int;      // Run lengh violation setting CRAMs
wire     [5:0]  rrundisp_ch1_int;      // Run lengh violation setting CRAMs
wire     [5:0]  rrundisp_ch2_int;      // Run lengh violation setting CRAMs
wire     [5:0]  rrundisp_ch3_int;      // Run lengh violation setting CRAMs
wire     [1:0]  rib_inv_cd_ch0_int;    // Invalid code setting CRAMs for IB
wire     [1:0]  rib_inv_cd_ch1_int;    // Invalid code setting CRAMs for IB
wire     [1:0]  rib_inv_cd_ch2_int;    // Invalid code setting CRAMs for IB
wire     [1:0]  rib_inv_cd_ch3_int;    // Invalid code setting CRAMs for IB
wire     [3:0]  rrlv_en_int;           // RLV enable CRAM
wire     [3:0]  rsync_sm_dis_int;      // GIGE/XAUI Sync SM disable CRAM
wire     [3:0]  rautobtalg_dis_int;    // BITSLIP mode enable CRAM
wire     [3:0]  rdis_rx_disp_int;      // Receive running disparity calculation disable CRAM
wire     [3:0]  rmatchen_int;          // Clock compensation enable CRAM
wire     [3:0]  rgenericfifo_int;      // GenericFIFO mode enable CRAM
wire     [3:0]  rendec_rx_int;         // 10B/8B decoder enable CRAM
wire     [3:0]  rdwidth_rx_int;        // RX parallel interface data width selection CRAM
wire     [3:0]  rlp20ben_int;          // 20-b loopback enable CRAM
wire     [3:0]  rrxfifo_dis_int;       // RX FIFO bypassing CRAM
wire     [2:0]  renumber_ch0_int;      // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire     [2:0]  renumber_ch1_int;      // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire     [2:0]  renumber_ch2_int;      // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire     [2:0]  renumber_ch3_int;      // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire     [7:0]  rknumber_ch0_int;      // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire     [7:0]  rknumber_ch1_int;      // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire     [7:0]  rknumber_ch2_int;      // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire     [7:0]  rknumber_ch3_int;      // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire     [3:0]  renpolinv_rx_int;      // Allow polarity inversion
wire     [7:0]  rgnumber_ch0_int;      // Number of consecutive good data to approach SYNC_ACQ
wire     [7:0]  rgnumber_ch1_int;      // Number of consecutive good data to approach SYNC_ACQ
wire     [7:0]  rgnumber_ch2_int;      // Number of consecutive good data to approach SYNC_ACQ
wire     [7:0]  rgnumber_ch3_int;      // Number of consecutive good data to approach SYNC_ACQ
wire     [3:0]  rclkcmpsqmd_int;       // How many characters to match
wire     [19:0] rclkcmpsq1p_ch0_int;   // Programmable 20-bit encoded comp sequence pos. disp.
wire     [19:0] rclkcmpsq1p_ch1_int;   // Programmable 20-bit encoded comp sequence pos. disp.
wire     [19:0] rclkcmpsq1p_ch2_int;   // Programmable 20-bit encoded comp sequence pos. disp.
wire     [19:0] rclkcmpsq1p_ch3_int;   // Programmable 20-bit encoded comp sequence pos. disp.
wire     [19:0] rclkcmpsq1n_ch0_int;   // Programmable 20-bit encoded comp sequence neg. disp.
wire     [19:0] rclkcmpsq1n_ch1_int;   // Programmable 20-bit encoded comp sequence neg. disp.
wire     [19:0] rclkcmpsq1n_ch2_int;   // Programmable 20-bit encoded comp sequence neg. disp.
wire     [19:0] rclkcmpsq1n_ch3_int;   // Programmable 20-bit encoded comp sequence neg. disp.
wire     [3:0]  rclkcmppos_int;        // Match only the pos disp. sequence 
wire     [1:0]  rosnumber_ch0_int;     // Length of the ordered set
wire     [1:0]  rosnumber_ch1_int;     // Length of the ordered set
wire     [1:0]  rosnumber_ch2_int;     // Length of the ordered set
wire     [1:0]  rosnumber_ch3_int;     // Length of the ordered set
wire     [3:0]  rosbased_int;          // Enable ordered-set based algorithm
wire     [3:0]  rkchar_int;            // use kchar at cg_bad logic calculation
wire     [3:0]  rcascaded_8b10b_en_rx_int; // Cascaded 8B/10B decoder enable CRAM
wire     [1:0]  resync_badcg_en_ch0_int;   //
wire     [1:0]  resync_badcg_en_ch1_int;   //
wire     [1:0]  resync_badcg_en_ch2_int;   //
wire     [1:0]  resync_badcg_en_ch3_int;   //
wire     [3:0]  rencdt_rising_int;         // encdt on rising edge enable CRAM
wire     [3:0]  rcomp_pat_porn_int;        // Positive and negative match enable CRAM
wire     [3:0]  rprbsen_rx_int;            // PRBS Verifier enable CRAM
wire     [3:0]  rprbs_clr_rslt_rx_int;     // PRBS pass/fail flag clear CRAM
wire     [3:0]  rbisten_rx_int;            // BIST Verifier enable CRAM
wire     [3:0]  rbist_clr_rx_int;          // BIST pass/fail flag clear CRAM
wire     [3:0]  rwa_6g_en_int;             // 6G word alignment enable CRAM
wire     [1:0]  rbitslip_size_ch0_int;     // BITSLIP size selection CRAM
wire     [1:0]  rbitslip_size_ch1_int;     // BITSLIP size selection CRAM
wire     [1:0]  rbitslip_size_ch2_int;     // BITSLIP size selection CRAM
wire     [1:0]  rbitslip_size_ch3_int;     // BITSLIP size selection CRAM
wire     [3:0]  rbytord_2sym_en_int;       // Enable 2 symbols byte orderring CRAM
wire     [3:0]  rbysync_polinv_en_int;     // Word alignment polarity inversion enable CRAM
wire     [3:0]  rbitloc_rev_en_int;        // Bit reversal enable CRAM
wire     [3:0]  rbyte_rev_en_int;          // Byte swap enable CRAM
wire     [1:0]  rbyteorden_ch0_int;        // Byte ordering enable CRAM
wire     [1:0]  rbyteorden_ch1_int;        // Byte ordering enable CRAM
wire     [1:0]  rbyteorden_ch2_int;        // Byte ordering enable CRAM
wire     [1:0]  rbyteorden_ch3_int;        // Byte ordering enable CRAM
wire     [3:0]  rbytordplden_int;          // PLD control signal BYTEORDPLD enable CRAM
wire     [3:0]  rphfifopldenrx_int;        // RX phase comp. FIFO read/write enable CRAM
wire     [3:0]  rautoinsdis_int;           // Disable CRAM for auto insertion of 8'h9C
wire     [5:0]  rppmsel_ch0_int;           // Programmable PPM ajustment CRAM
wire     [5:0]  rppmsel_ch1_int;           // Programmable PPM ajustment CRAM
wire     [5:0]  rppmsel_ch2_int;           // Programmable PPM ajustment CRAM
wire     [5:0]  rppmsel_ch3_int;           // Programmable PPM ajustment CRAM
wire     [3:0]  rforce0_freqdet_int;       // Forcing FREQDET signal to low CRAM
wire     [3:0]  rforce1_freqdet_int;       // Forcing FREQDET signal to high CRAM
wire     [9:0]  rbytordpat_ch0_int;        // Byte ordering pattern CRAM
wire     [9:0]  rbytordpat_ch1_int;        // Byte ordering pattern CRAM
wire     [9:0]  rbytordpat_ch2_int;        // Byte ordering pattern CRAM
wire     [9:0]  rbytordpat_ch3_int;        // Byte ordering pattern CRAM
wire     [9:0]  rbytordpad_ch0_int;        // Byte ordering pad pattern CRAM
wire     [9:0]  rbytordpad_ch1_int;        // Byte ordering pad pattern CRAM
wire     [9:0]  rbytordpad_ch2_int;        // Byte ordering pad pattern CRAM
wire     [9:0]  rbytordpad_ch3_int;        // Byte ordering pad pattern CRAM
wire     [3:0]  rforce_sig_det_pcs_int;    // Forcing sigdet to high in PCS CRAM
wire     [3:0]  rfreerun_rx_int;           // RX_CLK out free running during RX PCS reset enable CRAM
wire     [1:0]  rrcvd_clk_sel_ch0_int;     // RCVD_CLK domain selection CRAM
wire     [1:0]  rrcvd_clk_sel_ch1_int;     // RCVD_CLK domain selection CRAM
wire     [1:0]  rrcvd_clk_sel_ch2_int;     // RCVD_CLK domain selection CRAM
wire     [1:0]  rrcvd_clk_sel_ch3_int;     // RCVD_CLK domain selection CRAM
wire     [1:0]  rclk_1_sel_ch0_int;        // CLK_1 domain selection CRAM
wire     [1:0]  rclk_1_sel_ch1_int;        // CLK_1 domain selection CRAM
wire     [1:0]  rclk_1_sel_ch2_int;        // CLK_1 domain selection CRAM
wire     [1:0]  rclk_1_sel_ch3_int;        // CLK_1 domain selection CRAM
wire     [1:0]  rclk_2_sel_ch0_int;        // CLK_2 domain selection CRAM
wire     [1:0]  rclk_2_sel_ch1_int;        // CLK_2 domain selection CRAM
wire     [1:0]  rclk_2_sel_ch2_int;        // CLK_2 domain selection CRAM
wire     [1:0]  rclk_2_sel_ch3_int;        // CLK_2 domain selection CRAM
wire     [3:0]  rrx_rd_clk_sel_int;        // RX FIFO read clock selection CRAM
wire     [3:0]  rrx_pipe_enable_int;       // RX PIPE interface enable CRAM
wire     [3:0]  rall_one_dect_only_int;    // PRBS Verifier detect all one only enable CRAM
wire     [2:0]  rtest_bus_sel_ch0_int;     // Per channel test bus selection CRAMs
wire     [2:0]  rtest_bus_sel_ch1_int;     // Per channel test bus selection CRAMs
wire     [2:0]  rtest_bus_sel_ch2_int;     // Per channel test bus selection CRAMs
wire     [2:0]  rtest_bus_sel_ch3_int;     // Per channel test bus selection CRAMs
wire     [1:0]  r8b10b_dec_ibm_en_ch0_int; // 8B10B Decoder fix enable CRAM
wire     [1:0]  r8b10b_dec_ibm_en_ch1_int; // 8B10B Decoder fix enable CRAM
wire     [1:0]  r8b10b_dec_ibm_en_ch2_int; // 8B10B Decoder fix enable CRAM
wire     [1:0]  r8b10b_dec_ibm_en_ch3_int; // 8B10B Decoder fix enable CRAM
wire     [3:0]  rrxfifo_lowlatency_en_int; // RX FIFO low latency enable CRAM
wire     [3:0]  rppm_cnt_reset_int;        // PPM counter reset CRAM (latched version on Test bus)
wire     [3:0]  rrx_detect_bypass_int;     // PMA RX detection bypass enable CRAM
wire     [3:0]  rclkcmpinsertpad_int;      // Rate matching pad insertion enable CRAM
*/

// RX PMA CRAMs ----------------------------------------------------------------------------------
wire    [3:0]  rpmadwidth_rx;	      // RX PMA to RX PCS data width sel CRAMs
wire    [3:0]  rpma_doublewidth_rx;   // RX PMA/PCS double width (16/20) sel CRAM
wire    [2:0]  rrx_sloslv_ch0;	      // Signal loss threshold select CRAMs
wire    [2:0]  rrx_sloslv_ch1;	      // Signal loss threshold select CRAMs
wire    [2:0]  rrx_sloslv_ch2;	      // Signal loss threshold select CRAMs
wire    [2:0]  rrx_sloslv_ch3;	      // Signal loss threshold select CRAMs
wire    [1:0]  rrx_term_ch0;          // RX input buffer termination select CRAMs
wire    [1:0]  rrx_term_ch1;          // RX input buffer termination select CRAMs
wire    [1:0]  rrx_term_ch2;          // RX input buffer termination select CRAMs
wire    [1:0]  rrx_term_ch3;          // RX input buffer termination select CRAMs
wire    [3:0]  rrxvcobypass;	      // RX VCO bypass CRAM
wire    [1:0]  rbwctral_rx_ch0;	      // RX PLL loop filter bandwidth control CRAMs
wire    [1:0]  rbwctral_rx_ch1;	      // RX PLL loop filter bandwidth control CRAMs
wire    [1:0]  rbwctral_rx_ch2;	      // RX PLL loop filter bandwidth control CRAMs
wire    [1:0]  rbwctral_rx_ch3;	      // RX PLL loop filter bandwidth control CRAMs
wire    [3:0]  rforce_sigdet;         // SIGDET forcing CRAM
wire    [2:0]  rrefclk_sel_ch0;	      // RXPLL alternative clock source selection CRAMs
wire    [2:0]  rrefclk_sel_ch1;	      // RXPLL alternative clock source selection CRAMs
wire    [2:0]  rrefclk_sel_ch2;	      // RXPLL alternative clock source selection CRAMs
wire    [2:0]  rrefclk_sel_ch3;	      // RXPLL alternative clock source selection CRAMs
wire    [3:0]  rs_lpbk;		      // Serial loopback CRAM
wire    [3:0]  r_rlpbk;	              // Reverse serial loopback CRAM for RX channel
wire    [3:0]  rs_rdlpbk;	      // Serial reversed diagnostic loopback CRAM
wire    [3:0]  rrx_revlb_sw;	      // Reverse loopback switch CRAM
wire    [1:0]  risel_rx_ch0;	      // RXPLL charge pump current control CRAM
wire    [1:0]  risel_rx_ch1;	      // RXPLL charge pump current control CRAM
wire    [1:0]  risel_rx_ch2;	      // RXPLL charge pump current control CRAM
wire    [1:0]  risel_rx_ch3;	      // RXPLL charge pump current control CRAM
wire    [1:0]  riupsel_rx_ch0;	      // Intentionally mismatch UP/DN current CRAMs control (Iup)
wire    [1:0]  riupsel_rx_ch1;	      // Intentionally mismatch UP/DN current CRAMs control (Iup)
wire    [1:0]  riupsel_rx_ch2;	      // Intentionally mismatch UP/DN current CRAMs control (Iup)
wire    [1:0]  riupsel_rx_ch3;	      // Intentionally mismatch UP/DN current CRAMs control (Iup)
wire    [1:0]  ridnsel_rx_ch0;	      // Intentionally mismatch UP/DN current CRAMs control (Idn)
wire    [1:0]  ridnsel_rx_ch1;	      // Intentionally mismatch UP/DN current CRAMs control (Idn)
wire    [1:0]  ridnsel_rx_ch2;	      // Intentionally mismatch UP/DN current CRAMs control (Idn)
wire    [1:0]  ridnsel_rx_ch3;	      // Intentionally mismatch UP/DN current CRAMs control (Idn)
wire    [3:0]  rtesten_cp_rx;	      // Charge pump test mode control CRAM in RXPLL
wire    [3:0]  rtristate_cp_rx;	      // Charge pump tristate control CRAM in RXPLL
wire    [3:0]  rtestupen_cp_rx;       // Charge pump current test control CRAM in RXPLL
wire    [3:0]  rtestdnen_cp_rx;       // Charge pump current test control CRAM in RXPLL
wire    [2:0]  rrx_vtt_ch0;	      // Programmable termination voltage setting CRAM
wire    [2:0]  rrx_vtt_ch1;	      // Programmable termination voltage setting CRAM
wire    [2:0]  rrx_vtt_ch2;	      // Programmable termination voltage setting CRAM
wire    [2:0]  rrx_vtt_ch3;	      // Programmable termination voltage setting CRAM
wire    [3:0]  rlst_rx_ch0;	      // Low speed test selection CRAM
wire    [3:0]  rlst_rx_ch1;	      // Low speed test selection CRAM
wire    [3:0]  rlst_rx_ch2;	      // Low speed test selection CRAM
wire    [3:0]  rlst_rx_ch3;	      // Low speed test selection CRAM
wire    [3:0]  rlst_rxpll_ch0;	      // Low speed test selection CRAM
wire    [3:0]  rlst_rxpll_ch1;	      // Low speed test selection CRAM
wire    [3:0]  rlst_rxpll_ch2;	      // Low speed test selection CRAM
wire    [3:0]  rlst_rxpll_ch3;	      // Low speed test selection CRAM
wire    [3:0]  rltr;		      // Lock to reference clock enable CRAM
wire    [3:0]  rltd;		      // Lock to received data enable CRAM
wire    [3:0]  rrx_cru_m_ch0;	      // Programmable M control CRAM
wire    [3:0]  rrx_cru_m_ch1;	      // Programmable M control CRAM
wire    [3:0]  rrx_cru_m_ch2;	      // Programmable M control CRAM
wire    [3:0]  rrx_cru_m_ch3;	      // Programmable M control CRAM
wire    [1:0]  rrx_cru_l_ch0;	      // Programmable L contrl CRAM
wire    [1:0]  rrx_cru_l_ch1;	      // Programmable L contrl CRAM
wire    [1:0]  rrx_cru_l_ch2;	      // Programmable L contrl CRAM
wire    [1:0]  rrx_cru_l_ch3;	      // Programmable L contrl CRAM
wire    [3:0]  rrx_ignore_phslck;     // Ignore phase lock CRAM
wire    [5:0]  rrx_cru_ctl_ch0;	      // Programmable control CRAM
wire    [5:0]  rrx_cru_ctl_ch1;	      // Programmable control CRAM
wire    [5:0]  rrx_cru_ctl_ch2;	      // Programmable control CRAM
wire    [5:0]  rrx_cru_ctl_ch3;	      // Programmable control CRAM
wire    [3:0]  rreg_cp_rx;	      // RX PLL charge pump regulator enable CRAM
wire    [1:0]  rrx_piso_bypass_ch0;   // Reference bypass around PISO CRAM
wire    [1:0]  rrx_piso_bypass_ch1;   // Reference bypass around PISO CRAM
wire    [1:0]  rrx_piso_bypass_ch2;   // Reference bypass around PISO CRAM
wire    [1:0]  rrx_piso_bypass_ch3;   // Reference bypass around PISO CRAM
wire    [1:0]  rrx_cru_m_sel_ch0;     // Division ratio CRAM selection of input clock in CDR
wire    [1:0]  rrx_cru_m_sel_ch1;     // Division ratio CRAM selection of input clock in CDR
wire    [1:0]  rrx_cru_m_sel_ch2;     // Division ratio CRAM selection of input clock in CDR
wire    [1:0]  rrx_cru_m_sel_ch3;     // Division ratio CRAM selection of input clock in CDR
wire    [3:0]  rrx_cru_div2;	      // Reference clock divided by 2 enable CRAM
wire    [3:0]  rrx_osc_en;	      // CGB RX OSC enable CRAM
wire    [3:0]  rrx_cru_pdb;	      // Power down (bar) CRAM for CRU
wire    [3:0]  rrx_cru_rst;	      // Reset CRAM for PLL in CRU
wire    [3:0]  rrx_ib_pdb;	      // Power down (bar) for input buffer
wire    [3:0]  rurx_pdb;              // Enable CRAM for URX_PDB dynamic signal
wire    [3:0]  radce_pdb;             // Power down for adaptive equalization
wire    [3:0]  radce_rst;             // Reset CRAM for counters in adaptive engine
wire    [3:0]  rrxurstpma;            // Enable CRAM for RXURSTPMA dynamic signal
wire    [3:0]  rrx_dc_couple;         // Programmable DC couple CRAM for RX input buffer
wire    [1:0]  rrx_eq_dc_ch0;         // CRAMs for Equalizer block
wire    [1:0]  rrx_eq_dc_ch1;         // CRAMs for Equalizer block
wire    [1:0]  rrx_eq_dc_ch2;         // CRAMs for Equalizer block
wire    [1:0]  rrx_eq_dc_ch3;         // CRAMs for Equalizer block
wire    [3:0]  radce_adapt;           // Continuous adaptation enable CRAM
wire    [1:0]  rseq_sel_ch0;          // Sequence of adaptation selection CRAMs
wire    [1:0]  rseq_sel_ch1;          // Sequence of adaptation selection CRAMs
wire    [1:0]  rseq_sel_ch2;          // Sequence of adaptation selection CRAMs
wire    [1:0]  rseq_sel_ch3;          // Sequence of adaptation selection CRAMs
wire    [2:0]  rrgen_set_ch0;         // D2A control CRAMs
wire    [2:0]  rrgen_set_ch1;         // D2A control CRAMs
wire    [2:0]  rrgen_set_ch2;         // D2A control CRAMs
wire    [2:0]  rrgen_set_ch3;         // D2A control CRAMs
wire    [3:0]  rclkdiv_ch0;           // Division ration selection CRAMs for adaptation engine
wire    [3:0]  rclkdiv_ch1;           // Division ration selection CRAMs for adaptation engine
wire    [3:0]  rclkdiv_ch2;           // Division ration selection CRAMs for adaptation engine
wire    [3:0]  rclkdiv_ch3;           // Division ration selection CRAMs for adaptation engine
wire    [1:0]  rf_lpf_ch0;            // LPF corner frequency setting CRAMs
wire    [1:0]  rf_lpf_ch1;            // LPF corner frequency setting CRAMs
wire    [1:0]  rf_lpf_ch2;            // LPF corner frequency setting CRAMs
wire    [1:0]  rf_lpf_ch3;            // LPF corner frequency setting CRAMs
wire    [1:0]  rf_hpf_ch0;            // HPF corner frequency setting CRAMs
wire    [1:0]  rf_hpf_ch1;            // HPF corner frequency setting CRAMs
wire    [1:0]  rf_hpf_ch2;            // HPF corner frequency setting CRAMs
wire    [1:0]  rf_hpf_ch3;            // HPF corner frequency setting CRAMs
wire    [1:0]  rrgen_bw_ch0;          // RGEN corner frequency setting CRAMs
wire    [1:0]  rrgen_bw_ch1;          // RGEN corner frequency setting CRAMs
wire    [1:0]  rrgen_bw_ch2;          // RGEN corner frequency setting CRAMs
wire    [1:0]  rrgen_bw_ch3;          // RGEN corner frequency setting CRAMs
wire    [2:0]  rhyst_ch0;             // Programmable digital filtering setting CRAMs
wire    [2:0]  rhyst_ch1;             // Programmable digital filtering setting CRAMs
wire    [2:0]  rhyst_ch2;             // Programmable digital filtering setting CRAMs
wire    [2:0]  rhyst_ch3;             // Programmable digital filtering setting CRAMs
wire    [1:0]  rrect_adj_ch0;         // Rectifier leaker current setting CRAMs
wire    [1:0]  rrect_adj_ch1;         // Rectifier leaker current setting CRAMs
wire    [1:0]  rrect_adj_ch2;         // Rectifier leaker current setting CRAMs
wire    [1:0]  rrect_adj_ch3;         // Rectifier leaker current setting CRAMs
wire    [1:0]  rd2a_res_ch0;          // D2A resolution settting CRAMs
wire    [1:0]  rd2a_res_ch1;          // D2A resolution settting CRAMs
wire    [1:0]  rd2a_res_ch2;          // D2A resolution settting CRAMs
wire    [1:0]  rd2a_res_ch3;          // D2A resolution settting CRAMs
wire    [2:0]  rrgen_vod_ch0;         // RGEN amplitude setting CRAMs
wire    [2:0]  rrgen_vod_ch1;         // RGEN amplitude setting CRAMs
wire    [2:0]  rrgen_vod_ch2;         // RGEN amplitude setting CRAMs
wire    [2:0]  rrgen_vod_ch3;         // RGEN amplitude setting CRAMs
wire    [3:0]  rlf_os_ch0;            // Low freq. loop offset cancelling setting CRAMs
wire    [3:0]  rlf_os_ch1;            // Low freq. loop offset cancelling setting CRAMs
wire    [3:0]  rlf_os_ch2;            // Low freq. loop offset cancelling setting CRAMs
wire    [3:0]  rlf_os_ch3;            // Low freq. loop offset cancelling setting CRAMs
wire    [3:0]  rhf_os_ch0;            // High freq. loop offset cancelling setting CRAMs
wire    [3:0]  rhf_os_ch1;            // High freq. loop offset cancelling setting CRAMs
wire    [3:0]  rhf_os_ch2;            // High freq. loop offset cancelling setting CRAMs
wire    [3:0]  rhf_os_ch3;            // High freq. loop offset cancelling setting CRAMs
wire    [2:0]  reqa_ct_ch0;           // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqa_ct_ch1;           // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqa_ct_ch2;           // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqa_ct_ch3;           // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqb_ct_ch0;           // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqb_ct_ch1;           // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqb_ct_ch2;           // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqb_ct_ch3;           // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqc_ct_ch0;           // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqc_ct_ch1;           // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqc_ct_ch2;           // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqc_ct_ch3;           // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqd_ct_ch0;           // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqd_ct_ch1;           // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqd_ct_ch2;           // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqd_ct_ch3;           // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire    [2:0]  req_ctv_ch0;           // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire    [2:0]  req_ctv_ch1;           // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire    [2:0]  req_ctv_ch2;           // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire    [2:0]  req_ctv_ch3;           // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire    [1:0]  rdc_freq_ch0;          // ADCE CRAM
wire    [1:0]  rdc_freq_ch1;          // ADCE CRAM
wire    [1:0]  rdc_freq_ch2;          // ADCE CRAM
wire    [1:0]  rdc_freq_ch3;          // ADCE CRAM
wire    [3:0]  r_iqclk_ch0;           // IQCLK selection CRAM
wire    [3:0]  r_iqclk_ch1;           // IQCLK selection CRAM
wire    [3:0]  r_iqclk_ch2;           // IQCLK selection CRAM
wire    [3:0]  r_iqclk_ch3;           // IQCLK selection CRAM
wire    [5:0]  r_dfe_ch0;             // DFE CRAM
wire    [5:0]  r_dfe_ch1;             // DFE CRAM
wire    [5:0]  r_dfe_ch2;             // DFE CRAM
wire    [5:0]  r_dfe_ch3;             // DFE CRAM
wire    [3:0]  r_cp_mode;             // CP mode CRAM
wire    [1:0]  r_impctrl_ch0;         // IMPCTRL CRAM
wire    [1:0]  r_impctrl_ch1;         // IMPCTRL CRAM
wire    [1:0]  r_impctrl_ch2;         // IMPCTRL CRAM
wire    [1:0]  r_impctrl_ch3;         // IMPCTRL CRAM
wire    [3:0]  rpd_ien;               // PD current setting CRAM
wire    [2:0]  rrsvd_rx_ch0;          // Rerserved CRAMs for both RX PCS and RX PMA
wire    [2:0]  rrsvd_rx_ch1;          // Rerserved CRAMs for both RX PCS and RX PMA
wire    [2:0]  rrsvd_rx_ch2;          // Rerserved CRAMs for both RX PCS and RX PMA
wire    [2:0]  rrsvd_rx_ch3;          // Rerserved CRAMs for both RX PCS and RX PMA

// RX PMA CRAM outputs to RX PMAs ----------------------------------------------------------------------
/*
wire     [3:0]  rpmadwidth_rx_int;       // RX PMA to RX PCS data width sel CRAMs
wire     [3:0]  rpma_doublewidth_rx_int; // RX PMA/PCS double width (16/20) sel CRAM
wire     [2:0]  rrx_sloslv_ch0_int;	// Signal loss threshold select CRAMs
wire     [2:0]  rrx_sloslv_ch1_int;	// Signal loss threshold select CRAMs
wire     [2:0]  rrx_sloslv_ch2_int;	// Signal loss threshold select CRAMs
wire     [2:0]  rrx_sloslv_ch3_int;	// Signal loss threshold select CRAMs
wire     [1:0]  rrx_term_ch0_int;        // RX input buffer termination select CRAMs
wire     [1:0]  rrx_term_ch1_int;        // RX input buffer termination select CRAMs
wire     [1:0]  rrx_term_ch2_int;        // RX input buffer termination select CRAMs
wire     [1:0]  rrx_term_ch3_int;        // RX input buffer termination select CRAMs
wire     [3:0]  rrxvcobypass_int;	// RX VCO bypass CRAM
wire     [1:0]  rbwctral_rx_ch0_int;	// RX PLL loop filter bandwidth control CRAMs
wire     [1:0]  rbwctral_rx_ch1_int;	// RX PLL loop filter bandwidth control CRAMs
wire     [1:0]  rbwctral_rx_ch2_int;	// RX PLL loop filter bandwidth control CRAMs
wire     [1:0]  rbwctral_rx_ch3_int;	// RX PLL loop filter bandwidth control CRAMs
wire     [3:0]  rforce_sigdet_int;       // SIGDET forcing CRAM
wire     [2:0]  rrefclk_sel_ch0_int;	// RXPLL alternative clock source selection CRAMs
wire     [2:0]  rrefclk_sel_ch1_int;	// RXPLL alternative clock source selection CRAMs
wire     [2:0]  rrefclk_sel_ch2_int;	// RXPLL alternative clock source selection CRAMs
wire     [2:0]  rrefclk_sel_ch3_int;	// RXPLL alternative clock source selection CRAMs
wire     [3:0]  rs_lpbk_int;		// Serial loopback CRAM
wire     [3:0]  r_rlpbk_int;	        // Reverse serial loopback CRAM for RX channel
wire     [3:0]  rs_rdlpbk_int;	        // Serial reversed diagnostic loopback CRAM
wire     [3:0]  rrx_revlb_sw_int;	// Reverse loopback switch CRAM
wire     [1:0]  risel_rx_ch0_int;	// RXPLL charge pump current control CRAM
wire     [1:0]  risel_rx_ch1_int;	// RXPLL charge pump current control CRAM
wire     [1:0]  risel_rx_ch2_int;	// RXPLL charge pump current control CRAM
wire     [1:0]  risel_rx_ch3_int;	// RXPLL charge pump current control CRAM
wire     [1:0]  riupsel_rx_ch0_int;	// Intentionally mismatch UP/DN current CRAMs control (Iup)
wire     [1:0]  riupsel_rx_ch1_int;	// Intentionally mismatch UP/DN current CRAMs control (Iup)
wire     [1:0]  riupsel_rx_ch2_int;	// Intentionally mismatch UP/DN current CRAMs control (Iup)
wire     [1:0]  riupsel_rx_ch3_int;	// Intentionally mismatch UP/DN current CRAMs control (Iup)
wire     [1:0]  ridnsel_rx_ch0_int;	// Intentionally mismatch UP/DN current CRAMs control (Idn)
wire     [1:0]  ridnsel_rx_ch1_int;	// Intentionally mismatch UP/DN current CRAMs control (Idn)
wire     [1:0]  ridnsel_rx_ch2_int;	// Intentionally mismatch UP/DN current CRAMs control (Idn)
wire     [1:0]  ridnsel_rx_ch3_int;	// Intentionally mismatch UP/DN current CRAMs control (Idn)
wire     [3:0]  rtesten_cp_rx_int;	// Charge pump test mode control CRAM in RXPLL
wire     [3:0]  rtristate_cp_rx_int;	// Charge pump tristate control CRAM in RXPLL
wire     [3:0]  rtestupen_cp_rx_int;     // Charge pump current test control CRAM in RXPLL
wire     [3:0]  rtestdnen_cp_rx_int;     // Charge pump current test control CRAM in RXPLL
wire     [2:0]  rrx_vtt_ch0_int;	        // Programmable termination voltage setting CRAM
wire     [2:0]  rrx_vtt_ch1_int;	        // Programmable termination voltage setting CRAM
wire     [2:0]  rrx_vtt_ch2_int;	        // Programmable termination voltage setting CRAM
wire     [2:0]  rrx_vtt_ch3_int;	        // Programmable termination voltage setting CRAM
wire     [3:0]  rlst_rx_ch0_int;	        // Low speed test selection CRAM
wire     [3:0]  rlst_rx_ch1_int;	        // Low speed test selection CRAM
wire     [3:0]  rlst_rx_ch2_int;	        // Low speed test selection CRAM
wire     [3:0]  rlst_rx_ch3_int;	        // Low speed test selection CRAM
wire     [3:0]  rlst_rxpll_ch0_int;	// Low speed test selection CRAM
wire     [3:0]  rlst_rxpll_ch1_int;	// Low speed test selection CRAM
wire     [3:0]  rlst_rxpll_ch2_int;	// Low speed test selection CRAM
wire     [3:0]  rlst_rxpll_ch3_int;	// Low speed test selection CRAM
wire     [3:0]  rltr_int;		// Lock to reference clock enable CRAM
wire     [3:0]  rltd_int;		// Lock to received data enable CRAM
wire     [3:0]  rrx_cru_m_ch0_int;	// Programmable M control CRAM
wire     [3:0]  rrx_cru_m_ch1_int;	// Programmable M control CRAM
wire     [3:0]  rrx_cru_m_ch2_int;	// Programmable M control CRAM
wire     [3:0]  rrx_cru_m_ch3_int;	// Programmable M control CRAM
wire     [1:0]  rrx_cru_l_ch0_int;	// Programmable L contrl CRAM
wire     [1:0]  rrx_cru_l_ch1_int;	// Programmable L contrl CRAM
wire     [1:0]  rrx_cru_l_ch2_int;	// Programmable L contrl CRAM
wire     [1:0]  rrx_cru_l_ch3_int;	// Programmable L contrl CRAM
wire     [3:0]  rrx_ignore_phslck_int;   // Ignore phase lock CRAM
wire     [5:0]  rrx_cru_ctl_ch0_int;	// Programmable control CRAM
wire     [5:0]  rrx_cru_ctl_ch1_int;	// Programmable control CRAM
wire     [5:0]  rrx_cru_ctl_ch2_int;	// Programmable control CRAM
wire     [5:0]  rrx_cru_ctl_ch3_int;	// Programmable control CRAM
wire     [3:0]  rreg_cp_rx_int;	        // RX PLL charge pump regulator enable CRAM
wire     [1:0]  rrx_piso_bypass_ch0_int; // Reference bypass around PISO CRAM
wire     [1:0]  rrx_piso_bypass_ch1_int; // Reference bypass around PISO CRAM
wire     [1:0]  rrx_piso_bypass_ch2_int; // Reference bypass around PISO CRAM
wire     [1:0]  rrx_piso_bypass_ch3_int; // Reference bypass around PISO CRAM
wire     [1:0]  rrx_cru_m_sel_ch0_int;   // Division ratio CRAM selection of input clock in CDR
wire     [1:0]  rrx_cru_m_sel_ch1_int;   // Division ratio CRAM selection of input clock in CDR
wire     [1:0]  rrx_cru_m_sel_ch2_int;   // Division ratio CRAM selection of input clock in CDR
wire     [1:0]  rrx_cru_m_sel_ch3_int;   // Division ratio CRAM selection of input clock in CDR
wire     [3:0]  rrx_cru_div2_int;	// Reference clock divided by 2 enable CRAM
wire     [3:0]  rrx_osc_en_int;	        // CGB RX OSC enable CRAM
wire     [3:0]  rrx_cru_pdb_int;	        // Power down (bar) CRAM for CRU
wire     [3:0]  rrx_cru_rst_int;	        // Reset CRAM for PLL in CRU
wire     [3:0]  rrx_ib_pdb_int;	        // Power down (bar) for input buffer
//wire     [3:0]  rrx_sipo_pdb_int;	// Power down (bar) for SIPO
wire     [3:0]  rurx_pdb_int;            // Enable CRAM for URX_PDB dynamic signal
wire     [3:0]  radce_pdb_int;           // Power down for adaptive equalization
wire     [3:0]  radce_rst_int;           // Reset CRAM for counters in adaptive engine
wire     [3:0]  rrx_dc_couple_int;       // Programmable DC couple CRAM for RX outputbuffer
wire     [1:0]  rrx_eq_dc_ch0_int;       // CRAMs for Equalizer block
wire     [1:0]  rrx_eq_dc_ch1_int;       // CRAMs for Equalizer block
wire     [1:0]  rrx_eq_dc_ch2_int;       // CRAMs for Equalizer block
wire     [1:0]  rrx_eq_dc_ch3_int;       // CRAMs for Equalizer block
wire     [3:0]  radce_adapt_int;         // Continuous adaptation enable CRAM
wire     [1:0]  rseq_sel_ch0_int;        // Sequence of adaptation selection CRAMs
wire     [1:0]  rseq_sel_ch1_int;        // Sequence of adaptation selection CRAMs
wire     [1:0]  rseq_sel_ch2_int;        // Sequence of adaptation selection CRAMs
wire     [1:0]  rseq_sel_ch3_int;        // Sequence of adaptation selection CRAMs
wire     [2:0]  rrgen_set_ch0_int;       // D2A control CRAMs
wire     [2:0]  rrgen_set_ch1_int;       // D2A control CRAMs
wire     [2:0]  rrgen_set_ch2_int;       // D2A control CRAMs
wire     [2:0]  rrgen_set_ch3_int;       // D2A control CRAMs
wire     [3:0]  rclkdiv_ch0_int;         // Division ration selection CRAMs for adaptation engine
wire     [3:0]  rclkdiv_ch1_int;         // Division ration selection CRAMs for adaptation engine
wire     [3:0]  rclkdiv_ch2_int;         // Division ration selection CRAMs for adaptation engine
wire     [3:0]  rclkdiv_ch3_int;         // Division ration selection CRAMs for adaptation engine
wire     [1:0]  rf_lpf_ch0_int;          // LPF corner frequency setting CRAMs
wire     [1:0]  rf_lpf_ch1_int;          // LPF corner frequency setting CRAMs
wire     [1:0]  rf_lpf_ch2_int;          // LPF corner frequency setting CRAMs
wire     [1:0]  rf_lpf_ch3_int;          // LPF corner frequency setting CRAMs
wire     [1:0]  rf_hpf_ch0_int;          // HPF corner frequency setting CRAMs
wire     [1:0]  rf_hpf_ch1_int;          // HPF corner frequency setting CRAMs
wire     [1:0]  rf_hpf_ch2_int;          // HPF corner frequency setting CRAMs
wire     [1:0]  rf_hpf_ch3_int;          // HPF corner frequency setting CRAMs
wire     [1:0]  rrgen_bw_ch0_int;        // RGEN corner frequency setting CRAMs
wire     [1:0]  rrgen_bw_ch1_int;        // RGEN corner frequency setting CRAMs
wire     [1:0]  rrgen_bw_ch2_int;        // RGEN corner frequency setting CRAMs
wire     [1:0]  rrgen_bw_ch3_int;        // RGEN corner frequency setting CRAMs
wire     [2:0]  rhyst_ch0_int;           // Programmable digital filtering setting CRAMs
wire     [2:0]  rhyst_ch1_int;           // Programmable digital filtering setting CRAMs
wire     [2:0]  rhyst_ch2_int;           // Programmable digital filtering setting CRAMs
wire     [2:0]  rhyst_ch3_int;           // Programmable digital filtering setting CRAMs
wire     [1:0]  rrect_adj_ch0_int;       // Rectifier leaker current setting CRAMs
wire     [1:0]  rrect_adj_ch1_int;       // Rectifier leaker current setting CRAMs
wire     [1:0]  rrect_adj_ch2_int;       // Rectifier leaker current setting CRAMs
wire     [1:0]  rrect_adj_ch3_int;       // Rectifier leaker current setting CRAMs
wire     [1:0]  rd2a_res_ch0_int;        // D2A resolution settting CRAMs
wire     [1:0]  rd2a_res_ch1_int;        // D2A resolution settting CRAMs
wire     [1:0]  rd2a_res_ch2_int;        // D2A resolution settting CRAMs
wire     [1:0]  rd2a_res_ch3_int;        // D2A resolution settting CRAMs
wire     [2:0]  rrgen_vod_ch0_int;       // RGEN amplitude setting CRAMs
wire     [2:0]  rrgen_vod_ch1_int;       // RGEN amplitude setting CRAMs
wire     [2:0]  rrgen_vod_ch2_int;       // RGEN amplitude setting CRAMs
wire     [2:0]  rrgen_vod_ch3_int;       // RGEN amplitude setting CRAMs
wire     [3:0]  rlf_os_ch0_int;          // Low freq. loop offset cancelling setting CRAMs
wire     [3:0]  rlf_os_ch1_int;          // Low freq. loop offset cancelling setting CRAMs
wire     [3:0]  rlf_os_ch2_int;          // Low freq. loop offset cancelling setting CRAMs
wire     [3:0]  rlf_os_ch3_int;          // Low freq. loop offset cancelling setting CRAMs
wire     [3:0]  rhf_os_ch0_int;          // High freq. loop offset cancelling setting CRAMs
wire     [3:0]  rhf_os_ch1_int;          // High freq. loop offset cancelling setting CRAMs
wire     [3:0]  rhf_os_ch2_int;          // High freq. loop offset cancelling setting CRAMs
wire     [3:0]  rhf_os_ch3_int;          // High freq. loop offset cancelling setting CRAMs
wire     [2:0]  reqa_ct_ch0_int;         // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqa_ct_ch1_int;         // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqa_ct_ch2_int;         // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqa_ct_ch3_int;         // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqb_ct_ch0_int;         // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqb_ct_ch1_int;         // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqb_ct_ch2_int;         // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqb_ct_ch3_int;         // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqc_ct_ch0_int;         // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqc_ct_ch1_int;         // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqc_ct_ch2_int;         // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqc_ct_ch3_int;         // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqd_ct_ch0_int;         // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqd_ct_ch1_int;         // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqd_ct_ch2_int;         // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire     [2:0]  reqd_ct_ch3_int;         // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire     [2:0]  req_ctv_ch0_int;         // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire     [2:0]  req_ctv_ch1_int;         // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire     [2:0]  req_ctv_ch2_int;         // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire     [2:0]  req_ctv_ch3_int;         // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire     [1:0]  rdc_freq_ch0_int;        // ADCE CRAM
wire     [1:0]  rdc_freq_ch1_int;        // ADCE CRAM
wire     [1:0]  rdc_freq_ch2_int;        // ADCE CRAM
wire     [1:0]  rdc_freq_ch3_int;        // ADCE CRAM
wire     [3:0]  r_iqclk_ch0_int;         // IQCLK selection CRAM
wire     [3:0]  r_iqclk_ch1_int;         // IQCLK selection CRAM
wire     [3:0]  r_iqclk_ch2_int;         // IQCLK selection CRAM
wire     [3:0]  r_iqclk_ch3_int;         // IQCLK selection CRAM
wire     [5:0]  r_dfe_ch0_int;           // DFE CRAM
wire     [5:0]  r_dfe_ch1_int;           // DFE CRAM
wire     [5:0]  r_dfe_ch2_int;           // DFE CRAM
wire     [5:0]  r_dfe_ch3_int;           // DFE CRAM
wire     [3:0]  r_cp_mode_int;           // CP mode CRAM
wire     [1:0]  r_impctrl_ch0_int;       // IMPCTRL CRAM
wire     [1:0]  r_impctrl_ch1_int;       // IMPCTRL CRAM
wire     [1:0]  r_impctrl_ch2_int;       // IMPCTRL CRAM
wire     [1:0]  r_impctrl_ch3_int;       // IMPCTRL CRAM
wire     [3:0]  rpd_ien_int;             // PD current setting CRAM
wire     [2:0]  rrsvd_rx_ch0_int;        // Rerserved CRAMs for both RX PCS and RX PMA
wire     [2:0]  rrsvd_rx_ch1_int;        // Rerserved CRAMs for both RX PCS and RX PMA
wire     [2:0]  rrsvd_rx_ch2_int;        // Rerserved CRAMs for both RX PCS and RX PMA
wire     [2:0]  rrsvd_rx_ch3_int;        // Rerserved CRAMs for both RX PCS and RX PMA
*/

// CMU PCS CRAMs wire  ----------------------------------------------------------------------
wire           rs_lpbk_all;           // Global serial loopback enable CRAM
wire           rindv_tx;              // TX SM bypassing CRAM
wire           rindv_rx;              // RX SM bypassing CRAM
wire           rdeskewen;             // Deskew function enable CRAM
wire    [1:0]  ralgnect;              // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire    [2:0]  ralgnact;              // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire    [1:0]  ralgngct;              // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire           rdskposdisp;           // Match the programmed de-skew pattern only
wire    [9:0]  rdskchrp;              // Programmable Deskew Char. Pos. Disp.
wire           ralgnopt;              // De-skew SM Hysteresis Option
wire           rfreerun_centrl;       // REFCLK_OUT free running enable CRAM
wire           rcentrl_clk_sel;       // REFCLK_PMA global clock selection CRAM
wire           rrefclk_out_div2;      // REFCLK_OUT divide by 2 enable CRAM
wire    [2:0]  rtest_bus_centrl_sel;  // Central Test bus selection CRAMs
wire           rendec_data_sel_tx;    // TX 8B10B encoder data in selection CRAM
wire           rendec_data_sel_rx;    // RX 8B10B decoder data out selection CRAM
wire           rphfifo_master_sel_tx; // TX Phase comp. FIFO pointers selection CRAM
wire           rphfifo_master_sel_rx; // TX Phase comp. FIFO pointers selection CRAM

// CMU PCS CRAMs outputs to CMU
wire            rs_lpbk_all_md;        // Output CRAM of RS_LPBK_ALL
/*
wire            rindv_tx_int;          // TX SM bypassing CRAM
wire            rindv_rx_int;          // RX SM bypassing CRAM
wire            rdeskewen_int;         // Deskew function enable CRAM
wire     [1:0]  ralgnect_int;          // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire     [2:0]  ralgnact_int;          // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire     [1:0]  ralgngct_int;          // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire            rdskposdisp_int;       // Match the programmed de-skew pattern only
wire     [9:0]  rdskchrp_int;          // Programmable Deskew Char. Pos. Disp.
wire            ralgnopt_int;          // De-skew SM Hysteresis Option
wire            rfreerun_centrl_int;   // REFCLK_OUT free running enable CRAM
wire            rcentrl_clk_sel_int;   // REFCLK_PMA global clock selection CRAM
wire            rrefclk_out_div2_int;  // REFCLK_OUT divide by 2 enable CRAM
wire     [2:0]  rtest_bus_centrl_sel_int;  // Central Test bus selection CRAMs
wire            rendec_data_sel_tx_int;// TX 8B10B encoder data in selection CRAM
wire            rendec_data_sel_rx_int;// RX 8B10B decoder data out selection CRAM
wire            rphfifo_master_sel_tx_int; // TX Phase comp. FIFO pointers selection CRAM
wire            rphfifo_master_sel_rx_int; // TX Phase comp. FIFO pointers selection CRAM
*/
                                      
// RESET, CMU PMA, and CLKREF CRAMs wire  ----------------------------------------------------------------------
wire           rpowerdown;            // Quad power down CRAM
wire           rnenbpin;              // Gated CRAM for ENPLL pin
wire           rpllurst;              // Gated CRAM for PLLURST
wire           rreset;                // Quad reset CRAM
wire           rbgbypass;	      // Bandgap bypass CRAM
wire   [3:0]   rlst_bg;	              // Programmable test bus setting CRAM
wire           rcmu_rst;	      // Reset CRAM for divider in CMU feedback loop
wire           rcmu_iqclkout_sel;     // REFClock select for going to IQ lines CRAM
wire   [1:0]   rcmu0_isel;	      // TXPLL charge pump current control CRAM
wire   [1:0]   rcmu1_isel;	      // TXPLL charge pump current control CRAM
wire   [1:0]   rcmu0_iupsel;	      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire   [1:0]   rcmu1_iupsel;	      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire   [1:0]   rcmu0_idnsel;	      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire   [1:0]   rcmu1_idnsel;	      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire           rcmu0_testen_cp;       // Charge pump test mode control CRAM in TXPLL0
wire           rcmu1_testen_cp;       // Charge pump test mode control CRAM in TXPLL1
wire           rcmu0_tristate_cp;     // Charge pump tristate control CRAM in TXPLL0
wire           rcmu1_tristate_cp;     // Charge pump tristate control CRAM in TXPLL1
wire           rcmu0_testupen_cp;     // Charge pump current test control CRAM in TXPLL0
wire           rcmu1_testupen_cp;     // Charge pump current test control CRAM in TXPLL1
wire   [3:0]   rcmu0_lst;	      // Low speed test selection CRAM
wire   [3:0]   rcmu1_lst;	      // Low speed test selection CRAM
wire   [7:0]   rcmu0_ctl;	      // Programmable control CRAM
wire   [7:0]   rcmu1_ctl;	      // Programmable control CRAM
wire           rcmu0_div2;	      // Reference clock divided by 2 enable CRAM
wire           rcmu1_div2;	      // Reference clock divided by 2 enable CRAM
wire   [1:0]   rcmu0_ref_sel;	      // Reference selection control CRAM
wire   [1:0]   rcmu1_ref_sel;	      // Reference selection control CRAM
wire   [3:0]   rcmu0_m;	              // Programmable M selection CRAM
wire   [3:0]   rcmu1_m;	              // Programmable M selection CRAM
wire   [1:0]   rcmu0_l;	              // Programmable L selection CRAM
wire   [1:0]   rcmu1_l;	              // Programmable L selection CRAM
wire           rcmu0_pdb;	      // Powerdown (bar)CMU CRAM
wire           rcmu1_pdb;	      // Powerdown (bar)CMU CRAM
wire           rcmu0_txpll_rst;       // TXPLL0 reset CRAM
wire           rcmu1_txpll_rst;       // TXPLL0 reset CRAM
wire           rcmu0_testdnen_cp;     // Charge pump current test control CRAM
wire           rcmu1_testdnen_cp;     // Charge pump current test control CRAM
wire   [3:0]   rcmu_peclrx0_cm;       // Common mode control CRAM
wire   [3:0]   rcmu_peclrx1_cm;       // Common mode control CRAM
wire   [3:0]   rcmu_peclrx0_lst;      // Analog test bus setting CRAM
wire   [3:0]   rcmu_peclrx1_lst;      // Analog test bus setting CRAM
wire           rcmu_txpll0_1x_en;     // 1X enable CRAM in central CGB
wire           rcmu_txpll1_1x_en;     // 1X enable CRAM in central CGB
wire   [2:0]   rcmu_txpll0_iqclkin_sel;// IQ clock selection CRAMs
wire   [2:0]   rcmu_txpll1_iqclkin_sel;// IQ clock selection CRAMs
wire   [1:0]   rcmu_cgb_cmusel;       // Central CGB CMU selection CRAM
wire   [1:0]   rcmu_cgb_ndiv;         // N-divider selection CRAM for wire  clock in central CGB
wire           rcmu_cgb_div5;         // TX PCS to TX PMA data width selection CRAM
wire           rcmu_cgb_div2;         // TX PCS to TX PMA double data width selection CRAM
wire           rcmu_cgb_vcobypass;    // CMU VCO bypass CRAM in central CGB
wire           rcmu_cgb_4x_en;        // Quad channel mode clock driver enable CRAM
wire           rcmu_cgb_8x_en;        // Eight channel mode clock driver enable CRAM
wire           rcmu_cgb_pclksel;      // Central CGB PCLK select CRAM
wire   [1:0]   rcmu2_isel;	      // TXPLL charge pump current control CRAM
wire   [1:0]   rcmu2_iupsel;	      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire   [1:0]   rcmu2_idnsel;	      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire           rcmu2_testen_cp;       // Charge pump test mode control CRAM in TXPLL2
wire           rcmu2_tristate_cp;     // Charge pump tristate control CRAM in TXPLL2
wire           rcmu2_testupen_cp;     // Charge pump current test control CRAM in TXPLL2
wire           rcmu2_testdnen_cp;     // Charge pump current test control CRAM in TXPLL2
wire   [3:0]   rcmu2_lst;	      // Low speed test selection CRAM
wire   [7:0]   rcmu2_ctl;	      // Programmable control CRAM
wire           rcmu2_refsel;          // Reference select CRAM for CMU2
wire   [3:0]   rcmu2_m;	              // Programmable M selection CRAM
wire   [1:0]   rcmu2_l;	              // Programmable L selection CRAM
wire           rcmu2_pdb;	      // Powerdown (bar)CMU CRAM
wire           rcmu2_txpll_rst;       // TXPLL2 reset CRAM
wire           rcmu0_rcp_mode;        // CMU0 charge pump mode select CRAM
wire           rcmu1_rcp_mode;        // CMU1 charge pump mode select CRAM
wire   [3:0]   rpma_testbus_sel;      // PMA testbus selection
wire   [4:0]   rrsvd_cmu;             // Reserved CRAMs for both PMA CMU and PCS CMU

// CMU PMA, and CLKREF CRAMs outputs ----------------------------------------------------------------------
/*
wire            rbgbypass_int;	      // Bandgap bypass CRAM
//wire            ratb_en_int;	      // Analog test bus enable CRAM
wire    [3:0]   rlst_bg_int;	      // Programmable test bus setting CRAM
wire            rcmu_rst_int;	      // Reset CRAM for divider in CMU feedback loop
wire            rcmu_iqclkout_sel_int; // REFClock select for going to IQ lines CRAM
wire    [1:0]   rcmu0_isel_int;	      // TXPLL charge pump current control CRAM
wire    [1:0]   rcmu1_isel_int;	      // TXPLL charge pump current control CRAM
wire    [1:0]   rcmu0_iupsel_int;      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire    [1:0]   rcmu1_iupsel_int;      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire    [1:0]   rcmu0_idnsel_int;      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire    [1:0]   rcmu1_idnsel_int;      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire            rcmu0_testen_cp_int;   // Charge pump test mode control CRAM in TXPLL0
wire            rcmu1_testen_cp_int;   // Charge pump test mode control CRAM in TXPLL1
wire            rcmu0_tristate_cp_int; // Charge pump tristate control CRAM in TXPLL0
wire            rcmu1_tristate_cp_int; // Charge pump tristate control CRAM in TXPLL1
wire            rcmu0_testupen_cp_int; // Charge pump current test control CRAM in TXPLL0
wire            rcmu1_testupen_cp_int; // Charge pump current test control CRAM in TXPLL1
wire    [3:0]   rcmu0_lst_int;	      // Low speed test selection CRAM
wire    [3:0]   rcmu1_lst_int;	      // Low speed test selection CRAM
wire    [7:0]   rcmu0_ctl_int;	      // Programmable control CRAM
wire    [7:0]   rcmu1_ctl_int;	      // Programmable control CRAM
wire            rcmu0_div2_int;	      // Reference clock divided by 2 enable CRAM
wire            rcmu1_div2_int;	      // Reference clock divided by 2 enable CRAM
wire    [1:0]   rcmu0_ref_sel_int;     // Reference selection control CRAM
wire    [1:0]   rcmu1_ref_sel_int;     // Reference selection control CRAM
wire    [3:0]   rcmu0_m_int;	      // Programmable M selection CRAM
wire    [3:0]   rcmu1_m_int;	      // Programmable M selection CRAM
wire    [1:0]   rcmu0_l_int;	      // Programmable L selection CRAM
wire    [1:0]   rcmu1_l_int;	      // Programmable L selection CRAM
wire            rcmu0_pdb_int;	      // Powerdown (bar)CMU CRAM
wire            rcmu1_pdb_int;	      // Powerdown (bar)CMU CRAM
wire            rcmu0_txpll_rst_int;   // TXPLL0 reset CRAM
wire            rcmu1_txpll_rst_int;   // TXPLL0 reset CRAM
wire            rcmu0_testdnen_cp_int; // Charge pump current test control CRAM
wire            rcmu1_testdnen_cp_int; // Charge pump current test control CRAM
wire    [3:0]   rcmu_peclrx0_cm_int;   // Common mode control CRAM
wire    [3:0]   rcmu_peclrx1_cm_int;   // Common mode control CRAM
wire    [3:0]   rcmu_peclrx0_lst_int;  // Analog test bus setting CRAM
wire    [3:0]   rcmu_peclrx1_lst_int;  // Analog test bus setting CRAM
wire            rcmu_txpll0_1x_en_int; // 1X enable CRAM in central CGB
wire            rcmu_txpll1_1x_en_int; // 1X enable CRAM in central CGB
wire    [2:0]   rcmu_txpll0_iqclkin_sel_int;// IQ clock selection CRAMs
wire    [2:0]   rcmu_txpll1_iqclkin_sel_int;// IQ clock selection CRAMs
wire    [1:0]   rcmu_cgb_cmusel_int;   // Central CGB CMU selection CRAM
wire    [1:0]   rcmu_cgb_ndiv_int;     // N-divider selection CRAM for outputclock in central CGB
wire            rcmu_cgb_div5_int;     // TX PCS to TX PMA data width selection CRAM
wire            rcmu_cgb_div2_int;     // TX PCS to TX PMA double data width selection CRAM
wire            rcmu_cgb_vcobypass_int;// CMU VCO bypass CRAM in central CGB
wire            rcmu_cgb_4x_en_int;    // Quad channel mode clock driver enable CRAM
wire            rcmu_cgb_8x_en_int;    // Eight channel mode clock driver enable CRAM
wire            rcmu_cgb_pclksel_int;  // Central CGB PCLK select CRAM
wire    [1:0]   rcmu2_isel_int;	      // TXPLL charge pump current control CRAM
wire    [1:0]   rcmu2_iupsel_int;      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire    [1:0]   rcmu2_idnsel_int;      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire            rcmu2_testen_cp_int;   // Charge pump test mode control CRAM in TXPLL2
wire            rcmu2_tristate_cp_int; // Charge pump tristate control CRAM in TXPLL2
wire            rcmu2_testupen_cp_int; // Charge pump current test control CRAM in TXPLL2
wire            rcmu2_testdnen_cp_int; // Charge pump current test control CRAM in TXPLL2
wire    [3:0]   rcmu2_lst_int;	      // Low speed test selection CRAM
wire    [7:0]   rcmu2_ctl_int;	      // Programmable control CRAM
wire            rcmu2_refsel_int;      // Reference select CRAM for CMU2
wire    [3:0]   rcmu2_m_int;	      // Programmable M selection CRAM
wire    [1:0]   rcmu2_l_int;	      // Programmable L selection CRAM
wire            rcmu2_pdb_int;	      // Powerdown (bar)CMU CRAM
wire            rcmu2_txpll_rst_int;   // TXPLL2 reset CRAM
wire            rcmu0_rcp_mode_int;    // CMU0 charge pump mode select CRAM
wire            rcmu1_rcp_mode_int;    // CMU1 charge pump mode select CRAM
wire     [3:0]  rpma_testbus_sel_int;  // PMA testbus selection
wire     [4:0]  rrsvd_cmu_int;         // Reserved CRAMs for both PMA CMU and PCS CMU
*/

// Output CRAM for Quad reset ----------------------------------------------------------------------
wire            rnenbpin_md;           // Output CRAM of RNENBPIN
wire            rpllurst_md;           // Output CRAM of RPLLURST
wire            rreset_md;             // Output CRAM of RRESET
wire            rpowerdown_md;         // Output CRAM of RPOWERDOWN
wire     [3:0]  rrxurstpcs_md;         // Output CRAM of RRXURSTPCS
wire     [3:0]  rpowdnr_md;            // Output CRAM of RPOWDNR
wire     [3:0]  rtxurstpcs_md;         // Output CRAM of RTXURSTPCS
wire     [3:0]  rpowdnt_md;            // Output CRAM of RPOWDNT
wire     [3:0]  rrxurstpma_md;         // Output CRAM of RRXURSTPMA

//////////////////////////////////////////////////////////////////////////////////////////////////////
//              end of named CRAMs                                                                  //
//////////////////////////////////////////////////////////////////////////////////////////////////////

// MDIO related wires
wire    [15:0] mbus_out;              // 16 bit output data
wire    [127:0] chain;
wire           local_fault;
wire           xs_link_status_rd;
wire           tx_rx_local_fault_status_rd;
wire           xs_tx_local_fault;
wire           xs_rx_local_fault;

// Control and Status register outputs
wire    [15:0] xgxs_ctrl_reg;
wire    [15:0] trunking_mode_reg;
wire    [15:0] pcs_ctrl1_ch0_reg;
wire    [15:0] pcs_ctrl1_ch1_reg;
wire    [15:0] pcs_ctrl1_ch2_reg;
wire    [15:0] pcs_ctrl1_ch3_reg;
wire    [15:0] pcs_ctrl2_ch0_reg;
wire    [15:0] pcs_ctrl2_ch1_reg;
wire    [15:0] pcs_ctrl2_ch2_reg;
wire    [15:0] pcs_ctrl2_ch3_reg;
wire    [15:0] pcs_ctrl3_ch0_reg;
wire    [15:0] pcs_ctrl3_ch1_reg;
wire    [15:0] pcs_ctrl3_ch2_reg;
wire    [15:0] pcs_ctrl3_ch3_reg;
wire    [15:0] pcs_ctrl4_ch0_reg;
wire    [15:0] pcs_ctrl4_ch1_reg;
wire    [15:0] pcs_ctrl4_ch2_reg;
wire    [15:0] pcs_ctrl4_ch3_reg;
wire    [15:0] pcs_ctrl5_ch0_reg;
wire    [15:0] pcs_ctrl5_ch1_reg;
wire    [15:0] pcs_ctrl5_ch2_reg;
wire    [15:0] pcs_ctrl5_ch3_reg;
wire    [15:0] pcs_ctrl6_ch0_reg;
wire    [15:0] pcs_ctrl6_ch1_reg;
wire    [15:0] pcs_ctrl6_ch2_reg;
wire    [15:0] pcs_ctrl6_ch3_reg;
wire    [15:0] pcs_ctrl7_ch0_reg;
wire    [15:0] pcs_ctrl7_ch1_reg;
wire    [15:0] pcs_ctrl7_ch2_reg;
wire    [15:0] pcs_ctrl7_ch3_reg;
wire    [15:0] pcs_ctrl8_ch0_reg;
wire    [15:0] pcs_ctrl8_ch1_reg;
wire    [15:0] pcs_ctrl8_ch2_reg;
wire    [15:0] pcs_ctrl8_ch3_reg;
wire    [15:0] prbs_bist_ctrl_ch0_reg;
wire    [15:0] prbs_bist_ctrl_ch1_reg;
wire    [15:0] prbs_bist_ctrl_ch2_reg;
wire    [15:0] prbs_bist_ctrl_ch3_reg;
wire    [15:0] pcs_ctrl9_ch0_reg;
wire    [15:0] pcs_ctrl9_ch1_reg;
wire    [15:0] pcs_ctrl9_ch2_reg;
wire    [15:0] pcs_ctrl9_ch3_reg;
wire    [15:0] pcs_ctrl10_ch0_reg;
wire    [15:0] pcs_ctrl10_ch1_reg;
wire    [15:0] pcs_ctrl10_ch2_reg;
wire    [15:0] pcs_ctrl10_ch3_reg;
wire    [15:0] pcs_ctrl11_ch0_reg;
wire    [15:0] pcs_ctrl11_ch1_reg;
wire    [15:0] pcs_ctrl11_ch2_reg;
wire    [15:0] pcs_ctrl11_ch3_reg;
wire    [15:0] pcs_ctrl12_ch0_reg;
wire    [15:0] pcs_ctrl12_ch1_reg;
wire    [15:0] pcs_ctrl12_ch2_reg;
wire    [15:0] pcs_ctrl12_ch3_reg;
wire    [15:0] pcs_ctrl13_ch0_reg;
wire    [15:0] pcs_ctrl13_ch1_reg;
wire    [15:0] pcs_ctrl13_ch2_reg;
wire    [15:0] pcs_ctrl13_ch3_reg;
wire    [15:0] pcs_ctrl14_ch0_reg;
wire    [15:0] pcs_ctrl14_ch1_reg;
wire    [15:0] pcs_ctrl14_ch2_reg;
wire    [15:0] pcs_ctrl14_ch3_reg;
wire    [15:0] pcs_ctrl15_ch0_reg;
wire    [15:0] pcs_ctrl15_ch1_reg;
wire    [15:0] pcs_ctrl15_ch2_reg;
wire    [15:0] pcs_ctrl15_ch3_reg;
wire    [15:0] pcs_global_ctrl0_reg;
wire    [15:0] pcs_global_ctrl1_reg;
wire    [15:0] pcs_global_ctrl2_reg;

wire    [15:0] pma_ctrl1_ch0_reg;
wire    [15:0] pma_ctrl1_ch1_reg;
wire    [15:0] pma_ctrl1_ch2_reg;
wire    [15:0] pma_ctrl1_ch3_reg;
wire    [15:0] pma_ctrl2_ch0_reg;
wire    [15:0] pma_ctrl2_ch1_reg;
wire    [15:0] pma_ctrl2_ch2_reg;
wire    [15:0] pma_ctrl2_ch3_reg;
wire    [15:0] pma_ctrl3_ch0_reg;
wire    [15:0] pma_ctrl3_ch1_reg;
wire    [15:0] pma_ctrl3_ch2_reg;
wire    [15:0] pma_ctrl3_ch3_reg;
wire    [15:0] pma_ctrl4_ch0_reg;
wire    [15:0] pma_ctrl4_ch1_reg;
wire    [15:0] pma_ctrl4_ch2_reg;
wire    [15:0] pma_ctrl4_ch3_reg;
wire    [15:0] pma_ctrl5_ch0_reg;
wire    [15:0] pma_ctrl5_ch1_reg;
wire    [15:0] pma_ctrl5_ch2_reg;
wire    [15:0] pma_ctrl5_ch3_reg;
wire    [15:0] pma_ctrl6_ch0_reg;
wire    [15:0] pma_ctrl6_ch1_reg;
wire    [15:0] pma_ctrl6_ch2_reg;
wire    [15:0] pma_ctrl6_ch3_reg;
wire    [15:0] pma_ctrl7_ch0_reg;
wire    [15:0] pma_ctrl7_ch1_reg;
wire    [15:0] pma_ctrl7_ch2_reg;
wire    [15:0] pma_ctrl7_ch3_reg;
wire    [15:0] pma_ctrl8_ch0_reg;
wire    [15:0] pma_ctrl8_ch1_reg;
wire    [15:0] pma_ctrl8_ch2_reg;
wire    [15:0] pma_ctrl8_ch3_reg;
wire    [15:0] pma_ctrl9_ch0_reg;
wire    [15:0] pma_ctrl9_ch1_reg;
wire    [15:0] pma_ctrl9_ch2_reg;
wire    [15:0] pma_ctrl9_ch3_reg;
wire    [15:0] pma_ctrl10_ch0_reg;
wire    [15:0] pma_ctrl10_ch1_reg;
wire    [15:0] pma_ctrl10_ch2_reg;
wire    [15:0] pma_ctrl10_ch3_reg;
wire    [15:0] pma_ctrl11_ch0_reg;
wire    [15:0] pma_ctrl11_ch1_reg;
wire    [15:0] pma_ctrl11_ch2_reg;
wire    [15:0] pma_ctrl11_ch3_reg;
wire    [15:0] pma_global_ctrl0_reg;
wire    [15:0] pma_global_ctrl1_reg;
wire    [15:0] pma_global_ctrl2_reg;
wire    [15:0] pma_global_ctrl3_reg;
wire    [15:0] pma_global_ctrl4_reg;
wire    [15:0] pma_global_ctrl5_reg;
wire    [15:0] pma_global_ctrl6_reg;
wire    [15:0] pma_global_ctrl7_reg;
wire    [15:0] pma_global_ctrl8_reg;
wire    [15:0] pma_global_ctrl9_reg;

wire    [15:0] xgxs_stat1_reg;    
wire    [15:0] xgxs_stat2_reg;    
wire    [15:0] xgxs_lane_stat_reg;

// External inputs for control registers
wire    [15:0] xgxs_ctrl_ext;
wire    [15:0] trunking_mode_ext;
wire    [15:0] pcs_ctrl1_ch0_ext;
wire    [15:0] pcs_ctrl1_ch1_ext;
wire    [15:0] pcs_ctrl1_ch2_ext;
wire    [15:0] pcs_ctrl1_ch3_ext;
wire    [15:0] pcs_ctrl2_ch0_ext;
wire    [15:0] pcs_ctrl2_ch1_ext;
wire    [15:0] pcs_ctrl2_ch2_ext;
wire    [15:0] pcs_ctrl2_ch3_ext;
wire    [15:0] pcs_ctrl3_ch0_ext;
wire    [15:0] pcs_ctrl3_ch1_ext;
wire    [15:0] pcs_ctrl3_ch2_ext;
wire    [15:0] pcs_ctrl3_ch3_ext;
wire    [15:0] pcs_ctrl4_ch0_ext;
wire    [15:0] pcs_ctrl4_ch1_ext;
wire    [15:0] pcs_ctrl4_ch2_ext;
wire    [15:0] pcs_ctrl4_ch3_ext;
wire    [15:0] pcs_ctrl5_ch0_ext;
wire    [15:0] pcs_ctrl5_ch1_ext;
wire    [15:0] pcs_ctrl5_ch2_ext;
wire    [15:0] pcs_ctrl5_ch3_ext;
wire    [15:0] pcs_ctrl6_ch0_ext;
wire    [15:0] pcs_ctrl6_ch1_ext;
wire    [15:0] pcs_ctrl6_ch2_ext;
wire    [15:0] pcs_ctrl6_ch3_ext;
wire    [15:0] pcs_ctrl7_ch0_ext;
wire    [15:0] pcs_ctrl7_ch1_ext;
wire    [15:0] pcs_ctrl7_ch2_ext;
wire    [15:0] pcs_ctrl7_ch3_ext;
wire    [15:0] pcs_ctrl8_ch0_ext;
wire    [15:0] pcs_ctrl8_ch1_ext;
wire    [15:0] pcs_ctrl8_ch2_ext;
wire    [15:0] pcs_ctrl8_ch3_ext;
wire    [15:0] prbs_bist_ctrl_ch0_ext;
wire    [15:0] prbs_bist_ctrl_ch1_ext;
wire    [15:0] prbs_bist_ctrl_ch2_ext;
wire    [15:0] prbs_bist_ctrl_ch3_ext;
wire    [15:0] pcs_ctrl9_ch0_ext;
wire    [15:0] pcs_ctrl9_ch1_ext;
wire    [15:0] pcs_ctrl9_ch2_ext;
wire    [15:0] pcs_ctrl9_ch3_ext;
wire    [15:0] pcs_ctrl10_ch0_ext;
wire    [15:0] pcs_ctrl10_ch1_ext;
wire    [15:0] pcs_ctrl10_ch2_ext;
wire    [15:0] pcs_ctrl10_ch3_ext;
wire    [15:0] pcs_ctrl11_ch0_ext;
wire    [15:0] pcs_ctrl11_ch1_ext;
wire    [15:0] pcs_ctrl11_ch2_ext;
wire    [15:0] pcs_ctrl11_ch3_ext;
wire    [15:0] pcs_ctrl12_ch0_ext;
wire    [15:0] pcs_ctrl12_ch1_ext;
wire    [15:0] pcs_ctrl12_ch2_ext;
wire    [15:0] pcs_ctrl12_ch3_ext;
wire    [15:0] pcs_ctrl13_ch0_ext;
wire    [15:0] pcs_ctrl13_ch1_ext;
wire    [15:0] pcs_ctrl13_ch2_ext;
wire    [15:0] pcs_ctrl13_ch3_ext;
wire    [15:0] pcs_ctrl14_ch0_ext;
wire    [15:0] pcs_ctrl14_ch1_ext;
wire    [15:0] pcs_ctrl14_ch2_ext;
wire    [15:0] pcs_ctrl14_ch3_ext;
wire    [15:0] pcs_ctrl15_ch0_ext;
wire    [15:0] pcs_ctrl15_ch1_ext;
wire    [15:0] pcs_ctrl15_ch2_ext;
wire    [15:0] pcs_ctrl15_ch3_ext;
wire    [15:0] pcs_global_ctrl0_ext;
wire    [15:0] pcs_global_ctrl1_ext;
wire    [15:0] pcs_global_ctrl2_ext;

wire    [15:0] pma_ctrl1_ch0_ext;
wire    [15:0] pma_ctrl1_ch1_ext;
wire    [15:0] pma_ctrl1_ch2_ext;
wire    [15:0] pma_ctrl1_ch3_ext;
wire    [15:0] pma_ctrl2_ch0_ext;
wire    [15:0] pma_ctrl2_ch1_ext;
wire    [15:0] pma_ctrl2_ch2_ext;
wire    [15:0] pma_ctrl2_ch3_ext;
wire    [15:0] pma_ctrl3_ch0_ext;
wire    [15:0] pma_ctrl3_ch1_ext;
wire    [15:0] pma_ctrl3_ch2_ext;
wire    [15:0] pma_ctrl3_ch3_ext;
wire    [15:0] pma_ctrl4_ch0_ext;
wire    [15:0] pma_ctrl4_ch1_ext;
wire    [15:0] pma_ctrl4_ch2_ext;
wire    [15:0] pma_ctrl4_ch3_ext;
wire    [15:0] pma_ctrl5_ch0_ext;
wire    [15:0] pma_ctrl5_ch1_ext;
wire    [15:0] pma_ctrl5_ch2_ext;
wire    [15:0] pma_ctrl5_ch3_ext;
wire    [15:0] pma_ctrl6_ch0_ext;
wire    [15:0] pma_ctrl6_ch1_ext;
wire    [15:0] pma_ctrl6_ch2_ext;
wire    [15:0] pma_ctrl6_ch3_ext;
wire    [15:0] pma_ctrl7_ch0_ext;
wire    [15:0] pma_ctrl7_ch1_ext;
wire    [15:0] pma_ctrl7_ch2_ext;
wire    [15:0] pma_ctrl7_ch3_ext;
wire    [15:0] pma_ctrl8_ch0_ext;
wire    [15:0] pma_ctrl8_ch1_ext;
wire    [15:0] pma_ctrl8_ch2_ext;
wire    [15:0] pma_ctrl8_ch3_ext;
wire    [15:0] pma_ctrl9_ch0_ext;
wire    [15:0] pma_ctrl9_ch1_ext;
wire    [15:0] pma_ctrl9_ch2_ext;
wire    [15:0] pma_ctrl9_ch3_ext;
wire    [15:0] pma_ctrl10_ch0_ext;
wire    [15:0] pma_ctrl10_ch1_ext;
wire    [15:0] pma_ctrl10_ch2_ext;
wire    [15:0] pma_ctrl10_ch3_ext;
wire    [15:0] pma_ctrl11_ch0_ext;
wire    [15:0] pma_ctrl11_ch1_ext;
wire    [15:0] pma_ctrl11_ch2_ext;
wire    [15:0] pma_ctrl11_ch3_ext;
wire    [15:0] pma_global_ctrl0_ext;
wire    [15:0] pma_global_ctrl1_ext;
wire    [15:0] pma_global_ctrl2_ext;
wire    [15:0] pma_global_ctrl3_ext;
wire    [15:0] pma_global_ctrl4_ext;
wire    [15:0] pma_global_ctrl5_ext;
wire    [15:0] pma_global_ctrl6_ext;
wire    [15:0] pma_global_ctrl7_ext;
wire    [15:0] pma_global_ctrl8_ext;
wire    [15:0] pma_global_ctrl9_ext;

// TX PCS CRAMs wires to TX PCS
wire    [3:0]  rbisten_tx_int;           // ENBIST CRAM
wire    [3:0]  rrev_loopbk_int;	      // CRAM - Enable dynamic Reverse, PIPE mode
wire 	[3:0]  rforce_disp_int;	      // Acting with TXD[9, 19] forces current disparity to 1 or 0
wire    [3:0]  rib_force_disp_int;    // Disparity force CRAM in IB mode
wire    [3:0]  rforce_echar_int;      // Force /E/ char CRAM
wire    [3:0]  rforce_kchar_int;      // Force /K/ char CRAM
wire    [3:0]  rendec_tx_int;         // Enable 8B/10B encoder CRAM
wire    [3:0]  rge_xaui_tx_int;       // GIGE Idle test enable CRAM
wire    [3:0]  rdwidth_tx_int;        // TX parallel interface data width CRAM
wire    [3:0]  rtxfifo_dis_int;       // TX FIFO disable CRAM
wire    [3:0]  rcascaded_8b10b_en_tx_int; // Caascaded 8b/10b encoder enable CRAM
wire    [3:0]  rprbsen_tx_int;            // PRBS generator enable CRAM
wire    [2:0]  rprbs_sel_ch0_int;         // PRBS selection CRAM
wire    [2:0]  rprbs_sel_ch1_int;         // PRBS selection CRAM
wire    [2:0]  rprbs_sel_ch2_int;         // PRBS selection CRAM
wire    [2:0]  rprbs_sel_ch3_int;         // PRBS selection CRAM
wire    [1:0]  rbist_sel_ch0_int;         // BIST selection CRAM
wire    [1:0]  rbist_sel_ch1_int;         // BIST selection CRAM
wire    [1:0]  rbist_sel_ch2_int;         // BIST selection CRAM
wire    [1:0]  rbist_sel_ch3_int;         // BIST selection CRAM
wire    [1:0]  rcxpat_chnl_en_ch0_int;    // CRPAT or CJPAT selection CRAM
wire    [1:0]  rcxpat_chnl_en_ch1_int;    // CRPAT or CJPAT selection CRAM
wire    [1:0]  rcxpat_chnl_en_ch2_int;    // CRPAT or CJPAT selection CRAM
wire    [1:0]  rcxpat_chnl_en_ch3_int;    // CRPAT or CJPAT selection CRAM
wire    [3:0]  renpolinv_tx_int;          // TX Polarity inversion enable CRAM
wire    [3:0]  rphfifopldentx_int;        // TX phase comp. FIFO PLD read/write enable CRAM
wire    [3:0]  rphfifoursttx_int;         // TX phase comp. FIFO user reset enable CRAM
wire    [3:0]  rfreerun_tx_int;           // TX_CLK out free running during TX PCS reset enable CRAM
wire    [3:0]  rtxwrclksel_int;           // TX FIFO write clock selection CRAM
wire    [3:0]  rtxrdclksel_int;           // TX FIFO read clock selection CRAM
wire    [3:0]  rtx_pipe_enable_int;       // TX PIPE interface enable CRAM
wire    [3:0]  renbitrev_tx_int;          // TX bit reversal enable CRAM
wire    [3:0]  rensymswap_tx_int;         // TX symbol swap enable CRAM
wire    [3:0]  r8b10b_enc_ibm_en_int;     // 8B10B Encoder fix enable CRAM
wire    [3:0]  rtxfifo_lowlatency_en_int; // TX FIFO low latency enable CRAM
wire    [1:0]  rtx_idle_delay_ch0_int;    // PIPE TxElecIdle delay value CRAM
wire    [1:0]  rtx_idle_delay_ch1_int;    // PIPE TxElecIdle delay value CRAM
wire    [1:0]  rtx_idle_delay_ch2_int;    // PIPE TxElecIdle delay value CRAM
wire    [1:0]  rtx_idle_delay_ch3_int;    // PIPE TxElecIdle delay value CRAM

// TX PMA CRAMs wires to TX PMAs
wire    [3:0]  rpmadwidth_tx_int;     // TX PCS to TX PMA data width selection CRAM
wire    [3:0]  rpma_doublewidth_tx_int;// PCS/PMA double width (16/20) selection CRAM
wire    [1:0]  rtx_term_ch0_int;      // TX output buffer termination select CRAMs
wire    [1:0]  rtx_term_ch1_int;      // TX output buffer termination select CRAMs
wire    [1:0]  rtx_term_ch2_int;      // TX output buffer termination select CRAMs
wire    [1:0]  rtx_term_ch3_int;      // TX output buffer termination select CRAMs
wire    [2:0]  rtx_vod_sel_ch0_int;   // TX output buffer Vod switching control CRAMs
wire    [2:0]  rtx_vod_sel_ch1_int;   // TX output buffer Vod switching control CRAMs
wire    [2:0]  rtx_vod_sel_ch2_int;   // TX output buffer Vod switching control CRAMs
wire    [2:0]  rtx_vod_sel_ch3_int;   // TX output buffer Vod switching control CRAMs
wire    [3:0]  rpmphs_1tap_ch0_int;   // TX output buffer pre-emphasis switching control CRAMs
wire    [3:0]  rpmphs_1tap_ch1_int;   // TX output buffer pre-emphasis switching control CRAMs
wire    [3:0]  rpmphs_1tap_ch2_int;   // TX output buffer pre-emphasis switching control CRAMs
wire    [3:0]  rpmphs_1tap_ch3_int;   // TX output buffer pre-emphasis switching control CRAMs
wire    [3:0]  rtx_slewrate_int;      // Slew rate control CRAM
wire    [3:0]  rlst_tx_ch0_int;       // Low speed Test selection CRAMs
wire    [3:0]  rlst_tx_ch1_int;       // Low speed Test selection CRAMs
wire    [3:0]  rlst_tx_ch2_int;       // Low speed Test selection CRAMs
wire    [3:0]  rlst_tx_ch3_int;       // Low speed Test selection CRAMs
wire    [3:0]  rtx_cmu_sel_int;       // CMU selection CRAM
wire    [1:0]  rtx_m_sel_ch0_int;     // Division ratio CRAM selection of output clock in CLKGENBUF
wire    [1:0]  rtx_m_sel_ch1_int;     // Division ratio CRAM selection of output clock in CLKGENBUF
wire    [1:0]  rtx_m_sel_ch2_int;     // Division ratio CRAM selection of output clock in CLKGENBUF
wire    [1:0]  rtx_m_sel_ch3_int;     // Division ratio CRAM selection of output clock in CLKGENBUF
wire    [3:0]  rtxvcobypass_int;      // TX VCO bypass CRAM
wire    [3:0]  rtx_cgb_1x_en_int;     // Single CLKGENBUF mode enable CRAM
wire    [3:0]  rtx_cgb_4x_en_int;     // Quad CLKGENBUF mode enable CRAM
wire    [3:0]  rtx_4x_sw_int;         // Xaui mode (CPULSE aligned across 4 channels) selection CRAM
wire    [3:0]  rsig_inv_2tap_int;     // Pre-emphasis FIR-tap selection CRAM
wire    [2:0]  rpmphs_ptap_ch0_int;   // Control CRAM
wire    [2:0]  rpmphs_ptap_ch1_int;   // Control CRAM
wire    [2:0]  rpmphs_ptap_ch2_int;   // Control CRAM
wire    [2:0]  rpmphs_ptap_ch3_int;   // Control CRAM
wire    [3:0]  rtx_cgb_pdb_int;       // Power down (bar) CRAM for CLKGENBUF6G
//wire    [3:0]  rtx_piso_pdb_int;      // Power down (bar) CRAM for PISO
wire    [3:0]  rtx_ob_pdb_int;        // Power down (bar) CRAM for output buffer
wire    [1:0]  r_tx_det_rx_ch0_int;   // RX Detect block CRAMs
wire    [1:0]  r_tx_det_rx_ch1_int;   // RX Detect block CRAMs
wire    [1:0]  r_tx_det_rx_ch2_int;   // RX Detect block CRAMs
wire    [1:0]  r_tx_det_rx_ch3_int;   // RX Detect block CRAMs
wire    [2:0]  rpmphs_2tap_ch0_int;   // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire    [2:0]  rpmphs_2tap_ch1_int;   // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire    [2:0]  rpmphs_2tap_ch2_int;   // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire    [2:0]  rpmphs_2tap_ch3_int;   // Enable CRAM for PMPHS_2TAP_CHn[1:0] dynamic control signal
wire    [1:0]  rtx_vtt_ch0_int;       // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire    [1:0]  rtx_vtt_ch1_int;       // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire    [1:0]  rtx_vtt_ch2_int;       // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire    [1:0]  rtx_vtt_ch3_int;       // Enable CRAM for TX_VTT_CHn[2:0] dynamic control signal
wire    [3:0]  rsig_inv_pre_int;      // Enable CRAM for SIG_INV_PRE dynamic control signal
wire    [4:0]  rrsvd_tx_ch0_int;      // Rerserved CRAMs for both TX PCS and TX PMA
wire    [4:0]  rrsvd_tx_ch1_int;      // Rerserved CRAMs for both TX PCS and TX PMA
wire    [4:0]  rrsvd_tx_ch2_int;      // Rerserved CRAMs for both TX PCS and TX PMA
wire    [4:0]  rrsvd_tx_ch3_int;      // Rerserved CRAMs for both TX PCS and TX PMA

// RX PCS CRAMs wires to RX PCS
wire    [3:0]  rskpsetbased_int;      // Enable rate matching for PCI-E/PIPE, other standards based on COMMA DEL DEL..
wire    [3:0]  rtruebac2bac_int;      // Enabled (high) for all standards except PIPE. Back to back rate match enable.
wire    [3:0]  ralfull_ch0_int;       // Program when almost full goes high	
wire    [3:0]  ralempty_ch0_int;      // Program when almost empty goes high
wire    [3:0]  ralfull_ch1_int;       // Program when almost full goes high	
wire    [3:0]  ralempty_ch1_int;      // Program when almost empty goes high
wire    [3:0]  ralfull_ch2_int;       // Program when almost full goes high	
wire    [3:0]  ralempty_ch2_int;      // Program when almost empty goes high
wire    [3:0]  ralfull_ch3_int;       // Program when almost full goes high	
wire    [3:0]  ralempty_ch3_int;      // Program when almost empty goes high
wire    [3:0]  rcmpfifourst_int;      // Enable cmpfifourst
wire    [3:0]  rphfifourstrx_int;     // Enable phfifourst_rx
wire    [2:0]  rcomp_size_ch0_int;    // Pattern comparision length CRAMs
wire    [2:0]  rcomp_size_ch1_int;    // Pattern comparision length CRAMs
wire    [2:0]  rcomp_size_ch2_int;    // Pattern comparision length CRAMs
wire    [2:0]  rcomp_size_ch3_int;    // Pattern comparision length CRAMs
wire    [39:0] rcomp_pat_ch0_int;     // Sync pattern CRAMs
wire    [39:0] rcomp_pat_ch1_int;     // Sync pattern CRAMs
wire    [39:0] rcomp_pat_ch2_int;     // Sync pattern CRAMs
wire    [39:0] rcomp_pat_ch3_int;     // Sync pattern CRAMs
wire    [5:0]  rrundisp_ch0_int;      // Run lengh violation setting CRAMs
wire    [5:0]  rrundisp_ch1_int;      // Run lengh violation setting CRAMs
wire    [5:0]  rrundisp_ch2_int;      // Run lengh violation setting CRAMs
wire    [5:0]  rrundisp_ch3_int;      // Run lengh violation setting CRAMs
wire    [1:0]  rib_inv_cd_ch0_int;    // Invalid code setting CRAMs for IB
wire    [1:0]  rib_inv_cd_ch1_int;    // Invalid code setting CRAMs for IB
wire    [1:0]  rib_inv_cd_ch2_int;    // Invalid code setting CRAMs for IB
wire    [1:0]  rib_inv_cd_ch3_int;    // Invalid code setting CRAMs for IB
wire    [3:0]  rrlv_en_int;           // RLV enable CRAM
wire    [3:0]  rsync_sm_dis_int;      // GIGE/XAUI Sync SM disable CRAM
wire    [3:0]  rautobtalg_dis_int;    // BITSLIP mode enable CRAM
wire    [3:0]  rdis_rx_disp_int;      // Receive running disparity calculation disable CRAM
wire    [3:0]  rmatchen_int;          // Clock compensation enable CRAM
wire    [3:0]  rgenericfifo_int;      // GenericFIFO mode enable CRAM
wire    [3:0]  rendec_rx_int;         // 10B/8B decoder enable CRAM
wire    [3:0]  rdwidth_rx_int;        // RX parallel interface data width selection CRAM
wire    [3:0]  rlp20ben_int;          // 20-b loopback enable CRAM
wire    [3:0]  rrxfifo_dis_int;       // RX FIFO bypassing CRAM
wire    [2:0]  renumber_ch0_int;      // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire    [2:0]  renumber_ch1_int;      // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire    [2:0]  renumber_ch2_int;      // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire    [2:0]  renumber_ch3_int;      // Number of consecutive errors without valid data to goto LOSS_OF_SYNC
wire    [7:0]  rknumber_ch0_int;      // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire    [7:0]  rknumber_ch1_int;      // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire    [7:0]  rknumber_ch2_int;      // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire    [7:0]  rknumber_ch3_int;      // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC
wire    [3:0]  renpolinv_rx_int;      // Allow polarity inversion
wire    [7:0]  rgnumber_ch0_int;      // Number of consecutive good data to approach SYNC_ACQ
wire    [7:0]  rgnumber_ch1_int;      // Number of consecutive good data to approach SYNC_ACQ
wire    [7:0]  rgnumber_ch2_int;      // Number of consecutive good data to approach SYNC_ACQ
wire    [7:0]  rgnumber_ch3_int;      // Number of consecutive good data to approach SYNC_ACQ
wire    [3:0]  rclkcmpsqmd_int;       // How many characters to match
wire    [19:0] rclkcmpsq1p_ch0_int;   // Programmable 20-bit encoded comp sequence pos. disp.
wire    [19:0] rclkcmpsq1p_ch1_int;   // Programmable 20-bit encoded comp sequence pos. disp.
wire    [19:0] rclkcmpsq1p_ch2_int;   // Programmable 20-bit encoded comp sequence pos. disp.
wire    [19:0] rclkcmpsq1p_ch3_int;   // Programmable 20-bit encoded comp sequence pos. disp.
wire    [19:0] rclkcmpsq1n_ch0_int;   // Programmable 20-bit encoded comp sequence neg. disp.
wire    [19:0] rclkcmpsq1n_ch1_int;   // Programmable 20-bit encoded comp sequence neg. disp.
wire    [19:0] rclkcmpsq1n_ch2_int;   // Programmable 20-bit encoded comp sequence neg. disp.
wire    [19:0] rclkcmpsq1n_ch3_int;   // Programmable 20-bit encoded comp sequence neg. disp.
wire    [3:0]  rclkcmppos_int;        // Match only the pos disp. sequence 
wire    [1:0]  rosnumber_ch0_int;     // Length of the ordered set
wire    [1:0]  rosnumber_ch1_int;     // Length of the ordered set
wire    [1:0]  rosnumber_ch2_int;     // Length of the ordered set
wire    [1:0]  rosnumber_ch3_int;     // Length of the ordered set
wire    [3:0]  rosbased_int;          // Enable ordered-set based algorithm
wire    [3:0]  rkchar_int;            // use kchar at cg_bad logic calculation
wire    [3:0]  rcascaded_8b10b_en_rx_int; // Cascaded 8B/10B decoder enable CRAM
wire    [1:0]  resync_badcg_en_ch0_int;   //
wire    [1:0]  resync_badcg_en_ch1_int;   //
wire    [1:0]  resync_badcg_en_ch2_int;   //
wire    [1:0]  resync_badcg_en_ch3_int;   //
wire    [3:0]  rencdt_rising_int;         // encdt on rising edge enable CRAM
wire    [3:0]  rcomp_pat_porn_int;        // Positive and negative match enable CRAM
wire    [3:0]  rprbsen_rx_int;            // PRBS Verifier enable CRAM
wire    [3:0]  rprbs_clr_rslt_rx_int;     // PRBS pass/fail flag clear CRAM
wire    [3:0]  rbisten_rx_int;            // BIST Verifier enable CRAM
wire    [3:0]  rbist_clr_rx_int;          // BIST pass/fail flag clear CRAM
wire    [3:0]  rwa_6g_en_int;             // 6G word alignment enable CRAM
wire    [1:0]  rbitslip_size_ch0_int;     // BITSLIP size selection CRAM
wire    [1:0]  rbitslip_size_ch1_int;     // BITSLIP size selection CRAM
wire    [1:0]  rbitslip_size_ch2_int;     // BITSLIP size selection CRAM
wire    [1:0]  rbitslip_size_ch3_int;     // BITSLIP size selection CRAM
wire    [3:0]  rbytord_2sym_en_int;       // Enable 2 symbols byte orderring CRAM
wire    [3:0]  rbysync_polinv_en_int;     // Word alignment polarity inversion enable CRAM
wire    [3:0]  rbitloc_rev_en_int;        // Bit reversal enable CRAM
wire    [3:0]  rbyte_rev_en_int;          // Byte swap enable CRAM
wire    [1:0]  rbyteorden_ch0_int;        // Byte ordering enable CRAM
wire    [1:0]  rbyteorden_ch1_int;        // Byte ordering enable CRAM
wire    [1:0]  rbyteorden_ch2_int;        // Byte ordering enable CRAM
wire    [1:0]  rbyteorden_ch3_int;        // Byte ordering enable CRAM
wire    [3:0]  rbytordplden_int;          // PLD control signal BYTEORDPLD enable CRAM
wire    [3:0]  rphfifopldenrx_int;        // RX phase comp. FIFO read/write enable CRAM
wire    [3:0]  rautoinsdis_int;           // Disable CRAM for auto insertion of 8'h9C
wire    [5:0]  rppmsel_ch0_int;           // Programmable PPM ajustment CRAM
wire    [5:0]  rppmsel_ch1_int;           // Programmable PPM ajustment CRAM
wire    [5:0]  rppmsel_ch2_int;           // Programmable PPM ajustment CRAM
wire    [5:0]  rppmsel_ch3_int;           // Programmable PPM ajustment CRAM
wire    [3:0]  rforce0_freqdet_int;       // Forcing FREQDET signal to low CRAM
wire    [3:0]  rforce1_freqdet_int;       // Forcing FREQDET signal to high CRAM
wire    [9:0]  rbytordpat_ch0_int;        // Byte ordering pattern CRAM
wire    [9:0]  rbytordpat_ch1_int;        // Byte ordering pattern CRAM
wire    [9:0]  rbytordpat_ch2_int;        // Byte ordering pattern CRAM
wire    [9:0]  rbytordpat_ch3_int;        // Byte ordering pattern CRAM
wire    [9:0]  rbytordpad_ch0_int;        // Byte ordering pad pattern CRAM
wire    [9:0]  rbytordpad_ch1_int;        // Byte ordering pad pattern CRAM
wire    [9:0]  rbytordpad_ch2_int;        // Byte ordering pad pattern CRAM
wire    [9:0]  rbytordpad_ch3_int;        // Byte ordering pad pattern CRAM
wire    [3:0]  rforce_sig_det_pcs_int;    // Forcing sigdet to high in PCS CRAM
wire    [3:0]  rfreerun_rx_int;           // RX_CLK out free running during RX PCS reset enable CRAM
wire    [1:0]  rrcvd_clk_sel_ch0_int;     // RCVD_CLK domain selection CRAM
wire    [1:0]  rrcvd_clk_sel_ch1_int;     // RCVD_CLK domain selection CRAM
wire    [1:0]  rrcvd_clk_sel_ch2_int;     // RCVD_CLK domain selection CRAM
wire    [1:0]  rrcvd_clk_sel_ch3_int;     // RCVD_CLK domain selection CRAM
wire    [1:0]  rclk_1_sel_ch0_int;        // CLK_1 domain selection CRAM
wire    [1:0]  rclk_1_sel_ch1_int;        // CLK_1 domain selection CRAM
wire    [1:0]  rclk_1_sel_ch2_int;        // CLK_1 domain selection CRAM
wire    [1:0]  rclk_1_sel_ch3_int;        // CLK_1 domain selection CRAM
wire    [1:0]  rclk_2_sel_ch0_int;        // CLK_2 domain selection CRAM
wire    [1:0]  rclk_2_sel_ch1_int;        // CLK_2 domain selection CRAM
wire    [1:0]  rclk_2_sel_ch2_int;        // CLK_2 domain selection CRAM
wire    [1:0]  rclk_2_sel_ch3_int;        // CLK_2 domain selection CRAM
wire    [3:0]  rrx_rd_clk_sel_int;        // RX FIFO read clock selection CRAM
wire    [3:0]  rrx_pipe_enable_int;       // RX PIPE interface enable CRAM
wire    [3:0]  rall_one_dect_only_int;    // PRBS Verifier detect all one only enable CRAM
wire    [2:0]  rtest_bus_sel_ch0_int;     // Per channel test bus selection CRAMs
wire    [2:0]  rtest_bus_sel_ch1_int;     // Per channel test bus selection CRAMs
wire    [2:0]  rtest_bus_sel_ch2_int;     // Per channel test bus selection CRAMs
wire    [2:0]  rtest_bus_sel_ch3_int;     // Per channel test bus selection CRAMs
wire    [1:0]  r8b10b_dec_ibm_en_ch0_int; // 8B10B Decoder fix enable CRAM
wire    [1:0]  r8b10b_dec_ibm_en_ch1_int; // 8B10B Decoder fix enable CRAM
wire    [1:0]  r8b10b_dec_ibm_en_ch2_int; // 8B10B Decoder fix enable CRAM
wire    [1:0]  r8b10b_dec_ibm_en_ch3_int; // 8B10B Decoder fix enable CRAM
wire    [3:0]  rrxfifo_lowlatency_en_int; // RX FIFO low latency enable CRAM
wire    [3:0]  rppm_cnt_reset_int;        // PPM counter reset CRAM (latched version on Test bus)
wire    [3:0]  rrx_detect_bypass_int;     // PMA RX detection bypass enable CRAM
wire    [3:0]  rclkcmpinsertpad_int;      // Rate matching pad insertion enable CRAM

// RX PMA CRAM wires to RX PMAs
wire    [3:0]  rpmadwidth_rx_int;       // RX PMA to RX PCS data width sel CRAMs
wire    [3:0]  rpma_doublewidth_rx_int; // RX PMA/PCS double width (16/20) sel CRAM
wire    [2:0]  rrx_sloslv_ch0_int;	// Signal loss threshold select CRAMs
wire    [2:0]  rrx_sloslv_ch1_int;	// Signal loss threshold select CRAMs
wire    [2:0]  rrx_sloslv_ch2_int;	// Signal loss threshold select CRAMs
wire    [2:0]  rrx_sloslv_ch3_int;	// Signal loss threshold select CRAMs
wire    [1:0]  rrx_term_ch0_int;        // RX input buffer termination select CRAMs
wire    [1:0]  rrx_term_ch1_int;        // RX input buffer termination select CRAMs
wire    [1:0]  rrx_term_ch2_int;        // RX input buffer termination select CRAMs
wire    [1:0]  rrx_term_ch3_int;        // RX input buffer termination select CRAMs
wire    [3:0]  rrxvcobypass_int;	// RX VCO bypass CRAM
wire    [1:0]  rbwctral_rx_ch0_int;	// RX PLL loop filter bandwidth control CRAMs
wire    [1:0]  rbwctral_rx_ch1_int;	// RX PLL loop filter bandwidth control CRAMs
wire    [1:0]  rbwctral_rx_ch2_int;	// RX PLL loop filter bandwidth control CRAMs
wire    [1:0]  rbwctral_rx_ch3_int;	// RX PLL loop filter bandwidth control CRAMs
wire    [3:0]  rforce_sigdet_int;       // SIGDET forcing CRAM
wire    [2:0]  rrefclk_sel_ch0_int;	// RXPLL alternative clock source selection CRAMs
wire    [2:0]  rrefclk_sel_ch1_int;	// RXPLL alternative clock source selection CRAMs
wire    [2:0]  rrefclk_sel_ch2_int;	// RXPLL alternative clock source selection CRAMs
wire    [2:0]  rrefclk_sel_ch3_int;	// RXPLL alternative clock source selection CRAMs
wire    [3:0]  rs_lpbk_int;		// Serial loopback CRAM
wire    [3:0]  r_rlpbk_int;	        // Reverse serial loopback CRAM for RX channel
wire    [3:0]  rs_rdlpbk_int;	        // Serial reversed diagnostic loopback CRAM
wire    [3:0]  rrx_revlb_sw_int;	// Reverse loopback switch CRAM
wire    [1:0]  risel_rx_ch0_int;	// RXPLL charge pump current control CRAM
wire    [1:0]  risel_rx_ch1_int;	// RXPLL charge pump current control CRAM
wire    [1:0]  risel_rx_ch2_int;	// RXPLL charge pump current control CRAM
wire    [1:0]  risel_rx_ch3_int;	// RXPLL charge pump current control CRAM
wire    [1:0]  riupsel_rx_ch0_int;	// Intentionally mismatch UP/DN current CRAMs control (Iup)
wire    [1:0]  riupsel_rx_ch1_int;	// Intentionally mismatch UP/DN current CRAMs control (Iup)
wire    [1:0]  riupsel_rx_ch2_int;	// Intentionally mismatch UP/DN current CRAMs control (Iup)
wire    [1:0]  riupsel_rx_ch3_int;	// Intentionally mismatch UP/DN current CRAMs control (Iup)
wire    [1:0]  ridnsel_rx_ch0_int;	// Intentionally mismatch UP/DN current CRAMs control (Idn)
wire    [1:0]  ridnsel_rx_ch1_int;	// Intentionally mismatch UP/DN current CRAMs control (Idn)
wire    [1:0]  ridnsel_rx_ch2_int;	// Intentionally mismatch UP/DN current CRAMs control (Idn)
wire    [1:0]  ridnsel_rx_ch3_int;	// Intentionally mismatch UP/DN current CRAMs control (Idn)
wire    [3:0]  rtesten_cp_rx_int;	// Charge pump test mode control CRAM in RXPLL
wire    [3:0]  rtristate_cp_rx_int;	// Charge pump tristate control CRAM in RXPLL
wire    [3:0]  rtestupen_cp_rx_int;     // Charge pump current test control CRAM in RXPLL
wire    [3:0]  rtestdnen_cp_rx_int;     // Charge pump current test control CRAM in RXPLL
wire    [2:0]  rrx_vtt_ch0_int;	        // Programmable termination voltage setting CRAM
wire    [2:0]  rrx_vtt_ch1_int;	        // Programmable termination voltage setting CRAM
wire    [2:0]  rrx_vtt_ch2_int;	        // Programmable termination voltage setting CRAM
wire    [2:0]  rrx_vtt_ch3_int;	        // Programmable termination voltage setting CRAM
wire    [3:0]  rlst_rx_ch0_int;	        // Low speed test selection CRAM
wire    [3:0]  rlst_rx_ch1_int;	        // Low speed test selection CRAM
wire    [3:0]  rlst_rx_ch2_int;	        // Low speed test selection CRAM
wire    [3:0]  rlst_rx_ch3_int;	        // Low speed test selection CRAM
wire    [3:0]  rlst_rxpll_ch0_int;	// Low speed test selection CRAM
wire    [3:0]  rlst_rxpll_ch1_int;	// Low speed test selection CRAM
wire    [3:0]  rlst_rxpll_ch2_int;	// Low speed test selection CRAM
wire    [3:0]  rlst_rxpll_ch3_int;	// Low speed test selection CRAM
wire    [3:0]  rltr_int;		// Lock to reference clock enable CRAM
wire    [3:0]  rltd_int;		// Lock to received data enable CRAM
wire    [3:0]  rrx_cru_m_ch0_int;	// Programmable M control CRAM
wire    [3:0]  rrx_cru_m_ch1_int;	// Programmable M control CRAM
wire    [3:0]  rrx_cru_m_ch2_int;	// Programmable M control CRAM
wire    [3:0]  rrx_cru_m_ch3_int;	// Programmable M control CRAM
wire    [1:0]  rrx_cru_l_ch0_int;	// Programmable L contrl CRAM
wire    [1:0]  rrx_cru_l_ch1_int;	// Programmable L contrl CRAM
wire    [1:0]  rrx_cru_l_ch2_int;	// Programmable L contrl CRAM
wire    [1:0]  rrx_cru_l_ch3_int;	// Programmable L contrl CRAM
wire    [3:0]  rrx_ignore_phslck_int;   // Ignore phase lock CRAM
wire    [5:0]  rrx_cru_ctl_ch0_int;	// Programmable control CRAM
wire    [5:0]  rrx_cru_ctl_ch1_int;	// Programmable control CRAM
wire    [5:0]  rrx_cru_ctl_ch2_int;	// Programmable control CRAM
wire    [5:0]  rrx_cru_ctl_ch3_int;	// Programmable control CRAM
wire    [3:0]  rreg_cp_rx_int;	        // RX PLL charge pump regulator enable CRAM
wire    [1:0]  rrx_piso_bypass_ch0_int; // Reference bypass around PISO CRAM
wire    [1:0]  rrx_piso_bypass_ch1_int; // Reference bypass around PISO CRAM
wire    [1:0]  rrx_piso_bypass_ch2_int; // Reference bypass around PISO CRAM
wire    [1:0]  rrx_piso_bypass_ch3_int; // Reference bypass around PISO CRAM
wire    [1:0]  rrx_cru_m_sel_ch0_int;   // Division ratio CRAM selection of input clock in CDR
wire    [1:0]  rrx_cru_m_sel_ch1_int;   // Division ratio CRAM selection of input clock in CDR
wire    [1:0]  rrx_cru_m_sel_ch2_int;   // Division ratio CRAM selection of input clock in CDR
wire    [1:0]  rrx_cru_m_sel_ch3_int;   // Division ratio CRAM selection of input clock in CDR
wire    [3:0]  rrx_cru_div2_int;	// Reference clock divided by 2 enable CRAM
wire    [3:0]  rrx_osc_en_int;	        // CGB RX OSC enable CRAM
wire    [3:0]  rrx_cru_pdb_int;	        // Power down (bar) CRAM for CRU
wire    [3:0]  rrx_cru_rst_int;	        // Reset CRAM for PLL in CRU
wire    [3:0]  rrx_ib_pdb_int;	        // Power down (bar) for input buffer
//wire    [3:0]  rrx_sipo_pdb_int;	// Power down (bar) for SIPO
wire    [3:0]  rurx_pdb_int;            // Enable CRAM for URX_PDB dynamic signal
wire    [3:0]  radce_pdb_int;           // Power down for adaptive equalization
wire    [3:0]  radce_rst_int;           // Reset CRAM for counters in adaptive engine
wire    [3:0]  rrx_dc_couple_int;       // Programmable DC couple CRAM for RX wire  buffer
wire    [1:0]  rrx_eq_dc_ch0_int;       // CRAMs for Equalizer block
wire    [1:0]  rrx_eq_dc_ch1_int;       // CRAMs for Equalizer block
wire    [1:0]  rrx_eq_dc_ch2_int;       // CRAMs for Equalizer block
wire    [1:0]  rrx_eq_dc_ch3_int;       // CRAMs for Equalizer block
wire    [3:0]  radce_adapt_int;         // Continuous adaptation enable CRAM
wire    [1:0]  rseq_sel_ch0_int;        // Sequence of adaptation selection CRAMs
wire    [1:0]  rseq_sel_ch1_int;        // Sequence of adaptation selection CRAMs
wire    [1:0]  rseq_sel_ch2_int;        // Sequence of adaptation selection CRAMs
wire    [1:0]  rseq_sel_ch3_int;        // Sequence of adaptation selection CRAMs
wire    [2:0]  rrgen_set_ch0_int;       // D2A control CRAMs
wire    [2:0]  rrgen_set_ch1_int;       // D2A control CRAMs
wire    [2:0]  rrgen_set_ch2_int;       // D2A control CRAMs
wire    [2:0]  rrgen_set_ch3_int;       // D2A control CRAMs
wire    [3:0]  rclkdiv_ch0_int;         // Division ration selection CRAMs for adaptation engine
wire    [3:0]  rclkdiv_ch1_int;         // Division ration selection CRAMs for adaptation engine
wire    [3:0]  rclkdiv_ch2_int;         // Division ration selection CRAMs for adaptation engine
wire    [3:0]  rclkdiv_ch3_int;         // Division ration selection CRAMs for adaptation engine
wire    [1:0]  rf_lpf_ch0_int;          // LPF corner frequency setting CRAMs
wire    [1:0]  rf_lpf_ch1_int;          // LPF corner frequency setting CRAMs
wire    [1:0]  rf_lpf_ch2_int;          // LPF corner frequency setting CRAMs
wire    [1:0]  rf_lpf_ch3_int;          // LPF corner frequency setting CRAMs
wire    [1:0]  rf_hpf_ch0_int;          // HPF corner frequency setting CRAMs
wire    [1:0]  rf_hpf_ch1_int;          // HPF corner frequency setting CRAMs
wire    [1:0]  rf_hpf_ch2_int;          // HPF corner frequency setting CRAMs
wire    [1:0]  rf_hpf_ch3_int;          // HPF corner frequency setting CRAMs
wire    [1:0]  rrgen_bw_ch0_int;        // RGEN corner frequency setting CRAMs
wire    [1:0]  rrgen_bw_ch1_int;        // RGEN corner frequency setting CRAMs
wire    [1:0]  rrgen_bw_ch2_int;        // RGEN corner frequency setting CRAMs
wire    [1:0]  rrgen_bw_ch3_int;        // RGEN corner frequency setting CRAMs
wire    [2:0]  rhyst_ch0_int;           // Programmable digital filtering setting CRAMs
wire    [2:0]  rhyst_ch1_int;           // Programmable digital filtering setting CRAMs
wire    [2:0]  rhyst_ch2_int;           // Programmable digital filtering setting CRAMs
wire    [2:0]  rhyst_ch3_int;           // Programmable digital filtering setting CRAMs
wire    [1:0]  rrect_adj_ch0_int;       // Rectifier leaker current setting CRAMs
wire    [1:0]  rrect_adj_ch1_int;       // Rectifier leaker current setting CRAMs
wire    [1:0]  rrect_adj_ch2_int;       // Rectifier leaker current setting CRAMs
wire    [1:0]  rrect_adj_ch3_int;       // Rectifier leaker current setting CRAMs
wire    [1:0]  rd2a_res_ch0_int;        // D2A resolution settting CRAMs
wire    [1:0]  rd2a_res_ch1_int;        // D2A resolution settting CRAMs
wire    [1:0]  rd2a_res_ch2_int;        // D2A resolution settting CRAMs
wire    [1:0]  rd2a_res_ch3_int;        // D2A resolution settting CRAMs
wire    [2:0]  rrgen_vod_ch0_int;       // RGEN amplitude setting CRAMs
wire    [2:0]  rrgen_vod_ch1_int;       // RGEN amplitude setting CRAMs
wire    [2:0]  rrgen_vod_ch2_int;       // RGEN amplitude setting CRAMs
wire    [2:0]  rrgen_vod_ch3_int;       // RGEN amplitude setting CRAMs
wire    [3:0]  rlf_os_ch0_int;          // Low freq. loop offset cancelling setting CRAMs
wire    [3:0]  rlf_os_ch1_int;          // Low freq. loop offset cancelling setting CRAMs
wire    [3:0]  rlf_os_ch2_int;          // Low freq. loop offset cancelling setting CRAMs
wire    [3:0]  rlf_os_ch3_int;          // Low freq. loop offset cancelling setting CRAMs
wire    [3:0]  rhf_os_ch0_int;          // High freq. loop offset cancelling setting CRAMs
wire    [3:0]  rhf_os_ch1_int;          // High freq. loop offset cancelling setting CRAMs
wire    [3:0]  rhf_os_ch2_int;          // High freq. loop offset cancelling setting CRAMs
wire    [3:0]  rhf_os_ch3_int;          // High freq. loop offset cancelling setting CRAMs
wire    [2:0]  reqa_ct_ch0_int;         // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqa_ct_ch1_int;         // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqa_ct_ch2_int;         // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqa_ct_ch3_int;         // Enable CRAMs for EQA_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqb_ct_ch0_int;         // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqb_ct_ch1_int;         // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqb_ct_ch2_int;         // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqb_ct_ch3_int;         // Enable CRAMs for EQB_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqc_ct_ch0_int;         // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqc_ct_ch1_int;         // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqc_ct_ch2_int;         // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqc_ct_ch3_int;         // Enable CRAMs for EQC_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqd_ct_ch0_int;         // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqd_ct_ch1_int;         // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqd_ct_ch2_int;         // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire    [2:0]  reqd_ct_ch3_int;         // Enable CRAMs for EQD_CT_CHn[2:0] dynamic control signals
wire    [2:0]  req_ctv_ch0_int;         // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire    [2:0]  req_ctv_ch1_int;         // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire    [2:0]  req_ctv_ch2_int;         // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire    [2:0]  req_ctv_ch3_int;         // Enable CRAMs for EQ_CTV_CHn[2:0] dynamic control signals
wire    [1:0]  rdc_freq_ch0_int;        // ADCE CRAM
wire    [1:0]  rdc_freq_ch1_int;        // ADCE CRAM
wire    [1:0]  rdc_freq_ch2_int;        // ADCE CRAM
wire    [1:0]  rdc_freq_ch3_int;        // ADCE CRAM
wire    [3:0]  r_iqclk_ch0_int;         // IQCLK selection CRAM
wire    [3:0]  r_iqclk_ch1_int;         // IQCLK selection CRAM
wire    [3:0]  r_iqclk_ch2_int;         // IQCLK selection CRAM
wire    [3:0]  r_iqclk_ch3_int;         // IQCLK selection CRAM
wire    [5:0]  r_dfe_ch0_int;           // DFE CRAM
wire    [5:0]  r_dfe_ch1_int;           // DFE CRAM
wire    [5:0]  r_dfe_ch2_int;           // DFE CRAM
wire    [5:0]  r_dfe_ch3_int;           // DFE CRAM
wire    [3:0]  r_cp_mode_int;           // CP mode CRAM
wire    [1:0]  r_impctrl_ch0_int;       // IMPCTRL CRAM
wire    [1:0]  r_impctrl_ch1_int;       // IMPCTRL CRAM
wire    [1:0]  r_impctrl_ch2_int;       // IMPCTRL CRAM
wire    [1:0]  r_impctrl_ch3_int;       // IMPCTRL CRAM
wire    [3:0]  rpd_ien_int;             // PD current setting CRAM
wire    [2:0]  rrsvd_rx_ch0_int;        // Rerserved CRAMs for both RX PCS and RX PMA
wire    [2:0]  rrsvd_rx_ch1_int;        // Rerserved CRAMs for both RX PCS and RX PMA
wire    [2:0]  rrsvd_rx_ch2_int;        // Rerserved CRAMs for both RX PCS and RX PMA
wire    [2:0]  rrsvd_rx_ch3_int;        // Rerserved CRAMs for both RX PCS and RX PMA

// CMU PCS CRAMs wires to CMU
wire           rindv_tx_int;          // TX SM bypassing CRAM
wire           rindv_rx_int;          // RX SM bypassing CRAM
wire           rdeskewen_int;         // Deskew function enable CRAM
wire    [1:0]  ralgnect_int;          // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire    [2:0]  ralgnact_int;          // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire    [1:0]  ralgngct_int;          // Number of consecutive errors without valid data to goto LOSS_OF_ALIGN
wire           rdskposdisp_int;       // Match the programmed de-skew pattern only
wire    [9:0]  rdskchrp_int;          // Programmable Deskew Char. Pos. Disp.
wire           ralgnopt_int;          // De-skew SM Hysteresis Option
wire           rfreerun_centrl_int;   // REFCLK_OUT free running enable CRAM
wire           rcentrl_clk_sel_int;   // REFCLK_PMA global clock selection CRAM
wire           rrefclk_out_div2_int;  // REFCLK_OUT divide by 2 enable CRAM
wire    [2:0]  rtest_bus_centrl_sel_int;  // Central Test bus selection CRAMs
wire           rendec_data_sel_tx_int;// TX 8B10B encoder data in selection CRAM
wire           rendec_data_sel_rx_int;// RX 8B10B decoder data out selection CRAM
wire           rphfifo_master_sel_tx_int; // TX Phase comp. FIFO pointers selection CRAM
wire           rphfifo_master_sel_rx_int; // TX Phase comp. FIFO pointers selection CRAM

// CMU PMA, and CLKREF CRAMs wires
wire           rbgbypass_int;	      // Bandgap bypass CRAM
//wire           ratb_en_int;	      // Analog test bus enable CRAM
wire   [3:0]   rlst_bg_int;	      // Programmable test bus setting CRAM
wire           rcmu_rst_int;	      // Reset CRAM for divider in CMU feedback loop
wire           rcmu_iqclkout_sel_int; // REFClock select for going to IQ lines CRAM
wire   [1:0]   rcmu0_isel_int;	      // TXPLL charge pump current control CRAM
wire   [1:0]   rcmu1_isel_int;	      // TXPLL charge pump current control CRAM
wire   [1:0]   rcmu0_iupsel_int;      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire   [1:0]   rcmu1_iupsel_int;      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire   [1:0]   rcmu0_idnsel_int;      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire   [1:0]   rcmu1_idnsel_int;      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire           rcmu0_testen_cp_int;   // Charge pump test mode control CRAM in TXPLL0
wire           rcmu1_testen_cp_int;   // Charge pump test mode control CRAM in TXPLL1
wire           rcmu0_tristate_cp_int; // Charge pump tristate control CRAM in TXPLL0
wire           rcmu1_tristate_cp_int; // Charge pump tristate control CRAM in TXPLL1
wire           rcmu0_testupen_cp_int; // Charge pump current test control CRAM in TXPLL0
wire           rcmu1_testupen_cp_int; // Charge pump current test control CRAM in TXPLL1
wire   [3:0]   rcmu0_lst_int;	      // Low speed test selection CRAM
wire   [3:0]   rcmu1_lst_int;	      // Low speed test selection CRAM
wire   [7:0]   rcmu0_ctl_int;	      // Programmable control CRAM
wire   [7:0]   rcmu1_ctl_int;	      // Programmable control CRAM
wire           rcmu0_div2_int;	      // Reference clock divided by 2 enable CRAM
wire           rcmu1_div2_int;	      // Reference clock divided by 2 enable CRAM
wire   [1:0]   rcmu0_ref_sel_int;     // Reference selection control CRAM
wire   [1:0]   rcmu1_ref_sel_int;     // Reference selection control CRAM
wire   [3:0]   rcmu0_m_int;	      // Programmable M selection CRAM
wire   [3:0]   rcmu1_m_int;	      // Programmable M selection CRAM
wire   [1:0]   rcmu0_l_int;	      // Programmable L selection CRAM
wire   [1:0]   rcmu1_l_int;	      // Programmable L selection CRAM
wire           rcmu0_pdb_int;	      // Powerdown (bar)CMU CRAM
wire           rcmu1_pdb_int;	      // Powerdown (bar)CMU CRAM
wire           rcmu0_txpll_rst_int;   // TXPLL0 reset CRAM
wire           rcmu1_txpll_rst_int;   // TXPLL0 reset CRAM
wire           rcmu0_testdnen_cp_int; // Charge pump current test control CRAM
wire           rcmu1_testdnen_cp_int; // Charge pump current test control CRAM
wire   [3:0]   rcmu_peclrx0_cm_int;   // Common mode control CRAM
wire   [3:0]   rcmu_peclrx1_cm_int;   // Common mode control CRAM
wire   [3:0]   rcmu_peclrx0_lst_int;  // Analog test bus setting CRAM
wire   [3:0]   rcmu_peclrx1_lst_int;  // Analog test bus setting CRAM
wire           rcmu_txpll0_1x_en_int; // 1X enable CRAM in central CGB
wire           rcmu_txpll1_1x_en_int; // 1X enable CRAM in central CGB
wire   [2:0]   rcmu_txpll0_iqclkin_sel_int;// IQ clock selection CRAMs
wire   [2:0]   rcmu_txpll1_iqclkin_sel_int;// IQ clock selection CRAMs
wire   [1:0]   rcmu_cgb_cmusel_int;   // Central CGB CMU selection CRAM
wire   [1:0]   rcmu_cgb_ndiv_int;     // N-divider selection CRAM for wire  clock in central CGB
wire           rcmu_cgb_div5_int;     // TX PCS to TX PMA data width selection CRAM
wire           rcmu_cgb_div2_int;     // TX PCS to TX PMA double data width selection CRAM
wire           rcmu_cgb_vcobypass_int;// CMU VCO bypass CRAM in central CGB
wire           rcmu_cgb_4x_en_int;    // Quad channel mode clock driver enable CRAM
wire           rcmu_cgb_8x_en_int;    // Eight channel mode clock driver enable CRAM
wire           rcmu_cgb_pclksel_int;  // Central CGB PCLK select CRAM
wire   [1:0]   rcmu2_isel_int;	      // TXPLL charge pump current control CRAM
wire   [1:0]   rcmu2_iupsel_int;      // Intentionally mismatch UP/DN current control CRAM (Iup)
wire   [1:0]   rcmu2_idnsel_int;      // Intentionally mismatch UP/DN current control CRAM (Idn)
wire           rcmu2_testen_cp_int;   // Charge pump test mode control CRAM in TXPLL2
wire           rcmu2_tristate_cp_int; // Charge pump tristate control CRAM in TXPLL2
wire           rcmu2_testupen_cp_int; // Charge pump current test control CRAM in TXPLL2
wire           rcmu2_testdnen_cp_int; // Charge pump current test control CRAM in TXPLL2
wire   [3:0]   rcmu2_lst_int;	      // Low speed test selection CRAM
wire   [7:0]   rcmu2_ctl_int;	      // Programmable control CRAM
wire           rcmu2_refsel_int;      // Reference select CRAM for CMU2
wire   [3:0]   rcmu2_m_int;	      // Programmable M selection CRAM
wire   [1:0]   rcmu2_l_int;	      // Programmable L selection CRAM
wire           rcmu2_pdb_int;	      // Powerdown (bar)CMU CRAM
wire           rcmu2_txpll_rst_int;   // TXPLL2 reset CRAM
wire           rcmu0_rcp_mode_int;    // CMU0 charge pump mode select CRAM
wire           rcmu1_rcp_mode_int;    // CMU1 charge pump mode select CRAM
wire    [3:0]  rpma_testbus_sel_int;  // PMA testbus selection
wire    [4:0]  rrsvd_cmu_int;         // Reserved CRAMs for both PMA CMU and PCS CMU

wire    [15:0] pcs_ctrl_out_ch0;      // PCS MDIO out for channel0
wire    [15:0] pcs_ctrl_out_ch1;      // PCS MDIO out for channel1
wire    [15:0] pcs_ctrl_out_ch2;      // PCS MDIO out for channel2
wire    [15:0] pcs_ctrl_out_ch3;      // PCS MDIO out for channel3

// Control register address parameters
parameter XGXS_CTRL          = 16'h0000;
parameter XGXS_STATUS1       = 16'h0001;
parameter XGXS_STATUS2       = 16'h0008;
parameter XGXS_LANE_STATUS   = 16'h0018;
parameter TRUNKING_MODE      = 16'h8000;
parameter PCS_CTRL1_CH0      = 16'h8001;
parameter PCS_CTRL1_CH1      = 16'h8002;
parameter PCS_CTRL1_CH2      = 16'h8003;
parameter PCS_CTRL1_CH3      = 16'h8004;
parameter PCS_CTRL2_CH0      = 16'h8005;
parameter PCS_CTRL2_CH1      = 16'h8006;
parameter PCS_CTRL2_CH2      = 16'h8007;
parameter PCS_CTRL2_CH3      = 16'h8008;
parameter PCS_CTRL3_CH0      = 16'h8009;
parameter PCS_CTRL3_CH1      = 16'h800a;
parameter PCS_CTRL3_CH2      = 16'h800b;
parameter PCS_CTRL3_CH3      = 16'h800c;
parameter PCS_CTRL4_CH0      = 16'h800d;
parameter PCS_CTRL4_CH1      = 16'h800e;
parameter PCS_CTRL4_CH2      = 16'h800f;
parameter PCS_CTRL4_CH3      = 16'h8010;
parameter PCS_CTRL5_CH0      = 16'h8011;
parameter PCS_CTRL5_CH1      = 16'h8012;
parameter PCS_CTRL5_CH2      = 16'h8013;
parameter PCS_CTRL5_CH3      = 16'h8014;
parameter PCS_CTRL6_CH0      = 16'h8015;
parameter PCS_CTRL6_CH1      = 16'h8016;
parameter PCS_CTRL6_CH2      = 16'h8017;
parameter PCS_CTRL6_CH3      = 16'h8018;
parameter PCS_CTRL7_CH0      = 16'h8019;
parameter PCS_CTRL7_CH1      = 16'h801a;
parameter PCS_CTRL7_CH2      = 16'h801b;
parameter PCS_CTRL7_CH3      = 16'h801c;
parameter PCS_CTRL8_CH0      = 16'h801d;
parameter PCS_CTRL8_CH1      = 16'h801e;
parameter PCS_CTRL8_CH2      = 16'h801f;
parameter PCS_CTRL8_CH3      = 16'h8020;
parameter PRBS_BIST_CTRL_CH0 = 16'h8021;
parameter PRBS_BIST_CTRL_CH1 = 16'h8022;
parameter PRBS_BIST_CTRL_CH2 = 16'h8023;
parameter PRBS_BIST_CTRL_CH3 = 16'h8024;
parameter PCS_CTRL9_CH0      = 16'h8025;
parameter PCS_CTRL9_CH1      = 16'h8026;
parameter PCS_CTRL9_CH2      = 16'h8027;
parameter PCS_CTRL9_CH3      = 16'h8028;
parameter PCS_CTRL10_CH0     = 16'h8029;
parameter PCS_CTRL10_CH1     = 16'h802a;
parameter PCS_CTRL10_CH2     = 16'h802b;
parameter PCS_CTRL10_CH3     = 16'h802c;
parameter PCS_CTRL11_CH0     = 16'h802d;
parameter PCS_CTRL11_CH1     = 16'h802e;
parameter PCS_CTRL11_CH2     = 16'h802f;
parameter PCS_CTRL11_CH3     = 16'h8030;
parameter PCS_CTRL12_CH0     = 16'h8031;
parameter PCS_CTRL12_CH1     = 16'h8032;
parameter PCS_CTRL12_CH2     = 16'h8033;
parameter PCS_CTRL12_CH3     = 16'h8034;
parameter PCS_CTRL13_CH0     = 16'h8035;
parameter PCS_CTRL13_CH1     = 16'h8036;
parameter PCS_CTRL13_CH2     = 16'h8037;
parameter PCS_CTRL13_CH3     = 16'h8038;
parameter PCS_CTRL14_CH0     = 16'h8039;
parameter PCS_CTRL14_CH1     = 16'h803a;
parameter PCS_CTRL14_CH2     = 16'h803b;
parameter PCS_CTRL14_CH3     = 16'h803c;
parameter PCS_CTRL15_CH0     = 16'h803d;
parameter PCS_CTRL15_CH1     = 16'h803e;
parameter PCS_CTRL15_CH2     = 16'h803f;
parameter PCS_CTRL15_CH3     = 16'h8040;

parameter PCS_GLOBAL_CTRL0   = 16'h8050;
parameter PCS_GLOBAL_CTRL1   = 16'h8051;
parameter PCS_GLOBAL_CTRL2   = 16'h8052;

parameter PMA_CTRL1_CH0      = 16'h8060;
parameter PMA_CTRL1_CH1      = 16'h8061;
parameter PMA_CTRL1_CH2      = 16'h8062;
parameter PMA_CTRL1_CH3      = 16'h8063;
parameter PMA_CTRL2_CH0      = 16'h8064;
parameter PMA_CTRL2_CH1      = 16'h8065;
parameter PMA_CTRL2_CH2      = 16'h8066;
parameter PMA_CTRL2_CH3      = 16'h8067;
parameter PMA_CTRL3_CH0      = 16'h8068;
parameter PMA_CTRL3_CH1      = 16'h8069;
parameter PMA_CTRL3_CH2      = 16'h806a;
parameter PMA_CTRL3_CH3      = 16'h806b;
parameter PMA_CTRL4_CH0      = 16'h806c;
parameter PMA_CTRL4_CH1      = 16'h806d;
parameter PMA_CTRL4_CH2      = 16'h806e;
parameter PMA_CTRL4_CH3      = 16'h806f;
parameter PMA_CTRL5_CH0      = 16'h8070;
parameter PMA_CTRL5_CH1      = 16'h8071;
parameter PMA_CTRL5_CH2      = 16'h8072;
parameter PMA_CTRL5_CH3      = 16'h8073;
parameter PMA_CTRL6_CH0      = 16'h8074;
parameter PMA_CTRL6_CH1      = 16'h8075;
parameter PMA_CTRL6_CH2      = 16'h8076;
parameter PMA_CTRL6_CH3      = 16'h8077;
parameter PMA_CTRL7_CH0      = 16'h8078;
parameter PMA_CTRL7_CH1      = 16'h8079;
parameter PMA_CTRL7_CH2      = 16'h807a;
parameter PMA_CTRL7_CH3      = 16'h807b;
parameter PMA_CTRL8_CH0      = 16'h807c;
parameter PMA_CTRL8_CH1      = 16'h807d;
parameter PMA_CTRL8_CH2      = 16'h807e;
parameter PMA_CTRL8_CH3      = 16'h807f;
parameter PMA_CTRL9_CH0      = 16'h8080;
parameter PMA_CTRL9_CH1      = 16'h8081;
parameter PMA_CTRL9_CH2      = 16'h8082;
parameter PMA_CTRL9_CH3      = 16'h8083;
parameter PMA_CTRL10_CH0     = 16'h8084;
parameter PMA_CTRL10_CH1     = 16'h8085;
parameter PMA_CTRL10_CH2     = 16'h8086;
parameter PMA_CTRL10_CH3     = 16'h8087;
parameter PMA_CTRL11_CH0     = 16'h8088;
parameter PMA_CTRL11_CH1     = 16'h8089;
parameter PMA_CTRL11_CH2     = 16'h808a;
parameter PMA_CTRL11_CH3     = 16'h808b;

parameter PMA_GLOBAL_CTRL0   = 16'h8090;
parameter PMA_GLOBAL_CTRL1   = 16'h8091;
parameter PMA_GLOBAL_CTRL2   = 16'h8092;
parameter PMA_GLOBAL_CTRL3   = 16'h8093;
parameter PMA_GLOBAL_CTRL4   = 16'h8094;
parameter PMA_GLOBAL_CTRL5   = 16'h8095;
parameter PMA_GLOBAL_CTRL6   = 16'h8096;
parameter PMA_GLOBAL_CTRL7   = 16'h8097;
parameter PMA_GLOBAL_CTRL8   = 16'h8098;
parameter PMA_GLOBAL_CTRL9   = 16'h8099;

////////////////////////////////////////////////////////////////////////////////
// dbg dump                                                                   //
////////////////////////////////////////////////////////////////////////////////
initial begin
    #sim_dump_dprio_internal_reg_at_time;
    if (sim_dump_dprio_internal_reg_at_time != 0)
    begin
        dbg_file = $fopen(sim_dump_filename);
        
        $fdisplay(dbg_file, "The CRAM values of %m at simulation time %d", sim_dump_dprio_internal_reg_at_time);
        $fdisplay(dbg_file, "");
        
        $fdisplay(dbg_file, "Global Control Registers - PCS ----------------------");
        $fdisplay(dbg_file, "");
        $fdisplay(dbg_file, "%b // %h", pcs_global_ctrl0_reg, PCS_GLOBAL_CTRL0);
        $fdisplay(dbg_file, "%b // %h", pcs_global_ctrl1_reg, PCS_GLOBAL_CTRL1);
        $fdisplay(dbg_file, "%b // %h", pcs_global_ctrl2_reg, PCS_GLOBAL_CTRL2);
        $fdisplay(dbg_file, "");
        
        $fdisplay(dbg_file, "Global Control Registers - PMA ----------------------");
        $fdisplay(dbg_file, "");
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl0_reg, PMA_GLOBAL_CTRL0);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl1_reg, PMA_GLOBAL_CTRL1);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl2_reg, PMA_GLOBAL_CTRL2);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl3_reg, PMA_GLOBAL_CTRL3);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl4_reg, PMA_GLOBAL_CTRL4);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl5_reg, PMA_GLOBAL_CTRL5);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl6_reg, PMA_GLOBAL_CTRL6);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl7_reg, PMA_GLOBAL_CTRL7);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl8_reg, PMA_GLOBAL_CTRL8);
        $fdisplay(dbg_file, "%b // %h", pma_global_ctrl9_reg, PMA_GLOBAL_CTRL9);
        $fdisplay(dbg_file, "");
        
        $fdisplay(dbg_file, "Channel_0 - PCS -------------------------------------");
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl1_ch0_reg, PCS_CTRL1_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl2_ch0_reg, PCS_CTRL2_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl3_ch0_reg, PCS_CTRL3_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl4_ch0_reg, PCS_CTRL4_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl5_ch0_reg, PCS_CTRL5_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl6_ch0_reg, PCS_CTRL6_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl7_ch0_reg, PCS_CTRL7_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl8_ch0_reg, PCS_CTRL8_CH0);
        $fdisplay(dbg_file, "%b // %h", prbs_bist_ctrl_ch0_reg, PRBS_BIST_CTRL_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl9_ch0_reg, PCS_CTRL9_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl10_ch0_reg, PCS_CTRL10_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl11_ch0_reg, PCS_CTRL11_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl12_ch0_reg, PCS_CTRL12_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl13_ch0_reg, PCS_CTRL13_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl14_ch0_reg, PCS_CTRL14_CH0);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl15_ch0_reg, PCS_CTRL15_CH0);        
        $fdisplay(dbg_file, "");

        $fdisplay(dbg_file, "Channel_0 - PMA -------------------------------------");
        $fdisplay(dbg_file, "%b // %h", pma_ctrl1_ch0_reg, PMA_CTRL1_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl2_ch0_reg, PMA_CTRL2_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl3_ch0_reg, PMA_CTRL3_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl4_ch0_reg, PMA_CTRL4_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl5_ch0_reg, PMA_CTRL5_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl6_ch0_reg, PMA_CTRL6_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl7_ch0_reg, PMA_CTRL7_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl8_ch0_reg, PMA_CTRL8_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl9_ch0_reg, PMA_CTRL9_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl10_ch0_reg, PMA_CTRL10_CH0);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl11_ch0_reg, PMA_CTRL11_CH0);
        $fdisplay(dbg_file, "");
        
        $fdisplay(dbg_file, "Channel_1 - PCS -------------------------------------");
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl1_ch1_reg, PCS_CTRL1_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl2_ch1_reg, PCS_CTRL2_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl3_ch1_reg, PCS_CTRL3_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl4_ch1_reg, PCS_CTRL4_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl5_ch1_reg, PCS_CTRL5_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl6_ch1_reg, PCS_CTRL6_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl7_ch1_reg, PCS_CTRL7_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl8_ch1_reg, PCS_CTRL8_CH1);
        $fdisplay(dbg_file, "%b // %h", prbs_bist_ctrl_ch1_reg, PRBS_BIST_CTRL_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl9_ch1_reg, PCS_CTRL9_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl10_ch1_reg, PCS_CTRL10_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl11_ch1_reg, PCS_CTRL11_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl12_ch1_reg, PCS_CTRL12_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl13_ch1_reg, PCS_CTRL13_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl14_ch1_reg, PCS_CTRL14_CH1);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl15_ch1_reg, PCS_CTRL15_CH1);        
        $fdisplay(dbg_file, "");

        $fdisplay(dbg_file, "Channel_1 - PMA -------------------------------------");
        $fdisplay(dbg_file, "%b // %h", pma_ctrl1_ch1_reg, PMA_CTRL1_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl2_ch1_reg, PMA_CTRL2_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl3_ch1_reg, PMA_CTRL3_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl4_ch1_reg, PMA_CTRL4_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl5_ch1_reg, PMA_CTRL5_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl6_ch1_reg, PMA_CTRL6_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl7_ch1_reg, PMA_CTRL7_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl8_ch1_reg, PMA_CTRL8_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl9_ch1_reg, PMA_CTRL9_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl10_ch1_reg, PMA_CTRL10_CH1);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl11_ch1_reg, PMA_CTRL11_CH1);
        $fdisplay(dbg_file, "");
        
        
        $fdisplay(dbg_file, "Channel_2 - PCS -------------------------------------");
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl1_ch2_reg, PCS_CTRL1_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl2_ch2_reg, PCS_CTRL2_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl3_ch2_reg, PCS_CTRL3_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl4_ch2_reg, PCS_CTRL4_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl5_ch2_reg, PCS_CTRL5_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl6_ch2_reg, PCS_CTRL6_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl7_ch2_reg, PCS_CTRL7_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl8_ch2_reg, PCS_CTRL8_CH2);
        $fdisplay(dbg_file, "%b // %h", prbs_bist_ctrl_ch2_reg, PRBS_BIST_CTRL_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl9_ch2_reg, PCS_CTRL9_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl10_ch2_reg, PCS_CTRL10_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl11_ch2_reg, PCS_CTRL11_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl12_ch2_reg, PCS_CTRL12_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl13_ch2_reg, PCS_CTRL13_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl14_ch2_reg, PCS_CTRL14_CH2);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl15_ch2_reg, PCS_CTRL15_CH2);        
        $fdisplay(dbg_file, "");

        $fdisplay(dbg_file, "Channel_2 - PMA -------------------------------------");
        $fdisplay(dbg_file, "%b // %h", pma_ctrl1_ch2_reg, PMA_CTRL1_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl2_ch2_reg, PMA_CTRL2_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl3_ch2_reg, PMA_CTRL3_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl4_ch2_reg, PMA_CTRL4_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl5_ch2_reg, PMA_CTRL5_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl6_ch2_reg, PMA_CTRL6_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl7_ch2_reg, PMA_CTRL7_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl8_ch2_reg, PMA_CTRL8_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl9_ch2_reg, PMA_CTRL9_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl10_ch2_reg, PMA_CTRL10_CH2);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl11_ch2_reg, PMA_CTRL11_CH2);
        $fdisplay(dbg_file, "");
                
        $fdisplay(dbg_file, "Channel_3 - PCS -------------------------------------");
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl1_ch3_reg, PCS_CTRL1_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl2_ch3_reg, PCS_CTRL2_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl3_ch3_reg, PCS_CTRL3_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl4_ch3_reg, PCS_CTRL4_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl5_ch3_reg, PCS_CTRL5_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl6_ch3_reg, PCS_CTRL6_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl7_ch3_reg, PCS_CTRL7_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl8_ch3_reg, PCS_CTRL8_CH3);
        $fdisplay(dbg_file, "%b // %h", prbs_bist_ctrl_ch3_reg, PRBS_BIST_CTRL_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl9_ch3_reg, PCS_CTRL9_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl10_ch3_reg, PCS_CTRL10_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl11_ch3_reg, PCS_CTRL11_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl12_ch3_reg, PCS_CTRL12_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl13_ch3_reg, PCS_CTRL13_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl14_ch3_reg, PCS_CTRL14_CH3);
        $fdisplay(dbg_file, "%b // %h", pcs_ctrl15_ch3_reg, PCS_CTRL15_CH3);        
        $fdisplay(dbg_file, "");

        $fdisplay(dbg_file, "Channel_3 - PMA -------------------------------------");
        $fdisplay(dbg_file, "%b // %h", pma_ctrl1_ch3_reg, PMA_CTRL1_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl2_ch3_reg, PMA_CTRL2_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl3_ch3_reg, PMA_CTRL3_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl4_ch3_reg, PMA_CTRL4_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl5_ch3_reg, PMA_CTRL5_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl6_ch3_reg, PMA_CTRL6_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl7_ch3_reg, PMA_CTRL7_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl8_ch3_reg, PMA_CTRL8_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl9_ch3_reg, PMA_CTRL9_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl10_ch3_reg, PMA_CTRL10_CH3);
        $fdisplay(dbg_file, "%b // %h", pma_ctrl11_ch3_reg, PMA_CTRL11_CH3);
        $fdisplay(dbg_file, "");
                       
        $fclose(dbg_file);
    end
end

////////////////////////////////////////////////////////////////////////////////
// mqmap begin                                                                //
////////////////////////////////////////////////////////////////////////////////
//parameter TX_PMA_ST = 68;
//parameter RX_PMA_ST = 26;  // only used 32: 26 => 48. New ones use index

//logic - in and out: interface to upper level
reg [299:0] rxdprioin_logic_ch0, rxdprioin_logic_ch1, rxdprioin_logic_ch2, rxdprioin_logic_ch3; 
reg [149:0] txdprioin_logic_ch0, txdprioin_logic_ch1, txdprioin_logic_ch2, txdprioin_logic_ch3; 
wire [39:0] cmuplldprioin_logic_0, cmuplldprioin_logic_1, cmuplldprioin_logic_2; 

wire [299:0] rxdprioout_logic_ch0, rxdprioout_logic_ch1, rxdprioout_logic_ch2, rxdprioout_logic_ch3; 
wire [149:0] txdprioout_logic_ch0, txdprioout_logic_ch1, txdprioout_logic_ch2, txdprioout_logic_ch3; 
wire [39:0] cmuplldprioout_logic_0, cmuplldprioout_logic_1, cmuplldprioout_logic_2; 

// phy - in and out: interface to lower level
wire [299:0] rxdprioin_phy_ch0, rxdprioin_phy_ch1, rxdprioin_phy_ch2, rxdprioin_phy_ch3; 
wire [149:0]  txdprioin_phy_ch0, txdprioin_phy_ch1, txdprioin_phy_ch2, txdprioin_phy_ch3; 
wire [39:0]  cmuplldprioin_phy_0, cmuplldprioin_phy_1, cmuplldprioin_phy_2; 

wire [299:0] rxdprioout_phy_ch0, rxdprioout_phy_ch1, rxdprioout_phy_ch2, rxdprioout_phy_ch3; 
wire [149:0]  txdprioout_phy_ch0, txdprioout_phy_ch1, txdprioout_phy_ch2, txdprioout_phy_ch3; 
wire [39:0]  cmuplldprioout_phy_0, cmuplldprioout_phy_1, cmuplldprioout_phy_2; 

// for parameterization
integer i, j;
reg [rx_dprio_width - 1 : 0] rxdprioout_logic_reg; 
reg [tx_dprio_width - 1 : 0] txdprioout_logic_reg; 

// logic
// assign rxdprioin_logic_ch0 = {rxdprioin[899 :800 ], rxdprioin[199:0  ]};
// assign rxdprioin_logic_ch1 = {rxdprioin[999 :900 ], rxdprioin[399:200]};
// assign rxdprioin_logic_ch2 = {rxdprioin[1099:1000], rxdprioin[599:400]};
// assign rxdprioin_logic_ch3 = {rxdprioin[1199:1100], rxdprioin[799:600]};

assign cmuplldprioin_logic_0 = cmuplldprioin[39:0];
assign cmuplldprioin_logic_1 = cmuplldprioin[79:40];
assign cmuplldprioin_logic_2 = cmuplldprioin[119:80];

always @(rxdprioin)
begin
    for (i=0; i<rx_dprio_width; i=i+1)
    begin
        if (i<200)
            rxdprioin_logic_ch0[i] = rxdprioin[i];
        else if (i<400 && i>=200)
            rxdprioin_logic_ch1[i-200] = rxdprioin[i];
        else if (i<600 && i>=400)
            rxdprioin_logic_ch2[i-400] = rxdprioin[i];
        else if (i<800 && i>=600)
            rxdprioin_logic_ch3[i-600] = rxdprioin[i];
        else if (i<900 && i>=800)    
            rxdprioin_logic_ch0[i-800 + 200] = rxdprioin[i];
        else if (i<1000 && i>=900)    
            rxdprioin_logic_ch1[i-900 + 200] = rxdprioin[i];
        else if (i<1100 && i>=1000)    
            rxdprioin_logic_ch2[i-1000 + 200] = rxdprioin[i];        
        else if (i<1200 && i>=1100)    
            rxdprioin_logic_ch3[i-1100 + 200] = rxdprioin[i];        
    end
end


//assign rxdprioout[199:0]   = rxdprioout_logic_ch0[199:0];
//assign rxdprioout[399:200] = rxdprioout_logic_ch1[199:0];
//assign rxdprioout[599:400] = rxdprioout_logic_ch2[199:0];
//assign rxdprioout[799:600] = rxdprioout_logic_ch3[199:0];
// expanded in 6.1
//assign rxdprioout[899 :800 ] = rxdprioout_logic_ch0[299:200];
//assign rxdprioout[999 :900 ] = rxdprioout_logic_ch1[299:200];
//assign rxdprioout[1099:1000] = rxdprioout_logic_ch2[299:200];
//assign rxdprioout[1199:1100] = rxdprioout_logic_ch3[299:200];

assign cmuplldprioout = {cmuplldprioout_logic_2, cmuplldprioout_logic_1, cmuplldprioout_logic_0};

assign rxdprioout = rxdprioout_logic_reg;
always @(rxdprioout_logic_ch0 or rxdprioout_logic_ch1 or rxdprioout_logic_ch2 or rxdprioout_logic_ch3)
begin
    for (i=0; i<rx_dprio_width; i=i+1)
    begin
        if (i<200)
            rxdprioout_logic_reg[i] = rxdprioout_logic_ch0[i];
        else if (i<400 && i>=200)
            rxdprioout_logic_reg[i] = rxdprioout_logic_ch1[i-200];
        else if (i<600 && i>=400)
            rxdprioout_logic_reg[i] = rxdprioout_logic_ch2[i-400];
        else if (i<800 && i>=600)
            rxdprioout_logic_reg[i] = rxdprioout_logic_ch3[i-600];
        else if (i<900 && i>=800)    
            rxdprioout_logic_reg[i] = rxdprioout_logic_ch0[i-800 + 200];
        else if (i<1000 && i>=900)    
            rxdprioout_logic_reg[i] = rxdprioout_logic_ch1[i-900 + 200];
        else if (i<1100 && i>=1000)    
            rxdprioout_logic_reg[i] = rxdprioout_logic_ch2[i-1000 + 200];        
        else if (i<1200 && i>=1100)    
            rxdprioout_logic_reg[i] = rxdprioout_logic_ch3[i-1100 + 200];        
    end
end

//assign txdprioin_logic_ch0 = {txdprioin[449:400], txdprioin[99 :0  ]};
//assign txdprioin_logic_ch1 = {txdprioin[499:450], txdprioin[199:100]};
//assign txdprioin_logic_ch2 = {txdprioin[549:500], txdprioin[299:200]};
//assign txdprioin_logic_ch3 = {txdprioin[599:550], txdprioin[399:300]};
always @(txdprioin)
begin
    for (i=0; i<tx_dprio_width; i=i+1)
    begin
        if (i<100)
            txdprioin_logic_ch0[i] = txdprioin[i];
        else if (i<200 && i>=100)
            txdprioin_logic_ch1[i-100] = txdprioin[i];
        else if (i<300 && i>=200)
            txdprioin_logic_ch2[i-200] = txdprioin[i];
        else if (i<400 && i>=300)
            txdprioin_logic_ch3[i-300] = txdprioin[i];
        else if (i<450 && i>=400)    
            txdprioin_logic_ch0[i-400 + 100] = txdprioin[i];
        else if (i<500 && i>=450)    
            txdprioin_logic_ch1[i-450 + 100] = txdprioin[i];
        else if (i<550 && i>=500)    
            txdprioin_logic_ch2[i-500 + 100] = txdprioin[i];        
        else if (i<600 && i>=550)    
            txdprioin_logic_ch3[i-550 + 100] = txdprioin[i];        
    end
end

//assign txdprioout[99:0]    = txdprioout_logic_ch0[99:0];
//assign txdprioout[199:100] = txdprioout_logic_ch1[99:0];
//assign txdprioout[299:200] = txdprioout_logic_ch2[99:0];
//assign txdprioout[399:300] = txdprioout_logic_ch3[99:0];
// expanded in 6.1
//assign txdprioout[449:400] = txdprioout_logic_ch0[149:100];
//assign txdprioout[499:450] = txdprioout_logic_ch1[149:100];
//assign txdprioout[549:500] = txdprioout_logic_ch2[149:100];
//assign txdprioout[599:550] = txdprioout_logic_ch3[149:100];
assign txdprioout = txdprioout_logic_reg;
always @(txdprioout_logic_ch0 or txdprioout_logic_ch1 or txdprioout_logic_ch2 or txdprioout_logic_ch3)
begin
    for (i=0; i<tx_dprio_width; i=i+1)
    begin
        if (i<100)
            txdprioout_logic_reg[i] = txdprioout_logic_ch0[i];
        else if (i<200 && i>=100)
            txdprioout_logic_reg[i] = txdprioout_logic_ch1[i-100];
        else if (i<300 && i>=200)
            txdprioout_logic_reg[i] = txdprioout_logic_ch2[i-200];
        else if (i<400 && i>=300)
            txdprioout_logic_reg[i] = txdprioout_logic_ch3[i-300];
        else if (i<450 && i>=400)    
            txdprioout_logic_reg[i] = txdprioout_logic_ch0[i-400 + 100];
        else if (i<500 && i>=450)    
            txdprioout_logic_reg[i] = txdprioout_logic_ch1[i-450 + 100];
        else if (i<550 && i>=500)    
            txdprioout_logic_reg[i] = txdprioout_logic_ch2[i-500 + 100];        
        else if (i<600 && i>=550)    
            txdprioout_logic_reg[i] = txdprioout_logic_ch3[i-550 + 100];        
    end
end


// phy map: input is logic --> phy
assign rxdprioin_phy_ch0 = (rx0_phy == 0) ? rxdprioin_logic_ch0 : 
                           (rx1_phy == 0) ? rxdprioin_logic_ch1 :
                           (rx2_phy == 0) ? rxdprioin_logic_ch2 : rxdprioin_logic_ch3;
assign rxdprioin_phy_ch1 = (rx0_phy == 1) ? rxdprioin_logic_ch0 : 
                           (rx1_phy == 1) ? rxdprioin_logic_ch1 :
                           (rx2_phy == 1) ? rxdprioin_logic_ch2 : rxdprioin_logic_ch3;
assign rxdprioin_phy_ch2 = (rx0_phy == 2) ? rxdprioin_logic_ch0 : 
                           (rx1_phy == 2) ? rxdprioin_logic_ch1 :
                           (rx2_phy == 2) ? rxdprioin_logic_ch2 : rxdprioin_logic_ch3;
assign rxdprioin_phy_ch3 = (rx0_phy == 3) ? rxdprioin_logic_ch0 : 
                           (rx1_phy == 3) ? rxdprioin_logic_ch1 :
                           (rx2_phy == 3) ? rxdprioin_logic_ch2 : rxdprioin_logic_ch3;

assign txdprioin_phy_ch0 = (tx0_phy == 0) ? txdprioin_logic_ch0 : 
                           (tx1_phy == 0) ? txdprioin_logic_ch1 :
                           (tx2_phy == 0) ? txdprioin_logic_ch2 : txdprioin_logic_ch3;
assign txdprioin_phy_ch1 = (tx0_phy == 1) ? txdprioin_logic_ch0 : 
                           (tx1_phy == 1) ? txdprioin_logic_ch1 :
                           (tx2_phy == 1) ? txdprioin_logic_ch2 : txdprioin_logic_ch3;
assign txdprioin_phy_ch2 = (tx0_phy == 2) ? txdprioin_logic_ch0 : 
                           (tx1_phy == 2) ? txdprioin_logic_ch1 :
                           (tx2_phy == 2) ? txdprioin_logic_ch2 : txdprioin_logic_ch3;
assign txdprioin_phy_ch3 = (tx0_phy == 3) ? txdprioin_logic_ch0 : 
                           (tx1_phy == 3) ? txdprioin_logic_ch1 :
                           (tx2_phy == 3) ? txdprioin_logic_ch2 : txdprioin_logic_ch3;

assign cmuplldprioin_phy_0 =  (pll0_phy == 0) ? cmuplldprioin_logic_0 : 
                           (pll1_phy == 0) ? cmuplldprioin_logic_1 : cmuplldprioin_logic_2;
assign cmuplldprioin_phy_1 =  (pll0_phy == 1) ? cmuplldprioin_logic_0 : 
                           (pll1_phy == 1) ? cmuplldprioin_logic_1 : cmuplldprioin_logic_2;
assign cmuplldprioin_phy_2 =  (pll0_phy == 2) ? cmuplldprioin_logic_0 : 
                           (pll1_phy == 2) ? cmuplldprioin_logic_1 : cmuplldprioin_logic_2;

// phy map: output is phy --> logic
assign rxdprioout_logic_ch0 = (rx0_phy == 0) ? rxdprioout_phy_ch0 : 
                              (rx0_phy == 1) ? rxdprioout_phy_ch1 :
                              (rx0_phy == 2) ? rxdprioout_phy_ch2 : rxdprioout_phy_ch3;
assign rxdprioout_logic_ch1 = (rx1_phy == 0) ? rxdprioout_phy_ch0 : 
                              (rx1_phy == 1) ? rxdprioout_phy_ch1 :
                              (rx1_phy == 2) ? rxdprioout_phy_ch2 : rxdprioout_phy_ch3;
assign rxdprioout_logic_ch2 = (rx2_phy == 0) ? rxdprioout_phy_ch0 : 
                              (rx2_phy == 1) ? rxdprioout_phy_ch1 :
                              (rx2_phy == 2) ? rxdprioout_phy_ch2 : rxdprioout_phy_ch3;
assign rxdprioout_logic_ch3 = (rx3_phy == 0) ? rxdprioout_phy_ch0 : 
                              (rx3_phy == 1) ? rxdprioout_phy_ch1 :
                              (rx3_phy == 2) ? rxdprioout_phy_ch2 : rxdprioout_phy_ch3;

assign txdprioout_logic_ch0 = (tx0_phy == 0) ? txdprioout_phy_ch0 : 
                              (tx0_phy == 1) ? txdprioout_phy_ch1 :
                              (tx0_phy == 2) ? txdprioout_phy_ch2 : txdprioout_phy_ch3;
assign txdprioout_logic_ch1 = (tx1_phy == 0) ? txdprioout_phy_ch0 : 
                              (tx1_phy == 1) ? txdprioout_phy_ch1 :
                              (tx1_phy == 2) ? txdprioout_phy_ch2 : txdprioout_phy_ch3;
assign txdprioout_logic_ch2 = (tx2_phy == 0) ? txdprioout_phy_ch0 : 
                              (tx2_phy == 1) ? txdprioout_phy_ch1 :
                              (tx2_phy == 2) ? txdprioout_phy_ch2 : txdprioout_phy_ch3;
assign txdprioout_logic_ch3 = (tx3_phy == 0) ? txdprioout_phy_ch0 : 
                              (tx3_phy == 1) ? txdprioout_phy_ch1 :
                              (tx3_phy == 2) ? txdprioout_phy_ch2 : txdprioout_phy_ch3;

assign cmuplldprioout_logic_0 =  (pll0_phy == 0) ? cmuplldprioout_phy_0 : 
                              (pll0_phy == 1) ? cmuplldprioout_phy_1 : cmuplldprioout_phy_1;
assign cmuplldprioout_logic_1 =  (pll1_phy == 0) ? cmuplldprioout_phy_0 : 
                              (pll1_phy == 1) ? cmuplldprioout_phy_1 : cmuplldprioout_phy_1;
assign cmuplldprioout_logic_2 =  (pll2_phy == 0) ? cmuplldprioout_phy_0 : 
                              (pll2_phy == 1) ? cmuplldprioout_phy_1 : cmuplldprioout_phy_1;

//CMUPLL clock_select begin ------------------------------------------------------------
// CMUPLL_CLOCK_SElECT - input (parameter) ------------------------------------------------
// -------------------------------------------------------------------------------------
initial begin
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ0]        = 6'b10z000;
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ1]        = 6'b10z001;
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ2]        = 6'b10z010;
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ3]        = 6'b10z011;
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ4]        = 6'b10z100;
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_PLD_CLK]    = 6'b10z101;
    // iqsel below is donot care so take default for preventing X values passing around
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_REFCLK0]    = 6'b00z000; 
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_REFCLK1]    = 6'b01z000;
    cmupll0_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_ERR]        = 6'b11z111;
    
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ0]        = 6'b10z000;
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ1]        = 6'b10z001;
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ2]        = 6'b10z010;
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ3]        = 6'b10z011;
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_IQ4]        = 6'b10z100;
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_PLD_CLK]    = 6'b10z101;
    // iqsel below is donot care so take default for preventing X values passing around
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_REFCLK0]    = 6'b01z000; 
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_REFCLK1]    = 6'b00z000;
    cmupll1_clock_phyport_to_cram[`CMUPLL_CLOCK_SELECT_ERR]        = 6'b11z111;
end

initial begin
    cmupll0_clock_index_to_phyport[0] = convert_cmupll_phyport_str_to_phyport_enum(pll0_inclk0_logical_to_physical_mapping);
    cmupll0_clock_index_to_phyport[1] = convert_cmupll_phyport_str_to_phyport_enum(pll0_inclk1_logical_to_physical_mapping);
    cmupll0_clock_index_to_phyport[2] = convert_cmupll_phyport_str_to_phyport_enum(pll0_inclk2_logical_to_physical_mapping);
    cmupll0_clock_index_to_phyport[3] = convert_cmupll_phyport_str_to_phyport_enum(pll0_inclk3_logical_to_physical_mapping);
    cmupll0_clock_index_to_phyport[4] = convert_cmupll_phyport_str_to_phyport_enum(pll0_inclk4_logical_to_physical_mapping);
    cmupll0_clock_index_to_phyport[5] = convert_cmupll_phyport_str_to_phyport_enum(pll0_inclk5_logical_to_physical_mapping);
    cmupll0_clock_index_to_phyport[6] = convert_cmupll_phyport_str_to_phyport_enum(pll0_inclk6_logical_to_physical_mapping);
    cmupll0_clock_index_to_phyport[7] = convert_cmupll_phyport_str_to_phyport_enum(pll0_inclk7_logical_to_physical_mapping);

    cmupll1_clock_index_to_phyport[0] = convert_cmupll_phyport_str_to_phyport_enum(pll1_inclk0_logical_to_physical_mapping);
    cmupll1_clock_index_to_phyport[1] = convert_cmupll_phyport_str_to_phyport_enum(pll1_inclk1_logical_to_physical_mapping);
    cmupll1_clock_index_to_phyport[2] = convert_cmupll_phyport_str_to_phyport_enum(pll1_inclk2_logical_to_physical_mapping);
    cmupll1_clock_index_to_phyport[3] = convert_cmupll_phyport_str_to_phyport_enum(pll1_inclk3_logical_to_physical_mapping);
    cmupll1_clock_index_to_phyport[4] = convert_cmupll_phyport_str_to_phyport_enum(pll1_inclk4_logical_to_physical_mapping);
    cmupll1_clock_index_to_phyport[5] = convert_cmupll_phyport_str_to_phyport_enum(pll1_inclk5_logical_to_physical_mapping);
    cmupll1_clock_index_to_phyport[6] = convert_cmupll_phyport_str_to_phyport_enum(pll1_inclk6_logical_to_physical_mapping);
    cmupll1_clock_index_to_phyport[7] = convert_cmupll_phyport_str_to_phyport_enum(pll1_inclk7_logical_to_physical_mapping);

end

// pll0 - logic channel
assign cmupll0_clock_select = ((cmuplldprioin_logic_0[`refclk_select_DP_CMUPLL_IDX_0] === 1'b1 || cmuplldprioin_logic_0[`refclk_select_DP_CMUPLL_IDX_0] === 1'b0) &&
                               (cmuplldprioin_logic_0[`refclk_select_DP_CMUPLL_IDX_1] === 1'b1 || cmuplldprioin_logic_0[`refclk_select_DP_CMUPLL_IDX_1] === 1'b0) &&
                               (cmuplldprioin_logic_0[`refclk_select_DP_CMUPLL_IDX_2] === 1'b1 || cmuplldprioin_logic_0[`refclk_select_DP_CMUPLL_IDX_2] === 1'b0)) ? 
                               cmuplldprioin_logic_0[`refclk_select_DP_CMUPLL_IDX_2 : `refclk_select_DP_CMUPLL_IDX_0] : 3'b000;

assign cmupll0_clock_phyport = cmupll0_clock_index_to_phyport[cmupll0_clock_select];
// switch to physical PLL number as the phyport_to_cram conversion based on NPP is on physical PLL channel
assign cmupll0_clock_phyport_phy = (pll0_phy == 0) ? cmupll0_clock_phyport : cmupll1_clock_phyport;
// this table is on physical channel
assign cmupll0_clock_cram_phy = cmupll0_clock_phyport_to_cram[cmupll0_clock_phyport_phy];
assign rcmu0_ref_sel           = cmupll0_clock_cram_phy[5:4];
assign rcmu_txpll0_iqclkin_sel = cmupll0_clock_cram_phy[2:0];

// pll1 - logic channel
assign cmupll1_clock_select = ((cmuplldprioin_logic_1[`refclk_select_DP_CMUPLL_IDX_0] === 1'b1 || cmuplldprioin_logic_1[`refclk_select_DP_CMUPLL_IDX_0] === 1'b0) &&
                               (cmuplldprioin_logic_1[`refclk_select_DP_CMUPLL_IDX_1] === 1'b1 || cmuplldprioin_logic_1[`refclk_select_DP_CMUPLL_IDX_1] === 1'b0) &&
                               (cmuplldprioin_logic_1[`refclk_select_DP_CMUPLL_IDX_2] === 1'b1 || cmuplldprioin_logic_1[`refclk_select_DP_CMUPLL_IDX_2] === 1'b0)) ? 
                               cmuplldprioin_logic_1[`refclk_select_DP_CMUPLL_IDX_2 : `refclk_select_DP_CMUPLL_IDX_0] : 3'b000;

assign cmupll1_clock_phyport = cmupll1_clock_index_to_phyport[cmupll1_clock_select];
// switch to physical PLL number as the phyport_to_cram conversion based on NPP is on physical PLL channel
assign cmupll1_clock_phyport_phy = (pll1_phy == 1) ? cmupll1_clock_phyport : cmupll0_clock_phyport;
// this table is on physical channel
assign cmupll1_clock_cram_phy = cmupll1_clock_phyport_to_cram[cmupll1_clock_phyport_phy];
assign rcmu1_ref_sel           = cmupll1_clock_cram_phy[5:4];
assign rcmu_txpll1_iqclkin_sel = cmupll1_clock_cram_phy[2:0];

                                
// CMUPLL_CLOCK_SElECT - output (parameter) ------------------------------
// pll0 - CRMA on physical 
assign cmupll0_clock_phyport_out = convert_cmupll0_clock_cram_to_phyport(rcmu0_ref_sel_int, rcmu_txpll0_iqclkin_sel_int);
// but the map is on logic channel 
assign cmupll0_clock_phyport_out_logic = (pll0_phy == 0) ? cmupll0_clock_phyport_out : cmupll1_clock_phyport_out;

assign cmupll0_clock_select_out_logic = (cmupll0_clock_index_to_phyport[0] === cmupll0_clock_phyport_out_logic) ? 4'b0000 : 
                                        (cmupll0_clock_index_to_phyport[1] === cmupll0_clock_phyport_out_logic) ? 4'b0001 : 
                                        (cmupll0_clock_index_to_phyport[2] === cmupll0_clock_phyport_out_logic) ? 4'b0010 : 
                                        (cmupll0_clock_index_to_phyport[3] === cmupll0_clock_phyport_out_logic) ? 4'b0011 : 
                                        (cmupll0_clock_index_to_phyport[4] === cmupll0_clock_phyport_out_logic) ? 4'b0100 : 
                                        (cmupll0_clock_index_to_phyport[5] === cmupll0_clock_phyport_out_logic) ? 4'b0101 : 
                                        (cmupll0_clock_index_to_phyport[6] === cmupll0_clock_phyport_out_logic) ? 4'b0110 : 
                                        (cmupll0_clock_index_to_phyport[7] === cmupll0_clock_phyport_out_logic) ? 4'b0111 : 
                                        4'b1000;  // invalid cram values
// back to physical
assign cmupll0_clock_select_out = (pll0_phy == 0) ? cmupll0_clock_select_out_logic : cmupll1_clock_select_out_logic;
                                                                          
assign cmuplldprioout_phy_0[`refclk_select_DP_CMUPLL_IDX_2 :  `refclk_select_DP_CMUPLL_IDX_0] = cmupll0_clock_select_out[2:0];                            

// pll1 - CRMA on physical 
assign cmupll1_clock_phyport_out = convert_cmupll1_clock_cram_to_phyport(rcmu1_ref_sel_int, rcmu_txpll1_iqclkin_sel_int);
// but the map is on logic channel 
assign cmupll1_clock_phyport_out_logic = (pll1_phy == 1) ? cmupll1_clock_phyport_out : cmupll0_clock_phyport_out;

assign cmupll1_clock_select_out_logic = (cmupll1_clock_index_to_phyport[0] === cmupll1_clock_phyport_out_logic) ? 4'b0000 : 
                                        (cmupll1_clock_index_to_phyport[1] === cmupll1_clock_phyport_out_logic) ? 4'b0001 : 
                                        (cmupll1_clock_index_to_phyport[2] === cmupll1_clock_phyport_out_logic) ? 4'b0010 : 
                                        (cmupll1_clock_index_to_phyport[3] === cmupll1_clock_phyport_out_logic) ? 4'b0011 : 
                                        (cmupll1_clock_index_to_phyport[4] === cmupll1_clock_phyport_out_logic) ? 4'b0100 : 
                                        (cmupll1_clock_index_to_phyport[5] === cmupll1_clock_phyport_out_logic) ? 4'b0101 : 
                                        (cmupll1_clock_index_to_phyport[6] === cmupll1_clock_phyport_out_logic) ? 4'b0110 : 
                                        (cmupll1_clock_index_to_phyport[7] === cmupll1_clock_phyport_out_logic) ? 4'b0111 : 
                                        4'b1000;  // invalid cram values
// back to physical
assign cmupll1_clock_select_out = (pll1_phy == 1) ? cmupll1_clock_select_out_logic : cmupll0_clock_select_out_logic;
                                                                          
assign cmuplldprioout_phy_1[`refclk_select_DP_CMUPLL_IDX_2 :  `refclk_select_DP_CMUPLL_IDX_0] = cmupll1_clock_select_out[2:0];                            

                          
// CRU_CLOCK_SElECT - input (parameter) ------------------------------------------------
// cram rrefclk_sel_ch0_int in PMA page 6
// rrx_piso_bypass_ch0_int in PMA page 4
// -------------------------------------------------------------------------------------
initial begin
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_NONE]       = 6'b111z11;
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_IQ0]        = 6'b000z11;
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_IQ1]        = 6'b001z11;
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_IQ2]        = 6'b010z11;
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_IQ3]        = 6'b011z11;
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_IQ4]        = 6'b100z11;
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_PLD_CRU_CLK]= 6'b101z11;
    // rrefclk_sel below is donot care so take default for preventing X values passing around
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_REFCLK0]    = 6'b000z00; 
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_REFCLK1]    = 6'b000z01;
    cru_clock_phyport_to_cram[`CRU_CLOCK_SELECT_CMU_DIV_CLK]= 6'b000z10;
end

initial begin
    rx0_cru_clock_index_to_phyport[0] = convert_phyport_str_to_phyport_enum(rx0_cru_clock0_physical_mapping);
    rx0_cru_clock_index_to_phyport[1] = convert_phyport_str_to_phyport_enum(rx0_cru_clock1_physical_mapping);
    rx0_cru_clock_index_to_phyport[2] = convert_phyport_str_to_phyport_enum(rx0_cru_clock2_physical_mapping);
    rx0_cru_clock_index_to_phyport[3] = convert_phyport_str_to_phyport_enum(rx0_cru_clock3_physical_mapping);
    rx0_cru_clock_index_to_phyport[4] = convert_phyport_str_to_phyport_enum(rx0_cru_clock4_physical_mapping);
    rx0_cru_clock_index_to_phyport[5] = convert_phyport_str_to_phyport_enum(rx0_cru_clock5_physical_mapping);
    rx0_cru_clock_index_to_phyport[6] = convert_phyport_str_to_phyport_enum(rx0_cru_clock6_physical_mapping);
    rx0_cru_clock_index_to_phyport[7] = convert_phyport_str_to_phyport_enum(rx0_cru_clock7_physical_mapping);
    rx0_cru_clock_index_to_phyport[8] = convert_phyport_str_to_phyport_enum(rx0_cru_clock8_physical_mapping);

    rx1_cru_clock_index_to_phyport[0] = convert_phyport_str_to_phyport_enum(rx1_cru_clock0_physical_mapping);
    rx1_cru_clock_index_to_phyport[1] = convert_phyport_str_to_phyport_enum(rx1_cru_clock1_physical_mapping);
    rx1_cru_clock_index_to_phyport[2] = convert_phyport_str_to_phyport_enum(rx1_cru_clock2_physical_mapping);
    rx1_cru_clock_index_to_phyport[3] = convert_phyport_str_to_phyport_enum(rx1_cru_clock3_physical_mapping);
    rx1_cru_clock_index_to_phyport[4] = convert_phyport_str_to_phyport_enum(rx1_cru_clock4_physical_mapping);
    rx1_cru_clock_index_to_phyport[5] = convert_phyport_str_to_phyport_enum(rx1_cru_clock5_physical_mapping);
    rx1_cru_clock_index_to_phyport[6] = convert_phyport_str_to_phyport_enum(rx1_cru_clock6_physical_mapping);
    rx1_cru_clock_index_to_phyport[7] = convert_phyport_str_to_phyport_enum(rx1_cru_clock7_physical_mapping);
    rx1_cru_clock_index_to_phyport[8] = convert_phyport_str_to_phyport_enum(rx1_cru_clock8_physical_mapping);

    rx2_cru_clock_index_to_phyport[0] = convert_phyport_str_to_phyport_enum(rx2_cru_clock0_physical_mapping);
    rx2_cru_clock_index_to_phyport[1] = convert_phyport_str_to_phyport_enum(rx2_cru_clock1_physical_mapping);
    rx2_cru_clock_index_to_phyport[2] = convert_phyport_str_to_phyport_enum(rx2_cru_clock2_physical_mapping);
    rx2_cru_clock_index_to_phyport[3] = convert_phyport_str_to_phyport_enum(rx2_cru_clock3_physical_mapping);
    rx2_cru_clock_index_to_phyport[4] = convert_phyport_str_to_phyport_enum(rx2_cru_clock4_physical_mapping);
    rx2_cru_clock_index_to_phyport[5] = convert_phyport_str_to_phyport_enum(rx2_cru_clock5_physical_mapping);
    rx2_cru_clock_index_to_phyport[6] = convert_phyport_str_to_phyport_enum(rx2_cru_clock6_physical_mapping);
    rx2_cru_clock_index_to_phyport[7] = convert_phyport_str_to_phyport_enum(rx2_cru_clock7_physical_mapping);
    rx2_cru_clock_index_to_phyport[8] = convert_phyport_str_to_phyport_enum(rx2_cru_clock8_physical_mapping);

    rx3_cru_clock_index_to_phyport[0] = convert_phyport_str_to_phyport_enum(rx3_cru_clock0_physical_mapping);
    rx3_cru_clock_index_to_phyport[1] = convert_phyport_str_to_phyport_enum(rx3_cru_clock1_physical_mapping);
    rx3_cru_clock_index_to_phyport[2] = convert_phyport_str_to_phyport_enum(rx3_cru_clock2_physical_mapping);
    rx3_cru_clock_index_to_phyport[3] = convert_phyport_str_to_phyport_enum(rx3_cru_clock3_physical_mapping);
    rx3_cru_clock_index_to_phyport[4] = convert_phyport_str_to_phyport_enum(rx3_cru_clock4_physical_mapping);
    rx3_cru_clock_index_to_phyport[5] = convert_phyport_str_to_phyport_enum(rx3_cru_clock5_physical_mapping);
    rx3_cru_clock_index_to_phyport[6] = convert_phyport_str_to_phyport_enum(rx3_cru_clock6_physical_mapping);
    rx3_cru_clock_index_to_phyport[7] = convert_phyport_str_to_phyport_enum(rx3_cru_clock7_physical_mapping);
    rx3_cru_clock_index_to_phyport[8] = convert_phyport_str_to_phyport_enum(rx3_cru_clock8_physical_mapping); 
end

// logic channel
assign rx0_cru_clock_select = ((rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_0] === 1'b1 || rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_0] === 1'b0) &&
                               (rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_1] === 1'b1 || rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_1] === 1'b0) &&
                               (rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_2] === 1'b1 || rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_2] === 1'b0) &&
                               (rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_3] === 1'b1 || rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_3] === 1'b0)) ? 
                               rxdprioin_logic_ch0[`cru_clock_select_DP_RX_IDX_3 : `cru_clock_select_DP_RX_IDX_0] : 4'b0000;

assign rx0_cru_clock_phyport = rx0_cru_clock_index_to_phyport[rx0_cru_clock_select];
assign rx0_cru_clock_cram_logic = cru_clock_phyport_to_cram[rx0_cru_clock_phyport];
// logic to physical
assign rx0_cru_clock_cram_phy = (rx0_phy == 0) ? rx0_cru_clock_cram_logic : 
                                (rx1_phy == 0) ? rx1_cru_clock_cram_logic :
                                (rx2_phy == 0) ? rx2_cru_clock_cram_logic : rx3_cru_clock_cram_logic;                  
assign rrefclk_sel_ch0         = rx0_cru_clock_cram_phy[5:3];
assign rrx_piso_bypass_ch0     = rx0_cru_clock_cram_phy[1:0];

// logic channel
assign rx1_cru_clock_select = ((rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_0] === 1'b1 || rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_0] === 1'b0) &&
                               (rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_1] === 1'b1 || rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_1] === 1'b0) &&
                               (rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_2] === 1'b1 || rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_2] === 1'b0) &&
                               (rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_3] === 1'b1 || rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_3] === 1'b0)) ? 
                               rxdprioin_logic_ch1[`cru_clock_select_DP_RX_IDX_3 : `cru_clock_select_DP_RX_IDX_0] : 4'b0000;

assign rx1_cru_clock_phyport = rx1_cru_clock_index_to_phyport[rx1_cru_clock_select];
assign rx1_cru_clock_cram_logic = cru_clock_phyport_to_cram[rx1_cru_clock_phyport];
// logic to physical
assign rx1_cru_clock_cram_phy = (rx0_phy == 1) ? rx0_cru_clock_cram_logic : 
                                (rx1_phy == 1) ? rx1_cru_clock_cram_logic :
                                (rx2_phy == 1) ? rx2_cru_clock_cram_logic : rx3_cru_clock_cram_logic;                  
assign rrefclk_sel_ch1         = rx1_cru_clock_cram_phy[5:3];
assign rrx_piso_bypass_ch1     = rx1_cru_clock_cram_phy[1:0];

// logic channel
assign rx2_cru_clock_select = ((rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_0] === 1'b1 || rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_0] === 1'b0) &&
                               (rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_1] === 1'b1 || rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_1] === 1'b0) &&
                               (rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_2] === 1'b1 || rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_2] === 1'b0) &&
                               (rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_3] === 1'b1 || rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_3] === 1'b0)) ? 
                               rxdprioin_logic_ch2[`cru_clock_select_DP_RX_IDX_3 : `cru_clock_select_DP_RX_IDX_0] : 4'b0000;

assign rx2_cru_clock_phyport = rx2_cru_clock_index_to_phyport[rx2_cru_clock_select];
assign rx2_cru_clock_cram_logic = cru_clock_phyport_to_cram[rx2_cru_clock_phyport];
// logic to physical
assign rx2_cru_clock_cram_phy = (rx0_phy == 2) ? rx0_cru_clock_cram_logic : 
                                (rx1_phy == 2) ? rx1_cru_clock_cram_logic :
                                (rx2_phy == 2) ? rx2_cru_clock_cram_logic : rx3_cru_clock_cram_logic;                  
assign rrefclk_sel_ch2         = rx2_cru_clock_cram_phy[5:3];
assign rrx_piso_bypass_ch2     = rx2_cru_clock_cram_phy[1:0];

// logic channel
assign rx3_cru_clock_select = ((rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_0] === 1'b1 || rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_0] === 1'b0) &&
                               (rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_1] === 1'b1 || rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_1] === 1'b0) &&
                               (rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_2] === 1'b1 || rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_2] === 1'b0) &&
                               (rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_3] === 1'b1 || rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_3] === 1'b0)) ? 
                               rxdprioin_logic_ch3[`cru_clock_select_DP_RX_IDX_3 : `cru_clock_select_DP_RX_IDX_0] : 4'b0000;

assign rx3_cru_clock_phyport = rx3_cru_clock_index_to_phyport[rx3_cru_clock_select];
assign rx3_cru_clock_cram_logic = cru_clock_phyport_to_cram[rx3_cru_clock_phyport];
// logic to physical
assign rx3_cru_clock_cram_phy = (rx0_phy == 3) ? rx0_cru_clock_cram_logic : 
                                (rx1_phy == 3) ? rx1_cru_clock_cram_logic :
                                (rx2_phy == 3) ? rx2_cru_clock_cram_logic : rx3_cru_clock_cram_logic;                  
assign rrefclk_sel_ch3         = rx3_cru_clock_cram_phy[5:3];
assign rrx_piso_bypass_ch3     = rx3_cru_clock_cram_phy[1:0];

                                
// CRU_CLOCK_SElECT - output (parameter) ------------------------------
// CRMA on physical ch
assign rx0_cru_clock_phyport_out = convert_cru_clock_cram_to_phyport(rrefclk_sel_ch0_int,rrx_piso_bypass_ch0_int);
// but the map is on logic channel 
assign rx0_cru_clock_phyport_out_logic = (rx0_phy == 0) ? rx0_cru_clock_phyport_out :
                                         (rx0_phy == 1) ? rx1_cru_clock_phyport_out :
                                         (rx0_phy == 2) ? rx2_cru_clock_phyport_out : rx3_cru_clock_phyport_out;

assign rx0_cru_clock_select_out_logic = (rx0_cru_clock_index_to_phyport[0] === rx0_cru_clock_phyport_out_logic) ? 4'b0000 : 
                                        (rx0_cru_clock_index_to_phyport[1] === rx0_cru_clock_phyport_out_logic) ? 4'b0001 : 
                                        (rx0_cru_clock_index_to_phyport[2] === rx0_cru_clock_phyport_out_logic) ? 4'b0010 : 
                                        (rx0_cru_clock_index_to_phyport[3] === rx0_cru_clock_phyport_out_logic) ? 4'b0011 : 
                                        (rx0_cru_clock_index_to_phyport[4] === rx0_cru_clock_phyport_out_logic) ? 4'b0100 : 
                                        (rx0_cru_clock_index_to_phyport[5] === rx0_cru_clock_phyport_out_logic) ? 4'b0101 : 
                                        (rx0_cru_clock_index_to_phyport[6] === rx0_cru_clock_phyport_out_logic) ? 4'b0110 : 
                                        (rx0_cru_clock_index_to_phyport[7] === rx0_cru_clock_phyport_out_logic) ? 4'b0111 : 
                                        (rx0_cru_clock_index_to_phyport[8] === rx0_cru_clock_phyport_out_logic) ? 4'b1000 : 
                                        4'b1111;  // invalid cram values
// back to physical
assign rx0_cru_clock_select_out = (rx0_phy == 0) ? rx0_cru_clock_select_out_logic :
                                  (rx1_phy == 0) ? rx1_cru_clock_select_out_logic :
                                  (rx2_phy == 0) ? rx2_cru_clock_select_out_logic : rx3_cru_clock_select_out_logic;
                                                                          
assign rxdprioout_phy_ch0[`cru_clock_select_DP_RX_IDX_3 :  `cru_clock_select_DP_RX_IDX_0] = rx0_cru_clock_select_out;                            

// ch1
// CRMA on physical ch
assign rx1_cru_clock_phyport_out = convert_cru_clock_cram_to_phyport(rrefclk_sel_ch1_int,rrx_piso_bypass_ch1_int);
// but the map is on logic channel 
assign rx1_cru_clock_phyport_out_logic = (rx1_phy == 0) ? rx0_cru_clock_phyport_out :
                                         (rx1_phy == 1) ? rx1_cru_clock_phyport_out :
                                         (rx1_phy == 2) ? rx2_cru_clock_phyport_out : rx3_cru_clock_phyport_out;

assign rx1_cru_clock_select_out_logic = (rx1_cru_clock_index_to_phyport[0] === rx1_cru_clock_phyport_out_logic) ? 4'b0000 : 
                                        (rx1_cru_clock_index_to_phyport[1] === rx1_cru_clock_phyport_out_logic) ? 4'b0001 : 
                                        (rx1_cru_clock_index_to_phyport[2] === rx1_cru_clock_phyport_out_logic) ? 4'b0010 : 
                                        (rx1_cru_clock_index_to_phyport[3] === rx1_cru_clock_phyport_out_logic) ? 4'b0011 : 
                                        (rx1_cru_clock_index_to_phyport[4] === rx1_cru_clock_phyport_out_logic) ? 4'b0100 : 
                                        (rx1_cru_clock_index_to_phyport[5] === rx1_cru_clock_phyport_out_logic) ? 4'b0101 : 
                                        (rx1_cru_clock_index_to_phyport[6] === rx1_cru_clock_phyport_out_logic) ? 4'b0110 : 
                                        (rx1_cru_clock_index_to_phyport[7] === rx1_cru_clock_phyport_out_logic) ? 4'b0111 : 
                                        (rx1_cru_clock_index_to_phyport[8] === rx1_cru_clock_phyport_out_logic) ? 4'b1000 : 
                                        4'b1111;  // invalid cram values
// back to physical
assign rx1_cru_clock_select_out = (rx0_phy == 1) ? rx0_cru_clock_select_out_logic :
                                  (rx1_phy == 1) ? rx1_cru_clock_select_out_logic :
                                  (rx2_phy == 1) ? rx2_cru_clock_select_out_logic : rx3_cru_clock_select_out_logic;
                                                                          
assign rxdprioout_phy_ch1[`cru_clock_select_DP_RX_IDX_3 :  `cru_clock_select_DP_RX_IDX_0] = rx1_cru_clock_select_out;                            

// ch2
// CRMA on physical ch
assign rx2_cru_clock_phyport_out = convert_cru_clock_cram_to_phyport(rrefclk_sel_ch2_int,rrx_piso_bypass_ch2_int);
// but the map is on logic channel 
assign rx2_cru_clock_phyport_out_logic = (rx2_phy == 0) ? rx0_cru_clock_phyport_out :
                                         (rx2_phy == 1) ? rx1_cru_clock_phyport_out :
                                         (rx2_phy == 2) ? rx2_cru_clock_phyport_out : rx3_cru_clock_phyport_out;

assign rx2_cru_clock_select_out_logic = (rx2_cru_clock_index_to_phyport[0] === rx2_cru_clock_phyport_out_logic) ? 4'b0000 : 
                                        (rx2_cru_clock_index_to_phyport[1] === rx2_cru_clock_phyport_out_logic) ? 4'b0001 : 
                                        (rx2_cru_clock_index_to_phyport[2] === rx2_cru_clock_phyport_out_logic) ? 4'b0010 : 
                                        (rx2_cru_clock_index_to_phyport[3] === rx2_cru_clock_phyport_out_logic) ? 4'b0011 : 
                                        (rx2_cru_clock_index_to_phyport[4] === rx2_cru_clock_phyport_out_logic) ? 4'b0100 : 
                                        (rx2_cru_clock_index_to_phyport[5] === rx2_cru_clock_phyport_out_logic) ? 4'b0101 : 
                                        (rx2_cru_clock_index_to_phyport[6] === rx2_cru_clock_phyport_out_logic) ? 4'b0110 : 
                                        (rx2_cru_clock_index_to_phyport[7] === rx2_cru_clock_phyport_out_logic) ? 4'b0111 : 
                                        (rx2_cru_clock_index_to_phyport[8] === rx2_cru_clock_phyport_out_logic) ? 4'b1000 : 
                                        4'b1111;  // invalid cram values
// back to physical
assign rx2_cru_clock_select_out = (rx0_phy == 2) ? rx0_cru_clock_select_out_logic :
                                  (rx1_phy == 2) ? rx1_cru_clock_select_out_logic :
                                  (rx2_phy == 2) ? rx2_cru_clock_select_out_logic : rx3_cru_clock_select_out_logic;
                                                                          
assign rxdprioout_phy_ch2[`cru_clock_select_DP_RX_IDX_3 :  `cru_clock_select_DP_RX_IDX_0] = rx2_cru_clock_select_out;                            

// ch3
// CRMA on physical ch
assign rx3_cru_clock_phyport_out = convert_cru_clock_cram_to_phyport(rrefclk_sel_ch3_int,rrx_piso_bypass_ch3_int);
// but the map is on logic channel 
assign rx3_cru_clock_phyport_out_logic = (rx3_phy == 0) ? rx0_cru_clock_phyport_out :
                                         (rx3_phy == 1) ? rx1_cru_clock_phyport_out :
                                         (rx3_phy == 2) ? rx2_cru_clock_phyport_out : rx3_cru_clock_phyport_out;

assign rx3_cru_clock_select_out_logic = (rx3_cru_clock_index_to_phyport[0] === rx3_cru_clock_phyport_out_logic) ? 4'b0000 : 
                                        (rx3_cru_clock_index_to_phyport[1] === rx3_cru_clock_phyport_out_logic) ? 4'b0001 : 
                                        (rx3_cru_clock_index_to_phyport[2] === rx3_cru_clock_phyport_out_logic) ? 4'b0010 : 
                                        (rx3_cru_clock_index_to_phyport[3] === rx3_cru_clock_phyport_out_logic) ? 4'b0011 : 
                                        (rx3_cru_clock_index_to_phyport[4] === rx3_cru_clock_phyport_out_logic) ? 4'b0100 : 
                                        (rx3_cru_clock_index_to_phyport[5] === rx3_cru_clock_phyport_out_logic) ? 4'b0101 : 
                                        (rx3_cru_clock_index_to_phyport[6] === rx3_cru_clock_phyport_out_logic) ? 4'b0110 : 
                                        (rx3_cru_clock_index_to_phyport[7] === rx3_cru_clock_phyport_out_logic) ? 4'b0111 : 
                                        (rx3_cru_clock_index_to_phyport[8] === rx3_cru_clock_phyport_out_logic) ? 4'b1000 : 
                                        4'b1111;  // invalid cram values
// back to physical
assign rx3_cru_clock_select_out = (rx0_phy == 3) ? rx0_cru_clock_select_out_logic :
                                  (rx1_phy == 3) ? rx1_cru_clock_select_out_logic :
                                  (rx2_phy == 3) ? rx2_cru_clock_select_out_logic : rx3_cru_clock_select_out_logic;
                                                                          
assign rxdprioout_phy_ch3[`cru_clock_select_DP_RX_IDX_3 :  `cru_clock_select_DP_RX_IDX_0] = rx3_cru_clock_select_out;                            

// Tx clock divider refclk selection ---------------------------------------------------------------------------------------- 
// needs logic to physical mapping as logic pll0 can place into physical pll1
// selection_pll0 CRAM means physical PLL0

// input -------------------------------------------------------------------------------

assign rtx_cmu_sel_logic[0]  = (txdprioin_logic_ch0[`rtx_cmu_sel_DP_TX_IDX] === 1'b0) ?   // tx0 uses logic pll0
                                ((tx0_pll_fast_clk0_physical_mapping == "pll0") ? 1'b0 :    // logic pll0 placed at phy pll0
                                                                                  1'b1)     // logic pll0 placed at phy pll1
                               :                                                         //  tx0 uses logic pll1
                                ((tx0_pll_fast_clk1_physical_mapping == "pll0") ? 1'b0 :    // logic pll1 places at phy pll0
                                                                                  1'b1);    // logic pll1 placed at phy pll1
// phy channel tx                                
assign rtx_cmu_sel[0]        = (tx0_phy == 0) ? rtx_cmu_sel_logic[0] : 
                               (tx1_phy == 0) ? rtx_cmu_sel_logic[1] :
                               (tx2_phy == 0) ? rtx_cmu_sel_logic[2] : rtx_cmu_sel_logic[3];
 
assign rtx_cmu_sel_logic[1]  = (txdprioin_logic_ch1[`rtx_cmu_sel_DP_TX_IDX] === 1'b0) ?   // tx1 uses logic pll0
                                ((tx1_pll_fast_clk0_physical_mapping == "pll0") ? 1'b0 :    // logic pll0 placed at phy pll0
                                                                                  1'b1)     // logic pll0 placed at phy pll1
                               :                                                         //  tx1 uses logic pll1
                                ((tx1_pll_fast_clk1_physical_mapping == "pll0") ? 1'b0 :    // logic pll1 places at phy pll0
                                                                                  1'b1);    // logic pll1 placed at phy pll1
// phy channel tx                                
assign rtx_cmu_sel[1]        = (tx0_phy == 1) ? rtx_cmu_sel_logic[0] : 
                               (tx1_phy == 1) ? rtx_cmu_sel_logic[1] :
                               (tx2_phy == 1) ? rtx_cmu_sel_logic[2] : rtx_cmu_sel_logic[3];
 
assign rtx_cmu_sel_logic[2]  = (txdprioin_logic_ch2[`rtx_cmu_sel_DP_TX_IDX] === 1'b0) ?   // tx2 uses logic pll0
                                ((tx2_pll_fast_clk0_physical_mapping == "pll0") ? 1'b0 :    // logic pll0 placed at phy pll0
                                                                                  1'b1)     // logic pll0 placed at phy pll1
                               :                                                         //  tx2 uses logic pll1
                                ((tx2_pll_fast_clk1_physical_mapping == "pll0") ? 1'b0 :    // logic pll1 places at phy pll0
                                                                                  1'b1);    // logic pll1 placed at phy pll1
// phy channel tx                                
assign rtx_cmu_sel[2]        = (tx0_phy == 2) ? rtx_cmu_sel_logic[0] : 
                               (tx1_phy == 2) ? rtx_cmu_sel_logic[1] :
                               (tx2_phy == 2) ? rtx_cmu_sel_logic[2] : rtx_cmu_sel_logic[3];
 
assign rtx_cmu_sel_logic[3]  = (txdprioin_logic_ch3[`rtx_cmu_sel_DP_TX_IDX] === 1'b0) ?   // tx3 uses logic pll0
                                ((tx3_pll_fast_clk0_physical_mapping == "pll0") ? 1'b0 :    // logic pll0 placed at phy pll0
                                                                                  1'b1)     // logic pll0 placed at phy pll1
                               :                                                         //  tx3 uses logic pll1
                                ((tx3_pll_fast_clk1_physical_mapping == "pll0") ? 1'b0 :    // logic pll1 places at phy pll0
                                                                                  1'b1);    // logic pll1 placed at phy pll1
// phy channel tx                                
assign rtx_cmu_sel[3]        = (tx0_phy == 3) ? rtx_cmu_sel_logic[0] : 
                               (tx1_phy == 3) ? rtx_cmu_sel_logic[1] :
                               (tx2_phy == 3) ? rtx_cmu_sel_logic[2] : rtx_cmu_sel_logic[3];
 
                     
// output --------------------------------------------------------------------------------
// resolve to logic refclk (pll0/1) selection

// work on logic tx channel as the tx_pll_fast_clk_physical_mapping is defined on logic tx channel
// The cram from dprio is on logic tx channel but refers to physical PLL
assign rtx_cmu_sel_int_logic[0] = (tx0_phy == 0) ? rtx_cmu_sel_int[0] :
                                  (tx0_phy == 1) ? rtx_cmu_sel_int[1] :
                                  (tx0_phy == 2) ? rtx_cmu_sel_int[2] : rtx_cmu_sel_int[3];
// physcial PLL to logic PLL map still on logic tx channel                                  
assign tx_refclk_select_out[0] = (rtx_cmu_sel_int_logic[0] === 1'b0) ?                   // tx0 uses physical pll0
                                ((tx0_pll_fast_clk0_physical_mapping == "pll0") ? 1'b0 :    // logic pll0 placed at phy pll0 
                                 (tx0_pll_fast_clk1_physical_mapping == "pll0") ? 1'b1 :    // logic pll1 placed at phy pll0                                
                                                                                  1'bx)     // must be map error
                               :                                                         //  tx0 uses physical pll1
                                ((tx0_pll_fast_clk0_physical_mapping == "pll1") ? 1'b0 :    // logic pll0 places at phy pll1
                                 (tx0_pll_fast_clk1_physical_mapping == "pll1") ? 1'b1 :    // logic pll1 placed at phy pll1                                
                                                                                  1'bx);    // must be map error

// has to send out at phy_ch as last phy_ch to logic map for everyone
assign tx_refclk_select_out_phy[0] = (tx0_phy == 0) ? tx_refclk_select_out[0] :
                                     (tx1_phy == 0) ? tx_refclk_select_out[1] :
                                     (tx2_phy == 0) ? tx_refclk_select_out[2] : tx_refclk_select_out[3];
assign txdprioout_phy_ch0[`rtx_cmu_sel_DP_TX_IDX]         = tx_refclk_select_out_phy[0];   

// channel1
assign rtx_cmu_sel_int_logic[1] = (tx1_phy == 0) ? rtx_cmu_sel_int[0] :
                                  (tx1_phy == 1) ? rtx_cmu_sel_int[1] :
                                  (tx1_phy == 2) ? rtx_cmu_sel_int[2] : rtx_cmu_sel_int[3];
assign tx_refclk_select_out[1] = (rtx_cmu_sel_int_logic[1] === 1'b0) ?                   // tx1 uses physical pll0
                                ((tx1_pll_fast_clk0_physical_mapping == "pll0") ? 1'b0 :    // logic pll0 placed at phy pll0
                                 (tx1_pll_fast_clk1_physical_mapping == "pll0") ? 1'b1 :    // logic pll1 placed at phy pll0                                
                                                                                  1'bx)     // must be map error
                               :                                                         //  tx1 uses physical pll1
                                ((tx1_pll_fast_clk0_physical_mapping == "pll1") ? 1'b0 :    // logic pll0 places at phy pll1
                                 (tx1_pll_fast_clk1_physical_mapping == "pll1") ? 1'b1 :    // logic pll1 placed at phy pll1                                
                                                                                  1'bx);    // must be map error
// has to send out at phy_ch as last phy_ch to logic map for everyone
assign tx_refclk_select_out_phy[1] = (tx0_phy == 1) ? tx_refclk_select_out[0] :
                                     (tx1_phy == 1) ? tx_refclk_select_out[1] :
                                     (tx2_phy == 1) ? tx_refclk_select_out[2] : tx_refclk_select_out[3];
assign txdprioout_phy_ch1[`rtx_cmu_sel_DP_TX_IDX]         = tx_refclk_select_out_phy[1];   

// channel2
assign rtx_cmu_sel_int_logic[2] = (tx2_phy == 0) ? rtx_cmu_sel_int[0] :
                                  (tx2_phy == 1) ? rtx_cmu_sel_int[1] :
                                  (tx2_phy == 2) ? rtx_cmu_sel_int[2] : rtx_cmu_sel_int[3];
assign tx_refclk_select_out[2] = (rtx_cmu_sel_int_logic[2] === 1'b0) ?                   // tx2 uses physical pll0
                                ((tx2_pll_fast_clk0_physical_mapping == "pll0") ? 1'b0 :    // logic pll0 placed at phy pll0
                                 (tx2_pll_fast_clk1_physical_mapping == "pll0") ? 1'b1 :    // logic pll1 placed at phy pll0                                
                                                                                  1'bx)     // must be map error
                               :                                                         //  tx2 uses physical pll1
                                ((tx2_pll_fast_clk0_physical_mapping == "pll1") ? 1'b0 :    // logic pll0 places at phy pll1
                                 (tx2_pll_fast_clk1_physical_mapping == "pll1") ? 1'b1 :    // logic pll1 placed at phy pll1                                
                                                                                  1'bx);    // must be map error
// has to send out at phy_ch as last phy_ch to logic map for everyone
assign tx_refclk_select_out_phy[2] = (tx0_phy == 2) ? tx_refclk_select_out[0] :
                                     (tx1_phy == 2) ? tx_refclk_select_out[1] :
                                     (tx2_phy == 2) ? tx_refclk_select_out[2] : tx_refclk_select_out[3];
assign txdprioout_phy_ch2[`rtx_cmu_sel_DP_TX_IDX]         = tx_refclk_select_out_phy[2];   

// channel3
assign rtx_cmu_sel_int_logic[3] = (tx3_phy == 0) ? rtx_cmu_sel_int[0] :
                                  (tx3_phy == 1) ? rtx_cmu_sel_int[1] :
                                  (tx3_phy == 2) ? rtx_cmu_sel_int[2] : rtx_cmu_sel_int[3];
assign tx_refclk_select_out[3] = (rtx_cmu_sel_int_logic[3] === 1'b0) ?                   // tx3 uses physical pll0
                                ((tx3_pll_fast_clk0_physical_mapping == "pll0") ? 1'b0 :    // logic pll0 placed at phy pll0
                                 (tx3_pll_fast_clk1_physical_mapping == "pll0") ? 1'b1 :    // logic pll1 placed at phy pll0                                
                                                                                  1'bx)     // must be map error
                               :                                                         //  tx3 uses physical pll1
                                ((tx3_pll_fast_clk0_physical_mapping == "pll1") ? 1'b0 :    // logic pll0 places at phy pll1
                                 (tx3_pll_fast_clk1_physical_mapping == "pll1") ? 1'b1 :    // logic pll1 placed at phy pll1                                
                                                                                  1'bx);    // must be map error
// has to send out at phy_ch as last phy_ch to logic map for everyone
assign tx_refclk_select_out_phy[3] = (tx0_phy == 3) ? tx_refclk_select_out[0] :
                                     (tx1_phy == 3) ? tx_refclk_select_out[1] :
                                     (tx2_phy == 3) ? tx_refclk_select_out[2] : tx_refclk_select_out[3];
assign txdprioout_phy_ch3[`rtx_cmu_sel_DP_TX_IDX]         = tx_refclk_select_out_phy[3];   
                              
// TX PMA CRAM - input (parameter) ----------------------------------------------------

// pma_ctrl1: 4.8060-4.8063 (tx)
assign rtx_vod_sel_ch0  = txdprioin_phy_ch0[`rtx_vod_sel_DP_TX_IDX_2 : `rtx_vod_sel_DP_TX_IDX_0];  // 3-bits
assign rtx_slewrate[0]  = txdprioin_phy_ch0[`rtx_slewrate_DP_TX_IDX];                              // 1-bit
assign rpmphs_2tap_ch0  = txdprioin_phy_ch0[`rpmphs_2tap_DP_TX_IDX_2 : `rpmphs_2tap_DP_TX_IDX_0];  // 3
assign rpmphs_1tap_ch0  = txdprioin_phy_ch0[`rpmphs_1tap_DP_TX_IDX_3 : `rpmphs_1tap_DP_TX_IDX_0];  // 4 
assign rtx_vtt_ch0      = txdprioin_phy_ch0[`rtx_vtt_DP_TX_IDX_1 : `rtx_vtt_DP_TX_IDX_0];          // 2 - to add in wys
assign rpmphs_ptap_ch0  = txdprioin_phy_ch0[`rpmphs_ptap_DP_TX_IDX_2 : `rpmphs_ptap_DP_TX_IDX_0];  // 3

assign rtx_vod_sel_ch1  = txdprioin_phy_ch1[`rtx_vod_sel_DP_TX_IDX_2 : `rtx_vod_sel_DP_TX_IDX_0];  // 3-bits
assign rtx_slewrate[1]  = txdprioin_phy_ch1[`rtx_slewrate_DP_TX_IDX];                              // 1-bit
assign rpmphs_2tap_ch1  = txdprioin_phy_ch1[`rpmphs_2tap_DP_TX_IDX_2 : `rpmphs_2tap_DP_TX_IDX_0];  // 3
assign rpmphs_1tap_ch1  = txdprioin_phy_ch1[`rpmphs_1tap_DP_TX_IDX_3 : `rpmphs_1tap_DP_TX_IDX_0];  // 4 
assign rtx_vtt_ch1      = txdprioin_phy_ch1[`rtx_vtt_DP_TX_IDX_1 : `rtx_vtt_DP_TX_IDX_0];          // 2 - to add in wys
assign rpmphs_ptap_ch1  = txdprioin_phy_ch1[`rpmphs_ptap_DP_TX_IDX_2 : `rpmphs_ptap_DP_TX_IDX_0];  // 3

assign rtx_vod_sel_ch2  = txdprioin_phy_ch2[`rtx_vod_sel_DP_TX_IDX_2 : `rtx_vod_sel_DP_TX_IDX_0];  // 3-bits
assign rtx_slewrate[2]  = txdprioin_phy_ch2[`rtx_slewrate_DP_TX_IDX];                              // 1-bit
assign rpmphs_2tap_ch2  = txdprioin_phy_ch2[`rpmphs_2tap_DP_TX_IDX_2 : `rpmphs_2tap_DP_TX_IDX_0];  // 3
assign rpmphs_1tap_ch2  = txdprioin_phy_ch2[`rpmphs_1tap_DP_TX_IDX_3 : `rpmphs_1tap_DP_TX_IDX_0];  // 4 
assign rtx_vtt_ch2      = txdprioin_phy_ch2[`rtx_vtt_DP_TX_IDX_1 : `rtx_vtt_DP_TX_IDX_0];          // 2 - to add in wys
assign rpmphs_ptap_ch2  = txdprioin_phy_ch2[`rpmphs_ptap_DP_TX_IDX_2 : `rpmphs_ptap_DP_TX_IDX_0];  // 3

assign rtx_vod_sel_ch3  = txdprioin_phy_ch3[`rtx_vod_sel_DP_TX_IDX_2 : `rtx_vod_sel_DP_TX_IDX_0];  // 3-bits
assign rtx_slewrate[3]  = txdprioin_phy_ch3[`rtx_slewrate_DP_TX_IDX];                              // 1-bit
assign rpmphs_2tap_ch3  = txdprioin_phy_ch3[`rpmphs_2tap_DP_TX_IDX_2 : `rpmphs_2tap_DP_TX_IDX_0];  // 3
assign rpmphs_1tap_ch3  = txdprioin_phy_ch3[`rpmphs_1tap_DP_TX_IDX_3 : `rpmphs_1tap_DP_TX_IDX_0];  // 4 
assign rtx_vtt_ch3      = txdprioin_phy_ch3[`rtx_vtt_DP_TX_IDX_1 : `rtx_vtt_DP_TX_IDX_0];          // 2 - to add in wys
assign rpmphs_ptap_ch3  = txdprioin_phy_ch3[`rpmphs_ptap_DP_TX_IDX_2 : `rpmphs_ptap_DP_TX_IDX_0];  // 3

// pma_ctrl8: 4.807c-807h - TX portion
//assign  pma_ctrl8_ch0_ext = {rs_lpbk[0], r_rlpbk[0], rs_rdlpbk[0], rrx_revlb_sw[0],
//                             rurx_pdb[0], rtx_cgb_pdb[0], rtx_ob_pdb[0], rrx_cru_pdb[0],
//                             rrx_cru_rst[0], rrx_ib_pdb[0], rrxurstpma[0], radce_adapt[0],
//                             radce_pdb[0], radce_rst[0], rsig_inv_2tap[0], rsig_inv_pre[0]};
assign r_rlpbk[0]       = txdprioin_phy_ch0[`r_rlpbk_DP_TX_IDX];             // 14 - tx
assign rs_rdlpbk[0]     = txdprioin_phy_ch0[`rs_rdlpbk_DP_TX_IDX];           // 13 - tx
assign rsig_inv_2tap[0] = txdprioin_phy_ch0[`rsig_inv_2tap_DP_TX_IDX];       // 1 
assign rsig_inv_pre[0]  = txdprioin_phy_ch0[`rsig_inv_pre_DP_TX_IDX];        // 1

assign r_rlpbk[1]       = txdprioin_phy_ch1[`r_rlpbk_DP_TX_IDX];             // 14 - tx
assign rs_rdlpbk[1]     = txdprioin_phy_ch1[`rs_rdlpbk_DP_TX_IDX];           // 13 - tx
assign rsig_inv_2tap[1] = txdprioin_phy_ch1[`rsig_inv_2tap_DP_TX_IDX];       // 1 
assign rsig_inv_pre[1]  = txdprioin_phy_ch1[`rsig_inv_pre_DP_TX_IDX];        // 1

assign r_rlpbk[2]       = txdprioin_phy_ch2[`r_rlpbk_DP_TX_IDX];             // 14 - tx
assign rs_rdlpbk[2]     = txdprioin_phy_ch2[`rs_rdlpbk_DP_TX_IDX];           // 13 - tx
assign rsig_inv_2tap[2] = txdprioin_phy_ch2[`rsig_inv_2tap_DP_TX_IDX];       // 1 
assign rsig_inv_pre[2]  = txdprioin_phy_ch2[`rsig_inv_pre_DP_TX_IDX];        // 1

assign r_rlpbk[3]       = txdprioin_phy_ch3[`r_rlpbk_DP_TX_IDX];             // 14 - tx
assign rs_rdlpbk[3]     = txdprioin_phy_ch3[`rs_rdlpbk_DP_TX_IDX];           // 13 - tx
assign rsig_inv_2tap[3] = txdprioin_phy_ch3[`rsig_inv_2tap_DP_TX_IDX];       // 1 
assign rsig_inv_pre[3]  = txdprioin_phy_ch3[`rsig_inv_pre_DP_TX_IDX];        // 1


// The address covers both rx(pma and dpma widths defined in RX) and tx
// pma_ctrl4_ch0_ext = {rpmadwidth_tx[0], rpma_doublewidth_tx[0], rtx_cmu_sel[0],
// 806Ch                rtx_m_sel_ch0, rtxvcobypass[0], rtx_cgb_1x_en[0], rtx_cgb_4x_en[0],
//                      rtx_4x_sw[0], rpmadwidth_rx[0], rpma_doublewidth_rx[0],
//                      rrxvcobypass[0],rrect_adj_ch0, rrx_piso_bypass_ch0};
assign rpmadwidth_tx[0]       = txdprioin_phy_ch0[`rpmadwidth_tx_DP_TX_IDX];                       // 1 
assign rpma_doublewidth_tx[0] = txdprioin_phy_ch0[`rpma_doublewidth_tx_DP_TX_IDX];                 // 1 
//assign rtx_cmu_sel[0]         = txdprioin_phy_ch0[`rtx_cmu_sel_DP_TX_IDX];                         // 1 
assign rtx_m_sel_ch0          = txdprioin_phy_ch0[`rtx_m_sel_DP_TX_IDX_1 : `rtx_m_sel_DP_TX_IDX_0]; // 2 
assign rtx_cgb_1x_en[0]       = txdprioin_phy_ch0[`rtx_cgb_1x_en_DP_TX_IDX];                       // 1 
assign rtx_cgb_4x_en[0]       = txdprioin_phy_ch0[`rtx_cgb_4x_en_DP_TX_IDX];                       // 1 
assign rtx_4x_sw[0]           = txdprioin_phy_ch0[`rtx_4x_sw_DP_TX_IDX];                           // 1 

assign rpmadwidth_tx[1]       = txdprioin_phy_ch1[`rpmadwidth_tx_DP_TX_IDX];                       // 1 
assign rpma_doublewidth_tx[1] = txdprioin_phy_ch1[`rpma_doublewidth_tx_DP_TX_IDX];                 // 1 
//assign rtx_cmu_sel[1]         = txdprioin_phy_ch1[`rtx_cmu_sel_DP_TX_IDX];                         // 1 
assign rtx_m_sel_ch1          = txdprioin_phy_ch1[`rtx_m_sel_DP_TX_IDX_1 : `rtx_m_sel_DP_TX_IDX_0]; // 2 
assign rtx_cgb_1x_en[1]       = txdprioin_phy_ch1[`rtx_cgb_1x_en_DP_TX_IDX];                       // 1 
assign rtx_cgb_4x_en[1]       = txdprioin_phy_ch1[`rtx_cgb_4x_en_DP_TX_IDX];                       // 1 
assign rtx_4x_sw[1]           = txdprioin_phy_ch1[`rtx_4x_sw_DP_TX_IDX];                           // 1 

assign rpmadwidth_tx[2]       = txdprioin_phy_ch2[`rpmadwidth_tx_DP_TX_IDX];                       // 1 
assign rpma_doublewidth_tx[2] = txdprioin_phy_ch2[`rpma_doublewidth_tx_DP_TX_IDX];                 // 1 
//assign rtx_cmu_sel[2]         = txdprioin_phy_ch2[`rtx_cmu_sel_DP_TX_IDX];                         // 1 
assign rtx_m_sel_ch2          = txdprioin_phy_ch2[`rtx_m_sel_DP_TX_IDX_1 : `rtx_m_sel_DP_TX_IDX_0]; // 2 
assign rtx_cgb_1x_en[2]       = txdprioin_phy_ch2[`rtx_cgb_1x_en_DP_TX_IDX];                       // 1 
assign rtx_cgb_4x_en[2]       = txdprioin_phy_ch2[`rtx_cgb_4x_en_DP_TX_IDX];                       // 1 
assign rtx_4x_sw[2]           = txdprioin_phy_ch2[`rtx_4x_sw_DP_TX_IDX];                           // 1 

assign rpmadwidth_tx[3]       = txdprioin_phy_ch3[`rpmadwidth_tx_DP_TX_IDX];                       // 1 
assign rpma_doublewidth_tx[3] = txdprioin_phy_ch3[`rpma_doublewidth_tx_DP_TX_IDX];                 // 1 
//assign rtx_cmu_sel[3]         = txdprioin_phy_ch3[`rtx_cmu_sel_DP_TX_IDX];                         // 1 
assign rtx_m_sel_ch3          = txdprioin_phy_ch3[`rtx_m_sel_DP_TX_IDX_1 : `rtx_m_sel_DP_TX_IDX_0]; // 2 
assign rtx_cgb_1x_en[3]       = txdprioin_phy_ch3[`rtx_cgb_1x_en_DP_TX_IDX];                       // 1 
assign rtx_cgb_4x_en[3]       = txdprioin_phy_ch3[`rtx_cgb_4x_en_DP_TX_IDX];                       // 1 
assign rtx_4x_sw[3]           = txdprioin_phy_ch3[`rtx_4x_sw_DP_TX_IDX];                           // 1 

// txpma_ctrl_input_to_add  


// TX PMA - output -----------------------------------------------------------------------------

// pma_ctrl1: 4.8060-4.8063 (tx)
assign txdprioout_phy_ch0[`rtx_vod_sel_DP_TX_IDX_2 : `rtx_vod_sel_DP_TX_IDX_0] = rtx_vod_sel_ch0_int;    // 3-bits - qpmaused
assign txdprioout_phy_ch0[`rtx_slewrate_DP_TX_IDX]                             = rtx_slewrate_int[0];   // 1-bit
assign txdprioout_phy_ch0[`rpmphs_2tap_DP_TX_IDX_2 : `rpmphs_2tap_DP_TX_IDX_0] = rpmphs_2tap_ch0_int;    // 3  - qpmaused
assign txdprioout_phy_ch0[`rpmphs_1tap_DP_TX_IDX_3 : `rpmphs_1tap_DP_TX_IDX_0] = rpmphs_1tap_ch0_int;    // 4  - qpmaused
assign txdprioout_phy_ch0[`rtx_vtt_DP_TX_IDX_1     : `rtx_vtt_DP_TX_IDX_0]     = rtx_vtt_ch0_int;        // 2 - to add in wys
assign txdprioout_phy_ch0[`rpmphs_ptap_DP_TX_IDX_2 : `rpmphs_ptap_DP_TX_IDX_0] = rpmphs_ptap_ch0_int;    // 3 - qpmaused

assign txdprioout_phy_ch1[`rtx_vod_sel_DP_TX_IDX_2 : `rtx_vod_sel_DP_TX_IDX_0] = rtx_vod_sel_ch1_int;    // 3-bits - qpmaused
assign txdprioout_phy_ch1[`rtx_slewrate_DP_TX_IDX]                             = rtx_slewrate_int[1];   // 1-bit
assign txdprioout_phy_ch1[`rpmphs_2tap_DP_TX_IDX_2 : `rpmphs_2tap_DP_TX_IDX_0] = rpmphs_2tap_ch1_int;    // 3  - qpmaused
assign txdprioout_phy_ch1[`rpmphs_1tap_DP_TX_IDX_3 : `rpmphs_1tap_DP_TX_IDX_0] = rpmphs_1tap_ch1_int;    // 4  - qpmaused
assign txdprioout_phy_ch1[`rtx_vtt_DP_TX_IDX_1     : `rtx_vtt_DP_TX_IDX_0]     = rtx_vtt_ch1_int;        // 2 - to add in wys
assign txdprioout_phy_ch1[`rpmphs_ptap_DP_TX_IDX_2 : `rpmphs_ptap_DP_TX_IDX_0] = rpmphs_ptap_ch1_int;    // 3 - qpmaused

assign txdprioout_phy_ch2[`rtx_vod_sel_DP_TX_IDX_2 : `rtx_vod_sel_DP_TX_IDX_0] = rtx_vod_sel_ch2_int;    // 3-bits - qpmaused
assign txdprioout_phy_ch2[`rtx_slewrate_DP_TX_IDX]                             = rtx_slewrate_int[2];   // 1-bit
assign txdprioout_phy_ch2[`rpmphs_2tap_DP_TX_IDX_2 : `rpmphs_2tap_DP_TX_IDX_0] = rpmphs_2tap_ch2_int;    // 3  - qpmaused
assign txdprioout_phy_ch2[`rpmphs_1tap_DP_TX_IDX_3 : `rpmphs_1tap_DP_TX_IDX_0] = rpmphs_1tap_ch2_int;    // 4  - qpmaused
assign txdprioout_phy_ch2[`rtx_vtt_DP_TX_IDX_1     : `rtx_vtt_DP_TX_IDX_0]     = rtx_vtt_ch2_int;        // 2 - to add in wys
assign txdprioout_phy_ch2[`rpmphs_ptap_DP_TX_IDX_2 : `rpmphs_ptap_DP_TX_IDX_0] = rpmphs_ptap_ch2_int;    // 3 - qpmaused

assign txdprioout_phy_ch3[`rtx_vod_sel_DP_TX_IDX_2 : `rtx_vod_sel_DP_TX_IDX_0] = rtx_vod_sel_ch3_int;    // 3-bits - qpmaused
assign txdprioout_phy_ch3[`rtx_slewrate_DP_TX_IDX]                             = rtx_slewrate_int[3];   // 1-bit
assign txdprioout_phy_ch3[`rpmphs_2tap_DP_TX_IDX_2 : `rpmphs_2tap_DP_TX_IDX_0] = rpmphs_2tap_ch3_int;    // 3  - qpmaused
assign txdprioout_phy_ch3[`rpmphs_1tap_DP_TX_IDX_3 : `rpmphs_1tap_DP_TX_IDX_0] = rpmphs_1tap_ch3_int;    // 4  - qpmaused
assign txdprioout_phy_ch3[`rtx_vtt_DP_TX_IDX_1     : `rtx_vtt_DP_TX_IDX_0]     = rtx_vtt_ch3_int;        // 2 - to add in wys
assign txdprioout_phy_ch3[`rpmphs_ptap_DP_TX_IDX_2 : `rpmphs_ptap_DP_TX_IDX_0] = rpmphs_ptap_ch3_int;    // 3 - qpmaused


// pma_ctrl8: 4.807c-807h - skipping other 14 bits (some are RX)
assign txdprioout_phy_ch0[`r_rlpbk_DP_TX_IDX]       = r_rlpbk_int[0];  // 1 
assign txdprioout_phy_ch0[`rs_rdlpbk_DP_TX_IDX]     = rs_rdlpbk_int[0];   // 1
assign txdprioout_phy_ch0[`rsig_inv_2tap_DP_TX_IDX] = rsig_inv_2tap_int[0];  // 1 
assign txdprioout_phy_ch0[`rsig_inv_pre_DP_TX_IDX]  = rsig_inv_pre_int[0];   // 1

assign txdprioout_phy_ch1[`r_rlpbk_DP_TX_IDX]       = r_rlpbk_int[1];  // 1 
assign txdprioout_phy_ch1[`rs_rdlpbk_DP_TX_IDX]     = rs_rdlpbk_int[1];   // 1
assign txdprioout_phy_ch1[`rsig_inv_2tap_DP_TX_IDX] = rsig_inv_2tap_int[1];  // 1 
assign txdprioout_phy_ch1[`rsig_inv_pre_DP_TX_IDX]  = rsig_inv_pre_int[1];   // 1

assign txdprioout_phy_ch2[`r_rlpbk_DP_TX_IDX]       = r_rlpbk_int[2];  // 1 
assign txdprioout_phy_ch2[`rs_rdlpbk_DP_TX_IDX]     = rs_rdlpbk_int[2];   // 1
assign txdprioout_phy_ch2[`rsig_inv_2tap_DP_TX_IDX] = rsig_inv_2tap_int[2];  // 1 
assign txdprioout_phy_ch2[`rsig_inv_pre_DP_TX_IDX]  = rsig_inv_pre_int[2];   // 1

assign txdprioout_phy_ch3[`r_rlpbk_DP_TX_IDX]       = r_rlpbk_int[3];  // 1 
assign txdprioout_phy_ch3[`rs_rdlpbk_DP_TX_IDX]     = rs_rdlpbk_int[3];   // 1
assign txdprioout_phy_ch3[`rsig_inv_2tap_DP_TX_IDX] = rsig_inv_2tap_int[3];  // 1 
assign txdprioout_phy_ch3[`rsig_inv_pre_DP_TX_IDX]  = rsig_inv_pre_int[3];   // 1


// The address covers both rx(pma and dpma widths defined in RX) and tx
// pma_ctrl4_ch0_ext = {rpmadwidth_tx[0], rpma_doublewidth_tx[0], rtx_cmu_sel[0],
// 806Ch                rtx_m_sel_ch0, rtxvcobypass[0], rtx_cgb_1x_en[0], rtx_cgb_4x_en[0],
//                      rtx_4x_sw[0], rpmadwidth_rx[0], rpma_doublewidth_rx[0],
//                      rrxvcobypass[0],rrect_adj_ch0, rrx_piso_bypass_ch0};
assign txdprioout_phy_ch0[`rpmadwidth_tx_DP_TX_IDX]       = rpmadwidth_tx_int[0];          // 1 
assign txdprioout_phy_ch0[`rpma_doublewidth_tx_DP_TX_IDX] = rpma_doublewidth_tx_int[0];    // 1 
//assign txdprioout_phy_ch0[`rtx_cmu_sel_DP_TX_IDX]         = rtx_cmu_sel_int[0];            // 1 
assign txdprioout_phy_ch0[`rtx_m_sel_DP_TX_IDX_1 : `rtx_m_sel_DP_TX_IDX_0] = rtx_m_sel_ch0_int; // 2 
assign txdprioout_phy_ch0[`rtx_cgb_1x_en_DP_TX_IDX]       = rtx_cgb_1x_en_int[0];          // 1 
assign txdprioout_phy_ch0[`rtx_cgb_4x_en_DP_TX_IDX]       = rtx_cgb_4x_en_int[0];          // 1 
assign txdprioout_phy_ch0[`rtx_4x_sw_DP_TX_IDX]           = rtx_4x_sw_int[0];              // 1 

assign txdprioout_phy_ch1[`rpmadwidth_tx_DP_TX_IDX]       = rpmadwidth_tx_int[1];          // 1 
assign txdprioout_phy_ch1[`rpma_doublewidth_tx_DP_TX_IDX] = rpma_doublewidth_tx_int[1];    // 1 
//assign txdprioout_phy_ch1[`rtx_cmu_sel_DP_TX_IDX]         = rtx_cmu_sel_int[1];            // 1 
assign txdprioout_phy_ch1[`rtx_m_sel_DP_TX_IDX_1 : `rtx_m_sel_DP_TX_IDX_0] = rtx_m_sel_ch1_int; // 2 
assign txdprioout_phy_ch1[`rtx_cgb_1x_en_DP_TX_IDX]       = rtx_cgb_1x_en_int[1];          // 1 
assign txdprioout_phy_ch1[`rtx_cgb_4x_en_DP_TX_IDX]       = rtx_cgb_4x_en_int[1];          // 1 
assign txdprioout_phy_ch1[`rtx_4x_sw_DP_TX_IDX]           = rtx_4x_sw_int[1];              // 1 

assign txdprioout_phy_ch2[`rpmadwidth_tx_DP_TX_IDX]       = rpmadwidth_tx_int[2];          // 1 
assign txdprioout_phy_ch2[`rpma_doublewidth_tx_DP_TX_IDX] = rpma_doublewidth_tx_int[2];    // 1 
//assign txdprioout_phy_ch2[`rtx_cmu_sel_DP_TX_IDX]         = rtx_cmu_sel_int[2];            // 1 
assign txdprioout_phy_ch2[`rtx_m_sel_DP_TX_IDX_1 : `rtx_m_sel_DP_TX_IDX_0] = rtx_m_sel_ch2_int; // 2 
assign txdprioout_phy_ch2[`rtx_cgb_1x_en_DP_TX_IDX]       = rtx_cgb_1x_en_int[2];          // 1 
assign txdprioout_phy_ch2[`rtx_cgb_4x_en_DP_TX_IDX]       = rtx_cgb_4x_en_int[2];          // 1 
assign txdprioout_phy_ch2[`rtx_4x_sw_DP_TX_IDX]           = rtx_4x_sw_int[2];              // 1 

assign txdprioout_phy_ch3[`rpmadwidth_tx_DP_TX_IDX]       = rpmadwidth_tx_int[3];          // 1 
assign txdprioout_phy_ch3[`rpma_doublewidth_tx_DP_TX_IDX] = rpma_doublewidth_tx_int[3];    // 1 
//assign txdprioout_phy_ch3[`rtx_cmu_sel_DP_TX_IDX]         = rtx_cmu_sel_int[3];            // 1 
assign txdprioout_phy_ch3[`rtx_m_sel_DP_TX_IDX_1 : `rtx_m_sel_DP_TX_IDX_0] = rtx_m_sel_ch3_int; // 2 
assign txdprioout_phy_ch3[`rtx_cgb_1x_en_DP_TX_IDX]       = rtx_cgb_1x_en_int[3];          // 1 
assign txdprioout_phy_ch3[`rtx_cgb_4x_en_DP_TX_IDX]       = rtx_cgb_4x_en_int[3];          // 1 
assign txdprioout_phy_ch3[`rtx_4x_sw_DP_TX_IDX]           = rtx_4x_sw_int[3];              // 1 

// txpma_ctrl_output_to_add  - make sure _int is used


// RX PMA - input-----------------------------------------------------------------------------

// pma_ctrl2: 4.8064-4.8067 (rx)
assign rtx_term_ch0     = rxdprioin_phy_ch0[`rtx_term_DP_RX_IDX_1    : `rtx_term_DP_RX_IDX_0];      // 2-bits
assign r_tx_det_rx_ch0  = rxdprioin_phy_ch0[`r_tx_det_rx_DP_RX_IDX_1 : `r_tx_det_rx_DP_RX_IDX_0];   // 2-bit
assign rrx_term_ch0     = rxdprioin_phy_ch0[`rrx_term_DP_RX_IDX_1    : `rrx_term_DP_RX_IDX_0];      // 2
assign rforce_sigdet[0] = rxdprioin_phy_ch0[`rforce_sigdet_DP_RX_IDX];                      // 1 
assign rrx_dc_couple[0] = rxdprioin_phy_ch0[`rrx_dc_couple_DP_RX_IDX];                      // 1
assign rrx_eq_dc_ch0    = rxdprioin_phy_ch0[`rrx_eq_dc_DP_RX_IDX_1   : `rrx_eq_dc_DP_RX_IDX_0];     // 2 - qpmaused
assign rrx_vtt_ch0      = rxdprioin_phy_ch0[`rrx_vtt_DP_RX_IDX_2     : `rrx_vtt_DP_RX_IDX_0];       // 3
assign rrx_sloslv_ch0   = rxdprioin_phy_ch0[`rrx_sloslv_DP_RX_IDX_2  : `rrx_sloslv_DP_RX_IDX_0];    // 3

assign rtx_term_ch1     = rxdprioin_phy_ch1[`rtx_term_DP_RX_IDX_1    : `rtx_term_DP_RX_IDX_0];      // 2-bits
assign r_tx_det_rx_ch1  = rxdprioin_phy_ch1[`r_tx_det_rx_DP_RX_IDX_1 : `r_tx_det_rx_DP_RX_IDX_0];   // 2-bit
assign rrx_term_ch1     = rxdprioin_phy_ch1[`rrx_term_DP_RX_IDX_1    : `rrx_term_DP_RX_IDX_0];      // 2
assign rforce_sigdet[1] = rxdprioin_phy_ch1[`rforce_sigdet_DP_RX_IDX];                      // 1 
assign rrx_dc_couple[1] = rxdprioin_phy_ch1[`rrx_dc_couple_DP_RX_IDX];                      // 1
assign rrx_eq_dc_ch1    = rxdprioin_phy_ch1[`rrx_eq_dc_DP_RX_IDX_1   : `rrx_eq_dc_DP_RX_IDX_0];     // 2 - qpmaused
assign rrx_vtt_ch1      = rxdprioin_phy_ch1[`rrx_vtt_DP_RX_IDX_2     : `rrx_vtt_DP_RX_IDX_0];       // 3
assign rrx_sloslv_ch1   = rxdprioin_phy_ch1[`rrx_sloslv_DP_RX_IDX_2  : `rrx_sloslv_DP_RX_IDX_0];    // 3

assign rtx_term_ch2     = rxdprioin_phy_ch2[`rtx_term_DP_RX_IDX_1    : `rtx_term_DP_RX_IDX_0];      // 2-bits
assign r_tx_det_rx_ch2  = rxdprioin_phy_ch2[`r_tx_det_rx_DP_RX_IDX_1 : `r_tx_det_rx_DP_RX_IDX_0];   // 2-bit
assign rrx_term_ch2     = rxdprioin_phy_ch2[`rrx_term_DP_RX_IDX_1    : `rrx_term_DP_RX_IDX_0];      // 2
assign rforce_sigdet[2] = rxdprioin_phy_ch2[`rforce_sigdet_DP_RX_IDX];                      // 1 
assign rrx_dc_couple[2] = rxdprioin_phy_ch2[`rrx_dc_couple_DP_RX_IDX];                      // 1
assign rrx_eq_dc_ch2    = rxdprioin_phy_ch2[`rrx_eq_dc_DP_RX_IDX_1   : `rrx_eq_dc_DP_RX_IDX_0];     // 2 - qpmaused
assign rrx_vtt_ch2      = rxdprioin_phy_ch2[`rrx_vtt_DP_RX_IDX_2     : `rrx_vtt_DP_RX_IDX_0];       // 3
assign rrx_sloslv_ch2   = rxdprioin_phy_ch2[`rrx_sloslv_DP_RX_IDX_2  : `rrx_sloslv_DP_RX_IDX_0];    // 3

assign rtx_term_ch3     = rxdprioin_phy_ch3[`rtx_term_DP_RX_IDX_1    : `rtx_term_DP_RX_IDX_0];      // 2-bits
assign r_tx_det_rx_ch3  = rxdprioin_phy_ch3[`r_tx_det_rx_DP_RX_IDX_1 : `r_tx_det_rx_DP_RX_IDX_0];   // 2-bit
assign rrx_term_ch3     = rxdprioin_phy_ch3[`rrx_term_DP_RX_IDX_1    : `rrx_term_DP_RX_IDX_0];      // 2
assign rforce_sigdet[3] = rxdprioin_phy_ch3[`rforce_sigdet_DP_RX_IDX];                      // 1 
assign rrx_dc_couple[3] = rxdprioin_phy_ch3[`rrx_dc_couple_DP_RX_IDX];                      // 1
assign rrx_eq_dc_ch3    = rxdprioin_phy_ch3[`rrx_eq_dc_DP_RX_IDX_1   : `rrx_eq_dc_DP_RX_IDX_0];     // 2 - qpmaused
assign rrx_vtt_ch3      = rxdprioin_phy_ch3[`rrx_vtt_DP_RX_IDX_2     : `rrx_vtt_DP_RX_IDX_0];       // 3
assign rrx_sloslv_ch3   = rxdprioin_phy_ch3[`rrx_sloslv_DP_RX_IDX_2  : `rrx_sloslv_DP_RX_IDX_0];    // 3


// pma_ctrl3: 4.8068-4.806b (rx)
assign reqa_ct_ch0     = rxdprioin_phy_ch0[`reqa_ct_DP_RX_IDX_2     : `reqa_ct_DP_RX_IDX_0]; // 3-bits  - qpmaused
assign reqb_ct_ch0     = rxdprioin_phy_ch0[`reqb_ct_DP_RX_IDX_2     : `reqb_ct_DP_RX_IDX_0]; // 3-bit - qpmaused
assign reqc_ct_ch0     = rxdprioin_phy_ch0[`reqc_ct_DP_RX_IDX_2     : `reqc_ct_DP_RX_IDX_0];   // 3 - qpmaused
assign reqd_ct_ch0     = rxdprioin_phy_ch0[`reqd_ct_DP_RX_IDX_2     : `reqd_ct_DP_RX_IDX_0];   // 3 - qpmaused 
assign req_ctv_ch0     = rxdprioin_phy_ch0[`req_ctv_DP_RX_IDX_2     : `req_ctv_DP_RX_IDX_0];   // 3 - qpmaused

assign reqa_ct_ch1     = rxdprioin_phy_ch1[`reqa_ct_DP_RX_IDX_2     : `reqa_ct_DP_RX_IDX_0]; // 3-bits  - qpmaused
assign reqb_ct_ch1     = rxdprioin_phy_ch1[`reqb_ct_DP_RX_IDX_2     : `reqb_ct_DP_RX_IDX_0]; // 3-bit - qpmaused
assign reqc_ct_ch1     = rxdprioin_phy_ch1[`reqc_ct_DP_RX_IDX_2     : `reqc_ct_DP_RX_IDX_0];   // 3 - qpmaused
assign reqd_ct_ch1     = rxdprioin_phy_ch1[`reqd_ct_DP_RX_IDX_2     : `reqd_ct_DP_RX_IDX_0];   // 3 - qpmaused 
assign req_ctv_ch1     = rxdprioin_phy_ch1[`req_ctv_DP_RX_IDX_2     : `req_ctv_DP_RX_IDX_0];   // 3 - qpmaused

assign reqa_ct_ch2     = rxdprioin_phy_ch2[`reqa_ct_DP_RX_IDX_2     : `reqa_ct_DP_RX_IDX_0]; // 3-bits  - qpmaused
assign reqb_ct_ch2     = rxdprioin_phy_ch2[`reqb_ct_DP_RX_IDX_2     : `reqb_ct_DP_RX_IDX_0]; // 3-bit - qpmaused
assign reqc_ct_ch2     = rxdprioin_phy_ch2[`reqc_ct_DP_RX_IDX_2     : `reqc_ct_DP_RX_IDX_0];   // 3 - qpmaused
assign reqd_ct_ch2     = rxdprioin_phy_ch2[`reqd_ct_DP_RX_IDX_2     : `reqd_ct_DP_RX_IDX_0];   // 3 - qpmaused 
assign req_ctv_ch2     = rxdprioin_phy_ch2[`req_ctv_DP_RX_IDX_2     : `req_ctv_DP_RX_IDX_0];   // 3 - qpmaused

assign reqa_ct_ch3     = rxdprioin_phy_ch3[`reqa_ct_DP_RX_IDX_2     : `reqa_ct_DP_RX_IDX_0]; // 3-bits  - qpmaused
assign reqb_ct_ch3     = rxdprioin_phy_ch3[`reqb_ct_DP_RX_IDX_2     : `reqb_ct_DP_RX_IDX_0]; // 3-bit - qpmaused
assign reqc_ct_ch3     = rxdprioin_phy_ch3[`reqc_ct_DP_RX_IDX_2     : `reqc_ct_DP_RX_IDX_0];   // 3 - qpmaused
assign reqd_ct_ch3     = rxdprioin_phy_ch3[`reqd_ct_DP_RX_IDX_2     : `reqd_ct_DP_RX_IDX_0];   // 3 - qpmaused 
assign req_ctv_ch3     = rxdprioin_phy_ch3[`req_ctv_DP_RX_IDX_2     : `req_ctv_DP_RX_IDX_0];   // 3 - qpmaused

// part of pma_ctrl4 806Ch
// = {rpmadwidth_tx[0], rpma_doublewidth_tx[0], rtx_cmu_sel[0],
//    rtx_m_sel_ch0, rtxvcobypass[0], rtx_cgb_1x_en[0], rtx_cgb_4x_en[0],
//    rtx_4x_sw[0], rpmadwidth_rx[0], rpma_doublewidth_rx[0],
//    rrxvcobypass[0],rrect_adj_ch0, rrx_piso_bypass_ch0};
assign rpmadwidth_rx[0]        = rxdprioin_phy_ch0[`rpmadwidth_rx_DP_RX_IDX];
assign rpma_doublewidth_rx[0]  = rxdprioin_phy_ch0[`rpma_doublewidth_rx_DP_RX_IDX];
                                                                                                     
assign rpmadwidth_rx[1]        = rxdprioin_phy_ch1[`rpmadwidth_rx_DP_RX_IDX];
assign rpma_doublewidth_rx[1]  = rxdprioin_phy_ch1[`rpma_doublewidth_rx_DP_RX_IDX];

assign rpmadwidth_rx[2]        = rxdprioin_phy_ch2[`rpmadwidth_rx_DP_RX_IDX];
assign rpma_doublewidth_rx[2]  = rxdprioin_phy_ch2[`rpma_doublewidth_rx_DP_RX_IDX];

assign rpmadwidth_rx[3]        = rxdprioin_phy_ch3[`rpmadwidth_rx_DP_RX_IDX];
assign rpma_doublewidth_rx[3]  = rxdprioin_phy_ch3[`rpma_doublewidth_rx_DP_RX_IDX];

// pma_ctrl6_ch0_ext = {rrefclk_sel_ch0, rbwctral_rx_ch0, rrx_cru_m_sel_ch0, 
// 8074h                rrx_cru_div2[0], rrx_cru_ctl_ch0, rltr[0], rltd[0]};
assign rrx_cru_m_sel_ch0 = rxdprioin_phy_ch0[`rrx_cru_m_sel_DP_RX_IDX_1 : `rrx_cru_m_sel_DP_RX_IDX_0]; // 2-bits
assign rrx_cru_div2[0]   = rxdprioin_phy_ch0[`rrx_cru_div2_DP_RX_IDX];                                // 1-bits
assign rltr[0]           = rxdprioin_phy_ch0[`rltr_DP_RX_IDX];                                        // 1-bit
assign rltd[0]           = rxdprioin_phy_ch0[`rltd_DP_RX_IDX];                                        // 1-bit
assign rrx_cru_m_sel_ch1 = rxdprioin_phy_ch1[`rrx_cru_m_sel_DP_RX_IDX_1 : `rrx_cru_m_sel_DP_RX_IDX_0]; // 2-bits
assign rrx_cru_div2[1]   = rxdprioin_phy_ch1[`rrx_cru_div2_DP_RX_IDX];                                // 1-bits
assign rltr[1]           = rxdprioin_phy_ch1[`rltr_DP_RX_IDX];                                        // 1-bit
assign rltd[1]           = rxdprioin_phy_ch1[`rltd_DP_RX_IDX];                                        // 1-bit
assign rrx_cru_m_sel_ch2 = rxdprioin_phy_ch2[`rrx_cru_m_sel_DP_RX_IDX_1 : `rrx_cru_m_sel_DP_RX_IDX_0]; // 2-bits
assign rrx_cru_div2[2]   = rxdprioin_phy_ch2[`rrx_cru_div2_DP_RX_IDX];                                // 1-bits
assign rltr[2]           = rxdprioin_phy_ch2[`rltr_DP_RX_IDX];                                        // 1-bit
assign rltd[2]           = rxdprioin_phy_ch2[`rltd_DP_RX_IDX];                                        // 1-bit
assign rrx_cru_m_sel_ch3 = rxdprioin_phy_ch3[`rrx_cru_m_sel_DP_RX_IDX_1 : `rrx_cru_m_sel_DP_RX_IDX_0]; // 2-bits
assign rrx_cru_div2[3]   = rxdprioin_phy_ch3[`rrx_cru_div2_DP_RX_IDX];                                // 1-bits
assign rltr[3]           = rxdprioin_phy_ch3[`rltr_DP_RX_IDX];                                        // 1-bit
assign rltd[3]           = rxdprioin_phy_ch3[`rltd_DP_RX_IDX];                                        // 1-bit

// pma_ctrl7_ch0_ext = {risel_rx_ch0, riupsel_rx_ch0, ridnsel_rx_ch0,
// 8078h               rtesten_cp_rx[0], rtristate_cp_rx[0], rtestupen_cp_rx[0],
//                     rtestdnen_cp_rx[0], rrx_cru_m_ch0, rrx_cru_l_ch0};
assign rrx_cru_m_ch0     = rxdprioin_phy_ch0[`rrx_cru_m_DP_RX_IDX_3 : `rrx_cru_m_DP_RX_IDX_0];         // 4-bit
assign rrx_cru_l_ch0     = rxdprioin_phy_ch0[`rrx_cru_l_DP_RX_IDX_1 : `rrx_cru_l_DP_RX_IDX_0];         // 2-bit
assign rrx_cru_m_ch1     = rxdprioin_phy_ch1[`rrx_cru_m_DP_RX_IDX_3 : `rrx_cru_m_DP_RX_IDX_0];         // 4-bit
assign rrx_cru_l_ch1     = rxdprioin_phy_ch1[`rrx_cru_l_DP_RX_IDX_1 : `rrx_cru_l_DP_RX_IDX_0];         // 2-bit
assign rrx_cru_m_ch2     = rxdprioin_phy_ch2[`rrx_cru_m_DP_RX_IDX_3 : `rrx_cru_m_DP_RX_IDX_0];         // 4-bit
assign rrx_cru_l_ch2     = rxdprioin_phy_ch2[`rrx_cru_l_DP_RX_IDX_1 : `rrx_cru_l_DP_RX_IDX_0];         // 2-bit
assign rrx_cru_m_ch3     = rxdprioin_phy_ch3[`rrx_cru_m_DP_RX_IDX_3 : `rrx_cru_m_DP_RX_IDX_0];         // 4-bit
assign rrx_cru_l_ch3     = rxdprioin_phy_ch3[`rrx_cru_l_DP_RX_IDX_1 : `rrx_cru_l_DP_RX_IDX_0];         // 2-bit

// pma_ctrl8: 4.807c-807h - RX portion
//assign  pma_ctrl8_ch0_ext = {rs_lpbk[0], r_rlpbk[0], rs_rdlpbk[0], rrx_revlb_sw[0],
//                             rurx_pdb[0], rtx_cgb_pdb[0], rtx_ob_pdb[0], rrx_cru_pdb[0],
//                             rrx_cru_rst[0], rrx_ib_pdb[0], rrxurstpma[0], radce_adapt[0],
//                             radce_pdb[0], radce_rst[0], rsig_inv_2tap[0], rsig_inv_pre[0]};
assign rs_lpbk[0]        = rxdprioin_phy_ch0[`rs_lpbk_DP_RX_IDX]; 
assign rrx_revlb_sw[0]   = rxdprioin_phy_ch0[`rrx_revlb_sw_DP_RX_IDX]; 
assign rs_lpbk[1]        = rxdprioin_phy_ch1[`rs_lpbk_DP_RX_IDX]; 
assign rrx_revlb_sw[1]   = rxdprioin_phy_ch1[`rrx_revlb_sw_DP_RX_IDX]; 
assign rs_lpbk[2]        = rxdprioin_phy_ch2[`rs_lpbk_DP_RX_IDX]; 
assign rrx_revlb_sw[2]   = rxdprioin_phy_ch2[`rrx_revlb_sw_DP_RX_IDX]; 
assign rs_lpbk[3]        = rxdprioin_phy_ch3[`rs_lpbk_DP_RX_IDX]; 
assign rrx_revlb_sw[3]   = rxdprioin_phy_ch3[`rrx_revlb_sw_DP_RX_IDX]; 


//  ============= rxpma_ctrl_input_to_add  ===================



// RX PMA - output -----------------------------------------------------------------------------

// pma_ctrl2: 4.8064-4.8067 (rx)
assign rxdprioout_phy_ch0[`rtx_term_DP_RX_IDX_1    : `rtx_term_DP_RX_IDX_0]    = rtx_term_ch0_int;      // 2-bits
assign rxdprioout_phy_ch0[`r_tx_det_rx_DP_RX_IDX_1 : `r_tx_det_rx_DP_RX_IDX_0] = r_tx_det_rx_ch0_int;   // 2-bit
assign rxdprioout_phy_ch0[`rrx_term_DP_RX_IDX_1    : `rrx_term_DP_RX_IDX_0]    = rrx_term_ch0_int;      // 2
assign rxdprioout_phy_ch0[`rforce_sigdet_DP_RX_IDX]                            = rforce_sigdet_int[0];  // 1 
assign rxdprioout_phy_ch0[`rrx_dc_couple_DP_RX_IDX]                            = rrx_dc_couple_int[0];  // 1
assign rxdprioout_phy_ch0[`rrx_eq_dc_DP_RX_IDX_1   : `rrx_eq_dc_DP_RX_IDX_0]   = rrx_eq_dc_ch0_int;     // 2 - qpmaused
assign rxdprioout_phy_ch0[`rrx_vtt_DP_RX_IDX_2     : `rrx_vtt_DP_RX_IDX_0]     = rrx_vtt_ch0_int;       // 3
assign rxdprioout_phy_ch0[`rrx_sloslv_DP_RX_IDX_2  : `rrx_sloslv_DP_RX_IDX_0]  = rrx_sloslv_ch0_int;    // 3

assign rxdprioout_phy_ch1[`rtx_term_DP_RX_IDX_1    : `rtx_term_DP_RX_IDX_0]    = rtx_term_ch1_int;      // 2-bits
assign rxdprioout_phy_ch1[`r_tx_det_rx_DP_RX_IDX_1 : `r_tx_det_rx_DP_RX_IDX_0] = r_tx_det_rx_ch1_int;   // 2-bit
assign rxdprioout_phy_ch1[`rrx_term_DP_RX_IDX_1    : `rrx_term_DP_RX_IDX_0]    = rrx_term_ch1_int;      // 2
assign rxdprioout_phy_ch1[`rforce_sigdet_DP_RX_IDX]                            = rforce_sigdet_int[1];  // 1 
assign rxdprioout_phy_ch1[`rrx_dc_couple_DP_RX_IDX]                            = rrx_dc_couple_int[1];  // 1
assign rxdprioout_phy_ch1[`rrx_eq_dc_DP_RX_IDX_1   : `rrx_eq_dc_DP_RX_IDX_0]   = rrx_eq_dc_ch1_int;     // 2 - qpmaused
assign rxdprioout_phy_ch1[`rrx_vtt_DP_RX_IDX_2     : `rrx_vtt_DP_RX_IDX_0]     = rrx_vtt_ch1_int;       // 3
assign rxdprioout_phy_ch1[`rrx_sloslv_DP_RX_IDX_2  : `rrx_sloslv_DP_RX_IDX_0]  = rrx_sloslv_ch1_int;    // 3

assign rxdprioout_phy_ch2[`rtx_term_DP_RX_IDX_1    : `rtx_term_DP_RX_IDX_0]    = rtx_term_ch2_int;      // 2-bits
assign rxdprioout_phy_ch2[`r_tx_det_rx_DP_RX_IDX_1 : `r_tx_det_rx_DP_RX_IDX_0] = r_tx_det_rx_ch2_int;   // 2-bit
assign rxdprioout_phy_ch2[`rrx_term_DP_RX_IDX_1    : `rrx_term_DP_RX_IDX_0]    = rrx_term_ch2_int;      // 2
assign rxdprioout_phy_ch2[`rforce_sigdet_DP_RX_IDX]                            = rforce_sigdet_int[2];  // 1 
assign rxdprioout_phy_ch2[`rrx_dc_couple_DP_RX_IDX]                            = rrx_dc_couple_int[2];  // 1
assign rxdprioout_phy_ch2[`rrx_eq_dc_DP_RX_IDX_1   : `rrx_eq_dc_DP_RX_IDX_0]   = rrx_eq_dc_ch2_int;     // 2 - qpmaused
assign rxdprioout_phy_ch2[`rrx_vtt_DP_RX_IDX_2     : `rrx_vtt_DP_RX_IDX_0]     = rrx_vtt_ch2_int;       // 3
assign rxdprioout_phy_ch2[`rrx_sloslv_DP_RX_IDX_2  : `rrx_sloslv_DP_RX_IDX_0]  = rrx_sloslv_ch2_int;    // 3

assign rxdprioout_phy_ch3[`rtx_term_DP_RX_IDX_1    : `rtx_term_DP_RX_IDX_0]    = rtx_term_ch3_int;      // 2-bits
assign rxdprioout_phy_ch3[`r_tx_det_rx_DP_RX_IDX_1 : `r_tx_det_rx_DP_RX_IDX_0] = r_tx_det_rx_ch3_int;   // 2-bit
assign rxdprioout_phy_ch3[`rrx_term_DP_RX_IDX_1    : `rrx_term_DP_RX_IDX_0]    = rrx_term_ch3_int;      // 2
assign rxdprioout_phy_ch3[`rforce_sigdet_DP_RX_IDX]                            = rforce_sigdet_int[3];  // 1 
assign rxdprioout_phy_ch3[`rrx_dc_couple_DP_RX_IDX]                            = rrx_dc_couple_int[3];  // 1
assign rxdprioout_phy_ch3[`rrx_eq_dc_DP_RX_IDX_1   : `rrx_eq_dc_DP_RX_IDX_0]   = rrx_eq_dc_ch3_int;     // 2 - qpmaused
assign rxdprioout_phy_ch3[`rrx_vtt_DP_RX_IDX_2     : `rrx_vtt_DP_RX_IDX_0]     = rrx_vtt_ch3_int;       // 3
assign rxdprioout_phy_ch3[`rrx_sloslv_DP_RX_IDX_2  : `rrx_sloslv_DP_RX_IDX_0]  = rrx_sloslv_ch3_int;    // 3

// pma_ctrl3: 4.8068-4.806b (rx)
assign rxdprioout_phy_ch0[`reqa_ct_DP_RX_IDX_2 : `reqa_ct_DP_RX_IDX_0] = reqa_ct_ch0_int;    // 3-bits  - qpmaused
assign rxdprioout_phy_ch0[`reqb_ct_DP_RX_IDX_2 : `reqb_ct_DP_RX_IDX_0] = reqb_ct_ch0_int;    // 3-bit - qpmaused
assign rxdprioout_phy_ch0[`reqc_ct_DP_RX_IDX_2 : `reqc_ct_DP_RX_IDX_0]  = reqc_ct_ch0_int;    // 3 - qpmaused
assign rxdprioout_phy_ch0[`reqd_ct_DP_RX_IDX_2 : `reqd_ct_DP_RX_IDX_0]  = reqd_ct_ch0_int;    // 3 - qpmaused 
assign rxdprioout_phy_ch0[`req_ctv_DP_RX_IDX_2 : `req_ctv_DP_RX_IDX_0]  = req_ctv_ch0_int;    // 3 - qpmaused

assign rxdprioout_phy_ch1[`reqa_ct_DP_RX_IDX_2 : `reqa_ct_DP_RX_IDX_0] = reqa_ct_ch1_int;    // 3-bits  - qpmaused
assign rxdprioout_phy_ch1[`reqb_ct_DP_RX_IDX_2 : `reqb_ct_DP_RX_IDX_0] = reqb_ct_ch1_int;    // 3-bit - qpmaused
assign rxdprioout_phy_ch1[`reqc_ct_DP_RX_IDX_2 : `reqc_ct_DP_RX_IDX_0]  = reqc_ct_ch1_int;    // 3 - qpmaused
assign rxdprioout_phy_ch1[`reqd_ct_DP_RX_IDX_2 : `reqd_ct_DP_RX_IDX_0]  = reqd_ct_ch1_int;    // 3 - qpmaused 
assign rxdprioout_phy_ch1[`req_ctv_DP_RX_IDX_2 : `req_ctv_DP_RX_IDX_0]  = req_ctv_ch1_int;    // 3 - qpmaused

assign rxdprioout_phy_ch2[`reqa_ct_DP_RX_IDX_2 : `reqa_ct_DP_RX_IDX_0] = reqa_ct_ch2_int;    // 3-bits  - qpmaused
assign rxdprioout_phy_ch2[`reqb_ct_DP_RX_IDX_2 : `reqb_ct_DP_RX_IDX_0] = reqb_ct_ch2_int;    // 3-bit - qpmaused
assign rxdprioout_phy_ch2[`reqc_ct_DP_RX_IDX_2 : `reqc_ct_DP_RX_IDX_0]  = reqc_ct_ch2_int;    // 3 - qpmaused
assign rxdprioout_phy_ch2[`reqd_ct_DP_RX_IDX_2 : `reqd_ct_DP_RX_IDX_0]  = reqd_ct_ch2_int;    // 3 - qpmaused 
assign rxdprioout_phy_ch2[`req_ctv_DP_RX_IDX_2 : `req_ctv_DP_RX_IDX_0]  = req_ctv_ch2_int;    // 3 - qpmaused

assign rxdprioout_phy_ch3[`reqa_ct_DP_RX_IDX_2 : `reqa_ct_DP_RX_IDX_0] = reqa_ct_ch3_int;    // 3-bits  - qpmaused
assign rxdprioout_phy_ch3[`reqb_ct_DP_RX_IDX_2 : `reqb_ct_DP_RX_IDX_0] = reqb_ct_ch3_int;    // 3-bit - qpmaused
assign rxdprioout_phy_ch3[`reqc_ct_DP_RX_IDX_2 : `reqc_ct_DP_RX_IDX_0]  = reqc_ct_ch3_int;    // 3 - qpmaused
assign rxdprioout_phy_ch3[`reqd_ct_DP_RX_IDX_2 : `reqd_ct_DP_RX_IDX_0]  = reqd_ct_ch3_int;    // 3 - qpmaused 
assign rxdprioout_phy_ch3[`req_ctv_DP_RX_IDX_2 : `req_ctv_DP_RX_IDX_0]  = req_ctv_ch3_int;    // 3 - qpmaused

// part of pma_ctrl4 806Ch
assign rxdprioout_phy_ch0[`rpmadwidth_rx_DP_RX_IDX]       = rpmadwidth_rx_int[0];
assign rxdprioout_phy_ch0[`rpma_doublewidth_rx_DP_RX_IDX] = rpma_doublewidth_rx_int[0];
                                                                                                     
assign rxdprioout_phy_ch1[`rpmadwidth_rx_DP_RX_IDX]       = rpmadwidth_rx_int[1];
assign rxdprioout_phy_ch1[`rpma_doublewidth_rx_DP_RX_IDX] = rpma_doublewidth_rx_int[1];
                                                                                                     
assign rxdprioout_phy_ch2[`rpmadwidth_rx_DP_RX_IDX]       = rpmadwidth_rx_int[2];
assign rxdprioout_phy_ch2[`rpma_doublewidth_rx_DP_RX_IDX] = rpma_doublewidth_rx_int[2];
                                                                                                     
assign rxdprioout_phy_ch3[`rpmadwidth_rx_DP_RX_IDX]       = rpmadwidth_rx_int[3];
assign rxdprioout_phy_ch3[`rpma_doublewidth_rx_DP_RX_IDX] = rpma_doublewidth_rx_int[3];

// pma_ctrl6: 8074-8077 (rx)
assign rxdprioout_phy_ch0[`rrx_cru_m_sel_DP_RX_IDX_1 : `rrx_cru_m_sel_DP_RX_IDX_0] = rrx_cru_m_sel_ch0_int;
assign rxdprioout_phy_ch0[`rrx_cru_div2_DP_RX_IDX]                                = rrx_cru_div2_int[0];
assign rxdprioout_phy_ch0[`rltr_DP_RX_IDX]                                        = rltr_int[0];
assign rxdprioout_phy_ch0[`rltd_DP_RX_IDX]                                        = rltd_int[0];

assign rxdprioout_phy_ch1[`rrx_cru_m_sel_DP_RX_IDX_1 : `rrx_cru_m_sel_DP_RX_IDX_0] = rrx_cru_m_sel_ch1_int;
assign rxdprioout_phy_ch1[`rrx_cru_div2_DP_RX_IDX]                                = rrx_cru_div2_int[1];
assign rxdprioout_phy_ch1[`rltr_DP_RX_IDX]                                        = rltr_int[1];
assign rxdprioout_phy_ch1[`rltd_DP_RX_IDX]                                        = rltd_int[1];

assign rxdprioout_phy_ch2[`rrx_cru_m_sel_DP_RX_IDX_1 : `rrx_cru_m_sel_DP_RX_IDX_0] = rrx_cru_m_sel_ch2_int;
assign rxdprioout_phy_ch2[`rrx_cru_div2_DP_RX_IDX]                                = rrx_cru_div2_int[2];
assign rxdprioout_phy_ch2[`rltr_DP_RX_IDX]                                        = rltr_int[2];
assign rxdprioout_phy_ch2[`rltd_DP_RX_IDX]                                        = rltd_int[2];

assign rxdprioout_phy_ch3[`rrx_cru_m_sel_DP_RX_IDX_1 : `rrx_cru_m_sel_DP_RX_IDX_0] = rrx_cru_m_sel_ch3_int;
assign rxdprioout_phy_ch3[`rrx_cru_div2_DP_RX_IDX]                                = rrx_cru_div2_int[3];
assign rxdprioout_phy_ch3[`rltr_DP_RX_IDX]                                        = rltr_int[3];
assign rxdprioout_phy_ch3[`rltd_DP_RX_IDX]                                        = rltd_int[3];

// pma_ctrl7: 8078-807B
assign rxdprioout_phy_ch0[`rrx_cru_m_DP_RX_IDX_3 : `rrx_cru_m_DP_RX_IDX_0] = rrx_cru_m_ch0_int;
assign rxdprioout_phy_ch0[`rrx_cru_l_DP_RX_IDX_1 : `rrx_cru_l_DP_RX_IDX_0] = rrx_cru_l_ch0_int;

assign rxdprioout_phy_ch1[`rrx_cru_m_DP_RX_IDX_3 : `rrx_cru_m_DP_RX_IDX_0] = rrx_cru_m_ch1_int;
assign rxdprioout_phy_ch1[`rrx_cru_l_DP_RX_IDX_1 : `rrx_cru_l_DP_RX_IDX_0] = rrx_cru_l_ch1_int;

assign rxdprioout_phy_ch2[`rrx_cru_m_DP_RX_IDX_3 : `rrx_cru_m_DP_RX_IDX_0] = rrx_cru_m_ch2_int;
assign rxdprioout_phy_ch2[`rrx_cru_l_DP_RX_IDX_1 : `rrx_cru_l_DP_RX_IDX_0] = rrx_cru_l_ch2_int;

assign rxdprioout_phy_ch3[`rrx_cru_m_DP_RX_IDX_3 : `rrx_cru_m_DP_RX_IDX_0] = rrx_cru_m_ch3_int;
assign rxdprioout_phy_ch3[`rrx_cru_l_DP_RX_IDX_1 : `rrx_cru_l_DP_RX_IDX_0] = rrx_cru_l_ch3_int;
                                                                                                     
// pma_ctrl8: 4.807c-807h - RX portion
assign rxdprioout_phy_ch0[`rs_lpbk_DP_RX_IDX]              = rs_lpbk_int[0]; 
assign rxdprioout_phy_ch0[`rrx_revlb_sw_DP_RX_IDX]         = rrx_revlb_sw_int[0]; 
assign rxdprioout_phy_ch1[`rs_lpbk_DP_RX_IDX]              = rs_lpbk_int[1]; 
assign rxdprioout_phy_ch1[`rrx_revlb_sw_DP_RX_IDX]         = rrx_revlb_sw_int[1]; 
assign rxdprioout_phy_ch2[`rs_lpbk_DP_RX_IDX]              = rs_lpbk_int[2]; 
assign rxdprioout_phy_ch2[`rrx_revlb_sw_DP_RX_IDX]         = rrx_revlb_sw_int[2]; 
assign rxdprioout_phy_ch3[`rs_lpbk_DP_RX_IDX]              = rs_lpbk_int[3]; 
assign rxdprioout_phy_ch3[`rrx_revlb_sw_DP_RX_IDX]         = rrx_revlb_sw_int[3]; 

// ============= rxpma_ctrl_output_to_add  - make sure _int is used =============

// PMA_GLOBAL_CTRL_4
// assign  pma_global_ctrl4_ext = {rcmu0_m, rcmu1_m, rcmu0_l, rcmu1_l, rcmu0_pdb, rcmu1_pdb,
//                                rcmu0_txpll_rst, rcmu1_txpll_rst};

assign tmp_cmupll_m0 = cmuplldprioin_phy_0[`rcmu_m_DP_CMUPLL_IDX_7 : `rcmu_m_DP_CMUPLL_IDX_0];
assign tmp_cmupll_l0 = cmuplldprioin_phy_0[`rcmu_l_DP_CMUPLL_IDX_7 : `rcmu_l_DP_CMUPLL_IDX_0];
assign tmp_cmupll_m1 = cmuplldprioin_phy_1[`rcmu_m_DP_CMUPLL_IDX_7 : `rcmu_m_DP_CMUPLL_IDX_0];
assign tmp_cmupll_l1 = cmuplldprioin_phy_1[`rcmu_l_DP_CMUPLL_IDX_7 : `rcmu_l_DP_CMUPLL_IDX_0];
assign tmp_cmupll_m2 = cmuplldprioin_phy_2[`rcmu_m_DP_CMUPLL_IDX_7 : `rcmu_m_DP_CMUPLL_IDX_0];
assign tmp_cmupll_l2 = cmuplldprioin_phy_2[`rcmu_l_DP_CMUPLL_IDX_7 : `rcmu_l_DP_CMUPLL_IDX_0];

assign rcmu0_m = convert_cmupll_m_in_to_cram(tmp_cmupll_m0);
assign rcmu1_m = convert_cmupll_m_in_to_cram(tmp_cmupll_m1);
assign rcmu2_m = convert_cmupll_m_in_to_cram(tmp_cmupll_m2);
assign rcmu0_l = convert_cmupll_l_in_to_cram(tmp_cmupll_l0);
assign rcmu1_l = convert_cmupll_l_in_to_cram(tmp_cmupll_l1);
assign rcmu2_l = convert_cmupll_l_in_to_cram(tmp_cmupll_l2);

assign rcmu0_pdb = 1'b1; // default by design cmuplldprioin_phy_0[`rcmu_pdb_DP_CMUPLL_IDX];
assign rcmu1_pdb = 1'b1; // default by design cmuplldprioin_phy_1[`rcmu_pdb_DP_CMUPLL_IDX];
assign rcmu2_pdb = 1'b1; // default by design cmuplldprioin_phy_2[`rcmu_pdb_DP_CMUPLL_IDX];

assign rcmu0_txpll_rst = 1'b0; // default by design cmuplldprioin_phy_0[`rcmu_txpll_rst_DP_CMUPLL_IDX];
assign rcmu1_txpll_rst = 1'b0; // default by design cmuplldprioin_phy_1[`rcmu_txpll_rst_DP_CMUPLL_IDX];
assign rcmu2_txpll_rst = 1'b0; // default by design cmuplldprioin_phy_2[`rcmu_txpll_rst_DP_CMUPLL_IDX];

                 
// ============= cmupll_ctrl_input_to_add   =============


// CMUPLL output ---------------------------------------------------------------------------
assign tmp_cmupll_m0_int = convert_cram_to_cmupll_m_out(rcmu0_m_int);
assign tmp_cmupll_l0_int = convert_cram_to_cmupll_l_out(rcmu0_l_int);
assign tmp_cmupll_m1_int = convert_cram_to_cmupll_m_out(rcmu1_m_int);
assign tmp_cmupll_l1_int = convert_cram_to_cmupll_l_out(rcmu1_l_int);
assign tmp_cmupll_m2_int = convert_cram_to_cmupll_m_out(rcmu2_m_int);
assign tmp_cmupll_l2_int = convert_cram_to_cmupll_l_out(rcmu2_l_int);

assign cmuplldprioout_phy_0[`rcmu_m_DP_CMUPLL_IDX_7 : `rcmu_m_DP_CMUPLL_IDX_0] = tmp_cmupll_m0_int;
assign cmuplldprioout_phy_0[`rcmu_l_DP_CMUPLL_IDX_7 : `rcmu_l_DP_CMUPLL_IDX_0] = tmp_cmupll_l0_int;
assign cmuplldprioout_phy_1[`rcmu_m_DP_CMUPLL_IDX_7 : `rcmu_m_DP_CMUPLL_IDX_0] = tmp_cmupll_m1_int;
assign cmuplldprioout_phy_1[`rcmu_l_DP_CMUPLL_IDX_7 : `rcmu_l_DP_CMUPLL_IDX_0] = tmp_cmupll_l1_int;
assign cmuplldprioout_phy_2[`rcmu_m_DP_CMUPLL_IDX_7 : `rcmu_m_DP_CMUPLL_IDX_0] = tmp_cmupll_m2_int;
assign cmuplldprioout_phy_2[`rcmu_l_DP_CMUPLL_IDX_7 : `rcmu_l_DP_CMUPLL_IDX_0] = tmp_cmupll_l2_int;

assign cmuplldprioout_phy_0[`rcmu_pdb_DP_CMUPLL_IDX] = (rcmu0_pdb_int === 1'b0) ? 1'b1 : 1'b0;
assign cmuplldprioout_phy_1[`rcmu_pdb_DP_CMUPLL_IDX] = (rcmu1_pdb_int === 1'b0) ? 1'b1 : 1'b0;
assign cmuplldprioout_phy_2[`rcmu_pdb_DP_CMUPLL_IDX] = (rcmu2_pdb_int === 1'b0) ? 1'b1 : 1'b0;

assign cmuplldprioout_phy_0[`rcmu_txpll_rst_DP_CMUPLL_IDX] = (rcmu0_txpll_rst_int === 1'b1) ? 1'b1 : 1'b0;
assign cmuplldprioout_phy_1[`rcmu_txpll_rst_DP_CMUPLL_IDX] = (rcmu1_txpll_rst_int === 1'b1) ? 1'b1 : 1'b0;
assign cmuplldprioout_phy_2[`rcmu_txpll_rst_DP_CMUPLL_IDX] = (rcmu2_txpll_rst_int === 1'b1) ? 1'b1 : 1'b0;

// ============= cmupll_ctrl_output_to_add  - make sure _int is used =============


// PCS  - rx and tx mixed together within the 16-bit register

// PCS input -----------------------------------------------------------------------------

// PCS Trunking 
// rx = 4, tx=3
//assign  trunking_mode_ext = {1'b0, rphfifo_master_sel_tx, rphfifo_master_sel_rx, 
// 8000h same for all ch       rendec_data_sel_tx, rendec_data_sel_rx, rnenbpin, rpllurst, 
//                             rreset, rrsvd_cmu, rdeskewen, rindv_tx, rindv_rx};
// every channel within the quad is the same in trunking.

assign rphfifo_master_sel_rx    = (rxdprioin_phy_ch0[`rphfifo_master_sel_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch0[`rphfifo_master_sel_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch0[`rphfifo_master_sel_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch1[`rphfifo_master_sel_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch1[`rphfifo_master_sel_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch1[`rphfifo_master_sel_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch2[`rphfifo_master_sel_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch2[`rphfifo_master_sel_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch2[`rphfifo_master_sel_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch3[`rphfifo_master_sel_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch3[`rphfifo_master_sel_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch3[`rphfifo_master_sel_rx_DP_RX_IDX] :
                                  1'b1;
assign rendec_data_sel_rx       = (rxdprioin_phy_ch0[`rendec_data_sel_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch0[`rendec_data_sel_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch0[`rendec_data_sel_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch1[`rendec_data_sel_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch1[`rendec_data_sel_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch1[`rendec_data_sel_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch2[`rendec_data_sel_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch2[`rendec_data_sel_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch2[`rendec_data_sel_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch3[`rendec_data_sel_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch3[`rendec_data_sel_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch3[`rendec_data_sel_rx_DP_RX_IDX] :
                                  1'b1; // 0 = XAUI
assign rindv_rx                 = (rxdprioin_phy_ch0[`rindv_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch0[`rindv_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch0[`rindv_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch1[`rindv_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch1[`rindv_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch1[`rindv_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch2[`rindv_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch2[`rindv_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch2[`rindv_rx_DP_RX_IDX] :
                                  (rxdprioin_phy_ch3[`rindv_rx_DP_RX_IDX] === 1'b0 || rxdprioin_phy_ch3[`rindv_rx_DP_RX_IDX] === 1'b1) ? rxdprioin_phy_ch3[`rindv_rx_DP_RX_IDX] :
                                  1'b1;
//tx
assign rphfifo_master_sel_tx    = (txdprioin_phy_ch0[`rphfifo_master_sel_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch0[`rphfifo_master_sel_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch0[`rphfifo_master_sel_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch1[`rphfifo_master_sel_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch1[`rphfifo_master_sel_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch1[`rphfifo_master_sel_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch2[`rphfifo_master_sel_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch2[`rphfifo_master_sel_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch2[`rphfifo_master_sel_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch3[`rphfifo_master_sel_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch3[`rphfifo_master_sel_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch3[`rphfifo_master_sel_tx_DP_TX_IDX] :
                                  1'b1;
assign rendec_data_sel_tx       = (txdprioin_phy_ch0[`rendec_data_sel_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch0[`rendec_data_sel_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch0[`rendec_data_sel_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch1[`rendec_data_sel_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch1[`rendec_data_sel_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch1[`rendec_data_sel_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch2[`rendec_data_sel_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch2[`rendec_data_sel_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch2[`rendec_data_sel_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch3[`rendec_data_sel_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch3[`rendec_data_sel_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch3[`rendec_data_sel_tx_DP_TX_IDX] :
                                  1'b1; // 0 = XAUI
assign rindv_tx                 = (txdprioin_phy_ch0[`rindv_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch0[`rindv_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch0[`rindv_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch1[`rindv_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch1[`rindv_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch1[`rindv_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch2[`rindv_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch2[`rindv_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch2[`rindv_tx_DP_TX_IDX] :
                                  (txdprioin_phy_ch3[`rindv_tx_DP_TX_IDX] === 1'b0 || txdprioin_phy_ch3[`rindv_tx_DP_TX_IDX] === 1'b1) ? txdprioin_phy_ch3[`rindv_tx_DP_TX_IDX] :
                                  1'b1;


// PCS_CTRL1 - mix of RX and TX
// page divided into both rx and tx
// pcs_ctrl1_ch0_ext = {rtx_pipe_enable[0], rrx_pipe_enable[0], rpowdnr[0], rpowdnt[0],
// 8001-8004            rendec_tx[0], rendec_rx[0], r8b10b_enc_ibm_en[0], rmatchen[0],
//                      r8b10b_dec_ibm_en_ch0, rforce_kchar[0], rforce_echar[0],
//                      rlp20ben[0], rgenericfifo[0], rcascaded_8b10b_en_tx[0],
//                      rcascaded_8b10b_en_rx[0]};
assign rtx_pipe_enable[0]       = txdprioin_phy_ch0[`rtx_pipe_enable_DP_TX_IDX];
assign rrx_pipe_enable[0]       = rxdprioin_phy_ch0[`rrx_pipe_enable_DP_RX_IDX];
assign rpowdnt[0]               = txdprioin_phy_ch0[`rpowdnt_DP_TX_IDX];
assign rpowdnr[0]               = rxdprioin_phy_ch0[`rpowdnr_DP_RX_IDX];
assign rendec_tx[0]             = txdprioin_phy_ch0[`rendec_tx_DP_TX_IDX];
assign rendec_rx[0]             = rxdprioin_phy_ch0[`rendec_rx_DP_RX_IDX];
assign r8b10b_enc_ibm_en[0]     = txdprioin_phy_ch0[`r8b10b_enc_ibm_en_DP_TX_IDX];
assign rmatchen[0]              = rxdprioin_phy_ch0[`rmatchen_DP_RX_IDX];
assign r8b10b_dec_ibm_en_ch0    = rxdprioin_phy_ch0[`r8b10b_dec_ibm_en_DP_RX_IDX_1 : `r8b10b_dec_ibm_en_DP_RX_IDX_0];
assign rforce_kchar[0]          = txdprioin_phy_ch0[`rforce_kchar_DP_TX_IDX];
assign rforce_echar[0]          = txdprioin_phy_ch0[`rforce_echar_DP_TX_IDX];
assign rlp20ben[0]              = rxdprioin_phy_ch0[`rlp20ben_DP_RX_IDX];
assign rgenericfifo[0]          = rxdprioin_phy_ch0[`rgenericfifo_DP_RX_IDX];
assign rcascaded_8b10b_en_tx[0] = txdprioin_phy_ch0[`rcascaded_8b10b_en_tx_DP_TX_IDX];
assign rcascaded_8b10b_en_rx[0] = rxdprioin_phy_ch0[`rcascaded_8b10b_en_rx_DP_RX_IDX];

assign rtx_pipe_enable[1]       = txdprioin_phy_ch1[`rtx_pipe_enable_DP_TX_IDX];
assign rrx_pipe_enable[1]       = rxdprioin_phy_ch1[`rrx_pipe_enable_DP_RX_IDX];
assign rpowdnt[1]               = txdprioin_phy_ch1[`rpowdnt_DP_TX_IDX];
assign rpowdnr[1]               = rxdprioin_phy_ch1[`rpowdnr_DP_RX_IDX];
assign rendec_tx[1]             = txdprioin_phy_ch1[`rendec_tx_DP_TX_IDX];
assign rendec_rx[1]             = rxdprioin_phy_ch1[`rendec_rx_DP_RX_IDX];
assign r8b10b_enc_ibm_en[1]     = txdprioin_phy_ch1[`r8b10b_enc_ibm_en_DP_TX_IDX];
assign rmatchen[1]              = rxdprioin_phy_ch1[`rmatchen_DP_RX_IDX];
assign r8b10b_dec_ibm_en_ch1    = rxdprioin_phy_ch1[`r8b10b_dec_ibm_en_DP_RX_IDX_1 : `r8b10b_dec_ibm_en_DP_RX_IDX_0];
assign rforce_kchar[1]          = txdprioin_phy_ch1[`rforce_kchar_DP_TX_IDX];
assign rforce_echar[1]          = txdprioin_phy_ch1[`rforce_echar_DP_TX_IDX];
assign rlp20ben[1]              = rxdprioin_phy_ch1[`rlp20ben_DP_RX_IDX];
assign rgenericfifo[1]          = rxdprioin_phy_ch1[`rgenericfifo_DP_RX_IDX];
assign rcascaded_8b10b_en_tx[1] = txdprioin_phy_ch1[`rcascaded_8b10b_en_tx_DP_TX_IDX];
assign rcascaded_8b10b_en_rx[1] = rxdprioin_phy_ch1[`rcascaded_8b10b_en_rx_DP_RX_IDX];

assign rtx_pipe_enable[2]       = txdprioin_phy_ch2[`rtx_pipe_enable_DP_TX_IDX];
assign rrx_pipe_enable[2]       = rxdprioin_phy_ch2[`rrx_pipe_enable_DP_RX_IDX];
assign rpowdnt[2]               = txdprioin_phy_ch2[`rpowdnt_DP_TX_IDX];
assign rpowdnr[2]               = rxdprioin_phy_ch2[`rpowdnr_DP_RX_IDX];
assign rendec_tx[2]             = txdprioin_phy_ch2[`rendec_tx_DP_TX_IDX];
assign rendec_rx[2]             = rxdprioin_phy_ch2[`rendec_rx_DP_RX_IDX];
assign r8b10b_enc_ibm_en[2]     = txdprioin_phy_ch2[`r8b10b_enc_ibm_en_DP_TX_IDX];
assign rmatchen[2]              = rxdprioin_phy_ch2[`rmatchen_DP_RX_IDX];
assign r8b10b_dec_ibm_en_ch2    = rxdprioin_phy_ch2[`r8b10b_dec_ibm_en_DP_RX_IDX_1 : `r8b10b_dec_ibm_en_DP_RX_IDX_0];
assign rforce_kchar[2]          = txdprioin_phy_ch2[`rforce_kchar_DP_TX_IDX];
assign rforce_echar[2]          = txdprioin_phy_ch2[`rforce_echar_DP_TX_IDX];
assign rlp20ben[2]              = rxdprioin_phy_ch2[`rlp20ben_DP_RX_IDX];
assign rgenericfifo[2]          = rxdprioin_phy_ch2[`rgenericfifo_DP_RX_IDX];
assign rcascaded_8b10b_en_tx[2] = txdprioin_phy_ch2[`rcascaded_8b10b_en_tx_DP_TX_IDX];
assign rcascaded_8b10b_en_rx[2] = rxdprioin_phy_ch2[`rcascaded_8b10b_en_rx_DP_RX_IDX];

assign rtx_pipe_enable[3]       = txdprioin_phy_ch3[`rtx_pipe_enable_DP_TX_IDX];
assign rrx_pipe_enable[3]       = rxdprioin_phy_ch3[`rrx_pipe_enable_DP_RX_IDX];
assign rpowdnt[3]               = txdprioin_phy_ch3[`rpowdnt_DP_TX_IDX];
assign rpowdnr[3]               = rxdprioin_phy_ch3[`rpowdnr_DP_RX_IDX];
assign rendec_tx[3]             = txdprioin_phy_ch3[`rendec_tx_DP_TX_IDX];
assign rendec_rx[3]             = rxdprioin_phy_ch3[`rendec_rx_DP_RX_IDX];
assign r8b10b_enc_ibm_en[3]     = txdprioin_phy_ch3[`r8b10b_enc_ibm_en_DP_TX_IDX];
assign rmatchen[3]              = rxdprioin_phy_ch3[`rmatchen_DP_RX_IDX];
assign r8b10b_dec_ibm_en_ch3    = rxdprioin_phy_ch3[`r8b10b_dec_ibm_en_DP_RX_IDX_1 : `r8b10b_dec_ibm_en_DP_RX_IDX_0];
assign rforce_kchar[3]          = txdprioin_phy_ch3[`rforce_kchar_DP_TX_IDX];
assign rforce_echar[3]          = txdprioin_phy_ch3[`rforce_echar_DP_TX_IDX];
assign rlp20ben[3]              = rxdprioin_phy_ch3[`rlp20ben_DP_RX_IDX];
assign rgenericfifo[3]          = rxdprioin_phy_ch3[`rgenericfifo_DP_RX_IDX];
assign rcascaded_8b10b_en_tx[3] = txdprioin_phy_ch3[`rcascaded_8b10b_en_tx_DP_TX_IDX];
assign rcascaded_8b10b_en_rx[3] = rxdprioin_phy_ch3[`rcascaded_8b10b_en_rx_DP_RX_IDX];

// PCS_CTRL2 - all RX
//assign  pcs_ctrl2_ch0_ext = {resync_badcg_en_ch0, rencdt_rising[0], rdis_rx_disp[0],
// 8005-8008                   rcomp_pat_porn[0], rcomp_size_ch0, rcomp_pat_ch0[39:32]};
assign resync_badcg_en_ch0 = 2'b00; 
assign rencdt_rising[0]    = rxdprioin_phy_ch0[`rencdt_rising_DP_RX_IDX]; 
assign rdis_rx_disp[0]     = rxdprioin_phy_ch0[`rdis_rx_disp_DP_RX_IDX];
assign rcomp_pat_porn[0]   = rxdprioin_phy_ch0[`rcomp_pat_porn_DP_RX_IDX]; 
assign rcomp_size_ch0      = rxdprioin_phy_ch0[`rcomp_size_DP_RX_IDX_2 : `rcomp_size_DP_RX_IDX_0]; 

assign resync_badcg_en_ch1 = 2'b00; 
assign rencdt_rising[1]    = rxdprioin_phy_ch1[`rencdt_rising_DP_RX_IDX]; 
assign rdis_rx_disp[1]     = rxdprioin_phy_ch1[`rdis_rx_disp_DP_RX_IDX];
assign rcomp_pat_porn[1]   = rxdprioin_phy_ch1[`rcomp_pat_porn_DP_RX_IDX]; 
assign rcomp_size_ch1      = rxdprioin_phy_ch1[`rcomp_size_DP_RX_IDX_2 : `rcomp_size_DP_RX_IDX_0]; 

assign resync_badcg_en_ch2 = 2'b00; 
assign rencdt_rising[2]    = rxdprioin_phy_ch2[`rencdt_rising_DP_RX_IDX]; 
assign rdis_rx_disp[2]     = rxdprioin_phy_ch2[`rdis_rx_disp_DP_RX_IDX];
assign rcomp_pat_porn[2]   = rxdprioin_phy_ch2[`rcomp_pat_porn_DP_RX_IDX]; 
assign rcomp_size_ch2      = rxdprioin_phy_ch2[`rcomp_size_DP_RX_IDX_2 : `rcomp_size_DP_RX_IDX_0]; 

assign resync_badcg_en_ch3 = 2'b00; 
assign rencdt_rising[3]    = rxdprioin_phy_ch3[`rencdt_rising_DP_RX_IDX]; 
assign rdis_rx_disp[3]     = rxdprioin_phy_ch3[`rdis_rx_disp_DP_RX_IDX];
assign rcomp_pat_porn[3]   = rxdprioin_phy_ch3[`rcomp_pat_porn_DP_RX_IDX]; 
assign rcomp_size_ch3      = rxdprioin_phy_ch3[`rcomp_size_DP_RX_IDX_2 : `rcomp_size_DP_RX_IDX_0]; 

// PCS_CTRL3 and 4 - all RX
// page 2 (part) + 3 + 4 - all rx - 32
//assign  pcs_ctrl3_ch0_ext = {rcomp_pat_ch0[31:16]};
// 8009-800c
//assign  pcs_ctrl4_ch0_ext = {rcomp_pat_ch0[15:0]};
// 800d-8010
assign rcomp_pat_ch0 = rxdprioin_phy_ch0[`rcomp_pat_DP_RX_IDX_39 : `rcomp_pat_DP_RX_IDX_0]; 
assign rcomp_pat_ch1 = rxdprioin_phy_ch1[`rcomp_pat_DP_RX_IDX_39 : `rcomp_pat_DP_RX_IDX_0]; 
assign rcomp_pat_ch2 = rxdprioin_phy_ch2[`rcomp_pat_DP_RX_IDX_39 : `rcomp_pat_DP_RX_IDX_0]; 
assign rcomp_pat_ch3 = rxdprioin_phy_ch3[`rcomp_pat_DP_RX_IDX_39 : `rcomp_pat_DP_RX_IDX_0]; 

// PCS_CTRL5 - mix of RX and TX
// rx - 12
//assign  pcs_ctrl5_ch0_ext = {rrxfifo_dis[0], rtxfifo_dis[0], rib_force_disp[0],
//8011-8014                  rrundisp_ch0, rtxfifo_lowlatency_en[0], rrlv_en[0], rautobtalg_dis[0],
//                           rsync_sm_dis[0], rib_inv_cd_ch0, rrxfifo_lowlatency_en[0]};
assign rrxfifo_dis[0]           = rxdprioin_phy_ch0[`rrxfifo_dis_DP_RX_IDX]; 
assign rrundisp_ch0             = rxdprioin_phy_ch0[`rrundisp_DP_RX_IDX_5 : `rrundisp_DP_RX_IDX_0]; 
assign rrlv_en[0]               = rxdprioin_phy_ch0[`rrlv_en_DP_RX_IDX]; 
assign rautobtalg_dis[0]        = rxdprioin_phy_ch0[`rautobtalg_dis_DP_RX_IDX];
assign rsync_sm_dis[0]          = rxdprioin_phy_ch0[`rsync_sm_dis_DP_RX_IDX]; 
assign rib_inv_cd_ch0           = rxdprioin_phy_ch0[`rib_inv_cd_DP_RX_IDX_1 : `rib_inv_cd_DP_RX_IDX_0]; 
assign rrxfifo_lowlatency_en[0] = rxdprioin_phy_ch0[`rrxfifo_lowlatency_en_DP_RX_IDX];
// tx
assign rtxfifo_dis[0]           = txdprioin_phy_ch0[`rtxfifo_dis_DP_TX_IDX]; 
assign rib_force_disp[0]        = txdprioin_phy_ch0[`rib_force_disp_DP_TX_IDX];                 
assign rtxfifo_lowlatency_en[0] = txdprioin_phy_ch0[`rtxfifo_lowlatency_en_DP_TX_IDX]; 

assign rrxfifo_dis[1]           = rxdprioin_phy_ch1[`rrxfifo_dis_DP_RX_IDX]; 
assign rrundisp_ch1             = rxdprioin_phy_ch1[`rrundisp_DP_RX_IDX_5 : `rrundisp_DP_RX_IDX_0]; 
assign rrlv_en[1]               = rxdprioin_phy_ch1[`rrlv_en_DP_RX_IDX]; 
assign rautobtalg_dis[1]        = rxdprioin_phy_ch1[`rautobtalg_dis_DP_RX_IDX];
assign rsync_sm_dis[1]          = rxdprioin_phy_ch1[`rsync_sm_dis_DP_RX_IDX]; 
assign rib_inv_cd_ch1           = rxdprioin_phy_ch1[`rib_inv_cd_DP_RX_IDX_1 : `rib_inv_cd_DP_RX_IDX_0]; 
assign rrxfifo_lowlatency_en[1] = rxdprioin_phy_ch1[`rrxfifo_lowlatency_en_DP_RX_IDX];
// tx
assign rtxfifo_dis[1]           = txdprioin_phy_ch1[`rtxfifo_dis_DP_TX_IDX]; 
assign rib_force_disp[1]        = txdprioin_phy_ch1[`rib_force_disp_DP_TX_IDX];                 
assign rtxfifo_lowlatency_en[1] = txdprioin_phy_ch1[`rtxfifo_lowlatency_en_DP_TX_IDX]; 

assign rrxfifo_dis[2]           = rxdprioin_phy_ch2[`rrxfifo_dis_DP_RX_IDX]; 
assign rrundisp_ch2             = rxdprioin_phy_ch2[`rrundisp_DP_RX_IDX_5 : `rrundisp_DP_RX_IDX_0]; 
assign rrlv_en[2]               = rxdprioin_phy_ch2[`rrlv_en_DP_RX_IDX]; 
assign rautobtalg_dis[2]        = rxdprioin_phy_ch2[`rautobtalg_dis_DP_RX_IDX];
assign rsync_sm_dis[2]          = rxdprioin_phy_ch2[`rsync_sm_dis_DP_RX_IDX]; 
assign rib_inv_cd_ch2           = rxdprioin_phy_ch2[`rib_inv_cd_DP_RX_IDX_1 : `rib_inv_cd_DP_RX_IDX_0]; 
assign rrxfifo_lowlatency_en[2] = rxdprioin_phy_ch2[`rrxfifo_lowlatency_en_DP_RX_IDX];
// tx
assign rtxfifo_dis[2]           = txdprioin_phy_ch2[`rtxfifo_dis_DP_TX_IDX]; 
assign rib_force_disp[2]        = txdprioin_phy_ch2[`rib_force_disp_DP_TX_IDX];                 
assign rtxfifo_lowlatency_en[2] = txdprioin_phy_ch2[`rtxfifo_lowlatency_en_DP_TX_IDX]; 

assign rrxfifo_dis[3]           = rxdprioin_phy_ch3[`rrxfifo_dis_DP_RX_IDX]; 
assign rrundisp_ch3             = rxdprioin_phy_ch3[`rrundisp_DP_RX_IDX_5 : `rrundisp_DP_RX_IDX_0]; 
assign rrlv_en[3]               = rxdprioin_phy_ch3[`rrlv_en_DP_RX_IDX]; 
assign rautobtalg_dis[3]        = rxdprioin_phy_ch3[`rautobtalg_dis_DP_RX_IDX];
assign rsync_sm_dis[3]          = rxdprioin_phy_ch3[`rsync_sm_dis_DP_RX_IDX]; 
assign rib_inv_cd_ch3           = rxdprioin_phy_ch3[`rib_inv_cd_DP_RX_IDX_1 : `rib_inv_cd_DP_RX_IDX_0]; 
assign rrxfifo_lowlatency_en[3] = rxdprioin_phy_ch3[`rrxfifo_lowlatency_en_DP_RX_IDX];
// tx
assign rtxfifo_dis[3]           = txdprioin_phy_ch3[`rtxfifo_dis_DP_TX_IDX]; 
assign rib_force_disp[3]        = txdprioin_phy_ch3[`rib_force_disp_DP_TX_IDX];                 
assign rtxfifo_lowlatency_en[3] = txdprioin_phy_ch3[`rtxfifo_lowlatency_en_DP_TX_IDX]; 

// PCS_CTRL6 - mix of RX and TX
// rx - 8
//assign  pcs_ctrl6_ch0_ext = {rdwidth_tx[0], rdwidth_rx[0], rge_xaui_tx[0],
// 8015 - 8018                 rrx_detect_bypass[0], rtxurstpcs[0], rrxurstpcs[0],
//                             rrsvd_tx_ch0, rskpsetbased[0], rtruebac2bac[0],rrsvd_rx_ch0};
//
assign rdwidth_tx[0]         = txdprioin_phy_ch0[`rdwidth_tx_DP_TX_IDX];
assign rdwidth_rx[0]         = rxdprioin_phy_ch0[`rdwidth_rx_DP_RX_IDX];
assign rge_xaui_tx[0]        = txdprioin_phy_ch0[`rge_xaui_tx_DP_TX_IDX];
assign rrx_detect_bypass[0]  = rxdprioin_phy_ch0[`rrx_detect_bypass_DP_RX_IDX];
assign rtxurstpcs[0]         = txdprioin_phy_ch0[`rtxurstpcs_DP_TX_IDX];
assign rrxurstpcs[0]         = rxdprioin_phy_ch0[`rrxurstpcs_DP_RX_IDX];
assign rrsvd_tx_ch0          = txdprioin_phy_ch0[`rrsvd_tx_DP_TX_IDX_4 : `rrsvd_tx_DP_TX_IDX_0]; 
assign rskpsetbased[0]       = rxdprioin_phy_ch0[`rskpsetbased_DP_RX_IDX];
assign rtruebac2bac[0]       = rxdprioin_phy_ch0[`rtruebac2bac_DP_RX_IDX];
assign rrsvd_rx_ch0          = rxdprioin_phy_ch0[`rrsvd_rx_DP_RX_IDX_2 : `rrsvd_rx_DP_RX_IDX_0]; 

assign rdwidth_tx[1]         = txdprioin_phy_ch1[`rdwidth_tx_DP_TX_IDX];
assign rdwidth_rx[1]         = rxdprioin_phy_ch1[`rdwidth_rx_DP_RX_IDX];
assign rge_xaui_tx[1]        = txdprioin_phy_ch1[`rge_xaui_tx_DP_TX_IDX];
assign rrx_detect_bypass[1]  = rxdprioin_phy_ch1[`rrx_detect_bypass_DP_RX_IDX];
assign rtxurstpcs[1]         = txdprioin_phy_ch1[`rtxurstpcs_DP_TX_IDX];
assign rrxurstpcs[1]         = rxdprioin_phy_ch1[`rrxurstpcs_DP_RX_IDX];
assign rrsvd_tx_ch1          = txdprioin_phy_ch1[`rrsvd_tx_DP_TX_IDX_4 : `rrsvd_tx_DP_TX_IDX_0]; 
assign rskpsetbased[1]       = rxdprioin_phy_ch1[`rskpsetbased_DP_RX_IDX];
assign rtruebac2bac[1]       = rxdprioin_phy_ch1[`rtruebac2bac_DP_RX_IDX];
assign rrsvd_rx_ch1          = rxdprioin_phy_ch1[`rrsvd_rx_DP_RX_IDX_2 : `rrsvd_rx_DP_RX_IDX_0]; 

assign rdwidth_tx[2]         = txdprioin_phy_ch2[`rdwidth_tx_DP_TX_IDX];
assign rdwidth_rx[2]         = rxdprioin_phy_ch2[`rdwidth_rx_DP_RX_IDX];
assign rge_xaui_tx[2]        = txdprioin_phy_ch2[`rge_xaui_tx_DP_TX_IDX];
assign rrx_detect_bypass[2]  = rxdprioin_phy_ch2[`rrx_detect_bypass_DP_RX_IDX];
assign rtxurstpcs[2]         = txdprioin_phy_ch2[`rtxurstpcs_DP_TX_IDX];
assign rrxurstpcs[2]         = rxdprioin_phy_ch2[`rrxurstpcs_DP_RX_IDX];
assign rrsvd_tx_ch2          = txdprioin_phy_ch2[`rrsvd_tx_DP_TX_IDX_4 : `rrsvd_tx_DP_TX_IDX_0]; 
assign rskpsetbased[2]       = rxdprioin_phy_ch2[`rskpsetbased_DP_RX_IDX];
assign rtruebac2bac[2]       = rxdprioin_phy_ch2[`rtruebac2bac_DP_RX_IDX];
assign rrsvd_rx_ch2          = rxdprioin_phy_ch2[`rrsvd_rx_DP_RX_IDX_2 : `rrsvd_rx_DP_RX_IDX_0]; 

assign rdwidth_tx[3]         = txdprioin_phy_ch3[`rdwidth_tx_DP_TX_IDX];
assign rdwidth_rx[3]         = rxdprioin_phy_ch3[`rdwidth_rx_DP_RX_IDX];
assign rge_xaui_tx[3]        = txdprioin_phy_ch3[`rge_xaui_tx_DP_TX_IDX];
assign rrx_detect_bypass[3]  = rxdprioin_phy_ch3[`rrx_detect_bypass_DP_RX_IDX];
assign rtxurstpcs[3]         = txdprioin_phy_ch3[`rtxurstpcs_DP_TX_IDX];
assign rrxurstpcs[3]         = rxdprioin_phy_ch3[`rrxurstpcs_DP_RX_IDX];
assign rrsvd_tx_ch3          = txdprioin_phy_ch3[`rrsvd_tx_DP_TX_IDX_4 : `rrsvd_tx_DP_TX_IDX_0]; 
assign rskpsetbased[3]       = rxdprioin_phy_ch3[`rskpsetbased_DP_RX_IDX];
assign rtruebac2bac[3]       = rxdprioin_phy_ch3[`rtruebac2bac_DP_RX_IDX];
assign rrsvd_rx_ch3          = rxdprioin_phy_ch3[`rrsvd_rx_DP_RX_IDX_2 : `rrsvd_rx_DP_RX_IDX_0]; 

// PCS_CTRL7
// all rx   - 16                          
// assign  pcs_ctrl7_ch0_ext = {rgnumber_ch0, rknumber_ch0};
assign rgnumber_ch0          = rxdprioin_phy_ch0[`rgnumber_DP_RX_IDX_7 : `rgnumber_DP_RX_IDX_0]; 
assign rknumber_ch0          = rxdprioin_phy_ch0[`rknumber_DP_RX_IDX_7 : `rknumber_DP_RX_IDX_0]; 
assign rgnumber_ch1          = rxdprioin_phy_ch1[`rgnumber_DP_RX_IDX_7 : `rgnumber_DP_RX_IDX_0]; 
assign rknumber_ch1          = rxdprioin_phy_ch1[`rknumber_DP_RX_IDX_7 : `rknumber_DP_RX_IDX_0]; 
assign rgnumber_ch2          = rxdprioin_phy_ch2[`rgnumber_DP_RX_IDX_7 : `rgnumber_DP_RX_IDX_0]; 
assign rknumber_ch2          = rxdprioin_phy_ch2[`rknumber_DP_RX_IDX_7 : `rknumber_DP_RX_IDX_0]; 
assign rgnumber_ch3          = rxdprioin_phy_ch3[`rgnumber_DP_RX_IDX_7 : `rgnumber_DP_RX_IDX_0]; 
assign rknumber_ch3          = rxdprioin_phy_ch3[`rknumber_DP_RX_IDX_7 : `rknumber_DP_RX_IDX_0]; 


// PCS_CTRL8
assign rfreerun_rx[0]        = rxdprioin_phy_ch0[`rfreerun_rx_DP_RX_IDX];  // 4'h0;  for POF
assign rrx_rd_clk_sel[0]     = rxdprioin_phy_ch0[`rrx_rd_clk_sel_DP_RX_IDX];
assign renumber_ch0          = rxdprioin_phy_ch0[`renumber_DP_RX_IDX_2 : `renumber_DP_RX_IDX_0]; 
assign renpolinv_rx[0]       = rxdprioin_phy_ch0[`renpolinv_rx_DP_RX_IDX]; 
assign rclkcmpinsertpad[0]   = rxdprioin_phy_ch0[`rclkcmpinsertpad_DP_RX_IDX];
// tx
assign rfreerun_tx[0]        = txdprioin_phy_ch0[`rfreerun_tx_DP_TX_IDX];  // 4'h0;  for POF
assign rtxwrclksel[0]        = txdprioin_phy_ch0[`rtxwrclksel_DP_TX_IDX];
assign rtxrdclksel[0]        = txdprioin_phy_ch0[`rtxrdclksel_DP_TX_IDX]; 
assign rclk_1_sel_ch0     = rxdprioin_phy_ch0[`rclk_1_sel_DP_RX_IDX_1    : `rclk_1_sel_DP_RX_IDX_0];       // dprio_enabled: bits 9-8 
assign rclk_2_sel_ch0     = rxdprioin_phy_ch0[`rclk_2_sel_DP_RX_IDX_1    : `rclk_2_sel_DP_RX_IDX_0];       // dprio_enabled: bits 7-6
assign rrcvd_clk_sel_ch0  = rxdprioin_phy_ch0[`rrcvd_clk_sel_DP_RX_IDX_1 : `rrcvd_clk_sel_DP_RX_IDX_0];    // dprio_enabled: bits 11-10 

assign rfreerun_rx[1]        = rxdprioin_phy_ch1[`rfreerun_rx_DP_RX_IDX];  // 4'h0;  for POF
assign rrx_rd_clk_sel[1]     = rxdprioin_phy_ch1[`rrx_rd_clk_sel_DP_RX_IDX];
assign renumber_ch1          = rxdprioin_phy_ch1[`renumber_DP_RX_IDX_2 : `renumber_DP_RX_IDX_0]; 
assign renpolinv_rx[1]       = rxdprioin_phy_ch1[`renpolinv_rx_DP_RX_IDX]; 
assign rclkcmpinsertpad[1]   = rxdprioin_phy_ch1[`rclkcmpinsertpad_DP_RX_IDX];
// tx
assign rfreerun_tx[1]        = txdprioin_phy_ch1[`rfreerun_tx_DP_TX_IDX];  // 4'h0;  for POF
assign rtxwrclksel[1]        = txdprioin_phy_ch1[`rtxwrclksel_DP_TX_IDX];
assign rtxrdclksel[1]        = txdprioin_phy_ch1[`rtxrdclksel_DP_TX_IDX]; 
assign rclk_1_sel_ch1     = rxdprioin_phy_ch1[`rclk_1_sel_DP_RX_IDX_1    : `rclk_1_sel_DP_RX_IDX_0];       // dprio_enabled: bits 9-8 
assign rclk_2_sel_ch1     = rxdprioin_phy_ch1[`rclk_2_sel_DP_RX_IDX_1    : `rclk_2_sel_DP_RX_IDX_0];       // dprio_enabled: bits 7-6
assign rrcvd_clk_sel_ch1  = rxdprioin_phy_ch1[`rrcvd_clk_sel_DP_RX_IDX_1 : `rrcvd_clk_sel_DP_RX_IDX_0];    // dprio_enabled: bits 11-10 

assign rfreerun_rx[2]        = rxdprioin_phy_ch2[`rfreerun_rx_DP_RX_IDX];  // 4'h0;  for POF
assign rrx_rd_clk_sel[2]     = rxdprioin_phy_ch2[`rrx_rd_clk_sel_DP_RX_IDX];
assign renumber_ch2          = rxdprioin_phy_ch2[`renumber_DP_RX_IDX_2 : `renumber_DP_RX_IDX_0]; 
assign renpolinv_rx[2]       = rxdprioin_phy_ch2[`renpolinv_rx_DP_RX_IDX]; 
assign rclkcmpinsertpad[2]   = rxdprioin_phy_ch2[`rclkcmpinsertpad_DP_RX_IDX];
// tx
assign rfreerun_tx[2]        = txdprioin_phy_ch2[`rfreerun_tx_DP_TX_IDX];  // 4'h0;  for POF
assign rtxwrclksel[2]        = txdprioin_phy_ch2[`rtxwrclksel_DP_TX_IDX];
assign rtxrdclksel[2]        = txdprioin_phy_ch2[`rtxrdclksel_DP_TX_IDX]; 
assign rclk_1_sel_ch2     = rxdprioin_phy_ch2[`rclk_1_sel_DP_RX_IDX_1    : `rclk_1_sel_DP_RX_IDX_0];       // dprio_enabled: bits 9-8 
assign rclk_2_sel_ch2     = rxdprioin_phy_ch2[`rclk_2_sel_DP_RX_IDX_1    : `rclk_2_sel_DP_RX_IDX_0];       // dprio_enabled: bits 7-6
assign rrcvd_clk_sel_ch2  = rxdprioin_phy_ch2[`rrcvd_clk_sel_DP_RX_IDX_1 : `rrcvd_clk_sel_DP_RX_IDX_0];    // dprio_enabled: bits 11-10 

assign rfreerun_rx[3]        = rxdprioin_phy_ch3[`rfreerun_rx_DP_RX_IDX];  // 4'h0;  for POF
assign rrx_rd_clk_sel[3]     = rxdprioin_phy_ch3[`rrx_rd_clk_sel_DP_RX_IDX];
assign renumber_ch3          = rxdprioin_phy_ch3[`renumber_DP_RX_IDX_2 : `renumber_DP_RX_IDX_0]; 
assign renpolinv_rx[3]       = rxdprioin_phy_ch3[`renpolinv_rx_DP_RX_IDX]; 
assign rclkcmpinsertpad[3]   = rxdprioin_phy_ch3[`rclkcmpinsertpad_DP_RX_IDX];
// tx
assign rfreerun_tx[3]        = txdprioin_phy_ch3[`rfreerun_tx_DP_TX_IDX];  // 4'h0;  for POF
assign rtxwrclksel[3]        = txdprioin_phy_ch3[`rtxwrclksel_DP_TX_IDX];
assign rtxrdclksel[3]        = txdprioin_phy_ch3[`rtxrdclksel_DP_TX_IDX]; 
assign rclk_1_sel_ch3     = rxdprioin_phy_ch3[`rclk_1_sel_DP_RX_IDX_1    : `rclk_1_sel_DP_RX_IDX_0];       // dprio_enabled: bits 9-8 
assign rclk_2_sel_ch3     = rxdprioin_phy_ch3[`rclk_2_sel_DP_RX_IDX_1    : `rclk_2_sel_DP_RX_IDX_0];       // dprio_enabled: bits 7-6
assign rrcvd_clk_sel_ch3  = rxdprioin_phy_ch3[`rrcvd_clk_sel_DP_RX_IDX_1 : `rrcvd_clk_sel_DP_RX_IDX_0];    // dprio_enabled: bits 11-10 

// PCS_CTRL_9
//assign  pcs_ctrl9_ch0_ext = {rppm_cnt_reset[0], rphfifourstrx[0], rcmpfifourst[0], 
// 8025 - 8028                 rtx_idle_delay_ch0, rclkcmpsqmd[0], rclkcmpsq1p_ch0[9:0]};
assign rppm_cnt_reset[0]       = rxdprioin_phy_ch0[`rppm_cnt_reset_DP_RX_IDX];
assign rphfifourstrx[0]        = rxdprioin_phy_ch0[`rphfifourstrx_DP_RX_IDX];
assign rcmpfifourst[0]         = rxdprioin_phy_ch0[`rcmpfifourst_DP_RX_IDX];
assign rtx_idle_delay_ch0      = rxdprioin_phy_ch0[`rtx_idle_delay_DP_RX_IDX_1 : `rtx_idle_delay_DP_RX_IDX_0];
assign rclkcmpsqmd[0]          = rxdprioin_phy_ch0[`rclkcmpsqmd_DP_RX_IDX];
assign rclkcmpsq1p_ch0[19:0]   = rxdprioin_phy_ch0[`rclkcmpsq1p_DP_RX_IDX_19   : `rclkcmpsq1p_DP_RX_IDX_0];

assign rppm_cnt_reset[1]       = rxdprioin_phy_ch1[`rppm_cnt_reset_DP_RX_IDX];
assign rphfifourstrx[1]        = rxdprioin_phy_ch1[`rphfifourstrx_DP_RX_IDX];
assign rcmpfifourst[1]         = rxdprioin_phy_ch1[`rcmpfifourst_DP_RX_IDX];
assign rtx_idle_delay_ch1      = rxdprioin_phy_ch1[`rtx_idle_delay_DP_RX_IDX_1 : `rtx_idle_delay_DP_RX_IDX_0];
assign rclkcmpsqmd[1]          = rxdprioin_phy_ch1[`rclkcmpsqmd_DP_RX_IDX];
assign rclkcmpsq1p_ch1[19:0]   = rxdprioin_phy_ch1[`rclkcmpsq1p_DP_RX_IDX_19   : `rclkcmpsq1p_DP_RX_IDX_0];

assign rppm_cnt_reset[2]       = rxdprioin_phy_ch2[`rppm_cnt_reset_DP_RX_IDX];
assign rphfifourstrx[2]        = rxdprioin_phy_ch2[`rphfifourstrx_DP_RX_IDX];
assign rcmpfifourst[2]         = rxdprioin_phy_ch2[`rcmpfifourst_DP_RX_IDX];
assign rtx_idle_delay_ch2      = rxdprioin_phy_ch2[`rtx_idle_delay_DP_RX_IDX_1 : `rtx_idle_delay_DP_RX_IDX_0];
assign rclkcmpsqmd[2]          = rxdprioin_phy_ch2[`rclkcmpsqmd_DP_RX_IDX];
assign rclkcmpsq1p_ch2[19:0]   = rxdprioin_phy_ch2[`rclkcmpsq1p_DP_RX_IDX_19   : `rclkcmpsq1p_DP_RX_IDX_0];

assign rppm_cnt_reset[3]       = rxdprioin_phy_ch3[`rppm_cnt_reset_DP_RX_IDX];
assign rphfifourstrx[3]        = rxdprioin_phy_ch3[`rphfifourstrx_DP_RX_IDX];
assign rcmpfifourst[3]         = rxdprioin_phy_ch3[`rcmpfifourst_DP_RX_IDX];
assign rtx_idle_delay_ch3      = rxdprioin_phy_ch3[`rtx_idle_delay_DP_RX_IDX_1 : `rtx_idle_delay_DP_RX_IDX_0];
assign rclkcmpsqmd[3]          = rxdprioin_phy_ch3[`rclkcmpsqmd_DP_RX_IDX];
assign rclkcmpsq1p_ch3[19:0]   = rxdprioin_phy_ch3[`rclkcmpsq1p_DP_RX_IDX_19 : `rclkcmpsq1p_DP_RX_IDX_0];

// PCS_CTRL_10, 11
// all rx - pages 10 and 11 - 21
// 8029 - 802C
//assign  pcs_ctrl10_ch0_ext = {rclkcmpsq1n_ch0[19:15], rclkcmppos[0], rclkcmpsq1p_ch0[19:10]};
// 802D - 8030
//assign  pcs_ctrl11_ch0_ext = {rclkcmpsq1n_ch0[14:10], 1'b0, rclkcmpsq1n_ch0[9:0]};
assign rclkcmpsq1n_ch0      = rxdprioin_phy_ch0[`rclkcmpsq1n_DP_RX_IDX_19 : `rclkcmpsq1n_DP_RX_IDX_0];
assign rclkcmppos[0]        = rxdprioin_phy_ch0[`rclkcmppos_DP_RX_IDX];

assign rclkcmpsq1n_ch1      = rxdprioin_phy_ch1[`rclkcmpsq1n_DP_RX_IDX_19 : `rclkcmpsq1n_DP_RX_IDX_0];
assign rclkcmppos[1]        = rxdprioin_phy_ch1[`rclkcmppos_DP_RX_IDX];

assign rclkcmpsq1n_ch2      = rxdprioin_phy_ch2[`rclkcmpsq1n_DP_RX_IDX_19 : `rclkcmpsq1n_DP_RX_IDX_0];
assign rclkcmppos[1]        = rxdprioin_phy_ch2[`rclkcmppos_DP_RX_IDX];

assign rclkcmpsq1n_ch3      = rxdprioin_phy_ch3[`rclkcmpsq1n_DP_RX_IDX_19 : `rclkcmpsq1n_DP_RX_IDX_0];
assign rclkcmppos[3]        = rxdprioin_phy_ch3[`rclkcmppos_DP_RX_IDX];

// PCS_CTRL_12 - rx and tx mixed
// page 12 - rx: 12
//assign  pcs_ctrl12_ch0_ext = {rrev_loopbk[0], ralempty_ch0, ralfull_ch0, rforce_disp[0], 
//                              rkchar[0], rosbased[0], rensymswap_tx[0], 1'b0, rosnumber_ch0};
assign ralempty_ch0         = rxdprioin_phy_ch0[`ralempty_DP_RX_IDX_3 : `ralempty_DP_RX_IDX_0];
assign ralfull_ch0          = rxdprioin_phy_ch0[`ralfull_DP_RX_IDX_3 : `ralfull_DP_RX_IDX_0];
assign rkchar[0]            = rxdprioin_phy_ch0[`rkchar_DP_RX_IDX];
assign rosbased[0]          = rxdprioin_phy_ch0[`rosbased_DP_RX_IDX];
assign rosnumber_ch0        = rxdprioin_phy_ch0[`rosnumber_DP_RX_IDX_1 : `rosnumber_DP_RX_IDX_0];
//tx
assign rrev_loopbk[0]       = txdprioin_phy_ch0[`rrev_loopbk_DP_TX_IDX];
assign rforce_disp[0]       = txdprioin_phy_ch0[`rforce_disp_DP_TX_IDX];
assign rensymswap_tx[0]     = txdprioin_phy_ch0[`rensymswap_tx_DP_TX_IDX];

assign ralempty_ch1         = rxdprioin_phy_ch1[`ralempty_DP_RX_IDX_3 : `ralempty_DP_RX_IDX_0];
assign ralfull_ch1          = rxdprioin_phy_ch1[`ralfull_DP_RX_IDX_3 : `ralfull_DP_RX_IDX_0];
assign rkchar[1]            = rxdprioin_phy_ch1[`rkchar_DP_RX_IDX];
assign rosbased[1]          = rxdprioin_phy_ch1[`rosbased_DP_RX_IDX];
assign rosnumber_ch1        = rxdprioin_phy_ch1[`rosnumber_DP_RX_IDX_1 : `rosnumber_DP_RX_IDX_0];
//tx
assign rrev_loopbk[1]       = txdprioin_phy_ch1[`rrev_loopbk_DP_TX_IDX];
assign rforce_disp[1]       = txdprioin_phy_ch1[`rforce_disp_DP_TX_IDX];
assign rensymswap_tx[1]     = txdprioin_phy_ch1[`rensymswap_tx_DP_TX_IDX];

assign ralempty_ch2         = rxdprioin_phy_ch2[`ralempty_DP_RX_IDX_3 : `ralempty_DP_RX_IDX_0];
assign ralfull_ch2          = rxdprioin_phy_ch2[`ralfull_DP_RX_IDX_3 : `ralfull_DP_RX_IDX_0];
assign rkchar[2]            = rxdprioin_phy_ch2[`rkchar_DP_RX_IDX];
assign rosbased[2]          = rxdprioin_phy_ch2[`rosbased_DP_RX_IDX];
assign rosnumber_ch2        = rxdprioin_phy_ch2[`rosnumber_DP_RX_IDX_1 : `rosnumber_DP_RX_IDX_0];
//tx
assign rrev_loopbk[2]       = txdprioin_phy_ch2[`rrev_loopbk_DP_TX_IDX];
assign rforce_disp[2]       = txdprioin_phy_ch2[`rforce_disp_DP_TX_IDX];
assign rensymswap_tx[2]     = txdprioin_phy_ch2[`rensymswap_tx_DP_TX_IDX];

assign ralempty_ch3         = rxdprioin_phy_ch3[`ralempty_DP_RX_IDX_3 : `ralempty_DP_RX_IDX_0];
assign ralfull_ch3          = rxdprioin_phy_ch3[`ralfull_DP_RX_IDX_3 : `ralfull_DP_RX_IDX_0];
assign rkchar[3]            = rxdprioin_phy_ch3[`rkchar_DP_RX_IDX];
assign rosbased[3]          = rxdprioin_phy_ch3[`rosbased_DP_RX_IDX];
assign rosnumber_ch3        = rxdprioin_phy_ch3[`rosnumber_DP_RX_IDX_1 : `rosnumber_DP_RX_IDX_0];
//tx
assign rrev_loopbk[3]       = txdprioin_phy_ch3[`rrev_loopbk_DP_TX_IDX];
assign rforce_disp[3]       = txdprioin_phy_ch3[`rforce_disp_DP_TX_IDX];
assign rensymswap_tx[3]     = txdprioin_phy_ch3[`rensymswap_tx_DP_TX_IDX];

// PCS_CTRL_13
// rx:12
//assign  pcs_ctrl13_ch0_ext = {rwa_6g_en[0], renpolinv_tx[0], rbitslip_size_ch0, rbytord_2sym_en[0],
//                              rbysync_polinv_en[0], rbitloc_rev_en[0], rbyte_rev_en[0], renbitrev_tx[0],
//                              rbyteorden_ch0, rbytordplden[0], rphfifopldentx[0], rphfifoursttx[0],
//                              rphfifopldenrx[0], rautoinsdis[0]};
assign rwa_6g_en[0]         = rxdprioin_phy_ch0[`rwa_6g_en_DP_RX_IDX];
assign rbitslip_size_ch0    = rxdprioin_phy_ch0[`rbitslip_size_DP_RX_IDX_1 : `rbitslip_size_DP_RX_IDX_0];
assign rbytord_2sym_en[0]   = rxdprioin_phy_ch0[`rbytord_2sym_en_DP_RX_IDX];
assign rbysync_polinv_en[0] = rxdprioin_phy_ch0[`rbysync_polinv_en_DP_RX_IDX];
assign rbitloc_rev_en[0]    = rxdprioin_phy_ch0[`rbitloc_rev_en_DP_RX_IDX];
assign rbyte_rev_en[0]      = rxdprioin_phy_ch0[`rbyte_rev_en_DP_RX_IDX];
assign rbyteorden_ch0       = rxdprioin_phy_ch0[`rbyteorden_DP_RX_IDX_1 : `rbyteorden_DP_RX_IDX_0];
assign rbytordplden[0]      = rxdprioin_phy_ch0[`rbytordplden_DP_RX_IDX];
assign rphfifopldenrx[0]    = rxdprioin_phy_ch0[`rphfifopldenrx_DP_RX_IDX];
assign rautoinsdis[0]       = rxdprioin_phy_ch0[`rautoinsdis_DP_RX_IDX];
//tx
assign renpolinv_tx[0]      = txdprioin_phy_ch0[`renpolinv_tx_DP_TX_IDX];
assign renbitrev_tx[0]      = txdprioin_phy_ch0[`renbitrev_tx_DP_TX_IDX];
assign rphfifopldentx[0]    = txdprioin_phy_ch0[`rphfifopldentx_DP_TX_IDX];
assign rphfifoursttx[0]     = txdprioin_phy_ch0[`rphfifoursttx_DP_TX_IDX];

assign rwa_6g_en[1]         = rxdprioin_phy_ch1[`rwa_6g_en_DP_RX_IDX];
assign rbitslip_size_ch1    = rxdprioin_phy_ch1[`rbitslip_size_DP_RX_IDX_1 : `rbitslip_size_DP_RX_IDX_0];
assign rbytord_2sym_en[1]   = rxdprioin_phy_ch1[`rbytord_2sym_en_DP_RX_IDX];
assign rbysync_polinv_en[1] = rxdprioin_phy_ch1[`rbysync_polinv_en_DP_RX_IDX];
assign rbitloc_rev_en[1]    = rxdprioin_phy_ch1[`rbitloc_rev_en_DP_RX_IDX];
assign rbyte_rev_en[1]      = rxdprioin_phy_ch1[`rbyte_rev_en_DP_RX_IDX];
assign rbyteorden_ch1       = rxdprioin_phy_ch1[`rbyteorden_DP_RX_IDX_1 : `rbyteorden_DP_RX_IDX_0];
assign rbytordplden[1]      = rxdprioin_phy_ch1[`rbytordplden_DP_RX_IDX];
assign rphfifopldenrx[1]    = rxdprioin_phy_ch1[`rphfifopldenrx_DP_RX_IDX];
assign rautoinsdis[1]       = rxdprioin_phy_ch1[`rautoinsdis_DP_RX_IDX];
//tx
assign renpolinv_tx[1]      = txdprioin_phy_ch1[`renpolinv_tx_DP_TX_IDX];
assign renbitrev_tx[1]      = txdprioin_phy_ch1[`renbitrev_tx_DP_TX_IDX];
assign rphfifopldentx[1]    = txdprioin_phy_ch1[`rphfifopldentx_DP_TX_IDX];
assign rphfifoursttx[1]     = txdprioin_phy_ch1[`rphfifoursttx_DP_TX_IDX];

assign rwa_6g_en[2]         = rxdprioin_phy_ch2[`rwa_6g_en_DP_RX_IDX];
assign rbitslip_size_ch2    = rxdprioin_phy_ch2[`rbitslip_size_DP_RX_IDX_1 : `rbitslip_size_DP_RX_IDX_0];
assign rbytord_2sym_en[2]   = rxdprioin_phy_ch2[`rbytord_2sym_en_DP_RX_IDX];
assign rbysync_polinv_en[2] = rxdprioin_phy_ch2[`rbysync_polinv_en_DP_RX_IDX];
assign rbitloc_rev_en[2]    = rxdprioin_phy_ch2[`rbitloc_rev_en_DP_RX_IDX];
assign rbyte_rev_en[2]      = rxdprioin_phy_ch2[`rbyte_rev_en_DP_RX_IDX];
assign rbyteorden_ch2       = rxdprioin_phy_ch2[`rbyteorden_DP_RX_IDX_1 : `rbyteorden_DP_RX_IDX_0];
assign rbytordplden[2]      = rxdprioin_phy_ch2[`rbytordplden_DP_RX_IDX];
assign rphfifopldenrx[2]    = rxdprioin_phy_ch2[`rphfifopldenrx_DP_RX_IDX];
assign rautoinsdis[2]       = rxdprioin_phy_ch2[`rautoinsdis_DP_RX_IDX];
//tx
assign renpolinv_tx[2]      = txdprioin_phy_ch2[`renpolinv_tx_DP_TX_IDX];
assign renbitrev_tx[2]      = txdprioin_phy_ch2[`renbitrev_tx_DP_TX_IDX];
assign rphfifopldentx[2]    = txdprioin_phy_ch2[`rphfifopldentx_DP_TX_IDX];
assign rphfifoursttx[2]     = txdprioin_phy_ch2[`rphfifoursttx_DP_TX_IDX];

assign rwa_6g_en[3]         = rxdprioin_phy_ch3[`rwa_6g_en_DP_RX_IDX];
assign rbitslip_size_ch3    = rxdprioin_phy_ch3[`rbitslip_size_DP_RX_IDX_1 : `rbitslip_size_DP_RX_IDX_0];
assign rbytord_2sym_en[3]   = rxdprioin_phy_ch3[`rbytord_2sym_en_DP_RX_IDX];
assign rbysync_polinv_en[3] = rxdprioin_phy_ch3[`rbysync_polinv_en_DP_RX_IDX];
assign rbitloc_rev_en[3]    = rxdprioin_phy_ch3[`rbitloc_rev_en_DP_RX_IDX];
assign rbyte_rev_en[3]      = rxdprioin_phy_ch3[`rbyte_rev_en_DP_RX_IDX];
assign rbyteorden_ch3       = rxdprioin_phy_ch3[`rbyteorden_DP_RX_IDX_1 : `rbyteorden_DP_RX_IDX_0];
assign rbytordplden[3]      = rxdprioin_phy_ch3[`rbytordplden_DP_RX_IDX];
assign rphfifopldenrx[3]    = rxdprioin_phy_ch3[`rphfifopldenrx_DP_RX_IDX];
assign rautoinsdis[3]       = rxdprioin_phy_ch3[`rautoinsdis_DP_RX_IDX];
//tx
assign renpolinv_tx[3]      = txdprioin_phy_ch3[`renpolinv_tx_DP_TX_IDX];
assign renbitrev_tx[3]      = txdprioin_phy_ch3[`renbitrev_tx_DP_TX_IDX];
assign rphfifopldentx[3]    = txdprioin_phy_ch3[`rphfifopldentx_DP_TX_IDX];
assign rphfifoursttx[3]     = txdprioin_phy_ch3[`rphfifoursttx_DP_TX_IDX];

// PCS_CTRL_14
// all rx
//assign  pcs_ctrl14_ch0_ext = {rppmsel_ch0, rbytordpat_ch0};
assign rppmsel_ch0          = rxdprioin_phy_ch0[`rppmsel_DP_RX_IDX_5 : `rppmsel_DP_RX_IDX_0];
assign rbytordpat_ch0       = rxdprioin_phy_ch0[`rbytordpat_DP_RX_IDX_9 : `rbytordpat_DP_RX_IDX_0];
assign rppmsel_ch1          = rxdprioin_phy_ch1[`rppmsel_DP_RX_IDX_5 : `rppmsel_DP_RX_IDX_0];
assign rbytordpat_ch1       = rxdprioin_phy_ch1[`rbytordpat_DP_RX_IDX_9 : `rbytordpat_DP_RX_IDX_0];
assign rppmsel_ch2          = rxdprioin_phy_ch2[`rppmsel_DP_RX_IDX_5 : `rppmsel_DP_RX_IDX_0];
assign rbytordpat_ch2       = rxdprioin_phy_ch2[`rbytordpat_DP_RX_IDX_9 : `rbytordpat_DP_RX_IDX_0];
assign rppmsel_ch3          = rxdprioin_phy_ch3[`rppmsel_DP_RX_IDX_5 : `rppmsel_DP_RX_IDX_0];
assign rbytordpat_ch3       = rxdprioin_phy_ch3[`rbytordpat_DP_RX_IDX_9 : `rbytordpat_DP_RX_IDX_0];

// PCS_CTRL_15
//assign  pcs_ctrl15_ch0_ext = {rtest_bus_sel_ch0, rforce_sig_det_pcs[0], rforce0_freqdet[0], 
//                              rforce1_freqdet[0], rbytordpad_ch0};
assign rtest_bus_sel_ch0    = 3'b000;
assign rforce_sig_det_pcs[0]= rxdprioin_phy_ch0[`rforce_sig_det_pcs_DP_RX_IDX];
assign rforce0_freqdet[0]   = rxdprioin_phy_ch0[`rforce0_freqdet_DP_RX_IDX];
assign rforce1_freqdet[0]   = rxdprioin_phy_ch0[`rforce1_freqdet_DP_RX_IDX];
assign rbytordpad_ch0       = rxdprioin_phy_ch0[`rbytordpad_DP_RX_IDX_9 : `rbytordpad_DP_RX_IDX_0];

assign rtest_bus_sel_ch1    = 3'b000;
assign rforce_sig_det_pcs[1]= rxdprioin_phy_ch1[`rforce_sig_det_pcs_DP_RX_IDX];
assign rforce0_freqdet[1]   = rxdprioin_phy_ch1[`rforce0_freqdet_DP_RX_IDX];
assign rforce1_freqdet[1]   = rxdprioin_phy_ch1[`rforce1_freqdet_DP_RX_IDX];
assign rbytordpad_ch1       = rxdprioin_phy_ch1[`rbytordpad_DP_RX_IDX_9 : `rbytordpad_DP_RX_IDX_0];

assign rtest_bus_sel_ch2    = 3'b000;
assign rforce_sig_det_pcs[2]= rxdprioin_phy_ch2[`rforce_sig_det_pcs_DP_RX_IDX];
assign rforce0_freqdet[2]   = rxdprioin_phy_ch2[`rforce0_freqdet_DP_RX_IDX];
assign rforce1_freqdet[2]   = rxdprioin_phy_ch2[`rforce1_freqdet_DP_RX_IDX];
assign rbytordpad_ch2       = rxdprioin_phy_ch2[`rbytordpad_DP_RX_IDX_9 : `rbytordpad_DP_RX_IDX_0];

assign rtest_bus_sel_ch3    = 3'b000;
assign rforce_sig_det_pcs[3]= rxdprioin_phy_ch3[`rforce_sig_det_pcs_DP_RX_IDX];
assign rforce0_freqdet[3]   = rxdprioin_phy_ch3[`rforce0_freqdet_DP_RX_IDX];
assign rforce1_freqdet[3]   = rxdprioin_phy_ch3[`rforce1_freqdet_DP_RX_IDX];
assign rbytordpad_ch3       = rxdprioin_phy_ch3[`rbytordpad_DP_RX_IDX_9 : `rbytordpad_DP_RX_IDX_0];

// pcs_ctrl in to add

// PCS output -----------------------------------------------------------------------------

// PCS Trunking 
assign rxdprioout_phy_ch0[`rphfifo_master_sel_rx_DP_RX_IDX]   = rphfifo_master_sel_rx_int;
assign rxdprioout_phy_ch1[`rphfifo_master_sel_rx_DP_RX_IDX]   = rphfifo_master_sel_rx_int;
assign rxdprioout_phy_ch2[`rphfifo_master_sel_rx_DP_RX_IDX]   = rphfifo_master_sel_rx_int;
assign rxdprioout_phy_ch3[`rphfifo_master_sel_rx_DP_RX_IDX]   = rphfifo_master_sel_rx_int;
assign rxdprioout_phy_ch0[`rendec_data_sel_rx_DP_RX_IDX]      = rendec_data_sel_rx_int;
assign rxdprioout_phy_ch1[`rendec_data_sel_rx_DP_RX_IDX]      = rendec_data_sel_rx_int;
assign rxdprioout_phy_ch2[`rendec_data_sel_rx_DP_RX_IDX]      = rendec_data_sel_rx_int;
assign rxdprioout_phy_ch3[`rendec_data_sel_rx_DP_RX_IDX]      = rendec_data_sel_rx_int;
assign rxdprioout_phy_ch0[`rindv_rx_DP_RX_IDX]                = rindv_rx_int;
assign rxdprioout_phy_ch1[`rindv_rx_DP_RX_IDX]                = rindv_rx_int;
assign rxdprioout_phy_ch2[`rindv_rx_DP_RX_IDX]                = rindv_rx_int;
assign rxdprioout_phy_ch3[`rindv_rx_DP_RX_IDX]                = rindv_rx_int;
//tx
assign txdprioout_phy_ch0[`rphfifo_master_sel_tx_DP_TX_IDX]   = rphfifo_master_sel_tx_int;
assign txdprioout_phy_ch1[`rphfifo_master_sel_tx_DP_TX_IDX]   = rphfifo_master_sel_tx_int;
assign txdprioout_phy_ch2[`rphfifo_master_sel_tx_DP_TX_IDX]   = rphfifo_master_sel_tx_int;
assign txdprioout_phy_ch3[`rphfifo_master_sel_tx_DP_TX_IDX]   = rphfifo_master_sel_tx_int;
assign txdprioout_phy_ch0[`rendec_data_sel_tx_DP_TX_IDX]      = rendec_data_sel_tx_int;
assign txdprioout_phy_ch1[`rendec_data_sel_tx_DP_TX_IDX]      = rendec_data_sel_tx_int;
assign txdprioout_phy_ch2[`rendec_data_sel_tx_DP_TX_IDX]      = rendec_data_sel_tx_int;
assign txdprioout_phy_ch3[`rendec_data_sel_tx_DP_TX_IDX]      = rendec_data_sel_tx_int;
assign txdprioout_phy_ch0[`rindv_tx_DP_TX_IDX]                = rindv_tx_int;
assign txdprioout_phy_ch1[`rindv_tx_DP_TX_IDX]                = rindv_tx_int;
assign txdprioout_phy_ch2[`rindv_tx_DP_TX_IDX]                = rindv_tx_int;
assign txdprioout_phy_ch3[`rindv_tx_DP_TX_IDX]                = rindv_tx_int;

// PCS_CTRL1 - mix of RX and TX
assign txdprioout_phy_ch0[`rtx_pipe_enable_DP_TX_IDX]   = rtx_pipe_enable_int[0];
assign rxdprioout_phy_ch0[`rrx_pipe_enable_DP_RX_IDX]   = rrx_pipe_enable_int[0];
assign txdprioout_phy_ch0[`rpowdnt_DP_TX_IDX]           = rpowdnt_md[0];
assign rxdprioout_phy_ch0[`rpowdnr_DP_RX_IDX]           = rpowdnr_md[0];
assign txdprioout_phy_ch0[`rendec_tx_DP_TX_IDX]         = rendec_tx_int[0];
assign rxdprioout_phy_ch0[`rendec_rx_DP_RX_IDX]         = rendec_rx_int[0];
assign txdprioout_phy_ch0[`r8b10b_enc_ibm_en_DP_TX_IDX] = r8b10b_enc_ibm_en_int[0];
assign rxdprioout_phy_ch0[`rmatchen_DP_RX_IDX]          = rmatchen_int[0];
assign rxdprioout_phy_ch0[`r8b10b_dec_ibm_en_DP_RX_IDX_1 : `r8b10b_dec_ibm_en_DP_RX_IDX_0] = r8b10b_dec_ibm_en_ch0_int;
assign txdprioout_phy_ch0[`rforce_kchar_DP_TX_IDX]      = rforce_kchar_int[0];
assign txdprioout_phy_ch0[`rforce_echar_DP_TX_IDX]      = rforce_echar_int[0];
assign rxdprioout_phy_ch0[`rlp20ben_DP_RX_IDX]          = rlp20ben_int[0];
assign rxdprioout_phy_ch0[`rgenericfifo_DP_RX_IDX]      = rgenericfifo_int[0];
assign txdprioout_phy_ch0[`rcascaded_8b10b_en_tx_DP_TX_IDX] = rcascaded_8b10b_en_tx_int[0];
assign rxdprioout_phy_ch0[`rcascaded_8b10b_en_rx_DP_RX_IDX] = rcascaded_8b10b_en_rx_int[0];

assign txdprioout_phy_ch1[`rtx_pipe_enable_DP_TX_IDX]   = rtx_pipe_enable_int[1];
assign rxdprioout_phy_ch1[`rrx_pipe_enable_DP_RX_IDX]   = rrx_pipe_enable_int[1];
assign txdprioout_phy_ch1[`rpowdnt_DP_TX_IDX]           = rpowdnt_md[1];
assign rxdprioout_phy_ch1[`rpowdnr_DP_RX_IDX]           = rpowdnr_md[1];
assign txdprioout_phy_ch1[`rendec_tx_DP_TX_IDX]         = rendec_tx_int[1];
assign rxdprioout_phy_ch1[`rendec_rx_DP_RX_IDX]         = rendec_rx_int[1];
assign txdprioout_phy_ch1[`r8b10b_enc_ibm_en_DP_TX_IDX] = r8b10b_enc_ibm_en_int[1];
assign rxdprioout_phy_ch1[`rmatchen_DP_RX_IDX]          = rmatchen_int[1];
assign rxdprioout_phy_ch1[`r8b10b_dec_ibm_en_DP_RX_IDX_1 : `r8b10b_dec_ibm_en_DP_RX_IDX_0] = r8b10b_dec_ibm_en_ch1_int;
assign txdprioout_phy_ch1[`rforce_kchar_DP_TX_IDX]      = rforce_kchar_int[1];
assign txdprioout_phy_ch1[`rforce_echar_DP_TX_IDX]      = rforce_echar_int[1];
assign rxdprioout_phy_ch1[`rlp20ben_DP_RX_IDX]          = rlp20ben_int[1];
assign rxdprioout_phy_ch1[`rgenericfifo_DP_RX_IDX]      = rgenericfifo_int[1];
assign txdprioout_phy_ch1[`rcascaded_8b10b_en_tx_DP_TX_IDX] = rcascaded_8b10b_en_tx_int[1];
assign rxdprioout_phy_ch1[`rcascaded_8b10b_en_rx_DP_RX_IDX] = rcascaded_8b10b_en_rx_int[1];

assign txdprioout_phy_ch2[`rtx_pipe_enable_DP_TX_IDX]   = rtx_pipe_enable_int[2];
assign rxdprioout_phy_ch2[`rrx_pipe_enable_DP_RX_IDX]   = rrx_pipe_enable_int[2];
assign txdprioout_phy_ch2[`rpowdnt_DP_TX_IDX]           = rpowdnt_md[2];
assign rxdprioout_phy_ch2[`rpowdnr_DP_RX_IDX]           = rpowdnr_md[2];
assign txdprioout_phy_ch2[`rendec_tx_DP_TX_IDX]         = rendec_tx_int[2];
assign rxdprioout_phy_ch2[`rendec_rx_DP_RX_IDX]         = rendec_rx_int[2];
assign txdprioout_phy_ch2[`r8b10b_enc_ibm_en_DP_TX_IDX] = r8b10b_enc_ibm_en_int[2];
assign rxdprioout_phy_ch2[`rmatchen_DP_RX_IDX]          = rmatchen_int[2];
assign rxdprioout_phy_ch2[`r8b10b_dec_ibm_en_DP_RX_IDX_1 : `r8b10b_dec_ibm_en_DP_RX_IDX_0] = r8b10b_dec_ibm_en_ch2_int;
assign txdprioout_phy_ch2[`rforce_kchar_DP_TX_IDX]      = rforce_kchar_int[2];
assign txdprioout_phy_ch2[`rforce_echar_DP_TX_IDX]      = rforce_echar_int[2];
assign rxdprioout_phy_ch2[`rlp20ben_DP_RX_IDX]          = rlp20ben_int[2];
assign rxdprioout_phy_ch2[`rgenericfifo_DP_RX_IDX]      = rgenericfifo_int[2];
assign txdprioout_phy_ch2[`rcascaded_8b10b_en_tx_DP_TX_IDX] = rcascaded_8b10b_en_tx_int[2];
assign rxdprioout_phy_ch2[`rcascaded_8b10b_en_rx_DP_RX_IDX] = rcascaded_8b10b_en_rx_int[2];

assign txdprioout_phy_ch3[`rtx_pipe_enable_DP_TX_IDX]   = rtx_pipe_enable_int[3];
assign rxdprioout_phy_ch3[`rrx_pipe_enable_DP_RX_IDX]   = rrx_pipe_enable_int[3];
assign txdprioout_phy_ch3[`rpowdnt_DP_TX_IDX]           = rpowdnt_md[3];
assign rxdprioout_phy_ch3[`rpowdnr_DP_RX_IDX]           = rpowdnr_md[3];
assign txdprioout_phy_ch3[`rendec_tx_DP_TX_IDX]         = rendec_tx_int[3];
assign rxdprioout_phy_ch3[`rendec_rx_DP_RX_IDX]         = rendec_rx_int[3];
assign txdprioout_phy_ch3[`r8b10b_enc_ibm_en_DP_TX_IDX] = r8b10b_enc_ibm_en_int[3];
assign rxdprioout_phy_ch3[`rmatchen_DP_RX_IDX]          = rmatchen_int[3];
assign rxdprioout_phy_ch3[`r8b10b_dec_ibm_en_DP_RX_IDX_1 : `r8b10b_dec_ibm_en_DP_RX_IDX_0] = r8b10b_dec_ibm_en_ch3_int;
assign txdprioout_phy_ch3[`rforce_kchar_DP_TX_IDX]      = rforce_kchar_int[3];
assign txdprioout_phy_ch3[`rforce_echar_DP_TX_IDX]      = rforce_echar_int[3];
assign rxdprioout_phy_ch3[`rlp20ben_DP_RX_IDX]          = rlp20ben_int[3];
assign rxdprioout_phy_ch3[`rgenericfifo_DP_RX_IDX]      = rgenericfifo_int[3];
assign txdprioout_phy_ch3[`rcascaded_8b10b_en_tx_DP_TX_IDX] = rcascaded_8b10b_en_tx_int[3];
assign rxdprioout_phy_ch3[`rcascaded_8b10b_en_rx_DP_RX_IDX] = rcascaded_8b10b_en_rx_int[3];

// PCS_CTRL2 (part) - all RX
assign rxdprioout_phy_ch0[`rencdt_rising_DP_RX_IDX]     =  rencdt_rising_int[0]; 
assign rxdprioout_phy_ch0[`rdis_rx_disp_DP_RX_IDX]      =  rdis_rx_disp_int[0];
assign rxdprioout_phy_ch0[`rcomp_pat_porn_DP_RX_IDX]    =  rcomp_pat_porn_int[0]; 
assign rxdprioout_phy_ch1[`rencdt_rising_DP_RX_IDX]     =  rencdt_rising_int[1]; 
assign rxdprioout_phy_ch1[`rdis_rx_disp_DP_RX_IDX]      =  rdis_rx_disp_int[1];
assign rxdprioout_phy_ch1[`rcomp_pat_porn_DP_RX_IDX]    =  rcomp_pat_porn_int[1]; 
assign rxdprioout_phy_ch2[`rencdt_rising_DP_RX_IDX]     =  rencdt_rising_int[2]; 
assign rxdprioout_phy_ch2[`rdis_rx_disp_DP_RX_IDX]      =  rdis_rx_disp_int[2];
assign rxdprioout_phy_ch2[`rcomp_pat_porn_DP_RX_IDX]    =  rcomp_pat_porn_int[2]; 
assign rxdprioout_phy_ch3[`rencdt_rising_DP_RX_IDX]     =  rencdt_rising_int[3]; 
assign rxdprioout_phy_ch3[`rdis_rx_disp_DP_RX_IDX]      =  rdis_rx_disp_int[3];
assign rxdprioout_phy_ch3[`rcomp_pat_porn_DP_RX_IDX]    =  rcomp_pat_porn_int[3]; 

// PCS_CTRL2 (part), PCS_CTRL3, PCS_CTRL4
assign rxdprioout_phy_ch0[`rcomp_size_DP_RX_IDX_2 : `rcomp_size_DP_RX_IDX_0] =  rcomp_size_ch0_int;
assign rxdprioout_phy_ch0[`rcomp_pat_DP_RX_IDX_39 : `rcomp_pat_DP_RX_IDX_0]  =  rcomp_pat_ch0_int;
assign rxdprioout_phy_ch1[`rcomp_size_DP_RX_IDX_2 : `rcomp_size_DP_RX_IDX_0] =  rcomp_size_ch1_int;
assign rxdprioout_phy_ch1[`rcomp_pat_DP_RX_IDX_39 : `rcomp_pat_DP_RX_IDX_0]  =  rcomp_pat_ch1_int;
assign rxdprioout_phy_ch2[`rcomp_size_DP_RX_IDX_2 : `rcomp_size_DP_RX_IDX_0] =  rcomp_size_ch2_int;
assign rxdprioout_phy_ch2[`rcomp_pat_DP_RX_IDX_39 : `rcomp_pat_DP_RX_IDX_0]  =  rcomp_pat_ch2_int;
assign rxdprioout_phy_ch3[`rcomp_size_DP_RX_IDX_2 : `rcomp_size_DP_RX_IDX_0] =  rcomp_size_ch3_int;
assign rxdprioout_phy_ch3[`rcomp_pat_DP_RX_IDX_39 : `rcomp_pat_DP_RX_IDX_0]  =  rcomp_pat_ch3_int;

// PCS_CTRL5 - mix of RX and TX
assign rxdprioout_phy_ch0[`rrxfifo_dis_DP_RX_IDX]           =  rrxfifo_dis_int[0]; 
assign rxdprioout_phy_ch0[`rrundisp_DP_RX_IDX_5 : `rrundisp_DP_RX_IDX_0] =  rrundisp_ch0_int; 
assign rxdprioout_phy_ch0[`rrlv_en_DP_RX_IDX]               =  rrlv_en_int[0]; 
assign rxdprioout_phy_ch0[`rautobtalg_dis_DP_RX_IDX]        =  rautobtalg_dis_int[0];
assign rxdprioout_phy_ch0[`rsync_sm_dis_DP_RX_IDX]          =  rsync_sm_dis_int[0]; 
assign rxdprioout_phy_ch0[`rib_inv_cd_DP_RX_IDX_1 : `rib_inv_cd_DP_RX_IDX_0] =  rib_inv_cd_ch0_int; 
assign rxdprioout_phy_ch0[`rrxfifo_lowlatency_en_DP_RX_IDX] =  rrxfifo_lowlatency_en_int[0];
// tx
assign txdprioout_phy_ch0[`rtxfifo_dis_DP_TX_IDX]           = rtxfifo_dis_int[0]; 
assign txdprioout_phy_ch0[`rib_force_disp_DP_TX_IDX]        = rib_force_disp_int[0];                 
assign txdprioout_phy_ch0[`rtxfifo_lowlatency_en_DP_TX_IDX] = rtxfifo_lowlatency_en_int[0];

assign rxdprioout_phy_ch1[`rrxfifo_dis_DP_RX_IDX]           =  rrxfifo_dis_int[1]; 
assign rxdprioout_phy_ch1[`rrundisp_DP_RX_IDX_5 : `rrundisp_DP_RX_IDX_0] =  rrundisp_ch1_int; 
assign rxdprioout_phy_ch1[`rrlv_en_DP_RX_IDX]               =  rrlv_en_int[1]; 
assign rxdprioout_phy_ch1[`rautobtalg_dis_DP_RX_IDX]        =  rautobtalg_dis_int[1];
assign rxdprioout_phy_ch1[`rsync_sm_dis_DP_RX_IDX]          =  rsync_sm_dis_int[1]; 
assign rxdprioout_phy_ch1[`rib_inv_cd_DP_RX_IDX_1 : `rib_inv_cd_DP_RX_IDX_0] =  rib_inv_cd_ch1_int; 
assign rxdprioout_phy_ch1[`rrxfifo_lowlatency_en_DP_RX_IDX] =  rrxfifo_lowlatency_en_int[1];
// tx
assign txdprioout_phy_ch1[`rtxfifo_dis_DP_TX_IDX]           = rtxfifo_dis_int[1]; 
assign txdprioout_phy_ch1[`rib_force_disp_DP_TX_IDX]        = rib_force_disp_int[1];                 
assign txdprioout_phy_ch1[`rtxfifo_lowlatency_en_DP_TX_IDX] = rtxfifo_lowlatency_en_int[1];

assign rxdprioout_phy_ch2[`rrxfifo_dis_DP_RX_IDX]           =  rrxfifo_dis_int[2]; 
assign rxdprioout_phy_ch2[`rrundisp_DP_RX_IDX_5 : `rrundisp_DP_RX_IDX_0] =  rrundisp_ch2_int; 
assign rxdprioout_phy_ch2[`rrlv_en_DP_RX_IDX]               =  rrlv_en_int[2]; 
assign rxdprioout_phy_ch2[`rautobtalg_dis_DP_RX_IDX]        =  rautobtalg_dis_int[2];
assign rxdprioout_phy_ch2[`rsync_sm_dis_DP_RX_IDX]          =  rsync_sm_dis_int[2]; 
assign rxdprioout_phy_ch2[`rib_inv_cd_DP_RX_IDX_1 : `rib_inv_cd_DP_RX_IDX_0] =  rib_inv_cd_ch2_int; 
assign rxdprioout_phy_ch2[`rrxfifo_lowlatency_en_DP_RX_IDX] =  rrxfifo_lowlatency_en_int[2];
// tx
assign txdprioout_phy_ch2[`rtxfifo_dis_DP_TX_IDX]           = rtxfifo_dis_int[2]; 
assign txdprioout_phy_ch2[`rib_force_disp_DP_TX_IDX]        = rib_force_disp_int[2];                 
assign txdprioout_phy_ch2[`rtxfifo_lowlatency_en_DP_TX_IDX] = rtxfifo_lowlatency_en_int[2];

assign rxdprioout_phy_ch3[`rrxfifo_dis_DP_RX_IDX]           =  rrxfifo_dis_int[3]; 
assign rxdprioout_phy_ch3[`rrundisp_DP_RX_IDX_5 : `rrundisp_DP_RX_IDX_0] =  rrundisp_ch3_int; 
assign rxdprioout_phy_ch3[`rrlv_en_DP_RX_IDX]               =  rrlv_en_int[3]; 
assign rxdprioout_phy_ch3[`rautobtalg_dis_DP_RX_IDX]        =  rautobtalg_dis_int[3];
assign rxdprioout_phy_ch3[`rsync_sm_dis_DP_RX_IDX]          =  rsync_sm_dis_int[3]; 
assign rxdprioout_phy_ch3[`rib_inv_cd_DP_RX_IDX_1 : `rib_inv_cd_DP_RX_IDX_0] =  rib_inv_cd_ch3_int; 
assign rxdprioout_phy_ch3[`rrxfifo_lowlatency_en_DP_RX_IDX] =  rrxfifo_lowlatency_en_int[3];
// tx
assign txdprioout_phy_ch3[`rtxfifo_dis_DP_TX_IDX]           = rtxfifo_dis_int[3]; 
assign txdprioout_phy_ch3[`rib_force_disp_DP_TX_IDX]        = rib_force_disp_int[3];                 
assign txdprioout_phy_ch3[`rtxfifo_lowlatency_en_DP_TX_IDX] = rtxfifo_lowlatency_en_int[3];

// PCS_CTRL6 - mix of RX and TX
assign txdprioout_phy_ch0[`rdwidth_tx_DP_TX_IDX]        = rdwidth_tx_int[0];
assign rxdprioout_phy_ch0[`rdwidth_rx_DP_RX_IDX]        = rdwidth_rx_int[0];
assign txdprioout_phy_ch0[`rge_xaui_tx_DP_TX_IDX]       = rge_xaui_tx_int[0];
assign rxdprioout_phy_ch0[`rrx_detect_bypass_DP_RX_IDX] = rrx_detect_bypass_int[0];
assign txdprioout_phy_ch0[`rtxurstpcs_DP_TX_IDX]        = rtxurstpcs_md[0];
assign rxdprioout_phy_ch0[`rrxurstpcs_DP_RX_IDX]        = rrxurstpcs_md[0];
assign txdprioout_phy_ch0[`rrsvd_tx_DP_TX_IDX_4 : `rrsvd_tx_DP_TX_IDX_0] = rrsvd_tx_ch0_int; 
assign rxdprioout_phy_ch0[`rskpsetbased_DP_RX_IDX]      = rskpsetbased_int[0];
assign rxdprioout_phy_ch0[`rtruebac2bac_DP_RX_IDX]      = rtruebac2bac_int[0];
assign rxdprioout_phy_ch0[`rrsvd_rx_DP_RX_IDX_2 : `rrsvd_rx_DP_RX_IDX_0] = rrsvd_rx_ch0_int; 

assign txdprioout_phy_ch1[`rdwidth_tx_DP_TX_IDX]        = rdwidth_tx_int[1];
assign rxdprioout_phy_ch1[`rdwidth_rx_DP_RX_IDX]        = rdwidth_rx_int[1];
assign txdprioout_phy_ch1[`rge_xaui_tx_DP_TX_IDX]       = rge_xaui_tx_int[1];
assign rxdprioout_phy_ch1[`rrx_detect_bypass_DP_RX_IDX] = rrx_detect_bypass_int[1];
assign txdprioout_phy_ch1[`rtxurstpcs_DP_TX_IDX]        = rtxurstpcs_md[1];
assign rxdprioout_phy_ch1[`rrxurstpcs_DP_RX_IDX]        = rrxurstpcs_md[1];
assign txdprioout_phy_ch1[`rrsvd_tx_DP_TX_IDX_4 : `rrsvd_tx_DP_TX_IDX_0] = rrsvd_tx_ch1_int; 
assign rxdprioout_phy_ch1[`rskpsetbased_DP_RX_IDX]      = rskpsetbased_int[1];
assign rxdprioout_phy_ch1[`rtruebac2bac_DP_RX_IDX]      = rtruebac2bac_int[1];
assign rxdprioout_phy_ch1[`rrsvd_rx_DP_RX_IDX_2 : `rrsvd_rx_DP_RX_IDX_0] = rrsvd_rx_ch1_int; 

assign txdprioout_phy_ch2[`rdwidth_tx_DP_TX_IDX]        = rdwidth_tx_int[2];
assign rxdprioout_phy_ch2[`rdwidth_rx_DP_RX_IDX]        = rdwidth_rx_int[2];
assign txdprioout_phy_ch2[`rge_xaui_tx_DP_TX_IDX]       = rge_xaui_tx_int[2];
assign rxdprioout_phy_ch2[`rrx_detect_bypass_DP_RX_IDX] = rrx_detect_bypass_int[2];
assign txdprioout_phy_ch2[`rtxurstpcs_DP_TX_IDX]        = rtxurstpcs_md[2];
assign rxdprioout_phy_ch2[`rrxurstpcs_DP_RX_IDX]        = rrxurstpcs_md[2];
assign txdprioout_phy_ch2[`rrsvd_tx_DP_TX_IDX_4 : `rrsvd_tx_DP_TX_IDX_0] = rrsvd_tx_ch2_int; 
assign rxdprioout_phy_ch2[`rskpsetbased_DP_RX_IDX]      = rskpsetbased_int[2];
assign rxdprioout_phy_ch2[`rtruebac2bac_DP_RX_IDX]      = rtruebac2bac_int[2];
assign rxdprioout_phy_ch2[`rrsvd_rx_DP_RX_IDX_2 : `rrsvd_rx_DP_RX_IDX_0] = rrsvd_rx_ch2_int; 

assign txdprioout_phy_ch3[`rdwidth_tx_DP_TX_IDX]        = rdwidth_tx_int[3];
assign rxdprioout_phy_ch3[`rdwidth_rx_DP_RX_IDX]        = rdwidth_rx_int[3];
assign txdprioout_phy_ch3[`rge_xaui_tx_DP_TX_IDX]       = rge_xaui_tx_int[3];
assign rxdprioout_phy_ch3[`rrx_detect_bypass_DP_RX_IDX] = rrx_detect_bypass_int[3];
assign txdprioout_phy_ch3[`rtxurstpcs_DP_TX_IDX]        = rtxurstpcs_md[3];
assign rxdprioout_phy_ch3[`rrxurstpcs_DP_RX_IDX]        = rrxurstpcs_md[3];
assign txdprioout_phy_ch3[`rrsvd_tx_DP_TX_IDX_4 : `rrsvd_tx_DP_TX_IDX_0] = rrsvd_tx_ch3_int; 
assign rxdprioout_phy_ch3[`rskpsetbased_DP_RX_IDX]      = rskpsetbased_int[3];
assign rxdprioout_phy_ch3[`rtruebac2bac_DP_RX_IDX]      = rtruebac2bac_int[3];
assign rxdprioout_phy_ch3[`rrsvd_rx_DP_RX_IDX_2 : `rrsvd_rx_DP_RX_IDX_0] = rrsvd_rx_ch3_int; 

// PCS_CTRL7 - all RX
assign rxdprioout_phy_ch0[`rgnumber_DP_RX_IDX_7 : `rgnumber_DP_RX_IDX_0] = rgnumber_ch0_int; 
assign rxdprioout_phy_ch1[`rgnumber_DP_RX_IDX_7 : `rgnumber_DP_RX_IDX_0] = rgnumber_ch1_int; 
assign rxdprioout_phy_ch2[`rgnumber_DP_RX_IDX_7 : `rgnumber_DP_RX_IDX_0] = rgnumber_ch2_int; 
assign rxdprioout_phy_ch3[`rgnumber_DP_RX_IDX_7 : `rgnumber_DP_RX_IDX_0] = rgnumber_ch3_int; 
assign rxdprioout_phy_ch0[`rknumber_DP_RX_IDX_7 : `rknumber_DP_RX_IDX_0] = rknumber_ch0_int; 
assign rxdprioout_phy_ch1[`rknumber_DP_RX_IDX_7 : `rknumber_DP_RX_IDX_0] = rknumber_ch1_int; 
assign rxdprioout_phy_ch2[`rknumber_DP_RX_IDX_7 : `rknumber_DP_RX_IDX_0] = rknumber_ch2_int; 
assign rxdprioout_phy_ch3[`rknumber_DP_RX_IDX_7 : `rknumber_DP_RX_IDX_0] = rknumber_ch3_int; 

// PCS_CTRL8
assign rxdprioout_phy_ch0[`rfreerun_rx_DP_RX_IDX]       = rfreerun_rx_int[0];  // 4'h0;  for POF
assign rxdprioout_phy_ch0[`rrx_rd_clk_sel_DP_RX_IDX]    = rrx_rd_clk_sel_int[0];
assign rxdprioout_phy_ch0[`renumber_DP_RX_IDX_2 : `renumber_DP_RX_IDX_0] = renumber_ch0_int;
assign rxdprioout_phy_ch0[`renpolinv_rx_DP_RX_IDX]      = renpolinv_rx_int[0]; 
assign rxdprioout_phy_ch0[`rclkcmpinsertpad_DP_RX_IDX]  = rclkcmpinsertpad_int[0];
// tx
assign txdprioout_phy_ch0[`rfreerun_tx_DP_TX_IDX]       = rfreerun_tx_int[0];  // 4'h0;  for POF
assign txdprioout_phy_ch0[`rtxwrclksel_DP_TX_IDX]       = rtxwrclksel_int[0];
assign txdprioout_phy_ch0[`rtxrdclksel_DP_TX_IDX]       = rtxrdclksel_int[0]; 
assign rxdprioout_phy_ch0[`rrcvd_clk_sel_DP_RX_IDX_1 : `rrcvd_clk_sel_DP_RX_IDX_0] = rrcvd_clk_sel_ch0_int ; // dprio_enabled: bits 11-10 
assign rxdprioout_phy_ch0[`rclk_1_sel_DP_RX_IDX_1    : `rclk_1_sel_DP_RX_IDX_0]    = rclk_1_sel_ch0_int;     // dprio_enabled: bits 9-8 
assign rxdprioout_phy_ch0[`rclk_2_sel_DP_RX_IDX_1    : `rclk_2_sel_DP_RX_IDX_0]    = rclk_2_sel_ch0_int;     // dprio_enabled: bits 7-6

assign rxdprioout_phy_ch1[`rfreerun_rx_DP_RX_IDX]       = rfreerun_rx_int[1];  // 4'h0;  for POF
assign rxdprioout_phy_ch1[`rrx_rd_clk_sel_DP_RX_IDX]    = rrx_rd_clk_sel_int[1];
assign rxdprioout_phy_ch1[`renumber_DP_RX_IDX_2 : `renumber_DP_RX_IDX_0] = renumber_ch1_int;
assign rxdprioout_phy_ch1[`renpolinv_rx_DP_RX_IDX]      = renpolinv_rx_int[1]; 
assign rxdprioout_phy_ch1[`rclkcmpinsertpad_DP_RX_IDX]  = rclkcmpinsertpad_int[1];
// tx
assign txdprioout_phy_ch1[`rfreerun_tx_DP_TX_IDX]       = rfreerun_tx_int[1];  // 4'h0;  for POF
assign txdprioout_phy_ch1[`rtxwrclksel_DP_TX_IDX]       = rtxwrclksel_int[1];
assign txdprioout_phy_ch1[`rtxrdclksel_DP_TX_IDX]       = rtxrdclksel_int[1]; 
assign rxdprioout_phy_ch1[`rrcvd_clk_sel_DP_RX_IDX_1 : `rrcvd_clk_sel_DP_RX_IDX_0] = rrcvd_clk_sel_ch1_int ; // dprio_enabled: bits 11-10 
assign rxdprioout_phy_ch1[`rclk_1_sel_DP_RX_IDX_1    : `rclk_1_sel_DP_RX_IDX_0]    = rclk_1_sel_ch1_int;     // dprio_enabled: bits 9-8 
assign rxdprioout_phy_ch1[`rclk_2_sel_DP_RX_IDX_1    : `rclk_2_sel_DP_RX_IDX_0]    = rclk_2_sel_ch1_int;     // dprio_enabled: bits 7-6

assign rxdprioout_phy_ch2[`rfreerun_rx_DP_RX_IDX]       = rfreerun_rx_int[2];  // 4'h0;  for POF
assign rxdprioout_phy_ch2[`rrx_rd_clk_sel_DP_RX_IDX]    = rrx_rd_clk_sel_int[2];
assign rxdprioout_phy_ch2[`renumber_DP_RX_IDX_2 : `renumber_DP_RX_IDX_0] = renumber_ch2_int;
assign rxdprioout_phy_ch2[`renpolinv_rx_DP_RX_IDX]      = renpolinv_rx_int[2]; 
assign rxdprioout_phy_ch2[`rclkcmpinsertpad_DP_RX_IDX]  = rclkcmpinsertpad_int[2];
// tx
assign txdprioout_phy_ch2[`rfreerun_tx_DP_TX_IDX]       = rfreerun_tx_int[2];  // 4'h0;  for POF
assign txdprioout_phy_ch2[`rtxwrclksel_DP_TX_IDX]       = rtxwrclksel_int[2];
assign txdprioout_phy_ch2[`rtxrdclksel_DP_TX_IDX]       = rtxrdclksel_int[2]; 
assign rxdprioout_phy_ch2[`rrcvd_clk_sel_DP_RX_IDX_1 : `rrcvd_clk_sel_DP_RX_IDX_0] = rrcvd_clk_sel_ch2_int ; // dprio_enabled: bits 11-10 
assign rxdprioout_phy_ch2[`rclk_1_sel_DP_RX_IDX_1    : `rclk_1_sel_DP_RX_IDX_0]    = rclk_1_sel_ch2_int;     // dprio_enabled: bits 9-8 
assign rxdprioout_phy_ch2[`rclk_2_sel_DP_RX_IDX_1    : `rclk_2_sel_DP_RX_IDX_0]    = rclk_2_sel_ch2_int;     // dprio_enabled: bits 7-6

assign rxdprioout_phy_ch3[`rfreerun_rx_DP_RX_IDX]       = rfreerun_rx_int[3];  // 4'h0;  for POF
assign rxdprioout_phy_ch3[`rrx_rd_clk_sel_DP_RX_IDX]    = rrx_rd_clk_sel_int[3];
assign rxdprioout_phy_ch3[`renumber_DP_RX_IDX_2 : `renumber_DP_RX_IDX_0] = renumber_ch3_int;
assign rxdprioout_phy_ch3[`renpolinv_rx_DP_RX_IDX]      = renpolinv_rx_int[3]; 
assign rxdprioout_phy_ch3[`rclkcmpinsertpad_DP_RX_IDX]  = rclkcmpinsertpad_int[3];
// tx
assign txdprioout_phy_ch3[`rfreerun_tx_DP_TX_IDX]       = rfreerun_tx_int[3];  // 4'h0;  for POF
assign txdprioout_phy_ch3[`rtxwrclksel_DP_TX_IDX]       = rtxwrclksel_int[3];
assign txdprioout_phy_ch3[`rtxrdclksel_DP_TX_IDX]       = rtxrdclksel_int[3]; 
assign rxdprioout_phy_ch3[`rrcvd_clk_sel_DP_RX_IDX_1 : `rrcvd_clk_sel_DP_RX_IDX_0] = rrcvd_clk_sel_ch3_int ; // dprio_enabled: bits 11-10 
assign rxdprioout_phy_ch3[`rclk_1_sel_DP_RX_IDX_1    : `rclk_1_sel_DP_RX_IDX_0]    = rclk_1_sel_ch3_int;     // dprio_enabled: bits 9-8 
assign rxdprioout_phy_ch3[`rclk_2_sel_DP_RX_IDX_1    : `rclk_2_sel_DP_RX_IDX_0]    = rclk_2_sel_ch3_int;     // dprio_enabled: bits 7-6

// PCS_CTRL_9
assign rxdprioout_phy_ch0[`rppm_cnt_reset_DP_RX_IDX] = rppm_cnt_reset_int[0];
assign rxdprioout_phy_ch0[`rphfifourstrx_DP_RX_IDX]  = rphfifourstrx_int[0];
assign rxdprioout_phy_ch0[`rcmpfifourst_DP_RX_IDX]   = rcmpfifourst_int[0];
assign rxdprioout_phy_ch0[`rclkcmpsqmd_DP_RX_IDX]    = rclkcmpsqmd_int[0];
assign rxdprioout_phy_ch0[`rtx_idle_delay_DP_RX_IDX_1 : `rtx_idle_delay_DP_RX_IDX_0] = rtx_idle_delay_ch0_int;
assign rxdprioout_phy_ch0[`rclkcmpsq1p_DP_RX_IDX_19  : `rclkcmpsq1p_DP_RX_IDX_0]    = rclkcmpsq1p_ch0_int[19:0];

assign rxdprioout_phy_ch1[`rppm_cnt_reset_DP_RX_IDX] = rppm_cnt_reset_int[1];
assign rxdprioout_phy_ch1[`rphfifourstrx_DP_RX_IDX]  = rphfifourstrx_int[1];
assign rxdprioout_phy_ch1[`rcmpfifourst_DP_RX_IDX]   = rcmpfifourst_int[1];
assign rxdprioout_phy_ch1[`rclkcmpsqmd_DP_RX_IDX]    = rclkcmpsqmd_int[1];
assign rxdprioout_phy_ch1[`rtx_idle_delay_DP_RX_IDX_1 : `rtx_idle_delay_DP_RX_IDX_0] = rtx_idle_delay_ch1_int;
assign rxdprioout_phy_ch1[`rclkcmpsq1p_DP_RX_IDX_19   : `rclkcmpsq1p_DP_RX_IDX_0]    = rclkcmpsq1p_ch1_int[19:0];

assign rxdprioout_phy_ch2[`rppm_cnt_reset_DP_RX_IDX] = rppm_cnt_reset_int[2];
assign rxdprioout_phy_ch2[`rphfifourstrx_DP_RX_IDX]  = rphfifourstrx_int[2];
assign rxdprioout_phy_ch2[`rcmpfifourst_DP_RX_IDX]   = rcmpfifourst_int[2];
assign rxdprioout_phy_ch2[`rclkcmpsqmd_DP_RX_IDX]    = rclkcmpsqmd_int[2];
assign rxdprioout_phy_ch2[`rtx_idle_delay_DP_RX_IDX_1 : `rtx_idle_delay_DP_RX_IDX_0] = rtx_idle_delay_ch2_int;
assign rxdprioout_phy_ch2[`rclkcmpsq1p_DP_RX_IDX_19   : `rclkcmpsq1p_DP_RX_IDX_0]    = rclkcmpsq1p_ch2_int[19:0];

assign rxdprioout_phy_ch3[`rppm_cnt_reset_DP_RX_IDX] = rppm_cnt_reset_int[3];
assign rxdprioout_phy_ch3[`rphfifourstrx_DP_RX_IDX]  = rphfifourstrx_int[3];
assign rxdprioout_phy_ch3[`rcmpfifourst_DP_RX_IDX]   = rcmpfifourst_int[3];
assign rxdprioout_phy_ch3[`rclkcmpsqmd_DP_RX_IDX]    = rclkcmpsqmd_int[3];
assign rxdprioout_phy_ch3[`rtx_idle_delay_DP_RX_IDX_1 : `rtx_idle_delay_DP_RX_IDX_0] = rtx_idle_delay_ch3_int;
assign rxdprioout_phy_ch3[`rclkcmpsq1p_DP_RX_IDX_19   : `rclkcmpsq1p_DP_RX_IDX_0]    = rclkcmpsq1p_ch3_int[19:0];

// PCS_CTRL_10, 11
assign rxdprioout_phy_ch0[`rclkcmpsq1n_DP_RX_IDX_19 : `rclkcmpsq1n_DP_RX_IDX_0] = rclkcmpsq1n_ch0_int;
assign rxdprioout_phy_ch0[`rclkcmppos_DP_RX_IDX] = rclkcmppos_int[0];

assign rxdprioout_phy_ch1[`rclkcmpsq1n_DP_RX_IDX_19 : `rclkcmpsq1n_DP_RX_IDX_0] = rclkcmpsq1n_ch1_int;
assign rxdprioout_phy_ch1[`rclkcmppos_DP_RX_IDX] = rclkcmppos_int[1];

assign rxdprioout_phy_ch2[`rclkcmpsq1n_DP_RX_IDX_19 : `rclkcmpsq1n_DP_RX_IDX_0] = rclkcmpsq1n_ch2_int;
assign rxdprioout_phy_ch2[`rclkcmppos_DP_RX_IDX] = rclkcmppos_int[2];

assign rxdprioout_phy_ch3[`rclkcmpsq1n_DP_RX_IDX_19 : `rclkcmpsq1n_DP_RX_IDX_0] = rclkcmpsq1n_ch3_int;
assign rxdprioout_phy_ch3[`rclkcmppos_DP_RX_IDX] = rclkcmppos_int[3];

// PCS_CTRL_12 - rx and tx mixed
assign rxdprioout_phy_ch0[`ralempty_DP_RX_IDX_3 : `ralempty_DP_RX_IDX_0]   =  ralempty_ch0_int;
assign rxdprioout_phy_ch0[`ralfull_DP_RX_IDX_3 : `ralfull_DP_RX_IDX_0]     =  ralfull_ch0_int;
assign rxdprioout_phy_ch0[`rkchar_DP_RX_IDX]       = rkchar_int[0];
assign rxdprioout_phy_ch0[`rosbased_DP_RX_IDX]     = rosbased_int[0];
assign rxdprioout_phy_ch0[`rosnumber_DP_RX_IDX_1 : `rosnumber_DP_RX_IDX_0] = rosnumber_ch0_int;
//tx
assign txdprioout_phy_ch0[`rrev_loopbk_DP_TX_IDX]  = rrev_loopbk_int[0];
assign txdprioout_phy_ch0[`rforce_disp_DP_TX_IDX]  = rforce_disp_int[0];
assign txdprioout_phy_ch0[`rensymswap_tx_DP_TX_IDX]= rensymswap_tx_int[0];

assign rxdprioout_phy_ch1[`ralempty_DP_RX_IDX_3 : `ralempty_DP_RX_IDX_0]   =  ralempty_ch1_int;
assign rxdprioout_phy_ch1[`ralfull_DP_RX_IDX_3 : `ralfull_DP_RX_IDX_0]     =  ralfull_ch1_int;
assign rxdprioout_phy_ch1[`rkchar_DP_RX_IDX]       = rkchar_int[1];
assign rxdprioout_phy_ch1[`rosbased_DP_RX_IDX]     = rosbased_int[1];
assign rxdprioout_phy_ch1[`rosnumber_DP_RX_IDX_1 : `rosnumber_DP_RX_IDX_0] = rosnumber_ch1_int;
//tx
assign txdprioout_phy_ch1[`rrev_loopbk_DP_TX_IDX]  = rrev_loopbk_int[1];
assign txdprioout_phy_ch1[`rforce_disp_DP_TX_IDX]  = rforce_disp_int[1];
assign txdprioout_phy_ch1[`rensymswap_tx_DP_TX_IDX]= rensymswap_tx_int[1];

assign rxdprioout_phy_ch2[`ralempty_DP_RX_IDX_3 : `ralempty_DP_RX_IDX_0]   =  ralempty_ch2_int;
assign rxdprioout_phy_ch2[`ralfull_DP_RX_IDX_3 : `ralfull_DP_RX_IDX_0]     =  ralfull_ch2_int;
assign rxdprioout_phy_ch2[`rkchar_DP_RX_IDX]       = rkchar_int[2];
assign rxdprioout_phy_ch2[`rosbased_DP_RX_IDX]     = rosbased_int[2];
assign rxdprioout_phy_ch2[`rosnumber_DP_RX_IDX_1 : `rosnumber_DP_RX_IDX_0] = rosnumber_ch2_int;
//tx
assign txdprioout_phy_ch2[`rrev_loopbk_DP_TX_IDX]  = rrev_loopbk_int[2];
assign txdprioout_phy_ch2[`rforce_disp_DP_TX_IDX]  = rforce_disp_int[2];
assign txdprioout_phy_ch2[`rensymswap_tx_DP_TX_IDX]= rensymswap_tx_int[2];

assign rxdprioout_phy_ch3[`ralempty_DP_RX_IDX_3 : `ralempty_DP_RX_IDX_0]   =  ralempty_ch3_int;
assign rxdprioout_phy_ch3[`ralfull_DP_RX_IDX_3 : `ralfull_DP_RX_IDX_0]     =  ralfull_ch3_int;
assign rxdprioout_phy_ch3[`rkchar_DP_RX_IDX]       = rkchar_int[3];
assign rxdprioout_phy_ch3[`rosbased_DP_RX_IDX]     = rosbased_int[3];
assign rxdprioout_phy_ch3[`rosnumber_DP_RX_IDX_1 : `rosnumber_DP_RX_IDX_0] = rosnumber_ch3_int;
//tx
assign txdprioout_phy_ch3[`rrev_loopbk_DP_TX_IDX]  = rrev_loopbk_int[3];
assign txdprioout_phy_ch3[`rforce_disp_DP_TX_IDX]  = rforce_disp_int[3];
assign txdprioout_phy_ch3[`rensymswap_tx_DP_TX_IDX]= rensymswap_tx_int[3];

// PCS_CTRL_13
assign rxdprioout_phy_ch0[`rwa_6g_en_DP_RX_IDX]    = rwa_6g_en_int[0];
assign rxdprioout_phy_ch0[`rbitslip_size_DP_RX_IDX_1 : `rbitslip_size_DP_RX_IDX_0] = rbitslip_size_ch0_int;
assign rxdprioout_phy_ch0[`rbytord_2sym_en_DP_RX_IDX]   = rbytord_2sym_en_int[0];
assign rxdprioout_phy_ch0[`rbysync_polinv_en_DP_RX_IDX] = rbysync_polinv_en_int[0];
assign rxdprioout_phy_ch0[`rbitloc_rev_en_DP_RX_IDX]    = rbitloc_rev_en_int[0];
assign rxdprioout_phy_ch0[`rbyte_rev_en_DP_RX_IDX]      = rbyte_rev_en_int[0];
assign rxdprioout_phy_ch0[`rbyteorden_DP_RX_IDX_1 : `rbyteorden_DP_RX_IDX_0]      = rbyteorden_ch0_int;
assign rxdprioout_phy_ch0[`rbytordplden_DP_RX_IDX]      = rbytordplden_int[0];
assign rxdprioout_phy_ch0[`rphfifopldenrx_DP_RX_IDX]    = rphfifopldenrx_int[0];
assign rxdprioout_phy_ch0[`rautoinsdis_DP_RX_IDX]       = rautoinsdis_int[0];
//tx
assign txdprioout_phy_ch0[`renpolinv_tx_DP_TX_IDX]      = renpolinv_tx_int[0];
assign txdprioout_phy_ch0[`renbitrev_tx_DP_TX_IDX]      = renbitrev_tx_int[0];
assign txdprioout_phy_ch0[`rphfifopldentx_DP_TX_IDX]    = rphfifopldentx_int[0];
assign txdprioout_phy_ch0[`rphfifoursttx_DP_TX_IDX]     = rphfifoursttx_int[0];

assign rxdprioout_phy_ch1[`rwa_6g_en_DP_RX_IDX]    = rwa_6g_en_int[1];
assign rxdprioout_phy_ch1[`rbitslip_size_DP_RX_IDX_1 : `rbitslip_size_DP_RX_IDX_0] = rbitslip_size_ch1_int;
assign rxdprioout_phy_ch1[`rbytord_2sym_en_DP_RX_IDX]   = rbytord_2sym_en_int[1];
assign rxdprioout_phy_ch1[`rbysync_polinv_en_DP_RX_IDX] = rbysync_polinv_en_int[1];
assign rxdprioout_phy_ch1[`rbitloc_rev_en_DP_RX_IDX]    = rbitloc_rev_en_int[1];
assign rxdprioout_phy_ch1[`rbyte_rev_en_DP_RX_IDX]      = rbyte_rev_en_int[1];
assign rxdprioout_phy_ch1[`rbyteorden_DP_RX_IDX_1 : `rbyteorden_DP_RX_IDX_0]      = rbyteorden_ch1_int;
assign rxdprioout_phy_ch1[`rbytordplden_DP_RX_IDX]      = rbytordplden_int[1];
assign rxdprioout_phy_ch1[`rphfifopldenrx_DP_RX_IDX]    = rphfifopldenrx_int[1];
assign rxdprioout_phy_ch1[`rautoinsdis_DP_RX_IDX]       = rautoinsdis_int[1];
//tx
assign txdprioout_phy_ch1[`renpolinv_tx_DP_TX_IDX]      = renpolinv_tx_int[1];
assign txdprioout_phy_ch1[`renbitrev_tx_DP_TX_IDX]      = renbitrev_tx_int[1];
assign txdprioout_phy_ch1[`rphfifopldentx_DP_TX_IDX]    = rphfifopldentx_int[1];
assign txdprioout_phy_ch1[`rphfifoursttx_DP_TX_IDX]     = rphfifoursttx_int[1];

assign rxdprioout_phy_ch2[`rwa_6g_en_DP_RX_IDX]    = rwa_6g_en_int[2];
assign rxdprioout_phy_ch2[`rbitslip_size_DP_RX_IDX_1 : `rbitslip_size_DP_RX_IDX_0] = rbitslip_size_ch2_int;
assign rxdprioout_phy_ch2[`rbytord_2sym_en_DP_RX_IDX]   = rbytord_2sym_en_int[2];
assign rxdprioout_phy_ch2[`rbysync_polinv_en_DP_RX_IDX] = rbysync_polinv_en_int[2];
assign rxdprioout_phy_ch2[`rbitloc_rev_en_DP_RX_IDX]    = rbitloc_rev_en_int[2];
assign rxdprioout_phy_ch2[`rbyte_rev_en_DP_RX_IDX]      = rbyte_rev_en_int[2];
assign rxdprioout_phy_ch2[`rbyteorden_DP_RX_IDX_1 : `rbyteorden_DP_RX_IDX_0]      = rbyteorden_ch2_int;
assign rxdprioout_phy_ch2[`rbytordplden_DP_RX_IDX]      = rbytordplden_int[2];
assign rxdprioout_phy_ch2[`rphfifopldenrx_DP_RX_IDX]    = rphfifopldenrx_int[2];
assign rxdprioout_phy_ch2[`rautoinsdis_DP_RX_IDX]       = rautoinsdis_int[2];
//tx
assign txdprioout_phy_ch2[`renpolinv_tx_DP_TX_IDX]      = renpolinv_tx_int[2];
assign txdprioout_phy_ch2[`renbitrev_tx_DP_TX_IDX]      = renbitrev_tx_int[2];
assign txdprioout_phy_ch2[`rphfifopldentx_DP_TX_IDX]    = rphfifopldentx_int[2];
assign txdprioout_phy_ch2[`rphfifoursttx_DP_TX_IDX]     = rphfifoursttx_int[2];

assign rxdprioout_phy_ch3[`rwa_6g_en_DP_RX_IDX]    = rwa_6g_en_int[3];
assign rxdprioout_phy_ch3[`rbitslip_size_DP_RX_IDX_1 : `rbitslip_size_DP_RX_IDX_0] = rbitslip_size_ch3_int;
assign rxdprioout_phy_ch3[`rbytord_2sym_en_DP_RX_IDX]   = rbytord_2sym_en_int[3];
assign rxdprioout_phy_ch3[`rbysync_polinv_en_DP_RX_IDX] = rbysync_polinv_en_int[3];
assign rxdprioout_phy_ch3[`rbitloc_rev_en_DP_RX_IDX]    = rbitloc_rev_en_int[3];
assign rxdprioout_phy_ch3[`rbyte_rev_en_DP_RX_IDX]      = rbyte_rev_en_int[3];
assign rxdprioout_phy_ch3[`rbyteorden_DP_RX_IDX_1 : `rbyteorden_DP_RX_IDX_0]      = rbyteorden_ch3_int;
assign rxdprioout_phy_ch3[`rbytordplden_DP_RX_IDX]      = rbytordplden_int[3];
assign rxdprioout_phy_ch3[`rphfifopldenrx_DP_RX_IDX]    = rphfifopldenrx_int[3];
assign rxdprioout_phy_ch3[`rautoinsdis_DP_RX_IDX]       = rautoinsdis_int[3];
//tx
assign txdprioout_phy_ch3[`renpolinv_tx_DP_TX_IDX]      = renpolinv_tx_int[3];
assign txdprioout_phy_ch3[`renbitrev_tx_DP_TX_IDX]      = renbitrev_tx_int[3];
assign txdprioout_phy_ch3[`rphfifopldentx_DP_TX_IDX]    = rphfifopldentx_int[3];
assign txdprioout_phy_ch3[`rphfifoursttx_DP_TX_IDX]     = rphfifoursttx_int[3];

// PCS_CTRL_14
assign rxdprioout_phy_ch0[`rppmsel_DP_RX_IDX_5 : `rppmsel_DP_RX_IDX_0]       = rppmsel_ch0_int;
assign rxdprioout_phy_ch0[`rbytordpat_DP_RX_IDX_9 : `rbytordpat_DP_RX_IDX_0] = rbytordpat_ch0_int;
assign rxdprioout_phy_ch1[`rppmsel_DP_RX_IDX_5 : `rppmsel_DP_RX_IDX_0]       = rppmsel_ch1_int;
assign rxdprioout_phy_ch1[`rbytordpat_DP_RX_IDX_9 : `rbytordpat_DP_RX_IDX_0] = rbytordpat_ch1_int;
assign rxdprioout_phy_ch2[`rppmsel_DP_RX_IDX_5 : `rppmsel_DP_RX_IDX_0]       = rppmsel_ch2_int;
assign rxdprioout_phy_ch2[`rbytordpat_DP_RX_IDX_9 : `rbytordpat_DP_RX_IDX_0] = rbytordpat_ch2_int;
assign rxdprioout_phy_ch3[`rppmsel_DP_RX_IDX_5 : `rppmsel_DP_RX_IDX_0]       = rppmsel_ch3_int;
assign rxdprioout_phy_ch3[`rbytordpat_DP_RX_IDX_9 : `rbytordpat_DP_RX_IDX_0] = rbytordpat_ch3_int;

// PCS_CTRL_15
//assign testbus_ch0_int 
assign rxdprioout_phy_ch0[`rforce_sig_det_pcs_DP_RX_IDX] = rforce_sig_det_pcs_int[0];
assign rxdprioout_phy_ch0[`rforce0_freqdet_DP_RX_IDX]    = rforce0_freqdet_int[0];
assign rxdprioout_phy_ch0[`rforce1_freqdet_DP_RX_IDX]    = rforce1_freqdet_int[0];
assign rxdprioout_phy_ch0[`rbytordpad_DP_RX_IDX_9 : `rbytordpad_DP_RX_IDX_0] = rbytordpad_ch0_int;

assign rxdprioout_phy_ch1[`rforce_sig_det_pcs_DP_RX_IDX] = rforce_sig_det_pcs_int[1];
assign rxdprioout_phy_ch1[`rforce0_freqdet_DP_RX_IDX]    = rforce0_freqdet_int[1];
assign rxdprioout_phy_ch1[`rforce1_freqdet_DP_RX_IDX]    = rforce1_freqdet_int[1];
assign rxdprioout_phy_ch1[`rbytordpad_DP_RX_IDX_9 : `rbytordpad_DP_RX_IDX_0] = rbytordpad_ch1_int;

assign rxdprioout_phy_ch2[`rforce_sig_det_pcs_DP_RX_IDX] = rforce_sig_det_pcs_int[2];
assign rxdprioout_phy_ch2[`rforce0_freqdet_DP_RX_IDX]    = rforce0_freqdet_int[2];
assign rxdprioout_phy_ch2[`rforce1_freqdet_DP_RX_IDX]    = rforce1_freqdet_int[2];
assign rxdprioout_phy_ch2[`rbytordpad_DP_RX_IDX_9 : `rbytordpad_DP_RX_IDX_0] = rbytordpad_ch2_int;

assign rxdprioout_phy_ch3[`rforce_sig_det_pcs_DP_RX_IDX] = rforce_sig_det_pcs_int[3];
assign rxdprioout_phy_ch3[`rforce0_freqdet_DP_RX_IDX]    = rforce0_freqdet_int[3];
assign rxdprioout_phy_ch3[`rforce1_freqdet_DP_RX_IDX]    = rforce1_freqdet_int[3];
assign rxdprioout_phy_ch3[`rbytordpad_DP_RX_IDX_9 : `rbytordpad_DP_RX_IDX_0] = rbytordpad_ch3_int;

// passing reconfig_clk to RX ADCE
assign rxdprioout_phy_ch0[`reconfig_clk_DP_RX_IDX] = mdc;
assign rxdprioout_phy_ch1[`reconfig_clk_DP_RX_IDX] = mdc;
assign rxdprioout_phy_ch2[`reconfig_clk_DP_RX_IDX] = mdc;
assign rxdprioout_phy_ch3[`reconfig_clk_DP_RX_IDX] = mdc;


// pcs_ctrl out to add - make sure ended with _int

////////////////////////////////////////////////////////////////////////////////
// mqmap end                                                                 //
////////////////////////////////////////////////////////////////////////////////

// XGXS_STATUS1 and XGXS_STATUS2 status registers
assign xs_link_status_rd = mdio_rd & (reg_addr==XGXS_STATUS1); 
assign tx_rx_local_fault_status_rd = mdio_rd & (reg_addr==XGXS_STATUS2); 


// Output data
// PCS channel0 output
arriagx_hssi_mdio_pcs_bus_out_mux pcs_chnl_0 (.pcs_ctrl_in1(pcs_ctrl1_ch0_reg),
			         .pcs_ctrl_in2(pcs_ctrl2_ch0_reg),
			         .pcs_ctrl_in3(pcs_ctrl3_ch0_reg),
			         .pcs_ctrl_in4(pcs_ctrl4_ch0_reg),
			         .pcs_ctrl_in5(pcs_ctrl5_ch0_reg),
			         .pcs_ctrl_in6(pcs_ctrl6_ch0_reg),
			         .pcs_ctrl_in7(pcs_ctrl7_ch0_reg),
			         .pcs_ctrl_in8(pcs_ctrl8_ch0_reg),
			         .pcs_ctrl_in9(pcs_ctrl9_ch0_reg),
			         .pcs_ctrl_in10(pcs_ctrl10_ch0_reg),
			         .pcs_ctrl_in11(pcs_ctrl11_ch0_reg),
			         .pcs_ctrl_in12(pcs_ctrl12_ch0_reg),
			         .pcs_ctrl_in13(pcs_ctrl13_ch0_reg),
			         .pcs_ctrl_in14(pcs_ctrl14_ch0_reg),
			         .pcs_ctrl_in15(pcs_ctrl15_ch0_reg),
			         .pcs_ctrl_in16(prbs_bist_ctrl_ch0_reg),
			         .hw_address_ctrl_in1(PCS_CTRL1_CH0),
			         .hw_address_ctrl_in2(PCS_CTRL2_CH0),
			         .hw_address_ctrl_in3(PCS_CTRL3_CH0),
			         .hw_address_ctrl_in4(PCS_CTRL4_CH0),
			         .hw_address_ctrl_in5(PCS_CTRL5_CH0),
			         .hw_address_ctrl_in6(PCS_CTRL6_CH0),
			         .hw_address_ctrl_in7(PCS_CTRL7_CH0),
			         .hw_address_ctrl_in8(PCS_CTRL8_CH0),
			         .hw_address_ctrl_in9(PCS_CTRL9_CH0),
			         .hw_address_ctrl_in10(PCS_CTRL10_CH0),
			         .hw_address_ctrl_in11(PCS_CTRL11_CH0),
			         .hw_address_ctrl_in12(PCS_CTRL12_CH0),
			         .hw_address_ctrl_in13(PCS_CTRL13_CH0),
			         .hw_address_ctrl_in14(PCS_CTRL14_CH0),
			         .hw_address_ctrl_in15(PCS_CTRL15_CH0),
			         .hw_address_ctrl_in16(PRBS_BIST_CTRL_CH0),
			         .reg_addr(reg_addr),
			         .pcs_ctrl_out(pcs_ctrl_out_ch0)
                                 );

// PCS channel1 output
arriagx_hssi_mdio_pcs_bus_out_mux pcs_chnl_1 (.pcs_ctrl_in1(pcs_ctrl1_ch1_reg),
			         .pcs_ctrl_in2(pcs_ctrl2_ch1_reg),
			         .pcs_ctrl_in3(pcs_ctrl3_ch1_reg),
			         .pcs_ctrl_in4(pcs_ctrl4_ch1_reg),
			         .pcs_ctrl_in5(pcs_ctrl5_ch1_reg),
			         .pcs_ctrl_in6(pcs_ctrl6_ch1_reg),
			         .pcs_ctrl_in7(pcs_ctrl7_ch1_reg),
			         .pcs_ctrl_in8(pcs_ctrl8_ch1_reg),
			         .pcs_ctrl_in9(pcs_ctrl9_ch1_reg),
			         .pcs_ctrl_in10(pcs_ctrl10_ch1_reg),
			         .pcs_ctrl_in11(pcs_ctrl11_ch1_reg),
			         .pcs_ctrl_in12(pcs_ctrl12_ch1_reg),
			         .pcs_ctrl_in13(pcs_ctrl13_ch1_reg),
			         .pcs_ctrl_in14(pcs_ctrl14_ch1_reg),
			         .pcs_ctrl_in15(pcs_ctrl15_ch1_reg),
			         .pcs_ctrl_in16(prbs_bist_ctrl_ch1_reg),
			         .hw_address_ctrl_in1(PCS_CTRL1_CH1),
			         .hw_address_ctrl_in2(PCS_CTRL2_CH1),
			         .hw_address_ctrl_in3(PCS_CTRL3_CH1),
			         .hw_address_ctrl_in4(PCS_CTRL4_CH1),
			         .hw_address_ctrl_in5(PCS_CTRL5_CH1),
			         .hw_address_ctrl_in6(PCS_CTRL6_CH1),
			         .hw_address_ctrl_in7(PCS_CTRL7_CH1),
			         .hw_address_ctrl_in8(PCS_CTRL8_CH1),
			         .hw_address_ctrl_in9(PCS_CTRL9_CH1),
			         .hw_address_ctrl_in10(PCS_CTRL10_CH1),
			         .hw_address_ctrl_in11(PCS_CTRL11_CH1),
			         .hw_address_ctrl_in12(PCS_CTRL12_CH1),
			         .hw_address_ctrl_in13(PCS_CTRL13_CH1),
			         .hw_address_ctrl_in14(PCS_CTRL14_CH1),
			         .hw_address_ctrl_in15(PCS_CTRL15_CH1),
			         .hw_address_ctrl_in16(PRBS_BIST_CTRL_CH1),
			         .reg_addr(reg_addr),
			         .pcs_ctrl_out(pcs_ctrl_out_ch1)
                                 );

// PCS channel2 output
arriagx_hssi_mdio_pcs_bus_out_mux pcs_chnl_2 (.pcs_ctrl_in1(pcs_ctrl1_ch2_reg),
			         .pcs_ctrl_in2(pcs_ctrl2_ch2_reg),
			         .pcs_ctrl_in3(pcs_ctrl3_ch2_reg),
			         .pcs_ctrl_in4(pcs_ctrl4_ch2_reg),
			         .pcs_ctrl_in5(pcs_ctrl5_ch2_reg),
			         .pcs_ctrl_in6(pcs_ctrl6_ch2_reg),
			         .pcs_ctrl_in7(pcs_ctrl7_ch2_reg),
			         .pcs_ctrl_in8(pcs_ctrl8_ch2_reg),
			         .pcs_ctrl_in9(pcs_ctrl9_ch2_reg),
			         .pcs_ctrl_in10(pcs_ctrl10_ch2_reg),
			         .pcs_ctrl_in11(pcs_ctrl11_ch2_reg),
			         .pcs_ctrl_in12(pcs_ctrl12_ch2_reg),
			         .pcs_ctrl_in13(pcs_ctrl13_ch2_reg),
			         .pcs_ctrl_in14(pcs_ctrl14_ch2_reg),
			         .pcs_ctrl_in15(pcs_ctrl15_ch2_reg),
			         .pcs_ctrl_in16(prbs_bist_ctrl_ch2_reg),
			         .hw_address_ctrl_in1(PCS_CTRL1_CH2),
			         .hw_address_ctrl_in2(PCS_CTRL2_CH2),
			         .hw_address_ctrl_in3(PCS_CTRL3_CH2),
			         .hw_address_ctrl_in4(PCS_CTRL4_CH2),
			         .hw_address_ctrl_in5(PCS_CTRL5_CH2),
			         .hw_address_ctrl_in6(PCS_CTRL6_CH2),
			         .hw_address_ctrl_in7(PCS_CTRL7_CH2),
			         .hw_address_ctrl_in8(PCS_CTRL8_CH2),
			         .hw_address_ctrl_in9(PCS_CTRL9_CH2),
			         .hw_address_ctrl_in10(PCS_CTRL10_CH2),
			         .hw_address_ctrl_in11(PCS_CTRL11_CH2),
			         .hw_address_ctrl_in12(PCS_CTRL12_CH2),
			         .hw_address_ctrl_in13(PCS_CTRL13_CH2),
			         .hw_address_ctrl_in14(PCS_CTRL14_CH2),
			         .hw_address_ctrl_in15(PCS_CTRL15_CH2),
			         .hw_address_ctrl_in16(PRBS_BIST_CTRL_CH2),
			         .reg_addr(reg_addr),
			         .pcs_ctrl_out(pcs_ctrl_out_ch2)
                                 );

// PCS channel3 output
arriagx_hssi_mdio_pcs_bus_out_mux pcs_chnl_3 (.pcs_ctrl_in1(pcs_ctrl1_ch3_reg),
			         .pcs_ctrl_in2(pcs_ctrl2_ch3_reg),
			         .pcs_ctrl_in3(pcs_ctrl3_ch3_reg),
			         .pcs_ctrl_in4(pcs_ctrl4_ch3_reg),
			         .pcs_ctrl_in5(pcs_ctrl5_ch3_reg),
			         .pcs_ctrl_in6(pcs_ctrl6_ch3_reg),
			         .pcs_ctrl_in7(pcs_ctrl7_ch3_reg),
			         .pcs_ctrl_in8(pcs_ctrl8_ch3_reg),
			         .pcs_ctrl_in9(pcs_ctrl9_ch3_reg),
			         .pcs_ctrl_in10(pcs_ctrl10_ch3_reg),
			         .pcs_ctrl_in11(pcs_ctrl11_ch3_reg),
			         .pcs_ctrl_in12(pcs_ctrl12_ch3_reg),
			         .pcs_ctrl_in13(pcs_ctrl13_ch3_reg),
			         .pcs_ctrl_in14(pcs_ctrl14_ch3_reg),
			         .pcs_ctrl_in15(pcs_ctrl15_ch3_reg),
			         .pcs_ctrl_in16(prbs_bist_ctrl_ch3_reg),
			         .hw_address_ctrl_in1(PCS_CTRL1_CH3),
			         .hw_address_ctrl_in2(PCS_CTRL2_CH3),
			         .hw_address_ctrl_in3(PCS_CTRL3_CH3),
			         .hw_address_ctrl_in4(PCS_CTRL4_CH3),
			         .hw_address_ctrl_in5(PCS_CTRL5_CH3),
			         .hw_address_ctrl_in6(PCS_CTRL6_CH3),
			         .hw_address_ctrl_in7(PCS_CTRL7_CH3),
			         .hw_address_ctrl_in8(PCS_CTRL8_CH3),
			         .hw_address_ctrl_in9(PCS_CTRL9_CH3),
			         .hw_address_ctrl_in10(PCS_CTRL10_CH3),
			         .hw_address_ctrl_in11(PCS_CTRL11_CH3),
			         .hw_address_ctrl_in12(PCS_CTRL12_CH3),
			         .hw_address_ctrl_in13(PCS_CTRL13_CH3),
			         .hw_address_ctrl_in14(PCS_CTRL14_CH3),
			         .hw_address_ctrl_in15(PCS_CTRL15_CH3),
			         .hw_address_ctrl_in16(PRBS_BIST_CTRL_CH3),
			         .reg_addr(reg_addr),
			         .pcs_ctrl_out(pcs_ctrl_out_ch3)
                                 );

assign mbus_out = (reg_addr == XGXS_CTRL)          ? xgxs_ctrl_reg :
                  (reg_addr == XGXS_STATUS1)       ? xgxs_stat1_reg :      
                  (reg_addr == XGXS_STATUS2)       ? xgxs_stat2_reg :       
                  (reg_addr == XGXS_LANE_STATUS)   ? xgxs_lane_stat_reg :  
                  (reg_addr == TRUNKING_MODE)      ? trunking_mode_reg :
                  (reg_addr == PCS_CTRL1_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL1_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL1_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL1_CH3)      ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL2_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL2_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL2_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL2_CH3)      ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL3_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL3_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL3_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL3_CH3)      ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL4_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL4_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL4_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL4_CH3)      ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL5_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL5_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL5_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL5_CH3)      ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL6_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL6_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL6_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL6_CH3)      ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL7_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL7_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL7_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL7_CH3)      ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL8_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL8_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL8_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL8_CH3)      ? pcs_ctrl_out_ch3 : mbusout_s1;
assign mbusout_s1=(reg_addr == PRBS_BIST_CTRL_CH0) ? pcs_ctrl_out_ch0 :
                  (reg_addr == PRBS_BIST_CTRL_CH1) ? pcs_ctrl_out_ch1 :
                  (reg_addr == PRBS_BIST_CTRL_CH2) ? pcs_ctrl_out_ch2 :
                  (reg_addr == PRBS_BIST_CTRL_CH3) ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL9_CH0)      ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL9_CH1)      ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL9_CH2)      ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL9_CH3)      ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL10_CH0)     ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL10_CH1)     ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL10_CH2)     ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL10_CH3)     ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL11_CH0)     ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL11_CH1)     ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL11_CH2)     ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL11_CH3)     ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL12_CH0)     ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL12_CH1)     ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL12_CH2)     ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL12_CH3)     ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL13_CH0)     ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL13_CH1)     ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL13_CH2)     ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL13_CH3)     ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL14_CH0)     ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL14_CH1)     ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL14_CH2)     ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL14_CH3)     ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_CTRL15_CH0)     ? pcs_ctrl_out_ch0 :
                  (reg_addr == PCS_CTRL15_CH1)     ? pcs_ctrl_out_ch1 :
                  (reg_addr == PCS_CTRL15_CH2)     ? pcs_ctrl_out_ch2 :
                  (reg_addr == PCS_CTRL15_CH3)     ? pcs_ctrl_out_ch3 :
                  (reg_addr == PCS_GLOBAL_CTRL0)   ? pcs_global_ctrl0_reg :
                  (reg_addr == PCS_GLOBAL_CTRL1)   ? pcs_global_ctrl1_reg :
                  (reg_addr == PCS_GLOBAL_CTRL2)   ? pcs_global_ctrl2_reg : mbusout_s2;
assign mbusout_s2=(reg_addr == PMA_CTRL1_CH0)      ? pma_ctrl1_ch0_reg :
                  (reg_addr == PMA_CTRL1_CH1)      ? pma_ctrl1_ch1_reg :
                  (reg_addr == PMA_CTRL1_CH2)      ? pma_ctrl1_ch2_reg :
                  (reg_addr == PMA_CTRL1_CH3)      ? pma_ctrl1_ch3_reg :
                  (reg_addr == PMA_CTRL2_CH0)      ? pma_ctrl2_ch0_reg :
                  (reg_addr == PMA_CTRL2_CH1)      ? pma_ctrl2_ch1_reg :
                  (reg_addr == PMA_CTRL2_CH2)      ? pma_ctrl2_ch2_reg :
                  (reg_addr == PMA_CTRL2_CH3)      ? pma_ctrl2_ch3_reg :
                  (reg_addr == PMA_CTRL3_CH0)      ? pma_ctrl3_ch0_reg :
                  (reg_addr == PMA_CTRL3_CH1)      ? pma_ctrl3_ch1_reg :
                  (reg_addr == PMA_CTRL3_CH2)      ? pma_ctrl3_ch2_reg :
                  (reg_addr == PMA_CTRL3_CH3)      ? pma_ctrl3_ch3_reg :
                  (reg_addr == PMA_CTRL4_CH0)      ? pma_ctrl4_ch0_reg :
                  (reg_addr == PMA_CTRL4_CH1)      ? pma_ctrl4_ch1_reg :
                  (reg_addr == PMA_CTRL4_CH2)      ? pma_ctrl4_ch2_reg :
                  (reg_addr == PMA_CTRL4_CH3)      ? pma_ctrl4_ch3_reg :
                  (reg_addr == PMA_CTRL5_CH0)      ? pma_ctrl5_ch0_reg :
                  (reg_addr == PMA_CTRL5_CH1)      ? pma_ctrl5_ch1_reg :
                  (reg_addr == PMA_CTRL5_CH2)      ? pma_ctrl5_ch2_reg :
                  (reg_addr == PMA_CTRL5_CH3)      ? pma_ctrl5_ch3_reg :
                  (reg_addr == PMA_CTRL6_CH0)      ? pma_ctrl6_ch0_reg :
                  (reg_addr == PMA_CTRL6_CH1)      ? pma_ctrl6_ch1_reg :
                  (reg_addr == PMA_CTRL6_CH2)      ? pma_ctrl6_ch2_reg :
                  (reg_addr == PMA_CTRL6_CH3)      ? pma_ctrl6_ch3_reg :
                  (reg_addr == PMA_CTRL7_CH0)      ? pma_ctrl7_ch0_reg :
                  (reg_addr == PMA_CTRL7_CH1)      ? pma_ctrl7_ch1_reg :
                  (reg_addr == PMA_CTRL7_CH2)      ? pma_ctrl7_ch2_reg :
                  (reg_addr == PMA_CTRL7_CH3)      ? pma_ctrl7_ch3_reg :
                  (reg_addr == PMA_CTRL8_CH0)      ? pma_ctrl8_ch0_reg :
                  (reg_addr == PMA_CTRL8_CH1)      ? pma_ctrl8_ch1_reg :
                  (reg_addr == PMA_CTRL8_CH2)      ? pma_ctrl8_ch2_reg :
                  (reg_addr == PMA_CTRL8_CH3)      ? pma_ctrl8_ch3_reg :
                  (reg_addr == PMA_CTRL9_CH0)      ? pma_ctrl9_ch0_reg :
                  (reg_addr == PMA_CTRL9_CH1)      ? pma_ctrl9_ch1_reg :
                  (reg_addr == PMA_CTRL9_CH2)      ? pma_ctrl9_ch2_reg :
                  (reg_addr == PMA_CTRL9_CH3)      ? pma_ctrl9_ch3_reg :
                  (reg_addr == PMA_CTRL10_CH0)     ? pma_ctrl10_ch0_reg :
                  (reg_addr == PMA_CTRL10_CH1)     ? pma_ctrl10_ch1_reg :
                  (reg_addr == PMA_CTRL10_CH2)     ? pma_ctrl10_ch2_reg :
                  (reg_addr == PMA_CTRL10_CH3)     ? pma_ctrl10_ch3_reg :
                  (reg_addr == PMA_CTRL11_CH0)     ? pma_ctrl11_ch0_reg :
                  (reg_addr == PMA_CTRL11_CH1)     ? pma_ctrl11_ch1_reg :
                  (reg_addr == PMA_CTRL11_CH2)     ? pma_ctrl11_ch2_reg :
                  (reg_addr == PMA_CTRL11_CH3)     ? pma_ctrl11_ch3_reg :
                  (reg_addr == PMA_GLOBAL_CTRL0)   ? pma_global_ctrl0_reg :
                  (reg_addr == PMA_GLOBAL_CTRL1)   ? pma_global_ctrl1_reg :
                  (reg_addr == PMA_GLOBAL_CTRL2)   ? pma_global_ctrl2_reg :
                  (reg_addr == PMA_GLOBAL_CTRL3)   ? pma_global_ctrl3_reg :
                  (reg_addr == PMA_GLOBAL_CTRL4)   ? pma_global_ctrl4_reg :
                  (reg_addr == PMA_GLOBAL_CTRL5)   ? pma_global_ctrl5_reg :
                  (reg_addr == PMA_GLOBAL_CTRL6)   ? pma_global_ctrl6_reg :
                  (reg_addr == PMA_GLOBAL_CTRL7)   ? pma_global_ctrl7_reg :
                  (reg_addr == PMA_GLOBAL_CTRL8)   ? pma_global_ctrl8_reg :
                  (reg_addr == PMA_GLOBAL_CTRL9)   ? pma_global_ctrl9_reg :
                  16'h0000;


// EXTERNAL INPUTS FOR CONTROL REGISTERS
assign  xgxs_ctrl_ext = {1'b0, rs_lpbk_all, 2'b00, rpowerdown, 11'b00000000000};
//************************************************************************************
// Status registers
assign local_fault = tx_local_fault | rx_local_fault;
assign xgxs_stat1_reg = {8'h00, local_fault, 4'h0, xs_link_status, 2'b10};
assign xs_tx_local_fault = (dev_addr_0) ? tx_local_fault : rx_local_fault ;
assign xs_rx_local_fault = (dev_addr_0) ? rx_local_fault : tx_local_fault ;
assign xgxs_stat2_reg = {4'h8, xs_rx_local_fault, xs_tx_local_fault, 10'b0000000000};
assign xgxs_lane_stat_reg = {3'b000, align_status, 8'hc0, sync_status};
// ***********************************************************************************
// PCS CRAMs
assign  trunking_mode_ext = {1'b0, rphfifo_master_sel_tx, rphfifo_master_sel_rx, 
                             rendec_data_sel_tx, rendec_data_sel_rx, rnenbpin, rpllurst, 
                             rreset, rrsvd_cmu, rdeskewen, rindv_tx, rindv_rx};

assign  pcs_ctrl1_ch0_ext = {rtx_pipe_enable[0], rrx_pipe_enable[0], rpowdnr[0], rpowdnt[0],
                             rendec_tx[0], rendec_rx[0], r8b10b_enc_ibm_en[0], rmatchen[0],
                             r8b10b_dec_ibm_en_ch0, rforce_kchar[0], rforce_echar[0],
                             rlp20ben[0], rgenericfifo[0], rcascaded_8b10b_en_tx[0],
                             rcascaded_8b10b_en_rx[0]};
assign  pcs_ctrl1_ch1_ext = {rtx_pipe_enable[1], rrx_pipe_enable[1], rpowdnr[1], rpowdnt[1],
                             rendec_tx[1], rendec_rx[1], r8b10b_enc_ibm_en[1], rmatchen[1],
                             r8b10b_dec_ibm_en_ch1, rforce_kchar[1], rforce_echar[1],
                             rlp20ben[1], rgenericfifo[1], rcascaded_8b10b_en_tx[1],
                             rcascaded_8b10b_en_rx[1]};
assign  pcs_ctrl1_ch2_ext = {rtx_pipe_enable[2], rrx_pipe_enable[2], rpowdnr[2], rpowdnt[2],
                             rendec_tx[2], rendec_rx[2], r8b10b_enc_ibm_en[2], rmatchen[2],
                             r8b10b_dec_ibm_en_ch2, rforce_kchar[2], rforce_echar[2],
                             rlp20ben[2], rgenericfifo[2], rcascaded_8b10b_en_tx[2],
                             rcascaded_8b10b_en_rx[2]};
assign  pcs_ctrl1_ch3_ext = {rtx_pipe_enable[3], rrx_pipe_enable[3], rpowdnr[3], rpowdnt[3],
                             rendec_tx[3], rendec_rx[3], r8b10b_enc_ibm_en[3], rmatchen[3],
                             r8b10b_dec_ibm_en_ch3, rforce_kchar[3], rforce_echar[3],
                             rlp20ben[3], rgenericfifo[3], rcascaded_8b10b_en_tx[3],
                             rcascaded_8b10b_en_rx[3]};

assign  pcs_ctrl2_ch0_ext = {resync_badcg_en_ch0, rencdt_rising[0], rdis_rx_disp[0],
                             rcomp_pat_porn[0], rcomp_size_ch0, rcomp_pat_ch0[39:32]};
assign  pcs_ctrl2_ch1_ext = {resync_badcg_en_ch1, rencdt_rising[1], rdis_rx_disp[1],
                             rcomp_pat_porn[1], rcomp_size_ch1, rcomp_pat_ch1[39:32]};                             
assign  pcs_ctrl2_ch2_ext = {resync_badcg_en_ch2, rencdt_rising[2], rdis_rx_disp[2],
                             rcomp_pat_porn[2], rcomp_size_ch2, rcomp_pat_ch2[39:32]};
assign  pcs_ctrl2_ch3_ext = {resync_badcg_en_ch3, rencdt_rising[3], rdis_rx_disp[3],
                             rcomp_pat_porn[3], rcomp_size_ch3, rcomp_pat_ch3[39:32]};

assign  pcs_ctrl3_ch0_ext = {rcomp_pat_ch0[31:16]};
assign  pcs_ctrl3_ch1_ext = {rcomp_pat_ch1[31:16]};
assign  pcs_ctrl3_ch2_ext = {rcomp_pat_ch2[31:16]};
assign  pcs_ctrl3_ch3_ext = {rcomp_pat_ch3[31:16]};

assign  pcs_ctrl4_ch0_ext = {rcomp_pat_ch0[15:0]};
assign  pcs_ctrl4_ch1_ext = {rcomp_pat_ch1[15:0]};
assign  pcs_ctrl4_ch2_ext = {rcomp_pat_ch2[15:0]};
assign  pcs_ctrl4_ch3_ext = {rcomp_pat_ch3[15:0]};

assign  pcs_ctrl5_ch0_ext = {rrxfifo_dis[0], rtxfifo_dis[0], rib_force_disp[0],
                             rrundisp_ch0, rtxfifo_lowlatency_en[0], rrlv_en[0], rautobtalg_dis[0],
                             rsync_sm_dis[0], rib_inv_cd_ch0, rrxfifo_lowlatency_en[0]};
assign  pcs_ctrl5_ch1_ext = {rrxfifo_dis[1], rtxfifo_dis[1], rib_force_disp[1],
                             rrundisp_ch1, rtxfifo_lowlatency_en[1], rrlv_en[1], rautobtalg_dis[1],
                             rsync_sm_dis[1], rib_inv_cd_ch1, rrxfifo_lowlatency_en[1]};
assign  pcs_ctrl5_ch2_ext = {rrxfifo_dis[2], rtxfifo_dis[2], rib_force_disp[2],
                             rrundisp_ch2, rtxfifo_lowlatency_en[2], rrlv_en[2], rautobtalg_dis[2],
                             rsync_sm_dis[2], rib_inv_cd_ch2, rrxfifo_lowlatency_en[2]};
assign  pcs_ctrl5_ch3_ext = {rrxfifo_dis[3], rtxfifo_dis[3], rib_force_disp[3],
                             rrundisp_ch3, rtxfifo_lowlatency_en[3], rrlv_en[3], rautobtalg_dis[3],
                             rsync_sm_dis[3], rib_inv_cd_ch3, rrxfifo_lowlatency_en[3]};

assign  pcs_ctrl6_ch0_ext = {rdwidth_tx[0], rdwidth_rx[0], rge_xaui_tx[0],
                             rrx_detect_bypass[0], rtxurstpcs[0], rrxurstpcs[0],
                             rrsvd_tx_ch0, rskpsetbased[0], rtruebac2bac[0],rrsvd_rx_ch0};
assign  pcs_ctrl6_ch1_ext = {rdwidth_tx[1], rdwidth_rx[1], rge_xaui_tx[1],
                             rrx_detect_bypass[1], rtxurstpcs[1], rrxurstpcs[1],
                             rrsvd_tx_ch1, rskpsetbased[1], rtruebac2bac[1],rrsvd_rx_ch1};
assign  pcs_ctrl6_ch2_ext = {rdwidth_tx[2], rdwidth_rx[2], rge_xaui_tx[2],
                             rrx_detect_bypass[2], rtxurstpcs[2], rrxurstpcs[2],
                             rrsvd_tx_ch2, rskpsetbased[2], rtruebac2bac[2],rrsvd_rx_ch2};
assign  pcs_ctrl6_ch3_ext = {rdwidth_tx[3], rdwidth_rx[3], rge_xaui_tx[3],
                             rrx_detect_bypass[3], rtxurstpcs[3], rrxurstpcs[3],
                             rrsvd_tx_ch3, rskpsetbased[3], rtruebac2bac[3],rrsvd_rx_ch3};

assign  pcs_ctrl7_ch0_ext = {rgnumber_ch0, rknumber_ch0};
assign  pcs_ctrl7_ch1_ext = {rgnumber_ch1, rknumber_ch1};
assign  pcs_ctrl7_ch2_ext = {rgnumber_ch2, rknumber_ch2};
assign  pcs_ctrl7_ch3_ext = {rgnumber_ch3, rknumber_ch3};

assign  pcs_ctrl8_ch0_ext = {rfreerun_tx[0], rtxwrclksel[0], rtxrdclksel[0],
                             rfreerun_rx[0], rrcvd_clk_sel_ch0, 
                             rclk_1_sel_ch0, rclk_2_sel_ch0, rrx_rd_clk_sel[0], 
                             renumber_ch0, renpolinv_rx[0], rclkcmpinsertpad[0]};
assign  pcs_ctrl8_ch1_ext = {rfreerun_tx[1], rtxwrclksel[1], rtxrdclksel[1],
                             rfreerun_rx[1], rrcvd_clk_sel_ch1, 
                             rclk_1_sel_ch1, rclk_2_sel_ch1, rrx_rd_clk_sel[1], 
                             renumber_ch1, renpolinv_rx[1], rclkcmpinsertpad[1]};
assign  pcs_ctrl8_ch2_ext = {rfreerun_tx[2], rtxwrclksel[2], rtxrdclksel[2],
                             rfreerun_rx[2], rrcvd_clk_sel_ch2, 
                             rclk_1_sel_ch2, rclk_2_sel_ch2, rrx_rd_clk_sel[2], 
                             renumber_ch2, renpolinv_rx[2], rclkcmpinsertpad[2]};
assign  pcs_ctrl8_ch3_ext = {rfreerun_tx[3], rtxwrclksel[3], rtxrdclksel[3],
                             rfreerun_rx[3], rrcvd_clk_sel_ch3, 
                             rclk_1_sel_ch3, rclk_2_sel_ch3, rrx_rd_clk_sel[3], 
                             renumber_ch3, renpolinv_rx[3], rclkcmpinsertpad[3]};

assign  prbs_bist_ctrl_ch0_ext = {rprbsen_tx[0], rprbsen_rx[0], rprbs_clr_rslt_rx[0],
                                  rprbs_sel_ch0, rbisten_tx[0], rbisten_rx[0],
                                  rbist_clr_rx[0], rbist_sel_ch0,
                                  rcxpat_chnl_en_ch0, rall_one_dect_only[0], 2'b00};
assign  prbs_bist_ctrl_ch1_ext = {rprbsen_tx[1], rprbsen_rx[1], rprbs_clr_rslt_rx[1],
                                  rprbs_sel_ch1, rbisten_tx[1], rbisten_rx[1],
                                  rbist_clr_rx[1], rbist_sel_ch1,
                                  rcxpat_chnl_en_ch1, rall_one_dect_only[1], 2'b00};
assign  prbs_bist_ctrl_ch2_ext = {rprbsen_tx[2], rprbsen_rx[2], rprbs_clr_rslt_rx[2],
                                  rprbs_sel_ch2, rbisten_tx[2], rbisten_rx[2],
                                  rbist_clr_rx[2], rbist_sel_ch2,
                                  rcxpat_chnl_en_ch2, rall_one_dect_only[2], 2'b00};
assign  prbs_bist_ctrl_ch3_ext = {rprbsen_tx[3], rprbsen_rx[3], rprbs_clr_rslt_rx[3],
                                  rprbs_sel_ch3, rbisten_tx[3], rbisten_rx[3],
                                  rbist_clr_rx[3], rbist_sel_ch3,
                                  rcxpat_chnl_en_ch3, rall_one_dect_only[3], 2'b00};

assign  pcs_ctrl9_ch0_ext = {rppm_cnt_reset[0], rphfifourstrx[0], rcmpfifourst[0], rtx_idle_delay_ch0, 
                             rclkcmpsqmd[0], rclkcmpsq1p_ch0[9:0]};
assign  pcs_ctrl9_ch1_ext = {rppm_cnt_reset[1], rphfifourstrx[1], rcmpfifourst[1], rtx_idle_delay_ch1, 
                             rclkcmpsqmd[1], rclkcmpsq1p_ch1[9:0]};
assign  pcs_ctrl9_ch2_ext = {rppm_cnt_reset[2], rphfifourstrx[2], rcmpfifourst[2], rtx_idle_delay_ch2, 
                             rclkcmpsqmd[2], rclkcmpsq1p_ch2[9:0]};
assign  pcs_ctrl9_ch3_ext = {rppm_cnt_reset[3], rphfifourstrx[3], rcmpfifourst[3], rtx_idle_delay_ch3, 
                             rclkcmpsqmd[3], rclkcmpsq1p_ch3[9:0]};

assign  pcs_ctrl10_ch0_ext = {rclkcmpsq1n_ch0[19:15], rclkcmppos[0], rclkcmpsq1p_ch0[19:10]};
assign  pcs_ctrl10_ch1_ext = {rclkcmpsq1n_ch1[19:15], rclkcmppos[1], rclkcmpsq1p_ch1[19:10]};
assign  pcs_ctrl10_ch2_ext = {rclkcmpsq1n_ch2[19:15], rclkcmppos[2], rclkcmpsq1p_ch2[19:10]};
assign  pcs_ctrl10_ch3_ext = {rclkcmpsq1n_ch3[19:15], rclkcmppos[3], rclkcmpsq1p_ch3[19:10]};

assign  pcs_ctrl11_ch0_ext = {rclkcmpsq1n_ch0[14:10], 1'b0, rclkcmpsq1n_ch0[9:0]};
assign  pcs_ctrl11_ch1_ext = {rclkcmpsq1n_ch1[14:10], 1'b0, rclkcmpsq1n_ch1[9:0]};
assign  pcs_ctrl11_ch2_ext = {rclkcmpsq1n_ch2[14:10], 1'b0, rclkcmpsq1n_ch2[9:0]};
assign  pcs_ctrl11_ch3_ext = {rclkcmpsq1n_ch3[14:10], 1'b0, rclkcmpsq1n_ch3[9:0]};

assign  pcs_ctrl12_ch0_ext = {rrev_loopbk[0], ralempty_ch0, ralfull_ch0, rforce_disp[0], 
                              rkchar[0], rosbased[0], rensymswap_tx[0], 1'b0, rosnumber_ch0};
assign  pcs_ctrl12_ch1_ext = {rrev_loopbk[1], ralempty_ch1, ralfull_ch1, rforce_disp[1],
                              rkchar[1], rosbased[1], rensymswap_tx[1], 1'b0, rosnumber_ch1};
assign  pcs_ctrl12_ch2_ext = {rrev_loopbk[2], ralempty_ch2, ralfull_ch2, rforce_disp[2],
                              rkchar[2], rosbased[2], rensymswap_tx[2], 1'b0, rosnumber_ch2};
assign  pcs_ctrl12_ch3_ext = {rrev_loopbk[3], ralempty_ch3, ralfull_ch3, rforce_disp[3],
                              rkchar[3], rosbased[3], rensymswap_tx[3], 1'b0, rosnumber_ch3};

assign  pcs_ctrl13_ch0_ext = {rwa_6g_en[0], renpolinv_tx[0], rbitslip_size_ch0, rbytord_2sym_en[0],
                              rbysync_polinv_en[0], rbitloc_rev_en[0], rbyte_rev_en[0], renbitrev_tx[0],
                              rbyteorden_ch0, rbytordplden[0], rphfifopldentx[0], rphfifoursttx[0],
                              rphfifopldenrx[0], rautoinsdis[0]};
assign  pcs_ctrl13_ch1_ext = {rwa_6g_en[1], renpolinv_tx[1], rbitslip_size_ch1, rbytord_2sym_en[1],
                              rbysync_polinv_en[1], rbitloc_rev_en[1], rbyte_rev_en[1], renbitrev_tx[1],
                              rbyteorden_ch1, rbytordplden[1], rphfifopldentx[1], rphfifoursttx[1],
                              rphfifopldenrx[1], rautoinsdis[1]};
assign  pcs_ctrl13_ch2_ext = {rwa_6g_en[2], renpolinv_tx[2], rbitslip_size_ch2, rbytord_2sym_en[2],
                              rbysync_polinv_en[2], rbitloc_rev_en[2], rbyte_rev_en[2], renbitrev_tx[2],
                              rbyteorden_ch2, rbytordplden[2], rphfifopldentx[2], rphfifoursttx[2],
                              rphfifopldenrx[2], rautoinsdis[2]};
assign  pcs_ctrl13_ch3_ext = {rwa_6g_en[3], renpolinv_tx[3], rbitslip_size_ch3, rbytord_2sym_en[3],
                              rbysync_polinv_en[3], rbitloc_rev_en[3], rbyte_rev_en[3], renbitrev_tx[3],
                              rbyteorden_ch3, rbytordplden[3], rphfifopldentx[3], rphfifoursttx[3],
                              rphfifopldenrx[3], rautoinsdis[3]};

assign  pcs_ctrl14_ch0_ext = {rppmsel_ch0, rbytordpat_ch0};
assign  pcs_ctrl14_ch1_ext = {rppmsel_ch1, rbytordpat_ch1};
assign  pcs_ctrl14_ch2_ext = {rppmsel_ch2, rbytordpat_ch2};
assign  pcs_ctrl14_ch3_ext = {rppmsel_ch3, rbytordpat_ch3};

assign  pcs_ctrl15_ch0_ext = {rtest_bus_sel_ch0, rforce_sig_det_pcs[0], rforce0_freqdet[0], 
                              rforce1_freqdet[0], rbytordpad_ch0};
assign  pcs_ctrl15_ch1_ext = {rtest_bus_sel_ch1, rforce_sig_det_pcs[1], rforce0_freqdet[1], 
                              rforce1_freqdet[1], rbytordpad_ch1};
assign  pcs_ctrl15_ch2_ext = {rtest_bus_sel_ch2, rforce_sig_det_pcs[2], rforce0_freqdet[2], 
                              rforce1_freqdet[2], rbytordpad_ch2};
assign  pcs_ctrl15_ch3_ext = {rtest_bus_sel_ch3, rforce_sig_det_pcs[3], rforce0_freqdet[3], 
                              rforce1_freqdet[3], rbytordpad_ch3};

assign  pcs_global_ctrl0_ext = {9'b000000000, ralgnect, ralgngct, ralgnact};
assign  pcs_global_ctrl1_ext = {rfreerun_centrl, rcentrl_clk_sel, 2'b00, rrefclk_out_div2, rdskposdisp, rdskchrp};
assign  pcs_global_ctrl2_ext = {2'b00, ralgnopt, rtest_bus_centrl_sel, 10'b0000000000};

// Analog CRAMs
assign  pma_ctrl1_ch0_ext = {rtx_vod_sel_ch0, rtx_slewrate[0], rpmphs_2tap_ch0,
                             rpmphs_1tap_ch0, rtx_vtt_ch0, rpmphs_ptap_ch0};
assign  pma_ctrl1_ch1_ext = {rtx_vod_sel_ch1, rtx_slewrate[1], rpmphs_2tap_ch1,
                             rpmphs_1tap_ch1, rtx_vtt_ch1, rpmphs_ptap_ch1};
assign  pma_ctrl1_ch2_ext = {rtx_vod_sel_ch2, rtx_slewrate[2], rpmphs_2tap_ch2,
                             rpmphs_1tap_ch2, rtx_vtt_ch2, rpmphs_ptap_ch2};
assign  pma_ctrl1_ch3_ext = {rtx_vod_sel_ch3, rtx_slewrate[3], rpmphs_2tap_ch3,
                             rpmphs_1tap_ch3, rtx_vtt_ch3, rpmphs_ptap_ch3};

assign  pma_ctrl2_ch0_ext = {rtx_term_ch0, r_tx_det_rx_ch0, rrx_term_ch0, rforce_sigdet[0],
                             rrx_dc_couple[0], rrx_eq_dc_ch0, rrx_vtt_ch0, rrx_sloslv_ch0};
assign  pma_ctrl2_ch1_ext = {rtx_term_ch1, r_tx_det_rx_ch1, rrx_term_ch1, rforce_sigdet[1],
                             rrx_dc_couple[1], rrx_eq_dc_ch1, rrx_vtt_ch1, rrx_sloslv_ch1};
assign  pma_ctrl2_ch2_ext = {rtx_term_ch2, r_tx_det_rx_ch2, rrx_term_ch2, rforce_sigdet[2],
                             rrx_dc_couple[2], rrx_eq_dc_ch2, rrx_vtt_ch2, rrx_sloslv_ch2};
assign  pma_ctrl2_ch3_ext = {rtx_term_ch3, r_tx_det_rx_ch3, rrx_term_ch3, rforce_sigdet[3],
                             rrx_dc_couple[3], rrx_eq_dc_ch3, rrx_vtt_ch3, rrx_sloslv_ch3};
                             
assign  pma_ctrl3_ch0_ext = {reqa_ct_ch0, reqb_ct_ch0, reqc_ct_ch0, reqd_ct_ch0, req_ctv_ch0, 1'b0};
assign  pma_ctrl3_ch1_ext = {reqa_ct_ch1, reqb_ct_ch1, reqc_ct_ch1, reqd_ct_ch1, req_ctv_ch1, 1'b0};
assign  pma_ctrl3_ch2_ext = {reqa_ct_ch2, reqb_ct_ch2, reqc_ct_ch2, reqd_ct_ch2, req_ctv_ch2, 1'b0};
assign  pma_ctrl3_ch3_ext = {reqa_ct_ch3, reqb_ct_ch3, reqc_ct_ch3, reqd_ct_ch3, req_ctv_ch3, 1'b0};

assign  pma_ctrl4_ch0_ext = {rpmadwidth_tx[0], rpma_doublewidth_tx[0], rtx_cmu_sel[0],
                             rtx_m_sel_ch0, rtxvcobypass[0], rtx_cgb_1x_en[0], rtx_cgb_4x_en[0],
                             rtx_4x_sw[0], rpmadwidth_rx[0], rpma_doublewidth_rx[0],
                             rrxvcobypass[0],rrect_adj_ch0, rrx_piso_bypass_ch0};
assign  pma_ctrl4_ch1_ext = {rpmadwidth_tx[1], rpma_doublewidth_tx[1], rtx_cmu_sel[1],
                             rtx_m_sel_ch1, rtxvcobypass[1], rtx_cgb_1x_en[1], rtx_cgb_4x_en[1],
                             rtx_4x_sw[1], rpmadwidth_rx[1], rpma_doublewidth_rx[1],
                             rrxvcobypass[1],rrect_adj_ch1, rrx_piso_bypass_ch1};
assign  pma_ctrl4_ch2_ext = {rpmadwidth_tx[2], rpma_doublewidth_tx[2], rtx_cmu_sel[2],
                             rtx_m_sel_ch2, rtxvcobypass[2], rtx_cgb_1x_en[2], rtx_cgb_4x_en[2],
                             rtx_4x_sw[2], rpmadwidth_rx[2], rpma_doublewidth_rx[2],
                             rrxvcobypass[2],rrect_adj_ch2, rrx_piso_bypass_ch2};
assign  pma_ctrl4_ch3_ext = {rpmadwidth_tx[3], rpma_doublewidth_tx[3], rtx_cmu_sel[3],
                             rtx_m_sel_ch3, rtxvcobypass[3], rtx_cgb_1x_en[3], rtx_cgb_4x_en[3],
                             rtx_4x_sw[3], rpmadwidth_rx[3], rpma_doublewidth_rx[3],
                             rrxvcobypass[3],rrect_adj_ch3, rrx_piso_bypass_ch3};

assign  pma_ctrl5_ch0_ext = {rlst_tx_ch0, rlst_rx_ch0, rlst_rxpll_ch0, rrx_ignore_phslck[0],
                             rdc_freq_ch0, rrx_osc_en[0]};
assign  pma_ctrl5_ch1_ext = {rlst_tx_ch1, rlst_rx_ch1, rlst_rxpll_ch1, rrx_ignore_phslck[1],
                             rdc_freq_ch1, rrx_osc_en[1]};
assign  pma_ctrl5_ch2_ext = {rlst_tx_ch2, rlst_rx_ch2, rlst_rxpll_ch2, rrx_ignore_phslck[2],
                             rdc_freq_ch2, rrx_osc_en[2]};
assign  pma_ctrl5_ch3_ext = {rlst_tx_ch3, rlst_rx_ch3, rlst_rxpll_ch3, rrx_ignore_phslck[3],
                             rdc_freq_ch3, rrx_osc_en[3]};

assign  pma_ctrl6_ch0_ext = {rrefclk_sel_ch0, rbwctral_rx_ch0, rrx_cru_m_sel_ch0, 
                             rrx_cru_div2[0], rrx_cru_ctl_ch0, rltr[0], rltd[0]};
assign  pma_ctrl6_ch1_ext = {rrefclk_sel_ch1, rbwctral_rx_ch1, rrx_cru_m_sel_ch1, 
                             rrx_cru_div2[1], rrx_cru_ctl_ch1, rltr[1], rltd[1]};
assign  pma_ctrl6_ch2_ext = {rrefclk_sel_ch2, rbwctral_rx_ch2, rrx_cru_m_sel_ch2, 
                             rrx_cru_div2[2], rrx_cru_ctl_ch2, rltr[2], rltd[2]};
assign  pma_ctrl6_ch3_ext = {rrefclk_sel_ch3, rbwctral_rx_ch3, rrx_cru_m_sel_ch3, 
                             rrx_cru_div2[3], rrx_cru_ctl_ch3, rltr[3], rltd[3]};

assign  pma_ctrl7_ch0_ext = {risel_rx_ch0, riupsel_rx_ch0, ridnsel_rx_ch0,
                             rtesten_cp_rx[0], rtristate_cp_rx[0], rtestupen_cp_rx[0],
                             rtestdnen_cp_rx[0], rrx_cru_m_ch0, rrx_cru_l_ch0};
assign  pma_ctrl7_ch1_ext = {risel_rx_ch1, riupsel_rx_ch1, ridnsel_rx_ch1,
                             rtesten_cp_rx[1], rtristate_cp_rx[1], rtestupen_cp_rx[1],
                             rtestdnen_cp_rx[1], rrx_cru_m_ch1, rrx_cru_l_ch1};
assign  pma_ctrl7_ch2_ext = {risel_rx_ch2, riupsel_rx_ch2, ridnsel_rx_ch2,
                             rtesten_cp_rx[2], rtristate_cp_rx[2], rtestupen_cp_rx[2],
                             rtestdnen_cp_rx[2], rrx_cru_m_ch2, rrx_cru_l_ch2};
assign  pma_ctrl7_ch3_ext = {risel_rx_ch3, riupsel_rx_ch3, ridnsel_rx_ch3,
                             rtesten_cp_rx[3], rtristate_cp_rx[3], rtestupen_cp_rx[3],
                             rtestdnen_cp_rx[3], rrx_cru_m_ch3, rrx_cru_l_ch3};
                             
assign  pma_ctrl8_ch0_ext = {rs_lpbk[0], r_rlpbk[0], rs_rdlpbk[0], rrx_revlb_sw[0],
                             rurx_pdb[0], rtx_cgb_pdb[0], rtx_ob_pdb[0], rrx_cru_pdb[0],
                             rrx_cru_rst[0], rrx_ib_pdb[0], rrxurstpma[0], radce_adapt[0],
                             radce_pdb[0], radce_rst[0], rsig_inv_2tap[0], rsig_inv_pre[0]};
assign  pma_ctrl8_ch1_ext = {rs_lpbk[1], r_rlpbk[1], rs_rdlpbk[1], rrx_revlb_sw[1],
                             rurx_pdb[1], rtx_cgb_pdb[1], rtx_ob_pdb[1], rrx_cru_pdb[1],
                             rrx_cru_rst[1], rrx_ib_pdb[1], rrxurstpma[1], radce_adapt[1],
                             radce_pdb[1], radce_rst[1], rsig_inv_2tap[1], rsig_inv_pre[1]};
assign  pma_ctrl8_ch2_ext = {rs_lpbk[2], r_rlpbk[2], rs_rdlpbk[2], rrx_revlb_sw[2],
                             rurx_pdb[2], rtx_cgb_pdb[2], rtx_ob_pdb[2], rrx_cru_pdb[2],
                             rrx_cru_rst[2], rrx_ib_pdb[2], rrxurstpma[2], radce_adapt[2],
                             radce_pdb[2], radce_rst[2], rsig_inv_2tap[2], rsig_inv_pre[2]};
assign  pma_ctrl8_ch3_ext = {rs_lpbk[3], r_rlpbk[3], rs_rdlpbk[3], rrx_revlb_sw[3],
                             rurx_pdb[3], rtx_cgb_pdb[3], rtx_ob_pdb[3], rrx_cru_pdb[3],
                             rrx_cru_rst[3], rrx_ib_pdb[3], rrxurstpma[3], radce_adapt[3],
                             radce_pdb[3], radce_rst[3], rsig_inv_2tap[3], rsig_inv_pre[3]};

assign  pma_ctrl9_ch0_ext = {rseq_sel_ch0, rrgen_set_ch0, rclkdiv_ch0, rf_lpf_ch0, 
                             rf_hpf_ch0, rrgen_bw_ch0, 1'b0};
assign  pma_ctrl9_ch1_ext = {rseq_sel_ch1, rrgen_set_ch1, rclkdiv_ch1, rf_lpf_ch1, 
                             rf_hpf_ch1, rrgen_bw_ch1, 1'b0};
assign  pma_ctrl9_ch2_ext = {rseq_sel_ch2, rrgen_set_ch2, rclkdiv_ch2, rf_lpf_ch2, 
                             rf_hpf_ch2, rrgen_bw_ch2, 1'b0};
assign  pma_ctrl9_ch3_ext = {rseq_sel_ch3, rrgen_set_ch3, rclkdiv_ch3, rf_lpf_ch3, 
                             rf_hpf_ch3, rrgen_bw_ch3, 1'b0};

assign  pma_ctrl10_ch0_ext= {rhyst_ch0, rd2a_res_ch0, rrgen_vod_ch0,
                             rlf_os_ch0, rhf_os_ch0};
assign  pma_ctrl10_ch1_ext= {rhyst_ch1, rd2a_res_ch1, rrgen_vod_ch1,
                             rlf_os_ch1, rhf_os_ch1};
assign  pma_ctrl10_ch2_ext= {rhyst_ch2, rd2a_res_ch2, rrgen_vod_ch2,
                             rlf_os_ch2, rhf_os_ch2};
assign  pma_ctrl10_ch3_ext= {rhyst_ch3, rd2a_res_ch3, rrgen_vod_ch3,
                             rlf_os_ch3, rhf_os_ch3};

assign  pma_ctrl11_ch0_ext= {r_iqclk_ch0, r_dfe_ch0, r_cp_mode[0], rreg_cp_rx[0], r_impctrl_ch0, rpd_ien[0], 1'b0};
assign  pma_ctrl11_ch1_ext= {r_iqclk_ch1, r_dfe_ch1, r_cp_mode[1], rreg_cp_rx[1], r_impctrl_ch1, rpd_ien[1], 1'b0};
assign  pma_ctrl11_ch2_ext= {r_iqclk_ch2, r_dfe_ch2, r_cp_mode[2], rreg_cp_rx[2], r_impctrl_ch2, rpd_ien[2], 1'b0};
assign  pma_ctrl11_ch3_ext= {r_iqclk_ch3, r_dfe_ch3, r_cp_mode[3], rreg_cp_rx[3], r_impctrl_ch3, rpd_ien[3], 1'b0};

assign  pma_global_ctrl0_ext = {rbgbypass, 1'b0, rlst_bg, rcmu_rst, 3'b000,
                                rcmu2_isel, rcmu0_isel, rcmu1_isel};
assign  pma_global_ctrl1_ext = {rcmu0_iupsel, rcmu1_iupsel, rcmu2_iupsel, rcmu0_idnsel, rcmu1_idnsel, rcmu2_idnsel,
                                rcmu0_testen_cp, rcmu1_testen_cp, rcmu0_tristate_cp, rcmu1_tristate_cp};
assign  pma_global_ctrl2_ext = {2'b00, rcmu0_lst, rcmu1_lst,
                                rcmu0_div2, rcmu1_div2, rcmu0_ref_sel, rcmu1_ref_sel};
assign  pma_global_ctrl3_ext = {rcmu0_ctl, rcmu1_ctl};
assign  pma_global_ctrl4_ext = {rcmu0_m, rcmu1_m, rcmu0_l, rcmu1_l, rcmu0_pdb, rcmu1_pdb,
                                rcmu0_txpll_rst, rcmu1_txpll_rst};
assign  pma_global_ctrl5_ext = {rpma_testbus_sel, rcmu_peclrx0_cm, rcmu_peclrx1_cm,
                                rcmu0_testupen_cp, rcmu1_testupen_cp, rcmu0_testdnen_cp, rcmu1_testdnen_cp};                                
assign  pma_global_ctrl6_ext = {rcmu_peclrx0_lst, rcmu_peclrx1_lst, 1'b0, rcmu_iqclkout_sel,
                                rcmu_txpll0_iqclkin_sel, rcmu_txpll1_iqclkin_sel};
assign  pma_global_ctrl7_ext = {rcmu_cgb_cmusel, rcmu_cgb_ndiv, rcmu_cgb_div5, rcmu_cgb_div2,
                                rcmu_cgb_vcobypass, rcmu_txpll0_1x_en, rcmu_txpll1_1x_en, 
                                rcmu_cgb_4x_en, rcmu_cgb_8x_en, rcmu_cgb_pclksel, 4'b0000};
assign  pma_global_ctrl8_ext = {rcmu2_testen_cp, rcmu2_tristate_cp, rcmu2_testupen_cp,
                                rcmu2_testdnen_cp, rcmu2_lst, rcmu2_ctl};
assign  pma_global_ctrl9_ext = {rcmu2_refsel, rcmu2_m, rcmu2_l, rcmu2_pdb, rcmu2_txpll_rst, 
                                rcmu0_rcp_mode, rcmu1_rcp_mode, 5'b00000};                              

// OUTPUT CRAMS FROM CONTROL REGISTERS
// PCS CRAMs
// Outputs from DTE XG Control register (4.0h)
assign rs_lpbk_all_md = xgxs_ctrl_reg[14];
assign rpowerdown_md  = xgxs_ctrl_reg[11];

// Outputs from Trunking mode Control register (4.8000h)
assign rphfifo_master_sel_tx_int = trunking_mode_reg[14];
assign rphfifo_master_sel_rx_int = trunking_mode_reg[13];
assign rendec_data_sel_tx_int    = trunking_mode_reg[12];
assign rendec_data_sel_rx_int    = trunking_mode_reg[11];
assign rnenbpin_md               = trunking_mode_reg[10];
assign rpllurst_md               = trunking_mode_reg[9];
assign rreset_md                 = trunking_mode_reg[8];
assign rrsvd_cmu_int             = trunking_mode_reg[7:3];
assign rdeskewen_int             = trunking_mode_reg[2];
assign rindv_tx_int              = trunking_mode_reg[1];
assign rindv_rx_int              = trunking_mode_reg[0];

// Outputs from PCS Per channel control register 1 for channel0 (4.8001h)
assign rtx_pipe_enable_int[0]   = pcs_ctrl1_ch0_reg[15];
assign rrx_pipe_enable_int[0]   = pcs_ctrl1_ch0_reg[14];
assign rpowdnr_md[0]            = pcs_ctrl1_ch0_reg[13];
assign rpowdnt_md[0]            = pcs_ctrl1_ch0_reg[12];
assign rendec_tx_int[0]         = pcs_ctrl1_ch0_reg[11];
assign rendec_rx_int[0]         = pcs_ctrl1_ch0_reg[10];
assign r8b10b_enc_ibm_en_int[0] = pcs_ctrl1_ch0_reg[9];
assign rmatchen_int[0]          = pcs_ctrl1_ch0_reg[8];
assign r8b10b_dec_ibm_en_ch0_int= pcs_ctrl1_ch0_reg[7:6];
assign rforce_kchar_int[0]      = pcs_ctrl1_ch0_reg[5];
assign rforce_echar_int[0]      = pcs_ctrl1_ch0_reg[4];
assign rlp20ben_int[0]          = pcs_ctrl1_ch0_reg[3];
assign rgenericfifo_int[0]      = pcs_ctrl1_ch0_reg[2];
assign rcascaded_8b10b_en_tx_int[0] = pcs_ctrl1_ch0_reg[1];
assign rcascaded_8b10b_en_rx_int[0] = pcs_ctrl1_ch0_reg[0];

// Outputs from PCS Per channel control register 1 for channel1 (4.8002h)
assign rtx_pipe_enable_int[1]   = pcs_ctrl1_ch1_reg[15];
assign rrx_pipe_enable_int[1]   = pcs_ctrl1_ch1_reg[14];
assign rpowdnr_md[1]            = pcs_ctrl1_ch1_reg[13];
assign rpowdnt_md[1]            = pcs_ctrl1_ch1_reg[12];
assign rendec_tx_int[1]         = pcs_ctrl1_ch1_reg[11];
assign rendec_rx_int[1]         = pcs_ctrl1_ch1_reg[10];
assign r8b10b_enc_ibm_en_int[1] = pcs_ctrl1_ch1_reg[9];
assign rmatchen_int[1]          = pcs_ctrl1_ch1_reg[8];
assign r8b10b_dec_ibm_en_ch1_int= pcs_ctrl1_ch1_reg[7:6];
assign rforce_kchar_int[1]      = pcs_ctrl1_ch1_reg[5];
assign rforce_echar_int[1]      = pcs_ctrl1_ch1_reg[4];
assign rlp20ben_int[1]          = pcs_ctrl1_ch1_reg[3];
assign rgenericfifo_int[1]      = pcs_ctrl1_ch1_reg[2];
assign rcascaded_8b10b_en_tx_int[1] = pcs_ctrl1_ch1_reg[1];
assign rcascaded_8b10b_en_rx_int[1] = pcs_ctrl1_ch1_reg[0];

// Outputs from PCS Per channel control register 1 for channel2 (4.8003h)
assign rtx_pipe_enable_int[2]   = pcs_ctrl1_ch2_reg[15];
assign rrx_pipe_enable_int[2]   = pcs_ctrl1_ch2_reg[14];
assign rpowdnr_md[2]            = pcs_ctrl1_ch2_reg[13];
assign rpowdnt_md[2]            = pcs_ctrl1_ch2_reg[12];
assign rendec_tx_int[2]         = pcs_ctrl1_ch2_reg[11];
assign rendec_rx_int[2]         = pcs_ctrl1_ch2_reg[10];
assign r8b10b_enc_ibm_en_int[2] = pcs_ctrl1_ch2_reg[9];
assign rmatchen_int[2]          = pcs_ctrl1_ch2_reg[8];
assign r8b10b_dec_ibm_en_ch2_int= pcs_ctrl1_ch2_reg[7:6];
assign rforce_kchar_int[2]      = pcs_ctrl1_ch2_reg[5];
assign rforce_echar_int[2]      = pcs_ctrl1_ch2_reg[4];
assign rlp20ben_int[2]          = pcs_ctrl1_ch2_reg[3];
assign rgenericfifo_int[2]      = pcs_ctrl1_ch2_reg[2];
assign rcascaded_8b10b_en_tx_int[2] = pcs_ctrl1_ch2_reg[1];
assign rcascaded_8b10b_en_rx_int[2] = pcs_ctrl1_ch2_reg[0];

// Outputs from PCS Per channel control register 1 for channel3 (4.8004h)
assign rtx_pipe_enable_int[3]   = pcs_ctrl1_ch3_reg[15];
assign rrx_pipe_enable_int[3]   = pcs_ctrl1_ch3_reg[14];
assign rpowdnr_md[3]            = pcs_ctrl1_ch3_reg[13];
assign rpowdnt_md[3]            = pcs_ctrl1_ch3_reg[12];
assign rendec_tx_int[3]         = pcs_ctrl1_ch3_reg[11];
assign rendec_rx_int[3]         = pcs_ctrl1_ch3_reg[10];
assign r8b10b_enc_ibm_en_int[3] = pcs_ctrl1_ch3_reg[9];
assign rmatchen_int[3]          = pcs_ctrl1_ch3_reg[8];
assign r8b10b_dec_ibm_en_ch3_int= pcs_ctrl1_ch3_reg[7:6];
assign rforce_kchar_int[3]      = pcs_ctrl1_ch3_reg[5];
assign rforce_echar_int[3]      = pcs_ctrl1_ch3_reg[4];
assign rlp20ben_int[3]          = pcs_ctrl1_ch3_reg[3];
assign rgenericfifo_int[3]      = pcs_ctrl1_ch3_reg[2];
assign rcascaded_8b10b_en_tx_int[3] = pcs_ctrl1_ch3_reg[1];
assign rcascaded_8b10b_en_rx_int[3] = pcs_ctrl1_ch3_reg[0];

// Outputs from PCS Per channel control register 2 for channel0 (4.8005h)
assign resync_badcg_en_ch0_int  = pcs_ctrl2_ch0_reg[15:14];
assign rencdt_rising_int[0]     = pcs_ctrl2_ch0_reg[13];
assign rdis_rx_disp_int[0]      = pcs_ctrl2_ch0_reg[12];
assign rcomp_pat_porn_int[0]    = pcs_ctrl2_ch0_reg[11];
assign rcomp_size_ch0_int       = pcs_ctrl2_ch0_reg[10:8];
assign rcomp_pat_ch0_int[39:32] = pcs_ctrl2_ch0_reg[7:0];

// Outputs from PCS Per channel control register 2 for channel1 (4.8006h)
assign resync_badcg_en_ch1_int  = pcs_ctrl2_ch1_reg[15:14];
assign rencdt_rising_int[1]     = pcs_ctrl2_ch1_reg[13];
assign rdis_rx_disp_int[1]      = pcs_ctrl2_ch1_reg[12];
assign rcomp_pat_porn_int[1]    = pcs_ctrl2_ch1_reg[11];
assign rcomp_size_ch1_int       = pcs_ctrl2_ch1_reg[10:8];
assign rcomp_pat_ch1_int[39:32] = pcs_ctrl2_ch1_reg[7:0];

// Outputs from PCS Per channel control register 2 for channel2 (4.8007h)
assign resync_badcg_en_ch2_int  = pcs_ctrl2_ch2_reg[15:14];
assign rencdt_rising_int[2]     = pcs_ctrl2_ch2_reg[13];
assign rdis_rx_disp_int[2]      = pcs_ctrl2_ch2_reg[12];
assign rcomp_pat_porn_int[2]    = pcs_ctrl2_ch2_reg[11];
assign rcomp_size_ch2_int       = pcs_ctrl2_ch2_reg[10:8];
assign rcomp_pat_ch2_int[39:32] = pcs_ctrl2_ch2_reg[7:0];

// Outputs from PCS Per channel control register 2 for channel3 (4.8008h)
assign resync_badcg_en_ch3_int  = pcs_ctrl2_ch3_reg[15:14];
assign rencdt_rising_int[3]     = pcs_ctrl2_ch3_reg[13];
assign rdis_rx_disp_int[3]      = pcs_ctrl2_ch3_reg[12];
assign rcomp_pat_porn_int[3]    = pcs_ctrl2_ch3_reg[11];
assign rcomp_size_ch3_int       = pcs_ctrl2_ch3_reg[10:8];
assign rcomp_pat_ch3_int[39:32] = pcs_ctrl2_ch3_reg[7:0];

// Outputs from PCS Per channel control register 3 for channel0,1,2,3 (4.8009h-800Ch)
assign rcomp_pat_ch0_int[31:16] = pcs_ctrl3_ch0_reg;
assign rcomp_pat_ch1_int[31:16] = pcs_ctrl3_ch1_reg;
assign rcomp_pat_ch2_int[31:16] = pcs_ctrl3_ch2_reg;
assign rcomp_pat_ch3_int[31:16] = pcs_ctrl3_ch3_reg;

// Outputs from PCS Per channel control register 4 for channel0,1,2,3 (4.800Dh-8010h)
assign rcomp_pat_ch0_int[15:0] = pcs_ctrl4_ch0_reg;
assign rcomp_pat_ch1_int[15:0] = pcs_ctrl4_ch1_reg;
assign rcomp_pat_ch2_int[15:0] = pcs_ctrl4_ch2_reg;
assign rcomp_pat_ch3_int[15:0] = pcs_ctrl4_ch3_reg;

// Outputs from PCS Per channel control register 5 for channel0 (4.8011h)
assign rrxfifo_dis_int[0]          = pcs_ctrl5_ch0_reg[15];
assign rtxfifo_dis_int[0]          = pcs_ctrl5_ch0_reg[14];
assign rib_force_disp_int[0]       = pcs_ctrl5_ch0_reg[13];
assign rrundisp_ch0_int            = pcs_ctrl5_ch0_reg[12:7];
assign rtxfifo_lowlatency_en_int[0]= pcs_ctrl5_ch0_reg[6];
assign rrlv_en_int[0]              = pcs_ctrl5_ch0_reg[5];
assign rautobtalg_dis_int[0]       = pcs_ctrl5_ch0_reg[4];
assign rsync_sm_dis_int[0]         = pcs_ctrl5_ch0_reg[3];
assign rib_inv_cd_ch0_int          = pcs_ctrl5_ch0_reg[2:1];
assign rrxfifo_lowlatency_en_int[0]= pcs_ctrl5_ch0_reg[0];

// Outputs from PCS Per channel control register 5 for channel1 (4.8012h)
assign rrxfifo_dis_int[1]          = pcs_ctrl5_ch1_reg[15];
assign rtxfifo_dis_int[1]          = pcs_ctrl5_ch1_reg[14];
assign rib_force_disp_int[1]       = pcs_ctrl5_ch1_reg[13];
assign rrundisp_ch1_int            = pcs_ctrl5_ch1_reg[12:7];
assign rtxfifo_lowlatency_en_int[1]= pcs_ctrl5_ch1_reg[6];
assign rrlv_en_int[1]              = pcs_ctrl5_ch1_reg[5];
assign rautobtalg_dis_int[1]       = pcs_ctrl5_ch1_reg[4];
assign rsync_sm_dis_int[1]         = pcs_ctrl5_ch1_reg[3];
assign rib_inv_cd_ch1_int          = pcs_ctrl5_ch1_reg[2:1];
assign rrxfifo_lowlatency_en_int[1]= pcs_ctrl5_ch1_reg[0];

// Outputs from PCS Per channel control register 5 for channel2 (4.8013h)
assign rrxfifo_dis_int[2]          = pcs_ctrl5_ch2_reg[15];
assign rtxfifo_dis_int[2]          = pcs_ctrl5_ch2_reg[14];
assign rib_force_disp_int[2]       = pcs_ctrl5_ch2_reg[13];
assign rrundisp_ch2_int            = pcs_ctrl5_ch2_reg[12:7];
assign rtxfifo_lowlatency_en_int[2]= pcs_ctrl5_ch2_reg[6];
assign rrlv_en_int[2]              = pcs_ctrl5_ch2_reg[5];
assign rautobtalg_dis_int[2]       = pcs_ctrl5_ch2_reg[4];
assign rsync_sm_dis_int[2]         = pcs_ctrl5_ch2_reg[3];
assign rib_inv_cd_ch2_int          = pcs_ctrl5_ch2_reg[2:1];
assign rrxfifo_lowlatency_en_int[2]= pcs_ctrl5_ch2_reg[0];

// Outputs from PCS Per channel control register 5 for channel3 (4.8014h)
assign rrxfifo_dis_int[3]          = pcs_ctrl5_ch3_reg[15];
assign rtxfifo_dis_int[3]          = pcs_ctrl5_ch3_reg[14];
assign rib_force_disp_int[3]       = pcs_ctrl5_ch3_reg[13];
assign rrundisp_ch3_int            = pcs_ctrl5_ch3_reg[12:7];
assign rtxfifo_lowlatency_en_int[3]= pcs_ctrl5_ch3_reg[6];
assign rrlv_en_int[3]              = pcs_ctrl5_ch3_reg[5];
assign rautobtalg_dis_int[3]       = pcs_ctrl5_ch3_reg[4];
assign rsync_sm_dis_int[3]         = pcs_ctrl5_ch3_reg[3];
assign rib_inv_cd_ch3_int          = pcs_ctrl5_ch3_reg[2:1];
assign rrxfifo_lowlatency_en_int[3]= pcs_ctrl5_ch3_reg[0];

// Outputs from PCS Per channel control register 6 for channel0 (4.8015h)
assign rdwidth_tx_int[0]       = pcs_ctrl6_ch0_reg[15];
assign rdwidth_rx_int[0]       = pcs_ctrl6_ch0_reg[14];
assign rge_xaui_tx_int[0]      = pcs_ctrl6_ch0_reg[13];
assign rrx_detect_bypass_int[0]= pcs_ctrl6_ch0_reg[12];
assign rtxurstpcs_md[0]        = pcs_ctrl6_ch0_reg[11];
assign rrxurstpcs_md[0]        = pcs_ctrl6_ch0_reg[10];
assign rrsvd_tx_ch0_int        = pcs_ctrl6_ch0_reg[9:5];
assign rskpsetbased_int[0]     = pcs_ctrl6_ch0_reg[4];
assign rtruebac2bac_int[0]     = pcs_ctrl6_ch0_reg[3];
assign rrsvd_rx_ch0_int        = pcs_ctrl6_ch0_reg[2:0];

// Outputs from PCS Per channel control register 6 for channel1 (4.8016h)
assign rdwidth_tx_int[1]       = pcs_ctrl6_ch1_reg[15];
assign rdwidth_rx_int[1]       = pcs_ctrl6_ch1_reg[14];
assign rge_xaui_tx_int[1]      = pcs_ctrl6_ch1_reg[13];
assign rrx_detect_bypass_int[1]= pcs_ctrl6_ch1_reg[12];
assign rtxurstpcs_md[1]        = pcs_ctrl6_ch1_reg[11];
assign rrxurstpcs_md[1]        = pcs_ctrl6_ch1_reg[10];
assign rrsvd_tx_ch1_int        = pcs_ctrl6_ch1_reg[9:5];
assign rskpsetbased_int[1]     = pcs_ctrl6_ch1_reg[4];
assign rtruebac2bac_int[1]     = pcs_ctrl6_ch1_reg[3];
assign rrsvd_rx_ch1_int        = pcs_ctrl6_ch1_reg[2:0];

// Outputs from PCS Per channel control register 6 for channel2 (4.8017h)
assign rdwidth_tx_int[2]       = pcs_ctrl6_ch2_reg[15];
assign rdwidth_rx_int[2]       = pcs_ctrl6_ch2_reg[14];
assign rge_xaui_tx_int[2]      = pcs_ctrl6_ch2_reg[13];
assign rrx_detect_bypass_int[2]= pcs_ctrl6_ch2_reg[12];
assign rtxurstpcs_md[2]        = pcs_ctrl6_ch2_reg[11];
assign rrxurstpcs_md[2]        = pcs_ctrl6_ch2_reg[10];
assign rrsvd_tx_ch2_int        = pcs_ctrl6_ch2_reg[9:5];
assign rskpsetbased_int[2]     = pcs_ctrl6_ch2_reg[4];
assign rtruebac2bac_int[2]     = pcs_ctrl6_ch2_reg[3];
assign rrsvd_rx_ch2_int        = pcs_ctrl6_ch2_reg[2:0];

// Outputs from PCS Per channel control register 6 for channel3 (4.8018h)
assign rdwidth_tx_int[3]       = pcs_ctrl6_ch3_reg[15];
assign rdwidth_rx_int[3]       = pcs_ctrl6_ch3_reg[14];
assign rge_xaui_tx_int[3]      = pcs_ctrl6_ch3_reg[13];
assign rrx_detect_bypass_int[3]= pcs_ctrl6_ch3_reg[12];
assign rtxurstpcs_md[3]        = pcs_ctrl6_ch3_reg[11];
assign rrxurstpcs_md[3]        = pcs_ctrl6_ch3_reg[10];
assign rrsvd_tx_ch3_int        = pcs_ctrl6_ch3_reg[9:5];
assign rskpsetbased_int[3]     = pcs_ctrl6_ch3_reg[4];
assign rtruebac2bac_int[3]     = pcs_ctrl6_ch3_reg[3];
assign rrsvd_rx_ch3_int        = pcs_ctrl6_ch3_reg[2:0];

// Outputs from PCS Per channel control register 7 for channel0 (4.8019h)
assign rgnumber_ch0_int      = pcs_ctrl7_ch0_reg[15:8];
assign rknumber_ch0_int      = pcs_ctrl7_ch0_reg[7:0];

// Outputs from PCS Per channel control register 7 for channel1 (4.801Ah)
assign rgnumber_ch1_int      = pcs_ctrl7_ch1_reg[15:8];
assign rknumber_ch1_int      = pcs_ctrl7_ch1_reg[7:0];

// Outputs from PCS Per channel control register 7 for channel2 (4.801Bh)
assign rgnumber_ch2_int      = pcs_ctrl7_ch2_reg[15:8];
assign rknumber_ch2_int      = pcs_ctrl7_ch2_reg[7:0];

// Outputs from PCS Per channel control register 7 for channel3 (4.801Ch)
assign rgnumber_ch3_int      = pcs_ctrl7_ch3_reg[15:8];
assign rknumber_ch3_int      = pcs_ctrl7_ch3_reg[7:0];

// Outputs from PCS Per channel control register 8 for channel0 (4.801Dh)
assign rfreerun_tx_int[0]      = pcs_ctrl8_ch0_reg[15];
assign rtxwrclksel_int[0]      = pcs_ctrl8_ch0_reg[14];
assign rtxrdclksel_int[0]      = pcs_ctrl8_ch0_reg[13];
assign rfreerun_rx_int[0]      = pcs_ctrl8_ch0_reg[12];
assign rrcvd_clk_sel_ch0_int   = pcs_ctrl8_ch0_reg[11:10];
assign rclk_1_sel_ch0_int      = pcs_ctrl8_ch0_reg[9:8];
assign rclk_2_sel_ch0_int      = pcs_ctrl8_ch0_reg[7:6];
assign rrx_rd_clk_sel_int[0]   = pcs_ctrl8_ch0_reg[5];
assign renumber_ch0_int        = pcs_ctrl8_ch0_reg[4:2];
assign renpolinv_rx_int[0]     = pcs_ctrl8_ch0_reg[1];
assign rclkcmpinsertpad_int[0] = pcs_ctrl8_ch0_reg[0];

// Outputs from PCS Per channel control register 8 for channel1 (4.801Eh)
assign rfreerun_tx_int[1]      = pcs_ctrl8_ch1_reg[15];
assign rtxwrclksel_int[1]      = pcs_ctrl8_ch1_reg[14];
assign rtxrdclksel_int[1]      = pcs_ctrl8_ch1_reg[13];
assign rfreerun_rx_int[1]      = pcs_ctrl8_ch1_reg[12];
assign rrcvd_clk_sel_ch1_int   = pcs_ctrl8_ch1_reg[11:10];
assign rclk_1_sel_ch1_int      = pcs_ctrl8_ch1_reg[9:8];
assign rclk_2_sel_ch1_int      = pcs_ctrl8_ch1_reg[7:6];
assign rrx_rd_clk_sel_int[1]   = pcs_ctrl8_ch1_reg[5];
assign renumber_ch1_int        = pcs_ctrl8_ch1_reg[4:2];
assign renpolinv_rx_int[1]     = pcs_ctrl8_ch1_reg[1];
assign rclkcmpinsertpad_int[1] = pcs_ctrl8_ch1_reg[0];

// Outputs from PCS Per channel control register 8 for channel2 (4.801Fh)
assign rfreerun_tx_int[2]      = pcs_ctrl8_ch2_reg[15];
assign rtxwrclksel_int[2]      = pcs_ctrl8_ch2_reg[14];
assign rtxrdclksel_int[2]      = pcs_ctrl8_ch2_reg[13];
assign rfreerun_rx_int[2]      = pcs_ctrl8_ch2_reg[12];
assign rrcvd_clk_sel_ch2_int   = pcs_ctrl8_ch2_reg[11:10];
assign rclk_1_sel_ch2_int      = pcs_ctrl8_ch2_reg[9:8];
assign rclk_2_sel_ch2_int      = pcs_ctrl8_ch2_reg[7:6];
assign rrx_rd_clk_sel_int[2]   = pcs_ctrl8_ch2_reg[5];
assign renumber_ch2_int        = pcs_ctrl8_ch2_reg[4:2];
assign renpolinv_rx_int[2]     = pcs_ctrl8_ch2_reg[1];
assign rclkcmpinsertpad_int[2] = pcs_ctrl8_ch2_reg[0];

// Outputs from PCS Per channel control register 8 for channel3 (4.8020h)
assign rfreerun_tx_int[3]      = pcs_ctrl8_ch3_reg[15];
assign rtxwrclksel_int[3]      = pcs_ctrl8_ch3_reg[14];
assign rtxrdclksel_int[3]      = pcs_ctrl8_ch3_reg[13];
assign rfreerun_rx_int[3]      = pcs_ctrl8_ch3_reg[12];
assign rrcvd_clk_sel_ch3_int   = pcs_ctrl8_ch3_reg[11:10];
assign rclk_1_sel_ch3_int      = pcs_ctrl8_ch3_reg[9:8];
assign rclk_2_sel_ch3_int      = pcs_ctrl8_ch3_reg[7:6];
assign rrx_rd_clk_sel_int[3]   = pcs_ctrl8_ch3_reg[5];
assign renumber_ch3_int        = pcs_ctrl8_ch3_reg[4:2];
assign renpolinv_rx_int[3]     = pcs_ctrl8_ch3_reg[1];
assign rclkcmpinsertpad_int[3] = pcs_ctrl8_ch3_reg[0];

// Outputs from BIST/PRBS test control register for channel0 (4.8021h)
assign rprbsen_tx_int[0]        = prbs_bist_ctrl_ch0_reg[15];
assign rprbsen_rx_int[0]        = prbs_bist_ctrl_ch0_reg[14];
assign rprbs_clr_rslt_rx_int[0] = prbs_bist_ctrl_ch0_reg[13];
assign rprbs_sel_ch0_int        = prbs_bist_ctrl_ch0_reg[12:10];
assign rbisten_tx_int[0]        = prbs_bist_ctrl_ch0_reg[9];
assign rbisten_rx_int[0]        = prbs_bist_ctrl_ch0_reg[8];
assign rbist_clr_rx_int[0]      = prbs_bist_ctrl_ch0_reg[7];
assign rbist_sel_ch0_int        = prbs_bist_ctrl_ch0_reg[6:5];
assign rcxpat_chnl_en_ch0_int   = prbs_bist_ctrl_ch0_reg[4:3];
assign rall_one_dect_only_int[0]= prbs_bist_ctrl_ch0_reg[2];

// Outputs from BIST/PRBS test control register for channel1 (4.8022h)
assign rprbsen_tx_int[1]        = prbs_bist_ctrl_ch1_reg[15];
assign rprbsen_rx_int[1]        = prbs_bist_ctrl_ch1_reg[14];
assign rprbs_clr_rslt_rx_int[1] = prbs_bist_ctrl_ch1_reg[13];
assign rprbs_sel_ch1_int        = prbs_bist_ctrl_ch1_reg[12:10];
assign rbisten_tx_int[1]        = prbs_bist_ctrl_ch1_reg[9];
assign rbisten_rx_int[1]        = prbs_bist_ctrl_ch1_reg[8];
assign rbist_clr_rx_int[1]      = prbs_bist_ctrl_ch1_reg[7];
assign rbist_sel_ch1_int        = prbs_bist_ctrl_ch1_reg[6:5];
assign rcxpat_chnl_en_ch1_int   = prbs_bist_ctrl_ch1_reg[4:3];
assign rall_one_dect_only_int[1]= prbs_bist_ctrl_ch1_reg[2];

// Outputs from BIST/PRBS test control register for channel2 (4.8023h)
assign rprbsen_tx_int[2]        = prbs_bist_ctrl_ch2_reg[15];
assign rprbsen_rx_int[2]        = prbs_bist_ctrl_ch2_reg[14];
assign rprbs_clr_rslt_rx_int[2] = prbs_bist_ctrl_ch2_reg[13];
assign rprbs_sel_ch2_int        = prbs_bist_ctrl_ch2_reg[12:10];
assign rbisten_tx_int[2]        = prbs_bist_ctrl_ch2_reg[9];
assign rbisten_rx_int[2]        = prbs_bist_ctrl_ch2_reg[8];
assign rbist_clr_rx_int[2]      = prbs_bist_ctrl_ch2_reg[7];
assign rbist_sel_ch2_int        = prbs_bist_ctrl_ch2_reg[6:5];
assign rcxpat_chnl_en_ch2_int   = prbs_bist_ctrl_ch2_reg[4:3];
assign rall_one_dect_only_int[2]= prbs_bist_ctrl_ch2_reg[2];

// Outputs from BIST/PRBS test control register for channel3 (4.8024h)
assign rprbsen_tx_int[3]        = prbs_bist_ctrl_ch3_reg[15];
assign rprbsen_rx_int[3]        = prbs_bist_ctrl_ch3_reg[14];
assign rprbs_clr_rslt_rx_int[3] = prbs_bist_ctrl_ch3_reg[13];
assign rprbs_sel_ch3_int        = prbs_bist_ctrl_ch3_reg[12:10];
assign rbisten_tx_int[3]        = prbs_bist_ctrl_ch3_reg[9];
assign rbisten_rx_int[3]        = prbs_bist_ctrl_ch3_reg[8];
assign rbist_clr_rx_int[3]      = prbs_bist_ctrl_ch3_reg[7];
assign rbist_sel_ch3_int        = prbs_bist_ctrl_ch3_reg[6:5];
assign rcxpat_chnl_en_ch3_int   = prbs_bist_ctrl_ch3_reg[4:3];
assign rall_one_dect_only_int[3]= prbs_bist_ctrl_ch3_reg[2];

// Outputs from PCS Per channel control register 9 for channel0 (4.8025h)
assign rppm_cnt_reset_int[0]     = pcs_ctrl9_ch0_reg[15];
assign rphfifourstrx_int[0]      = pcs_ctrl9_ch0_reg[14];
assign rcmpfifourst_int[0]       = pcs_ctrl9_ch0_reg[13];
assign rtx_idle_delay_ch0_int    = pcs_ctrl9_ch0_reg[12:11];
assign rclkcmpsqmd_int[0]        = pcs_ctrl9_ch0_reg[10];
assign rclkcmpsq1p_ch0_int[9:0]  = pcs_ctrl9_ch0_reg[9:0];

// Outputs from PCS Per channel control register 9 for channel1 (4.8026h)
assign rppm_cnt_reset_int[1]     = pcs_ctrl9_ch1_reg[15];
assign rphfifourstrx_int[1]      = pcs_ctrl9_ch1_reg[14];
assign rcmpfifourst_int[1]       = pcs_ctrl9_ch1_reg[13];
assign rtx_idle_delay_ch1_int    = pcs_ctrl9_ch1_reg[12:11];
assign rclkcmpsqmd_int[1]        = pcs_ctrl9_ch1_reg[10];
assign rclkcmpsq1p_ch1_int[9:0]  = pcs_ctrl9_ch1_reg[9:0];

// Outputs from PCS Per channel control register 9 for channel2 (4.8027h)
assign rppm_cnt_reset_int[2]     = pcs_ctrl9_ch2_reg[15];
assign rphfifourstrx_int[2]      = pcs_ctrl9_ch2_reg[14];
assign rcmpfifourst_int[2]       = pcs_ctrl9_ch2_reg[13];
assign rtx_idle_delay_ch2_int    = pcs_ctrl9_ch2_reg[12:11];
assign rclkcmpsqmd_int[2]        = pcs_ctrl9_ch2_reg[10];
assign rclkcmpsq1p_ch2_int[9:0]  = pcs_ctrl9_ch2_reg[9:0];

// Outputs from PCS Per channel control register 9 for channel3 (4.8028h)
assign rppm_cnt_reset_int[3]     = pcs_ctrl9_ch3_reg[15];
assign rphfifourstrx_int[3]      = pcs_ctrl9_ch3_reg[14];
assign rcmpfifourst_int[3]       = pcs_ctrl9_ch3_reg[13];
assign rtx_idle_delay_ch3_int    = pcs_ctrl9_ch3_reg[12:11];
assign rclkcmpsqmd_int[3]        = pcs_ctrl9_ch3_reg[10];
assign rclkcmpsq1p_ch3_int[9:0]  = pcs_ctrl9_ch3_reg[9:0];

// Outputs from PCS Per channel control register 10 for channel0 (4.8029h)
assign rclkcmpsq1n_ch0_int[19:15]  = pcs_ctrl10_ch0_reg[15:11];
assign rclkcmppos_int[0]           = pcs_ctrl10_ch0_reg[10];
assign rclkcmpsq1p_ch0_int[19:10]  = pcs_ctrl10_ch0_reg[9:0];

// Outputs from PCS Per channel control register 10 for channel1 (4.802Ah)
assign rclkcmpsq1n_ch1_int[19:15]  = pcs_ctrl10_ch1_reg[15:11];
assign rclkcmppos_int[1]           = pcs_ctrl10_ch1_reg[10];
assign rclkcmpsq1p_ch1_int[19:10]  = pcs_ctrl10_ch1_reg[9:0];

// Outputs from PCS Per channel control register 10 for channel2 (4.802Bh)
assign rclkcmpsq1n_ch2_int[19:15]  = pcs_ctrl10_ch2_reg[15:11];
assign rclkcmppos_int[2]           = pcs_ctrl10_ch2_reg[10];
assign rclkcmpsq1p_ch2_int[19:10]  = pcs_ctrl10_ch2_reg[9:0];

// Outputs from PCS Per channel control register 10 for channel3 (4.802Ch)
assign rclkcmpsq1n_ch3_int[19:15]  = pcs_ctrl10_ch3_reg[15:11];
assign rclkcmppos_int[3]           = pcs_ctrl10_ch3_reg[10];
assign rclkcmpsq1p_ch3_int[19:10]  = pcs_ctrl10_ch3_reg[9:0];

// Outputs from PCS Per channel control register 11 for channel0 (4.802Dh)
assign rclkcmpsq1n_ch0_int[14:10]  = pcs_ctrl11_ch0_reg[15:11];
assign rclkcmpsq1n_ch0_int[9:0]    = pcs_ctrl11_ch0_reg[9:0];

// Outputs from PCS Per channel control register 11 for channel1 (4.802Eh)
assign rclkcmpsq1n_ch1_int[14:10]  = pcs_ctrl11_ch1_reg[15:11];
assign rclkcmpsq1n_ch1_int[9:0]    = pcs_ctrl11_ch1_reg[9:0];

// Outputs from PCS Per channel control register 11 for channel2 (4.802Fh)
assign rclkcmpsq1n_ch2_int[14:10]  = pcs_ctrl11_ch2_reg[15:11];
assign rclkcmpsq1n_ch2_int[9:0]    = pcs_ctrl11_ch2_reg[9:0];

// Outputs from PCS Per channel control register 11 for channel3 (4.8030h)
assign rclkcmpsq1n_ch3_int[14:10]  = pcs_ctrl11_ch3_reg[15:11];
assign rclkcmpsq1n_ch3_int[9:0]    = pcs_ctrl11_ch3_reg[9:0];

// Outputs from PCS Per channel control register 12 for channel0 (4.8031h)
assign rrev_loopbk_int[0]          = pcs_ctrl12_ch0_reg[15];
assign ralempty_ch0_int            = pcs_ctrl12_ch0_reg[14:11];
assign ralfull_ch0_int             = pcs_ctrl12_ch0_reg[10:7];
assign rforce_disp_int[0]          = pcs_ctrl12_ch0_reg[6];
assign rkchar_int[0]               = pcs_ctrl12_ch0_reg[5];
assign rosbased_int[0]             = pcs_ctrl12_ch0_reg[4];
assign rensymswap_tx_int[0]        = pcs_ctrl12_ch0_reg[3];
assign rosnumber_ch0_int           = pcs_ctrl12_ch0_reg[1:0];

// Outputs from PCS Per channel control register 12 for channel1 (4.8032h)
assign rrev_loopbk_int[1]          = pcs_ctrl12_ch1_reg[15];
assign ralempty_ch1_int            = pcs_ctrl12_ch1_reg[14:11];
assign ralfull_ch1_int             = pcs_ctrl12_ch1_reg[10:7];
assign rforce_disp_int[1]          = pcs_ctrl12_ch1_reg[6];
assign rkchar_int[1]               = pcs_ctrl12_ch1_reg[5];
assign rosbased_int[1]             = pcs_ctrl12_ch1_reg[4];
assign rensymswap_tx_int[1]        = pcs_ctrl12_ch1_reg[3];
assign rosnumber_ch1_int           = pcs_ctrl12_ch1_reg[1:0];

// Outputs from PCS Per channel control register 12 for channel2 (4.8033h)
assign rrev_loopbk_int[2]          = pcs_ctrl12_ch2_reg[15];
assign ralempty_ch2_int            = pcs_ctrl12_ch2_reg[14:11];
assign ralfull_ch2_int             = pcs_ctrl12_ch2_reg[10:7];
assign rforce_disp_int[2]          = pcs_ctrl12_ch2_reg[6];
assign rkchar_int[2]               = pcs_ctrl12_ch2_reg[5];
assign rosbased_int[2]             = pcs_ctrl12_ch2_reg[4];
assign rensymswap_tx_int[2]        = pcs_ctrl12_ch2_reg[3];
assign rosnumber_ch2_int           = pcs_ctrl12_ch2_reg[1:0];

// Outputs from PCS Per channel control register 12 for channel3 (4.8034h)
assign rrev_loopbk_int[3]          = pcs_ctrl12_ch3_reg[15];
assign ralempty_ch3_int            = pcs_ctrl12_ch3_reg[14:11];
assign ralfull_ch3_int             = pcs_ctrl12_ch3_reg[10:7];
assign rforce_disp_int[3]          = pcs_ctrl12_ch3_reg[6];
assign rkchar_int[3]               = pcs_ctrl12_ch3_reg[5];
assign rosbased_int[3]             = pcs_ctrl12_ch3_reg[4];
assign rensymswap_tx_int[3]        = pcs_ctrl12_ch3_reg[3];
assign rosnumber_ch3_int           = pcs_ctrl12_ch3_reg[1:0];

// Outputs from PCS Per channel control register 13 for channel0 (4.8035h)
assign rwa_6g_en_int[0]            = pcs_ctrl13_ch0_reg[15];
assign renpolinv_tx_int[0]         = pcs_ctrl13_ch0_reg[14];
assign rbitslip_size_ch0_int       = pcs_ctrl13_ch0_reg[13:12];
assign rbytord_2sym_en_int[0]      = pcs_ctrl13_ch0_reg[11];
assign rbysync_polinv_en_int[0]    = pcs_ctrl13_ch0_reg[10];
assign rbitloc_rev_en_int[0]       = pcs_ctrl13_ch0_reg[9];
assign rbyte_rev_en_int[0]         = pcs_ctrl13_ch0_reg[8];
assign renbitrev_tx_int[0]         = pcs_ctrl13_ch0_reg[7];
assign rbyteorden_ch0_int          = pcs_ctrl13_ch0_reg[6:5];
assign rbytordplden_int[0]         = pcs_ctrl13_ch0_reg[4];
assign rphfifopldentx_int[0]       = pcs_ctrl13_ch0_reg[3];
assign rphfifoursttx_int[0]        = pcs_ctrl13_ch0_reg[2];
assign rphfifopldenrx_int[0]       = pcs_ctrl13_ch0_reg[1];
assign rautoinsdis_int[0]          = pcs_ctrl13_ch0_reg[0];

// Outputs from PCS Per channel control register 13 for channel1 (4.8036h)
assign rwa_6g_en_int[1]            = pcs_ctrl13_ch1_reg[15];
assign renpolinv_tx_int[1]         = pcs_ctrl13_ch1_reg[14];
assign rbitslip_size_ch1_int       = pcs_ctrl13_ch1_reg[13:12];
assign rbytord_2sym_en_int[1]      = pcs_ctrl13_ch1_reg[11];
assign rbysync_polinv_en_int[1]    = pcs_ctrl13_ch1_reg[10];
assign rbitloc_rev_en_int[1]       = pcs_ctrl13_ch1_reg[9];
assign rbyte_rev_en_int[1]         = pcs_ctrl13_ch1_reg[8];
assign renbitrev_tx_int[1]         = pcs_ctrl13_ch1_reg[7];
assign rbyteorden_ch1_int          = pcs_ctrl13_ch1_reg[6:5];
assign rbytordplden_int[1]         = pcs_ctrl13_ch1_reg[4];
assign rphfifopldentx_int[1]       = pcs_ctrl13_ch1_reg[3];
assign rphfifoursttx_int[1]        = pcs_ctrl13_ch1_reg[2];
assign rphfifopldenrx_int[1]       = pcs_ctrl13_ch1_reg[1];
assign rautoinsdis_int[1]          = pcs_ctrl13_ch1_reg[0];

// Outputs from PCS Per channel control register 13 for channel2 (4.8037h)
assign rwa_6g_en_int[2]            = pcs_ctrl13_ch2_reg[15];
assign renpolinv_tx_int[2]         = pcs_ctrl13_ch2_reg[14];
assign rbitslip_size_ch2_int       = pcs_ctrl13_ch2_reg[13:12];
assign rbytord_2sym_en_int[2]      = pcs_ctrl13_ch2_reg[11];
assign rbysync_polinv_en_int[2]    = pcs_ctrl13_ch2_reg[10];
assign rbitloc_rev_en_int[2]       = pcs_ctrl13_ch2_reg[9];
assign rbyte_rev_en_int[2]         = pcs_ctrl13_ch2_reg[8];
assign renbitrev_tx_int[2]         = pcs_ctrl13_ch2_reg[7];
assign rbyteorden_ch2_int          = pcs_ctrl13_ch2_reg[6:5];
assign rbytordplden_int[2]         = pcs_ctrl13_ch2_reg[4];
assign rphfifopldentx_int[2]       = pcs_ctrl13_ch2_reg[3];
assign rphfifoursttx_int[2]        = pcs_ctrl13_ch2_reg[2];
assign rphfifopldenrx_int[2]       = pcs_ctrl13_ch2_reg[1];
assign rautoinsdis_int[2]          = pcs_ctrl13_ch2_reg[0];

// Outputs from PCS Per channel control register 13 for channel3 (4.8038h)
assign rwa_6g_en_int[3]            = pcs_ctrl13_ch3_reg[15];
assign renpolinv_tx_int[3]         = pcs_ctrl13_ch3_reg[14];
assign rbitslip_size_ch3_int       = pcs_ctrl13_ch3_reg[13:12];
assign rbytord_2sym_en_int[3]      = pcs_ctrl13_ch3_reg[11];
assign rbysync_polinv_en_int[3]    = pcs_ctrl13_ch3_reg[10];
assign rbitloc_rev_en_int[3]       = pcs_ctrl13_ch3_reg[9];
assign rbyte_rev_en_int[3]         = pcs_ctrl13_ch3_reg[8];
assign renbitrev_tx_int[3]         = pcs_ctrl13_ch3_reg[7];
assign rbyteorden_ch3_int          = pcs_ctrl13_ch3_reg[6:5];
assign rbytordplden_int[3]         = pcs_ctrl13_ch3_reg[4];
assign rphfifopldentx_int[3]       = pcs_ctrl13_ch3_reg[3];
assign rphfifoursttx_int[3]        = pcs_ctrl13_ch3_reg[2];
assign rphfifopldenrx_int[3]       = pcs_ctrl13_ch3_reg[1];
assign rautoinsdis_int[3]          = pcs_ctrl13_ch3_reg[0];

// Outputs from PCS Per channel control register 14 for channel0 (4.8039h)
assign rppmsel_ch0_int       = pcs_ctrl14_ch0_reg[15:10];
assign rbytordpat_ch0_int    = pcs_ctrl14_ch0_reg[9:0];

// Outputs from PCS Per channel control register 14 for channel1 (4.803Ah)
assign rppmsel_ch1_int       = pcs_ctrl14_ch1_reg[15:10];
assign rbytordpat_ch1_int    = pcs_ctrl14_ch1_reg[9:0];

// Outputs from PCS Per channel control register 14 for channel2 (4.803Bh)
assign rppmsel_ch2_int       = pcs_ctrl14_ch2_reg[15:10];
assign rbytordpat_ch2_int    = pcs_ctrl14_ch2_reg[9:0];

// Outputs from PCS Per channel control register 14 for channel3 (4.803Ch)
assign rppmsel_ch3_int       = pcs_ctrl14_ch3_reg[15:10];
assign rbytordpat_ch3_int    = pcs_ctrl14_ch3_reg[9:0];

// Outputs from PCS Per channel control register 15 for channel0 (4.803Dh)
assign rtest_bus_sel_ch0_int        = pcs_ctrl15_ch0_reg[15:13];
assign rforce_sig_det_pcs_int[0]    = pcs_ctrl15_ch0_reg[12];
assign rforce0_freqdet_int[0]       = pcs_ctrl15_ch0_reg[11];
assign rforce1_freqdet_int[0]       = pcs_ctrl15_ch0_reg[10];
assign rbytordpad_ch0_int           = pcs_ctrl15_ch0_reg[9:0];

// Outputs from PCS Per channel control register 15 for channel1 (4.803Eh)
assign rtest_bus_sel_ch1_int        = pcs_ctrl15_ch1_reg[15:13];
assign rforce_sig_det_pcs_int[1]    = pcs_ctrl15_ch1_reg[12];
assign rforce0_freqdet_int[1]       = pcs_ctrl15_ch1_reg[11];
assign rforce1_freqdet_int[1]       = pcs_ctrl15_ch1_reg[10];
assign rbytordpad_ch1_int           = pcs_ctrl15_ch1_reg[9:0];

// Outputs from PCS Per channel control register 15 for channel2 (4.803Fh)
assign rtest_bus_sel_ch2_int        = pcs_ctrl15_ch2_reg[15:13];
assign rforce_sig_det_pcs_int[2]    = pcs_ctrl15_ch2_reg[12];
assign rforce0_freqdet_int[2]       = pcs_ctrl15_ch2_reg[11];
assign rforce1_freqdet_int[2]       = pcs_ctrl15_ch2_reg[10];
assign rbytordpad_ch2_int           = pcs_ctrl15_ch2_reg[9:0];

// Outputs from PCS Per channel control register 15 for channel3 (4.8040h)
assign rtest_bus_sel_ch3_int        = pcs_ctrl15_ch3_reg[15:13];
assign rforce_sig_det_pcs_int[3]    = pcs_ctrl15_ch3_reg[12];
assign rforce0_freqdet_int[3]       = pcs_ctrl15_ch3_reg[11];
assign rforce1_freqdet_int[3]       = pcs_ctrl15_ch3_reg[10];
assign rbytordpad_ch3_int           = pcs_ctrl15_ch3_reg[9:0];

// Outputs from PCS Global control register 0 (4.8050h)
assign ralgnect_int     = pcs_global_ctrl0_reg[6:5];
assign ralgngct_int     = pcs_global_ctrl0_reg[4:3];
assign ralgnact_int     = pcs_global_ctrl0_reg[2:0];

// Outputs from PCS Global control register 1 (4.8051h)
assign rfreerun_centrl_int = pcs_global_ctrl1_reg[15];
assign rcentrl_clk_sel_int = pcs_global_ctrl1_reg[14];
assign rrefclk_out_div2_int= pcs_global_ctrl1_reg[11];
assign rdskposdisp_int     = pcs_global_ctrl1_reg[10];
assign rdskchrp_int        = pcs_global_ctrl1_reg[9:0];

// Outputs from PCS Global control register 2 (4.8052h)
assign rtest_bus_centrl_sel_int = pcs_global_ctrl2_reg[12:10];
assign ralgnopt_int             = pcs_global_ctrl2_reg[13];

// PMA CRAMs
// Outputs from PMA Per channel control register 1 for channel0 (4.8060h)
assign  rtx_vod_sel_ch0_int          = pma_ctrl1_ch0_reg[15:13];
assign  rtx_slewrate_int[0]          = pma_ctrl1_ch0_reg[12];
assign  rpmphs_2tap_ch0_int          = pma_ctrl1_ch0_reg[11:9];
assign  rpmphs_1tap_ch0_int          = pma_ctrl1_ch0_reg[8:5];
assign  rtx_vtt_ch0_int              = pma_ctrl1_ch0_reg[4:3];
assign  rpmphs_ptap_ch0_int          = pma_ctrl1_ch0_reg[2:0];

// Outputs from PMA Per channel control register 1 for channel1 (4.8061h)
assign  rtx_vod_sel_ch1_int          = pma_ctrl1_ch1_reg[15:13];
assign  rtx_slewrate_int[1]          = pma_ctrl1_ch1_reg[12];
assign  rpmphs_2tap_ch1_int          = pma_ctrl1_ch1_reg[11:9];
assign  rpmphs_1tap_ch1_int          = pma_ctrl1_ch1_reg[8:5];
assign  rtx_vtt_ch1_int              = pma_ctrl1_ch1_reg[4:3];
assign  rpmphs_ptap_ch1_int          = pma_ctrl1_ch1_reg[2:0];

// Outputs from PMA Per channel control register 1 for channel2 (4.8062h)
assign  rtx_vod_sel_ch2_int          = pma_ctrl1_ch2_reg[15:13];
assign  rtx_slewrate_int[2]          = pma_ctrl1_ch2_reg[12];
assign  rpmphs_2tap_ch2_int          = pma_ctrl1_ch2_reg[11:9];
assign  rpmphs_1tap_ch2_int          = pma_ctrl1_ch2_reg[8:5];
assign  rtx_vtt_ch2_int              = pma_ctrl1_ch2_reg[4:3];
assign  rpmphs_ptap_ch2_int          = pma_ctrl1_ch2_reg[2:0];

// Outputs from PMA Per channel control register 1 for channel3 (4.8063h)
assign  rtx_vod_sel_ch3_int          = pma_ctrl1_ch3_reg[15:13];
assign  rtx_slewrate_int[3]          = pma_ctrl1_ch3_reg[12];
assign  rpmphs_2tap_ch3_int          = pma_ctrl1_ch3_reg[11:9];
assign  rpmphs_1tap_ch3_int          = pma_ctrl1_ch3_reg[8:5];
assign  rtx_vtt_ch3_int              = pma_ctrl1_ch3_reg[4:3];
assign  rpmphs_ptap_ch3_int          = pma_ctrl1_ch3_reg[2:0];

// Outputs from PMA Per channel control register 2 for channel0 (4.8064h)
assign  rtx_term_ch0_int             = pma_ctrl2_ch0_reg[15:14];
assign  r_tx_det_rx_ch0_int          = pma_ctrl2_ch0_reg[13:12];
assign  rrx_term_ch0_int             = pma_ctrl2_ch0_reg[11:10];
assign  rforce_sigdet_int[0]         = pma_ctrl2_ch0_reg[9];
assign  rrx_dc_couple_int[0]         = pma_ctrl2_ch0_reg[8];
assign  rrx_eq_dc_ch0_int            = pma_ctrl2_ch0_reg[7:6];
assign  rrx_vtt_ch0_int              = pma_ctrl2_ch0_reg[5:3];
assign  rrx_sloslv_ch0_int           = pma_ctrl2_ch0_reg[2:0];

// Outputs from PMA Per channel control register 2 for channel1 (4.8065h)
assign  rtx_term_ch1_int             = pma_ctrl2_ch1_reg[15:14];
assign  r_tx_det_rx_ch1_int          = pma_ctrl2_ch1_reg[13:12];
assign  rrx_term_ch1_int             = pma_ctrl2_ch1_reg[11:10];
assign  rforce_sigdet_int[1]         = pma_ctrl2_ch1_reg[9];
assign  rrx_dc_couple_int[1]         = pma_ctrl2_ch1_reg[8];
assign  rrx_eq_dc_ch1_int            = pma_ctrl2_ch1_reg[7:6];
assign  rrx_vtt_ch1_int              = pma_ctrl2_ch1_reg[5:3];
assign  rrx_sloslv_ch1_int           = pma_ctrl2_ch1_reg[2:0];

// Outputs from PMA Per channel control register 2 for channel2 (4.8066h)
assign  rtx_term_ch2_int             = pma_ctrl2_ch2_reg[15:14];
assign  r_tx_det_rx_ch2_int          = pma_ctrl2_ch2_reg[13:12];
assign  rrx_term_ch2_int             = pma_ctrl2_ch2_reg[11:10];
assign  rforce_sigdet_int[2]         = pma_ctrl2_ch2_reg[9];
assign  rrx_dc_couple_int[2]         = pma_ctrl2_ch2_reg[8];
assign  rrx_eq_dc_ch2_int            = pma_ctrl2_ch2_reg[7:6];
assign  rrx_vtt_ch2_int              = pma_ctrl2_ch2_reg[5:3];
assign  rrx_sloslv_ch2_int           = pma_ctrl2_ch2_reg[2:0];

// Outputs from PMA Per channel control register 2 for channel3 (4.8067h)
assign  rtx_term_ch3_int             = pma_ctrl2_ch3_reg[15:14];
assign  r_tx_det_rx_ch3_int          = pma_ctrl2_ch3_reg[13:12];
assign  rrx_term_ch3_int             = pma_ctrl2_ch3_reg[11:10];
assign  rforce_sigdet_int[3]         = pma_ctrl2_ch3_reg[9];
assign  rrx_dc_couple_int[3]         = pma_ctrl2_ch3_reg[8];
assign  rrx_eq_dc_ch3_int            = pma_ctrl2_ch3_reg[7:6];
assign  rrx_vtt_ch3_int              = pma_ctrl2_ch3_reg[5:3];
assign  rrx_sloslv_ch3_int           = pma_ctrl2_ch3_reg[2:0];

// Outputs from PMA Per channel control register 3 for channel0 (4.8068h)
assign	reqa_ct_ch0_int	             = pma_ctrl3_ch0_reg[15:13];
assign	reqb_ct_ch0_int	             = pma_ctrl3_ch0_reg[12:10];
assign	reqc_ct_ch0_int	             = pma_ctrl3_ch0_reg[9:7];
assign	reqd_ct_ch0_int	             = pma_ctrl3_ch0_reg[6:4];
assign	req_ctv_ch0_int	             = pma_ctrl3_ch0_reg[3:1];

// Outputs from PMA Per channel control register 3 for channel1 (4.8069h)
assign	reqa_ct_ch1_int	             = pma_ctrl3_ch1_reg[15:13];
assign	reqb_ct_ch1_int	             = pma_ctrl3_ch1_reg[12:10];
assign	reqc_ct_ch1_int	             = pma_ctrl3_ch1_reg[9:7];
assign	reqd_ct_ch1_int	             = pma_ctrl3_ch1_reg[6:4];
assign	req_ctv_ch1_int	             = pma_ctrl3_ch1_reg[3:1];

// Outputs from PMA Per channel control register 3 for channel2 (4.806Ah)
assign	reqa_ct_ch2_int	             = pma_ctrl3_ch2_reg[15:13];
assign	reqb_ct_ch2_int	             = pma_ctrl3_ch2_reg[12:10];
assign	reqc_ct_ch2_int	             = pma_ctrl3_ch2_reg[9:7];
assign	reqd_ct_ch2_int	             = pma_ctrl3_ch2_reg[6:4];
assign	req_ctv_ch2_int	             = pma_ctrl3_ch2_reg[3:1];

// Outputs from PMA Per channel control register 3 for channel3 (4.806Bh)
assign	reqa_ct_ch3_int	             = pma_ctrl3_ch3_reg[15:13];
assign	reqb_ct_ch3_int	             = pma_ctrl3_ch3_reg[12:10];
assign	reqc_ct_ch3_int	             = pma_ctrl3_ch3_reg[9:7];
assign	reqd_ct_ch3_int	             = pma_ctrl3_ch3_reg[6:4];
assign	req_ctv_ch3_int	             = pma_ctrl3_ch3_reg[3:1];

// Outputs from PMA Per channel control register 4 for channel0 (4.806Ch)
assign  rpmadwidth_tx_int[0]         = pma_ctrl4_ch0_reg[15];
assign  rpma_doublewidth_tx_int[0]   = pma_ctrl4_ch0_reg[14];
assign  rtx_cmu_sel_int[0]           = pma_ctrl4_ch0_reg[13];
assign  rtx_m_sel_ch0_int            = pma_ctrl4_ch0_reg[12:11];
assign  rtxvcobypass_int[0]          = pma_ctrl4_ch0_reg[10];
assign  rtx_cgb_1x_en_int[0]         = pma_ctrl4_ch0_reg[9];
assign  rtx_cgb_4x_en_int[0]         = pma_ctrl4_ch0_reg[8];
assign  rtx_4x_sw_int[0]             = pma_ctrl4_ch0_reg[7];
assign  rpmadwidth_rx_int[0]         = pma_ctrl4_ch0_reg[6];
assign  rpma_doublewidth_rx_int[0]   = pma_ctrl4_ch0_reg[5];
assign  rrxvcobypass_int[0]          = pma_ctrl4_ch0_reg[4];
assign  rrect_adj_ch0_int            = pma_ctrl4_ch0_reg[3:2];
assign  rrx_piso_bypass_ch0_int      = pma_ctrl4_ch0_reg[1:0];

// Outputs from PMA Per channel control register 4 for channel1 (4.806Dh)
assign  rpmadwidth_tx_int[1]         = pma_ctrl4_ch1_reg[15];
assign  rpma_doublewidth_tx_int[1]   = pma_ctrl4_ch1_reg[14];
assign  rtx_cmu_sel_int[1]           = pma_ctrl4_ch1_reg[13];
assign  rtx_m_sel_ch1_int            = pma_ctrl4_ch1_reg[12:11];
assign  rtxvcobypass_int[1]          = pma_ctrl4_ch1_reg[10];
assign  rtx_cgb_1x_en_int[1]         = pma_ctrl4_ch1_reg[9];
assign  rtx_cgb_4x_en_int[1]         = pma_ctrl4_ch1_reg[8];
assign  rtx_4x_sw_int[1]             = pma_ctrl4_ch1_reg[7];
assign  rpmadwidth_rx_int[1]         = pma_ctrl4_ch1_reg[6];
assign  rpma_doublewidth_rx_int[1]   = pma_ctrl4_ch1_reg[5];
assign  rrxvcobypass_int[1]          = pma_ctrl4_ch1_reg[4];
assign  rrect_adj_ch1_int            = pma_ctrl4_ch1_reg[3:2];
assign  rrx_piso_bypass_ch1_int      = pma_ctrl4_ch1_reg[1:0];

// Outputs from PMA Per channel control register 4 for channel2 (4.806Eh)
assign  rpmadwidth_tx_int[2]         = pma_ctrl4_ch2_reg[15];
assign  rpma_doublewidth_tx_int[2]   = pma_ctrl4_ch2_reg[14];
assign  rtx_cmu_sel_int[2]           = pma_ctrl4_ch2_reg[13];
assign  rtx_m_sel_ch2_int            = pma_ctrl4_ch2_reg[12:11];
assign  rtxvcobypass_int[2]          = pma_ctrl4_ch2_reg[10];
assign  rtx_cgb_1x_en_int[2]         = pma_ctrl4_ch2_reg[9];
assign  rtx_cgb_4x_en_int[2]         = pma_ctrl4_ch2_reg[8];
assign  rtx_4x_sw_int[2]             = pma_ctrl4_ch2_reg[7];
assign  rpmadwidth_rx_int[2]         = pma_ctrl4_ch2_reg[6];
assign  rpma_doublewidth_rx_int[2]   = pma_ctrl4_ch2_reg[5];
assign  rrxvcobypass_int[2]          = pma_ctrl4_ch2_reg[4];
assign  rrect_adj_ch2_int            = pma_ctrl4_ch2_reg[3:2];
assign  rrx_piso_bypass_ch2_int      = pma_ctrl4_ch2_reg[1:0];

// Outputs from PMA Per channel control register 4 for channel3 (4.806Fh)
assign  rpmadwidth_tx_int[3]         = pma_ctrl4_ch3_reg[15];
assign  rpma_doublewidth_tx_int[3]   = pma_ctrl4_ch3_reg[14];
assign  rtx_cmu_sel_int[3]           = pma_ctrl4_ch3_reg[13];
assign  rtx_m_sel_ch3_int            = pma_ctrl4_ch3_reg[12:11];
assign  rtxvcobypass_int[3]          = pma_ctrl4_ch3_reg[10];
assign  rtx_cgb_1x_en_int[3]         = pma_ctrl4_ch3_reg[9];
assign  rtx_cgb_4x_en_int[3]         = pma_ctrl4_ch3_reg[8];
assign  rtx_4x_sw_int[3]             = pma_ctrl4_ch3_reg[7];
assign  rpmadwidth_rx_int[3]         = pma_ctrl4_ch3_reg[6];
assign  rpma_doublewidth_rx_int[3]   = pma_ctrl4_ch3_reg[5];
assign  rrxvcobypass_int[3]          = pma_ctrl4_ch3_reg[4];
assign  rrect_adj_ch3_int            = pma_ctrl4_ch3_reg[3:2];
assign  rrx_piso_bypass_ch3_int      = pma_ctrl4_ch3_reg[1:0];

// Outputs from PMA Per channel control register 5 for channel0 (4.8070h)
assign	rlst_tx_ch0_int              = pma_ctrl5_ch0_reg[15:12];
assign	rlst_rx_ch0_int              = pma_ctrl5_ch0_reg[11:8];
assign	rlst_rxpll_ch0_int           = pma_ctrl5_ch0_reg[7:4];
assign	rrx_ignore_phslck_int[0]     = pma_ctrl5_ch0_reg[3];
assign	rdc_freq_ch0_int             = pma_ctrl5_ch0_reg[2:1];
assign	rrx_osc_en_int[0]            = pma_ctrl5_ch0_reg[0];

// Outputs from PMA Per channel control register 5 for channel1 (4.8071h)
assign	rlst_tx_ch1_int              = pma_ctrl5_ch1_reg[15:12];
assign	rlst_rx_ch1_int              = pma_ctrl5_ch1_reg[11:8];
assign	rlst_rxpll_ch1_int           = pma_ctrl5_ch1_reg[7:4];
assign	rrx_ignore_phslck_int[1]     = pma_ctrl5_ch1_reg[3];
assign	rdc_freq_ch1_int             = pma_ctrl5_ch1_reg[2:1];
assign	rrx_osc_en_int[1]            = pma_ctrl5_ch1_reg[0];

// Outputs from PMA Per channel control register 5 for channel2 (4.8072h)
assign	rlst_tx_ch2_int              = pma_ctrl5_ch2_reg[15:12];
assign	rlst_rx_ch2_int              = pma_ctrl5_ch2_reg[11:8];
assign	rlst_rxpll_ch2_int           = pma_ctrl5_ch2_reg[7:4];
assign	rrx_ignore_phslck_int[2]     = pma_ctrl5_ch2_reg[3];
assign	rdc_freq_ch2_int             = pma_ctrl5_ch2_reg[2:1];
assign	rrx_osc_en_int[2]            = pma_ctrl5_ch2_reg[0];

// Outputs from PMA Per channel control register 5 for channel3 (4.8073h)
assign	rlst_tx_ch3_int              = pma_ctrl5_ch3_reg[15:12];
assign	rlst_rx_ch3_int              = pma_ctrl5_ch3_reg[11:8];
assign	rlst_rxpll_ch3_int           = pma_ctrl5_ch3_reg[7:4];
assign	rrx_ignore_phslck_int[3]     = pma_ctrl5_ch3_reg[3];
assign	rdc_freq_ch3_int             = pma_ctrl5_ch3_reg[2:1];
assign	rrx_osc_en_int[3]            = pma_ctrl5_ch3_reg[0];

// Outputs from PMA Per channel control register 6 for channel0 (4.8074h)
assign	rrefclk_sel_ch0_int          = pma_ctrl6_ch0_reg[15:13];
assign	rbwctral_rx_ch0_int          = pma_ctrl6_ch0_reg[12:11];
assign	rrx_cru_m_sel_ch0_int        = pma_ctrl6_ch0_reg[10:9];
assign	rrx_cru_div2_int[0]          = pma_ctrl6_ch0_reg[8];
assign	rrx_cru_ctl_ch0_int          = pma_ctrl6_ch0_reg[7:2];
assign	rltr_int[0]		     = pma_ctrl6_ch0_reg[1];
assign	rltd_int[0]		     = pma_ctrl6_ch0_reg[0];

// Outputs from PMA Per channel control register 6 for channel1 (4.8075h)
assign	rrefclk_sel_ch1_int          = pma_ctrl6_ch1_reg[15:13];
assign	rbwctral_rx_ch1_int          = pma_ctrl6_ch1_reg[12:11];
assign	rrx_cru_m_sel_ch1_int        = pma_ctrl6_ch1_reg[10:9];
assign	rrx_cru_div2_int[1]          = pma_ctrl6_ch1_reg[8];
assign	rrx_cru_ctl_ch1_int          = pma_ctrl6_ch1_reg[7:2];
assign	rltr_int[1]		     = pma_ctrl6_ch1_reg[1];
assign	rltd_int[1]		     = pma_ctrl6_ch1_reg[0];

// Outputs from PMA Per channel control register 6 for channel2 (4.8076h)
assign	rrefclk_sel_ch2_int          = pma_ctrl6_ch2_reg[15:13];
assign	rbwctral_rx_ch2_int          = pma_ctrl6_ch2_reg[12:11];
assign	rrx_cru_m_sel_ch2_int        = pma_ctrl6_ch2_reg[10:9];
assign	rrx_cru_div2_int[2]          = pma_ctrl6_ch2_reg[8];
assign	rrx_cru_ctl_ch2_int          = pma_ctrl6_ch2_reg[7:2];
assign	rltr_int[2]		     = pma_ctrl6_ch2_reg[1];
assign	rltd_int[2]		     = pma_ctrl6_ch2_reg[0];

// Outputs from PMA Per channel control register 6 for channel3 (4.8077h)
assign	rrefclk_sel_ch3_int          = pma_ctrl6_ch3_reg[15:13];
assign	rbwctral_rx_ch3_int          = pma_ctrl6_ch3_reg[12:11];
assign	rrx_cru_m_sel_ch3_int        = pma_ctrl6_ch3_reg[10:9];
assign	rrx_cru_div2_int[3]          = pma_ctrl6_ch3_reg[8];
assign	rrx_cru_ctl_ch3_int          = pma_ctrl6_ch3_reg[7:2];
assign	rltr_int[3]		     = pma_ctrl6_ch3_reg[1];
assign	rltd_int[3]		     = pma_ctrl6_ch3_reg[0];

// Outputs from PMA Per channel control register 7 for channel0 (4.8078h)
assign	risel_rx_ch0_int             = pma_ctrl7_ch0_reg[15:14];
assign	riupsel_rx_ch0_int           = pma_ctrl7_ch0_reg[13:12];
assign	ridnsel_rx_ch0_int           = pma_ctrl7_ch0_reg[11:10];
assign	rtesten_cp_rx_int[0]         = pma_ctrl7_ch0_reg[9];
assign	rtristate_cp_rx_int[0]       = pma_ctrl7_ch0_reg[8];
assign	rtestupen_cp_rx_int[0]       = pma_ctrl7_ch0_reg[7];
assign	rtestdnen_cp_rx_int[0]       = pma_ctrl7_ch0_reg[6];
assign	rrx_cru_m_ch0_int            = pma_ctrl7_ch0_reg[5:2];
assign	rrx_cru_l_ch0_int            = pma_ctrl7_ch0_reg[1:0];

// Outputs from PMA Per channel control register 7 for channel1 (4.8079h)
assign	risel_rx_ch1_int             = pma_ctrl7_ch1_reg[15:14];
assign	riupsel_rx_ch1_int           = pma_ctrl7_ch1_reg[13:12];
assign	ridnsel_rx_ch1_int           = pma_ctrl7_ch1_reg[11:10];
assign	rtesten_cp_rx_int[1]         = pma_ctrl7_ch1_reg[9];
assign	rtristate_cp_rx_int[1]       = pma_ctrl7_ch1_reg[8];
assign	rtestupen_cp_rx_int[1]       = pma_ctrl7_ch1_reg[7];
assign	rtestdnen_cp_rx_int[1]       = pma_ctrl7_ch1_reg[6];
assign	rrx_cru_m_ch1_int            = pma_ctrl7_ch1_reg[5:2];
assign	rrx_cru_l_ch1_int            = pma_ctrl7_ch1_reg[1:0];

// Outputs from PMA Per channel control register 7 for channel2 (4.807Ah)
assign	risel_rx_ch2_int             = pma_ctrl7_ch2_reg[15:14];
assign	riupsel_rx_ch2_int           = pma_ctrl7_ch2_reg[13:12];
assign	ridnsel_rx_ch2_int           = pma_ctrl7_ch2_reg[11:10];
assign	rtesten_cp_rx_int[2]         = pma_ctrl7_ch2_reg[9];
assign	rtristate_cp_rx_int[2]       = pma_ctrl7_ch2_reg[8];
assign	rtestupen_cp_rx_int[2]       = pma_ctrl7_ch2_reg[7];
assign	rtestdnen_cp_rx_int[2]       = pma_ctrl7_ch2_reg[6];
assign	rrx_cru_m_ch2_int            = pma_ctrl7_ch2_reg[5:2];
assign	rrx_cru_l_ch2_int            = pma_ctrl7_ch2_reg[1:0];

// Outputs from PMA Per channel control register 7 for channel3 (4.807Bh)
assign	risel_rx_ch3_int             = pma_ctrl7_ch3_reg[15:14];
assign	riupsel_rx_ch3_int           = pma_ctrl7_ch3_reg[13:12];
assign	ridnsel_rx_ch3_int           = pma_ctrl7_ch3_reg[11:10];
assign	rtesten_cp_rx_int[3]         = pma_ctrl7_ch3_reg[9];
assign	rtristate_cp_rx_int[3]       = pma_ctrl7_ch3_reg[8];
assign	rtestupen_cp_rx_int[3]       = pma_ctrl7_ch3_reg[7];
assign	rtestdnen_cp_rx_int[3]       = pma_ctrl7_ch3_reg[6];
assign	rrx_cru_m_ch3_int            = pma_ctrl7_ch3_reg[5:2];
assign	rrx_cru_l_ch3_int            = pma_ctrl7_ch3_reg[1:0];

// Outputs from PMA Per channel control register 8 for channel0 (4.807Ch)
assign	rs_lpbk_int[0]        	     = pma_ctrl8_ch0_reg[15];
assign	r_rlpbk_int[0]        	     = pma_ctrl8_ch0_reg[14];
assign	rs_rdlpbk_int[0]             = pma_ctrl8_ch0_reg[13];
assign	rrx_revlb_sw_int[0]          = pma_ctrl8_ch0_reg[12];
assign	rurx_pdb_int[0]        	     = pma_ctrl8_ch0_reg[11];
assign	rtx_cgb_pdb_int[0]           = pma_ctrl8_ch0_reg[10];
assign	rtx_ob_pdb_int[0]            = pma_ctrl8_ch0_reg[9];
assign	rrx_cru_pdb_int[0]           = pma_ctrl8_ch0_reg[8];
assign	rrx_cru_rst_int[0]           = pma_ctrl8_ch0_reg[7];
assign	rrx_ib_pdb_int[0]            = pma_ctrl8_ch0_reg[6];
assign	rrxurstpma_md[0]             = pma_ctrl8_ch0_reg[5];
assign	radce_adapt_int[0]           = pma_ctrl8_ch0_reg[4];
assign	radce_pdb_int[0]             = pma_ctrl8_ch0_reg[3];
assign	radce_rst_int[0]             = pma_ctrl8_ch0_reg[2];
assign	rsig_inv_2tap_int[0]         = pma_ctrl8_ch0_reg[1];
assign	rsig_inv_pre_int[0]          = pma_ctrl8_ch0_reg[0];

// Outputs from PMA Per channel control register 8 for channel1 (4.807Dh)
assign	rs_lpbk_int[1]        	     = pma_ctrl8_ch1_reg[15];
assign	r_rlpbk_int[1]        	     = pma_ctrl8_ch1_reg[14];
assign	rs_rdlpbk_int[1]             = pma_ctrl8_ch1_reg[13];
assign	rrx_revlb_sw_int[1]          = pma_ctrl8_ch1_reg[12];
assign	rurx_pdb_int[1]        	     = pma_ctrl8_ch1_reg[11];
assign	rtx_cgb_pdb_int[1]           = pma_ctrl8_ch1_reg[10];
assign	rtx_ob_pdb_int[1]            = pma_ctrl8_ch1_reg[9];
assign	rrx_cru_pdb_int[1]           = pma_ctrl8_ch1_reg[8];
assign	rrx_cru_rst_int[1]           = pma_ctrl8_ch1_reg[7];
assign	rrx_ib_pdb_int[1]            = pma_ctrl8_ch1_reg[6];
assign	rrxurstpma_md[1]             = pma_ctrl8_ch1_reg[5];
assign	radce_adapt_int[1]           = pma_ctrl8_ch1_reg[4];
assign	radce_pdb_int[1]             = pma_ctrl8_ch1_reg[3];
assign	radce_rst_int[1]             = pma_ctrl8_ch1_reg[2];
assign	rsig_inv_2tap_int[1]         = pma_ctrl8_ch1_reg[1];
assign	rsig_inv_pre_int[1]          = pma_ctrl8_ch1_reg[0];

// Outputs from PMA Per channel control register 8 for channel2 (4.807Eh)
assign	rs_lpbk_int[2]        	     = pma_ctrl8_ch2_reg[15];
assign	r_rlpbk_int[2]        	     = pma_ctrl8_ch2_reg[14];
assign	rs_rdlpbk_int[2]             = pma_ctrl8_ch2_reg[13];
assign	rrx_revlb_sw_int[2]          = pma_ctrl8_ch2_reg[12];
assign	rurx_pdb_int[2]        	     = pma_ctrl8_ch2_reg[11];
assign	rtx_cgb_pdb_int[2]           = pma_ctrl8_ch2_reg[10];
assign	rtx_ob_pdb_int[2]            = pma_ctrl8_ch2_reg[9];
assign	rrx_cru_pdb_int[2]           = pma_ctrl8_ch2_reg[8];
assign	rrx_cru_rst_int[2]           = pma_ctrl8_ch2_reg[7];
assign	rrx_ib_pdb_int[2]            = pma_ctrl8_ch2_reg[6];
assign	rrxurstpma_md[2]             = pma_ctrl8_ch2_reg[5];
assign	radce_adapt_int[2]           = pma_ctrl8_ch2_reg[4];
assign	radce_pdb_int[2]             = pma_ctrl8_ch2_reg[3];
assign	radce_rst_int[2]             = pma_ctrl8_ch2_reg[2];
assign	rsig_inv_2tap_int[2]         = pma_ctrl8_ch2_reg[1];
assign	rsig_inv_pre_int[2]          = pma_ctrl8_ch2_reg[0];

// Outputs from PMA Per channel control register 8 for channel3 (4.807Fh)
assign	rs_lpbk_int[3]        	     = pma_ctrl8_ch3_reg[15];
assign	r_rlpbk_int[3]        	     = pma_ctrl8_ch3_reg[14];
assign	rs_rdlpbk_int[3]             = pma_ctrl8_ch3_reg[13];
assign	rrx_revlb_sw_int[3]          = pma_ctrl8_ch3_reg[12];
assign	rurx_pdb_int[3]        	     = pma_ctrl8_ch3_reg[11];
assign	rtx_cgb_pdb_int[3]           = pma_ctrl8_ch3_reg[10];
assign	rtx_ob_pdb_int[3]            = pma_ctrl8_ch3_reg[9];
assign	rrx_cru_pdb_int[3]           = pma_ctrl8_ch3_reg[8];
assign	rrx_cru_rst_int[3]           = pma_ctrl8_ch3_reg[7];
assign	rrx_ib_pdb_int[3]            = pma_ctrl8_ch3_reg[6];
assign	rrxurstpma_md[3]             = pma_ctrl8_ch3_reg[5];
assign	radce_adapt_int[3]           = pma_ctrl8_ch3_reg[4];
assign	radce_pdb_int[3]             = pma_ctrl8_ch3_reg[3];
assign	radce_rst_int[3]             = pma_ctrl8_ch3_reg[2];
assign	rsig_inv_2tap_int[3]         = pma_ctrl8_ch3_reg[1];
assign	rsig_inv_pre_int[3]          = pma_ctrl8_ch3_reg[0];

// Outputs from PMA Per channel control register 9 for channel0 (4.8080h)
assign	rseq_sel_ch0_int	     = pma_ctrl9_ch0_reg[15:14];
assign	rrgen_set_ch0_int	     = pma_ctrl9_ch0_reg[13:11];
assign	rclkdiv_ch0_int 	     = pma_ctrl9_ch0_reg[10:7];
assign	rf_lpf_ch0_int  	     = pma_ctrl9_ch0_reg[6:5];
assign	rf_hpf_ch0_int  	     = pma_ctrl9_ch0_reg[4:3];
assign	rrgen_bw_ch0_int  	     = pma_ctrl9_ch0_reg[2:1];

// Outputs from PMA Per channel control register 9 for channel1 (4.8081h)
assign	rseq_sel_ch1_int	     = pma_ctrl9_ch1_reg[15:14];
assign	rrgen_set_ch1_int	     = pma_ctrl9_ch1_reg[13:11];
assign	rclkdiv_ch1_int 	     = pma_ctrl9_ch1_reg[10:7];
assign	rf_lpf_ch1_int  	     = pma_ctrl9_ch1_reg[6:5];
assign	rf_hpf_ch1_int  	     = pma_ctrl9_ch1_reg[4:3];
assign	rrgen_bw_ch1_int  	     = pma_ctrl9_ch1_reg[2:1];

// Outputs from PMA Per channel control register 9 for channel2 (4.8082h)
assign	rseq_sel_ch2_int	     = pma_ctrl9_ch2_reg[15:14];
assign	rrgen_set_ch2_int	     = pma_ctrl9_ch2_reg[13:11];
assign	rclkdiv_ch2_int 	     = pma_ctrl9_ch2_reg[10:7];
assign	rf_lpf_ch2_int  	     = pma_ctrl9_ch2_reg[6:5];
assign	rf_hpf_ch2_int  	     = pma_ctrl9_ch2_reg[4:3];
assign	rrgen_bw_ch2_int  	     = pma_ctrl9_ch2_reg[2:1];

// Outputs from PMA Per channel control register 9 for channel3 (4.8083h)
assign	rseq_sel_ch3_int	     = pma_ctrl9_ch3_reg[15:14];
assign	rrgen_set_ch3_int	     = pma_ctrl9_ch3_reg[13:11];
assign	rclkdiv_ch3_int 	     = pma_ctrl9_ch3_reg[10:7];
assign	rf_lpf_ch3_int  	     = pma_ctrl9_ch3_reg[6:5];
assign	rf_hpf_ch3_int  	     = pma_ctrl9_ch3_reg[4:3];
assign	rrgen_bw_ch3_int  	     = pma_ctrl9_ch3_reg[2:1];

// Outputs from PMA Per channel control register 10 for channel0 (4.8084h)
assign	rhyst_ch0_int	             = pma_ctrl10_ch0_reg[15:13];
assign	rd2a_res_ch0_int	     = pma_ctrl10_ch0_reg[12:11];
assign	rrgen_vod_ch0_int	     = pma_ctrl10_ch0_reg[10:8];
assign	rlf_os_ch0_int	             = pma_ctrl10_ch0_reg[7:4];
assign	rhf_os_ch0_int	             = pma_ctrl10_ch0_reg[3:0];

// Outputs from PMA Per channel control register 10 for channel1 (4.8085h)
assign	rhyst_ch1_int	             = pma_ctrl10_ch1_reg[15:13];
assign	rd2a_res_ch1_int	     = pma_ctrl10_ch1_reg[12:11];
assign	rrgen_vod_ch1_int	     = pma_ctrl10_ch1_reg[10:8];
assign	rlf_os_ch1_int	             = pma_ctrl10_ch1_reg[7:4];
assign	rhf_os_ch1_int	             = pma_ctrl10_ch1_reg[3:0];

// Outputs from PMA Per channel control register 10 for channel2 (4.8086h)
assign	rhyst_ch2_int	             = pma_ctrl10_ch2_reg[15:13];
assign	rd2a_res_ch2_int	     = pma_ctrl10_ch2_reg[12:11];
assign	rrgen_vod_ch2_int	     = pma_ctrl10_ch2_reg[10:8];
assign	rlf_os_ch2_int	             = pma_ctrl10_ch2_reg[7:4];
assign	rhf_os_ch2_int	             = pma_ctrl10_ch2_reg[3:0];

// Outputs from PMA Per channel control register 10 for channel3 (4.8087h)
assign	rhyst_ch3_int	             = pma_ctrl10_ch3_reg[15:13];
assign	rd2a_res_ch3_int	     = pma_ctrl10_ch3_reg[12:11];
assign	rrgen_vod_ch3_int	     = pma_ctrl10_ch3_reg[10:8];
assign	rlf_os_ch3_int	             = pma_ctrl10_ch3_reg[7:4];
assign	rhf_os_ch3_int	             = pma_ctrl10_ch3_reg[3:0];

// Outputs from PMA Per channel control register 11 for channel0 (4.8088h)
assign	r_iqclk_ch0_int    	     = pma_ctrl11_ch0_reg[15:12];
assign	r_dfe_ch0_int     	     = pma_ctrl11_ch0_reg[11:6];
assign	r_cp_mode_int[0]    	     = pma_ctrl11_ch0_reg[5];
assign	rreg_cp_rx_int[0]    	     = pma_ctrl11_ch0_reg[4];
assign	r_impctrl_ch0_int    	     = pma_ctrl11_ch0_reg[3:2];
assign	rpd_ien_int[0]    	     = pma_ctrl11_ch0_reg[1];

// Outputs from PMA Per channel control register 11 for channel1 (4.8089h)
assign	r_iqclk_ch1_int    	     = pma_ctrl11_ch1_reg[15:12];
assign	r_dfe_ch1_int     	     = pma_ctrl11_ch1_reg[11:6];
assign	r_cp_mode_int[1]    	     = pma_ctrl11_ch1_reg[5];
assign	rreg_cp_rx_int[1]    	     = pma_ctrl11_ch1_reg[4];
assign	r_impctrl_ch1_int    	     = pma_ctrl11_ch1_reg[3:2];
assign	rpd_ien_int[1]    	     = pma_ctrl11_ch1_reg[1];

// Outputs from PMA Per channel control register 11 for channel2 (4.808Ah)
assign	r_iqclk_ch2_int    	     = pma_ctrl11_ch2_reg[15:12];
assign	r_dfe_ch2_int     	     = pma_ctrl11_ch2_reg[11:6];
assign	r_cp_mode_int[2]    	     = pma_ctrl11_ch2_reg[5];
assign	rreg_cp_rx_int[2]    	     = pma_ctrl11_ch2_reg[4];
assign	r_impctrl_ch2_int    	     = pma_ctrl11_ch2_reg[3:2];
assign	rpd_ien_int[2]    	     = pma_ctrl11_ch2_reg[1];

// Outputs from PMA Per channel control register 11 for channel3 (4.808Bh)
assign	r_iqclk_ch3_int    	     = pma_ctrl11_ch3_reg[15:12];
assign	r_dfe_ch3_int     	     = pma_ctrl11_ch3_reg[11:6];
assign	r_cp_mode_int[3]    	     = pma_ctrl11_ch3_reg[5];
assign	rreg_cp_rx_int[3]    	     = pma_ctrl11_ch3_reg[4];
assign	r_impctrl_ch3_int    	     = pma_ctrl11_ch3_reg[3:2];
assign	rpd_ien_int[3]    	     = pma_ctrl11_ch3_reg[1];


// Outputs from PMA Global control register 0 (4.8090h)
assign	rbgbypass_int	          = pma_global_ctrl0_reg[15];
assign	rlst_bg_int	          = pma_global_ctrl0_reg[13:10];
assign	rcmu_rst_int	          = pma_global_ctrl0_reg[9];
assign  rcmu2_isel_int            = pma_global_ctrl0_reg[5:4]; 
assign	rcmu0_isel_int	          = pma_global_ctrl0_reg[3:2];
assign	rcmu1_isel_int	          = pma_global_ctrl0_reg[1:0];

// Outputs from PMA Global control register 1 (4.8091h)
assign	rcmu0_iupsel_int        = pma_global_ctrl1_reg[15:14];
assign	rcmu1_iupsel_int        = pma_global_ctrl1_reg[13:12];
assign	rcmu2_iupsel_int        = pma_global_ctrl1_reg[11:10];
assign	rcmu0_idnsel_int        = pma_global_ctrl1_reg[9:8];
assign	rcmu1_idnsel_int        = pma_global_ctrl1_reg[7:6];
assign	rcmu2_idnsel_int        = pma_global_ctrl1_reg[5:4];
assign	rcmu0_testen_cp_int     = pma_global_ctrl1_reg[3];
assign	rcmu1_testen_cp_int     = pma_global_ctrl1_reg[2];
assign	rcmu0_tristate_cp_int   = pma_global_ctrl1_reg[1];
assign	rcmu1_tristate_cp_int   = pma_global_ctrl1_reg[0];

// Outputs from PMA Global control register 2 (4.8092h)
assign	rcmu0_lst_int		= pma_global_ctrl2_reg[13:10];
assign	rcmu1_lst_int		= pma_global_ctrl2_reg[9:6];
assign	rcmu0_div2_int		= pma_global_ctrl2_reg[5];
assign	rcmu1_div2_int		= pma_global_ctrl2_reg[4];
assign	rcmu0_ref_sel_int	= pma_global_ctrl2_reg[3:2];
assign	rcmu1_ref_sel_int	= pma_global_ctrl2_reg[1:0];

// Outputs from PMA Global control register 3 (4.8093h)
assign	rcmu0_ctl_int	        = pma_global_ctrl3_reg[15:8];
assign	rcmu1_ctl_int	        = pma_global_ctrl3_reg[7:0];

// Outputs from PMA Global control register 4 (4.8094h)
assign	rcmu0_m_int		= pma_global_ctrl4_reg[15:12];
assign	rcmu1_m_int		= pma_global_ctrl4_reg[11:8];
assign	rcmu0_l_int		= pma_global_ctrl4_reg[7:6];
assign	rcmu1_l_int		= pma_global_ctrl4_reg[5:4];
assign	rcmu0_pdb_int		= pma_global_ctrl4_reg[3];
assign	rcmu1_pdb_int		= pma_global_ctrl4_reg[2];
assign	rcmu0_txpll_rst_int	= pma_global_ctrl4_reg[1];
assign	rcmu1_txpll_rst_int	= pma_global_ctrl4_reg[0];

// Outputs from PMA Global control register 5 (4.8095h)
assign  rpma_testbus_sel_int    = pma_global_ctrl5_reg[15:12];
assign	rcmu_peclrx0_cm_int	= pma_global_ctrl5_reg[11:8];
assign	rcmu_peclrx1_cm_int	= pma_global_ctrl5_reg[7:4];
assign	rcmu0_testupen_cp_int	= pma_global_ctrl5_reg[3];
assign	rcmu1_testupen_cp_int	= pma_global_ctrl5_reg[2];
assign	rcmu0_testdnen_cp_int	= pma_global_ctrl5_reg[1];
assign	rcmu1_testdnen_cp_int	= pma_global_ctrl5_reg[0];

// Outputs from PMA Global control register 6 (4.8096h)
assign	rcmu_peclrx0_lst_int	    = pma_global_ctrl6_reg[15:12];
assign	rcmu_peclrx1_lst_int	    = pma_global_ctrl6_reg[11:8];
assign  rcmu_iqclkout_sel_int       = pma_global_ctrl6_reg[6];
assign  rcmu_txpll0_iqclkin_sel_int = pma_global_ctrl6_reg[5:3];
assign  rcmu_txpll1_iqclkin_sel_int = pma_global_ctrl6_reg[2:0];

// Outputs from PMA Global control register 7 (4.8097h)
assign  rcmu_cgb_cmusel_int     = pma_global_ctrl7_reg[15:14];
assign  rcmu_cgb_ndiv_int       = pma_global_ctrl7_reg[13:12];
assign  rcmu_cgb_div5_int       = pma_global_ctrl7_reg[11];
assign  rcmu_cgb_div2_int       = pma_global_ctrl7_reg[10];
assign  rcmu_cgb_vcobypass_int  = pma_global_ctrl7_reg[9];
assign	rcmu_txpll0_1x_en_int	= pma_global_ctrl7_reg[8];
assign	rcmu_txpll1_1x_en_int	= pma_global_ctrl7_reg[7];
assign  rcmu_cgb_4x_en_int      = pma_global_ctrl7_reg[6];
assign  rcmu_cgb_8x_en_int      = pma_global_ctrl7_reg[5];
assign  rcmu_cgb_pclksel_int    = pma_global_ctrl7_reg[4];

// Outputs from PMA Global control register 8 (4.8098h)
assign  rcmu2_testen_cp_int     = pma_global_ctrl8_reg[15];
assign  rcmu2_tristate_cp_int   = pma_global_ctrl8_reg[14];
assign  rcmu2_testupen_cp_int   = pma_global_ctrl8_reg[13];
assign  rcmu2_testdnen_cp_int   = pma_global_ctrl8_reg[12];
assign  rcmu2_lst_int           = pma_global_ctrl8_reg[11:8];
assign  rcmu2_ctl_int           = pma_global_ctrl8_reg[7:0];

// Outputs from PMA Global control register 9 (4.8099h)
assign  rcmu2_refsel_int        = pma_global_ctrl9_reg[15];
assign  rcmu2_m_int             = pma_global_ctrl9_reg[14:11];
assign  rcmu2_l_int             = pma_global_ctrl9_reg[10:9];
assign  rcmu2_pdb_int           = pma_global_ctrl9_reg[8];
assign  rcmu2_txpll_rst_int     = pma_global_ctrl9_reg[7];
assign  rcmu0_rcp_mode_int      = pma_global_ctrl9_reg[6];
assign  rcmu1_rcp_mode_int      = pma_global_ctrl9_reg[5];

//Control and Status Registers instantiation

// Status Register
arriagx_hssi_bsc_out local_fault_0  (.reset (mdio_rst),
                        .clk (mdc),
                        .sig_in (local_fault),
                        .jtag_mode (jtag_mode),
                        .si (chain[126]),
                        .shift_load (jtag_shift_load),
                        .sig_out (local_fault_ext),
                        .so (chain[127]));

arriagx_hssi_bsc_out xs_link_status_0 (.reset (mdio_rst),
                        .clk (mdc),
                        .sig_in (xs_link_status),
                        .jtag_mode (jtag_mode),
                        .si (chain[125]),
                        .shift_load (jtag_shift_load),
                        .sig_out (xs_link_status_ext),
                        .so (chain[126]));

arriagx_hssi_bsc_out rx_local_fault_0 (.reset (mdio_rst),
                        .clk (mdc),
                        .sig_in (rx_local_fault),
                        .jtag_mode (jtag_mode),
                        .si (chain[124]),
                        .shift_load (jtag_shift_load),
                        .sig_out (rx_local_fault_ext),
                        .so (chain[125]));

arriagx_hssi_bsc_out tx_local_fault_0 (.reset (mdio_rst),
                        .clk (mdc),
                        .sig_in (tx_local_fault),
                        .jtag_mode (jtag_mode),
                        .si (chain[123]),
                        .shift_load (jtag_shift_load),
                        .sig_out (tx_local_fault_ext),
                        .so (chain[124]));

// Single control bits
arriagx_hssi_bsc_in_r xs_link_status_set (.reset (mdio_rst), 
                             .clk (mdc), 
                             .sig_in (xs_link_status_rd), 
                             .ext_in (rxs_link_status_set), 
                             .jtag_mode (jtag_mode), 
                             .si (chain[122]), 
                             .shift (jtag_shift_load), 
                             .mdio_dis (mdio_dis),
                             .sig_out (rxs_link_status_set_int), 
                             .so (chain[123]));

arriagx_hssi_bsc_in_r tx_rx_local_fault_clr (.reset (mdio_rst), 
                                .clk (mdc), 
                                .sig_in (tx_rx_local_fault_status_rd), 
                                .ext_in (rtx_rx_local_fault_clr), 
                                .jtag_mode (jtag_mode), 
                                .si (1'b0), 
                                .shift (jtag_shift_load), 
                                .mdio_dis (mdio_dis),
                                .sig_out (rtx_rx_local_fault_clr_int), 
                                .so (chain[122]));
                        

// Main control registers instantiation
arriagx_hssi_ctrl_reg xgxs_ctrl_0    (.reset (mdio_rst),
                         .mdio_wr (mdio_wr),
                         .reg_addr (reg_addr),
                         .target_addr (XGXS_CTRL),
                         .clk (mdc),
                         .sig_in (mbus_in),
                         .ext_in (xgxs_ctrl_ext),
                         .jtag_mode (jtag_mode),
                         .si (chain[121]),
                         .shift (jtag_shift_load),
                         .mdio_dis (mdio_dis),
                         .sig_out (xgxs_ctrl_reg),
                         .so (jtag_so));

arriagx_hssi_ctrl_reg trunking_mode_0 (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (TRUNKING_MODE),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (trunking_mode_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[120]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (trunking_mode_reg),
                        .so (chain[121]));

arriagx_hssi_ctrl_reg pcs_ctrl1_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL1_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl1_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[119]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl1_ch0_reg),
                        .so (chain[120]));

arriagx_hssi_ctrl_reg pcs_ctrl1_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL1_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl1_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[118]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl1_ch1_reg),
                        .so (chain[119]));

arriagx_hssi_ctrl_reg pcs_ctrl1_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL1_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl1_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[117]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl1_ch2_reg),
                        .so (chain[118]));

arriagx_hssi_ctrl_reg pcs_ctrl1_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL1_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl1_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[116]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl1_ch3_reg),
                        .so (chain[117]));

arriagx_hssi_ctrl_reg pcs_ctrl2_0    (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL2_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl2_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[115]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl2_ch0_reg),
                        .so (chain[116]));

arriagx_hssi_ctrl_reg pcs_ctrl2_1    (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL2_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl2_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[114]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl2_ch1_reg),
                        .so (chain[115]));

arriagx_hssi_ctrl_reg pcs_ctrl2_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL2_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl2_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[113]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl2_ch2_reg),
                        .so (chain[114]));

arriagx_hssi_ctrl_reg pcs_ctrl2_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL2_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl2_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[112]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl2_ch3_reg),
                        .so (chain[113]));

arriagx_hssi_ctrl_reg pcs_ctrl3_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL3_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl3_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[111]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl3_ch0_reg),
                        .so (chain[112]));

arriagx_hssi_ctrl_reg pcs_ctrl3_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL3_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl3_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[110]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl3_ch1_reg),
                        .so (chain[111]));

arriagx_hssi_ctrl_reg pcs_ctrl3_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL3_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl3_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[109]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl3_ch2_reg),
                        .so (chain[110]));

arriagx_hssi_ctrl_reg pcs_ctrl3_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL3_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl3_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[108]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl3_ch3_reg),
                        .so (chain[109]));

arriagx_hssi_ctrl_reg pcs_ctrl4_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL4_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl4_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[107]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl4_ch0_reg),
                        .so (chain[108]));

arriagx_hssi_ctrl_reg pcs_ctrl4_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL4_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl4_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[106]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl4_ch1_reg),
                        .so (chain[107]));

arriagx_hssi_ctrl_reg pcs_ctrl4_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL4_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl4_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[105]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl4_ch2_reg),
                        .so (chain[106]));

arriagx_hssi_ctrl_reg pcs_ctrl4_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL4_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl4_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[104]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl4_ch3_reg),
                        .so (chain[105]));

arriagx_hssi_ctrl_reg pcs_ctrl5_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL5_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl5_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[103]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl5_ch0_reg),
                        .so (chain[104]));

arriagx_hssi_ctrl_reg pcs_ctrl5_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL5_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl5_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[102]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl5_ch1_reg),
                        .so (chain[103]));

arriagx_hssi_ctrl_reg pcs_ctrl5_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL5_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl5_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[101]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl5_ch2_reg),
                        .so (chain[102]));

arriagx_hssi_ctrl_reg pcs_ctrl5_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL5_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl5_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[100]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl5_ch3_reg),
                        .so (chain[101]));

arriagx_hssi_ctrl_reg pcs_ctrl6_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL6_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl6_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[99]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl6_ch0_reg),
                        .so (chain[100]));

arriagx_hssi_ctrl_reg pcs_ctrl6_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL6_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl6_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[98]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl6_ch1_reg),
                        .so (chain[99]));

arriagx_hssi_ctrl_reg pcs_ctrl6_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL6_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl6_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[97]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl6_ch2_reg),
                        .so (chain[98]));

arriagx_hssi_ctrl_reg pcs_ctrl6_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL6_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl6_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[96]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl6_ch3_reg),
                        .so (chain[97]));
                        
arriagx_hssi_ctrl_reg pcs_ctrl7_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL7_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl7_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[95]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl7_ch0_reg),
                        .so (chain[96]));

arriagx_hssi_ctrl_reg pcs_ctrl7_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL7_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl7_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[94]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl7_ch1_reg),
                        .so (chain[95]));

arriagx_hssi_ctrl_reg pcs_ctrl7_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL7_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl7_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[93]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl7_ch2_reg),
                        .so (chain[94]));

arriagx_hssi_ctrl_reg pcs_ctrl7_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL7_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl7_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[92]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl7_ch3_reg),
                        .so (chain[93]));

arriagx_hssi_ctrl_reg pcs_ctrl8_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL8_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl8_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[91]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl8_ch0_reg),
                        .so (chain[92]));

arriagx_hssi_ctrl_reg pcs_ctrl8_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL8_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl8_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[90]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl8_ch1_reg),
                        .so (chain[91]));

arriagx_hssi_ctrl_reg pcs_ctrl8_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL8_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl8_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[89]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl8_ch2_reg),
                        .so (chain[90]));

arriagx_hssi_ctrl_reg pcs_ctrl8_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL8_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl8_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[88]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl8_ch3_reg),
                        .so (chain[89]));

arriagx_hssi_ctrl_reg bist_prbs_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PRBS_BIST_CTRL_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (prbs_bist_ctrl_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[87]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (prbs_bist_ctrl_ch0_reg),
                        .so (chain[88]));

arriagx_hssi_ctrl_reg bist_prbs_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PRBS_BIST_CTRL_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (prbs_bist_ctrl_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[86]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (prbs_bist_ctrl_ch1_reg),
                        .so (chain[87]));

arriagx_hssi_ctrl_reg bist_prbs_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PRBS_BIST_CTRL_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (prbs_bist_ctrl_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[85]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (prbs_bist_ctrl_ch2_reg),
                        .so (chain[86]));

arriagx_hssi_ctrl_reg bist_prbs_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PRBS_BIST_CTRL_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (prbs_bist_ctrl_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[84]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (prbs_bist_ctrl_ch3_reg),
                        .so (chain[85]));


arriagx_hssi_ctrl_reg pcs_ctrl9_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL9_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl9_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[83]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl9_ch0_reg),
                        .so (chain[84]));

arriagx_hssi_ctrl_reg pcs_ctrl9_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL9_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl9_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[82]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl9_ch1_reg),
                        .so (chain[83]));

arriagx_hssi_ctrl_reg pcs_ctrl9_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL9_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl9_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[81]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl9_ch2_reg),
                        .so (chain[82]));

arriagx_hssi_ctrl_reg pcs_ctrl9_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL9_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl9_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[80]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl9_ch3_reg),
                        .so (chain[81]));                        

arriagx_hssi_ctrl_reg pcs_ctrl10_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL10_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl10_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[79]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl10_ch0_reg),
                        .so (chain[80]));

arriagx_hssi_ctrl_reg pcs_ctrl10_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL10_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl10_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[78]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl10_ch1_reg),
                        .so (chain[79]));

arriagx_hssi_ctrl_reg pcs_ctrl10_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL10_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl10_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[77]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl10_ch2_reg),
                        .so (chain[78]));

arriagx_hssi_ctrl_reg pcs_ctrl10_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL10_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl10_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[76]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl10_ch3_reg),
                        .so (chain[77]));

arriagx_hssi_ctrl_reg pcs_ctrl11_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL11_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl11_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[75]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl11_ch0_reg),
                        .so (chain[76]));

arriagx_hssi_ctrl_reg pcs_ctrl11_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL11_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl11_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[74]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl11_ch1_reg),
                        .so (chain[75]));

arriagx_hssi_ctrl_reg pcs_ctrl11_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL11_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl11_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[73]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl11_ch2_reg),
                        .so (chain[74]));

arriagx_hssi_ctrl_reg pcs_ctrl11_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL11_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl11_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[72]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl11_ch3_reg),
                        .so (chain[73]));

arriagx_hssi_ctrl_reg pcs_ctrl12_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL12_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl12_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[71]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl12_ch0_reg),
                        .so (chain[72]));

arriagx_hssi_ctrl_reg pcs_ctrl12_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL12_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl12_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[70]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl12_ch1_reg),
                        .so (chain[71]));

arriagx_hssi_ctrl_reg pcs_ctrl12_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL12_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl12_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[69]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl12_ch2_reg),
                        .so (chain[70]));

arriagx_hssi_ctrl_reg pcs_ctrl12_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL12_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl12_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[68]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl12_ch3_reg),
                        .so (chain[69]));

arriagx_hssi_ctrl_reg pcs_ctrl13_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL13_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl13_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[67]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl13_ch0_reg),
                        .so (chain[68]));

arriagx_hssi_ctrl_reg pcs_ctrl13_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL13_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl13_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[66]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl13_ch1_reg),
                        .so (chain[67]));

arriagx_hssi_ctrl_reg pcs_ctrl13_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL13_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl13_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[65]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl13_ch2_reg),
                        .so (chain[66]));

arriagx_hssi_ctrl_reg pcs_ctrl13_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL13_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl13_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[64]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl13_ch3_reg),
                        .so (chain[65]));
                        
arriagx_hssi_ctrl_reg pcs_ctrl14_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL14_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl14_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[63]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl14_ch0_reg),
                        .so (chain[64]));

arriagx_hssi_ctrl_reg pcs_ctrl14_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL14_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl14_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[62]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl14_ch1_reg),
                        .so (chain[63]));

arriagx_hssi_ctrl_reg pcs_ctrl14_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL14_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl14_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[61]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl14_ch2_reg),
                        .so (chain[62]));

arriagx_hssi_ctrl_reg pcs_ctrl14_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL14_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl14_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[60]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl14_ch3_reg),
                        .so (chain[61]));                        

arriagx_hssi_ctrl_reg pcs_ctrl15_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL15_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl15_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[59]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl15_ch0_reg),
                        .so (chain[60]));

arriagx_hssi_ctrl_reg pcs_ctrl15_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL15_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl15_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[58]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl15_ch1_reg),
                        .so (chain[59]));

arriagx_hssi_ctrl_reg pcs_ctrl15_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL15_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl15_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[57]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl15_ch2_reg),
                        .so (chain[58]));

arriagx_hssi_ctrl_reg pcs_ctrl15_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PCS_CTRL15_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pcs_ctrl15_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[56]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pcs_ctrl15_ch3_reg),
                        .so (chain[57]));
                        
arriagx_hssi_ctrl_reg pcs_global_ctrl0   (.reset (mdio_rst),
                             .mdio_wr (mdio_wr),
                             .reg_addr (reg_addr),
                             .target_addr (PCS_GLOBAL_CTRL0),
                             .clk (mdc),
                             .sig_in (mbus_in),
                             .ext_in (pcs_global_ctrl0_ext),
                             .jtag_mode (jtag_mode),
                             .si (chain[55]),
                             .shift (jtag_shift_load),
                             .mdio_dis (mdio_dis),
                             .sig_out (pcs_global_ctrl0_reg),
                             .so (chain[56]));
                        
arriagx_hssi_ctrl_reg pcs_global_ctrl1   (.reset (mdio_rst),
                             .mdio_wr (mdio_wr),
                             .reg_addr (reg_addr),
                             .target_addr (PCS_GLOBAL_CTRL1),
                             .clk (mdc),
                             .sig_in (mbus_in),
                             .ext_in (pcs_global_ctrl1_ext),
                             .jtag_mode (jtag_mode),
                             .si (chain[54]),
                             .shift (jtag_shift_load),
                             .mdio_dis (mdio_dis),
                             .sig_out (pcs_global_ctrl1_reg),
                             .so (chain[55]));

arriagx_hssi_ctrl_reg pcs_global_ctrl2   (.reset (mdio_rst),
                             .mdio_wr (mdio_wr),
                             .reg_addr (reg_addr),
                             .target_addr (PCS_GLOBAL_CTRL2),
                             .clk (mdc),
                             .sig_in (mbus_in),
                             .ext_in (pcs_global_ctrl2_ext),
                             .jtag_mode (jtag_mode),
                             .si (chain[53]),
                             .shift (jtag_shift_load),
                             .mdio_dis (mdio_dis),
                             .sig_out (pcs_global_ctrl2_reg),
                             .so (chain[54]));

arriagx_hssi_ctrl_reg pma_ctrl1_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL1_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl1_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[52]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl1_ch0_reg),
                        .so (chain[53]));

arriagx_hssi_ctrl_reg pma_ctrl1_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL1_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl1_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[51]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl1_ch1_reg),
                        .so (chain[52]));

arriagx_hssi_ctrl_reg pma_ctrl1_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL1_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl1_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[50]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl1_ch2_reg),
                        .so (chain[51]));

arriagx_hssi_ctrl_reg pma_ctrl1_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL1_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl1_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[49]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl1_ch3_reg),
                        .so (chain[50]));

arriagx_hssi_ctrl_reg pma_ctrl2_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL2_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl2_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[48]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl2_ch0_reg),
                        .so (chain[49]));

arriagx_hssi_ctrl_reg pma_ctrl2_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL2_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl2_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[47]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl2_ch1_reg),
                        .so (chain[48]));

arriagx_hssi_ctrl_reg pma_ctrl2_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL2_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl2_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[46]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl2_ch2_reg),
                        .so (chain[47]));

arriagx_hssi_ctrl_reg pma_ctrl2_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL2_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl2_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[45]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl2_ch3_reg),
                        .so (chain[46]));

arriagx_hssi_ctrl_reg pma_ctrl3_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL3_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl3_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[44]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl3_ch0_reg),
                        .so (chain[45]));

arriagx_hssi_ctrl_reg pma_ctrl3_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL3_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl3_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[43]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl3_ch1_reg),
                        .so (chain[44]));

arriagx_hssi_ctrl_reg pma_ctrl3_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL3_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl3_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[42]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl3_ch2_reg),
                        .so (chain[43]));

arriagx_hssi_ctrl_reg pma_ctrl3_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL3_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl3_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[41]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl3_ch3_reg),
                        .so (chain[42]));

arriagx_hssi_ctrl_reg pma_ctrl4_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL4_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl4_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[40]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl4_ch0_reg),
                        .so (chain[41]));

arriagx_hssi_ctrl_reg pma_ctrl4_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL4_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl4_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[39]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl4_ch1_reg),
                        .so (chain[40]));

arriagx_hssi_ctrl_reg pma_ctrl4_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL4_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl4_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[38]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl4_ch2_reg),
                        .so (chain[39]));

arriagx_hssi_ctrl_reg pma_ctrl4_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL4_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl4_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[37]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl4_ch3_reg),
                        .so (chain[38]));

arriagx_hssi_ctrl_reg pma_ctrl5_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL5_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl5_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[36]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl5_ch0_reg),
                        .so (chain[37]));

arriagx_hssi_ctrl_reg pma_ctrl5_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL5_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl5_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[35]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl5_ch1_reg),
                        .so (chain[36]));

arriagx_hssi_ctrl_reg pma_ctrl5_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL5_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl5_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[34]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl5_ch2_reg),
                        .so (chain[35]));

arriagx_hssi_ctrl_reg pma_ctrl5_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL5_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl5_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[33]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl5_ch3_reg),
                        .so (chain[34]));

arriagx_hssi_ctrl_reg pma_ctrl6_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL6_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl6_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[32]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl6_ch0_reg),
                        .so (chain[33]));

arriagx_hssi_ctrl_reg pma_ctrl6_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL6_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl6_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[31]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl6_ch1_reg),
                        .so (chain[32]));

arriagx_hssi_ctrl_reg pma_ctrl6_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL6_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl6_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[30]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl6_ch2_reg),
                        .so (chain[31]));

arriagx_hssi_ctrl_reg pma_ctrl6_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL6_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl6_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[29]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl6_ch3_reg),
                        .so (chain[30]));

arriagx_hssi_ctrl_reg pma_ctrl7_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL7_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl7_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[28]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl7_ch0_reg),
                        .so (chain[29]));

arriagx_hssi_ctrl_reg pma_ctrl7_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL7_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl7_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[27]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl7_ch1_reg),
                        .so (chain[28]));

arriagx_hssi_ctrl_reg pma_ctrl7_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL7_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl7_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[26]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl7_ch2_reg),
                        .so (chain[27]));

arriagx_hssi_ctrl_reg pma_ctrl7_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL7_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl7_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[25]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl7_ch3_reg),
                        .so (chain[26]));

arriagx_hssi_ctrl_reg pma_ctrl8_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL8_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl8_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[24]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl8_ch0_reg),
                        .so (chain[25]));

arriagx_hssi_ctrl_reg pma_ctrl8_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL8_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl8_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[23]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl8_ch1_reg),
                        .so (chain[24]));
                        
arriagx_hssi_ctrl_reg pma_ctrl8_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL8_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl8_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[22]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl8_ch2_reg),
                        .so (chain[23]));
                        
arriagx_hssi_ctrl_reg pma_ctrl8_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL8_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl8_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[21]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl8_ch3_reg),
                        .so (chain[22]));

arriagx_hssi_ctrl_reg pma_ctrl9_0   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL9_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl9_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[20]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl9_ch0_reg),
                        .so (chain[21]));

arriagx_hssi_ctrl_reg pma_ctrl9_1   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL9_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl9_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[19]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl9_ch1_reg),
                        .so (chain[20]));

arriagx_hssi_ctrl_reg pma_ctrl9_2   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL9_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl9_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[18]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl9_ch2_reg),
                        .so (chain[19]));

arriagx_hssi_ctrl_reg pma_ctrl9_3   (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL9_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl9_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[17]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl9_ch3_reg),
                        .so (chain[18]));

arriagx_hssi_ctrl_reg pma_ctrl10_0  (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL10_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl10_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[16]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl10_ch0_reg),
                        .so (chain[17]));

arriagx_hssi_ctrl_reg pma_ctrl10_1  (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL10_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl10_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[15]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl10_ch1_reg),
                        .so (chain[16]));

arriagx_hssi_ctrl_reg pma_ctrl10_2  (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL10_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl10_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[14]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl10_ch2_reg),
                        .so (chain[15]));

arriagx_hssi_ctrl_reg pma_ctrl10_3  (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL10_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl10_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[13]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl10_ch3_reg),
                        .so (chain[14]));

arriagx_hssi_ctrl_reg pma_ctrl11_0  (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL11_CH0),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl11_ch0_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[12]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl11_ch0_reg),
                        .so (chain[13]));

arriagx_hssi_ctrl_reg pma_ctrl11_1  (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL11_CH1),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl11_ch1_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[11]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl11_ch1_reg),
                        .so (chain[12]));

arriagx_hssi_ctrl_reg pma_ctrl11_2  (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL11_CH2),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl11_ch2_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[10]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl11_ch2_reg),
                        .so (chain[11]));
                        
arriagx_hssi_ctrl_reg pma_ctrl11_3  (.reset (mdio_rst),
                        .mdio_wr (mdio_wr),
                        .reg_addr (reg_addr),
                        .target_addr (PMA_CTRL11_CH3),
                        .clk (mdc),
                        .sig_in (mbus_in),
                        .ext_in (pma_ctrl11_ch3_ext),
                        .jtag_mode (jtag_mode),
                        .si (chain[9]),
                        .shift (jtag_shift_load),
                        .mdio_dis (mdio_dis),
                        .sig_out (pma_ctrl11_ch3_reg),
                        .so (chain[10]));                        

arriagx_hssi_ctrl_reg pma_global_ctrl0 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL0),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl0_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[8]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl0_reg),
                          .so (chain[9]));
                        
arriagx_hssi_ctrl_reg pma_global_ctrl1 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL1),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl1_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[7]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl1_reg),
                          .so (chain[8]));

arriagx_hssi_ctrl_reg pma_global_ctrl2 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL2),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl2_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[6]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl2_reg),
                          .so (chain[7]));
                        
arriagx_hssi_ctrl_reg pma_global_ctrl3 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL3),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl3_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[5]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl3_reg),
                          .so (chain[6]));

arriagx_hssi_ctrl_reg pma_global_ctrl4 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL4),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl4_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[4]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl4_reg),
                          .so (chain[5]));

arriagx_hssi_ctrl_reg pma_global_ctrl5 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL5),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl5_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[3]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl5_reg),
                          .so (chain[4]));
                        
arriagx_hssi_ctrl_reg pma_global_ctrl6 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL6),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl6_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[2]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl6_reg),
                          .so (chain[3]));
                        
arriagx_hssi_ctrl_reg pma_global_ctrl7 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL7),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl7_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[1]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl7_reg),
                          .so (chain[2]));

arriagx_hssi_ctrl_reg pma_global_ctrl8 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL8),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl8_ext),
                          .jtag_mode (jtag_mode),
                          .si (chain[0]),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl8_reg),
                          .so (chain[1]));

arriagx_hssi_ctrl_reg pma_global_ctrl9 (.reset (mdio_rst),
                          .mdio_wr (mdio_wr),
                          .reg_addr (reg_addr),
                          .target_addr (PMA_GLOBAL_CTRL9),
                          .clk (mdc),
                          .sig_in (mbus_in),
                          .ext_in (pma_global_ctrl9_ext),
                          .jtag_mode (jtag_mode),
                          .si (jtag_si),
                          .shift (jtag_shift_load),
                          .mdio_dis (mdio_dis),
                          .sig_out (pma_global_ctrl9_reg),
                          .so (chain[0]));

endmodule
 

`timescale 1 ps / 1 ps

module arriagx_hssi_cmu_dprio_top(
	sync_status,
	align_status,
	mdio_in,              
	mdc,                  
	port_addr,
	dev_addr,
	mdio_dis,
    dprioload,
	mdio_rst,
	cmudividerdprioin,
	cmuplldprioin,
	cmudprioin,
	refclkdividerdprioin,
	rxdprioin,
	txdprioin,
	cmudividerdprioout,
	cmuplldprioout,
	cmudprioout,
	refclkdividerdprioout,
	rxdprioout,
	txdprioout,
	mdio_out,          
	data_enable_n,
	mdio_curr_st
);
parameter rx_dprio_width = 800;                     // 6.1
parameter tx_dprio_width = 400;                     // 6.1

input [3:0]   sync_status;
input         align_status;

// MDIO inputs/outpus
input         mdio_in;              
input         mdc;                  
input [4:0]   port_addr;
input [4:0]   dev_addr;
input         mdio_rst;   

input         mdio_dis;  // 1'b1=output CRAM (para), 1'b0=output MDIO control register
input         dprioload; // load MDIO control register with CRAM_ext (parameter). SER_SHFIT_LOAD?


input [29:0]  cmudividerdprioin;
input [119:0] cmuplldprioin;
input [29:0]  cmudprioin;
input [1:0]   refclkdividerdprioin;
input [rx_dprio_width - 1 : 0] rxdprioin;
input [tx_dprio_width - 1 : 0] txdprioin;

output [29:0]  cmudividerdprioout;
output [119:0] cmuplldprioout;
output [29:0]  cmudprioout;
output [1:0]   refclkdividerdprioout;
output [rx_dprio_width - 1 : 0] rxdprioout;
output [tx_dprio_width - 1 : 0] txdprioout;

output         mdio_out;          
output         data_enable_n;
output [2:0]   mdio_curr_st;

// external parameters

parameter rx0_phy = 0;
parameter rx1_phy = 1;
parameter rx2_phy = 2;
parameter rx3_phy = 3;

parameter tx0_phy = 0;
parameter tx1_phy = 1;
parameter tx2_phy = 2;
parameter tx3_phy = 3;

parameter rx0_cru_clock0_physical_mapping = "refclk0"; 
parameter rx0_cru_clock1_physical_mapping = "refclk1"; 
parameter rx0_cru_clock2_physical_mapping = "iq0"; 
parameter rx0_cru_clock3_physical_mapping = "iq1"; 
parameter rx0_cru_clock4_physical_mapping = "iq2"; 
parameter rx0_cru_clock5_physical_mapping = "iq3"; 
parameter rx0_cru_clock6_physical_mapping = "iq4"; 
parameter rx0_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx0_cru_clock8_physical_mapping = "cmu_div_clk";
parameter rx1_cru_clock0_physical_mapping = "refclk0"; 
parameter rx1_cru_clock1_physical_mapping = "refclk1"; 
parameter rx1_cru_clock2_physical_mapping = "iq0"; 
parameter rx1_cru_clock3_physical_mapping = "iq1"; 
parameter rx1_cru_clock4_physical_mapping = "iq2"; 
parameter rx1_cru_clock5_physical_mapping = "iq3"; 
parameter rx1_cru_clock6_physical_mapping = "iq4"; 
parameter rx1_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx1_cru_clock8_physical_mapping = "cmu_div_clk";
parameter rx2_cru_clock0_physical_mapping = "refclk0"; 
parameter rx2_cru_clock1_physical_mapping = "refclk1"; 
parameter rx2_cru_clock2_physical_mapping = "iq0"; 
parameter rx2_cru_clock3_physical_mapping = "iq1"; 
parameter rx2_cru_clock4_physical_mapping = "iq2"; 
parameter rx2_cru_clock5_physical_mapping = "iq3"; 
parameter rx2_cru_clock6_physical_mapping = "iq4"; 
parameter rx2_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx2_cru_clock8_physical_mapping = "cmu_div_clk";
parameter rx3_cru_clock0_physical_mapping = "refclk0"; 
parameter rx3_cru_clock1_physical_mapping = "refclk1"; 
parameter rx3_cru_clock2_physical_mapping = "iq0"; 
parameter rx3_cru_clock3_physical_mapping = "iq1"; 
parameter rx3_cru_clock4_physical_mapping = "iq2"; 
parameter rx3_cru_clock5_physical_mapping = "iq3"; 
parameter rx3_cru_clock6_physical_mapping = "iq4"; 
parameter rx3_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx3_cru_clock8_physical_mapping = "cmu_div_clk";

parameter tx0_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx0_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx1_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx1_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx2_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx2_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx3_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx3_pll_fast_clk1_physical_mapping = "pll1"; 

// cmupll
parameter pll0_phy = 0;
parameter pll1_phy = 1;
parameter pll2_phy = 2;

parameter pll0_inclk0_logical_to_physical_mapping = "iq0";
parameter pll0_inclk1_logical_to_physical_mapping = "iq1";
parameter pll0_inclk2_logical_to_physical_mapping = "iq2";
parameter pll0_inclk3_logical_to_physical_mapping = "iq3";
parameter pll0_inclk4_logical_to_physical_mapping = "iq4";
parameter pll0_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll0_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll0_inclk7_logical_to_physical_mapping = "clkrefclk1";
parameter pll1_inclk0_logical_to_physical_mapping = "iq0";
parameter pll1_inclk1_logical_to_physical_mapping = "iq1";
parameter pll1_inclk2_logical_to_physical_mapping = "iq2";
parameter pll1_inclk3_logical_to_physical_mapping = "iq3";
parameter pll1_inclk4_logical_to_physical_mapping = "iq4";
parameter pll1_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll1_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll1_inclk7_logical_to_physical_mapping = "clkrefclk1";
parameter pll2_inclk0_logical_to_physical_mapping = "iq0";
parameter pll2_inclk1_logical_to_physical_mapping = "iq1";
parameter pll2_inclk2_logical_to_physical_mapping = "iq2";
parameter pll2_inclk3_logical_to_physical_mapping = "iq3";
parameter pll2_inclk4_logical_to_physical_mapping = "iq4";
parameter pll2_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll2_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll2_inclk7_logical_to_physical_mapping = "clkrefclk1";

// DEBUG dump
parameter sim_dump_dprio_internal_reg_at_time = 0; // in ps
parameter sim_dump_filename = "sim_dprio_dump.txt";

// unused ports to be moved into reg
wire          jtag_mode;
wire          jtag_shift_load;
wire          jtag_si;
wire          jtag_so;   // wire

// status signals generated by PCS
wire          tx_local_fault;        // from tx_sm
wire          rx_local_fault;        // from rcv_sm
wire          xs_link_status;        // from rcv_sm

wire         local_fault_ext;       // Status signal wire
wire         xs_link_status_ext;    // Status signal wire
wire         rx_local_fault_ext;    // Status signal wire
wire         tx_local_fault_ext;    // Status signal wire

// interconnect wires --------------------------------------------------

// wires from addr
wire [15:0] reg_addr;             // addr --> reg

// wires from sm
wire         shift_addr;          // sm --> addr
wire         incr_addr;           // sm --> addr

wire         ld_cnt;              // sm --> cnt
wire [4:0]   cnt_val;             // sm --> cnt
wire         ld_data;             // sm --> cnt

wire         shift_in;             // sm --> ctl_data
wire         shift_out;            // sm --> ctl_data
wire         latch_ctl;            // sm --> ctl_data
wire         valid_addr_lt;        // sm --> ctl_data

wire         mdio_wr;              // sm --> reg         
wire         mdio_rd;              // sm --> reg         

wire [2:0]   curr_state; // sm --> top (../../pcs_central_testbus in central_chnnl)

// wires from cnt
wire         cnt_eq_0;            // cnt --> sm

// wires from ctl_data
wire [15:0]  mbus_in;             // ctl_data --> reg
wire         valid_addr;          // ctl_data --> sm
wire [1:0]   opcode;              // ctl_data --> sm

wire         mdio_out;            // ctl_data --> top
wire         data_enable_n;       // ctl_data --> top

// wires from reg
wire [15:0]  mbus_out;            // reg --> ctl_data

//wires to reg
wire dev_addr_0;


// primary input/output connections ---------------------------------------

// outputs
assign  mdio_curr_st = curr_state;  // from SM

// module instantiatations ------------------------------------------------

arriagx_hssi_mdio_addr mdio_addr_1 ( .reset (mdio_rst),               // from top
                        .mdc (mdc),                      // from top
                        .mdio_in (mdio_in),              // from top
                        .shift_addr (shift_addr),        // from sm
                        .incr_addr (incr_addr),          // from sm
                        .reg_addr (reg_addr)             // To (16-bit reg addr) reg 
                      );
                      
arriagx_hssi_mdio_cnt mdio_cnt_1 ( .reset (mdio_rst),
                      .mdc (mdc),
                      .ld_cnt (ld_cnt),                  // from sm
                      .cnt_val (cnt_val),                // from sm
                      .cnt_eq_0 (cnt_eq_0)               // to sm
                    );


arriagx_hssi_mdio_sm mdio_sm_1 ( .reset (mdio_rst),
                    .mdio_in (mdio_in),                 // from top                 
                    .mdc (mdc),
                    .opcode (opcode),                   // from ctl_data
                    .valid_addr (valid_addr),           // from ctl_data
                    .cnt_eq_0 (cnt_eq_0),               // from cnt
                    .shift_addr (shift_addr),           // to addr
                    .incr_addr (incr_addr),             // to addr
                    .mdio_wr (mdio_wr),                 // to reg
                    .mdio_rd (mdio_rd),                 // to reg
                    .shift_in (shift_in),               // to ctl_data
                    .shift_out (shift_out),             // to ctl_data
                    .latch_ctl (latch_ctl),             // to ctl_data
                    .ld_data (ld_data),                 // to ctl_data
                    .valid_addr_lt(valid_addr_lt),      // to cnt_data
                    .ld_cnt (ld_cnt),                   // to cnt
                    .cnt_val (cnt_val),                 // to cnt (5-bit)
                    .curr_state (curr_state)            // to top
                  );

arriagx_hssi_mdio_ctl_data mdio_ctl_data_1 ( .reset (mdio_rst),
                                .mdc (mdc),
                                .mdio_in (mdio_in),
                                .shift_in (shift_in),        // from sm
                                .shift_out (shift_out),      // frm sm
                                .ld_data (ld_data),          // from sm
                                .latch_ctl (latch_ctl),      // from sm
                                .port_addr (port_addr),
                                .dev_addr (dev_addr),
                                .valid_addr_lt(valid_addr_lt), // from sm
                                .mbus_out (mbus_out),          // from reg
                                .mdio_out (mdio_out),          // to top
                                .mbus_in (mbus_in),            // to reg 
                                .opcode (opcode),              // to sm
                                .valid_addr (valid_addr),      // to sm
                                .data_enable_n (data_enable_n) // to top
                              );
                              
assign dev_addr_0 = dev_addr[0];
                              
arriagx_hssi_cmu_dprio_reg mdio_reg_1  ( .mdc(mdc),       // from top        
                        .mdio_rst(mdio_rst),                  // from top
                        .mdio_dis (mdio_dis),                 // from top
                        .dprioload(dprioload),                // from top     
                        .align_status (align_status),         // from top   
                        .sync_status (sync_status),           // from top
                        .reg_addr(reg_addr),                  // from addr
                        .mdio_wr(mdio_wr),                    // from sm        
                        .mdio_rd(mdio_rd),                    // from sm
                        .dev_addr_0 (dev_addr_0),             // from top
                        .mbus_in(mbus_in),                    // from ctrl_data
                        
                        .cmudividerdprioin(cmudividerdprioin),  // CRAM in from para
                        .cmuplldprioin(cmuplldprioin),
                        .cmudprioin(cmudprioin),
                        .refclkdividerdprioin(refclkdividerdprioin),
                        .rxdprioin(rxdprioin),
                        .txdprioin(txdprioin),
                        .cmudividerdprioout(cmudividerdprioout),// CRAM out to channels
                        .cmuplldprioout(cmuplldprioout),
                        .cmudprioout(cmudprioout),
                        .refclkdividerdprioout(refclkdividerdprioout),
                        .rxdprioout(rxdprioout),
                        .txdprioout(txdprioout),
 			            
 			            .mbus_out(mbus_out)                  // to ctrl_data
 			); 
            defparam mdio_reg_1.rx0_phy = rx0_phy;
            defparam mdio_reg_1.rx1_phy = rx1_phy;
            defparam mdio_reg_1.rx2_phy = rx2_phy;
            defparam mdio_reg_1.rx3_phy = rx3_phy;

            defparam mdio_reg_1.tx0_phy = tx0_phy;
            defparam mdio_reg_1.tx1_phy = tx1_phy;
            defparam mdio_reg_1.tx2_phy = tx2_phy;
            defparam mdio_reg_1.tx3_phy = tx3_phy;

            defparam mdio_reg_1.rx_dprio_width = rx_dprio_width;
            defparam mdio_reg_1.tx_dprio_width = tx_dprio_width;

            defparam mdio_reg_1.rx0_cru_clock0_physical_mapping = rx0_cru_clock0_physical_mapping; 
            defparam mdio_reg_1.rx0_cru_clock1_physical_mapping = rx0_cru_clock1_physical_mapping; 
            defparam mdio_reg_1.rx0_cru_clock2_physical_mapping = rx0_cru_clock2_physical_mapping; 
            defparam mdio_reg_1.rx0_cru_clock3_physical_mapping = rx0_cru_clock3_physical_mapping; 
            defparam mdio_reg_1.rx0_cru_clock4_physical_mapping = rx0_cru_clock4_physical_mapping; 
            defparam mdio_reg_1.rx0_cru_clock5_physical_mapping = rx0_cru_clock5_physical_mapping; 
            defparam mdio_reg_1.rx0_cru_clock6_physical_mapping = rx0_cru_clock6_physical_mapping; 
            defparam mdio_reg_1.rx0_cru_clock7_physical_mapping = rx0_cru_clock7_physical_mapping; 
            defparam mdio_reg_1.rx0_cru_clock8_physical_mapping = rx0_cru_clock8_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock0_physical_mapping = rx1_cru_clock0_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock1_physical_mapping = rx1_cru_clock1_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock2_physical_mapping = rx1_cru_clock2_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock3_physical_mapping = rx1_cru_clock3_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock4_physical_mapping = rx1_cru_clock4_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock5_physical_mapping = rx1_cru_clock5_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock6_physical_mapping = rx1_cru_clock6_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock7_physical_mapping = rx1_cru_clock7_physical_mapping; 
            defparam mdio_reg_1.rx1_cru_clock8_physical_mapping = rx1_cru_clock8_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock0_physical_mapping = rx2_cru_clock0_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock1_physical_mapping = rx2_cru_clock1_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock2_physical_mapping = rx2_cru_clock2_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock3_physical_mapping = rx2_cru_clock3_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock4_physical_mapping = rx2_cru_clock4_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock5_physical_mapping = rx2_cru_clock5_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock6_physical_mapping = rx2_cru_clock6_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock7_physical_mapping = rx2_cru_clock7_physical_mapping; 
            defparam mdio_reg_1.rx2_cru_clock8_physical_mapping = rx2_cru_clock8_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock0_physical_mapping = rx3_cru_clock0_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock1_physical_mapping = rx3_cru_clock1_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock2_physical_mapping = rx3_cru_clock2_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock3_physical_mapping = rx3_cru_clock3_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock4_physical_mapping = rx3_cru_clock4_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock5_physical_mapping = rx3_cru_clock5_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock6_physical_mapping = rx3_cru_clock6_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock7_physical_mapping = rx3_cru_clock7_physical_mapping; 
            defparam mdio_reg_1.rx3_cru_clock8_physical_mapping = rx3_cru_clock8_physical_mapping; 
            
            defparam mdio_reg_1.tx0_pll_fast_clk0_physical_mapping = tx0_pll_fast_clk0_physical_mapping; 
            defparam mdio_reg_1.tx0_pll_fast_clk1_physical_mapping = tx0_pll_fast_clk1_physical_mapping; 
            defparam mdio_reg_1.tx1_pll_fast_clk0_physical_mapping = tx1_pll_fast_clk0_physical_mapping; 
            defparam mdio_reg_1.tx1_pll_fast_clk1_physical_mapping = tx1_pll_fast_clk1_physical_mapping; 
            defparam mdio_reg_1.tx2_pll_fast_clk0_physical_mapping = tx2_pll_fast_clk0_physical_mapping; 
            defparam mdio_reg_1.tx2_pll_fast_clk1_physical_mapping = tx2_pll_fast_clk1_physical_mapping; 
            defparam mdio_reg_1.tx3_pll_fast_clk0_physical_mapping = tx3_pll_fast_clk0_physical_mapping; 
            defparam mdio_reg_1.tx3_pll_fast_clk1_physical_mapping = tx3_pll_fast_clk1_physical_mapping; 

            // CMU_PLL reconfiguration
            defparam mdio_reg_1.pll0_phy = pll0_phy;
            defparam mdio_reg_1.pll1_phy = pll1_phy;
            defparam mdio_reg_1.pll2_phy = pll2_phy; 

            defparam mdio_reg_1.pll0_inclk0_logical_to_physical_mapping = pll0_inclk0_logical_to_physical_mapping;
            defparam mdio_reg_1.pll0_inclk1_logical_to_physical_mapping = pll0_inclk1_logical_to_physical_mapping;
            defparam mdio_reg_1.pll0_inclk2_logical_to_physical_mapping = pll0_inclk2_logical_to_physical_mapping;
            defparam mdio_reg_1.pll0_inclk3_logical_to_physical_mapping = pll0_inclk3_logical_to_physical_mapping;
            defparam mdio_reg_1.pll0_inclk4_logical_to_physical_mapping = pll0_inclk4_logical_to_physical_mapping;
            defparam mdio_reg_1.pll0_inclk5_logical_to_physical_mapping = pll0_inclk5_logical_to_physical_mapping;
            defparam mdio_reg_1.pll0_inclk6_logical_to_physical_mapping = pll0_inclk6_logical_to_physical_mapping;
            defparam mdio_reg_1.pll0_inclk7_logical_to_physical_mapping = pll0_inclk7_logical_to_physical_mapping;
            defparam mdio_reg_1.pll1_inclk0_logical_to_physical_mapping = pll1_inclk0_logical_to_physical_mapping;
            defparam mdio_reg_1.pll1_inclk1_logical_to_physical_mapping = pll1_inclk1_logical_to_physical_mapping;
            defparam mdio_reg_1.pll1_inclk2_logical_to_physical_mapping = pll1_inclk2_logical_to_physical_mapping;
            defparam mdio_reg_1.pll1_inclk3_logical_to_physical_mapping = pll1_inclk3_logical_to_physical_mapping;
            defparam mdio_reg_1.pll1_inclk4_logical_to_physical_mapping = pll1_inclk4_logical_to_physical_mapping;
            defparam mdio_reg_1.pll1_inclk5_logical_to_physical_mapping = pll1_inclk5_logical_to_physical_mapping;
            defparam mdio_reg_1.pll1_inclk6_logical_to_physical_mapping = pll1_inclk6_logical_to_physical_mapping;
            defparam mdio_reg_1.pll1_inclk7_logical_to_physical_mapping = pll1_inclk7_logical_to_physical_mapping;
            defparam mdio_reg_1.pll2_inclk0_logical_to_physical_mapping = pll2_inclk0_logical_to_physical_mapping;
            defparam mdio_reg_1.pll2_inclk1_logical_to_physical_mapping = pll2_inclk1_logical_to_physical_mapping;
            defparam mdio_reg_1.pll2_inclk2_logical_to_physical_mapping = pll2_inclk2_logical_to_physical_mapping;
            defparam mdio_reg_1.pll2_inclk3_logical_to_physical_mapping = pll2_inclk3_logical_to_physical_mapping;
            defparam mdio_reg_1.pll2_inclk4_logical_to_physical_mapping = pll2_inclk4_logical_to_physical_mapping;
            defparam mdio_reg_1.pll2_inclk5_logical_to_physical_mapping = pll2_inclk5_logical_to_physical_mapping;
            defparam mdio_reg_1.pll2_inclk6_logical_to_physical_mapping = pll2_inclk6_logical_to_physical_mapping;
            defparam mdio_reg_1.pll2_inclk7_logical_to_physical_mapping = pll2_inclk7_logical_to_physical_mapping;
            
            defparam mdio_reg_1.sim_dump_dprio_internal_reg_at_time = sim_dump_dprio_internal_reg_at_time;
            defparam mdio_reg_1.sim_dump_filename = sim_dump_filename;

                       
endmodule

`timescale 1 ps / 1 ps
module arriagx_hssi_central_management_unit (
	adet,
	cmudividerdprioin,
	cmuplldprioin,
	dpclk,
	dpriodisable,
	dprioin,
	dprioload,
	fixedclk,
	quadenable ,
	quadreset,
	rdalign,
	rdenablesync,
	recovclk,
	refclkdividerdprioin,
	rxanalogreset,
	rxclk,
	rxctrl,
	rxdatain,
	rxdatavalid,
	rxdigitalreset,
	rxdprioin,
	rxpowerdown,
	rxrunningdisp,
	syncstatus,
	txclk,
	txctrl,
	txdatain,
	txdigitalreset,
	txdprioin,

	alignstatus,
	clkdivpowerdn,
	cmudividerdprioout,
	cmuplldprioout,
	dpriodisableout,
	dpriooe,
	dprioout,
	enabledeskew,
	fiforesetrd,
	pllresetout,
	pllpowerdn,
	quadresetout,
	refclkdividerdprioout,
	rxadcepowerdn,
	rxadceresetout,
	rxanalogresetout,
	rxcruresetout,
	rxcrupowerdn,
	rxctrlout,
	rxdataout,
	rxdigitalresetout,
	rxdprioout,
	rxibpowerdn,
	txctrlout,
	txdataout,
	txdigitalresetout,
	txanalogresetout,
	txdetectrxpowerdn,
	txdividerpowerdn,
	txobpowerdn,
	txdprioout,

	digitaltestout
);

// LOCAL_PARAMETERS_BEGIN

parameter rx_dprio_width = 800;                     // 6.1
parameter tx_dprio_width = 400;                     // 6.1

// LOCAL_PARAMETERS_END

input [3:0]   adet;
input [29:0]  cmudividerdprioin;
input [119:0] cmuplldprioin;
input         dpclk;
input         dpriodisable;
input         dprioin;
input         dprioload;
input [3:0]   fixedclk;
input         quadenable ;
input         quadreset;
input [3:0]   rdalign;
input         rdenablesync;
input         recovclk;                           // recover clk from channl0
input [1:0]   refclkdividerdprioin;
input [3:0]   rxanalogreset;
input         rxclk;                              // clk_2 in RX
input [3:0]   rxctrl;
input [31:0]  rxdatain;
input [3:0]   rxdatavalid;
input [3:0]   rxdigitalreset;
input [rx_dprio_width - 1 : 0] rxdprioin;        
input [3:0]   rxpowerdown;
input [3:0]   rxrunningdisp;
input [3:0]   syncstatus;
input         txclk;                              // refclk (mostly pclk from CMU_DIV) in TX
input [3:0]   txctrl;
input [31:0]  txdatain;
input [3:0]   txdigitalreset;
input [tx_dprio_width - 1 : 0] txdprioin;

output         alignstatus;
output         clkdivpowerdn;
output [29:0]  cmudividerdprioout;
output [119:0] cmuplldprioout;
output         dpriodisableout;
output         dpriooe;
output         dprioout;
output         enabledeskew;
output         fiforesetrd;
output [2:0]   pllpowerdn;
output [2:0]   pllresetout;
output         quadresetout;
output [1:0]   refclkdividerdprioout;
output [3:0]   rxadcepowerdn;
output [3:0]   rxadceresetout;
output [3:0]   rxanalogresetout;
output [3:0]   rxcrupowerdn;
output [3:0]   rxcruresetout;
output [3:0]   rxctrlout;
output [31:0]  rxdataout;
output [3:0]   rxdigitalresetout;
output [rx_dprio_width - 1 : 0] rxdprioout;            // 1200
output [3:0]   rxibpowerdn;
output [3:0]   txanalogresetout;
output [3:0]   txctrlout;
output [31:0]  txdataout;
output [3:0]   txdetectrxpowerdn;
output [3:0]   txdigitalresetout;
output [3:0]   txdividerpowerdn;
output [tx_dprio_width - 1 : 0] txdprioout;           // 600
output [3:0]   txobpowerdn;

output [9:0]   digitaltestout;                  // TEST ports

parameter in_xaui_mode = "false";                            // true

parameter portaddr = 1;                                      // 1 - based
parameter devaddr = 1;                                       // 1 - based

parameter bonded_quad_mode = "none";                // driver/receiver
parameter use_deskew_fifo = "false";                         // true
parameter num_con_errors_for_align_loss = 2;                 
parameter num_con_good_data_for_align_approach = 3;
parameter num_con_align_chars_for_align =  4;
parameter offset_all_errors_align = "false";
parameter lpm_type = "arriagx_hssi_central_management_unit";
parameter dprio_config_mode = 0;                    // 6.1


// Simulation-only parameters (DPRIO)
parameter rx0_cru_clock0_physical_mapping = "refclk0"; 
parameter rx0_cru_clock1_physical_mapping = "refclk1"; 
parameter rx0_cru_clock2_physical_mapping = "iq0"; 
parameter rx0_cru_clock3_physical_mapping = "iq1"; 
parameter rx0_cru_clock4_physical_mapping = "iq2"; 
parameter rx0_cru_clock5_physical_mapping = "iq3"; 
parameter rx0_cru_clock6_physical_mapping = "iq4"; 
parameter rx0_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx0_cru_clock8_physical_mapping = "cmu_div_clk"; // not used
parameter rx1_cru_clock0_physical_mapping = "refclk0"; 
parameter rx1_cru_clock1_physical_mapping = "refclk1"; 
parameter rx1_cru_clock2_physical_mapping = "iq0"; 
parameter rx1_cru_clock3_physical_mapping = "iq1"; 
parameter rx1_cru_clock4_physical_mapping = "iq2"; 
parameter rx1_cru_clock5_physical_mapping = "iq3"; 
parameter rx1_cru_clock6_physical_mapping = "iq4"; 
parameter rx1_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx1_cru_clock8_physical_mapping = "cmu_div_clk";
parameter rx2_cru_clock0_physical_mapping = "refclk0"; 
parameter rx2_cru_clock1_physical_mapping = "refclk1"; 
parameter rx2_cru_clock2_physical_mapping = "iq0"; 
parameter rx2_cru_clock3_physical_mapping = "iq1"; 
parameter rx2_cru_clock4_physical_mapping = "iq2"; 
parameter rx2_cru_clock5_physical_mapping = "iq3"; 
parameter rx2_cru_clock6_physical_mapping = "iq4"; 
parameter rx2_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx2_cru_clock8_physical_mapping = "cmu_div_clk";
parameter rx3_cru_clock0_physical_mapping = "refclk0"; 
parameter rx3_cru_clock1_physical_mapping = "refclk1"; 
parameter rx3_cru_clock2_physical_mapping = "iq0"; 
parameter rx3_cru_clock3_physical_mapping = "iq1"; 
parameter rx3_cru_clock4_physical_mapping = "iq2"; 
parameter rx3_cru_clock5_physical_mapping = "iq3"; 
parameter rx3_cru_clock6_physical_mapping = "iq4"; 
parameter rx3_cru_clock7_physical_mapping = "pld_cru_clk"; 
parameter rx3_cru_clock8_physical_mapping = "cmu_div_clk";

parameter tx0_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx0_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx1_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx1_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx2_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx2_pll_fast_clk1_physical_mapping = "pll1"; 
parameter tx3_pll_fast_clk0_physical_mapping = "pll0"; 
parameter tx3_pll_fast_clk1_physical_mapping = "pll1"; 

parameter pll0_inclk0_logical_to_physical_mapping = "iq0";
parameter pll0_inclk1_logical_to_physical_mapping = "iq1";
parameter pll0_inclk2_logical_to_physical_mapping = "iq2";
parameter pll0_inclk3_logical_to_physical_mapping = "iq3";
parameter pll0_inclk4_logical_to_physical_mapping = "iq4";
parameter pll0_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll0_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll0_inclk7_logical_to_physical_mapping = "clkrefclk1";
parameter pll1_inclk0_logical_to_physical_mapping = "iq0";
parameter pll1_inclk1_logical_to_physical_mapping = "iq1";
parameter pll1_inclk2_logical_to_physical_mapping = "iq2";
parameter pll1_inclk3_logical_to_physical_mapping = "iq3";
parameter pll1_inclk4_logical_to_physical_mapping = "iq4";
parameter pll1_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll1_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll1_inclk7_logical_to_physical_mapping = "clkrefclk1";
parameter pll2_inclk0_logical_to_physical_mapping = "iq0";
parameter pll2_inclk1_logical_to_physical_mapping = "iq1";
parameter pll2_inclk2_logical_to_physical_mapping = "iq2";
parameter pll2_inclk3_logical_to_physical_mapping = "iq3";
parameter pll2_inclk4_logical_to_physical_mapping = "iq4";
parameter pll2_inclk5_logical_to_physical_mapping = "pld_clk";
parameter pll2_inclk6_logical_to_physical_mapping = "clkrefclk0";
parameter pll2_inclk7_logical_to_physical_mapping = "clkrefclk1";

parameter cmu_divider_inclk0_physical_mapping = "pll0";
parameter cmu_divider_inclk1_physical_mapping = "pll1";
parameter cmu_divider_inclk2_physical_mapping = "pll2";

parameter rx0_logical_to_physical_mapping = 0;
parameter rx1_logical_to_physical_mapping = 1;
parameter rx2_logical_to_physical_mapping = 2;
parameter rx3_logical_to_physical_mapping = 3;

parameter tx0_logical_to_physical_mapping = 0;
parameter tx1_logical_to_physical_mapping = 1;
parameter tx2_logical_to_physical_mapping = 2;
parameter tx3_logical_to_physical_mapping = 3;

parameter pll0_logical_to_physical_mapping = 0;
parameter pll1_logical_to_physical_mapping = 1;
parameter pll2_logical_to_physical_mapping = 2;  // -1 means not used

parameter refclk_divider0_logical_to_physical_mapping = 0;
parameter refclk_divider1_logical_to_physical_mapping = 1; // -1 means not used

// PE-only
parameter analog_test_bus_enable = "false";
parameter bypass_bandgap = "true";
parameter central_test_bus_select = 5;

// DEBUG dump
parameter sim_dump_dprio_internal_reg_at_time = 0;  // in ps
parameter sim_dump_filename = "sim_dprio_dump.txt"; // over-write when multiple CMUs

///////////////////////////////////////////////////////////////////////////
// quad_reset ---------------------------------------------------------- //
///////////////////////////////////////////////////////////////////////////

wire       enpll;                              // input
wire       pllurst;
wire [3:0] rxurstpcs;
wire [3:0] txurstpcs;
wire [3:0] rxurstpma;
wire [3:0] urx_pdb;


wire       hard_reset;                         // output
wire [3:0] rxpma_rstb;
wire [3:0] txpma_rstb;
wire [3:0] rxpcs_rst;
wire [3:0] txpcs_rst;
// wire [3:0] pipe_rstb;            // commented out at pip_interface_top connect
wire [3:0] cru_rstb;                // = rxpma_rstb + rrx_cru_rst
wire [3:0] adce_rstb;               // = rxpma_rstb + radce_rst
wire [2:0] cmu_txpll_rstb;          // = hard_reset + rcmu_txpll_rst + rpowerdn

wire [3:0] tx_pdb;                  // implemented as active High when used as input
wire [3:0] rx_pdb;                  // rxuserpowder + hardreset
wire [3:0] cru_pdb;                 // same as hard_reset
wire [3:0] adce_pdb;             
wire [3:0] cgb_pdb;                 // tx_channel_clk_div
wire [2:0] cmu_txpll_pdb;
wire [3:0] rx_det_pdb;   // to tx (rx_detect) tied with power state inputs: p0_state etc

// inter wires - filtering X's
wire [3:0] rxpcsrst_hssi;
wire [3:0] txpcsrst_hssi;
wire [3:0] rxpmarst_hssi;
wire [3:0] pipe_rst_hssi;
wire [3:0] rx_pd_hssi;

// optimization 
reg        init_in_xaui_mode;

/////////////////////////////////////////////////////////////////////////////////
// TIMING - INPUT BUFFERS  ----------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire       dpclk_in;
wire       dpriodisable_in;
wire       dprioin_in;
wire       dprioload_in;
wire [3:0] fixedclk_in;
wire       quadenable_in;
wire       quadreset_in;
wire [3:0] rxanalogreset_in;
wire       rxclk_in;                            
wire [3:0] rxdigitalreset_in;
wire [3:0] rxpowerdown_in;
wire       txclk_in;    
wire [3:0] txdigitalreset_in;

buf buf_dpclk                 (dpclk_in,           dpclk);
buf buf_dpriodisable          (dpriodisable_in,    dpriodisable);
buf buf_dprioin               (dprioin_in,         dprioin);
buf buf_dprioload             (dprioload_in,       dprioload);
buf buf_fixedclk       [3:0]  (fixedclk_in,        fixedclk);
buf buf_quadenable            (quadenable_in,      quadenable );
buf buf_quadreset             (quadreset_in,       quadreset);
buf buf_rxanalogreset  [3:0]  (rxanalogreset_in,   rxanalogreset);
buf buf_rxclk                 (rxclk_in,           rxclk);                            
buf buf_rxdigitalreset [3:0]  (rxdigitalreset_in,  rxdigitalreset);
buf buf_rxpowerdown    [3:0]  (rxpowerdown_in,     rxpowerdown);
buf buf_txclk                 (txclk_in,           txclk);    
buf buf_txdigitalreset [3:0]  (txdigitalreset_in,  txdigitalreset);

/////////////////////////////////////////////////////////////////////////////////
// TIMING -- TCO/TSU/HOLD                                                      //
/////////////////////////////////////////////////////////////////////////////////
wire dprioout_tim;
wire dpriooe_tim;

specify

    $setuphold(posedge dpclk, dprioin,     0, 0);

    (posedge dpclk => (dprioout  +: dprioout_tim)) = (0, 0);
    (posedge dpclk => (dpriooe   +: dpriooe_tim))  = (0, 0);

endspecify

buf (dprioout, dprioout_tim);
buf (dpriooe,  dpriooe_tim);

/////////////////////////////////////////////////////////////////////////////////
// hook up inputs
/////////////////////////////////////////////////////////////////////////////////

assign enpll     = (quadenable_in === 1'b0) ? 1'b0 : 1'b1;
assign pllurst   = (quadreset_in === 1'b1) ? 1'b1 : 1'b0;
assign rxurstpcs = rxdigitalreset_in;
assign txurstpcs = txdigitalreset_in;
assign rxurstpma = rxanalogreset_in;
assign urx_pdb   = rxpowerdown_in;     // assume rxpowderdown Active High

assign hard_reset = (enpll === 1'b0 || pllurst === 1'b1) ? 1'b1 : 1'b0;  // ~enpll || pllurst;

// pcs reset
assign rxpcsrst_hssi[0] = rxurstpcs[0] === 1'b1 ? 1'b1 : 1'b0;  
assign rxpcsrst_hssi[1] = rxurstpcs[1] === 1'b1 ? 1'b1 : 1'b0;  
assign rxpcsrst_hssi[2] = rxurstpcs[2] === 1'b1 ? 1'b1 : 1'b0;  
assign rxpcsrst_hssi[3] = rxurstpcs[3] === 1'b1 ? 1'b1 : 1'b0;  
assign txpcsrst_hssi[0] = txurstpcs[0] === 1'b1 ? 1'b1 : 1'b0;  
assign txpcsrst_hssi[1] = txurstpcs[1] === 1'b1 ? 1'b1 : 1'b0;  
assign txpcsrst_hssi[2] = txurstpcs[2] === 1'b1 ? 1'b1 : 1'b0;  
assign txpcsrst_hssi[3] = txurstpcs[3] === 1'b1 ? 1'b1 : 1'b0;  

assign rxpcs_rst = rxpcsrst_hssi | {hard_reset,hard_reset,hard_reset,hard_reset};
assign txpcs_rst = txpcsrst_hssi | {hard_reset,hard_reset,hard_reset,hard_reset};

// pma reset
assign rxpmarst_hssi[0] = rxurstpma[0] === 1'b1 ? 1'b1 : 1'b0;  
assign rxpmarst_hssi[1] = rxurstpma[1] === 1'b1 ? 1'b1 : 1'b0;  
assign rxpmarst_hssi[2] = rxurstpma[2] === 1'b1 ? 1'b1 : 1'b0;  
assign rxpmarst_hssi[3] = rxurstpma[3] === 1'b1 ? 1'b1 : 1'b0;  

assign rxpma_rstb = ~(rxpmarst_hssi | {hard_reset,hard_reset,hard_reset,hard_reset});
assign txpma_rstb = ~({hard_reset,hard_reset,hard_reset,hard_reset});

// rx CRU and ADCE reset
assign cru_rstb  = rxpma_rstb;
assign adce_rstb = rxpma_rstb;

// cmu PLL reset
assign cmu_txpll_rstb = ~({hard_reset,hard_reset,hard_reset});

// pipe reset - commented out in pip_interface_top
// assign pipe_rst_hssi = (txpcs_rst &  rxpcs_rst & ~(rxpma_rstb));
// assign pipe_rstb = ~(pipe_rst_hssi | {hard_reset,hard_reset,hard_reset,hard_reset});

// power down
// assign rx_pd_hssi = ~(urx_pdb | ~(rurx_pdb)) | ~(rrx_ib_pdb) | rpowdnr | {rpowerdown,rpowerdown,rpowerdown,rpowerdown};
assign rx_pd_hssi[0] = (urx_pdb[0] === 1'b1) ? 1'b1 : 1'b0;
assign rx_pd_hssi[1] = (urx_pdb[1] === 1'b1) ? 1'b1 : 1'b0;
assign rx_pd_hssi[2] = (urx_pdb[2] === 1'b1) ? 1'b1 : 1'b0;
assign rx_pd_hssi[3] = (urx_pdb[3] === 1'b1) ? 1'b1 : 1'b0;
assign rx_pdb        = rx_pd_hssi | {hard_reset,hard_reset,hard_reset,hard_reset};
assign tx_pdb        = {hard_reset,hard_reset,hard_reset,hard_reset};
assign cru_pdb       = {hard_reset,hard_reset,hard_reset,hard_reset};
assign adce_pdb      = {hard_reset,hard_reset,hard_reset,hard_reset};
assign cgb_pdb       = {hard_reset,hard_reset,hard_reset,hard_reset};
assign rx_det_pdb    = {hard_reset,hard_reset,hard_reset,hard_reset};
assign cmu_txpll_pdb = {hard_reset,hard_reset,hard_reset};

///////////////////////////////////////////////////////////////////////////
// centrl_clk_ctl ------------------------------------------------------ //
///////////////////////////////////////////////////////////////////////////

wire refclk_pma_out;                           // output - Global TX PCS clock
wire mdc_b;                                    // MD Clock
assign refclk_pma_out = txclk_in;                 // txclk <= pclk/digitalrefclkout
assign mdc_b = dpclk_in;

// txclk_sel_centrl -----------------------------------------------------------
wire refclk_b;                                 // output to centrl_reset and TX_SM
assign refclk_b = refclk_pma_out;

// rxclk_sel_centrl ------------------------------------------------------------
wire clk_1_b;                        // output - feeding to Deskew SM only
wire clk_2_b;                        // output - to RCV_SM, centrl_reset
assign clk_1_b = recovclk;           // from ch0 of recover_clk
assign clk_2_b = rxclk_in;              // same as clk_2 in RX - masterclk in XAUI

// centrl_reset -------------------------------------------------------------------
wire rxrst_int;                      // to DSKW,RCV_SM, div2 on rxclk_sel (ignore)
wire txrst_int;

reg  txrst_sync1, txrst_sync2;
reg  rxrst_sync1, rxrst_sync2;

always @(posedge hard_reset or posedge clk_2_b)
begin
    if (hard_reset === 1'b1)
       begin
        rxrst_sync2	<= 1'b1;
        rxrst_sync1 	<= 1'b1;
       end
    else
       begin
         rxrst_sync2	<= #1 rxrst_sync1;
         rxrst_sync1	<= rxpcs_rst;
       end
end

always @(posedge hard_reset or posedge refclk_b)
begin
    if (hard_reset === 1'b1)
        begin
         txrst_sync2	<= 1'b1;
         txrst_sync1 	<= 1'b1;
        end
    else
        begin
         txrst_sync2	<= #1 txrst_sync1;
         txrst_sync1	<= txpcs_rst;
        end
end

assign txrst_int = txrst_sync2;
assign rxrst_int = rxrst_sync2;

///////////////////////////////////////////////////////////////////////////
// optimization  --------------------------------------------------------//
///////////////////////////////////////////////////////////////////////////

initial begin
    init_in_xaui_mode = (in_xaui_mode == "true" || use_deskew_fifo == "true") ? 1'b1 : 1'b0;
end
///////////////////////////////////////////////////////////////////////////
// instantiate DSKW SM ------------------------------------------------- //
///////////////////////////////////////////////////////////////////////////

wire [3:0] dskw_curr_st;
wire       alignstatus_int;            // feeding to PLD and DPRIO

wire       dskw_sm_clk;
assign dskw_sm_clk = (init_in_xaui_mode === 1'b1) ? clk_1_b : 1'b0;

arriagx_hssi_dskw_sm dskw_sm_1  ( .soft_reset     (rxrst_int),
                     //.clk_1        (clk_1_b),
                     .clk_1          (dskw_sm_clk),
		             .octal_mode     (1'b0),
                     .align_det_sync ({4'b1111, adet}),
                     .rd_align       ({4'b1111, rdalign}),
                     .sync_status    ({4'b1111,syncstatus}),
                     .align_status   (alignstatus_int),
                     .enable_deskew  (enabledeskew),
                     .fifo_reset_rd  (fiforesetrd),
		             .curr_state     (dskw_curr_st)
                   );

///////////////////////////////////////////////////////////////////////////
// instantiate TX SM --------------------------------------------------- //
///////////////////////////////////////////////////////////////////////////

wire       rtx_rx_local_fault_clr_int;          // from DPRIO
wire       rindv_tx_int;

wire [3:0] tx_curr_st;
wire       tx_local_fault_det;               // output to rx_sm
wire       tx_local_fault_int;               // feeding nowhere

wire       tx_sm_clk;
wire [31:0] tx_sm_datain;
wire [3:0] tx_sm_ctrlin;
wire       tx_sm_rdenablesyncin;

assign tx_sm_clk            = (init_in_xaui_mode === 1'b1) ? refclk_b : 1'b0;
assign tx_sm_datain         = (init_in_xaui_mode === 1'b1) ? txdatain : 'b0;
assign tx_sm_ctrlin         = (init_in_xaui_mode === 1'b1) ? txctrl : 'b0;
assign tx_sm_rdenablesyncin = (init_in_xaui_mode === 1'b1) ? rdenablesync : 1'b0;


assign rtx_rx_local_fault_clr_int = 1'b0;
assign rindv_tx_int = 1'b0;                 // tx sm just sends K when set

arriagx_hssi_tx_sm      tx_sm_1 ( .tx_clk             (tx_sm_clk),
                     //.tx_clk             (refclk_b),
                     .soft_reset         (txrst_int),
                     .indv               (rindv_tx_int),
                     .tx_data            (tx_sm_datain),
                     //.tx_data            (txdatain),
                     .tx_ctl             (tx_sm_ctrlin),
                     //.tx_ctl             (txctrl),
                     .rd_enable_sync     (tx_sm_rdenablesyncin), 
                     //.rd_enable_sync     (rdenablesync), 
                     .tx_local_fault_clr (rtx_rx_local_fault_clr_int), //shared with tx_sm
                     .sm_data            (txdataout),
                     .sm_ctl             (txctrlout),
                     .tx_local_fault_det (tx_local_fault_det), // to rcv_sm
                     .tx_local_fault     (tx_local_fault_int),
                     .curr_state         (tx_curr_st)
                    );

///////////////////////////////////////////////////////////////////////////
// instantiate RX SM --------------------------------------------------- //
///////////////////////////////////////////////////////////////////////////

wire rindv_rx_int;                 // from DPRIO
wire rxs_link_status_set_int;      // from DPRIO
wire xs_link_status_int;

wire rx_local_fault_int;           // feeding DPRIO
wire xlink_status_int;             // feeding DPRIO
wire [1:0] rcv_curr_st;

wire       rcv_sm_clk;
wire [3:0] rcv_sm_decdatavalid;
wire [31:0] rcv_sm_decdata;
wire [3:0] rcv_sm_decctl;
wire [3:0] rcv_sm_rxrunningdisp;

assign rcv_sm_clk           = (init_in_xaui_mode === 1'b1) ? clk_2_b       : 1'b0;
assign rcv_sm_decdatavalid  = (init_in_xaui_mode === 1'b1) ? rxdatavalid   :  'b1;
assign rcv_sm_decdata       = (init_in_xaui_mode === 1'b1) ? rxdatain      :  'b0;
assign rcv_sm_decctl        = (init_in_xaui_mode === 1'b1) ? rxctrl        :  'b0;
assign rcv_sm_rxrunningdisp = (init_in_xaui_mode === 1'b1) ? rxrunningdisp :  'b0;

assign rindv_rx_int = 1'b0;
assign rxs_link_status_set_int = 1'b0;

arriagx_hssi_rcv_sm     rcv_sm_1 (
                     .clk_2               (rcv_sm_clk),
                     //.clk_2             (clk_2_b),
                     .soft_reset          (rxrst_int),
                     .indv                (rindv_rx_int),
                     .dec_data_valid      (rcv_sm_decdatavalid),
                     //.dec_data_valid      (rxdatavalid),
                     .dec_data            (rcv_sm_decdata),
                     //.dec_data            (rxdatain),
                     .dec_ctl             (rcv_sm_decctl),
                     //.dec_ctl             (rxctrl),
                     .running_disp        (rcv_sm_rxrunningdisp),
                     //.running_disp        (rxrunningdisp),
                     .rx_local_fault_clr  (rtx_rx_local_fault_clr_int), //shared with tx_sm
                     .xs_link_status_set  (rxs_link_status_set_int),
                     .tx_local_fault_det  (tx_local_fault_det),   // from tx_sm
                     .rx_data_rs          (rxdataout),
                     .rx_ctl_rs           (rxctrlout),
                     .rx_local_fault      (rx_local_fault_int),
                     .xs_link_status      (xs_link_status_int),
       	             .curr_state          (rcv_curr_st)
                    );

///////////////////////////////////////////////////////////////////////////
// instantiate DPRIO_CONTROL_TOP --------------------------------------- //
///////////////////////////////////////////////////////////////////////////

wire [4:0]   port_addr;        // convert from top parameter
wire [4:0]   dev_addr;         // convert from top parameter
wire         mdio_rst;
wire [29:0]  cmudprioin;      //local wrt cmu
wire [29:0]  cmudprioout;     //local wrt cmu
wire [2:0]   mdio_curr_st;
wire         mdio_in;

reg          mdio_rst_reg;

assign port_addr = portaddr-1;     // int (1-based into 0-based) to 5'b conversion
assign dev_addr = devaddr-1;       // int (1-based into 0-based)to 5'b conversion

assign #1 mdio_in = dprioin_in;
assign mdio_rst = mdio_rst_reg;    // ~(plniotri & ~entest & npor);
initial begin
    mdio_rst_reg = 1'b1;
    #1000 mdio_rst_reg = 1'b0; 
end

assign cmudprioin = 'bx;

arriagx_hssi_cmu_dprio_top  control_top_0 (
                  .cmudividerdprioin(cmudividerdprioin),
                  .cmuplldprioin    (cmuplldprioin),
                  .cmudprioin       (cmudprioin),          //local wrt cmu
                  .refclkdividerdprioin(refclkdividerdprioin),
                  .rxdprioin        (rxdprioin),
                  .txdprioin        (txdprioin),
                  .cmudividerdprioout(cmudividerdprioout),
                  .cmuplldprioout    (cmuplldprioout),
                  .cmudprioout       (cmudprioout),          //local wrt cmu
                  .refclkdividerdprioout(refclkdividerdprioout),
                  .rxdprioout        (rxdprioout),
                  .txdprioout        (txdprioout),
                  .sync_status      (syncstatus),          // from top
                  .align_status     (alignstatus_int),     // from dskw_sm
                  .dprioload        (dprioload_in),           // from top
                  .mdio_in          (mdio_in),             // delayed from top               
                  .mdc              (dpclk_in),               // from top                   
                  .port_addr        (port_addr),           // from top para
                  .dev_addr         (dev_addr),            // from top para
                  .mdio_dis         (dpriodisable_in),        // from top
                  .mdio_rst         (mdio_rst),            // not user control
                  .mdio_out         (dprioout_tim),        // to top          
                  .data_enable_n    (dpriooe_tim),         // to top (L)
                  .mdio_curr_st     (mdio_curr_st)         // to local observe
				 );
defparam control_top_0.rx0_phy = rx0_logical_to_physical_mapping;
defparam control_top_0.rx1_phy = rx1_logical_to_physical_mapping;
defparam control_top_0.rx2_phy = rx2_logical_to_physical_mapping;
defparam control_top_0.rx3_phy = rx3_logical_to_physical_mapping;
defparam control_top_0.tx0_phy = tx0_logical_to_physical_mapping;
defparam control_top_0.tx1_phy = tx1_logical_to_physical_mapping;
defparam control_top_0.tx2_phy = tx2_logical_to_physical_mapping;
defparam control_top_0.tx3_phy = tx3_logical_to_physical_mapping;

defparam control_top_0.rx_dprio_width = rx_dprio_width;
defparam control_top_0.tx_dprio_width = tx_dprio_width;

defparam control_top_0.rx0_cru_clock0_physical_mapping = rx0_cru_clock0_physical_mapping; 
defparam control_top_0.rx0_cru_clock1_physical_mapping = rx0_cru_clock1_physical_mapping; 
defparam control_top_0.rx0_cru_clock2_physical_mapping = rx0_cru_clock2_physical_mapping; 
defparam control_top_0.rx0_cru_clock3_physical_mapping = rx0_cru_clock3_physical_mapping; 
defparam control_top_0.rx0_cru_clock4_physical_mapping = rx0_cru_clock4_physical_mapping; 
defparam control_top_0.rx0_cru_clock5_physical_mapping = rx0_cru_clock5_physical_mapping; 
defparam control_top_0.rx0_cru_clock6_physical_mapping = rx0_cru_clock6_physical_mapping; 
defparam control_top_0.rx0_cru_clock7_physical_mapping = rx0_cru_clock7_physical_mapping; 
defparam control_top_0.rx0_cru_clock8_physical_mapping = rx0_cru_clock8_physical_mapping; 
defparam control_top_0.rx1_cru_clock0_physical_mapping = rx1_cru_clock0_physical_mapping; 
defparam control_top_0.rx1_cru_clock1_physical_mapping = rx1_cru_clock1_physical_mapping; 
defparam control_top_0.rx1_cru_clock2_physical_mapping = rx1_cru_clock2_physical_mapping; 
defparam control_top_0.rx1_cru_clock3_physical_mapping = rx1_cru_clock3_physical_mapping; 
defparam control_top_0.rx1_cru_clock4_physical_mapping = rx1_cru_clock4_physical_mapping; 
defparam control_top_0.rx1_cru_clock5_physical_mapping = rx1_cru_clock5_physical_mapping; 
defparam control_top_0.rx1_cru_clock6_physical_mapping = rx1_cru_clock6_physical_mapping; 
defparam control_top_0.rx1_cru_clock7_physical_mapping = rx1_cru_clock7_physical_mapping; 
defparam control_top_0.rx1_cru_clock8_physical_mapping = rx1_cru_clock8_physical_mapping; 
defparam control_top_0.rx2_cru_clock0_physical_mapping = rx2_cru_clock0_physical_mapping; 
defparam control_top_0.rx2_cru_clock1_physical_mapping = rx2_cru_clock1_physical_mapping; 
defparam control_top_0.rx2_cru_clock2_physical_mapping = rx2_cru_clock2_physical_mapping; 
defparam control_top_0.rx2_cru_clock3_physical_mapping = rx2_cru_clock3_physical_mapping; 
defparam control_top_0.rx2_cru_clock4_physical_mapping = rx2_cru_clock4_physical_mapping; 
defparam control_top_0.rx2_cru_clock5_physical_mapping = rx2_cru_clock5_physical_mapping; 
defparam control_top_0.rx2_cru_clock6_physical_mapping = rx2_cru_clock6_physical_mapping; 
defparam control_top_0.rx2_cru_clock7_physical_mapping = rx2_cru_clock7_physical_mapping; 
defparam control_top_0.rx2_cru_clock8_physical_mapping = rx2_cru_clock8_physical_mapping; 
defparam control_top_0.rx3_cru_clock0_physical_mapping = rx3_cru_clock0_physical_mapping; 
defparam control_top_0.rx3_cru_clock1_physical_mapping = rx3_cru_clock1_physical_mapping; 
defparam control_top_0.rx3_cru_clock2_physical_mapping = rx3_cru_clock2_physical_mapping; 
defparam control_top_0.rx3_cru_clock3_physical_mapping = rx3_cru_clock3_physical_mapping; 
defparam control_top_0.rx3_cru_clock4_physical_mapping = rx3_cru_clock4_physical_mapping; 
defparam control_top_0.rx3_cru_clock5_physical_mapping = rx3_cru_clock5_physical_mapping; 
defparam control_top_0.rx3_cru_clock6_physical_mapping = rx3_cru_clock6_physical_mapping; 
defparam control_top_0.rx3_cru_clock7_physical_mapping = rx3_cru_clock7_physical_mapping; 
defparam control_top_0.rx3_cru_clock8_physical_mapping = rx3_cru_clock8_physical_mapping; 

defparam control_top_0.tx0_pll_fast_clk0_physical_mapping = tx0_pll_fast_clk0_physical_mapping; 
defparam control_top_0.tx0_pll_fast_clk1_physical_mapping = tx0_pll_fast_clk1_physical_mapping; 
defparam control_top_0.tx1_pll_fast_clk0_physical_mapping = tx1_pll_fast_clk0_physical_mapping; 
defparam control_top_0.tx1_pll_fast_clk1_physical_mapping = tx1_pll_fast_clk1_physical_mapping; 
defparam control_top_0.tx2_pll_fast_clk0_physical_mapping = tx2_pll_fast_clk0_physical_mapping; 
defparam control_top_0.tx2_pll_fast_clk1_physical_mapping = tx2_pll_fast_clk1_physical_mapping; 
defparam control_top_0.tx3_pll_fast_clk0_physical_mapping = tx3_pll_fast_clk0_physical_mapping; 
defparam control_top_0.tx3_pll_fast_clk1_physical_mapping = tx3_pll_fast_clk1_physical_mapping; 

// CMU_PLL reconfiguration
defparam control_top_0.pll0_phy = pll0_logical_to_physical_mapping;
defparam control_top_0.pll1_phy = pll1_logical_to_physical_mapping;
defparam control_top_0.pll2_phy = pll2_logical_to_physical_mapping; 

defparam control_top_0.pll0_inclk0_logical_to_physical_mapping = pll0_inclk0_logical_to_physical_mapping;
defparam control_top_0.pll0_inclk1_logical_to_physical_mapping = pll0_inclk1_logical_to_physical_mapping;
defparam control_top_0.pll0_inclk2_logical_to_physical_mapping = pll0_inclk2_logical_to_physical_mapping;
defparam control_top_0.pll0_inclk3_logical_to_physical_mapping = pll0_inclk3_logical_to_physical_mapping;
defparam control_top_0.pll0_inclk4_logical_to_physical_mapping = pll0_inclk4_logical_to_physical_mapping;
defparam control_top_0.pll0_inclk5_logical_to_physical_mapping = pll0_inclk5_logical_to_physical_mapping;
defparam control_top_0.pll0_inclk6_logical_to_physical_mapping = pll0_inclk6_logical_to_physical_mapping;
defparam control_top_0.pll0_inclk7_logical_to_physical_mapping = pll0_inclk7_logical_to_physical_mapping;
defparam control_top_0.pll1_inclk0_logical_to_physical_mapping = pll1_inclk0_logical_to_physical_mapping;
defparam control_top_0.pll1_inclk1_logical_to_physical_mapping = pll1_inclk1_logical_to_physical_mapping;
defparam control_top_0.pll1_inclk2_logical_to_physical_mapping = pll1_inclk2_logical_to_physical_mapping;
defparam control_top_0.pll1_inclk3_logical_to_physical_mapping = pll1_inclk3_logical_to_physical_mapping;
defparam control_top_0.pll1_inclk4_logical_to_physical_mapping = pll1_inclk4_logical_to_physical_mapping;
defparam control_top_0.pll1_inclk5_logical_to_physical_mapping = pll1_inclk5_logical_to_physical_mapping;
defparam control_top_0.pll1_inclk6_logical_to_physical_mapping = pll1_inclk6_logical_to_physical_mapping;
defparam control_top_0.pll1_inclk7_logical_to_physical_mapping = pll1_inclk7_logical_to_physical_mapping;
defparam control_top_0.pll2_inclk0_logical_to_physical_mapping = pll2_inclk0_logical_to_physical_mapping;
defparam control_top_0.pll2_inclk1_logical_to_physical_mapping = pll2_inclk1_logical_to_physical_mapping;
defparam control_top_0.pll2_inclk2_logical_to_physical_mapping = pll2_inclk2_logical_to_physical_mapping;
defparam control_top_0.pll2_inclk3_logical_to_physical_mapping = pll2_inclk3_logical_to_physical_mapping;
defparam control_top_0.pll2_inclk4_logical_to_physical_mapping = pll2_inclk4_logical_to_physical_mapping;
defparam control_top_0.pll2_inclk5_logical_to_physical_mapping = pll2_inclk5_logical_to_physical_mapping;
defparam control_top_0.pll2_inclk6_logical_to_physical_mapping = pll2_inclk6_logical_to_physical_mapping;
defparam control_top_0.pll2_inclk7_logical_to_physical_mapping = pll2_inclk7_logical_to_physical_mapping;

defparam control_top_0.sim_dump_dprio_internal_reg_at_time = sim_dump_dprio_internal_reg_at_time;
defparam control_top_0.sim_dump_filename = sim_dump_filename;

///////////////////////////////////////////////////////////////////////////
// establish outputs --------------------------------------------------- //
///////////////////////////////////////////////////////////////////////////

assign   alignstatus = alignstatus_int;   // from dskw_sm
//assign cmudividerdprioout = 'bx;  // connected in control_top
//assign cmuplldprioout = 'bx;      // connected in control_top
assign   dpriodisableout = dpriodisable_in;   // from top
//assign dpriooe = 1'b0;          // connected in control_top
//assign dprioout = 1'bx;         // connected in control_top
//assign enabledeskew;            // connected in sub module instantiation
//assign fiforesetrd              // connected in sub module instantiation
//assign refclkdividerdprioout = 'bx; // connected in control_top
//assign [3:0]   rxctrlout;       // connected in sub module instantiation
//assign [31:0]  rxdataout;       // connected in sub module instantiation
//assign rxdprioout = 'bx;          // connected in control_top
assign   digitaltestout = 'bx;       // 10 Test ports
//assign [3:0]   txctrlout;       // connected in sub module instantiation
//assign [31:0]  txdataout;       // connected in sub module instantiation
//assign txdprioout = 'bx;         // connected in control_top

// reset and powerdown - everything turns into Active High ---------------
assign pllresetout       = ~cmu_txpll_rstb;
assign quadresetout      = hard_reset;
assign rxadceresetout    = ~adce_rstb;
assign rxanalogresetout  = ~rxpma_rstb;
assign rxcruresetout     = ~cru_rstb;
assign rxdigitalresetout = rxpcs_rst;
assign txanalogresetout  = ~txpma_rstb;
assign txdigitalresetout = txpcs_rst;

// -------------------------- all in active H already --------------------

assign clkdivpowerdn     = 1'b0;           // no correspondent in RTL
assign pllpowerdn        = cmu_txpll_pdb;
assign rxadcepowerdn     = adce_pdb;
assign rxcrupowerdn      = cru_pdb;
assign rxibpowerdn       = rx_pdb;
assign txdetectrxpowerdn = rx_det_pdb;
assign txdividerpowerdn  = cgb_pdb;
assign txobpowerdn       = tx_pdb;

endmodule


/////////////////////////////////////////////////////////////////////////////////
// hssi_module: transmitter ***************************************************//
/////////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////
// DPRIO INDEX TABLE --------------------------------------------------------//
///////////////////////////////////////////////////////////////////////////////

// The address covers both rx(pma and dpma widths defined in RX) and tx
// pma_ctrl4_ch0_ext = {rpmadwidth_tx[0], rpma_doublewidth_tx[0], rtx_cmu_sel[0],
// 806Ch                rtx_m_sel_ch0, rtxvcobypass[0], rtx_cgb_1x_en[0], rtx_cgb_4x_en[0],
//                      rtx_4x_sw[0], rpmadwidth_rx[0], rpma_doublewidth_rx[0],
//                      rrxvcobypass[0],rrect_adj_ch0, rrx_piso_bypass_ch0};
`define rtx_cmu_sel_TX_IDX              9
`define rpmadwidth_tx_TX_IDX            10
`define rpma_doublewidth_tx_TX_IDX      11
`define rtx_m_sel_TX_IDX_0              12
`define rtx_m_sel_TX_IDX_1              13
`define rtx_cgb_1x_en_TX_IDX            14
`define rtx_cgb_4x_en_TX_IDX            15
`define rtx_4x_sw_TX_IDX                16


// tx - 3
//assign  trunking_mode_ext = {1'b0, rphfifo_master_sel_tx, rphfifo_master_sel_rx, 
// 8000h same for all ch       rendec_data_sel_tx, rendec_data_sel_rx, rnenbpin, rpllurst, 
//                             rreset, rrsvd_cmu, rdeskewen, rindv_tx, rindv_rx};
`define rphfifo_master_sel_tx_TX_IDX    20
`define rendec_data_sel_tx_TX_IDX       21
`define rindv_tx_TX_IDX                 22

// page divided into both rx and tx
// pcs_ctrl1_ch0_ext = {rtx_pipe_enable[0], rrx_pipe_enable[0], rpowdnr[0], rpowdnt[0],
// 8001-8004            rendec_tx[0], rendec_rx[0], r8b10b_enc_ibm_en[0], rmatchen[0],
//                      r8b10b_dec_ibm_en_ch0, rforce_kchar[0], rforce_echar[0],
//                      rlp20ben[0], rgenericfifo[0], rcascaded_8b10b_en_tx[0],
//                      rcascaded_8b10b_en_rx[0]};
`define rtx_pipe_enable_TX_IDX          25
`define rpowdnt_TX_IDX                  26
`define rendec_tx_TX_IDX                27
`define r8b10b_enc_ibm_en_TX_IDX        28
`define rforce_kchar_TX_IDX             29
`define rforce_echar_TX_IDX             30
`define rcascaded_8b10b_en_tx_TX_IDX    31

// tx - 3
//assign  pcs_ctrl5_ch0_ext = {rrxfifo_dis[0], rtxfifo_dis[0], rib_force_disp[0],
//8011-8014                  rrundisp_ch0, rtxfifo_lowlatency_en[0], rrlv_en[0], rautobtalg_dis[0],
//                           rsync_sm_dis[0], rib_inv_cd_ch0, rrxfifo_lowlatency_en[0]};
`define rtxfifo_dis_TX_IDX              34
`define rib_force_disp_TX_IDX           35
`define rtxfifo_lowlatency_en_TX_IDX    36

//assign  pcs_ctrl6_ch0_ext = {rdwidth_tx[0], rdwidth_rx[0], rge_xaui_tx[0],
// 8015 - 8018                 rrx_detect_bypass[0], rtxurstpcs[0], rrxurstpcs[0],
//                             rrsvd_tx_ch0, rskpsetbased[0], rtruebac2bac[0],rrsvd_rx_ch0};
//
`define rdwidth_tx_TX_IDX               37
`define rge_xaui_tx_TX_IDX              38
`define rtxurstpcs_TX_IDX               39
`define rrsvd_tx_TX_IDX_0               40
`define rrsvd_tx_TX_IDX_4               44

// page 7 PCS - all rx

// page 8 of rx moved to first as POF used rclk_2 long ago
//assign  pcs_ctrl8_ch0_ext = {rfreerun_tx[0], rtxwrclksel[0], rtxrdclksel[0],
//801d-8020                  rfreerun_rx[0], rrcvd_clk_sel_ch0, 
//                           rclk_1_sel_ch0, rclk_2_sel_ch0, rrx_rd_clk_sel[0], 
//                           renumber_ch0, renpolinv_rx[0], rclkcmpinsertpad[0]};
`define rfreerun_tx_TX_IDX              47
`define rtxwrclksel_TX_IDX              48
`define rtxrdclksel_TX_IDX              49

// page 12 - tx: 3
//assign  pcs_ctrl12_ch0_ext = {rrev_loopbk[0], ralempty_ch0, ralfull_ch0, rforce_disp[0], 
//                              rkchar[0], rosbased[0], rensymswap_tx[0], 1'b0, rosnumber_ch0};
`define rrev_loopbk_TX_IDX              50
`define rforce_disp_TX_IDX              51
`define rensymswap_tx_TX_IDX            52

// page 13 - tx: 4
//assign  pcs_ctrl13_ch0_ext = {rwa_6g_en[0], renpolinv_tx[0], rbitslip_size_ch0, rbytord_2sym_en[0],
//                              rbysync_polinv_en[0], rbitloc_rev_en[0], rbyte_rev_en[0], renbitrev_tx[0],
//                              rbyteorden_ch0, rbytordplden[0], rphfifopldentx[0], rphfifoursttx[0],
//                              rphfifopldenrx[0], rautoinsdis[0]};
`define renpolinv_tx_TX_IDX             54
`define renbitrev_tx_TX_IDX             55
`define rphfifopldentx_TX_IDX           56
`define rphfifoursttx_TX_IDX            57

// pma 1 - tx
//assign  pma_ctrl1_ch0_ext = {rtx_vod_sel_ch0, rtx_slewrate[0], rpmphs_2tap_ch0,
//                             rpmphs_1tap_ch0, rtx_vtt_ch0, rpmphs_ptap_ch0};
`define rtx_vod_sel_TX_IDX_0            60
`define rtx_vod_sel_TX_IDX_2            62
`define rtx_slewrate_TX_IDX             63
`define rpmphs_2tap_TX_IDX_0            64
`define rpmphs_2tap_TX_IDX_2            66
`define rpmphs_1tap_TX_IDX_0            67
`define rpmphs_1tap_TX_IDX_3            70
`define rtx_vtt_TX_IDX_0                71
`define rtx_vtt_TX_IDX_1                72
`define rpmphs_ptap_TX_IDX_0            73
`define rpmphs_ptap_TX_IDX_2         75

// pma_ctrl8: 4.807c-807h - TX portion
//assign  pma_ctrl8_ch0_ext = {rs_lpbk[0], r_rlpbk[0], rs_rdlpbk[0], rrx_revlb_sw[0],
//                             rurx_pdb[0], rtx_cgb_pdb[0], rtx_ob_pdb[0], rrx_cru_pdb[0],
//                             rrx_cru_rst[0], rrx_ib_pdb[0], rrxurstpma[0], radce_adapt[0],
//                             radce_pdb[0], radce_rst[0], rsig_inv_2tap[0], rsig_inv_pre[0]};
`define r_rlpbk_TX_IDX                  76
`define rs_rdlpbk_TX_IDX                77
`define rsig_inv_2tap_TX_IDX            78
`define rsig_inv_pre_TX_IDX             79


// tx_max = 149 ------------------------------------------------------------------------

`timescale 1 ps / 1 ps
module arriagx_hssi_transmitter (
    analogreset,
    analogx4fastrefclk,
    analogx4refclk,
    analogx8fastrefclk,
    analogx8refclk,
    coreclk,
    ctrlenable,
    datain,
    datainfull,
    detectrxloop,
    detectrxpowerdn,
    digitalreset,
    dispval,
    dividerpowerdn,
    dpriodisable,
    dprioin,
    enrevparallellpbk,
    forcedispcompliance,
    forcedisp,
    forceelecidle,
    invpol,
    obpowerdn,
    phfiforddisable,
    phfiforeset,
    phfifowrenable,
    phfifox4bytesel,
    phfifox4rdclk,
    phfifox4rdenable,
    phfifox4wrenable,
    phfifox8bytesel,
    phfifox8rdclk,
    phfifox8rdenable,
    phfifox8wrenable,
    pipestatetransdone,
    pllfastclk,
    powerdn,
    quadreset,
    refclk,
    revserialfdbk,
    revparallelfdbk,
    termvoltage,
    vcobypassin,
    xgmctrl,
    xgmdatain,

    clkout,
    dataout,
    dprioout,
    parallelfdbkout,
    phfifooverflow,
    phfifounderflow,
    phfifobyteselout,
    phfifordclkout,
    phfifordenableout,
    phfifowrenableout,
    pipepowerdownout,
    pipepowerstateout,
    rdenablesync,
    refclkout,
    rxdetectvalidout,
    rxfoundout,
    serialfdbkout,
    xgmctrlenable,
    xgmdataout
);

parameter allow_polarity_inversion = "false";
parameter channel_bonding          = "none";   // none, x8, x4
parameter channel_number           = 0;
parameter channel_width            = 8;
parameter disable_ph_low_latency_mode = "false";
parameter disparity_mode           = "none";   // legacy, new, none
parameter divider_refclk_select_pll_fast_clk0 = "true";
parameter dprio_mode               = "none";
parameter elec_idle_delay          = 5;  // new in 6.0 <3-6>
parameter enable_bit_reversal      = "false";
parameter enable_idle_selection    = "false";  
parameter enable_symbol_swap       = "false";
parameter enable_reverse_parallel_loopback = "false";
parameter enable_reverse_serial_loopback   = "false";
parameter enable_self_test_mode    = "false";
parameter enc_8b_10b_compatibility_mode    = "true"; 
parameter enc_8b_10b_mode          = "none";   // cascade, normal, none
parameter force_echar              = "false";
parameter force_kchar              = "false";
parameter low_speed_test_select    = 0;
parameter prbs_all_one_detect      = "false";
parameter protocol_hint            = "basic";
parameter refclk_divide_by         = 1;
parameter refclk_select            = "local";                          // cmu_clk_divider
parameter reset_clock_output_during_digital_reset = "false"; 
parameter rxdetect_ctrl            = 0;
parameter self_test_mode           = "incremental";      
parameter serializer_clk_select    = "local";  // analogx4refclk, anlogx8refclk
parameter transmit_protocol        = "basic";                     // xaui/pipe/gige/basic?
parameter use_double_data_mode     = "false"; 
parameter use_serializer_double_data_mode = "false";
parameter wr_clk_mux_select        = "CORE_CLK";  // INT_CLK                  // int_clk

// PMA settings
parameter vod_selection            = 0;
parameter enable_slew_rate         = "false";
parameter preemp_tap_1             = 0;
parameter preemp_tap_2             = 0;
parameter preemp_pretap            = 0;
parameter preemp_tap_2_inv         = "false"; // New in rev 2.1
parameter preemp_pretap_inv        = "false"; // New in rev 2.1

parameter termination              = "OCT_100_OHMS";  // new in 5.1SP1

parameter use_termvoltage_signal = "true";
parameter common_mode = "0.6V";
parameter analog_power = "1.5V"; 

// PE ONLY parameters
parameter allow_vco_bypass         = "false";

// POF ONLY parameters
parameter enable_phfifo_bypass     = "false";

// LOCAL_PARAMETERS_BEGIN

parameter dprio_width              = 100;             // 6.1
parameter dprio_config_mode        = 0;               // 6.1

parameter CTRL_IN_WIDTH = (use_serializer_double_data_mode == "true"  && use_double_data_mode == "true")  ? 4 :
                           (use_serializer_double_data_mode == "false" && use_double_data_mode == "false") ? 1 : 2;

parameter DATA_IN_WIDTH = channel_width;

// split 100 = 64 (PCS), 32 (PMA)
//parameter TX_PMA_ST = 68;

parameter DPRIO_CHANNEL_INTERFACE_BIT = 4;

// LOCAL_PARAMETERS_END

input                      analogreset;
input                      analogx4fastrefclk;
input                      analogx4refclk;
input                      analogx8fastrefclk;
input                      analogx8refclk;
input                      coreclk;
input [CTRL_IN_WIDTH-1:0]  ctrlenable;
input [DATA_IN_WIDTH-1:0]  datain;
input [43:0]               datainfull;
input                      detectrxloop;
input                      detectrxpowerdn;
input                      digitalreset;
input [CTRL_IN_WIDTH-1:0]  dispval;
input                      dividerpowerdn;
input                      dpriodisable;
input [dprio_width -1 : 0] dprioin;
input                      enrevparallellpbk;
input                      forcedispcompliance;
input [CTRL_IN_WIDTH-1:0]  forcedisp;
input                      forceelecidle;
input                      invpol;
input                      obpowerdn;
input                      phfiforddisable;
input                      phfiforeset;
input                      phfifowrenable;
input                      phfifox4bytesel;
input                      phfifox4rdclk;
input                      phfifox4rdenable;
input                      phfifox4wrenable;
input                      phfifox8bytesel;
input                      phfifox8rdclk;
input                      phfifox8rdenable;
input                      phfifox8wrenable;
input                      pipestatetransdone;
input [1:0]                pllfastclk;
input [1:0]	               powerdn;
input                      quadreset;
input                      refclk;
input                      revserialfdbk;
input [19:0]               revparallelfdbk;
input [1:0]                termvoltage;
input                      vcobypassin;    // PE, POF only
input                      xgmctrl;
input [7:0]	               xgmdatain;

output                     clkout;
output                     dataout;
output [dprio_width -1 : 0] dprioout;
output [19:0]              parallelfdbkout;
output                     phfifooverflow;
output                     phfifounderflow;
output                     phfifobyteselout;
output                     phfifordclkout;
output                     phfifordenableout;
output                     phfifowrenableout;
output [1:0]               pipepowerdownout;   
output [3:0]               pipepowerstateout;
output                     rdenablesync;
output                     refclkout;
output                     rxdetectvalidout;
output [1:0]               rxfoundout;
output                     serialfdbkout;
output                     xgmctrlenable;
output [7:0]               xgmdataout;

reg  [3:0]                tmp_ctrlenable;
reg  [39:0]               tmp_datain;
reg  [3:0]                tmp_dispval;
reg  [3:0]                tmp_forcedisp;

// atom level initial CRAM ---------------------------------------------------
reg init_r8b10b_enc_ibm_en;           // tx_pcs
reg [1:0] init_rbist_sel;
reg init_rbisten_tx;
reg init_rcascaded_8b10b_en_tx;
reg [1:0] init_rcxpat_chnl_en;
reg init_rdwidth_tx;
reg init_renbitrev_tx;
reg init_rendec_data_sel_tx;
reg init_rendec_tx;
reg init_renpolinv_tx;
reg init_rensymswap_tx;
reg init_rforce_disp;
reg init_rforce_echar;
reg init_rforce_kchar;
reg init_rfreerun_tx;
reg init_rge_xaui_tx;
reg init_rib_force_disp;
reg init_rindv_tx;
reg init_rphfifo_master_sel_tx;
reg init_rphfifopldentx;
reg init_rphfifoursttx;
reg init_rpma_doublewidth_tx;
reg init_rpmadwidth_tx;
reg [2:0 ] init_rprbs_sel;
reg init_rprbsen_tx;
reg init_rrev_loopbk;
reg init_rtx_cmu_sel;          // added in 6.1
reg init_rtx_pipe_enable;
reg init_rtxfifo_dis;
reg init_rtxfifo_lowlatency_en;
reg init_rtxrdclksel;
reg init_rtxwrclksel;
reg init_rclkcmpinsertpad;             // rx only ========= pipe ===========	
reg init_rrdwidth_rx;                  // rx only
reg init_rrx_detect_bypass;            // rx only
reg init_rrx_pipe_enable;              // rx only
reg [1:0] init_rtx_elec_idle_delay;    // rx only

reg init_is_lane0;
reg init_scan_mode;

// PMA CRAM
reg init_r_rlpbk;
reg init_rs_rdlpbk;
reg [1:0] init_serializer_clk_select;  // local = 2'b00, analogx4refclk = 2'b01, analogx8refclk = 2'b11;

// VOD_Selection and Pre_emphasis; Slewrate, VTT
reg [2:0] init_rtx_vod_sel;
reg       init_rtx_slewrate; 
reg [2:0] init_rpmphs_2tap;
reg [3:0] init_rpmphs_1tap; 
reg [1:0] init_rtx_vtt;
reg [2:0] init_rpmphs_ptap;
reg       init_rsig_inv_2tap;           // new in wys 2.1
reg       init_rsig_inv_pre;            // new in wys 2.1
                             
// tx_sub-block interface: tx channel clock divider (tcd) --------------------
wire  tcd_in_dpriodisable;
wire [9:0] tcd_in_dprioin;
wire  tcd_in_clkin0, tcd_in_clkin1;
wire  tcd_in_reset;
wire  tcd_out_lclkout, tcd_out_fclkout;

parameter tcd_para_clk_divide_by_m = ((enc_8b_10b_mode == "none") && ((channel_width == 8) || (channel_width == 16) || (channel_width == 32))) ? 4 : 5;
parameter tcd_para_clk_divide_by_2_select = "false";  // moved to 20 to 10 mux

// tx_sub-block interface: tx_serializer ------------------------------------
wire  ser_serialclk;
wire  ser_parallelclk;
wire  [19:0] ser_datain;
wire  ser_reset;
wire  ser_elecreset;           // Z dataout buf
wire  ser_rseriallpbkdatain;
wire  ser_rseriallpbkctrl;
wire  ser_rdwidth;             // 0 => 8-bit, 1 => 10-bit
wire  ser_rdoublewidth;        // 0 => 8/10,  1 => 16/20

wire ser_serialdataout;
wire ser_seriallpbkdataout;
wire ser_clkout;              // = parallelclk/2 when doublewidth 

// tx_sub-block interface: rx_det ------------------------------------------
wire rxdet_in_RX_DET_PDB; 
wire rxdet_in_CLK15M; 
wire rxdet_in_TX_DET_RX;

wire rxdet_out_RX_FOUND;
wire rxdet_out_RX_DET_VALID;

// tx_sub-block interface: pcs_reset (pr) ------------------------------------
wire   pr_in_hard_reset;
wire   pr_in_clk_2_b;
wire   pr_in_refclk_b_in;
wire   pr_in_scan_mode;
wire   pr_in_rxpcs_rst;
wire   pr_in_txpcs_rst;

wire   pr_out_rxrst_int;
wire   pr_out_txrst_int;

// tx_sub-block interface: pipe_interface (pi) --------------------------------

// inputs
wire         pi_in_pipe_tx_clk;
wire  [1:0]  pi_in_powerdown;
wire         pi_in_refclk_b;
wire         pi_in_refclk_b_reset_n;          // new in ww29
wire         pi_in_revloopback;
wire         pi_in_state_transition_done;
wire         pi_in_tx_elec_idle_comp;
wire         pi_in_tx_pipe_reset_n;
wire         pi_in_txcompliance;
wire  [43:0] pi_in_txd_ch;
wire  [43:0] pi_in_txd_ch_dprio;             // new in 6.1
wire         pi_in_txdetectrxloopback;
wire         pi_in_txelecidle;
wire  [43:0] pi_in_txd_ch_tmp;               // before interleaving in dwidth_single PMA

// outputs
wire  [3:0]  pi_out_powerstate; // to top - both cmu and rx
wire         pi_out_rev_loopbk;       // to TD
wire         pi_out_tx_elec_idle;     // to tx PMA - TX sending electrical idle
wire         pi_out_txbeacon;         // to tx PMA - died at digi_top
wire  [43:0] pi_out_txd;
wire         pi_out_txdetectrx;       // to tx PMA - RX_DET

// tx_sub-block interface: tx digital (td) -----------------------------------

// inputs
wire  td_in_phfifourst_tx;
wire  td_in_pld_tx_clk;
wire  td_in_polinv_tx;
wire  td_in_rddisable_tx;
wire  td_in_refclk_pma;
wire  [19:0] td_in_rev_loop_data;
wire  td_in_rev_loopbk;
wire  td_in_tx_ctl_ts;
wire  [7:0] td_in_tx_data_ts;
wire  [43:0] td_in_txd;
wire  [3:0] td_in_txfifo_shared_sig_in_ch0;
wire  [3:0] td_in_txfifo_shared_sig_in_q0_ch0;
wire  td_in_txpcs_rst;
wire  td_in_txpma_local_clk;
wire  td_in_wrenable_tx;


// outputs
wire  td_out_empty_tx;
wire  [9:0] td_out_encoder_testbus;
wire  td_out_full_tx;
wire  [19:0] td_out_pudr;
wire  td_out_rd_enable_sync;
wire  td_out_refclk_b;
wire  td_out_tx_clk_out;
wire  td_out_tx_ctl_tc;
wire  [9:0] td_out_tx_ctrl_testbus;
wire  [7:0] td_out_tx_data_tc;
wire  td_out_tx_pipe_clk;
wire  td_out_tx_pipe_electidle;
wire  td_out_tx_pipe_soft_reset;
wire  [3:0] td_out_txfifo_shared_sig_out;
wire  [19:0] td_out_txlp20b;


// atom level DPRIO input CRAM ------------------------------------------------
wire dprioin_r8b10b_enc_ibm_en;           // tx_pcs
wire [1:0] dprioin_rbist_sel;
wire dprioin_rbisten_tx;
wire dprioin_rcascaded_8b10b_en_tx;
wire [1:0] dprioin_rcxpat_chnl_en;
wire dprioin_rdwidth_tx;
wire dprioin_renbitrev_tx;
wire dprioin_rendec_data_sel_tx;
wire dprioin_rendec_tx;
wire dprioin_renpolinv_tx;
wire dprioin_rensymswap_tx;
wire dprioin_rforce_disp;
wire dprioin_rforce_echar;
wire dprioin_rforce_kchar;
wire dprioin_rfreerun_tx;
wire dprioin_rge_xaui_tx;
wire dprioin_rib_force_disp;
wire dprioin_rindv_tx;
wire dprioin_rphfifo_master_sel_tx;
wire dprioin_rphfifopldentx;
wire dprioin_rphfifoursttx;
wire dprioin_rpma_doublewidth_tx;
wire dprioin_rpmadwidth_tx;
wire [2:0] dprioin_rprbs_sel;
wire dprioin_rprbsen_tx;
wire dprioin_rrev_loopbk;
wire dprioin_rtx_cmu_sel;          // added in 6.1
wire dprioin_rtx_pipe_enable;
wire dprioin_rtxfifo_dis;
wire dprioin_rtxfifo_lowlatency_en;
wire dprioin_rtxrdclksel;
wire dprioin_rtxwrclksel;
wire dprioin_rclkcmpinsertpad;         // rx only ========= pipe ===========	
wire dprioin_rrdwidth_rx;              // rx only
wire dprioin_rrx_detect_bypass;        // rx only
wire dprioin_rrx_pipe_enable;          // rx only
wire [1:0] dprioin_rtx_elec_idle_delay;    // rx only

wire dprioin_is_lane0;
wire dprioin_scan_mode;

// PMA
wire       dprioin_r_rlpbk;
wire       dprioin_rs_rdlpbk;
wire [1:0] dprioin_serializer_clk_select;  // local = 2'b00, analogx4refclk = 2'b01, analogx8refclk = 2'b11;

wire [2:0] dprioin_rtx_vod_sel;
wire       dprioin_rtx_slewrate; 
wire [2:0] dprioin_rpmphs_2tap;
wire [3:0] dprioin_rpmphs_1tap; 
wire [1:0] dprioin_rtx_vtt;
wire [2:0] dprioin_rpmphs_ptap;
wire       dprioin_rsig_inv_2tap;           // new in wys 2.1
wire       dprioin_rsig_inv_pre;            // new in wys 2.1

// Final CRAM to pass to RTL ------------------------------------------
wire cram_r8b10b_enc_ibm_en;           // tx_pcs
wire [1:0] cram_rbist_sel;
wire cram_rbisten_tx;
wire cram_rcascaded_8b10b_en_tx;
wire [1:0] cram_rcxpat_chnl_en;
wire cram_rdwidth_tx;
wire cram_renbitrev_tx;
wire cram_rendec_data_sel_tx;
wire cram_rendec_tx;
wire cram_renpolinv_tx;
wire cram_rensymswap_tx;
wire cram_rforce_disp;
wire cram_rforce_echar;
wire cram_rforce_kchar;
wire cram_rfreerun_tx;
wire cram_rge_xaui_tx;
wire cram_rib_force_disp;
wire cram_rindv_tx;
wire cram_rphfifo_master_sel_tx;
wire cram_rphfifopldentx;
wire cram_rphfifoursttx;
wire cram_rpma_doublewidth_tx;
wire cram_rpmadwidth_tx;
wire [2:0] cram_rprbs_sel;
wire cram_rprbsen_tx;
wire cram_rrev_loopbk;
wire cram_rtx_cmu_sel;          // added in 6.1
wire cram_rtx_pipe_enable;
wire cram_rtxfifo_dis;
wire cram_rtxfifo_lowlatency_en;
wire cram_rtxrdclksel;
wire cram_rtxwrclksel;
wire cram_rclkcmpinsertpad;             // rx only ========= pipe ===========	
wire cram_rrdwidth_rx;                  // rx only
wire cram_rrx_detect_bypass;            // rx only
wire cram_rrx_pipe_enable;              // rx only
wire [1:0] cram_rtx_elec_idle_delay;    // rx only

// PMA CRAM
wire cram_r_rlpbk;
wire cram_rs_rdlpbk;

wire cram_is_lane0;
wire cram_scan_mode;

wire [2:0] cram_rtx_vod_sel;
wire       cram_rtx_slewrate; 
wire [2:0] cram_rpmphs_2tap;
wire [3:0] cram_rpmphs_1tap; 
wire [1:0] cram_rtx_vtt;
wire [2:0] cram_rpmphs_ptap;
wire       cram_rsig_inv_2tap;           // new in wys 2.1
wire       cram_rsig_inv_pre;            // new in wys 2.1

// dprio related to clock divider
reg  [1:0] init_rtx_m_sel;
reg        init_rtx_cgb_1x_en;
reg        init_rtx_cgb_4x_en;
reg        init_rtx_4x_sw;
wire [1:0] dprioin_rtx_m_sel;
wire       dprioin_rtx_cgb_1x_en;
wire       dprioin_rtx_cgb_4x_en;
wire       dprioin_rtx_4x_sw;
wire [1:0] cram_rtx_m_sel;
wire       cram_rtx_cgb_1x_en;
wire       cram_rtx_cgb_4x_en;
wire       cram_rtx_4x_sw;

/////////////////////////////////////////////////////////////////////////////////
// Internal Variables  --------------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////
integer i;
integer j;
reg     rxdet_fixclk_reg;

function [2:0] compute_rprbs_sel;
input          pma_doublewidth;
input          pma_width;
input          test_mode;
reg [8*20:1]   test_mode;
reg [2:0]      res;

begin
    case ({pma_doublewidth, pma_width})
        2'b00 : 
                begin
                    if (test_mode == "high_freq" || test_mode == "high frequency")
                        res = 3'b001;
                    else  
                        res = 3'b000;     // PRBS_8
                end
        2'b01 :
                begin
                    if (test_mode == "high_freq"  || test_mode == "high frequency")
                        res = 3'b001;
                    else if (test_mode == "low_freq"  || test_mode == "low frequency")
                        res = 3'b010;                     // pattern 10
                    else if (test_mode == "mixed_freq"  || test_mode == "mixed frequency")
                        res = 3'b011;                     // pattern 10
                    else
                        res = 3'b000;                     // PRBS_10
                end
        2'b10 : 
                begin
                    if (test_mode == "high_freq" || test_mode == "high frequency")
                        res = 3'b010;
                    else if (test_mode == "PRBS_23" || test_mode == "prbs_23" || test_mode == "prbs23")
                        res = 3'b001;                   
                    else
                        res = 3'b000;                     // PRBS_7
                end
        2'b11 :
                begin
                    if (test_mode == "high_freq" || test_mode == "high frequency")
                        res = 3'b010;
                    else if (test_mode == "low_freq" || test_mode == "low frequency")
                        res = 3'b011;                     // pattern 10
                    else if (test_mode == "mixed_freq" || test_mode == "mixed frequency")
                        res = 3'b100;                     // pattern 10
                    else if (test_mode == "PRBS_23" || test_mode == "prbs_23" || test_mode == "prbs23")
                        res = 3'b001;                   
                    else
                        res = 3'b000;                     // PRBS_7
                end

        default : $display("Invalid pma_doublewidth and pma_width selection");
    endcase
    compute_rprbs_sel = res;
end
endfunction

/////////////////////////////////////////////////////////////////////////////////
// Timing - INPUT BUFFERS  ----------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire [CTRL_IN_WIDTH-1:0]      ctrlenable_in;
wire [DATA_IN_WIDTH-1:0]      datain_in;
wire [CTRL_IN_WIDTH-1:0]      dispval_in;
wire [CTRL_IN_WIDTH-1:0]      forcedisp_in;
wire [1:0]	                  powerdn_in;

wire coreclk_in;
wire detectrxloop_in;
wire enrevparallellpbk_in;
wire forcedispcompliance_in;
wire forceelecidle_in;
wire invpol_in;
wire phfifowrenable_in;
wire refclk_in;

wire refclk_in_delayed; // to avoid race for x8 bonded

buf buf_coreclk                       (coreclk_in,             coreclk);
buf buf_ctrl [CTRL_IN_WIDTH-1:0]      (ctrlenable_in,          ctrlenable);
buf buf_data [DATA_IN_WIDTH-1:0]      (datain_in,              datain);
buf buf_detectrxloop                  (detectrxloop_in,        detectrxloop);
buf buf_dispval [CTRL_IN_WIDTH-1:0]   (dispval_in,             dispval);
buf buf_enrevparallellpbk             (enrevparallellpbk_in,   enrevparallellpbk);
buf buf_forcedispcompliance           (forcedispcompliance_in, forcedispcompliance);
buf buf_forcedisp [CTRL_IN_WIDTH-1:0] (forcedisp_in,           forcedisp);
buf buf_forceelecidle                 (forceelecidle_in,       forceelecidle);
buf buf_invpol                        (invpol_in,              invpol);
buf buf_phfifowrenable                (phfifowrenable_in,      phfifowrenable);
buf buf_powerdn [1:0]	              (powerdn_in,             powerdn);
buf buf_refclk                        (refclk_in,              refclk);

assign #2 refclk_in_delayed = refclk_in;

/////////////////////////////////////////////////////////////////////////////////
// TIMING -- TCO/TSU/HOLD                                                      //
/////////////////////////////////////////////////////////////////////////////////

specify

    $setuphold(posedge coreclk, ctrlenable,     0, 0);
    $setuphold(posedge coreclk, datain,         0, 0);
    $setuphold(posedge coreclk, datainfull,     0, 0);   // 9.1
    $setuphold(posedge coreclk, detectrxloop,   0, 0);
    $setuphold(posedge coreclk, dispval,        0, 0);
    $setuphold(posedge coreclk, forcedisp,      0, 0);
    $setuphold(posedge coreclk, forcedispcompliance, 0, 0);
    $setuphold(posedge coreclk, forceelecidle,  0, 0);
    $setuphold(posedge coreclk, phfifowrenable, 0, 0);
    $setuphold(posedge coreclk, powerdn,        0, 0);

    (posedge coreclk => (phfifooverflow  +: td_out_full_tx))  = (0, 0);
    (posedge coreclk => (phfifounderflow +: td_out_empty_tx)) = (0, 0);

endspecify

/////////////////////////////////////////////////////////////////////////////////
// dprio outputs
/////////////////////////////////////////////////////////////////////////////////

wire [149:0]  dprioin_in;
wire [149:0]  wire_dprioout;
assign dprioout = wire_dprioout;
assign dprioin_in = dprioin;

// inital CRAMs from parameters - CRAM_TABLE 1
initial begin
    init_r8b10b_enc_ibm_en     = (enc_8b_10b_compatibility_mode == "true") ? 1'b1 : 1'b0;
    init_rbist_sel             = (self_test_mode == "incremental") ? 2'b00 :        // to bist_gen
                                 (self_test_mode == "cjpat")        ? 2'b01 :
                                 (self_test_mode == "crpat")        ? 2'b10 : 2'b00;
    init_rbisten_tx            = ((enable_self_test_mode == "true") && 
                                  (self_test_mode == "incremental" || self_test_mode == "cjpat" ||  
                                   self_test_mode == "cjpat")) ? 1'b1 : 1'b0;  // bist_gen        
    init_rcascaded_8b10b_en_tx = (enc_8b_10b_mode == "cascaded") ? 1'b1 : 1'b0;
    init_rcxpat_chnl_en	       = (channel_number == 1) ? 2'b01 :               // bist_gen
                                 (channel_number == 2) ? 2'b10 :
                                 (channel_number == 3) ? 2'b11 : 2'b00;
    init_rdwidth_tx	           = (use_double_data_mode == "true") ? 1'b1 : 1'b0;
    init_renbitrev_tx          = (enable_bit_reversal == "true") ? 1'b1 : 1'b0;
    init_rendec_data_sel_tx	   = (transmit_protocol == "xaui") ? 1'b0 : 1'b1; // 0=ts_; 1=tc_
    init_rendec_tx             = (enc_8b_10b_mode != "none") ? 1'b1 : 1'b0;
    init_renpolinv_tx          = (allow_polarity_inversion == "true") ? 1'b1 : 1'b0;
    init_rensymswap_tx         = (enable_symbol_swap == "true") ? 1'b1 : 1'b0;
    init_rforce_disp           = (disparity_mode == "new") ? 1'b1 : 1'b0;
    init_rforce_echar          = (force_echar == "true") ? 1'b1 : 1'b0;
    init_rforce_kchar          = (force_kchar == "true") ? 1'b1 : 1'b0;
    init_rfreerun_tx           = (reset_clock_output_during_digital_reset == "false") ? 1'b1 : 1'b0;
    init_rge_xaui_tx           = (transmit_protocol == "gige" || enable_idle_selection == "true") ? 1'b1 : 1'b0;
    init_rib_force_disp	       = (disparity_mode == "legacy") ? 1'b1 : 1'b0;
    init_rindv_tx              = (channel_bonding == "x4" || channel_bonding == "x8" || transmit_protocol == "xaui") ? 1'b0 : 1'b1;
    init_rphfifo_master_sel_tx = (channel_bonding == "x8") ? 1'b0 : 1'b1;
    init_rphfifopldentx        = 1'b1;        // Altera Internal Mode - Enable PLD controlled write and read ** enabled to match ASM
    init_rphfifoursttx         = 1'b1;        // Altera Internal Mode - 0 = normal operation:                ** enabled for POF
    init_rpma_doublewidth_tx   = (use_serializer_double_data_mode == "true") ? 1'b1 : 1'b0; // 1 = 16/20, 0 = 8/10
    init_rpmadwidth_tx         =  ((enc_8b_10b_mode == "none") && ((channel_width == 8) || (channel_width == 16) || (channel_width == 32))) ? 1'b0 : 1'b1; // 0 = 8 bit, 1 = 10 bit
    init_rprbs_sel             = compute_rprbs_sel(init_rpma_doublewidth_tx,init_rpmadwidth_tx,self_test_mode);
    init_rprbsen_tx            = ((enable_self_test_mode == "true") && (self_test_mode != "incremental") &&
                                  (self_test_mode != "cjpat") && (self_test_mode != "crpat")) ?
                                   1'b1 : 1'b0;  // prbs_gen
    init_rrev_loopbk           = (enable_reverse_parallel_loopback == "true") ? 1'b1 : 1'b0;
    init_rtx_pipe_enable       = (transmit_protocol == "pipe") ? 1'b1 : 1'b0;
    init_rtxfifo_dis           = (enable_phfifo_bypass == "true") ? 1'b1 : 1'b0;           // cannot bypass
    init_rtxfifo_lowlatency_en = (disable_ph_low_latency_mode == "false") ? 1'b1 : 1'b0; 
    init_rtxrdclksel           = (refclk_select == "cmu_clock_divider" || refclk_select == "cmu clock divider") ? 1'b1 : 1'b0;      // TxFifo Rd clock 1=refclk_pma, 0=local_refclk_pma
    init_rtxwrclksel           = (wr_clk_mux_select == "int_clk" || wr_clk_mux_select == "INT_CLK" || 
                                  wr_clk_mux_select == "int clk" || wr_clk_mux_select == "internal clock") ? 1'b1 : 1'b0;  // TxFifo Write clk. 1=int_clk; 0=pld_tx_clk
    init_rclkcmpinsertpad      = 1'b1;      // for rx only   ====== pipe section started ========	
    init_rrdwidth_rx           = 1'b1;           // for rx only extra r in pipe interface
    init_rrx_detect_bypass     = 1'b1;     // for rx only
    init_rrx_pipe_enable       = 1'b1;       // for rx only
    init_rtx_elec_idle_delay   = 2'b11;   // Engineering bits - delay numbers - on purpse seting 6 to compensate PMA model

    init_is_lane0              = (channel_number == 0) ? 1'b1 : 1'b0;
    init_scan_mode             = 1'b0;

    // PMA CRAM
    init_r_rlpbk      = (enable_reverse_serial_loopback == "true") ? 1'b1 : 1'b0;
    init_rs_rdlpbk    = (enable_reverse_serial_loopback == "true") ? 1'b1 : 1'b0;
    init_serializer_clk_select = (serializer_clk_select == "local") ? 2'b00 :
                                 (serializer_clk_select == "analogx4refclk") ? 2'b01 :
                                 (serializer_clk_select == "analogx8refclk") ? 2'b11 : 2'bzz;

    // VOD_Selection and Pre_emphasis; Slewrate, VTT
    init_rtx_vod_sel  = vod_selection;                               // 3-bits
    init_rtx_slewrate = enable_slew_rate == "true" ? 1'b1 : 1'b0;    // 1-bit
    init_rpmphs_2tap  = preemp_tap_2;                                // 3
    init_rpmphs_1tap  = preemp_tap_1;                                // 4 
    init_rtx_vtt      = 2'b00;                                       // 2 - to add in wys
    init_rpmphs_ptap  = preemp_pretap;                               // 3

    init_rsig_inv_2tap = preemp_tap_2_inv == "true" ? 1'b1 : 1'b0;   // new in wys 2.1
    init_rsig_inv_pre  = preemp_pretap_inv == "true" ? 1'b1 : 1'b0;  // new in wys 2.1

	// dprio related to clock divider
	init_rtx_m_sel     = (refclk_divide_by == 2) ? 2'b01 :
	                     (refclk_divide_by == 4) ? 2'b10 : 2'b00;
	init_rtx_cgb_1x_en = (serializer_clk_select == "local") ? 1'b1 : 1'b0;
	init_rtx_cgb_4x_en = (serializer_clk_select == "analogx4refclk") ? 1'b1 : 1'b0;
	init_rtx_4x_sw     = (serializer_clk_select == "analogx8refclk") ? 1'b1 : 1'b0;

	// refclk selection to channel clock divider
    init_rtx_cmu_sel  =  (divider_refclk_select_pll_fast_clk0 == "true") ? 1'b0 : 1'b1;
    
	// padding extra bits
    for (i=CTRL_IN_WIDTH; i < 4; i=i+1)
        tmp_ctrlenable[i] = 1'b0;

    for (i=DATA_IN_WIDTH; i < 40; i=i+1)
        tmp_datain[i] = 1'b0;

    for (i=CTRL_IN_WIDTH; i < 4; i=i+1)
        tmp_dispval[i] = 1'b0;

    for (i=CTRL_IN_WIDTH; i < 4; i=i+1)
        tmp_forcedisp[i] = 1'b0;

end

// Set DPRIO input CRAM from dprioin - CRAM_Table 2A ----------------------------------------

// Table 2A needs to use def'ed INDEX for PCS
assign dprioin_r8b10b_enc_ibm_en     = dprioin_in[`r8b10b_enc_ibm_en_TX_IDX];
assign dprioin_rbist_sel             = init_rbist_sel;
assign dprioin_rbisten_tx            = init_rbisten_tx;
assign dprioin_rcascaded_8b10b_en_tx = dprioin_in[`rcascaded_8b10b_en_tx_TX_IDX];
assign dprioin_rcxpat_chnl_en        = init_rcxpat_chnl_en;
assign dprioin_rdwidth_tx            = dprioin_in[`rdwidth_tx_TX_IDX];
assign dprioin_renbitrev_tx          = dprioin_in[`renbitrev_tx_TX_IDX];
assign dprioin_rendec_data_sel_tx    = dprioin_in[`rendec_data_sel_tx_TX_IDX];
assign dprioin_rendec_tx             = dprioin_in[`rendec_tx_TX_IDX];
assign dprioin_renpolinv_tx          = dprioin_in[`renpolinv_tx_TX_IDX];
assign dprioin_rensymswap_tx         = dprioin_in[`rensymswap_tx_TX_IDX];
assign dprioin_rforce_disp           = dprioin_in[`rforce_disp_TX_IDX];
assign dprioin_rforce_echar          = dprioin_in[`rforce_echar_TX_IDX];
assign dprioin_rforce_kchar          = dprioin_in[`rforce_kchar_TX_IDX];
assign dprioin_rfreerun_tx           = dprioin_in[`rfreerun_tx_TX_IDX];
assign dprioin_rge_xaui_tx           = dprioin_in[`rge_xaui_tx_TX_IDX];
assign dprioin_rib_force_disp        = dprioin_in[`rib_force_disp_TX_IDX];
assign dprioin_rindv_tx              = dprioin_in[`rindv_tx_TX_IDX];
assign dprioin_rphfifo_master_sel_tx = dprioin_in[`rphfifo_master_sel_tx_TX_IDX];
assign dprioin_rphfifopldentx        = dprioin_in[`rphfifopldentx_TX_IDX];
assign dprioin_rphfifoursttx         = dprioin_in[`rphfifoursttx_TX_IDX];
assign dprioin_rpma_doublewidth_tx   = dprioin_in[`rpma_doublewidth_tx_TX_IDX];    //dprioen
assign dprioin_rpmadwidth_tx         = dprioin_in[`rpmadwidth_tx_TX_IDX];          //dprioen
assign dprioin_rprbs_sel             = init_rprbs_sel;
assign dprioin_rprbsen_tx            = init_rprbsen_tx;
assign dprioin_rrev_loopbk           = dprioin_in[`rrev_loopbk_TX_IDX];
assign dprioin_rtx_cmu_sel           = dprioin_in[`rtx_cmu_sel_TX_IDX];
assign dprioin_rtx_pipe_enable       = dprioin_in[`rtx_pipe_enable_TX_IDX];
assign dprioin_rtxfifo_dis           = dprioin_in[`rtxfifo_dis_TX_IDX];
assign dprioin_rtxfifo_lowlatency_en = dprioin_in[`rtxfifo_lowlatency_en_TX_IDX];
assign dprioin_rtxrdclksel           = dprioin_in[`rtxrdclksel_TX_IDX];
assign dprioin_rtxwrclksel           = dprioin_in[`rtxwrclksel_TX_IDX];

assign dprioin_rclkcmpinsertpad      = init_rclkcmpinsertpad;  // rx only ========= pipe ===========	
assign dprioin_rrdwidth_rx           = init_rrdwidth_rx;              // rx only
assign dprioin_rrx_detect_bypass     = init_rrx_detect_bypass;        // rx only
assign dprioin_rrx_pipe_enable       = init_rrx_pipe_enable;          // rx only
assign dprioin_rtx_elec_idle_delay   = init_rtx_elec_idle_delay;   // rx only

assign dprioin_is_lane0              = init_is_lane0;
assign dprioin_scan_mode             = init_scan_mode;

// PMA
assign dprioin_rtx_vod_sel  = dprioin_in[`rtx_vod_sel_TX_IDX_2 : `rtx_vod_sel_TX_IDX_0];  // 3-bits
assign dprioin_rtx_slewrate = dprioin_in[`rtx_slewrate_TX_IDX];                              // 1-bit
assign dprioin_rpmphs_2tap  = dprioin_in[`rpmphs_2tap_TX_IDX_2 : `rpmphs_2tap_TX_IDX_0];  // 3
assign dprioin_rpmphs_1tap  = dprioin_in[`rpmphs_1tap_TX_IDX_3 : `rpmphs_1tap_TX_IDX_0];  // 4 
assign dprioin_rtx_vtt      = dprioin_in[`rtx_vtt_TX_IDX_1 : `rtx_vtt_TX_IDX_0];          // 2 - to add in wys
assign dprioin_rpmphs_ptap  = dprioin_in[`rpmphs_ptap_TX_IDX_2 : `rpmphs_ptap_TX_IDX_0];  // 3

// skip other bits in this frame
assign dprioin_rs_rdlpbk          = dprioin_in[`rs_rdlpbk_TX_IDX];       // 1 
assign dprioin_r_rlpbk            = dprioin_in[`r_rlpbk_TX_IDX];       // 1 
assign dprioin_rsig_inv_pre       = dprioin_in[`rsig_inv_pre_TX_IDX];       // 1
assign dprioin_rsig_inv_2tap      = dprioin_in[`rsig_inv_2tap_TX_IDX];       // 1 
assign dprioin_rsig_inv_pre       = dprioin_in[`rsig_inv_pre_TX_IDX];       // 1

// dprio related to clock divider
assign dprioin_rtx_m_sel     = dprioin_in[`rtx_m_sel_TX_IDX_1 : `rtx_m_sel_TX_IDX_0];
assign dprioin_rtx_cgb_1x_en = dprioin_in[`rtx_cgb_1x_en_TX_IDX];
assign dprioin_rtx_cgb_4x_en = dprioin_in[`rtx_cgb_4x_en_TX_IDX];
assign dprioin_rtx_4x_sw     = dprioin_in[`rtx_4x_sw_TX_IDX];

// Set DPRIO reg with initial parameters - CRAM_Table 2B ---------------------------

assign wire_dprioout[`r8b10b_enc_ibm_en_TX_IDX]     = init_r8b10b_enc_ibm_en;     
assign wire_dprioout[`rcascaded_8b10b_en_tx_TX_IDX] = init_rcascaded_8b10b_en_tx; 
assign wire_dprioout[`rdwidth_tx_TX_IDX]            = init_rdwidth_tx;           
assign wire_dprioout[`renbitrev_tx_TX_IDX]          = init_renbitrev_tx;          
assign wire_dprioout[`rendec_data_sel_tx_TX_IDX]    = init_rendec_data_sel_tx;    
assign wire_dprioout[`rendec_tx_TX_IDX]             = init_rendec_tx;             
assign wire_dprioout[`renpolinv_tx_TX_IDX]          = init_renpolinv_tx;          
assign wire_dprioout[`rensymswap_tx_TX_IDX]         = init_rensymswap_tx;         
assign wire_dprioout[`rforce_disp_TX_IDX]           = init_rforce_disp;           
assign wire_dprioout[`rforce_echar_TX_IDX]          = init_rforce_echar;          
assign wire_dprioout[`rforce_kchar_TX_IDX]          = init_rforce_kchar;          
assign wire_dprioout[`rfreerun_tx_TX_IDX]           = init_rfreerun_tx;           
assign wire_dprioout[`rge_xaui_tx_TX_IDX]           = init_rge_xaui_tx;           
assign wire_dprioout[`rib_force_disp_TX_IDX]        = init_rib_force_disp;        
assign wire_dprioout[`rindv_tx_TX_IDX]              = init_rindv_tx;              
assign wire_dprioout[`rphfifo_master_sel_tx_TX_IDX] = init_rphfifo_master_sel_tx; 
assign wire_dprioout[`rphfifopldentx_TX_IDX]        = init_rphfifopldentx;        
assign wire_dprioout[`rphfifoursttx_TX_IDX]         = init_rphfifoursttx;         
assign wire_dprioout[`rpma_doublewidth_tx_TX_IDX]   = init_rpma_doublewidth_tx;   
assign wire_dprioout[`rpmadwidth_tx_TX_IDX]         = init_rpmadwidth_tx;         
assign wire_dprioout[`rrev_loopbk_TX_IDX]           = init_rrev_loopbk;           
assign wire_dprioout[`rtx_cmu_sel_TX_IDX]           = init_rtx_cmu_sel;           
assign wire_dprioout[`rtx_pipe_enable_TX_IDX]       = init_rtx_pipe_enable;       
assign wire_dprioout[`rtxfifo_dis_TX_IDX]           = init_rtxfifo_dis;           
assign wire_dprioout[`rtxfifo_lowlatency_en_TX_IDX] = init_rtxfifo_lowlatency_en; 
assign wire_dprioout[`rtxrdclksel_TX_IDX]           = init_rtxrdclksel;           
assign wire_dprioout[`rtxwrclksel_TX_IDX]           = init_rtxwrclksel;           

//assign wire_dprioout[`rpmadwidth_tx_TX_IDX]       = init_rpmadwidth_tx;
//assign wire_dprioout[`rpma_doublewidth_tx_TX_IDX] = init_rpma_doublewidth_tx;
//assign wire_dprioout[38] = init_rtx_pipe_enable;
//assign wire_dprioout[39] = init_is_lane0;
//assign wire_dprioout[40] = init_scan_mode;

// PMA
assign wire_dprioout[`rtx_vod_sel_TX_IDX_2 : `rtx_vod_sel_TX_IDX_0] = init_rtx_vod_sel;    // 3-bits
assign wire_dprioout[`rtx_slewrate_TX_IDX]                             = init_rtx_slewrate;   // 1-bit
assign wire_dprioout[`rpmphs_2tap_TX_IDX_2 : `rpmphs_2tap_TX_IDX_0] = init_rpmphs_2tap;    // 3
assign wire_dprioout[`rpmphs_1tap_TX_IDX_3 : `rpmphs_1tap_TX_IDX_0] = init_rpmphs_1tap;    // 4 
assign wire_dprioout[`rtx_vtt_TX_IDX_1     : `rtx_vtt_TX_IDX_0]     = init_rtx_vtt;        // 2 - to add in wys
assign wire_dprioout[`rpmphs_ptap_TX_IDX_2 : `rpmphs_ptap_TX_IDX_0] = init_rpmphs_ptap;    // 3

// skip other bits in this frame
assign wire_dprioout[`rs_rdlpbk_TX_IDX]     = init_rs_rdlpbk;           // 1 
assign wire_dprioout[`r_rlpbk_TX_IDX]       = init_r_rlpbk;             // 1
assign wire_dprioout[`rsig_inv_2tap_TX_IDX] = init_rsig_inv_2tap;       // 1 
assign wire_dprioout[`rsig_inv_pre_TX_IDX]  = init_rsig_inv_pre;        // 1

// dprio related to clock divider
assign wire_dprioout[`rtx_m_sel_TX_IDX_1 : `rtx_m_sel_TX_IDX_0] = init_rtx_m_sel;
assign wire_dprioout[`rtx_cgb_1x_en_TX_IDX] = init_rtx_cgb_1x_en;
assign wire_dprioout[`rtx_cgb_4x_en_TX_IDX] = init_rtx_cgb_4x_en;
assign wire_dprioout[`rtx_4x_sw_TX_IDX]     = init_rtx_4x_sw;

// select CRAMs between DPIRO vs. parameters ----------------------------------------------------------------

// PCS - disabled with mpcs_dpriodisable - enable case by case
wire   mpcs_dpriodisable;
assign mpcs_dpriodisable = 1'b1;

assign cram_r8b10b_enc_ibm_en = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_r8b10b_enc_ibm_en : dprioin_r8b10b_enc_ibm_en;
assign cram_rbist_sel         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbist_sel : dprioin_rbist_sel;  // 2 bits
assign cram_rbisten_tx        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbisten_tx : dprioin_rbisten_tx;
assign cram_rcascaded_8b10b_en_tx = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rcascaded_8b10b_en_tx : dprioin_rcascaded_8b10b_en_tx;
assign cram_rcxpat_chnl_en    = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rcxpat_chnl_en : dprioin_rcxpat_chnl_en;
assign cram_rdwidth_tx        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rdwidth_tx : dprioin_rdwidth_tx;
assign cram_renbitrev_tx      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_renbitrev_tx : dprioin_renbitrev_tx;
assign cram_rendec_data_sel_tx = init_rendec_data_sel_tx;          // disable reconfiguration for quad-level crams
assign cram_rendec_tx         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rendec_tx : dprioin_rendec_tx;
assign cram_renpolinv_tx      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_renpolinv_tx : dprioin_renpolinv_tx;
assign cram_rensymswap_tx     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rensymswap_tx : dprioin_rensymswap_tx;
assign cram_rforce_disp       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rforce_disp : dprioin_rforce_disp;
assign cram_rforce_echar      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rforce_echar : dprioin_rforce_echar;
assign cram_rforce_kchar      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rforce_kchar : dprioin_rforce_kchar; 
assign cram_rfreerun_tx       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rfreerun_tx : dprioin_rfreerun_tx;
assign cram_rge_xaui_tx       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rge_xaui_tx : dprioin_rge_xaui_tx;
assign cram_rib_force_disp    = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rib_force_disp : dprioin_rib_force_disp;
assign cram_rindv_tx              = init_rindv_tx;                 // disable reconfiguration for quad-level crams
assign cram_rphfifo_master_sel_tx = init_rphfifo_master_sel_tx;    // disable reconfiguration for quad-level crams
assign cram_rphfifopldentx    = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rphfifopldentx : dprioin_rphfifopldentx;
assign cram_rphfifoursttx     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rphfifoursttx : dprioin_rphfifoursttx;
assign cram_rpma_doublewidth_tx = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rpma_doublewidth_tx : dprioin_rpma_doublewidth_tx;
assign cram_rpmadwidth_tx     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rpmadwidth_tx       : dprioin_rpmadwidth_tx;      
assign cram_rprbs_sel         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rprbs_sel : dprioin_rprbs_sel;
assign cram_rprbsen_tx        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rprbsen_tx : dprioin_rprbsen_tx;
assign cram_rrev_loopbk       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrev_loopbk : dprioin_rrev_loopbk;
assign cram_rrev_loopbk       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrev_loopbk : dprioin_rrev_loopbk;
assign cram_rtx_cmu_sel       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_cmu_sel : dprioin_rtx_cmu_sel;
assign cram_rtxfifo_dis       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtxfifo_dis : dprioin_rtxfifo_dis;
assign cram_rtxfifo_lowlatency_en = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtxfifo_lowlatency_en : dprioin_rtxfifo_lowlatency_en;
assign cram_rtxrdclksel       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtxrdclksel : dprioin_rtxrdclksel;
assign cram_rtxwrclksel       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtxwrclksel : dprioin_rtxwrclksel;
assign cram_rclkcmpinsertpad  = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rclkcmpinsertpad : dprioin_rclkcmpinsertpad;           // rx only 	
assign cram_rrdwidth_rx       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrdwidth_rx : dprioin_rrdwidth_rx;                     // rx only
assign cram_rrx_detect_bypass = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrx_detect_bypass : dprioin_rrx_detect_bypass;         // rx only
assign cram_rrx_pipe_enable   = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrx_pipe_enable : dprioin_rrx_pipe_enable;             // rx only
assign cram_rtx_elec_idle_delay = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_elec_idle_delay : dprioin_rtx_elec_idle_delay;   // 2 bits  rx only
assign cram_rtx_pipe_enable   = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_pipe_enable : dprioin_rtx_pipe_enable;

assign cram_is_lane0          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_is_lane0 : dprioin_is_lane0;
assign cram_scan_mode         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_scan_mode : dprioin_scan_mode;


// PMA
assign cram_r_rlpbk = (dpriodisable !== 1'b0) ? init_r_rlpbk : dprioin_r_rlpbk;

assign cram_rtx_vod_sel  = (dpriodisable !== 1'b0) ? init_rtx_vod_sel  : dprioin_rtx_vod_sel;     // 3-bits
assign cram_rtx_slewrate = (dpriodisable !== 1'b0) ? init_rtx_slewrate : dprioin_rtx_slewrate;    // 1-bit
assign cram_rpmphs_2tap  = (dpriodisable !== 1'b0) ? init_rpmphs_2tap  : dprioin_rpmphs_2tap;     // 3
assign cram_rpmphs_1tap  = (dpriodisable !== 1'b0) ? init_rpmphs_1tap  : dprioin_rpmphs_1tap;     // 4 
assign cram_rtx_vtt      = (dpriodisable !== 1'b0) ? init_rtx_vtt      : dprioin_rtx_vtt;         // 2 - to add in wys
assign cram_rpmphs_ptap  = (dpriodisable !== 1'b0) ? init_rpmphs_ptap  : dprioin_rpmphs_ptap;     // 3

assign cram_rsig_inv_2tap= (dpriodisable !== 1'b0) ? init_rsig_inv_2tap : dprioin_rsig_inv_2tap; // 1
assign cram_rsig_inv_pre = (dpriodisable !== 1'b0) ? init_rsig_inv_pre  : dprioin_rsig_inv_pre;  // 3

// dprio related to clock divider
assign cram_rtx_m_sel     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_m_sel      : dprioin_rtx_m_sel;
assign cram_rtx_cgb_1x_en = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_cgb_1x_en  : dprioin_rtx_cgb_1x_en;
assign cram_rtx_cgb_4x_en = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_cgb_4x_en  : dprioin_rtx_cgb_4x_en;
assign cram_rtx_4x_sw     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_4x_sw      : dprioin_rtx_4x_sw;

/////////////////////////////////////////////////////////////////////////////////
// Connect Atom level input to appropriate RTL  - PORT_IN_Table -------------- //
/////////////////////////////////////////////////////////////////////////////////

//anlogreset
assign  ser_reset               = (dividerpowerdn === 1'b1 || analogreset === 1'b1) ? 1'b1 : 1'b0;
assign  tcd_in_reset            = (dividerpowerdn === 1'b1 || analogreset === 1'b1) ? 1'b1 : 1'b0;

//input         analogx4fastrefclk;                     ---- used in serializer mux
//input         analogx4refclk;
//input         analogx8fastrefclk;
//input         analogx8refclk;

//coreclk
assign td_in_pld_tx_clk =         coreclk; // coreclk_in;

////////////////////////////////////////////////////////////////////////////////////////////////////
// datain TXD mapping - datain[32/40], ctrlenable[4], forcedispacompliance, forcedisp[4], dispval[4]
////////////////////////////////////////////////////////////////////////////////////////////////////
always @(ctrlenable_in)
    for (i=0; i < CTRL_IN_WIDTH; i=i+1)
    begin
        if (ctrlenable_in[i] === 1'b1)
            tmp_ctrlenable[i] = 1'b1;
        else
            tmp_ctrlenable[i] = 1'b0;
    end

always @(datain_in)
    for (i=0; i < DATA_IN_WIDTH; i=i+1)
        tmp_datain[i] = datain_in[i];

always @(dispval_in)
    for (i=0; i < CTRL_IN_WIDTH; i=i+1)
    begin
        if (dispval_in[i] === 1'b1)
            tmp_dispval[i] = 1'b1;
        else
            tmp_dispval[i] = 1'b0;
    end

always @(forcedisp_in)
    for (i=0; i < CTRL_IN_WIDTH; i=i+1)
    begin
        if (forcedisp_in[i] === 1'b1)
            tmp_forcedisp[i] = 1'b1;
        else
            tmp_forcedisp[i] = 1'b0;
    end

assign pi_in_txd_ch_tmp[7:0] = tmp_datain[7:0];
assign pi_in_txd_ch_tmp[8] = (cram_rendec_tx == 1'b1) ? tmp_ctrlenable[0] : 
                          cram_rpmadwidth_tx == 1'b1 ? tmp_datain[8] : 1'bx;
assign pi_in_txd_ch_tmp[9] = (cram_rendec_tx == 1'b1) ? (cram_rtx_pipe_enable == 1'b1 ? forcedispcompliance_in : tmp_forcedisp[0]) : 
                          cram_rpmadwidth_tx == 1'b1 ? tmp_datain[9] : 1'bx;
assign pi_in_txd_ch_tmp[10] = (cram_rendec_tx == 1'b1) ? tmp_dispval[0] : 1'bx;

assign pi_in_txd_ch_tmp[18:11] = (cram_rendec_tx == 1'b1 || cram_rpmadwidth_tx == 1'b0) ? tmp_datain[15:8] : tmp_datain[17:10];
assign pi_in_txd_ch_tmp[19] = (cram_rendec_tx == 1'b1) ? tmp_ctrlenable[1] : 
                          cram_rpmadwidth_tx == 1'b1 ? tmp_datain[18] : 1'bx;
assign pi_in_txd_ch_tmp[20] = (cram_rendec_tx == 1'b1) ? (cram_rtx_pipe_enable == 1'b1 ? forcedispcompliance_in : tmp_forcedisp[1]) : 
                          cram_rpmadwidth_tx == 1'b1 ? tmp_datain[19] : 1'bx;
assign pi_in_txd_ch_tmp[21] = (cram_rendec_tx == 1'b1) ? tmp_dispval[1] : 1'bx;

assign pi_in_txd_ch_tmp[29:22] = (cram_rendec_tx == 1'b1 || cram_rpmadwidth_tx == 1'b0) ? tmp_datain[23:16] : tmp_datain[27:20];
assign pi_in_txd_ch_tmp[30] = (cram_rendec_tx == 1'b1) ? tmp_ctrlenable[2] : 
                          cram_rpmadwidth_tx == 1'b1 ? tmp_datain[28] : 1'bx;
assign pi_in_txd_ch_tmp[31] = (cram_rendec_tx == 1'b1) ? (cram_rtx_pipe_enable == 1'b1 ? forcedispcompliance_in : tmp_forcedisp[2]) : 
                          cram_rpmadwidth_tx == 1'b1 ? tmp_datain[29] : 1'bx;
assign pi_in_txd_ch_tmp[32] = (cram_rendec_tx == 1'b1) ? tmp_dispval[2] : 1'bx;

assign pi_in_txd_ch_tmp[40:33] = (cram_rendec_tx == 1'b1 || cram_rpmadwidth_tx == 1'b0) ? tmp_datain[31:24] : tmp_datain[37:30];
assign pi_in_txd_ch_tmp[41] = (cram_rendec_tx == 1'b1) ? tmp_ctrlenable[3] : 
                          cram_rpmadwidth_tx == 1'b1 ? tmp_datain[38] : 1'bx;
assign pi_in_txd_ch_tmp[42] = (cram_rendec_tx == 1'b1) ? (cram_rtx_pipe_enable == 1'b1 ? forcedispcompliance_in : tmp_forcedisp[3]) : 
                          cram_rpmadwidth_tx == 1'b1 ? tmp_datain[39] : 1'bx;
assign pi_in_txd_ch_tmp[43] = (cram_rendec_tx == 1'b1) ? tmp_dispval[3] : 1'bx;

//interleaving
assign pi_in_txd_ch[10:0]  = pi_in_txd_ch_tmp[10:0];
assign pi_in_txd_ch[32:22] = (cram_rdwidth_tx == 1'b1 && cram_rpma_doublewidth_tx == 1'b0) ? pi_in_txd_ch_tmp[21:11] : pi_in_txd_ch_tmp[32:22];  
assign pi_in_txd_ch[21:11] = (cram_rdwidth_tx == 1'b1 && cram_rpma_doublewidth_tx == 1'b0) ? pi_in_txd_ch_tmp[32:22] : pi_in_txd_ch_tmp[21:11];  
assign pi_in_txd_ch[43:33]  = pi_in_txd_ch_tmp[43:33];

// 6.1 - dprio interface change
assign pi_in_txd_ch_dprio = ((dprio_config_mode & DPRIO_CHANNEL_INTERFACE_BIT) != 0) ? datainfull : pi_in_txd_ch;

//detectrxloop
assign pi_in_txdetectrxloopback = (detectrxloop_in === 1'b1) ? 1'b1 : 1'b0;

//detectrxpowerdn
assign rxdet_in_RX_DET_PDB = (detectrxpowerdn === 1'b1) ? 1'b0 : 1'b1 ;  // active low

//digitalreset;
assign pr_in_txpcs_rst = (digitalreset === 1'b1) ? 1'b1 : 1'b0;

// used in CRAM
//dpriodisable;
//dprioin;

//enrevparallellpbk
assign  pi_in_revloopback = (enrevparallellpbk_in === 1'b1) ? 1'b1 : 1'b0; 

//forcedispcompliance
assign pi_in_txcompliance = (forcedispcompliance_in === 1'b1) ? 1'b1 : 1'b0;

//forceelecidle;
assign pi_in_txelecidle = forceelecidle_in;

// hardreset
assign pr_in_hard_reset  = (quadreset === 1'b1) ? 1'b1 : 1'b0;

//invpol;
assign td_in_polinv_tx = (invpol_in === 1'b1) ? 1'b1 : 1'b0;

//phfiforddisable;
assign td_in_rddisable_tx = (phfiforddisable === 1'b1) ? 1'b1 : 1'b0; // enable by default

//phfiforeset;
assign td_in_phfifourst_tx = (phfiforeset === 1'b1) ? 1'b1 : 1'b0;

//phfifowrenable;
assign td_in_wrenable_tx = (phfifowrenable_in === 1'b0) ? 1'b0 : 1'b1;  // enable by default 

//phfifox4bytesel,phfifox4rdclk,phfifox4rdenable,phfifox4wrenable
assign td_in_txfifo_shared_sig_in_ch0[0] = phfifox4bytesel;
assign td_in_txfifo_shared_sig_in_ch0[1] = phfifox4rdenable;
assign td_in_txfifo_shared_sig_in_ch0[2] = phfifox4wrenable;
assign td_in_txfifo_shared_sig_in_ch0[3] = phfifox4rdclk;
        
//phfifox8bytesel,phfifox8rdclk,phfifox8rdenable,phfifox8wrenable
assign td_in_txfifo_shared_sig_in_q0_ch0[0] = phfifox8bytesel;
assign td_in_txfifo_shared_sig_in_q0_ch0[1] = phfifox8rdenable;
assign td_in_txfifo_shared_sig_in_q0_ch0[2] = phfifox8wrenable;
assign td_in_txfifo_shared_sig_in_q0_ch0[3] = phfifox8rdclk;

//pi_in_state_transition_done
assign pi_in_state_transition_done = pipestatetransdone;

//pllfastclk;
assign tcd_in_clkin0 = pllfastclk[0];                   
assign tcd_in_clkin1 = pllfastclk[1];                   


//powerdn;
assign pi_in_powerdown = powerdn_in;

//refclk
assign  td_in_refclk_pma = (channel_bonding == "x8" || channel_bonding == "x8_unbundled") ? refclk_in_delayed : refclk_in;

// reverse serial loopback    
assign  ser_rseriallpbkdatain   = revserialfdbk;               
assign  ser_rseriallpbkctrl     = cram_r_rlpbk;

//revparallelfdbk
assign  td_in_rev_loop_data = revparallelfdbk;

//xgmctrl;
assign td_in_tx_ctl_ts = xgmctrl;

//xgmdatain;
assign td_in_tx_data_ts = xgmdatain;


/////////////////////////////////////////////////////////////////////////////////
// Connect Atom level output to appropriate RTL  - PORT_OUT_Table ------------ //
/////////////////////////////////////////////////////////////////////////////////

assign clkout            = td_out_tx_clk_out;
assign dataout           = (obpowerdn === 1'b1) ? 1'b0: ser_serialdataout;
// dprioout;                                   handled in CRAM
assign parallelfdbkout   = td_out_txlp20b;
assign phfifooverflow    = td_out_full_tx;
assign phfifounderflow   = td_out_empty_tx;
assign phfifobyteselout  = td_out_txfifo_shared_sig_out[0];
assign phfifordclkout    = td_out_txfifo_shared_sig_out[3];
assign phfifordenableout = td_out_txfifo_shared_sig_out[1];
assign phfifowrenableout = td_out_txfifo_shared_sig_out[2];

assign pipepowerdownout = powerdn_in;
assign pipepowerstateout = pi_out_powerstate[3:0];
assign rdenablesync      = td_out_rd_enable_sync;
assign refclkout         = ser_clkout;
assign rxfoundout[0]     = rxdet_out_RX_FOUND;
assign rxfoundout[1]     = pi_out_txdetectrx;
assign rxdetectvalidout  = rxdet_out_RX_DET_VALID; 
assign serialfdbkout     = ser_seriallpbkdataout;
assign xgmctrlenable     = td_out_tx_ctl_tc;
assign xgmdataout        = td_out_tx_data_tc;

/////////////////////////////////////////////////////////////////////////////////
// transmitter sub-block instantiation: channel_clk_div ---------------------- //
/////////////////////////////////////////////////////////////////////////////////

assign tcd_in_dpriodisable  = (dpriodisable === 1'b0) ? 1'b0 : 1'b1; // from TOP
assign tcd_in_dprioin       = {5'h00, cram_rtx_cmu_sel,cram_rpmadwidth_tx,cram_rpma_doublewidth_tx,cram_rtx_m_sel};

// tcd_in_clkin0 = pllfastclk[0];                              // from top atom
// tcd_in_clkin1 = pllfastclk[1];                              // from top atom
// tcd_in_reset  = dividerpowerdn | analogreset;               // from top atom

arriagx_hssi_tx_channel_clk_div m_tcd(
    .dpriodisable   (tcd_in_dpriodisable),
    .dprioin        (tcd_in_dprioin),
    .clkin0  (tcd_in_clkin0),
    .clkin1  (tcd_in_clkin1),
    .reset   (tcd_in_reset),
    .vcobypassin (vcobypassin),
    .lclkout (tcd_out_lclkout),
    .fclkout (tcd_out_fclkout) 
);

defparam m_tcd.clkin0_select = divider_refclk_select_pll_fast_clk0; 
defparam m_tcd.clk_divide_by_n = refclk_divide_by;         // n=1,2,4
defparam m_tcd.clk_divide_by_m = tcd_para_clk_divide_by_m; // m=4,5
defparam m_tcd.clk_divide_by_2_select = tcd_para_clk_divide_by_2_select;
defparam m_tcd.allow_vco_bypass = allow_vco_bypass;
defparam m_tcd.lclkout_latency = 0;
defparam m_tcd.fclkout_latency = 0;
defparam m_tcd.lclkout_phase_shift = 0;
defparam m_tcd.fclkout_phase_shift = 0; 

/////////////////////////////////////////////////////////////////////////////////
// tx sub-block instantiation: rx_det -----------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

// assign rxdet_in_RX_DET_PDB = ~detectrxpowerdn; 
assign rxdet_in_TX_DET_RX = pi_out_txdetectrx;

// 125Mhz clock
assign rxdet_in_CLK15M = rxdet_fixclk_reg; 
initial 
begin
    rxdet_fixclk_reg = 1'b0;
    forever
    begin
        #4000 rxdet_fixclk_reg = ~rxdet_fixclk_reg;
    end
end

arriagx_hssi_tx_rx_det m_rxdet(
    .RX_DET_PDB    (rxdet_in_RX_DET_PDB), 
	.CLK15M        (rxdet_in_CLK15M), 
	.TX_DET_RX     (rxdet_in_TX_DET_RX), 
	.RX_FOUND      (rxdet_out_RX_FOUND),
	.RX_DET_VALID  (rxdet_out_RX_DET_VALID)
);

/////////////////////////////////////////////////////////////////////////////////
// tx sub-block instantiation: tx_ser -----------------------------------------//
/////////////////////////////////////////////////////////////////////////////////
assign  ser_serialclk = (cram_rtx_cgb_1x_en == 1'b1) ? tcd_out_fclkout :
                        (cram_rtx_cgb_4x_en  == 1'b1)? analogx4fastrefclk :
                        (cram_rtx_4x_sw  == 1'b1)    ? analogx8fastrefclk : 1'bx;

assign  ser_parallelclk = (cram_rtx_cgb_1x_en == 1'b1) ? tcd_out_lclkout :
                          (cram_rtx_cgb_4x_en  == 1'b1) ? analogx4refclk :
                          (cram_rtx_4x_sw  == 1'b1) ? analogx8refclk : 1'bx;

assign  ser_datain                = td_out_pudr;
//assign  ser_reset               = analogreset;                 // connected in top
assign  ser_elecreset             = (pi_out_tx_elec_idle === 1'b1) ? 1'b1 : 1'b0;
//assign  ser_rseriallpbkdatain   = revserialfdbk;               // connected in top
//assign  ser_rseriallpbkctrl     = cram_r_rlpbk;       // connected in top
assign  ser_rdwidth               = cram_rpmadwidth_tx;          // 0 => 8-bit, 1 => 10-bit
assign  ser_rdoublewidth          = cram_rpma_doublewidth_tx;    // 0 => 8/10,  1 => 16/20

arriagx_hssi_tx_ser m_tx_ser
(
    .serialclk             (ser_serialclk),
    .parallelclk           (ser_parallelclk),
    .datain                (ser_datain),
    .reset                 (ser_reset),
	.elecreset             (ser_elecreset),
    .rseriallpbkdatain     (ser_rseriallpbkdatain),
    .rseriallpbkctrl       (ser_rseriallpbkctrl),
    .rdwidth               (ser_rdwidth),
    .rdoublewidth          (ser_rdoublewidth),
    .serialdataout         (ser_serialdataout),
    .seriallpbkdataout     (ser_seriallpbkdataout),
    .clkout                (ser_clkout)
);


/////////////////////////////////////////////////////////////////////////////////
// tx sub-block instantiation: pcs_reset --------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

// assign pr_in_hard_reset  = (quadreset == 1'b1) ? quadreset : 1'b0; // from top
assign pr_in_clk_2_b     = 1'b0;                                     // for rx side 
assign pr_in_refclk_b_in = td_out_refclk_b;
assign pr_in_scan_mode   = 1'b0;
assign pr_in_rxpcs_rst   = 1'b0;                                     // for rx side

assign pr_out_rxrst_int = 1'b0;                                  // to filter out x

arriagx_hssi_pcs_reset  tx_pcs_reset_1 (
    .hard_reset(pr_in_hard_reset), 
    .clk_2_b(pr_in_clk_2_b), 
    .refclk_b_in(pr_in_refclk_b_in),
    .scan_mode(pr_in_scan_mode),
    .rxpcs_rst(pr_in_rxpcs_rst), 
    .txpcs_rst(pr_in_txpcs_rst),
    .rxrst_int(), 
    .txrst_int(pr_out_txrst_int)
);


/////////////////////////////////////////////////////////////////////////////////
// tx sub-block instantiation: pipe_interface ---------------------------------//
/////////////////////////////////////////////////////////////////////////////////

// assign  pi_in_pipe_tx_clk      = td_out_tx_pipe_clk; 
   assign  pi_in_pipe_tx_clk      = (cram_rtx_pipe_enable === 1'b0) ? 1'b0 : td_out_tx_pipe_clk; 
// assign  pi_in_powerdown        = powerdn;              // already connected in top
// assign  pi_in_refclk_b         = td_out_refclk_b;
   assign  pi_in_refclk_b         = (cram_rtx_pipe_enable === 1'b0) ? 1'b0 : td_out_refclk_b;
   assign  pi_in_refclk_b_reset_n = ~pr_out_txrst_int;    // new in ww29
// assign  pi_in_revloopback      = 1'b0;                    // already connected in top
   assign  pi_in_tx_elec_idle_comp = td_out_tx_pipe_electidle;
   assign  pi_in_tx_pipe_reset_n  = ~td_out_tx_pipe_soft_reset;
// assign  pi_in_txcompliance     = forcedispcompliance;   // from top atom
// assign  [43:0] pi_in_txd_ch    = ;                     // from top atom
// assign pi_in_txdetectrxloopback = detectrxloop;     // from top atom
// assign  pi_in_txelecidle       = forceelecidle;           // from top atom
// assign  pi_in_state_transition_done = pipetranstatedone; // from top atom

arriagx_hssi_tx_pipe_interface tx_pipe_interface_inst (
	.clk							(pi_in_pipe_tx_clk),
	.refclk_b						(pi_in_refclk_b),
	.refclk_b_reset_n			    (pi_in_refclk_b_reset_n),  // new in ww29
	.reset_n						(pi_in_tx_pipe_reset_n),
	.rtx_pipe_enable				(cram_rtx_pipe_enable),
	.rtx_elec_idle_delay			(cram_rtx_elec_idle_delay),
	.txdetectrxloopback				(pi_in_txdetectrxloopback),
	.txelecidle					    (pi_in_txelecidle),
	.txcompliance					(pi_in_txcompliance),
	.powerdown					    (pi_in_powerdown),
	.txd_ch						    (pi_in_txd_ch_dprio),
	.revloopback					(pi_in_revloopback),
	.txd							(pi_out_txd),
	.rev_loopbk					    (pi_out_rev_loopbk),
	.tx_elec_idle_comp				(pi_in_tx_elec_idle_comp),
	.tx_elec_idle					(pi_out_tx_elec_idle),
	.txdetectrx					    (pi_out_txdetectrx),
	.txbeacon						(pi_out_txbeacon),
	.powerstate					    (pi_out_powerstate)
);


/////////////////////////////////////////////////////////////////////////////////
// tx sub-block instantiation: tx_digi ----------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

// assign td_in_phfifourst_tx  = phfiforeset;                    // from top atom
// assign td_in_pld_tx_clk     = coreclk;                        // from top atom
// assign td_in_polinv_tx      = invpol;                         // from top atom
// assign td_in_rddisable_tx   = phfiforddisable;                // from top atom
// assign td_in_refclk_pma     = 1'b0;                           // from top atom
// assign td_in_rev_loop_data  = 'b0;                            // from top atom
   assign td_in_rev_loopbk     = pi_out_rev_loopbk;              
// assign td_in_tx_data_ts     = xgmdatain;                     // from top atom
// assign td_in_tx_ctl_ts      = xgmctrl;                       // from top atom
   assign td_in_txd            = pi_out_txd;                    // 44 bit
// assign td_in_txfifo_shared_sig_in_ch0 = 'b0;                 // from top atom
// assign td_in_txfifo_shared_sig_in_q0_ch0 = 'b0;              // from top atom
   assign td_in_txpcs_rst      = pr_out_txrst_int;
   assign td_in_txpma_local_clk= ser_clkout;                     // from serializer
// assign td_in_wrenable_tx    = phfifowrenable;                 // from top atom


arriagx_hssi_tx_digi digi_tx_1 (
	.empty_tx                        (td_out_empty_tx),
	.encoder_testbus                 (td_out_encoder_testbus),
	.full_tx                         (td_out_full_tx),
	.phfifourst_tx                   (td_in_phfifourst_tx),
	.pld_tx_clk                      (td_in_pld_tx_clk),
	.polinv_tx                       (td_in_polinv_tx),
	.pudr                            (td_out_pudr),
	.r8b10b_enc_ibm_en               (cram_r8b10b_enc_ibm_en),
	.rbist_sel                       (cram_rbist_sel),
	.rbisten_tx                      (cram_rbisten_tx),
	.rcascaded_8b10b_en_tx           (cram_rcascaded_8b10b_en_tx),
	.rcxpat_chnl_en                  (cram_rcxpat_chnl_en),
	.rd_enable_sync                  (td_out_rd_enable_sync),
	.rddisable_tx                    (td_in_rddisable_tx),
	.rdwidth_tx                      (cram_rdwidth_tx),
	.refclk_b                        (td_out_refclk_b),
	.refclk_pma                      (td_in_refclk_pma),
	.renbitrev_tx                    (cram_renbitrev_tx),
	.rendec_data_sel_tx              (cram_rendec_data_sel_tx),
	.rendec_tx                       (cram_rendec_tx),
	.renpolinv_tx                    (cram_renpolinv_tx),
	.rensymswap_tx                   (cram_rensymswap_tx),
	.rev_loop_data                   (td_in_rev_loop_data),
	.rev_loopbk                      (td_in_rev_loopbk),
	.rforce_disp                     (cram_rforce_disp),
	.rforce_echar                    (cram_rforce_echar),
	.rforce_kchar                    (cram_rforce_kchar),
	.rfreerun_tx                     (cram_rfreerun_tx),
	.rge_xaui_tx                     (cram_rge_xaui_tx),
	.rib_force_disp                  (cram_rib_force_disp),
	.rindv_tx                        (cram_rindv_tx),
	.rphfifo_master_sel_tx           (cram_rphfifo_master_sel_tx),
	.rphfifopldentx                  (cram_rphfifopldentx),
	.rphfifoursttx                   (cram_rphfifoursttx),
	.rpma_doublewidth_tx             (cram_rpma_doublewidth_tx),
	.rpmadwidth_tx                   (cram_rpmadwidth_tx),
	.rprbs_sel                       (cram_rprbs_sel),
	.rprbsen_tx                      (cram_rprbsen_tx),
	.rrev_loopbk                     (cram_rrev_loopbk),
	.rtx_pipe_enable                 (cram_rtx_pipe_enable),
	.rtxfifo_dis                     (cram_rtxfifo_dis),
	.rtxfifo_lowlatency_en           (cram_rtxfifo_lowlatency_en),
	.rtxrdclksel                     (cram_rtxrdclksel),
	.rtxwrclksel                     (cram_rtxwrclksel),
	.scan_mode                       (cram_scan_mode),
	.tx_clk_out                      (td_out_tx_clk_out),
	.tx_ctl_tc                       (td_out_tx_ctl_tc),
	.tx_ctl_ts                       (td_in_tx_ctl_ts),
	.tx_ctrl_testbus                 (td_out_tx_ctrl_testbus),
	.tx_data_tc                      (td_out_tx_data_tc),
	.tx_data_ts                      (td_in_tx_data_ts),
	.tx_pipe_clk                     (td_out_tx_pipe_clk),
	.tx_pipe_electidle               (td_out_tx_pipe_electidle),
	.tx_pipe_soft_reset              (td_out_tx_pipe_soft_reset),
	.txd                             (td_in_txd),
	.txfifo_shared_sig_in_ch0        (td_in_txfifo_shared_sig_in_ch0),
	.txfifo_shared_sig_in_q0_ch0     (td_in_txfifo_shared_sig_in_q0_ch0),
	.txfifo_shared_sig_out           (td_out_txfifo_shared_sig_out),
	.txlp20b                         (td_out_txlp20b),
	.txpcs_rst                       (td_in_txpcs_rst),
	.txpma_local_clk                 (td_in_txpma_local_clk),
	.wrenable_tx                     (td_in_wrenable_tx)
);

endmodule // arriagx_hssi_transmitter 


`timescale 1 ps / 1 ps
module arriagx_hssi_rx_cdr (
    cruclk,
    dpriodisable,
    dprioin,
    freqlock,
    ltd,
    ltr,
    pdb,
    reset,
    rxin,
    clklow,
    dprioout,
    fref,
    freqlocked,
    phaselockloss, 
    revserialfdbk,
    serialclkout,
    signaldetect
);

parameter cru_clock_select               = 0;           //  <CRUCLK<n> where n is 0 through 7 >
parameter cru_divide_by                  = 1;           // <1,2,4>;
parameter cru_multiply_by                = 10;          // <1,2,4,5,8,10,16,20,25>;
parameter cru_pre_divide_by              = 1;           // <1,2,4,8>;
parameter cruclk0_period                 = 10000;       //  in ps
parameter cruclk1_period                 = 10000;       //  in ps
parameter cruclk2_period                 = 10000;       //  in ps
parameter cruclk3_period                 = 10000;       //  in ps
parameter cruclk4_period                 = 10000;       //  in ps
parameter cruclk5_period                 = 10000;       //  in ps
parameter cruclk6_period                 = 10000;       //  in ps
parameter cruclk7_period                 = 10000;       //  in ps
parameter force_signal_detect            = "false";     // RFORCE_SIGDET
parameter ignore_lock_detect             = "false";
parameter signal_detect_threshhold       = 0;
parameter send_direct_reverse_serial_loopback = "false";
parameter force_freq_det_high = "false";
parameter force_freq_det_low  = "false";

parameter sim_rxpll_clkout_phase_shift = 0;
parameter sim_rxpll_clkout_latency = 0;

parameter dprio_config_mode = 0;


input [8:0]  cruclk;
input        dpriodisable;
input [19:0] dprioin;
input        freqlock;     // from RD_
input        ltd;
input        ltr;
input        pdb;
input        reset;
input        rxin;

output        clklow;
output [19:0] dprioout;
output        fref;
output        freqlocked;    // to the top
output        phaselockloss; // !rxpll_phaselock,
output        revserialfdbk;
output        serialclkout;
output        signaldetect;

wire         refclk;
wire         predivided_clk;

wire [39:0]  rxpll_dprioin;
wire [7:0]   rxpllrefclk;
wire         rxpll_sclkout;
wire         rxpll_dpriodisable;

wire         rxpll_lock;
wire         rxpll_phaselock;

// freqlock
wire         mrxpll_not_locked;
reg          mfreqlocked_reg;
reg [3:0]    mfreqlocked_cnt;

reg          signal_detect_reg;
wire         signal_detect_reg_n;

// begin_dprio 
wire [1:0]   cram_rrx_cru_m_sel; // dprio_rtl
wire         cram_rrx_cru_div2;  // dprio_rtl
wire [3:0]   cram_cru_clock_select;

wire [3:0]   cram_rrx_cru_m;
wire [1:0]   cram_rrx_cru_l;
wire [7:0]   rxpll_m, rxpll_2m;  // representing actual m value
wire [7:0]   rxpll_l;

wire         nondprio_predivided_clk;
wire         dprio_predivided_clk;

wire         dprioout_predivided_clk_by1;
wire         dprioout_predivided_clk_by2;
wire         dprioout_predivided_clk_by4;
wire         dprioout_predivided_clk_by8;

assign cram_rrx_cru_m_sel = dprioin[1:0];
assign cram_rrx_cru_div2  = dprioin[2];
assign cram_rrx_cru_m     = dprioin[6:3];
assign cram_rrx_cru_l     = dprioin[8:7];
assign cram_cru_clock_select = dprioin[12:9];

assign rxpll_m = (cram_rrx_cru_m === 4'b0000) ? 8'd01 :
                 (cram_rrx_cru_m === 4'b0010) ? 8'd04 :
                 (cram_rrx_cru_m === 4'b0011) ? 8'd05 :
                 (cram_rrx_cru_m === 4'b0100) ? 8'd08 :
                 (cram_rrx_cru_m === 4'b0101) ? 8'd10 :
                 (cram_rrx_cru_m === 4'b0110) ? 8'd16 :
                 (cram_rrx_cru_m === 4'b0111) ? 8'd20 :
                 (cram_rrx_cru_m === 4'b1000) ? 8'd25 : 8'd01;
assign rxpll_l = (cram_rrx_cru_l === 2'b00)   ? 8'd01 :
                 (cram_rrx_cru_l === 2'b01)   ? 8'd02 :
                 (cram_rrx_cru_l === 2'b10)   ? 8'd04 : 8'd01;
assign rxpll_2m = 2 * rxpll_m;  // DES at rising edge only


assign dprio_predivided_clk = (cram_rrx_cru_div2 === 1'b1) ? dprioout_predivided_clk_by8 :
                              (cram_rrx_cru_m_sel === 2'b10) ? dprioout_predivided_clk_by4 :
                              (cram_rrx_cru_m_sel === 2'b01) ? dprioout_predivided_clk_by2 :
                              dprioout_predivided_clk_by1;
                              
assign predivided_clk = (dpriodisable !== 1'b0) ? nondprio_predivided_clk : dprio_predivided_clk;
                        
// end_dprio

// Connect primary outputs

assign revserialfdbk = (pdb === 1'b1) ? 1'bz : rxin;
assign freqlocked    = (force_freq_det_high == "true") ? 1'b1 :
                       (force_freq_det_low  == "true") ? 1'b0 : mfreqlocked_reg;
assign phaselockloss = rxpll_phaselock;
assign fref          = predivided_clk;
assign dprioout      = 'b0;
assign serialclkout  = rxpll_sclkout;
assign signaldetect = (force_signal_detect === "true") ? 1'b1 : signal_detect_reg;

// PRE-DIVIDER

assign refclk = (cram_cru_clock_select <= 8) ? cruclk[cram_cru_clock_select] : cruclk[0];

arriagx_hssi_aux_clock_div m_predivider (
    .clk(refclk),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(nondprio_predivided_clk)
);
defparam m_predivider.clk_divide_by = cru_pre_divide_by;   // included DIV2
defparam m_predivider.extra_latency = 0;

arriagx_hssi_aux_clock_div m_predivider_1 (
    .clk(refclk),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprioout_predivided_clk_by1)
);
defparam m_predivider_1.clk_divide_by = 1;   // included DIV2
defparam m_predivider_1.extra_latency = 0;

arriagx_hssi_aux_clock_div m_predivider_2 (
    .clk(refclk),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprioout_predivided_clk_by2)
);
defparam m_predivider_2.clk_divide_by = 2;   // included DIV2
defparam m_predivider_2.extra_latency = 0;

arriagx_hssi_aux_clock_div m_predivider_4 (
    .clk(refclk),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprioout_predivided_clk_by4)
);
defparam m_predivider_4.clk_divide_by = 4;   // included DIV2
defparam m_predivider_4.extra_latency = 0;

arriagx_hssi_aux_clock_div m_predivider_8 (
    .clk(refclk),
    .reset(reset),
    .enable_d (1'b0),     // enable dprio
    .d        (8'h00),    // dprio
    .clkout(dprioout_predivided_clk_by8)
);
defparam m_predivider_8.clk_divide_by = 8;   // included DIV2
defparam m_predivider_8.extra_latency = 0;

// RX PLL

assign rxpllrefclk[0]     = predivided_clk;
assign rxpllrefclk[1]     = predivided_clk;
assign rxpllrefclk[2]     = predivided_clk;
assign rxpllrefclk[3]     = predivided_clk;
assign rxpllrefclk[4]     = predivided_clk;
assign rxpllrefclk[5]     = predivided_clk;
assign rxpllrefclk[6]     = predivided_clk;
assign rxpllrefclk[7]     = predivided_clk;
//assign rxpll_dprioin      = {24'h000, rxpll_l, rxpll_2m};
assign rxpll_dprioin      = {19'h000, cram_cru_clock_select[2:0], 2'b00, rxpll_l, rxpll_2m};
assign rxpll_dpriodisable = (dprio_config_mode <= 1) ? 1'b1 : dpriodisable;

arriagx_hssi_cmu_pll m_rxpll (
                                   .clk          (rxpllrefclk),
                                   .dprioin      (rxpll_dprioin),
                                   .dpriodisable (rxpll_dpriodisable),
                                   .pllreset     (reset),
                                   .pllpowerdn   (pdb),
                                   .clkout       (rxpll_sclkout),
                                   .locked       (rxpll_phaselock),
                                   .dprioout(),
                                   .vcobypassout(),
								   .fbclkout     (clklow)
);
defparam m_rxpll.pfd_clk_select = cru_clock_select;   // 0;
defparam m_rxpll.inclk0_period  = cruclk0_period * cru_pre_divide_by;
defparam m_rxpll.inclk1_period  = cruclk1_period * cru_pre_divide_by;
defparam m_rxpll.inclk2_period  = cruclk2_period * cru_pre_divide_by;
defparam m_rxpll.inclk3_period  = cruclk3_period * cru_pre_divide_by;
defparam m_rxpll.inclk4_period  = cruclk4_period * cru_pre_divide_by;
defparam m_rxpll.inclk5_period  = cruclk5_period * cru_pre_divide_by;
defparam m_rxpll.inclk6_period  = cruclk6_period * cru_pre_divide_by;
defparam m_rxpll.inclk7_period  = cruclk7_period * cru_pre_divide_by;
defparam m_rxpll.multiply_by    = 2*cru_multiply_by; // DES uses rising edge clk
defparam m_rxpll.divide_by      = cru_divide_by;

defparam m_rxpll.dprio_config_mode = 6'b010000;      // cmu_pll_reconfig

defparam m_rxpll.sim_clkout_phase_shift  = sim_rxpll_clkout_phase_shift;
defparam m_rxpll.sim_clkout_latency  = sim_rxpll_clkout_latency;

// internal signal
assign rxpll_lock = (ignore_lock_detect == "true") ? signal_detect_reg : (rxpll_phaselock & signal_detect_reg);  

initial begin
        signal_detect_reg = 1'b0;
end

always @ (reset or rxin)
begin
    if (reset === 1'b1)
        signal_detect_reg <= 1'b0;
    else if (rxin === 1'b0 || rxin === 1'b1)
        signal_detect_reg <= 1'b1;
    else
        signal_detect_reg <= 1'b0;    
end

// simplified freqlock behavior:
//  (1). Responding to rising edge of rxpll_lock with small counter;
//  (2). Responding to analogreset
//  (3). Not responding to loss of rxpll_lock

assign mrxpll_not_locked = (rxpll_phaselock === 1'b1) ? 1'b0 : 1'b1;
assign signal_detect_reg_n = ~signal_detect_reg;

initial
begin
    mfreqlocked_reg = 1'b0;
    mfreqlocked_cnt = 4'b000;
end

always @ (posedge predivided_clk or posedge reset)
begin
    if (reset === 1'b1)
        mfreqlocked_reg <= 1'b0;
    else if (mfreqlocked_cnt === 4'b1111)
        mfreqlocked_reg <= 1'b1;
    else
        mfreqlocked_reg <= 1'b0;    
end

always @ (posedge predivided_clk or posedge mrxpll_not_locked or posedge signal_detect_reg_n)
begin
    if (mrxpll_not_locked === 1'b1 || signal_detect_reg_n === 1'b1)
        mfreqlocked_cnt <= 4'b0000;
    else if (mfreqlocked_cnt !== 4'b1111)
        mfreqlocked_cnt <= mfreqlocked_cnt + 4'b0001;
end

endmodule

`timescale 1 ps / 1 ps
module arriagx_hssi_rx_des (
    datain,
    rdoublewidth,
    rdwidth,
    reset,
    serialclk,
    serialfdbken,
    serialfdbkin,
             
    paralleldataout,    
    recvclkout
);

input         datain;
input         rdoublewidth;   // 1 = double pma
input         rdwidth;        // 1 = 10-bit, 0 = 8-bit
input         reset;
input         serialclk;
input         serialfdbken;
input         serialfdbkin;

output        recvclkout;
output [19:0] paralleldataout;    

reg           srcvd_clk;  
reg [19:0]    shift_reg;       // shift register buffer
wire          RXD;

wire          RCLK_PMA_int;  // recovered clk from DES
reg [9:0]     clk_shift_10b; // serial clk counter to generate rcvd clk
reg [9:0]     clk_shift_8b;

reg [9:0]     PUDI;

/////////////////////////////////////////////////////////////////////////
// Byte DES -----------------------------------------------------------//
/////////////////////////////////////////////////////////////////////////

reg           RCLK_PMA_int_sync;   // delayed by serialclk
reg           RCLK_PMA_int_sync1;  // recovered clk from DES
wire          RCLK_PMA_phi;  // delayed by 2 serial clk cycles of pma_clk
reg [9:0]     ddoutB;
reg [9:0]     ddoutA;
reg [9:0]     ddoutA_pre;
wire          ddclk_out;
reg           ddclk_by2;
wire          neg_ddclk_by2;
wire          pre_reg_clk;

initial srcvd_clk = 1'bz;
//assign #11 srcvd_clk = serialclk;
always @(serialclk)
    #11 srcvd_clk = serialclk;

assign RXD = (serialfdbken === 1'b1) ? serialfdbkin : datain;

initial begin
        clk_shift_10b      = {10'b0000111110};
        clk_shift_8b       = {10'b0000011110};
        ddclk_by2          = 1'b1;    // matching reset
end

// 10-bit shift register for received data - rising edge only
always @ (posedge reset or posedge srcvd_clk)
begin
    if (reset === 1'b1)
       begin
           shift_reg[19:10] <= #1 10'd0;
       end
    else
       begin // avoid X propagation at gate-level netlist
          if (RXD===1'b0 || RXD===1'b1)
              shift_reg[19]    <= #1 RXD;          // First goint to lower index
          else
              shift_reg[19]    <= #1 1'b0;
             	 
          shift_reg[18:10] <= #1 shift_reg[19:11];  // Pushing down to lower index
       end
end

/////////////////////////////////////////////////////////////////////
//  WORD boundary = loading time = 1 bit latency after reset ------//
/////////////////////////////////////////////////////////////////////

// 10-bit shift register for rcvd_clk 
always @ (posedge reset or posedge srcvd_clk)
begin
    if (reset === 1'b1)
        clk_shift_10b      <= {10'b0000111110};
    else     
        clk_shift_10b[9:0] <= {clk_shift_10b[0], clk_shift_10b[9:1]};
end

always @ (posedge reset or posedge srcvd_clk)
begin
    if (reset === 1'b1)
        clk_shift_8b      <= {10'b0000011110};
    else
        clk_shift_8b[7:0] <= {clk_shift_8b[0], clk_shift_8b[7:1]};
end

// Recovered clk from DES
assign RCLK_PMA_int = (rdwidth===1'b1) ? clk_shift_10b[0]: clk_shift_8b[0];

// 1 pclock latency
always @ (posedge reset or posedge RCLK_PMA_int)
begin
    if (reset === 1'b1)
        shift_reg[9:0]   <= #1 10'd0;
    else
        shift_reg[9:0]   <= #1 shift_reg[19:10];
end

// 2nd pclock latency
always @ (posedge reset or posedge RCLK_PMA_int)
begin
    if (reset === 1'b1)
        PUDI <= 10'd0;
    else
        PUDI <= shift_reg[9:0];
end

/////////////////////////////////////////////////////////////////////////
// Byte DES -----------------------------------------------------------//
/////////////////////////////////////////////////////////////////////////

assign RCLK_PMA_phi = RCLK_PMA_int_sync;

/////////////////////////////////////////////////////////////////////////
// double pma width: --------------------------------------------------//
//          1). same word boundary as 8/10 = 1 bit after reset         //
//          2). rcvd clkout is sent with 1 + 2 serial bit = 3 latency  //
/////////////////////////////////////////////////////////////////////////

// 2 serial bit latency
always @ (posedge reset or posedge srcvd_clk)
begin
    if (reset === 1'b1)
        begin
            RCLK_PMA_int_sync1 <= 1'b0;
            RCLK_PMA_int_sync  <= 1'b0;
        end
    else
        begin
            RCLK_PMA_int_sync1 <= RCLK_PMA_int;
            RCLK_PMA_int_sync  <= RCLK_PMA_int_sync1;
        end
end


/////////////////////////////////////////////////////////////////////////
// double pma width and pam width is 8 bit: ---------------------------//
//                                                                     //
//          walign_datain = {PUDI[17:10], PUDI[7:0]}                   //
/////////////////////////////////////////////////////////////////////////

assign paralleldataout = {ddoutB, ddoutA};
assign recvclkout      = ddclk_out;

assign ddclk_out = (rdoublewidth == 1'b1) ? ddclk_by2 : RCLK_PMA_int;

always @ (posedge reset or posedge ddclk_out)
begin
    if (reset === 1'b1 || rdoublewidth == 1'b0)
        ddoutB <= 'b0;
    else if (ddclk_out)
        ddoutB <= PUDI;
end

always @ (posedge reset or posedge ddclk_out)
begin
    if (reset === 1'b1)
        ddoutA <= 'b0;
    else if (ddclk_out)
        ddoutA <= ddoutA_pre;  // ddoutA_pre is negedge sampled
end

always @ (posedge reset or posedge RCLK_PMA_phi)
begin
    if (reset === 1'b1)
        ddclk_by2 <= 1'b1;    // on purpose
    else if (RCLK_PMA_phi)
        ddclk_by2 <= ~ddclk_by2;
end

assign neg_ddclk_by2 = ~ddclk_by2;
assign pre_reg_clk   = (rdoublewidth == 1'b1) ? neg_ddclk_by2 : RCLK_PMA_phi;

always @ (posedge reset or posedge pre_reg_clk)
begin
    if (reset === 1'b1)
        ddoutA_pre <= 'b0;
    else if (pre_reg_clk)
        ddoutA_pre <= PUDI;
end


endmodule

/////////////////////////////////////////////////////////////////////////////////
// hssi_module: receiver ******************************************************//
/////////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////
// DPRIO INDEX TABLE --------------------------------------------------------//
///////////////////////////////////////////////////////////////////////////////
// page 8 - as POF used rclk_2 long ago
// both rx and tx
//assign  pcs_ctrl8_ch0_ext = {rfreerun_tx[0], rtxwrclksel[0], rtxrdclksel[0],
//801d-8020                  rfreerun_rx[0], rrcvd_clk_sel_ch0, 
//                           rclk_1_sel_ch0, rclk_2_sel_ch0, rrx_rd_clk_sel[0], 
//                           renumber_ch0, renpolinv_rx[0], rclkcmpinsertpad[0]};

`define rfreerun_rx_RX_IDX       0    
`define rrx_rd_clk_sel_RX_IDX    1    
`define renumber_RX_IDX_0        2    
`define renumber_RX_IDX_1        3    
`define renumber_RX_IDX_2        4    
`define renpolinv_rx_RX_IDX      5    
`define rclkcmpinsertpad_RX_IDX  6  
  
`define rclk_1_sel_RX_IDX_0      7
`define rclk_1_sel_RX_IDX_1      8
`define rclk_2_sel_RX_IDX_0      9
`define rclk_2_sel_RX_IDX_1     10
`define rrcvd_clk_sel_RX_IDX_0  11
`define rrcvd_clk_sel_RX_IDX_1  12

// pma_ctrl6_ch0_ext = {rrefclk_sel_ch0, rbwctral_rx_ch0, rrx_cru_m_sel_ch0, 
// 8074h                rrx_cru_div2[0], rrx_cru_ctl_ch0, rltr[0], rltd[0]};
`define rrx_cru_m_sel_RX_IDX_0  13
`define rrx_cru_m_sel_RX_IDX_1  14
`define rrx_cru_div2_RX_IDX     15
`define rltr_RX_IDX             16
`define rltd_RX_IDX             17

// pma_ctrl7_ch0_ext = {risel_rx_ch0, riupsel_rx_ch0, ridnsel_rx_ch0,
// 8078h               rtesten_cp_rx[0], rtristate_cp_rx[0], rtestupen_cp_rx[0],
//                     rtestdnen_cp_rx[0], rrx_cru_m_ch0, rrx_cru_l_ch0};
// last two from pma_ctrl4 documented in tx side
// pma_ctrl7_ch0_ext = {risel_rx_ch0, riupsel_rx_ch0, ridnsel_rx_ch0,
// 8078h               rtesten_cp_rx[0], rtristate_cp_rx[0], rtestupen_cp_rx[0],
//                     rtestdnen_cp_rx[0], rrx_cru_m_ch0, rrx_cru_l_ch0};
// last two from pma_ctrl4 documented in tx side
`define rrx_cru_m_RX_IDX_0      18
`define rrx_cru_m_RX_IDX_1      19
`define rrx_cru_m_RX_IDX_2      20
`define rrx_cru_m_RX_IDX_3      21
`define rrx_cru_l_RX_IDX_0      22
`define rrx_cru_l_RX_IDX_1      23
`define rpmadwidth_rx_RX_IDX    24
`define rpma_doublewidth_rx_RX_IDX 25

// next 32 indices are used for RX_PMA prior to 6.1 for backward compatibility
// RX_PMA_ST =                     26
// RX_PMA_ED =                     58

// PMA_2
//assign  pma_ctrl2_ch0_ext = {rtx_term_ch0, r_tx_det_rx_ch0, rrx_term_ch0, rforce_sigdet[0],
//                             rrx_dc_couple[0], rrx_eq_dc_ch0, rrx_vtt_ch0, rrx_sloslv_ch0};
`define rtx_term_RX_IDX_0       26
`define rtx_term_RX_IDX_1       27
`define r_tx_det_rx_RX_IDX_0    28
`define r_tx_det_rx_RX_IDX_1    29
`define rrx_term_RX_IDX_0       30
`define rrx_term_RX_IDX_1       31
`define rforce_sigdet_RX_IDX    32
`define rrx_dc_couple_RX_IDX    33
`define rrx_eq_dc_RX_IDX_0      34
`define rrx_eq_dc_RX_IDX_1      35
`define rrx_vtt_RX_IDX_0        36
`define rrx_vtt_RX_IDX_2        38
`define rrx_sloslv_RX_IDX_0     39
`define rrx_sloslv_RX_IDX_2     41

// PMA_3                             
//assign  pma_ctrl3_ch0_ext = {reqa_ct_ch0, reqb_ct_ch0, reqc_ct_ch0, reqd_ct_ch0, req_ctv_ch0, 1'b0};
`define reqa_ct_RX_IDX_0        42
`define reqa_ct_RX_IDX_2        44
`define reqb_ct_RX_IDX_0        45
`define reqb_ct_RX_IDX_2        47
`define reqc_ct_RX_IDX_0        48
`define reqc_ct_RX_IDX_2        50
`define reqd_ct_RX_IDX_0        51
`define reqd_ct_RX_IDX_2        53
`define req_ctv_RX_IDX_0        54
`define req_ctv_RX_IDX_2        56


// rx - 4
//assign  trunking_mode_ext = {1'b0, rphfifo_master_sel_tx, rphfifo_master_sel_rx, 
// 8000h same for all ch       rendec_data_sel_tx, rendec_data_sel_rx, rnenbpin, rpllurst, 
//                             rreset, rrsvd_cmu, rdeskewen, rindv_tx, rindv_rx};
`define rphfifo_master_sel_rx_RX_IDX    59
`define rendec_data_sel_rx_RX_IDX       60
`define rdeskewen_RX_IDX                61
`define rindv_rx_RX_IDX                 62

// page divided into both rx and tx
// pcs_ctrl1_ch0_ext = {rtx_pipe_enable[0], rrx_pipe_enable[0], rpowdnr[0], rpowdnt[0],
// 8001-8004            rendec_tx[0], rendec_rx[0], r8b10b_enc_ibm_en[0], rmatchen[0],
//                      r8b10b_dec_ibm_en_ch0, rforce_kchar[0], rforce_echar[0],
//                      rlp20ben[0], rgenericfifo[0], rcascaded_8b10b_en_tx[0],
//                      rcascaded_8b10b_en_rx[0]};
`define rrx_pipe_enable_RX_IDX          63
`define rpowdnr_RX_IDX                  64
`define rendec_rx_RX_IDX                65
`define rmatchen_RX_IDX                 66
`define r8b10b_dec_ibm_en_RX_IDX_0      67
`define r8b10b_dec_ibm_en_RX_IDX_1      68
`define rlp20ben_RX_IDX                 69
`define rgenericfifo_RX_IDX             70
`define rcascaded_8b10b_en_rx_RX_IDX    71

// all rx - 14
//assign  pcs_ctrl2_ch0_ext = {resync_badcg_en_ch0, rencdt_rising[0], rdis_rx_disp[0],
// 8005-8008                   rcomp_pat_porn[0], rcomp_size_ch0, rcomp_pat_ch0[39:32]};
`define rencdt_rising_RX_IDX            72
`define rdis_rx_disp_RX_IDX             73
`define rcomp_pat_porn_RX_IDX           74
`define rcomp_size_RX_IDX_0             75
`define rcomp_size_RX_IDX_2             77

// page 3 + 4 - all rx - 32
//assign  pcs_ctrl3_ch0_ext = {rcomp_pat_ch0[31:16]};
// 8009-800c
//assign  pcs_ctrl4_ch0_ext = {rcomp_pat_ch0[15:0]};
// 800d-8010
`define rcomp_pat_RX_IDX_0              78
`define rcomp_pat_RX_IDX_39             117

// rx - 12
//assign  pcs_ctrl5_ch0_ext = {rrxfifo_dis[0], rtxfifo_dis[0], rib_force_disp[0],
//8011-8014                  rrundisp_ch0, rtxfifo_lowlatency_en[0], rrlv_en[0], rautobtalg_dis[0],
//                           rsync_sm_dis[0], rib_inv_cd_ch0, rrxfifo_lowlatency_en[0]};
`define rrxfifo_dis_RX_IDX              118
`define rrundisp_RX_IDX_0               119
`define rrundisp_RX_IDX_5               124
`define rrlv_en_RX_IDX                  125
`define rautobtalg_dis_RX_IDX           126
`define rsync_sm_dis_RX_IDX             127
`define rib_inv_cd_RX_IDX_0             128
`define rib_inv_cd_RX_IDX_1             129
`define rrxfifo_lowlatency_en_RX_IDX    130

// rx - 8
//assign  pcs_ctrl6_ch0_ext = {rdwidth_tx[0], rdwidth_rx[0], rge_xaui_tx[0],
// 8015 - 8018                 rrx_detect_bypass[0], rtxurstpcs[0], rrxurstpcs[0],
//                             rrsvd_tx_ch0, rskpsetbased[0], rtruebac2bac[0],rrsvd_rx_ch0};
//
`define rdwidth_rx_RX_IDX               133         
`define rrx_detect_bypass_RX_IDX        134        
`define rrxurstpcs_RX_IDX               135        
`define rskpsetbased_RX_IDX             136        
`define rtruebac2bac_RX_IDX             137        
`define rrsvd_rx_RX_IDX_0               138        
`define rrsvd_rx_RX_IDX_1               139        
`define rrsvd_rx_RX_IDX_2               140       

// all rx   - 16                          
//assign  pcs_ctrl7_ch0_ext = {rgnumber_ch0, rknumber_ch0};
// 8018 - 801c
`define rgnumber_RX_IDX_0               141
`define rgnumber_RX_IDX_7               148
`define rknumber_RX_IDX_0               149
`define rknumber_RX_IDX_7               156

// page 8 of rx moved to first as POF used rclk_2 long ago
//assign  pcs_ctrl8_ch0_ext = {rfreerun_tx[0], rtxwrclksel[0], rtxrdclksel[0],
//801d-8020                  rfreerun_rx[0], rrcvd_clk_sel_ch0, 
//                           rclk_1_sel_ch0, rclk_2_sel_ch0, rrx_rd_clk_sel[0], 
//                           renumber_ch0, renpolinv_rx[0], rclkcmpinsertpad[0]};

// all rx   - 26
//assign  pcs_ctrl9_ch0_ext = {rppm_cnt_reset[0], rphfifourstrx[0], rcmpfifourst[0], 
// 8025 - 8028                 rtx_idle_delay_ch0, rclkcmpsqmd[0], rclkcmpsq1p_ch0[9:0]};
`define rppm_cnt_reset_RX_IDX           157
`define rphfifourstrx_RX_IDX            158
`define rcmpfifourst_RX_IDX             159
`define rtx_idle_delay_RX_IDX_0         160
`define rtx_idle_delay_RX_IDX_1         161
`define rclkcmpsqmd_RX_IDX              162
`define rclkcmpsq1p_RX_IDX_0            163
`define rclkcmpsq1p_RX_IDX_19           182

// all rx - pages 10 and 11 - 21
// 8029 - 802C
//assign  pcs_ctrl10_ch0_ext = {rclkcmpsq1n_ch0[19:15], rclkcmppos[0], rclkcmpsq1p_ch0[19:10]};
// 802D - 8030
//assign  pcs_ctrl11_ch0_ext = {rclkcmpsq1n_ch0[14:10], 1'b0, rclkcmpsq1n_ch0[9:0]};
`define rclkcmpsq1n_RX_IDX_0           183
`define rclkcmpsq1n_RX_IDX_19          202
`define rclkcmppos_RX_IDX              203

// page 12 - rx: 12
//assign  pcs_ctrl12_ch0_ext = {rrev_loopbk[0], ralempty_ch0, ralfull_ch0, rforce_disp[0], 
//                              rkchar[0], rosbased[0], rensymswap_tx[0], 1'b0, rosnumber_ch0};
`define ralempty_RX_IDX_0              204
`define ralempty_RX_IDX_3              207
`define ralfull_RX_IDX_0               208
`define ralfull_RX_IDX_3               211
`define rkchar_RX_IDX                  212
`define rosbased_RX_IDX                213
`define rosnumber_RX_IDX_0             214
`define rosnumber_RX_IDX_1             215

// page 13 - rx: 12
//assign  pcs_ctrl13_ch0_ext = {rwa_6g_en[0], renpolinv_tx[0], rbitslip_size_ch0, rbytord_2sym_en[0],
//                              rbysync_polinv_en[0], rbitloc_rev_en[0], rbyte_rev_en[0], renbitrev_tx[0],
//                              rbyteorden_ch0, rbytordplden[0], rphfifopldentx[0], rphfifoursttx[0],
//                              rphfifopldenrx[0], rautoinsdis[0]};
`define rwa_6g_en_RX_IDX               216
`define rbitslip_size_RX_IDX_0         217
`define rbitslip_size_RX_IDX_1         218
`define rbytord_2sym_en_RX_IDX         219
`define rbysync_polinv_en_RX_IDX       220
`define rbitloc_rev_en_RX_IDX          221
`define rbyte_rev_en_RX_IDX            222
`define rbyteorden_RX_IDX_0            223
`define rbyteorden_RX_IDX_1            224
`define rbytordplden_RX_IDX            225
`define rphfifopldenrx_RX_IDX          226
`define rautoinsdis_RX_IDX             227


// page 14 - all rx
//assign  pcs_ctrl14_ch0_ext = {rppmsel_ch0, rbytordpat_ch0};
`define rppmsel_RX_IDX_0               228
`define rppmsel_RX_IDX_5               233
`define rbytordpat_RX_IDX_0            234
`define rbytordpat_RX_IDX_9            243

// page 15
//assign  pcs_ctrl15_ch0_ext = {rtest_bus_sel_ch0, rforce_sig_det_pcs[0], rforce0_freqdet[0], 
//                              rforce1_freqdet[0], rbytordpad_ch0};
`define test_bus_sel_RX_IDX_0          244
`define test_bus_sel_RX_IDX_2          246
`define rforce_sig_det_pcs_RX_IDX      247
`define rforce0_freqdet_RX_IDX         248
`define rforce1_freqdet_RX_IDX         249
`define rbytordpad_RX_IDX_0            250
`define rbytordpad_RX_IDX_9            259

// pma_ctrl8: 4.807c-807h - RX portion
//assign  pma_ctrl8_ch0_ext = {rs_lpbk[0], r_rlpbk[0], rs_rdlpbk[0], rrx_revlb_sw[0],
//                             rurx_pdb[0], rtx_cgb_pdb[0], rtx_ob_pdb[0], rrx_cru_pdb[0],
//                             rrx_cru_rst[0], rrx_ib_pdb[0], rrxurstpma[0], radce_adapt[0],
//                             radce_pdb[0], radce_rst[0], rsig_inv_2tap[0], rsig_inv_pre[0]};
`define rs_lpbk_RX_IDX                 260
`define rrx_revlb_sw_RX_IDX            261

// cru_clock_select index - SW twisted
`define cru_clock_select_RX_IDX_0      262
`define cru_clock_select_RX_IDX_1      263
`define cru_clock_select_RX_IDX_2      264
`define cru_clock_select_RX_IDX_3      265

`define reconfig_clk_RX_IDX            299
// MAX = 299

`timescale 1 ps / 1 ps
module arriagx_hssi_receiver (
    a1a2size,
    adcepowerdn,
    adcereset,        // in rev1.3 
    alignstatus,
    alignstatussync,  // added in rev1.2
    analogreset,
    bitslip,
    coreclk,
    cruclk, 
    crupowerdn,
    crureset,        // in rev1.3 
    datain,
    digitalreset,
    disablefifordin,
    disablefifowrin,
    dpriodisable,
    dprioin,
    enabledeskew,
    enabyteord,
    enapatternalign,
    fifordin,
    fiforesetrd,
    ibpowerdn, 
    invpol,       // invpolarity,
    localrefclk,
    locktodata, 
    locktorefclk,
    masterclk,
    parallelfdbk,
    phfifordenable,
    phfiforeset, 
    phfifowrdisable,
    phfifox4bytesel,
    phfifox4rdenable,
    phfifox4wrclk, 
    phfifox4wrenable, 
    phfifox8bytesel,
    phfifox8rdenable,
    phfifox8wrclk, 
    phfifox8wrenable,
    pipe8b10binvpolarity,  // in rev1.3
    pipepowerdown,
    pipepowerstate,
    quadreset, 
    refclk,
    revbitorderwa,
    revbyteorderwa,
    rmfifordena,
    rmfiforeset,
    rmfifowrena,
    rxdetectvalid,
    rxfound,
    serialfdbk,
    seriallpbken,
    termvoltage, 
    testsel, 
    xgmctrlin,
    xgmdatain,

    a1a2sizeout,
    a1detect,
    a2detect,
    adetectdeskew,
    alignstatussyncout,   // added in rev1.2
    analogtestbus,             
    bistdone,
    bisterr,
    byteorderalignstatus,
    clkout,                // clockout,
    cmudivclkout,
    ctrldetect,
    dataout,
    dataoutfull,          // new in 6.1
    disablefifordout,
    disablefifowrout,
    disperr,
    dprioout,
    errdetect,
    fifordout,
    freqlock,             // freqlocked,
    k1detect,
    k2detect, 
    patterndetect,
    phaselockloss,
    phfifobyteselout,
    phfifooverflow,  
    phfifordenableout,
    phfifounderflow,      
    phfifowrclkout,
    phfifowrenableout,
    pipebufferstat,
    pipedatavalid,
    pipeelecidle,
    pipephydonestatus,
    pipestatus,
    pipestatetransdoneout,  // added in rev1.3
    rdalign,
    recovclkout,
    revparallelfdbkdata,        
    revserialfdbkout,    
    rlv, 
    rmfifoalmostempty,
    rmfifoalmostfull,
    rmfifodatadeleted,        
    rmfifodatainserted,
    rmfifoempty,
    rmfifofull,
    runningdisp,
    signaldetect,
    syncstatus,
    syncstatusdeskew,
    xgmctrldet,
    xgmdataout,
    xgmdatavalid,
    xgmrunningdisp
);

parameter adaptive_equalization_mode    = "none";       // <continuous/stopped/none>; 
parameter align_loss_sync_error_num     = 4;            // <integer 0-7>;// wordalign
parameter align_ordered_set_based       = "false";       // <true/false>;           
parameter align_pattern                 = "0101111100"; //  word align: size of align_pattern_length; 
parameter align_pattern_length          = 10;           // <7, 8, 10, 16, 20, 32, 40>; 
parameter align_to_deskew_pattern_pos_disp_only = "false"; // <true/false>;
parameter allow_align_polarity_inversion = "false";     // <true/false>; 
parameter allow_pipe_polarity_inversion  = "false";     // <true/false>;
parameter allow_serial_loopback          = "false";     // <true/false>;
parameter bandwidth_mode                 = 0;           // <integer 0-3>;
parameter bit_slip_enable                = "false";     // <true/false>;
parameter byte_order_pad_pattern         = "0101111100";// <10-bit binary string>;            
parameter byte_order_pattern             = "0101111100";// <10-bit binary string>;
parameter byte_ordering_mode             = "none";      // <none/pattern-based/syncstatus-based>;
parameter channel_number                 = 0;           // <integer 0-3>;
parameter channel_bonding                = "none";      // <none, x4, x8>;
parameter channel_width                  = 10;          // <integer 8,10,16,20,32,40>;
parameter clk1_mux_select                = "recvd_clk"; // <RECVD_CLK, MASTER_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;      
parameter clk2_mux_select                = "recvd_clk"; // <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK, CORE_CLK>;
parameter cru_clock_select               = 0;           //  <CRUCLK<n> where n is 0 through 7 >
parameter cru_divide_by                  = 1;           // <1,2,4>;
parameter cru_multiply_by                = 10;          // <1,2,4,5,8,10,16,20,25>;
parameter cru_pre_divide_by              = 1;           // <1,2,4,8>;
parameter cruclk0_period                 = 10000;       //  in ps
parameter cruclk1_period                 = 10000;       //  in ps
parameter cruclk2_period                 = 10000;       //  in ps
parameter cruclk3_period                 = 10000;       //  in ps
parameter cruclk4_period                 = 10000;       //  in ps
parameter cruclk5_period                 = 10000;       //  in ps
parameter cruclk6_period                 = 10000;       //  in ps
parameter cruclk7_period                 = 10000;       //  in ps
parameter datapath_protocol              = "basic";     // <basic/pipe/xaui>;
parameter dec_8b_10b_compatibility_mode  = "true";     // <true/false>;
parameter dec_8b_10b_mode                = "none";      // <normal/cascaded/none>;
parameter deskew_pattern                 = "1100111100";// K28.3
parameter disable_auto_idle_insertion    = "false";      // <true/false>;  
parameter disable_ph_low_latency_mode    = "false";      // <true/false>;       
parameter disable_running_disp_in_word_align       = "false";    // <true/false>; 
parameter disallow_kchar_after_pattern_ordered_set = "false";    // <true/false>;
parameter dprio_mode                     = "none";      // <none/pma_electricals/full>;
parameter enable_bit_reversal            = "false";     // <true/false>;
parameter enable_byte_order_control_sig  = "false";     // <true/false>;           
parameter enable_dc_coupling             = "false";     // <true/false>;
parameter enable_deep_align              = "false";     // <true/false>;                          
parameter enable_deep_align_byte_swap    = "false";     // <true/false>;
parameter enable_lock_to_data_sig        = "false";     // <true/false>;
parameter enable_lock_to_refclk_sig      = "true";      // <true/false>;
parameter enable_self_test_mode          = "false";     // <true/false>;
parameter enable_true_complement_match_in_word_align = "true";    // <true/false>; 
parameter eq_adapt_seq_control           = 0;           // <integer 0-3>; 
parameter eq_max_gradient_control        = 0;           // <integer 0-7>;
parameter equalizer_ctrl_a               = 0;           // <integer 0-7>;
parameter equalizer_ctrl_b               = 0;           // < integer 0-7>;
parameter equalizer_ctrl_c               = 0;           // < integer 0-7>;
parameter equalizer_ctrl_d               = 0;           // < integer 0-7>;
parameter equalizer_ctrl_v               = 0;           // < integer 0-7>;
parameter equalizer_dc_gain              = 0;           // <integer 0-3>;
parameter force_freq_det_high            = "false";     // <true/false>;
parameter force_freq_det_low             = "false";     // <true/false>;
parameter force_signal_detect            = "false";     // <true/false>;
parameter force_signal_detect_dig        = "false";     // <true/false>;
parameter ignore_lock_detect             = "false";     // <true/false>;
parameter infiniband_invalid_code        = 0;           // <integer 0-3>;
parameter insert_pad_on_underflow        = "false";
parameter num_align_code_groups_in_ordered_set = 1;     // <integer 0-3>;   
parameter num_align_cons_good_data       = 3;           // wordalign<Integer 1-256>;
parameter num_align_cons_pat             = 4;           // <Integer 1-256>;
parameter phystatus_reset_toggle         = "false";      // new in 6.0           
parameter ppmselect                      = 20;          // <integer 0-63>;           
parameter prbs_all_one_detect            = "false";     // <true/false>;
parameter rate_match_almost_empty_threshold = 11;        // <integer 0-15>;           
parameter rate_match_almost_full_threshold  = 13;       // <integer 0-15>;           
parameter rate_match_back_to_back        = "false";     // <true/false>;           
parameter rate_match_fifo_mode           = "none";      // <normal/cascaded/generic/cascaded_generic/none>;
parameter rate_match_ordered_set_based   = "false";     // <integer 10 or 20>;
parameter rate_match_pattern_size        = 10;          // <integer 10 or 20>;
parameter rate_match_pattern1            = "00000000000010111100";  // <20-bit binary string>;           
parameter rate_match_pattern2            = "00000000000010111100";  // <20-bit binary string>;           
parameter rate_match_skip_set_based      = "false";     // <true/false>;  
parameter rd_clk_mux_select              = "int_clk";   // <INT_CLK, CORE_CLK>;
parameter recovered_clk_mux_select       = "recvd_clk"; // <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>; 
parameter reset_clock_output_during_digital_reset = "false";   // <true/false>;
parameter run_length                     = 200;         // <5-320 or 4-254 depending on the deserialization factor>; 
parameter run_length_enable              = "false";     // <true/false>; 
parameter rx_detect_bypass               = "false";
parameter self_test_mode                 = "incremental"; // <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
parameter send_direct_reverse_serial_loopback = "false";  // <true/false>;
parameter signal_detect_threshold        = 0;           // <integer 0-7 (actual values determined after PE char)>;
parameter termination                    = "OCT_100_OHMS";  // new in 5.1SP1
parameter use_align_state_machine        = "false";     // <true/false>;
parameter use_deserializer_double_data_mode = "false";  // <true/false>;
parameter use_deskew_fifo                = "false";     // <true/false>;                                                  
parameter use_double_data_mode           = "false";     // <true/false>; 
parameter use_parallel_loopback          = "false";     // <true/false>;
parameter use_rate_match_pattern1_only   = "false";     // <true/false>;           
parameter use_rising_edge_triggered_pattern_align = "false";         // <true/false>; 

// pma
parameter common_mode = "0.9V";                         // new in 5.1 SP1
parameter loop_filter_resistor_control = 0;             // new in 6.0
parameter loop_filter_ripple_capacitor_control = 0;     // new in 6.0
parameter pd_mode_charge_pump_current_control = 0;      // new in 6.0
parameter signal_detect_hysteresis_enabled = "false";   // new in 5.1 SP1
parameter single_detect_hysteresis_enabled = "false";   // new in 5.1 SP1 - used in code
parameter use_termvoltage_signal = "true";              // new in 5.1 SP10
parameter vco_range = "high";                           // new in 6.0
parameter sim_offset_cycle_count = 10;                  // new in 7.1 for adce

parameter protocol_hint = "basic"; // new in 6.0 -<gige,xaui,pcie_x1,pcie_x4,pcie_x8,sonet,cei, basic>

//  PE -only parameters
parameter allow_vco_bypass               = "false";     // <true/false>
parameter charge_pump_current_control    = 0;           // <integer 0-3>;
parameter up_dn_mismatch_control         = 0;           // <integer 0-3>;
parameter charge_pump_test_enable        = "false";     // <true/false>;
parameter charge_pump_current_test_control_pos = "false";  // <true/false>
parameter charge_pump_tristate_enable    = "false";     // <true/false>;
parameter low_speed_test_select          = 0;           // <integer 0-15>;
parameter cru_clk_sel_during_vco_bypass  = "refclk1";   // <refclk1/refclk2/ext1/ext2>
parameter test_bus_sel                   = 0;           // <integer 0-7>;

// POF ONLY parameters
parameter enable_phfifo_bypass     = "false";
parameter sim_rxpll_clkout_phase_shift = 0;
parameter sim_rxpll_clkout_latency = 0;

// LOCAL_PARAMETERS_BEGIN

parameter dprio_config_mode = 0;                        // 6.1
parameter dprio_width = 200;                            // 6.1

parameter CTRL_OUT_WIDTH = (use_deserializer_double_data_mode == "true"  && use_double_data_mode == "true")  ? 4 :
                          (use_deserializer_double_data_mode == "false" && use_double_data_mode == "false") ? 1 : 2;

parameter DATA_OUT_WIDTH = channel_width;

parameter A1K1_OUT_WIDTH = (use_deserializer_double_data_mode == "true") ? 2 : 1 ; // from walign directly

parameter BASIC_WIDTH    = (channel_width % 10 == 0) ? 10 : 8;
parameter NUM_OF_BASIC   = channel_width / BASIC_WIDTH;

//parameter RX_PMA_ST = 230;  // extended 152; now 70 cap used 32

// LOCAL_PARAMETERS_END

input          a1a2size;
input          adcepowerdn;
input          adcereset; 
input          alignstatus;
input          alignstatussync;
input          analogreset;
input          bitslip;
input          coreclk;
input [8:0]    cruclk; 
input          crupowerdn;
input          crureset;
input          datain;
input          digitalreset;
input          disablefifordin;
input          disablefifowrin;
input          dpriodisable;
input [dprio_width - 1 : 0]  dprioin;
input          enabledeskew;
input          enabyteord;
input          enapatternalign;
input          fifordin;
input          fiforesetrd;
input          ibpowerdn; 
input          invpol;
input          localrefclk;
input          locktodata; 
input          locktorefclk;
input          masterclk;
input [19:0]   parallelfdbk;
input          phfifordenable;
input          phfiforeset; 
input          phfifowrdisable;
input          phfifox4bytesel;
input          phfifox4rdenable;
input          phfifox4wrclk; 
input          phfifox4wrenable; 
input          phfifox8bytesel;
input          phfifox8rdenable;
input          phfifox8wrclk; 
input          phfifox8wrenable; 
input          pipe8b10binvpolarity; // new in rev1.2
input [1:0]    pipepowerdown;        // width from 1 -> 2 in rev1.2
input [3:0]    pipepowerstate;       // width change from 3 to 4 in rev1.3
input          quadreset; 
input          refclk;
input          revbitorderwa;
input          revbyteorderwa;
input          rmfifordena;
input          rmfiforeset;
input          rmfifowrena;
input          rxdetectvalid;
input [1:0]    rxfound;
input          serialfdbk;
input          seriallpbken;
input [2:0]    termvoltage; 
input [3:0]    testsel; 
input          xgmctrlin;
input [7:0]    xgmdatain;

output [CTRL_OUT_WIDTH-1:0]     a1a2sizeout;
output [A1K1_OUT_WIDTH-1:0]     a1detect;
output [A1K1_OUT_WIDTH-1:0]     a2detect;
output                          adetectdeskew;
output                          alignstatussyncout;
output [7:0]                    analogtestbus;             
output                          bistdone;
output                          bisterr;
output                          byteorderalignstatus;
output                          clkout;
output                          cmudivclkout;
output [CTRL_OUT_WIDTH-1:0]     ctrldetect;
output [DATA_OUT_WIDTH-1:0]     dataout;
output [63:0]                   dataoutfull;        // new in 6.1
output                          disablefifordout;
output                          disablefifowrout;
output [CTRL_OUT_WIDTH-1:0]     disperr;
output [dprio_width - 1 : 0]    dprioout;
output [CTRL_OUT_WIDTH-1:0]     errdetect;
output                          fifordout;
output                          freqlock;
output [A1K1_OUT_WIDTH-1:0]     k1detect;
output [1:0]                    k2detect; 
output [CTRL_OUT_WIDTH-1:0]     patterndetect;
output                          phaselockloss;
output                          phfifobyteselout;
output                          phfifooverflow;  
output                          phfifordenableout;
output                          phfifounderflow;      
output                          phfifowrclkout;
output                          phfifowrenableout;
output [3:0]                    pipebufferstat;
output                          pipedatavalid;
output                          pipeelecidle;
output                          pipephydonestatus;
output [2:0]                    pipestatus;
output                          pipestatetransdoneout;
output                          rdalign;
output                          recovclkout;
output [19:0]                   revparallelfdbkdata;        
output                          revserialfdbkout;    
output                          rlv; 
output                          rmfifoalmostempty;
output                          rmfifoalmostfull;
output [CTRL_OUT_WIDTH-1:0]     rmfifodatadeleted;        
output [CTRL_OUT_WIDTH-1:0]     rmfifodatainserted;
output                          rmfifoempty;
output                          rmfifofull;
output [CTRL_OUT_WIDTH-1:0]     runningdisp;
output                          signaldetect;
output [CTRL_OUT_WIDTH-1:0]     syncstatus;
output                          syncstatusdeskew;
output                          xgmctrldet;
output [7:0]                    xgmdataout;
output                          xgmdatavalid;
output                          xgmrunningdisp;

/////////////////////////////////////////////////////////////////////////////////
// Temp registers to reslove fixed width ==> varaiable width output transfer --//
/////////////////////////////////////////////////////////////////////////////////

reg [CTRL_OUT_WIDTH-1:0]     a1a2sizeout_reg;
reg [A1K1_OUT_WIDTH-1:0]     a1detect_reg;
reg [A1K1_OUT_WIDTH-1:0]     a2detect_reg;
reg [CTRL_OUT_WIDTH-1:0]     ctrldetect_reg;
reg [DATA_OUT_WIDTH-1:0]     dataout_reg;
reg [CTRL_OUT_WIDTH-1:0]     disperr_reg;
reg [CTRL_OUT_WIDTH-1:0]     errdetect_reg;
reg [A1K1_OUT_WIDTH-1:0]     k1detect_reg;
reg [1:0]                    k2detect_reg; 
reg [CTRL_OUT_WIDTH-1:0]     patterndetect_reg;
reg [CTRL_OUT_WIDTH-1:0]     rmfifodatadeleted_reg;        
reg [CTRL_OUT_WIDTH-1:0]     rmfifodatainserted_reg;
reg [CTRL_OUT_WIDTH-1:0]     runningdisp_reg;
reg [CTRL_OUT_WIDTH-1:0]     syncstatus_reg;


/////////////////////////////////////////////////////////////////////////////////
// atom level initial CRAM  ---------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

reg [1:0]     init_dskwclksel;
reg           init_is_lane0;         
reg [1:0]     init_r8b10b_dec_ibm_en;
reg [3:0]     init_ralempty;
reg [3:0]     init_ralfull;
reg           init_rall_one_dect_only;
reg           init_rautobtalg_dis;   
reg           init_rautoinsdis;
reg           init_rbist_clr_rx;         
reg [1:0]     init_rbist_sel;            
reg           init_rbisten_rx;           
reg           init_rbitloc_rev_en;       
reg [1:0]     init_rbitslip_size;        
reg           init_rbysync_polinv_en;    
reg           init_rbyte_rev_en;         
reg [1:0]     init_rbyteorden;           
reg           init_rbytord_2sym_en;        
reg [9:0]     init_rbytordpad;           
reg [9:0]     init_rbytordpat;           
reg           init_rbytordplden;         
reg           init_rcascaded_8b10b_en_rx;
reg [1:0]     init_rclk_1_sel;    
reg [1:0]     init_rclk_2_sel;    
reg           init_rclkcmpinsertpad;  // feeding both rx_digi and pipe 
reg           init_rclkcmppos;
reg [19:0]    init_rclkcmpsq1n;
reg [19:0]    init_rclkcmpsq1p;
reg           init_rclkcmpsqmd;
reg           init_rcmpfifourst;
reg [39:0]    init_rcomp_pat;        
reg           init_rcomp_pat_porn;       
reg [2:0]     init_rcomp_size;       
reg [1:0]     init_rcxpat_chnl_en;
reg           init_rdis_rx_disp;     
reg [9:0]     init_rdskchrp;
reg           init_rdskposdisp; 
reg           init_rdwidth_rx;       
reg           init_rencdt_rising;        
reg           init_rendec_data_sel_rx;
reg           init_rendec_rx;        
reg           init_renpolinv_rx;
reg [2:0]     init_renumber;
reg [1:0]     init_resync_badcg_en;      
reg           init_rforce_sig_det_pcs;
reg           init_rforce0_freqdet;
reg           init_rforce1_freqdet;
reg           init_rfreerun_rx;   
reg           init_rgenericfifo;     
reg [7:0]     init_rgnumber;
reg [1:0]     init_rib_inv_cd;       
reg           init_rindv_rx;         
reg           init_rkchar;
reg [7:0]     init_rknumber;
reg           init_rlp20ben;         
reg           init_rmatchen;         
reg           init_rosbased;
reg [1:0]     init_rosnumber;
reg           init_rphfifo_master_sel_rx;
reg           init_rphfifopldenrx;       
reg           init_rphfifourstrx;
reg           init_rpma_doublewidth_rx;
reg           init_rpmadwidth_rx;
reg           init_rppm_cnt_reset;
reg [5:0]     init_rppmsel;
reg           init_rprbs_clr_rslt_rx;    
reg [2:0]     init_rprbs_sel;            
reg           init_rprbsen_rx;           
reg [1:0]     init_rrcvd_clk_sel; 
reg           init_rrlv_en;          
reg [5:0]     init_rrundisp;         
reg           init_rrx_rd_clk_sel;
reg           init_rrx_revlb_sw;
reg           init_rrxfifo_dis;      
reg           init_rrxfifo_lowlatency_en;
reg           init_rs_lpbk;
reg           init_rskpsetbased;
reg           init_rsync_sm_dis;     
reg [2:0]     init_rtest_bus_sel;
reg           init_rtruebac2bac;
reg           init_rwa_6g_en;            
reg           init_scan_mode;                     
reg           init_sel_gp_md;
                                                 // ====== pipe ======
//reg         init_rclkcmpinsertpad;             // common between Rx and rx_digi	
reg           init_rphystatus_rst_toggle;        // new in ww29
reg           init_rrdwidth_rx;                  // rx only 
reg           init_rrx_detect_bypass;            // rx only 
reg           init_rrx_pipe_enable;              // rx only
reg [1:0]     init_rtx_elec_idle_delay;          // rx only
reg           init_rtx_pipe_enable;              // tx pipe

// PMA
reg [1:0]   init_rtx_term;      // 2-bits
reg [1:0]   init_r_tx_det_rx;   // 2-bit
reg [1:0]   init_rrx_term;      // 2
reg         init_rforce_sigdet; // 1 
reg         init_rrx_dc_couple; // 1 - qpmaused
reg [1:0]   init_rrx_eq_dc;     // 2
reg [2:0]   init_rrx_vtt;       // 3
reg [2:0]   init_rrx_sloslv;    // 3

reg [2:0]   init_reqa_ct;      // 3-bits  - qpmaused
reg [2:0]   init_reqb_ct;      // 3-bit - qpmaused
reg [2:0]   init_reqc_ct;      // 3 - qpmaused
reg [2:0]   init_reqd_ct;      // 3 - qpmaused 
reg [2:0]   init_req_ctv;      // 3 - qpmaused

// pma_ctrl6_ch0_ext: 8074h
reg [1:0]   init_rrx_cru_m_sel;  
reg         init_rrx_cru_div2;  
reg         init_rltr;
reg         init_rltd;

// pma_ctrl7_ch0_ext: 8078h
reg [3:0]   init_rrx_cru_m;
reg [1:0]   init_rrx_cru_l;

// cru_clock_select
reg [3:0]   init_cru_clock_select;

/////////////////////////////////////////////////////////////////////////////////
// signals from RX PCS to PMA  ------------------------------------//
/////////////////////////////////////////////////////////////////////////////////
wire pma_in_freqlock;

/////////////////////////////////////////////////////////////////////////////////
// signals from RX PMA to Digital portion  ------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire        pma_out_clklow;
wire        pma_out_fref;
wire [19:0] pma_out_pdata;
wire        pma_out_rcvd_clk;
wire        pma_out_sigdet;

/////////////////////////////////////////////////////////////////////////////////
// signals from RX PMA to Top level  ------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////
wire        pma_out_phaselockloss;
wire        pma_out_revserialfdbkout;

/////////////////////////////////////////////////////////////////////////////////
// sub-block interface: CDR   -------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire [8:0]    cdr_in_cruclk;
wire          cdr_in_dpriodisable;
wire [19:0]   cdr_in_dprioin;
wire          cdr_in_freqlock;
wire          cdr_in_ltd;
wire          cdr_in_ltr;
wire          cdr_in_pdb;
wire          cdr_in_reset;
wire          cdr_in_rxin;

wire [19:0]   cdr_out_dprioout;
wire          cdr_out_clklow;
wire          cdr_out_fref;
wire          cdr_out_freqlocked;
wire          cdr_out_phaselockloss; 
wire          cdr_out_revserialfdbk;
wire          cdr_out_serialclkout;
wire          cdr_out_signaldetect;

/////////////////////////////////////////////////////////////////////////////////
// sub-block interface: DESERIALIZER (des)   ----------------------------------//
/////////////////////////////////////////////////////////////////////////////////
wire        des_in_datain;
wire        des_in_rdoublewidth;   // 1 = double pma
wire        des_in_rdwidth;        // 1 = 10-bit, 0 = 8-bit
wire        des_in_reset;
wire        des_in_serialclk;
wire        des_in_serialfdbken;
wire        des_in_serialfdbkin;

wire        des_out_recvclkout;
wire [19:0] des_out_paralleldataout;    


/////////////////////////////////////////////////////////////////////////////////
// sub-block interface: ADCE                                                   //
/////////////////////////////////////////////////////////////////////////////////
wire                         reconfig_clk;
wire                         adce_ena;
reg                          reg_adce_high_out;
reg                          reg_adce_low_out;
integer                      adce_initial_cycle_cnt;

/////////////////////////////////////////////////////////////////////////////////
// sub-block interface: pcs_reset (pr)  ---------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire   pr_in_hard_reset;
wire   pr_in_clk_2_b;
wire   pr_in_refclk_b_in;
wire   pr_in_scan_mode;
wire   pr_in_rxpcs_rst;
wire   pr_in_txpcs_rst;

wire   pr_out_rxrst_int;
wire   pr_out_txrst_int;

/////////////////////////////////////////////////////////////////////////////////
// sub-block interface: pipe_interface (pi)  ----------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire         pi_in_pipe_rx_clk;    // beginning input
wire         pi_in_pipe_tx_clk;
wire         pi_in_polinv_rx;
wire         pi_in_power_state_transition_done;
wire         pi_in_power_state_transition_done_ena;
wire  [1:0]  pi_in_powerdown;
wire         pi_in_refclk_b;
wire         pi_in_refclk_b_reset;
wire         pi_in_revloopback;
wire         pi_in_rx_detect_valid;
wire         pi_in_rx_found;
wire         pi_in_rx_pipe_reset;
wire         pi_in_rxbeacon;
wire  [63:0] pi_in_rxd;
wire         pi_in_rxelectricalidle;
wire         pi_in_rxpolarity;
wire         pi_in_tx_elec_idle_comp;
wire         pi_in_tx_pipe_reset;
wire         pi_in_txcompliance;
wire  [43:0] pi_in_txd_ch;
wire         pi_in_txdetectrxloopback;
wire         pi_in_txelecidle;
wire  [3:0]  pi_in_powerstatein;
wire         pi_in_txdetectrxin;

wire         pi_out_phystatus;    // beginning output
wire         pi_out_sim_state_transition_done;
wire         pi_out_polinv_rx_int;
wire  [3:0]  pi_out_powerstate; // to both cmu and rx
wire         pi_out_rev_loopbk;
wire  [63:0] pi_out_rxd_ch;
wire         pi_out_rxelecidle;
wire  [2:0]  pi_out_rxstatus;
wire         pi_out_rxvalid;
wire         pi_out_tx_elec_idle;
wire         pi_out_txbeacon;
wire  [43:0] pi_out_txd;
wire         pi_out_txdetectrx;


/////////////////////////////////////////////////////////////////////////////////
// sub-block interface: rx_digi (rd)  -----------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire           rd_in_a1a2_size;         // begin input
wire           rd_in_align_status;     
wire           rd_in_align_status_sync_0;     
wire           rd_in_align_status_sync_2;     
wire           rd_in_bitloc_rev_en;
wire           rd_in_bitslip;          
wire           rd_in_byte_rev_en;
wire           rd_in_bytordpld;
wire           rd_in_clklow;
wire           rd_in_cmpfifourst;
wire           rd_in_disable_fifo_rd_0;
wire           rd_in_disable_fifo_rd_2;
wire           rd_in_disable_fifo_wr_0;
wire           rd_in_disable_fifo_wr_2;
wire           rd_in_en_dskw_gp;    
wire           rd_in_en_dskw_qd;    
wire           rd_in_encdt;            
wire [9:0]     rd_in_encoder_testbus;
wire           rd_in_fifo_rd_in_comp_0;  
wire           rd_in_fifo_rd_in_comp_2;  
wire           rd_in_fifo_rst_rd_gp;
wire           rd_in_fifo_rst_rd_qd;
wire           rd_in_fref;
wire           rd_in_hard_reset;
wire           rd_in_phfifourst_rx;
wire           rd_in_pld_rx_clk;
wire [7:0]     rd_in_pma_testbus;
wire           rd_in_polinv_rx;
wire [19:0]    rd_in_pudi;             
wire           rd_in_rcvd_clk_pma;
wire           rd_in_rcvd_clk0_pma;
wire           rd_in_rdenable_rmf;         
wire           rd_in_rdenable_rx;
wire           rd_in_refclk_pma;
wire           rd_in_rx_control_rs;    
wire           rd_in_rx_cru_pdb;
wire [7:0]     rd_in_rx_data_rs;       
wire [3:0]     rd_in_rxfifo_shared_sig_in_ch0;
wire [3:0]     rd_in_rxfifo_shared_sig_in_q0_ch0;
wire           rd_in_rxpma_rst;
wire           rd_in_rxpcs_rst;        
wire           rd_in_sigdetni;         
wire [9:0]     rd_in_tx_ctrl_testbus;
wire [19:0]    rd_in_txlp20b;          
wire           rd_in_txpma_local_clk;
wire           rd_in_wrdisable_rx;
wire           rd_in_wrenable_rmf;         

wire [3:0]     rd_out_a1a2_k1k2_flag;      // begin output
wire           rd_out_align_det_sync;   
wire           rd_out_align_status_sync;
wire           rd_out_almost_fl_rmf;        
wire           rd_out_almost_mt_rmf;        
wire           rd_out_bistdone;
wire           rd_out_bisterr;          
wire           rd_out_byteord_flag;
wire [1:0]     rd_out_cg_comma;         
wire [9:0]     rd_out_chnl_test_bus_out;
wire           rd_out_clk_2_b;          
wire           rd_out_dec_ctl;          
wire [7:0]     rd_out_dec_data;         
wire           rd_out_dec_data_valid;
wire           rd_out_disable_fifo_rd;  
wire           rd_out_disable_fifo_wr;  
wire           rd_out_empty_rmf; 
wire           rd_out_empty_rx;
wire [1:0]     rd_out_err_ctl;          
wire [15:0]    rd_out_err_data;         
wire           rd_out_fifo_rd_out_comp; 
wire           rd_out_freq_lock;
wire           rd_out_full_rmf;             
wire           rd_out_full_rx;
wire           rd_out_prbs_done;        
wire           rd_out_prbs_err_lt;      
wire           rd_out_rcvd_clk_pma_b;
wire           rd_out_rd_align;         
wire [19:0]    rd_out_rev_loop_data;
wire           rd_out_rlv;
wire           rd_out_rlv_lt;           
wire [1:0]     rd_out_running_disp;
wire           rd_out_rx_clk;           
wire           rd_out_rx_pipe_clk;
wire           rd_out_rx_pipe_soft_reset;
wire [63:0]    rd_out_rxd; 
wire [3:0]     rd_out_rxfifo_shared_sig_out;
wire           rd_out_selftest_done;
wire           rd_out_selftest_err;     
wire           rd_out_signal_detect_out;
wire           rd_out_sync_status;      

/////////////////////////////////////////////////////////////////////////////////
// Atom level DPRIO input CRAM  -----------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////
wire [1:0]    dprioin_dskwclksel;
wire          dprioin_is_lane0;         
wire [1:0]    dprioin_r8b10b_dec_ibm_en;
wire [3:0]    dprioin_ralempty;
wire [3:0]    dprioin_ralfull;
wire          dprioin_rall_one_dect_only;
wire          dprioin_rautobtalg_dis;   
wire          dprioin_rautoinsdis;
wire          dprioin_rbist_clr_rx;         
wire [1:0]    dprioin_rbist_sel;            
wire          dprioin_rbisten_rx;           
wire          dprioin_rbitloc_rev_en;       
wire [1:0]    dprioin_rbitslip_size;        
wire          dprioin_rbysync_polinv_en;    
wire          dprioin_rbyte_rev_en;         
wire [1:0]    dprioin_rbyteorden;           
wire          dprioin_rbytord_2sym_en;        
wire [9:0]    dprioin_rbytordpad;           
wire [9:0]    dprioin_rbytordpat;           
wire          dprioin_rbytordplden;         
wire          dprioin_rcascaded_8b10b_en_rx;
wire [1:0]    dprioin_rclk_1_sel;    
wire [1:0]    dprioin_rclk_2_sel;    
wire          dprioin_rclkcmpinsertpad;
wire          dprioin_rclkcmppos;
wire [19:0]   dprioin_rclkcmpsq1n;
wire [19:0]   dprioin_rclkcmpsq1p;
wire          dprioin_rclkcmpsqmd;
wire          dprioin_rcmpfifourst;
wire [39:0]   dprioin_rcomp_pat;        
wire          dprioin_rcomp_pat_porn;       
wire [2:0]    dprioin_rcomp_size;       
wire [1:0]    dprioin_rcxpat_chnl_en;
wire          dprioin_rdis_rx_disp;     
wire [9:0]    dprioin_rdskchrp;
wire          dprioin_rdskposdisp; 
wire          dprioin_rdwidth_rx;       
wire          dprioin_rencdt_rising;        
wire          dprioin_rendec_data_sel_rx;
wire          dprioin_rendec_rx;        
wire          dprioin_renpolinv_rx;
wire [2:0]    dprioin_renumber;
wire [1:0]    dprioin_resync_badcg_en;      
wire          dprioin_rforce_sig_det_pcs;
wire          dprioin_rforce0_freqdet;
wire          dprioin_rforce1_freqdet;
wire          dprioin_rfreerun_rx;   
wire          dprioin_rgenericfifo;     
wire [7:0]    dprioin_rgnumber;
wire [1:0]    dprioin_rib_inv_cd;       
wire          dprioin_rindv_rx;         
wire          dprioin_rkchar;
wire [7:0]    dprioin_rknumber;
wire          dprioin_rlp20ben;         
wire          dprioin_rmatchen;         
wire          dprioin_rosbased;
wire [1:0]    dprioin_rosnumber;
wire          dprioin_rphfifo_master_sel_rx;
wire          dprioin_rphfifopldenrx;       
wire          dprioin_rphfifourstrx;
wire          dprioin_rpma_doublewidth_rx;
wire          dprioin_rpmadwidth_rx;
wire          dprioin_rppm_cnt_reset;
wire [5:0]    dprioin_rppmsel;
wire          dprioin_rprbs_clr_rslt_rx;    
wire [2:0]    dprioin_rprbs_sel;            
wire          dprioin_rprbsen_rx;           
wire [1:0]    dprioin_rrcvd_clk_sel; 
wire          dprioin_rrlv_en;          
wire [5:0]    dprioin_rrundisp;         
wire          dprioin_rrx_rd_clk_sel;
wire          dprioin_rrx_revlb_sw;
wire          dprioin_rrxfifo_dis;      
wire          dprioin_rrxfifo_lowlatency_en;
wire          dprioin_rs_lpbk;
wire          dprioin_rskpsetbased;
wire          dprioin_rsync_sm_dis;     
wire [2:0]    dprioin_rtest_bus_sel;
wire          dprioin_rtruebac2bac;
wire          dprioin_rwa_6g_en;            
wire          dprioin_scan_mode;                     
wire          dprioin_sel_gp_md;
                                                //======= pipe =====
//wire        dprioin_rclkcmpinsertpad;         // rx only 	
wire          dprioin_rphystatus_rst_toggle;    // new in ww29
wire          dprioin_rrdwidth_rx;              // rx only
wire          dprioin_rrx_detect_bypass;        // rx only
wire          dprioin_rrx_pipe_enable;          // rx only
wire [1:0]    dprioin_rtx_elec_idle_delay;      // rx only
wire          dprioin_rtx_pipe_enable;

// PMA
wire [1:0]   dprioin_rtx_term;      // 2-bits
wire [1:0]   dprioin_r_tx_det_rx;   // 2-bit
wire [1:0]   dprioin_rrx_term;      // 2
wire         dprioin_rforce_sigdet; // 1 
wire         dprioin_rrx_dc_couple; // 1 - qpmaused
wire [1:0]   dprioin_rrx_eq_dc;     // 2
wire [2:0]   dprioin_rrx_vtt;       // 3
wire [2:0]   dprioin_rrx_sloslv;    // 3

wire [2:0]   dprioin_reqa_ct;      // 3-bits  - qpmaused
wire [2:0]   dprioin_reqb_ct;      // 3-bit - qpmaused
wire [2:0]   dprioin_reqc_ct;      // 3 - qpmaused
wire [2:0]   dprioin_reqd_ct;      // 3 - qpmaused 
wire [2:0]   dprioin_req_ctv;      // 3 - qpmaused

// pma_ctrl6_ch0_ext: 8074h
wire [1:0]   dprioin_rrx_cru_m_sel;
wire         dprioin_rrx_cru_div2;
wire         dprioin_rltr;
wire         dprioin_rltd;

// pma_ctrl7_ch0_ext: 8078h
wire [3:0]   dprioin_rrx_cru_m;
wire [1:0]   dprioin_rrx_cru_l;

// cru_clock_select
wire [3:0]   dprioin_cru_clock_select;


/////////////////////////////////////////////////////////////////////////////////
// Final CRAM to pass to RTL  -------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire [1:0]    cram_dskwclksel;
wire          cram_is_lane0;         
wire [1:0]    cram_r8b10b_dec_ibm_en;
wire [3:0]    cram_ralempty;
wire [3:0]    cram_ralfull;
wire          cram_rall_one_dect_only;
wire          cram_rautobtalg_dis;   
wire          cram_rautoinsdis;
wire          cram_rbist_clr_rx;         
wire [1:0]    cram_rbist_sel;            
wire          cram_rbisten_rx;           
wire          cram_rbitloc_rev_en;       
wire [1:0]    cram_rbitslip_size;        
wire          cram_rbysync_polinv_en;    
wire          cram_rbyte_rev_en;         
wire [1:0]    cram_rbyteorden;           
wire          cram_rbytord_2sym_en;        
wire [9:0]    cram_rbytordpad;           
wire [9:0]    cram_rbytordpat;           
wire          cram_rbytordplden;         
wire          cram_rcascaded_8b10b_en_rx;
wire [1:0]    cram_rclk_1_sel;    
wire [1:0]    cram_rclk_2_sel;    
wire          cram_rclkcmpinsertpad;
wire          cram_rclkcmppos;
wire [19:0]   cram_rclkcmpsq1n;
wire [19:0]   cram_rclkcmpsq1p;
wire          cram_rclkcmpsqmd;
wire          cram_rcmpfifourst;
wire [39:0]   cram_rcomp_pat;        
wire          cram_rcomp_pat_porn;       
wire [2:0]    cram_rcomp_size;       
wire [1:0]    cram_rcxpat_chnl_en;
wire          cram_rdis_rx_disp;     
wire [9:0]    cram_rdskchrp;
wire          cram_rdskposdisp; 
wire          cram_rdwidth_rx;       
wire          cram_rencdt_rising;        
wire          cram_rendec_data_sel_rx;
wire          cram_rendec_rx;        
wire          cram_renpolinv_rx;
wire [2:0]    cram_renumber;
wire [1:0]    cram_resync_badcg_en;      
wire          cram_rforce_sig_det_pcs;
wire          cram_rforce0_freqdet;
wire          cram_rforce1_freqdet;
wire          cram_rfreerun_rx;   
wire          cram_rgenericfifo;     
wire [7:0]    cram_rgnumber;
wire [1:0]    cram_rib_inv_cd;       
wire          cram_rindv_rx;         
wire          cram_rkchar;
wire [7:0]    cram_rknumber;
wire          cram_rlp20ben;         
wire          cram_rmatchen;         
wire          cram_rosbased;
wire [1:0]    cram_rosnumber;
wire          cram_rphfifo_master_sel_rx;
wire          cram_rphfifopldenrx;       
wire          cram_rphfifourstrx;
wire          cram_rpma_doublewidth_rx;
wire          cram_rpmadwidth_rx;
wire          cram_rppm_cnt_reset;
wire [5:0]    cram_rppmsel;
wire          cram_rprbs_clr_rslt_rx;    
wire [2:0]    cram_rprbs_sel;            
wire          cram_rprbsen_rx;           
wire [1:0]    cram_rrcvd_clk_sel; 
wire          cram_rrlv_en;          
wire [5:0]    cram_rrundisp;         
wire          cram_rrx_rd_clk_sel;
wire          cram_rrx_revlb_sw;
wire          cram_rrxfifo_dis;      
wire          cram_rrxfifo_lowlatency_en;
wire          cram_rskpsetbased;
wire          cram_rs_lpbk;
wire          cram_rsync_sm_dis;     
wire [2:0]    cram_rtest_bus_sel;
wire          cram_rtruebac2bac;
wire          cram_rwa_6g_en;            
wire          cram_scan_mode;                     
wire          cram_sel_gp_md;
                                                 //======= pipe =====
//wire        cram_rclkcmpinsertpad;             // common between rx_digi and pipe	
wire          cram_rphystatus_rst_toggle;        // new in ww29
wire          cram_rrdwidth_rx;                  // rx only
wire          cram_rrx_detect_bypass;            // rx only
wire          cram_rrx_pipe_enable;              // rx only
wire [1:0]    cram_rtx_elec_idle_delay;          // rx only
wire          cram_rtx_pipe_enable;

// PMA
wire [1:0]   cram_rtx_term;      // 2-bits
wire [1:0]   cram_r_tx_det_rx;   // 2-bit
wire [1:0]   cram_rrx_term;      // 2
wire         cram_rforce_sigdet; // 1 
wire         cram_rrx_dc_couple; // 1 - qpmaused
wire [1:0]   cram_rrx_eq_dc;     // 2
wire [2:0]   cram_rrx_vtt;       // 3
wire [2:0]   cram_rrx_sloslv;    // 3

wire [2:0]   cram_reqa_ct;      // 3-bits  - qpmaused
wire [2:0]   cram_reqb_ct;      // 3-bit - qpmaused
wire [2:0]   cram_reqc_ct;      // 3 - qpmaused
wire [2:0]   cram_reqd_ct;      // 3 - qpmaused 
wire [2:0]   cram_req_ctv;      // 3 - qpmaused

// pma_ctrl6_ch0_ext: 8074h
wire [1:0]   cram_rrx_cru_m_sel; // propagated to cdr and dprio_rtl
wire         cram_rrx_cru_div2;  // propagated to cdr and dprio_rtl
wire         cram_rltr;          // dprio_rd_wr
wire         cram_rltd;          // dprio_rd_wr

// pma_ctrl7_ch0_ext: 8078h
wire [3:0]   cram_rrx_cru_m;    // propagated to cdr
wire [1:0]   cram_rrx_cru_l;    // propagated to cdr

// cru_clock_select
wire [3:0]   cram_cru_clock_select;

/////////////////////////////////////////////////////////////////////////////////
// Internal Variables  --------------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////
integer i;
integer j;

reg  [39:0] tmp_reg40;
reg  [2:0]  tmp_rcomp_size;

/////////////////////////////////////////////////////////////////////////////////
// Internal Functions  --------------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

// function to convert at most 40-bit long string to binary
function [39 : 0] m_str_to_bin;
    input [40*8 : 1] s;
    reg   [40*8 : 1] reg_s;
    reg   [7 : 0]    tmp;
    reg   [40:1]     res;

    integer m;
    begin
      
        reg_s = s;
        for (m = 40; m > 0; m = m-1 )
        begin
            tmp = reg_s[320 : 313];
            res[m] = tmp & 8'b00000001;
            reg_s = reg_s << 8;
        end
          
        m_str_to_bin = res;
    end   
endfunction

function [2:0] compute_rprbs_sel_rx;
input          pma_doublewidth;
input          pma_width;
input          test_mode;
reg [8*20:1]   test_mode;
reg [2:0]      res;

begin
    case ({pma_doublewidth, pma_width})
        2'b00 : 
                begin
                    if (test_mode == "PRBS_8" || test_mode == "prbs_8" || test_mode == "prbs8")
                        res = 3'b000;
                    else 
                        res = 3'b111;     // default
                end
        2'b01 :
                begin
                    if (test_mode == "PRBS_10" || test_mode == "prbs_10" || test_mode == "prbs10")
                        res = 3'b000;
                    else 
                        res = 3'b111;     // default
                end
        2'b10 : 
                begin
                    if (test_mode == "PRBS_7" || test_mode == "prbs_7" || test_mode == "prbs7")
                        res = 3'b000;
                    else if (test_mode == "PRBS_23" || test_mode == "prbs_23" || test_mode == "prbs23")
                        res = 3'b001;
                    else 
                        res = 3'b111;     // default
                end
        2'b11 :
                begin
                    if (test_mode == "PRBS_7" || test_mode == "prbs_7" || test_mode == "prbs7")
                        res = 3'b000;
                    else if (test_mode == "PRBS_23" || test_mode == "prbs_23" || test_mode == "prbs23")
                        res = 3'b001;                     
                    else 
                        res = 3'b111;     // default
                end

        default : $display("Invalid pma_doublewidth and pma_width selection");
    endcase
    compute_rprbs_sel_rx = res;
end
endfunction

function [5:0] compute_rrundisp;
input          pma_doublewidth;
input          pma_width;
input          run_len;
integer        run_len;    // without this - it is assumed 1 bit.
integer        run_len_stepped;
reg [5:0]      res;

begin
    case ({pma_doublewidth, pma_width})   // 8-bit
        2'b00 : 
                begin
                    run_len_stepped = run_len / 4;
                    if (run_len_stepped == 32)
                        res = 6'b000000;
                    else
                        res = run_len_stepped;
                end
        2'b01 :                          // 10-bit
                begin
                    run_len_stepped = run_len / 5;
                    if (run_len_stepped == 32)
                        res = 6'b000000;
                    else
                        res = run_len_stepped;
                end
        2'b10 :                          // 16-bit
                begin
                    run_len_stepped = run_len / 8;
                    if (run_len_stepped == 64)
                        res = 6'b000000;
                    else
                        res = run_len_stepped;
                end
        2'b11 :                          // 20-bit
                begin
                    run_len_stepped = run_len / 10;
                    if (run_len_stepped == 64)
                        res = 6'b000000;
                    else
                        res = run_len_stepped;
                end

        default : $display("Invalid pma_doublewidth and pma_width selection");
    endcase
    compute_rrundisp = res;
end
endfunction

/////////////////////////////////////////////////////////////////////////////////
// TIMING -- INPUT BUFFERS  ---------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

wire [8:0]    cruclk_in;
wire [19:0]   parallelfdbk_in;
wire [1:0]    pipepowerdown_in;
wire [3:0]    pipepowerstate_in;
wire [1:0]    rxfound_in;
wire [2:0]    termvoltage_in; 
wire [3:0]    testsel_in; 
wire [7:0]    xgmdatain_in;

wire a1a2size_in;
wire adcepowerdn_in;
wire adcereset_in; 
wire alignstatus_in;
wire alignstatussync_in;
wire analogreset_in;
wire bitslip_in;
wire coreclk_in;
wire crupowerdn_in;
wire crureset_in;
wire datain_in;
wire digitalreset_in;
wire disablefifordin_in;
wire disablefifowrin_in;
wire dpriodisable_in;
wire enabledeskew_in;
wire enabyteord_in;
wire enapatternalign_in;
wire fifordin_in;
wire fiforesetrd_in;
wire ibpowerdn_in; 
wire invpolarity_in;
wire localrefclk_in;
wire locktodata_in; 
wire locktorefclk_in;
wire masterclk_in;
wire phfifordenable_in;
wire phfiforeset_in; 
wire phfifowrdisable_in;
wire phfifox4bytesel_in;
wire phfifox4rdenable_in;
wire phfifox4wrclk_in; 
wire phfifox4wrenable_in; 
wire phfifox8bytesel_in;
wire phfifox8rdenable_in;
wire phfifox8wrclk_in; 
wire phfifox8wrenable_in;
wire pipe8b10binvpolarity_in; 
wire quadreset_in; 
wire refclk_in;
wire revbitorderwa_in;
wire revbyteorderwa_in;
wire rmfifordena_in;
wire rmfiforeset_in;
wire rmfifowrena_in;
wire rxdetectvalid_in;
wire serialfdbk_in;
wire seriallpbken_in;
wire xgmctrlin_in;

wire refclk_in_delayed;  // for x8 slave quad latency reduction in functional sim

buf (a1a2size_in,        a1a2size);
buf (adcepowerdn_in,     adcepowerdn);
buf (adcereset_in,       adcereset); 
buf (alignstatus_in,     alignstatus);
buf (alignstatussync_in, alignstatussync);
buf (analogreset_in,     analogreset);
buf (bitslip_in,         bitslip);
buf (coreclk_in,         coreclk);
buf buf_cruclk [8:0]     (cruclk_in, cruclk); 
buf (crupowerdn_in,      crupowerdn);
buf (crureset_in,        crureset);
buf (datain_in,          datain);
buf (digitalreset_in,    digitalreset);
buf (disablefifordin_in, disablefifordin);
buf (disablefifowrin_in, disablefifowrin);
buf (dpriodisable_in,    dpriodisable);
buf (enabledeskew_in,    enabledeskew);
buf (enabyteord_in,      enabyteord);
buf (enapatternalign_in, enapatternalign);
buf (fifordin_in,        fifordin);
buf (fiforesetrd_in,     fiforesetrd);
buf (ibpowerdn_in,       ibpowerdn); 
buf (invpolarity_in,     invpol);
buf (localrefclk_in,     localrefclk);
buf (locktodata_in,      locktodata); 
buf (locktorefclk_in,    locktorefclk);
buf (masterclk_in,       masterclk);
buf buf_parallelfdbk [19:0] (parallelfdbk_in,  parallelfdbk);
buf (phfifordenable_in,  phfifordenable);
buf (phfiforeset_in,     phfiforeset); 
buf (phfifowrdisable_in, phfifowrdisable);
buf (phfifox4bytesel_in, phfifox4bytesel);
buf (phfifox4rdenable_in,phfifox4rdenable);
buf (phfifox4wrclk_in,   phfifox4wrclk); 
buf (phfifox4wrenable_in,phfifox4wrenable); 
buf (phfifox8bytesel_in, phfifox8bytesel);
buf (phfifox8rdenable_in,phfifox8rdenable);
buf (phfifox8wrclk_in,   phfifox8wrclk); 
buf (phfifox8wrenable_in,phfifox8wrenable);
buf (pipe8b10binvpolarity_in,pipe8b10binvpolarity); 
buf buf_pipepowerdown [1:0] (pipepowerdown_in,   pipepowerdown);
buf buf_pipepowerstate [3:0] (pipepowerstate_in,  pipepowerstate);
buf (quadreset_in,       quadreset); 
buf (refclk_in,          refclk);
buf (revbitorderwa_in,   revbitorderwa);
buf (revbyteorderwa_in,  revbyteorderwa);
buf (rmfifordena_in,     rmfifordena);
buf (rmfiforeset_in,     rmfiforeset);
buf (rmfifowrena_in,     rmfifowrena);
buf (rxdetectvalid_in,   rxdetectvalid);
buf buf_rxfound [1:0] (rxfound_in,  rxfound);
buf (serialfdbk_in,      serialfdbk);
buf (seriallpbken_in,    seriallpbken);
buf buf_termvoltage [2:0] (termvoltage_in,     termvoltage); 
buf buf_testsel [3:0] (testsel_in,         testsel); 
buf (xgmctrlin_in,       xgmctrlin);
buf buf_xgmdatain [7:0] (xgmdatain_in,       xgmdatain);

assign #2 refclk_in_delayed = refclk_in;

/////////////////////////////////////////////////////////////////////////////////
// TIMING -- TCO/TSU/HOLD                                                      //
/////////////////////////////////////////////////////////////////////////////////

specify
    (posedge coreclk => (a1a2sizeout        +: a1a2sizeout_reg))       = (0, 0);
    (posedge coreclk => (ctrldetect         +: ctrldetect_reg))        = (0, 0);
    (posedge coreclk => (dataout            +: dataout_reg))           = (0, 0);
    (posedge coreclk => (disperr            +: disperr_reg))           = (0, 0);
    (posedge coreclk => (errdetect          +: errdetect_reg))         = (0, 0);
    (posedge coreclk => (patterndetect      +: patterndetect_reg))     = (0, 0);
    (posedge coreclk => (rmfifodatadeleted  +: rmfifodatadeleted_reg)) = (0, 0);
    (posedge coreclk => (rmfifodatainserted +: rmfifodatainserted_reg))= (0, 0);
    (posedge coreclk => (runningdisp        +: runningdisp_reg))       = (0, 0);
    (posedge coreclk => (syncstatus         +: syncstatus_reg))        = (0, 0);

    (posedge coreclk => (pipebufferstat[0]     +: pi_out_rxd_ch[13]))  = (0, 0);
    (posedge coreclk => (pipebufferstat[1]     +: pi_out_rxd_ch[14]))  = (0, 0);
    (posedge coreclk => (pipebufferstat[2]     +: pi_out_rxd_ch[45]))  = (0, 0);
    (posedge coreclk => (pipebufferstat[3]     +: pi_out_rxd_ch[46]))  = (0, 0);
    (posedge coreclk => (byteorderalignstatus  +: rd_out_byteord_flag))= (0, 0);
    (posedge coreclk => (phfifooverflow        +: rd_out_full_rx))     = (0, 0);
    (posedge coreclk => (phfifounderflow       +: rd_out_empty_rx))    = (0, 0);
    (posedge coreclk => (pipestatus            +: pi_out_rxstatus))    = (0, 0);
    (posedge coreclk => (pipephydonestatus     +: pi_out_phystatus))   = (0, 0);
    (posedge coreclk => (pipedatavalid         +: pi_out_rxvalid))     = (0, 0);

    // new in 9.1
    (posedge coreclk => (dataoutfull           +: pi_out_rxd_ch))      = (0, 0);
    
    $setuphold(posedge coreclk, phfifordenable, 0, 0);
endspecify

/////////////////////////////////////////////////////////////////////////////////
// dprio outputs                                                               //
/////////////////////////////////////////////////////////////////////////////////
wire [299:0]  dprioin_in;
wire [299:0]  wire_dprioout;

/////////////////////////////////////////////////////////////////////////////////
// inital CRAMs from parameters - CRAM_TABLE 1  -------------------------------//
/////////////////////////////////////////////////////////////////////////////////

initial begin
    // moved up as they can be used by other parameter initialization
	init_rpma_doublewidth_rx = (use_deserializer_double_data_mode == "true") ? 1'b1 : 1'b0;
	init_rpmadwidth_rx      = ((dec_8b_10b_mode == "none") && ((channel_width == 8) || (channel_width == 16) || (channel_width == 32))) ? 1'b0 : 1'b1; // 0 = 8 bit, 1 = 10 bit;

	init_dskwclksel[1]      = (use_deskew_fifo == "true") ? 1'b1 : 1'b0;
	init_dskwclksel[0]      = 1'b0;
	init_is_lane0           = (channel_number == 0) ? 1'b1 : 1'b0;         
	init_r8b10b_dec_ibm_en[0] = (dec_8b_10b_compatibility_mode == "true") ? 1'b1 : 1'b0;
	init_r8b10b_dec_ibm_en[1] = 1'b0;               // reserved
	init_ralempty           = (rate_match_almost_empty_threshold == 11) ? 4'h0 : (16-rate_match_almost_empty_threshold);  // 4-bit
	init_ralfull            = (rate_match_almost_full_threshold == 13) ? 4'h0 : (rate_match_almost_full_threshold-4);     // 4-bit
	init_rall_one_dect_only = (prbs_all_one_detect == "true") ? 1'b1 : 1'b0; 
	init_rautobtalg_dis     = (bit_slip_enable == "true") ? 1'b1 : 1'b0 ;   
	init_rautoinsdis        = (disable_auto_idle_insertion == "true") ? 1'b1 : 1'b0;
	init_rbist_clr_rx       = 1'b0;      // used in bist_ver - not provided to users        
	init_rbist_sel          = (self_test_mode == "cjpat") ? 2'b01 : 
	                          (self_test_mode == "crpat") ? 2'b10 : 2'b00;            
	init_rbisten_rx         = ((enable_self_test_mode == "true") && 
	                           (self_test_mode == "cjpat" || self_test_mode == "crpat" ||
	                            self_test_mode == "incremental")) ? 1'b1 : 1'b0;           
	init_rbitloc_rev_en     = (enable_bit_reversal == "true") ? 1'b1 : 1'b0;       
	init_rbitslip_size      = (datapath_protocol == "pipe") ? 2'b11 : (datapath_protocol == "xaui") ? 2'b10: 2'b00; // expect wys - ICD change - ok with 33 config       
	init_rbysync_polinv_en  = (allow_align_polarity_inversion == "true") ? 1'b1 : 1'b0;    
	init_rbyte_rev_en       = (enable_deep_align_byte_swap == "true") ? 1'b1 : 1'b0;         
	init_rbyteorden         = (byte_ordering_mode == "none") ? 2'b00 :
                              (channel_width == 10 || channel_width == 20 || channel_width == 40) ? 2'b11 :
                              (dec_8b_10b_mode != "none") ? 2'b10 : 2'b01;
	init_rbytord_2sym_en    = 1'b0;        // reserved - 2 symbol matching
    tmp_reg40               = m_str_to_bin(byte_order_pad_pattern);      
	init_rbytordpad         = tmp_reg40[9:0];    // byte_order_pad_pattern into 10'b format           
    tmp_reg40               = m_str_to_bin(byte_order_pattern);      
	init_rbytordpat         = tmp_reg40[9:0];    // byte_order_pattern into 10'b format           
	init_rbytordplden       = (byte_ordering_mode == "pattern-based" || byte_ordering_mode == "pattern based") ? 1'b1 : 1'b0;  // default=0         
	init_rcascaded_8b10b_en_rx = (dec_8b_10b_mode == "cascaded") ? 1'b1 : 1'b0;

	init_rclk_1_sel         = (clk1_mux_select == "RECVD_CLK" || clk1_mux_select == "recvd_clk" || clk1_mux_select == "recovered clock") ? 2'b00 :
                              (clk1_mux_select == "DIGITAL_REFCLK" || clk1_mux_select == "digital_refclk" || clk1_mux_select == "digital reference clock") ? 2'b01 :
                              (clk1_mux_select == "LOCAL_REFCLK" || clk1_mux_select == "local_refclk" || clk1_mux_select == "local reference clock") ? 2'b10 : 
                              (clk1_mux_select == "MASTER_CLK" || clk1_mux_select == "master_clk" || clk1_mux_select == "master clock") ? 2'b11 : 2'bzz;   
							                                 
	init_rclk_2_sel         = (clk2_mux_select == "RECVD_CLK" || clk2_mux_select == "recvd_clk" || clk2_mux_select == "recovered clock") ? 2'b00 :
                              (clk2_mux_select == "DIGITAL_REFCLK" || clk2_mux_select == "digital_refclk" || clk2_mux_select == "digital reference clock") ? 2'b10 :
                              (clk2_mux_select == "LOCAL_REFCLK"  || clk2_mux_select == "local_refclk" || clk2_mux_select == "local reference clock") ? 2'b01 : 
                              (clk2_mux_select == "CORE_CLK" || clk2_mux_select == "core_clk" || clk2_mux_select == "core clk" || clk2_mux_select == "core clock") ? 2'b11 : 2'bzz;

	init_rclkcmpinsertpad   = (insert_pad_on_underflow == "true") ? 1'b1 : 1'b0; 
	init_rclkcmppos         = (use_rate_match_pattern1_only == "true") ? 1'b1 : 1'b0;
    tmp_reg40               = m_str_to_bin(rate_match_pattern2);      
	init_rclkcmpsq1n        = tmp_reg40[19:0];    // convert from rate_match_pattern2          
    tmp_reg40               = m_str_to_bin(rate_match_pattern1);      
	init_rclkcmpsq1p        = tmp_reg40[19:0];    // convert from rate_match_pattern1          
	init_rclkcmpsqmd        = (rate_match_ordered_set_based == "true") ? 1'b1 : 1'b0;   // 2 word deletion for GIGE
	init_rcmpfifourst       = 1'b1;   // internal mode   ** enabled for POF
	init_rcomp_pat          = m_str_to_bin(align_pattern); //40bit from align_pattern with align_pattern_size    
	init_rcomp_pat_porn     = (enable_true_complement_match_in_word_align == "true") ? 1'b1 : 1'b0;       
    
    // when J=8 (3G), pattern is 16-bit but hardware pattern len is 8. We fixed it in software
	tmp_rcomp_size         = (align_pattern_length == 16) ? 
                              ((init_rpmadwidth_rx == 1'b0 && init_rpma_doublewidth_rx == 1'b0) ? 3'b001 : 3'b011)
	                          : 3'bzzz;
	init_rcomp_size         = (align_pattern_length == 7)  ? 3'b000 :
                              (align_pattern_length == 8)  ? 3'b001 :
                              (align_pattern_length == 10) ? 3'b010 :
                              (align_pattern_length == 16) ? tmp_rcomp_size :  // 3'b011
                              (align_pattern_length == 20) ? 3'b100 : 
                              (align_pattern_length == 32) ? 3'b101 : 
                              (align_pattern_length == 40) ? 3'b110 : 
							  3'bzzz;       
	
	init_rcxpat_chnl_en     = (channel_number == 1) ? 2'b01 :               // bist_gen
                              (channel_number == 2) ? 2'b10 :
                              (channel_number == 3) ? 2'b11 : 2'b00;
	init_rdis_rx_disp       = (disable_running_disp_in_word_align == "true") ? 1'b1 : 1'b0;     
    tmp_reg40               = m_str_to_bin(deskew_pattern);      
	init_rdskchrp           = tmp_reg40[9:0];    // convert deskew_pattern
	init_rdskposdisp        = align_to_deskew_pattern_pos_disp_only == "true" ? 1'b1 : 1'b0; 
	init_rdwidth_rx         = (use_double_data_mode == "true") ? 1'b1 : 1'b0;       
	init_rencdt_rising      = (use_rising_edge_triggered_pattern_align == "true") ? 1'b1 : 1'b0;        
	init_rendec_data_sel_rx = (datapath_protocol == "xaui") ? 1'b0 : 1'b1;   // rx_ctrl
	init_rendec_rx          = (dec_8b_10b_mode != "none") ? 1'b1 : 1'b0;        
	init_renpolinv_rx       = (allow_pipe_polarity_inversion == "true") ? 1'b1 : 1'b0;
	init_renumber           = (align_loss_sync_error_num - 1);   // int to 3-bit conversion 
	init_resync_badcg_en    = 2'b00;  // reserved - 6G only    
	init_rforce_sig_det_pcs = (force_signal_detect_dig == "true") ? 1'b1 : 1'b0;
	init_rforce0_freqdet    = (force_freq_det_low == "true") ? 1'b1 : 1'b0;
	init_rforce1_freqdet    = (force_freq_det_high == "true") ? 1'b1 : 1'b0;
	init_rfreerun_rx        = (reset_clock_output_during_digital_reset == "false") ? 1'b1 : 1'b0;   
	init_rgenericfifo       = (rate_match_fifo_mode == "generic" || rate_match_fifo_mode == "cascaded_generic" ||
	                           rate_match_fifo_mode == "cascaded generic") ? 1'b1 : 1'b0;     
	init_rgnumber           = (num_align_cons_good_data - 1);   // int to 8-bit conversion 
	init_rib_inv_cd         = infiniband_invalid_code;    // int to 2-bit conversion        
	init_rindv_rx           = (channel_bonding == "x4" || channel_bonding == "x8" || datapath_protocol == "xaui") ? 1'b0 : 1'b1;         
	init_rkchar             = (disallow_kchar_after_pattern_ordered_set == "true") ? 1'b1 : 1'b0;
	init_rknumber           = (num_align_code_groups_in_ordered_set == 0) ? (num_align_cons_pat - 1) : num_align_cons_pat;     // int to 8-bit conversion 
	init_rlp20ben           = (use_parallel_loopback == "true") ? 1'b1 : 1'b0;         
	init_rmatchen           = (rate_match_fifo_mode != "none") ? 1'b1 : 1'b0;         
	init_rosbased           = (align_ordered_set_based == "true") ? 1'b1 : 1'b0;
	init_rosnumber          = num_align_code_groups_in_ordered_set;  // 2-bit
	init_rphfifo_master_sel_rx = (channel_bonding == "x8") ? 1'b0 : 1'b1;
	init_rphfifopldenrx     = 1'b1;             // internal mode - enable PLD write/read  ** enabled to match ASM   
	init_rphfifourstrx      = 1'b1;             // internal mode - enabled for POF
	init_rppm_cnt_reset     = 1'b0;             // internal mode
	init_rppmsel            = ppmselect;  // int to 6-bit conversion
	init_rprbs_clr_rslt_rx  = 1'b0;                                // default
	init_rprbs_sel          = compute_rprbs_sel_rx(init_rpma_doublewidth_rx,init_rpmadwidth_rx,self_test_mode);    
	init_rprbsen_rx         = ((enable_self_test_mode == "true") && 
	                           (self_test_mode != "incremental") && (self_test_mode != "cjpat") && 
	                           (self_test_mode != "crpat")) ? 1'b1 : 1'b0;           
	init_rrcvd_clk_sel      = (recovered_clk_mux_select == "RECVD_CLK" || recovered_clk_mux_select == "recvd_clk" || recovered_clk_mux_select == "recovered clock") ? 2'b00 :
                              (recovered_clk_mux_select == "DIGITAL_REFCLK" || recovered_clk_mux_select == "digital_refclk" || recovered_clk_mux_select == "digital reference clock") ? 2'b01 :
                              (recovered_clk_mux_select == "LOCAL_REFCLK" || recovered_clk_mux_select == "local_refclk" || recovered_clk_mux_select == "local reference clock") ? 2'b10 : 
                              2'bzz; 
	init_rrlv_en            = (run_length_enable == "true") ? 1'b1 : 1'b0;          
	init_rrundisp           = compute_rrundisp(init_rpma_doublewidth_rx,init_rpmadwidth_rx,run_length); // convert int to 6-bit       
	init_rrx_rd_clk_sel     = (rd_clk_mux_select == "CORE_CLK" || rd_clk_mux_select == "core_clk" || 
	                           rd_clk_mux_select == "core clk" || rd_clk_mux_select == "core clock") ? 1'b1 : 1'b0;
	init_rrx_revlb_sw       = (send_direct_reverse_serial_loopback == "true") ? 1'b0 : 1'b1;   // 0 = pre_cdr          
    init_rrxfifo_dis        = (enable_phfifo_bypass == "true") ? 1'b1 : 1'b0;           // cannot bypass
	init_rrxfifo_lowlatency_en = (disable_ph_low_latency_mode == "false") ? 1'b1 : 1'b0;  // internal mode - default 1
	init_rs_lpbk            = (allow_serial_loopback == "true") ? 1'b1 : 1'b0;          // there is enable port as well          
	init_rskpsetbased       = (rate_match_skip_set_based == "true") ? 1'b1 : 1'b0;
	init_rsync_sm_dis       = (use_align_state_machine == "false") ? 1'b1 : 1'b0;     
	init_rtest_bus_sel      = 3'b000;  // test_bus_sel
	init_rtruebac2bac       = (rate_match_back_to_back == "true") ? 1'b1 : 1'b0;
	init_rwa_6g_en          = (enable_deep_align == "true") ? 1'b1 : 1'b0;            
	init_scan_mode          = 1'b0;                     
	init_sel_gp_md          = 1'b0; // 1=group, 0=quad - hard wired in centrl_chnl.v

                                          //======= pipe =====
    //init_rclkcmpinsertpad    = 1'b1;    // common between rx_digi and pipe	
	init_rphystatus_rst_toggle = (phystatus_reset_toggle == "true") ? 1'b1 : 1'b0;  // default 0
    init_rrdwidth_rx         = (use_double_data_mode == "true") ? 1'b1 : 1'b0;
    init_rrx_detect_bypass   = (rx_detect_bypass == "true") ? 1'b1 : 1'b0;     
    init_rrx_pipe_enable     = (datapath_protocol == "pipe") ? 1'b1 : 1'b0; 
    init_rtx_elec_idle_delay = 2'b00;    // not modeled - delay numbers
    init_rtx_pipe_enable = 1'b0;
    
    // PMA
    init_rtx_term      = 2'bzz;      // 2-bits
    init_r_tx_det_rx   = 2'bzz;      // 2-bit
    init_rrx_term      = 2'bzz;      // 2
    init_rforce_sigdet = 2'bzz;      // 1 
    init_rrx_dc_couple = 1'bz;       // 1 
    init_rrx_eq_dc     = equalizer_dc_gain;     // 2- qpmaused
    init_rrx_vtt       = 3'bzzz;     // 3
    init_rrx_sloslv    = 3'bzzz;     // 3

    init_reqa_ct       = equalizer_ctrl_a;      // 3-bits  - qpmaused
    init_reqb_ct       = equalizer_ctrl_b;      // 3-bit - qpmaused
    init_reqc_ct       = equalizer_ctrl_c;      // 3 - qpmaused
    init_reqd_ct       = equalizer_ctrl_d;      // 3 - qpmaused 
    init_req_ctv       = equalizer_ctrl_v;      // 3 - qpmaused

    // pma_ctrl6_ch0_ext: 8074h
    init_rrx_cru_m_sel = (cru_pre_divide_by == 2) ? 2'b01 :
                         ((cru_pre_divide_by == 4) || (cru_pre_divide_by == 8)) ? 2'b10 : 2'b00;
    init_rrx_cru_div2  = (cru_pre_divide_by == 8) ? 1'b1 : 1'b0;
    init_rltr          = (enable_lock_to_refclk_sig == "true") ? 1'b1 : 1'b0;
    init_rltd          = (enable_lock_to_data_sig == "true") ? 1'b1 : 1'b0;

    // pma_ctrl7_ch0_ext: 8078h
    init_rrx_cru_m     = (cru_multiply_by == 4)  ? 4'b0010 :
                         (cru_multiply_by == 5)  ? 4'b0011 :
                         (cru_multiply_by == 8)  ? 4'b0100 :
                         (cru_multiply_by == 10) ? 4'b0101 :
                         (cru_multiply_by == 16) ? 4'b0110 :
                         (cru_multiply_by == 20) ? 4'b0111 :
                         (cru_multiply_by == 25) ? 4'b1000 : 4'b0000;
    init_rrx_cru_l     = (cru_divide_by == 2) ? 2'b01 :
                         (cru_divide_by == 4) ? 2'b10 : 2'b00;

    init_cru_clock_select = (cru_clock_select >= 0 && cru_clock_select < 10) ? cru_clock_select : 4'b0000;    
end

/////////////////////////////////////////////////////////////////////////////////
// Set DPRIO input CRAM from dprioin - CRAM_Table 2A  -------------------------//
/////////////////////////////////////////////////////////////////////////////////

assign dprioin_in   = dprioin;

assign dprioin_dskwclksel          = init_dskwclksel;
assign dprioin_is_lane0            = init_is_lane0;
assign dprioin_r8b10b_dec_ibm_en   = dprioin_in[`r8b10b_dec_ibm_en_RX_IDX_1 : `r8b10b_dec_ibm_en_RX_IDX_0];
assign dprioin_ralempty            = dprioin_in[`ralempty_RX_IDX_3 : `ralempty_RX_IDX_0];
assign dprioin_ralfull             = dprioin_in[`ralfull_RX_IDX_3 : `ralfull_RX_IDX_0];
assign dprioin_rall_one_dect_only  = init_rall_one_dect_only;
assign dprioin_rautobtalg_dis      = dprioin_in[`rautobtalg_dis_RX_IDX];
assign dprioin_rautoinsdis         = dprioin_in[`rautoinsdis_RX_IDX];
assign dprioin_rbist_clr_rx        = init_rbist_clr_rx;
assign dprioin_rbist_sel           = init_rbist_sel;
assign dprioin_rbisten_rx          = init_rbisten_rx;
assign dprioin_rbitloc_rev_en      = dprioin_in[`rbitloc_rev_en_RX_IDX];
assign dprioin_rbitslip_size       = dprioin_in[`rbitslip_size_RX_IDX_1 : `rbitslip_size_RX_IDX_0];
assign dprioin_rbysync_polinv_en   = dprioin_in[`rbysync_polinv_en_RX_IDX];
assign dprioin_rbyte_rev_en        = dprioin_in[`rbyte_rev_en_RX_IDX];
assign dprioin_rbyteorden          = dprioin_in[`rbyteorden_RX_IDX_1 : `rbyteorden_RX_IDX_0];
assign dprioin_rbytord_2sym_en     = dprioin_in[`rbytord_2sym_en_RX_IDX];
assign dprioin_rbytordpad          = dprioin_in[`rbytordpad_RX_IDX_9 : `rbytordpad_RX_IDX_0];
assign dprioin_rbytordpat          = dprioin_in[`rbytordpat_RX_IDX_9 : `rbytordpat_RX_IDX_0];
assign dprioin_rbytordplden        = dprioin_in[`rbytordplden_RX_IDX];
assign dprioin_rcascaded_8b10b_en_rx = dprioin_in[`rcascaded_8b10b_en_rx_RX_IDX];
assign dprioin_rclk_1_sel          = dprioin_in[`rclk_1_sel_RX_IDX_1 : `rclk_1_sel_RX_IDX_0]; // dprio
assign dprioin_rclk_2_sel          = dprioin_in[`rclk_2_sel_RX_IDX_1 : `rclk_2_sel_RX_IDX_0]; // dprio_enabled
assign dprioin_rclkcmpinsertpad    = dprioin_in[`rclkcmpinsertpad_RX_IDX];
assign dprioin_rclkcmppos          = dprioin_in[`rclkcmppos_RX_IDX];
assign dprioin_rclkcmpsq1n         = dprioin_in[`rclkcmpsq1n_RX_IDX_19 : `rclkcmpsq1n_RX_IDX_0];
assign dprioin_rclkcmpsq1p         = dprioin_in[`rclkcmpsq1p_RX_IDX_19 : `rclkcmpsq1p_RX_IDX_0];
assign dprioin_rclkcmpsqmd         = dprioin_in[`rclkcmpsqmd_RX_IDX];
assign dprioin_rcmpfifourst        = dprioin_in[`rcmpfifourst_RX_IDX];
assign dprioin_rcomp_pat           = dprioin_in[`rcomp_pat_RX_IDX_39 : `rcomp_pat_RX_IDX_0];
assign dprioin_rcomp_pat_porn      = dprioin_in[`rcomp_pat_porn_RX_IDX];
assign dprioin_rcomp_size          = dprioin_in[`rcomp_size_RX_IDX_2 : `rcomp_size_RX_IDX_0];
assign dprioin_rcxpat_chnl_en      = init_rcxpat_chnl_en;
assign dprioin_rdis_rx_disp        = dprioin_in[`rdis_rx_disp_RX_IDX];
assign dprioin_rdskchrp            = init_rdskchrp;
assign dprioin_rdskposdisp         = init_rdskposdisp;
assign dprioin_rdwidth_rx          = dprioin_in[`rdwidth_rx_RX_IDX];
assign dprioin_rencdt_rising       = dprioin_in[`rencdt_rising_RX_IDX];
assign dprioin_rendec_data_sel_rx  = dprioin_in[`rendec_data_sel_rx_RX_IDX];
assign dprioin_rendec_rx           = dprioin_in[`rendec_rx_RX_IDX];
assign dprioin_renpolinv_rx        = dprioin_in[`renpolinv_rx_RX_IDX];
assign dprioin_renumber            = dprioin_in[`renumber_RX_IDX_2 : `renumber_RX_IDX_0];
assign dprioin_resync_badcg_en     = init_resync_badcg_en;
assign dprioin_rforce_sig_det_pcs  = dprioin_in[`rforce_sig_det_pcs_RX_IDX];
assign dprioin_rforce0_freqdet     = dprioin_in[`rforce0_freqdet_RX_IDX];
assign dprioin_rforce1_freqdet     = dprioin_in[`rforce1_freqdet_RX_IDX];
assign dprioin_rfreerun_rx         = dprioin_in[`rfreerun_rx_RX_IDX];
assign dprioin_rgenericfifo        = dprioin_in[`rgenericfifo_RX_IDX];
assign dprioin_rgnumber            = dprioin_in[`rgnumber_RX_IDX_7 : `rgnumber_RX_IDX_0];
assign dprioin_rib_inv_cd          = dprioin_in[`rib_inv_cd_RX_IDX_1 : `rib_inv_cd_RX_IDX_0];
assign dprioin_rindv_rx            = dprioin_in[`rindv_rx_RX_IDX];
assign dprioin_rkchar              = dprioin_in[`rkchar_RX_IDX];
assign dprioin_rknumber            = dprioin_in[`rknumber_RX_IDX_7 : `rknumber_RX_IDX_0];
assign dprioin_rlp20ben            = dprioin_in[`rlp20ben_RX_IDX];
assign dprioin_rmatchen            = dprioin_in[`rmatchen_RX_IDX];
assign dprioin_rosbased            = dprioin_in[`rosbased_RX_IDX];
assign dprioin_rosnumber           = dprioin_in[`rosnumber_RX_IDX_1 : `rosnumber_RX_IDX_0];
assign dprioin_rphfifo_master_sel_rx = dprioin_in[`rphfifo_master_sel_rx_RX_IDX];
assign dprioin_rphfifopldenrx      = dprioin_in[`rphfifopldenrx_RX_IDX];
assign dprioin_rphfifourstrx       = dprioin_in[`rphfifourstrx_RX_IDX];
assign dprioin_rpma_doublewidth_rx = dprioin_in[`rpma_doublewidth_rx_RX_IDX]; // dprioin
assign dprioin_rpmadwidth_rx       = dprioin_in[`rpmadwidth_rx_RX_IDX];    // dprioin
assign dprioin_rppm_cnt_reset      = dprioin_in[`rppm_cnt_reset_RX_IDX];
assign dprioin_rppmsel             = dprioin_in[`rppmsel_RX_IDX_5 : `rppmsel_RX_IDX_0];
assign dprioin_rprbs_clr_rslt_rx   = init_rprbs_clr_rslt_rx;
assign dprioin_rprbs_sel           = init_rprbs_sel;
assign dprioin_rprbsen_rx          = init_rprbsen_rx;
assign dprioin_rrcvd_clk_sel       = dprioin_in[`rrcvd_clk_sel_RX_IDX_1 : `rrcvd_clk_sel_RX_IDX_0]; // dprio
assign dprioin_rrlv_en             = dprioin_in[`rrlv_en_RX_IDX];
assign dprioin_rrundisp            = dprioin_in[`rrundisp_RX_IDX_5 : `rrundisp_RX_IDX_0];
assign dprioin_rrx_rd_clk_sel      = dprioin_in[`rrx_rd_clk_sel_RX_IDX];
assign dprioin_rrx_revlb_sw        = dprioin_in[`rrx_revlb_sw_RX_IDX];
assign dprioin_rrxfifo_dis         = dprioin_in[`rrxfifo_dis_RX_IDX];
assign dprioin_rrxfifo_lowlatency_en = dprioin_in[`rrxfifo_lowlatency_en_RX_IDX];
assign dprioin_rs_lpbk             = dprioin_in[`rs_lpbk_RX_IDX];
assign dprioin_rskpsetbased        = dprioin_in[`rskpsetbased_RX_IDX];
assign dprioin_rsync_sm_dis        = dprioin_in[`rsync_sm_dis_RX_IDX];
assign dprioin_rtest_bus_sel       = init_rtest_bus_sel;
assign dprioin_rtruebac2bac        = dprioin_in[`rtruebac2bac_RX_IDX];
assign dprioin_rwa_6g_en           = dprioin_in[`rwa_6g_en_RX_IDX];
assign dprioin_scan_mode           = init_scan_mode;
assign dprioin_sel_gp_md           = init_sel_gp_md;
assign dprioin_rphystatus_rst_toggle = init_rphystatus_rst_toggle;  // new in ww29
assign dprioin_rrdwidth_rx         = dprioin_in[`rdwidth_rx_RX_IDX];
assign dprioin_rrx_detect_bypass   = dprioin_in[`rrx_detect_bypass_RX_IDX];
assign dprioin_rrx_pipe_enable     = dprioin_in[`rrx_pipe_enable_RX_IDX];
assign dprioin_rtx_elec_idle_delay = dprioin_in[`rtx_idle_delay_RX_IDX_1 : `rtx_idle_delay_RX_IDX_0];
assign dprioin_rtx_pipe_enable     = init_rtx_pipe_enable;

// PMA
// pma_ctrl2: 4.8064-4.8067 (rx)
assign dprioin_rtx_term     = dprioin_in[`rtx_term_RX_IDX_1    : `rtx_term_RX_IDX_0];      // 2-bits
assign dprioin_r_tx_det_rx  = dprioin_in[`r_tx_det_rx_RX_IDX_1 : `r_tx_det_rx_RX_IDX_0];   // 2-bit
assign dprioin_rrx_term     = dprioin_in[`rrx_term_RX_IDX_1    : `rrx_term_RX_IDX_0];      // 2
assign dprioin_rforce_sigdet= dprioin_in[`rforce_sigdet_RX_IDX];                      // 1 
assign dprioin_rrx_dc_couple= dprioin_in[`rrx_dc_couple_RX_IDX];                      // 1
assign dprioin_rrx_eq_dc    = dprioin_in[`rrx_eq_dc_RX_IDX_1   : `rrx_eq_dc_RX_IDX_0];     // 2 - qpmaused
assign dprioin_rrx_vtt      = dprioin_in[`rrx_vtt_RX_IDX_2     : `rrx_vtt_RX_IDX_0];       // 3
assign dprioin_rrx_sloslv   = dprioin_in[`rrx_sloslv_RX_IDX_2  : `rrx_sloslv_RX_IDX_0];    // 3

// pma_ctrl3: 4.8068-4.806b (rx)
assign dprioin_reqa_ct     = dprioin_in[`reqa_ct_RX_IDX_2     : `reqa_ct_RX_IDX_0]; // 3-bits  - qpmaused
assign dprioin_reqb_ct     = dprioin_in[`reqb_ct_RX_IDX_2     : `reqb_ct_RX_IDX_0]; // 3-bit - qpmaused
assign dprioin_reqc_ct     = dprioin_in[`reqc_ct_RX_IDX_2     : `reqc_ct_RX_IDX_0];   // 3 - qpmaused
assign dprioin_reqd_ct     = dprioin_in[`reqd_ct_RX_IDX_2     : `reqd_ct_RX_IDX_0];   // 3 - qpmaused
assign dprioin_req_ctv     = dprioin_in[`req_ctv_RX_IDX_2     : `req_ctv_RX_IDX_0];   // 3 - qpmaused

// pma_ctrl6: 8074h
assign dprioin_rrx_cru_m_sel = dprioin_in[`rrx_cru_m_sel_RX_IDX_1 : `rrx_cru_m_sel_RX_IDX_0]; // cru_pre_divide_by
assign dprioin_rrx_cru_div2  = dprioin_in[`rrx_cru_div2_RX_IDX];
assign dprioin_rltr          = dprioin_in[`rltr_RX_IDX];
assign dprioin_rltd          = dprioin_in[`rltd_RX_IDX];

// pma_ctrl7_ch0_ext: 8078h
assign dprioin_rrx_cru_m     = dprioin_in[`rrx_cru_m_RX_IDX_3 : `rrx_cru_m_RX_IDX_0];
assign dprioin_rrx_cru_l     = dprioin_in[`rrx_cru_l_RX_IDX_1 : `rrx_cru_l_RX_IDX_0];  // cru_divide_by

assign dprioin_cru_clock_select = dprioin_in[`cru_clock_select_RX_IDX_3 : `cru_clock_select_RX_IDX_0];


/////////////////////////////////////////////////////////////////////////////////
// Set DPRIO reg with initial parameters - CRAM_Table 2B  ---------------------//
/////////////////////////////////////////////////////////////////////////////////

// Index based for PCS
// make sure left is wire_dprioout ***
assign  wire_dprioout[`r8b10b_dec_ibm_en_RX_IDX_1 : `r8b10b_dec_ibm_en_RX_IDX_0] = init_r8b10b_dec_ibm_en;
assign  wire_dprioout[`ralempty_RX_IDX_3          : `ralempty_RX_IDX_0]          = init_ralempty;
assign  wire_dprioout[`ralfull_RX_IDX_3           : `ralfull_RX_IDX_0]           = init_ralfull;
assign  wire_dprioout[`rautobtalg_dis_RX_IDX]                                    = init_rautobtalg_dis;
assign  wire_dprioout[`rautoinsdis_RX_IDX]                                       = init_rautoinsdis;
assign  wire_dprioout[`rbitloc_rev_en_RX_IDX]                                    = init_rbitloc_rev_en;
assign  wire_dprioout[`rbitslip_size_RX_IDX_1     : `rbitslip_size_RX_IDX_0]     = init_rbitslip_size;
assign  wire_dprioout[`rbysync_polinv_en_RX_IDX]                                 = init_rbysync_polinv_en;
assign  wire_dprioout[`rbyte_rev_en_RX_IDX]                                      = init_rbyte_rev_en;
assign  wire_dprioout[`rbyteorden_RX_IDX_1        : `rbyteorden_RX_IDX_0]        = init_rbyteorden;
assign  wire_dprioout[`rbytord_2sym_en_RX_IDX]                                   = init_rbytord_2sym_en;
assign  wire_dprioout[`rbytordpad_RX_IDX_9        : `rbytordpad_RX_IDX_0]        = init_rbytordpad;
assign  wire_dprioout[`rbytordpat_RX_IDX_9        : `rbytordpat_RX_IDX_0]        = init_rbytordpat;
assign  wire_dprioout[`rbytordplden_RX_IDX]                                      = init_rbytordplden;
assign  wire_dprioout[`rcascaded_8b10b_en_rx_RX_IDX]                             = init_rcascaded_8b10b_en_rx;
assign  wire_dprioout[`rclk_1_sel_RX_IDX_1        : `rclk_1_sel_RX_IDX_0]        = init_rclk_1_sel;
assign  wire_dprioout[`rclk_2_sel_RX_IDX_1        : `rclk_2_sel_RX_IDX_0]        = init_rclk_2_sel;
assign  wire_dprioout[`rclkcmpinsertpad_RX_IDX]                                  = init_rclkcmpinsertpad;
assign  wire_dprioout[`rclkcmppos_RX_IDX]                                        = init_rclkcmppos;
assign  wire_dprioout[`rclkcmpsq1n_RX_IDX_19      : `rclkcmpsq1n_RX_IDX_0]       = init_rclkcmpsq1n;
assign  wire_dprioout[`rclkcmpsq1p_RX_IDX_19      : `rclkcmpsq1p_RX_IDX_0]       = init_rclkcmpsq1p;
assign  wire_dprioout[`rclkcmpsqmd_RX_IDX]                                       = init_rclkcmpsqmd;
assign  wire_dprioout[`rcmpfifourst_RX_IDX]                                      = init_rcmpfifourst;
assign  wire_dprioout[`rcomp_pat_RX_IDX_39        : `rcomp_pat_RX_IDX_0]         = init_rcomp_pat;
assign  wire_dprioout[`rcomp_pat_porn_RX_IDX]                                    = init_rcomp_pat_porn;
assign  wire_dprioout[`rcomp_size_RX_IDX_2        : `rcomp_size_RX_IDX_0]        = init_rcomp_size;
assign  wire_dprioout[`rdis_rx_disp_RX_IDX]                                      = init_rdis_rx_disp;
assign  wire_dprioout[`rdwidth_rx_RX_IDX]                                        = init_rdwidth_rx;
assign  wire_dprioout[`rencdt_rising_RX_IDX]                                     = init_rencdt_rising;
assign  wire_dprioout[`rendec_data_sel_rx_RX_IDX]                                = init_rendec_data_sel_rx;
assign  wire_dprioout[`rendec_rx_RX_IDX]                                         = init_rendec_rx;
assign  wire_dprioout[`renpolinv_rx_RX_IDX]                                      = init_renpolinv_rx;
assign  wire_dprioout[`renumber_RX_IDX_2          : `renumber_RX_IDX_0]          = init_renumber;
assign  wire_dprioout[`rforce_sig_det_pcs_RX_IDX]                                = init_rforce_sig_det_pcs;
assign  wire_dprioout[`rforce0_freqdet_RX_IDX]                                   = init_rforce0_freqdet;
assign  wire_dprioout[`rforce1_freqdet_RX_IDX]                                   = init_rforce1_freqdet;
assign  wire_dprioout[`rfreerun_rx_RX_IDX]                                       = init_rfreerun_rx;
assign  wire_dprioout[`rgenericfifo_RX_IDX]                                      = init_rgenericfifo;
assign  wire_dprioout[`rgnumber_RX_IDX_7          : `rgnumber_RX_IDX_0]          = init_rgnumber;
assign  wire_dprioout[`rib_inv_cd_RX_IDX_1        : `rib_inv_cd_RX_IDX_0]        = init_rib_inv_cd;
assign  wire_dprioout[`rindv_rx_RX_IDX]                                          = init_rindv_rx;
assign  wire_dprioout[`rkchar_RX_IDX]                                            = init_rkchar;
assign  wire_dprioout[`rknumber_RX_IDX_7          : `rknumber_RX_IDX_0]          = init_rknumber;
assign  wire_dprioout[`rlp20ben_RX_IDX]                                          = init_rlp20ben;
assign  wire_dprioout[`rmatchen_RX_IDX]                                          = init_rmatchen;
assign  wire_dprioout[`rosbased_RX_IDX]                                          = init_rosbased;
assign  wire_dprioout[`rosnumber_RX_IDX_1         : `rosnumber_RX_IDX_0]         = init_rosnumber;
assign  wire_dprioout[`rphfifo_master_sel_rx_RX_IDX]                             = init_rphfifo_master_sel_rx;
assign  wire_dprioout[`rphfifopldenrx_RX_IDX]                                    = init_rphfifopldenrx;
assign  wire_dprioout[`rphfifourstrx_RX_IDX]                                     = init_rphfifourstrx;
assign  wire_dprioout[`rpma_doublewidth_rx_RX_IDX]                               = init_rpma_doublewidth_rx;
assign  wire_dprioout[`rpmadwidth_rx_RX_IDX]                                     = init_rpmadwidth_rx;
assign  wire_dprioout[`rppm_cnt_reset_RX_IDX]                                    = init_rppm_cnt_reset;
assign  wire_dprioout[`rppmsel_RX_IDX_5           : `rppmsel_RX_IDX_0]           = init_rppmsel;
assign  wire_dprioout[`rrcvd_clk_sel_RX_IDX_1     : `rrcvd_clk_sel_RX_IDX_0]     = init_rrcvd_clk_sel;
assign  wire_dprioout[`rrlv_en_RX_IDX]                                           = init_rrlv_en;
assign  wire_dprioout[`rrundisp_RX_IDX_5          : `rrundisp_RX_IDX_0]          = init_rrundisp;
assign  wire_dprioout[`rrx_rd_clk_sel_RX_IDX]                                    = init_rrx_rd_clk_sel;
assign  wire_dprioout[`rrxfifo_dis_RX_IDX]                                       = init_rrxfifo_dis;
assign  wire_dprioout[`rrxfifo_lowlatency_en_RX_IDX]                             = init_rrxfifo_lowlatency_en;
assign  wire_dprioout[`rskpsetbased_RX_IDX]                                      = init_rskpsetbased;
assign  wire_dprioout[`rsync_sm_dis_RX_IDX]                                      = init_rsync_sm_dis;
assign  wire_dprioout[`rtruebac2bac_RX_IDX]                                      = init_rtruebac2bac;
assign  wire_dprioout[`rwa_6g_en_RX_IDX]                                         = init_rwa_6g_en;
assign  wire_dprioout[`rdwidth_rx_RX_IDX]                                        = init_rrdwidth_rx;
assign  wire_dprioout[`rrx_detect_bypass_RX_IDX]                                 = init_rrx_detect_bypass;
assign  wire_dprioout[`rrx_pipe_enable_RX_IDX]                                   = init_rrx_pipe_enable;
assign  wire_dprioout[`rtx_idle_delay_RX_IDX_1    : `rtx_idle_delay_RX_IDX_0]    = init_rtx_elec_idle_delay;

assign wire_dprioout[`rpowdnr_RX_IDX]           = 1'b0; // init_rpowdnr_md[0];
assign wire_dprioout[`rrxurstpcs_RX_IDX]        = 1'b1; // init_rrxurstpcs;
assign wire_dprioout[`rrsvd_rx_RX_IDX_2 : `rrsvd_rx_RX_IDX_0] = 3'b000;  // init_rrsvd_rx; 

// make sure left is wire_dprioout ***


// pma_ctrl2: 4.8064-4.8067 (rx)
assign wire_dprioout[`rtx_term_RX_IDX_1    : `rtx_term_RX_IDX_0]    = init_rtx_term;          // 2-bits
assign wire_dprioout[`r_tx_det_rx_RX_IDX_1 : `r_tx_det_rx_RX_IDX_0] = init_r_tx_det_rx;       // 2-bit
assign wire_dprioout[`rrx_term_RX_IDX_1    : `rrx_term_RX_IDX_0]    = init_rrx_term;          // 2
assign wire_dprioout[`rrx_dc_couple_RX_IDX]                            = init_rforce_sigdet;     // 1 
assign wire_dprioout[`rrx_dc_couple_RX_IDX]                            = init_rrx_dc_couple;     // 1
assign wire_dprioout[`rrx_eq_dc_RX_IDX_1   : `rrx_eq_dc_RX_IDX_0]   = init_rrx_eq_dc;         // 2 - qpmaused
assign wire_dprioout[`rrx_vtt_RX_IDX_2     : `rrx_vtt_RX_IDX_0]     = init_rrx_vtt;           // 3
assign wire_dprioout[`rrx_sloslv_RX_IDX_2  : `rrx_sloslv_RX_IDX_0]  = init_rrx_sloslv;        // 3

// pma_ctrl3: 4.8068-4.806b (rx)
assign wire_dprioout[`reqa_ct_RX_IDX_2 : `reqa_ct_RX_IDX_0] = init_reqa_ct;    // 3-bits  - qpmaused
assign wire_dprioout[`reqb_ct_RX_IDX_2 : `reqb_ct_RX_IDX_0] = init_reqb_ct;    // 3-bit - qpmaused
assign wire_dprioout[`reqc_ct_RX_IDX_2 : `reqc_ct_RX_IDX_0]  = init_reqc_ct;    // 3 - qpmaused
assign wire_dprioout[`reqd_ct_RX_IDX_2 : `reqd_ct_RX_IDX_0]  = init_reqd_ct;    // 3 - qpmaused 
assign wire_dprioout[`req_ctv_RX_IDX_2 : `req_ctv_RX_IDX_0]  = init_req_ctv;    // 3 - qpmaused

// pma_ctrl6: 4.8074-4.8077 (rx)
assign wire_dprioout[`rrx_cru_m_sel_RX_IDX_1 : `rrx_cru_m_sel_RX_IDX_0] = init_rrx_cru_m_sel; 
assign wire_dprioout[`rrx_cru_div2_RX_IDX]        = init_rrx_cru_div2;                  
assign wire_dprioout[`rltr_RX_IDX]                = init_rltr;                  
assign wire_dprioout[`rltd_RX_IDX]                = init_rltd;  
                
// pma_ctrl7: 4.8078-4.807B (rx)
assign wire_dprioout[`rrx_cru_m_RX_IDX_3 : `rrx_cru_m_RX_IDX_0] = init_rrx_cru_m; 
assign wire_dprioout[`rrx_cru_l_RX_IDX_1 : `rrx_cru_l_RX_IDX_0] = init_rrx_cru_l; 

// pma_ctrl8 (rx portion)
assign wire_dprioout[`rs_lpbk_RX_IDX]             = init_rs_lpbk; 
assign wire_dprioout[`rrx_revlb_sw_RX_IDX]       = init_rrx_revlb_sw; 

assign wire_dprioout[`cru_clock_select_RX_IDX_3 : `cru_clock_select_RX_IDX_0] = init_cru_clock_select;

/////////////////////////////////////////////////////////////////////////////////
// select CRAMs between DPIRO vs. parameters  ---------------------------------//
/////////////////////////////////////////////////////////////////////////////////
wire   mpcs_dpriodisable;
assign mpcs_dpriodisable = 1'b1;

assign cram_dskwclksel         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_dskwclksel        : dprioin_dskwclksel;
assign cram_is_lane0           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_is_lane0          : dprioin_is_lane0;
assign cram_r8b10b_dec_ibm_en  = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_r8b10b_dec_ibm_en : dprioin_r8b10b_dec_ibm_en;
assign cram_ralempty           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_ralempty          : dprioin_ralempty;
assign cram_ralfull            = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_ralfull           : dprioin_ralfull;
assign cram_rall_one_dect_only = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rall_one_dect_only : dprioin_rall_one_dect_only;
assign cram_rautobtalg_dis     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rautobtalg_dis    : dprioin_rautobtalg_dis;
assign cram_rautoinsdis        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rautoinsdis       : dprioin_rautoinsdis;
assign cram_rbist_clr_rx       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbist_clr_rx      : dprioin_rbist_clr_rx;
assign cram_rbist_sel          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbist_sel         : dprioin_rbist_sel;
assign cram_rbisten_rx         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbisten_rx        : dprioin_rbisten_rx;
assign cram_rbitloc_rev_en     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbitloc_rev_en    : dprioin_rbitloc_rev_en;
assign cram_rbitslip_size      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbitslip_size     : dprioin_rbitslip_size;
assign cram_rbysync_polinv_en  = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbysync_polinv_en : dprioin_rbysync_polinv_en;
assign cram_rbyte_rev_en       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbyte_rev_en      : dprioin_rbyte_rev_en;
assign cram_rbyteorden         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbyteorden        : dprioin_rbyteorden;
assign cram_rbytord_2sym_en    = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbytord_2sym_en   : dprioin_rbytord_2sym_en;
assign cram_rbytordpad         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbytordpad        : dprioin_rbytordpad;
assign cram_rbytordpat         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbytordpat        : dprioin_rbytordpat;
assign cram_rbytordplden       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rbytordplden      : dprioin_rbytordplden;
assign cram_rcascaded_8b10b_en_rx = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rcascaded_8b10b_en_rx : dprioin_rcascaded_8b10b_en_rx;
assign cram_rclk_1_sel         = (dpriodisable !== 1'b0) ? init_rclk_1_sel        : dprioin_rclk_1_sel;  // dprio_enabled prior to 6.1
assign cram_rclk_2_sel         = (dpriodisable !== 1'b0) ? init_rclk_2_sel        : dprioin_rclk_2_sel;  // dprio_enabled prior to 6.1
assign cram_rclkcmpinsertpad   = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rclkcmpinsertpad  : dprioin_rclkcmpinsertpad;
assign cram_rclkcmppos         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rclkcmppos        : dprioin_rclkcmppos; 
assign cram_rclkcmpsq1n        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rclkcmpsq1n       : dprioin_rclkcmpsq1n;
assign cram_rclkcmpsq1p        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rclkcmpsq1p       : dprioin_rclkcmpsq1p;
assign cram_rclkcmpsqmd        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rclkcmpsqmd       : dprioin_rclkcmpsqmd;
assign cram_rcmpfifourst       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rcmpfifourst      : dprioin_rcmpfifourst;
assign cram_rcomp_pat          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rcomp_pat         : dprioin_rcomp_pat;
assign cram_rcomp_pat_porn     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rcomp_pat_porn    : dprioin_rcomp_pat_porn;
assign cram_rcomp_size         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rcomp_size        : dprioin_rcomp_size;
assign cram_rcxpat_chnl_en     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rcxpat_chnl_en    : dprioin_rcxpat_chnl_en;
assign cram_rdis_rx_disp       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rdis_rx_disp      : dprioin_rdis_rx_disp;
assign cram_rdskchrp           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rdskchrp          : dprioin_rdskchrp;
assign cram_rdskposdisp        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rdskposdisp       : dprioin_rdskposdisp;
assign cram_rdwidth_rx         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rdwidth_rx        : dprioin_rdwidth_rx;
assign cram_rencdt_rising      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rencdt_rising     : dprioin_rencdt_rising;
assign cram_rendec_data_sel_rx = init_rendec_data_sel_rx;       // disable reconfiguration for quad-level crams 
assign cram_rendec_rx          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rendec_rx         : dprioin_rendec_rx;
assign cram_renpolinv_rx       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_renpolinv_rx      : dprioin_renpolinv_rx;
assign cram_renumber           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_renumber          : dprioin_renumber;
assign cram_resync_badcg_en    = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_resync_badcg_en   : dprioin_resync_badcg_en;
assign cram_rforce_sig_det_pcs = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rforce_sig_det_pcs: dprioin_rforce_sig_det_pcs;
assign cram_rforce0_freqdet    = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rforce0_freqdet   : dprioin_rforce0_freqdet;
assign cram_rforce1_freqdet    = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rforce1_freqdet   : dprioin_rforce1_freqdet;
assign cram_rfreerun_rx        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rfreerun_rx       : dprioin_rfreerun_rx;
assign cram_rgenericfifo       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rgenericfifo      : dprioin_rgenericfifo;
assign cram_rgnumber           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rgnumber          : dprioin_rgnumber;
assign cram_rib_inv_cd         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rib_inv_cd        : dprioin_rib_inv_cd;
assign cram_rindv_rx           = init_rindv_rx;                  // disable reconfiguration for quad-level crams
assign cram_rkchar             = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rkchar            : dprioin_rkchar;
assign cram_rknumber           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rknumber          : dprioin_rknumber;
assign cram_rlp20ben           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rlp20ben          : dprioin_rlp20ben;
assign cram_rmatchen           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rmatchen          : dprioin_rmatchen;
assign cram_rosbased           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rosbased          : dprioin_rosbased;
assign cram_rosnumber          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rosnumber         : dprioin_rosnumber;
assign cram_rphfifo_master_sel_rx = init_rphfifo_master_sel_rx;  // disable reconfiguration for quad-level crams
assign cram_rphfifopldenrx     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rphfifopldenrx    : dprioin_rphfifopldenrx;
assign cram_rphfifourstrx      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rphfifourstrx     : dprioin_rphfifourstrx;
assign cram_rpma_doublewidth_rx= (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rpma_doublewidth_rx    : dprioin_rpma_doublewidth_rx;  // enabled
assign cram_rpmadwidth_rx      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rpmadwidth_rx          : dprioin_rpmadwidth_rx;        // enabled
assign cram_rppm_cnt_reset     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rppm_cnt_reset    : dprioin_rppm_cnt_reset;
assign cram_rppmsel            = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rppmsel           : dprioin_rppmsel;
assign cram_rprbs_clr_rslt_rx  = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rprbs_clr_rslt_rx : dprioin_rprbs_clr_rslt_rx;
assign cram_rprbs_sel          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rprbs_sel         : dprioin_rprbs_sel;
assign cram_rprbsen_rx         = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rprbsen_rx        : dprioin_rprbsen_rx;
assign cram_rrcvd_clk_sel      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrcvd_clk_sel     : dprioin_rrcvd_clk_sel;
assign cram_rrlv_en            = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrlv_en           : dprioin_rrlv_en;
assign cram_rrundisp           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrundisp          : dprioin_rrundisp;
assign cram_rrx_rd_clk_sel     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrx_rd_clk_sel    : dprioin_rrx_rd_clk_sel;
assign cram_rrxfifo_dis        = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrxfifo_dis       : dprioin_rrxfifo_dis;
assign cram_rrxfifo_lowlatency_en = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrxfifo_lowlatency_en : dprioin_rrxfifo_lowlatency_en;
assign cram_rskpsetbased       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rskpsetbased      : dprioin_rskpsetbased;
assign cram_rsync_sm_dis       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rsync_sm_dis      : dprioin_rsync_sm_dis;
assign cram_rtest_bus_sel      = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtest_bus_sel     : dprioin_rtest_bus_sel;
assign cram_rtruebac2bac       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtruebac2bac      : dprioin_rtruebac2bac;
assign cram_rwa_6g_en          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rwa_6g_en         : dprioin_rwa_6g_en;
assign cram_scan_mode          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_scan_mode         : dprioin_scan_mode;
assign cram_sel_gp_md          = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_sel_gp_md         : dprioin_sel_gp_md;
// ================= pipe ====================                                                                    
assign cram_rphystatus_rst_toggle = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rphystatus_rst_toggle  : dprioin_rphystatus_rst_toggle; // new in ww29
assign cram_rrdwidth_rx           = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrdwidth_rx            : dprioin_rrdwidth_rx;
assign cram_rrx_detect_bypass     = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrx_detect_bypass      : dprioin_rrx_detect_bypass;
assign cram_rrx_pipe_enable       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrx_pipe_enable        : dprioin_rrx_pipe_enable;
assign cram_rtx_elec_idle_delay   = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_elec_idle_delay    :  dprioin_rtx_elec_idle_delay;
assign cram_rtx_pipe_enable       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rtx_pipe_enable        : dprioin_rtx_pipe_enable;


// PMA
assign cram_rtx_term      = (dpriodisable !== 1'b0) ? init_rtx_term      : dprioin_rtx_term;      // 2-bits
assign cram_r_tx_det_rx   = (dpriodisable !== 1'b0) ? init_r_tx_det_rx   : dprioin_r_tx_det_rx;   // 2-bit
assign cram_rrx_term      = (dpriodisable !== 1'b0) ? init_rrx_term      : dprioin_rrx_term;      // 2
assign cram_rforce_sigdet = (dpriodisable !== 1'b0) ? init_rforce_sigdet : dprioin_rforce_sigdet; // 1 
assign cram_rrx_dc_couple = (dpriodisable !== 1'b0) ? init_rrx_dc_couple : dprioin_rrx_dc_couple; // 1 - qpmaused
assign cram_rrx_eq_dc     = (dpriodisable !== 1'b0) ? init_rrx_eq_dc     : dprioin_rrx_eq_dc;     // 2
assign cram_rrx_vtt       = (dpriodisable !== 1'b0) ? init_rrx_vtt       : dprioin_rrx_vtt;       // 3
assign cram_rrx_sloslv    = (dpriodisable !== 1'b0) ? init_rrx_sloslv    : dprioin_rrx_sloslv;    // 3

// pma_ctrl3: 4.8068-4.806b (rx)
assign cram_reqa_ct     = (dpriodisable !== 1'b0) ? init_reqa_ct : dprioin_reqa_ct;   // 3-bits  - qpmaused
assign cram_reqb_ct     = (dpriodisable !== 1'b0) ? init_reqb_ct : dprioin_reqb_ct;   // 3-bit - qpmaused
assign cram_reqc_ct     = (dpriodisable !== 1'b0) ? init_reqc_ct : dprioin_reqc_ct;   // 3 - qpmaused
assign cram_reqd_ct     = (dpriodisable !== 1'b0) ? init_reqd_ct : dprioin_reqd_ct;   // 3 - qpmaused 
assign cram_req_ctv     = (dpriodisable !== 1'b0) ? init_req_ctv : dprioin_req_ctv;   // 3 - qpmaused

// pma_ctrl6: 4.8074-4.8077 (rx)
assign cram_rrx_cru_m_sel     = (dpriodisable !== 1'b0) ? init_rrx_cru_m_sel : dprioin_rrx_cru_m_sel;
assign cram_rrx_cru_div2     = (dpriodisable !== 1'b0) ? init_rrx_cru_div2 : dprioin_rrx_cru_div2;
assign cram_rltr     = (dpriodisable !== 1'b0) ? init_rltr : dprioin_rltr;
assign cram_rltd     = (dpriodisable !== 1'b0) ? init_rltd : dprioin_rltd;
                
// pma_ctrl7: 4.8078-4.807B (rx)
assign cram_rrx_cru_m     = (dpriodisable !== 1'b0) ? init_rrx_cru_m : dprioin_rrx_cru_m;
assign cram_rrx_cru_l     = (dpriodisable !== 1'b0) ? init_rrx_cru_l : dprioin_rrx_cru_l;

// pma_ctrl8:
assign cram_rs_lpbk       = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rs_lpbk      : dprioin_rs_lpbk;
assign cram_rrx_revlb_sw  = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_rrx_revlb_sw : dprioin_rrx_revlb_sw;

assign cram_cru_clock_select = (dpriodisable !== 1'b0 || dprio_config_mode == 0) ? init_cru_clock_select : dprioin_cru_clock_select;

/////////////////////////////////////////////////////////////////////////////////
// Connect top level output  --------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

assign a1a2sizeout        = a1a2sizeout_reg;
assign a1detect           = a1detect_reg;
assign a2detect           = a2detect_reg;
assign ctrldetect         = ctrldetect_reg;
assign dataout            = dataout_reg;
assign dataoutfull        = pi_out_rxd_ch;
assign disperr            = disperr_reg;
assign errdetect          = errdetect_reg;
assign k1detect           = k1detect_reg;
assign k2detect           = k2detect_reg; 
assign patterndetect      = patterndetect_reg;
assign rmfifodatadeleted  = rmfifodatadeleted_reg;        
assign rmfifodatainserted = rmfifodatainserted_reg;
assign runningdisp        = runningdisp_reg;
assign syncstatus         = syncstatus_reg;

// a1a2sizeout; - used in SONET mode
    always @(pi_out_rxd_ch[8] or pi_out_rxd_ch[24] or pi_out_rxd_ch[40] or pi_out_rxd_ch[56])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                a1a2sizeout_reg[i] = pi_out_rxd_ch[8 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                a1a2sizeout_reg[i] = pi_out_rxd_ch[8 + 16*i];
        end
    end
               
// a1detect; [1:0] - Async from Word align, not going BYTE SERDES
    always @(rd_out_a1a2_k1k2_flag[0] or rd_out_a1a2_k1k2_flag[2])
        for (i=0; i < A1K1_OUT_WIDTH; i=i+1)
            a1detect_reg[i] = rd_out_a1a2_k1k2_flag[2*i];

// a2detect; [0] = detecting A2 on datain[7:0]; [1] = on datain[15:8]
    always @(rd_out_a1a2_k1k2_flag[1] or rd_out_a1a2_k1k2_flag[3])
        for (i=0; i < A1K1_OUT_WIDTH; i=i+1)
            a2detect_reg[i] = rd_out_a1a2_k1k2_flag[1+2*i];

// adetectdeskew;
    assign adetectdeskew = rd_out_align_det_sync;

// analogtestbus; 8 - defined in ADCE below             
//    assign analogtestbus = 'b0;

// alignstatussyncout
    assign alignstatussyncout = rd_out_align_status_sync;       
	  
// bistdone;
    assign bistdone = rd_out_bistdone;

// bisterr;
    assign bisterr = rd_out_bisterr;

// byteorderalignstatus;
    assign byteorderalignstatus = rd_out_byteord_flag;

// clkout;
    assign clkout = rd_out_rx_clk;

// cmudivclkout
    assign cmudivclkout = cruclk_in[cru_clock_select]; 

// ctrldetect; - 8b10b used 
    always @(pi_out_rxd_ch[8] or pi_out_rxd_ch[24] or pi_out_rxd_ch[40] or pi_out_rxd_ch[56])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                ctrldetect_reg[i] = pi_out_rxd_ch[8 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                ctrldetect_reg[i] = pi_out_rxd_ch[8 + 16*i];
        end
    end

// dataout; - 40 => [7:0]/[9:0], [23:16]/[25:16], [39:32]/[41:32], [55:48]/[57:48]
    always @(pi_out_rxd_ch)
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < NUM_OF_BASIC) && (i < 2); i=i+1)
                for (j=0; j<BASIC_WIDTH; j=j+1)
                    dataout_reg[i*BASIC_WIDTH + j] = pi_out_rxd_ch[i*32 + j];
        end
		else
        begin
            for (i=0; i < NUM_OF_BASIC; i=i+1)
                for (j=0; j<BASIC_WIDTH; j=j+1)
                    dataout_reg[i*BASIC_WIDTH + j] = pi_out_rxd_ch[i*16 + j];
        end
    end

// disablefifordout;
    assign disablefifordout = rd_out_disable_fifo_rd;

// disablefifowrout;
    assign disablefifowrout = rd_out_disable_fifo_wr;

// disperr;
    always @(pi_out_rxd_ch[11] or pi_out_rxd_ch[27] or pi_out_rxd_ch[43] or pi_out_rxd_ch[59])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                disperr_reg[i] = pi_out_rxd_ch[11 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                disperr_reg[i] = pi_out_rxd_ch[11 + 16*i];
        end
    end


// dprioout
    assign dprioout = wire_dprioout;

// errdetect;
    always @(pi_out_rxd_ch[9] or pi_out_rxd_ch[25] or pi_out_rxd_ch[41] or pi_out_rxd_ch[57])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                errdetect_reg[i] = pi_out_rxd_ch[9 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                errdetect_reg[i] = pi_out_rxd_ch[9 + 16*i];
        end
    end

// fifordout;
    assign fifordout = rd_out_fifo_rd_out_comp;

// freqlock;
    //assign freqlock = rd_out_freq_lock;
    assign freqlock = cdr_out_freqlocked;    // simplified models
               
// k1detect; [1:0] - Async from Word align, not going BYTE SERDES
    always @(rd_out_a1a2_k1k2_flag[0] or rd_out_a1a2_k1k2_flag[2])
        for (i=0; i < A1K1_OUT_WIDTH; i=i+1)
            k1detect_reg[i] = rd_out_a1a2_k1k2_flag[2*i];

// k2detect; [0] = detecting K2 on datain[9:0]; [1] = datain[19:20]
    always @(rd_out_a1a2_k1k2_flag[1] or rd_out_a1a2_k1k2_flag[3])
        for (i=0; i < 2; i=i+1)
            k2detect_reg[i] = rd_out_a1a2_k1k2_flag[1+2*i];

// patterndetect;
    always @(pi_out_rxd_ch[12] or pi_out_rxd_ch[28] or pi_out_rxd_ch[44] or pi_out_rxd_ch[60])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                patterndetect_reg[i] = pi_out_rxd_ch[12 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                patterndetect_reg[i] = pi_out_rxd_ch[12 + 16*i];
        end
    end

// phaselockloss;
    assign phaselockloss = pma_out_phaselockloss;

// phfifobyteselout; - ch0 to others
    assign phfifobyteselout = rd_out_rxfifo_shared_sig_out[0];

// phfifooverflow;
    assign phfifooverflow = rd_out_full_rx;  

// phfifordenableout;
    assign phfifordenableout = rd_out_rxfifo_shared_sig_out[1];

// phfifounderflow; 
    assign phfifounderflow = rd_out_empty_rx;
      
// phfifowrclkout;
    assign phfifowrclkout = rd_out_rxfifo_shared_sig_out[3];

// phfifowrenableout;
    assign phfifowrenableout = rd_out_rxfifo_shared_sig_out[2];


// pipebufferstat; 4 - expect wys - may remove according ICD
    assign pipebufferstat[1:0] = pi_out_rxd_ch[14:13];
    assign pipebufferstat[3:2] = pi_out_rxd_ch[46:45];

// pipedatavalid;
    assign pipedatavalid = pi_out_rxvalid;

// pipeelecidle;
    assign pipeelecidle = pi_out_rxelecidle;

// pipephydonestatus;
    assign pipephydonestatus = pi_out_phystatus;

// pipestatus; 3
    assign pipestatus = pi_out_rxstatus;

// pipestatetransdoneout
    assign pipestatetransdoneout = pi_out_sim_state_transition_done;

// rdalign;
    assign rdalign = rd_out_rd_align;

// recovclkout;
    assign recovclkout = rd_out_rcvd_clk_pma_b;

// revparallelfdbkdata;        
    assign revparallelfdbkdata = rd_out_rev_loop_data;  
      
// revserialfdbkout;   
    assign revserialfdbkout = pma_out_revserialfdbkout;   
 
// rlv; 
    assign rlv = rd_out_rlv_lt; 

// rmfifoalmostempty;
    assign rmfifoalmostempty = rd_out_almost_mt_rmf;

// rmfifoalmostfull;
    assign rmfifoalmostfull = rd_out_almost_fl_rmf;

// rmfifodatadeleted - 4;  
    always @(pi_out_rxd_ch[13] or pi_out_rxd_ch[29] or pi_out_rxd_ch[45] or pi_out_rxd_ch[61])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                rmfifodatadeleted_reg[i] = pi_out_rxd_ch[13 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                rmfifodatadeleted_reg[i] = pi_out_rxd_ch[13 + 16*i];
        end
    end
      
// rmfifodatainserted - 4;  
    always @(pi_out_rxd_ch[14] or pi_out_rxd_ch[30] or pi_out_rxd_ch[46] or pi_out_rxd_ch[62])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                rmfifodatainserted_reg[i] = pi_out_rxd_ch[14 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                rmfifodatainserted_reg[i] = pi_out_rxd_ch[14 + 16*i];
        end
    end

// rmfifoempty;
    assign rmfifoempty = rd_out_empty_rmf;

// rmfifofull;
    assign rmfifofull = rd_out_full_rmf;

// runningdisp - 4;  
    always @(pi_out_rxd_ch[15] or pi_out_rxd_ch[31] or pi_out_rxd_ch[47] or pi_out_rxd_ch[63])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                runningdisp_reg[i] = pi_out_rxd_ch[15 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                runningdisp_reg[i] = pi_out_rxd_ch[15 + 16*i];
        end
    end

// signaldetect;
    assign signaldetect = rd_out_signal_detect_out;

// syncstatus;
    always @(pi_out_rxd_ch[10] or pi_out_rxd_ch[26] or pi_out_rxd_ch[42] or pi_out_rxd_ch[58])
    begin
        if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1)
        begin
            for (i=0; (i < CTRL_OUT_WIDTH) && (i < 2); i=i+1)
                syncstatus_reg[i] = pi_out_rxd_ch[10 + 32*i];
        end
		else
        begin
            for (i=0; i < CTRL_OUT_WIDTH; i=i+1)
                syncstatus_reg[i] = pi_out_rxd_ch[10 + 16*i];
        end
    end

// syncstatusdeskew;
    assign syncstatusdeskew = rd_out_sync_status;

// xgmctrldet;
    assign xgmctrldet = rd_out_dec_ctl;

// xgmdataout; - 8
    assign xgmdataout = rd_out_dec_data;

// xgmdatavalid;
    assign xgmdatavalid = rd_out_dec_data_valid;

// xgmrunningdisp;
    assign xgmrunningdisp = rd_out_running_disp[0];

/////////////////////////////////////////////////////////////////////////////////
// signals from RX PCS to PMA  ------------------------------------//
/////////////////////////////////////////////////////////////////////////////////
assign pma_in_freqlock = rd_out_freq_lock;

/////////////////////////////////////////////////////////////////////////////////
// signals from RX PMA to Digital portion  ------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

assign pma_out_pdata        = des_out_paralleldataout;
assign pma_out_rcvd_clk     = des_out_recvclkout;
assign pma_out_clklow       = cdr_out_clklow;
assign pma_out_fref         = cdr_out_fref;
assign pma_out_sigdet       = cdr_out_signaldetect;

/////////////////////////////////////////////////////////////////////////////////
// signals from RX PMA to Top level  ------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

assign pma_out_phaselockloss    = cdr_out_phaselockloss;
assign pma_out_revserialfdbkout = cdr_out_revserialfdbk;

/////////////////////////////////////////////////////////////////////////////////
// CDR Submodule  -------------------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

assign cdr_in_dpriodisable  = (dpriodisable_in === 1'b0) ? 1'b0 : 1'b1; // from TOP
assign cdr_in_dprioin       = {7'h00,cram_cru_clock_select, cram_rrx_cru_l, cram_rrx_cru_m, cram_rrx_cru_div2, cram_rrx_cru_m_sel};

assign cdr_in_cruclk        = cruclk_in;           // from TOP
assign cdr_in_freqlock      = pma_in_freqlock;     // from PCS
assign cdr_in_ltd           = locktodata_in;       // from TOP
assign cdr_in_ltr           = locktorefclk;        // from TOP
assign cdr_in_pdb           = (crupowerdn_in === 1'b1) ? 1'b1 : 1'b0;   // from TOP
                                                   // shut down RX_PMA in parallel loopback to match ASM
assign cdr_in_reset         = (analogreset_in === 1'b1 || crureset_in === 1'b1 || use_parallel_loopback == "true") ? 1'b1: 1'b0; // from TOP     
assign cdr_in_rxin          = (seriallpbken_in === 1'b1) ? serialfdbk_in : datain_in; // from TOP

arriagx_hssi_rx_cdr m_cdr(
    .cruclk         (cdr_in_cruclk),
    .dpriodisable   (cdr_in_dpriodisable),
    .dprioin        (cdr_in_dprioin),
    .freqlock       (cdr_in_freqlock),
    .ltd            (cdr_in_ltd),
    .ltr            (cdr_in_ltr),
    .pdb            (cdr_in_pdb),
    .reset          (cdr_in_reset),
    .rxin           (cdr_in_rxin),
    .clklow         (cdr_out_clklow),
    .dprioout       (cdr_out_dprioout),
    .fref           (cdr_out_fref),
    .freqlocked     (cdr_out_freqlocked),
    .phaselockloss  (cdr_out_phaselockloss),
    .revserialfdbk  (cdr_out_revserialfdbk),
    .serialclkout   (cdr_out_serialclkout),
    .signaldetect   (cdr_out_signaldetect)
);
defparam m_cdr.cru_clock_select            = cru_clock_select;
defparam m_cdr.cru_divide_by               = cru_divide_by;
defparam m_cdr.cru_multiply_by             = cru_multiply_by;
defparam m_cdr.cru_pre_divide_by           = cru_pre_divide_by;
defparam m_cdr.cruclk0_period              = cruclk0_period;       
defparam m_cdr.cruclk1_period              = cruclk1_period;       
defparam m_cdr.cruclk2_period              = cruclk2_period;       
defparam m_cdr.cruclk3_period              = cruclk3_period;       
defparam m_cdr.cruclk4_period              = cruclk4_period;       
defparam m_cdr.cruclk5_period              = cruclk5_period;       
defparam m_cdr.cruclk6_period              = cruclk6_period;       
defparam m_cdr.cruclk7_period              = cruclk7_period;       

defparam m_cdr.force_signal_detect         = force_signal_detect; // RFORCE_SIGDET
defparam m_cdr.ignore_lock_detect          = ignore_lock_detect;
defparam m_cdr.signal_detect_threshhold    = signal_detect_threshold;
defparam m_cdr.send_direct_reverse_serial_loopback = send_direct_reverse_serial_loopback;
defparam m_cdr.force_freq_det_high         = force_freq_det_high; // for simplied freqlock
defparam m_cdr.force_freq_det_low          = force_freq_det_low;
defparam m_cdr.dprio_config_mode           = dprio_config_mode;

// POF only
defparam m_cdr.sim_rxpll_clkout_phase_shift = sim_rxpll_clkout_phase_shift;
defparam m_cdr.sim_rxpll_clkout_latency = sim_rxpll_clkout_latency;

/////////////////////////////////////////////////////////////////////////////////
// DES Submodule  -------------------------------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

assign des_in_datain       = (ibpowerdn_in === 1'b1) ? 1'b0: datain_in; // rx_pdb  
assign des_in_rdoublewidth = cram_rpma_doublewidth_rx; 
assign des_in_rdwidth      = cram_rpmadwidth_rx;
assign des_in_reset        = (analogreset_in === 1'b1 || crupowerdn_in === 1'b1) ? 1'b1 : 1'b0;
assign des_in_serialclk    = (allow_vco_bypass == "false") ? cdr_out_serialclkout :
                             (cru_clock_select <= 7) ? cruclk_in[cru_clock_select] : 1'bx;
assign des_in_serialfdbken = (seriallpbken_in === 1'b1) ? 1'b1 : 1'b0;
assign des_in_serialfdbkin = serialfdbk_in;

arriagx_hssi_rx_des m_des (
    .datain               (des_in_datain),
    .rdoublewidth         (des_in_rdoublewidth),
    .rdwidth              (des_in_rdwidth),
    .reset                (des_in_reset),
    .serialclk            (des_in_serialclk),
    .serialfdbken         (des_in_serialfdbken),        
    .serialfdbkin         (des_in_serialfdbkin),
             
    .paralleldataout      (des_out_paralleldataout),    
    .recvclkout           (des_out_recvclkout)
);

/////////////////////////////////////////////////////////////////////////////////
// ADCE                                                                        //
/////////////////////////////////////////////////////////////////////////////////

assign reconfig_clk = (dprioin_in[`reconfig_clk_RX_IDX] == 1'b1) ? 1'b1 : 1'b0;
assign adce_ena       = 1'b1;      // testsel[1] or when testsel[3:0] == 4'b0010

initial begin
    adce_initial_cycle_cnt = 0;
    reg_adce_high_out = 1'b1;
    reg_adce_low_out  = 1'b0;
end

always @ (negedge reconfig_clk or negedge adce_ena)
begin
    if (adce_ena == 1'b0)  // reset
    begin
        reg_adce_high_out <= 1'b0;
        reg_adce_low_out  <= 1'b1;
        adce_initial_cycle_cnt <= 0;
    end
    else if (sim_offset_cycle_count > 0)
    begin
        if (adce_initial_cycle_cnt < sim_offset_cycle_count)
            adce_initial_cycle_cnt <= adce_initial_cycle_cnt + 1;
        else
        begin
            reg_adce_high_out <= ~reg_adce_high_out;
            reg_adce_low_out  <= ~reg_adce_low_out;        
        end
    end
end

assign analogtestbus = {4'bxxxx, reg_adce_high_out, reg_adce_low_out, 2'bxx};

/////////////////////////////////////////////////////////////////////////////////
// rx sub-block instantiation: pcs_reset --------------------------------------//
/////////////////////////////////////////////////////////////////////////////////

assign pr_in_hard_reset  = (quadreset_in === 1'b1) ? 1'b1 : 1'b0;    // from top
assign pr_in_clk_2_b     = rd_out_clk_2_b;              //  
assign pr_in_refclk_b_in = 1'b0;                        // tx only
assign pr_in_scan_mode   = 1'b0;                        
assign pr_in_rxpcs_rst   = (digitalreset_in === 1'b1) ? 1'b1 : 1'b0; // from top 
assign pr_in_txpcs_rst   = 1'b0;                        // for tx side

arriagx_hssi_pcs_reset  tx_pcs_reset_1 (
    .hard_reset   (pr_in_hard_reset), 
    .clk_2_b      (pr_in_clk_2_b), 
    .refclk_b_in  (pr_in_refclk_b_in),
    .scan_mode    (pr_in_scan_mode),
    .rxpcs_rst    (pr_in_rxpcs_rst), 
    .txpcs_rst    (pr_in_txpcs_rst),
    .rxrst_int    (pr_out_rxrst_int), 
    .txrst_int    (pr_out_txrst_int)
);


/////////////////////////////////////////////////////////////////////////////////
// tx sub-block instantiation: pipe_interface ---------------------------------//
/////////////////////////////////////////////////////////////////////////////////

//assign  pi_in_pipe_rx_clk = rd_out_rx_pipe_clk;
assign  pi_in_pipe_rx_clk = (cram_rrx_pipe_enable === 1'b0) ? 1'b0 : rd_out_rx_pipe_clk;
assign  pi_in_pipe_tx_clk = 1'b0;
assign  pi_in_polinv_rx   = (invpolarity_in === 1'b1) ? 1'b1 : 1'b0; // from top
assign  pi_in_power_state_transition_done = 1'b0;      // grounded in rtl - quad_top
assign  pi_in_power_state_transition_done_ena = 1'b0;  // grounded in rtl - digi_chnl
assign  pi_in_powerdown   = pipepowerdown_in;          // from top 
assign  pi_in_refclk_b    = 1'b0;                      // tx pipe
assign  pi_in_refclk_b_reset = 1'b0;                   // tx pipe
assign  pi_in_revloopback = 1'b0;                      // tx pipe
assign  pi_in_rx_detect_valid = rxdetectvalid_in;      // from top - TX_PMA  
assign  pi_in_rx_found        = rxfound_in[0];         // from top - TX_PMA
assign  pi_in_rx_pipe_reset   = rd_out_rx_pipe_soft_reset;                   
assign  pi_in_rxbeacon        = 1'b0;                  // grounded in rtl - quad_top
assign  pi_in_rxd             = rd_out_rxd;            // 64 bits
assign  pi_in_rxelectricalidle  = ~pma_out_sigdet;     // from rx pma
assign  pi_in_rxpolarity        = (pipe8b10binvpolarity_in === 1'b1) ? 1'b1 : 1'b0;   // from top
assign  pi_in_tx_elec_idle_comp = 1'b0;                // tx pipe
assign  pi_in_tx_pipe_reset     = 1'b0;                // tx pipe
assign  pi_in_txcompliance      = 1'b0;                // tx pipe
assign  pi_in_txd_ch            = 'b0;                 // tx pipe - 44 bits
assign  pi_in_txdetectrxloopback = 1'b0;               // tx pipe
assign  pi_in_txelecidle        = 1'b0;                // tx pipe

assign  pi_in_powerstatein      = pipepowerstate_in;   // from top - new by shawn
assign  pi_in_txdetectrxin      = rxfound_in[1];       // from top of tx_pipe - new by shawn

arriagx_hssi_q_pipe_interface_top rx_pipe_interface_top_1 (
	.phystatus                       (pi_out_phystatus),
	.pipe_rx_clk                     (pi_in_pipe_rx_clk),
	.pipe_tx_clk                     (pi_in_pipe_tx_clk),
	.polinv_rx                       (pi_in_polinv_rx),
	.polinv_rx_int                   (pi_out_polinv_rx_int),
	.power_state_transition_done     (pi_in_power_state_transition_done),
	.power_state_transition_done_ena (pi_in_power_state_transition_done_ena),
	.powerdown                       (pi_in_powerdown),
	.powerstate                      (pi_out_powerstate),
	.rclkcmpinsertpad                (cram_rclkcmpinsertpad),
	.refclk_b                        (pi_in_refclk_b),
	.refclk_b_reset                  (pi_in_refclk_b_reset),       // new in ww29
	.rev_loopbk                      (pi_out_rev_loopbk),
	.revloopback                     (pi_in_revloopback),
	.rphystatus_rst_toggle           (cram_rphystatus_rst_toggle), // new in ww29
	.rrdwidth_rx                     (cram_rdwidth_rx),
	.rrx_detect_bypass               (cram_rrx_detect_bypass),
	.rrx_pipe_enable                 (cram_rrx_pipe_enable),
	.rtx_elec_idle_delay             (cram_rtx_elec_idle_delay),
	.rtx_pipe_enable                 (cram_rtx_pipe_enable),
	.rx_detect_valid                 (pi_in_rx_detect_valid),
	.rx_found                        (pi_in_rx_found),
	.rx_pipe_reset                   (pi_in_rx_pipe_reset),
	.rxbeacon                        (pi_in_rxbeacon),
	.rxd                             (pi_in_rxd),
	.rxd_ch                          (pi_out_rxd_ch),
	.rxelecidle                      (pi_out_rxelecidle),
	.rxelectricalidle                (pi_in_rxelectricalidle),
	.rxpolarity                      (pi_in_rxpolarity),
	.rxstatus                        (pi_out_rxstatus),
	.rxvalid                         (pi_out_rxvalid),
	.tx_elec_idle                    (pi_out_tx_elec_idle),
	.tx_elec_idle_comp               (pi_in_tx_elec_idle_comp),
	.tx_pipe_reset                   (pi_in_tx_pipe_reset),
	.txbeacon                        (pi_out_txbeacon),
	.txcompliance                    (pi_in_txcompliance),
	.txd                             (pi_out_txd),
	.txd_ch                          (pi_in_txd_ch),
	.txdetectrx                      (pi_out_txdetectrx),
	.txdetectrxloopback              (pi_in_txdetectrxloopback),
	.txelecidle                      (pi_in_txelecidle),
    .txdetectrxin                    (pi_in_txdetectrxin),        // shawn
    .powerstatein                    (pi_in_powerstatein),        // shawn
    .use_powerstatein                (1'b1)                       // shawn

);


/////////////////////////////////////////////////////////////////////////////////
// rx sub-block instantiation: pipe_interface ---------------------------------//
/////////////////////////////////////////////////////////////////////////////////
assign rd_in_a1a2_size           = (a1a2size_in === 1'b1) ? 1'b1 : 1'b0; // from top        
assign rd_in_align_status        = alignstatus_in;     // from top   
assign rd_in_align_status_sync_0 = alignstatussync_in; // from top     
assign rd_in_align_status_sync_2 = alignstatussync_in; // from top - ideally from alignstatusout of channel2
assign rd_in_bitloc_rev_en       = (revbitorderwa_in === 1'b1) ? 1'b1 : 1'b0;  // from top
assign rd_in_bitslip             = (bitslip_in === 1'b1) ? 1'b1 : 1'b0;        // from top          
assign rd_in_byte_rev_en         = (revbyteorderwa_in === 1'b1) ? 1'b1 : 1'b0; // from top
assign rd_in_bytordpld           = (enabyteord_in === 1'b1) ? 1'b1 : 1'b0;     // from top
assign rd_in_clklow              = pma_out_clklow;    // VCO divided clk from CDR to freqdet
assign rd_in_cmpfifourst         = (rmfiforeset_in === 1'b1) ? 1'b1 : 1'b0;    // from top
assign rd_in_disable_fifo_rd_0   = disablefifordin_in;// from top - channel 0 of RX to rmfifo
assign rd_in_disable_fifo_rd_2   = 1'b0; // never used due to dskwrclksel[0]=0
assign rd_in_disable_fifo_wr_0   = disablefifowrin_in;// from top;
assign rd_in_disable_fifo_wr_2   = 1'b0;
assign rd_in_en_dskw_gp          = enabledeskew_in;   // from top - dskw_sm to dskw_fifo    
assign rd_in_en_dskw_qd          = enabledeskew_in;    
assign rd_in_encdt               = (enapatternalign_in === 1'b1) ? 1'b1 : 1'b0; // from top            
assign rd_in_encoder_testbus     = 'b0;  // 10 bit
assign rd_in_fifo_rd_in_comp_0   = fifordin_in;        // from top  
assign rd_in_fifo_rd_in_comp_2   = fifordin_in;        // from top  - ideally from fifordout of channel2  
assign rd_in_fifo_rst_rd_gp      = fiforesetrd_in;     // from top - dskw_sm to dskw_fifo
assign rd_in_fifo_rst_rd_qd      = fiforesetrd_in;
assign rd_in_fref                = pma_out_fref;      // ref clock from CDR to freqdet
assign rd_in_hard_reset          = (quadreset_in === 1'b1) ? 1'b1 : 1'b0;      // from top
assign rd_in_phfifourst_rx       = (phfiforeset_in === 1'b1) ? 1'b1 : 1'b0;    // from top
assign rd_in_pld_rx_clk          = coreclk;        // coreclk_in from top
assign rd_in_pma_testbus         = 'b0;  // 8 bit
assign rd_in_polinv_rx           = pi_out_polinv_rx_int;    
assign rd_in_pudi                = pma_out_pdata;     // 20 bit from RX PMA             
assign rd_in_rcvd_clk_pma        = pma_out_rcvd_clk;  // from RX PMA
assign rd_in_rcvd_clk0_pma       = masterclk_in;      // from top
assign rd_in_rdenable_rmf        = (rmfifordena_in === 1'b0) ? 1'b0 : 1'b1;    // from top         
assign rd_in_rdenable_rx         = (phfifordenable_in === 1'b0) ? 1'b0 : 1'b1; // from top
assign rd_in_refclk_pma          = (channel_bonding == "x8" || channel_bonding == "x8_unbundled") ? refclk_in_delayed : refclk_in;  // from top
assign rd_in_rx_control_rs       = xgmctrlin_in;        // from top    
assign rd_in_rx_cru_pdb          = crupowerdn_in;     // from top - feeding nowhere
assign rd_in_rx_data_rs          = xgmdatain_in;      // from top - 8 bit       
assign rd_in_rxfifo_shared_sig_in_ch0[0] = phfifox4bytesel;  // rx_we_in_ch0
assign rd_in_rxfifo_shared_sig_in_ch0[1] = phfifox4rdenable; // rd_enable_ch0
assign rd_in_rxfifo_shared_sig_in_ch0[2] = phfifox4wrenable; // wr_enable_ch0
assign rd_in_rxfifo_shared_sig_in_ch0[3] = phfifox4wrclk;    // rxclk_ctl (rx_div2_sync_in_ch0)
assign rd_in_rxfifo_shared_sig_in_q0_ch0[0] = phfifox8bytesel;  // rx_we_in_q0_ch0
assign rd_in_rxfifo_shared_sig_in_q0_ch0[1] = phfifox8rdenable; // rd_enable_q0_ch0
assign rd_in_rxfifo_shared_sig_in_q0_ch0[2] = phfifox8wrenable; // wr_enable_q0_ch0
assign rd_in_rxfifo_shared_sig_in_q0_ch0[3] = phfifox8wrclk;    // rxclk_ctl (rx_div2_sync_in_q0_ch0)
assign rd_in_rxpma_rst           = (analogreset_in === 1'b1) ? 1'b0 : 1'b1; //~analogreset_in;    // from top - to freqdet (hardreset) assuming active low
assign rd_in_rxpcs_rst           = pr_out_rxrst_int;        
assign rd_in_sigdetni            = pma_out_sigdet;         
assign rd_in_tx_ctrl_testbus     = 'b0; // 10 bit
assign rd_in_txlp20b             = parallelfdbk_in;   // from top - 20 bit         
assign rd_in_txpma_local_clk     = localrefclk_in;    // from top
assign rd_in_wrdisable_rx        = (phfifowrdisable_in === 1'b1) ? 1'b1 : 1'b0; // from top
assign rd_in_wrenable_rmf        = (rmfifowrena_in === 1'b0) ? 1'b0 : 1'b1;     // from top         

arriagx_hssi_rx_digi digi_rx_1 (
	.rxpcs_rst                   (rd_in_rxpcs_rst),        
	.hard_reset                  (rd_in_hard_reset),
	.rxpma_rst                   (rd_in_rxpma_rst),
	.cmpfifourst                 (rd_in_cmpfifourst),
	.phfifourst_rx               (rd_in_phfifourst_rx),
	.rphfifourstrx               (cram_rphfifourstrx),
	.scan_mode                   (cram_scan_mode),                     
	.encdt                       (rd_in_encdt),            
	.a1a2_size                   (rd_in_a1a2_size),        
	.bitslip                     (rd_in_bitslip),          
	.rdenable_rmf                (rd_in_rdenable_rmf),         
	.wrenable_rmf                (rd_in_wrenable_rmf),         
	.pld_rx_clk                  (rd_in_pld_rx_clk),
	.polinv_rx                   (rd_in_polinv_rx),
	.bitloc_rev_en               (rd_in_bitloc_rev_en),
	.byte_rev_en                 (rd_in_byte_rev_en),
	.rcvd_clk_pma                (rd_in_rcvd_clk_pma),
	.pudi                        (rd_in_pudi),             
	.sigdetni                    (rd_in_sigdetni),         
	.fifo_rst_rd_qd              (rd_in_fifo_rst_rd_qd),
	.fifo_rst_rd_gp              (rd_in_fifo_rst_rd_gp),
	.en_dskw_qd                  (rd_in_en_dskw_qd),    
	.en_dskw_gp                  (rd_in_en_dskw_gp),    
	.is_lane0                    (cram_is_lane0),         
	.align_status                (rd_in_align_status),     
	.align_status_sync_0         (rd_in_align_status_sync_0),     
	.align_status_sync_2         (rd_in_align_status_sync_2),     
	.disable_fifo_rd_0           (rd_in_disable_fifo_rd_0),
	.disable_fifo_rd_2           (rd_in_disable_fifo_rd_2),
	.disable_fifo_wr_0           (rd_in_disable_fifo_wr_0),
	.disable_fifo_wr_2           (rd_in_disable_fifo_wr_2),
	.rx_data_rs                  (rd_in_rx_data_rs),       
	.rx_control_rs               (rd_in_rx_control_rs),    
	.rcvd_clk0_pma               (rd_in_rcvd_clk0_pma),
	.fifo_rd_in_comp_0           (rd_in_fifo_rd_in_comp_0),  
	.fifo_rd_in_comp_2           (rd_in_fifo_rd_in_comp_2),  
	.txlp20b                     (rd_in_txlp20b),          
	.refclk_pma                  (rd_in_refclk_pma),
	.tx_pma_clk                  (rd_in_txpma_local_clk),
	.fref                        (rd_in_fref),
	.clklow                      (rd_in_clklow),
	.bytordpld                   (rd_in_bytordpld),
	.wrdisable_rx                (rd_in_wrdisable_rx),
	.rdenable_rx                 (rd_in_rdenable_rx),
	.pma_testbus                 (rd_in_pma_testbus),
	.encoder_testbus             (rd_in_encoder_testbus),
	.tx_ctrl_testbus             (rd_in_tx_ctrl_testbus),
	.rxfifo_shared_sig_in_ch0    (rd_in_rxfifo_shared_sig_in_ch0),
	.rxfifo_shared_sig_in_q0_ch0 (rd_in_rxfifo_shared_sig_in_q0_ch0),
	.rx_cru_pdb                  (rd_in_rx_cru_pdb),
	.rxfifo_shared_sig_out       (rd_out_rxfifo_shared_sig_out),			
	.fifo_rd_out_comp            (rd_out_fifo_rd_out_comp), 
	.rxd                         (rd_out_rxd), 
	.rev_loop_data               (rd_out_rev_loop_data),
	.rx_clk                      (rd_out_rx_clk),           
	.bisterr                     (rd_out_bisterr),          
	.cg_comma                    (rd_out_cg_comma),         
	.clk_2_b                     (rd_out_clk_2_b),          
	.rcvd_clk_pma_b              (rd_out_rcvd_clk_pma_b),
	.sync_status                 (rd_out_sync_status),      
	.disable_fifo_rd             (rd_out_disable_fifo_rd),  
	.disable_fifo_wr             (rd_out_disable_fifo_wr),  
	.align_status_sync           (rd_out_align_status_sync),
	.dec_data_valid              (rd_out_dec_data_valid),
	.dec_data                    (rd_out_dec_data),         
	.dec_ctl                     (rd_out_dec_ctl),          
	.running_disp                (rd_out_running_disp),
	.selftest_done               (rd_out_selftest_done),
	.selftest_err                (rd_out_selftest_err),     
	.err_data                    (rd_out_err_data),         
	.err_ctl                     (rd_out_err_ctl),          
	.prbs_done                   (rd_out_prbs_done),        
	.prbs_err_lt                 (rd_out_prbs_err_lt),      
	.signal_detect_out           (rd_out_signal_detect_out),
	.align_det_sync              (rd_out_align_det_sync),   
	.rd_align                    (rd_out_rd_align),         
	.bistdone                    (rd_out_bistdone),
	.rlv                         (rd_out_rlv),
	.rlv_lt                      (rd_out_rlv_lt),           
	.almost_fl_rmf               (rd_out_almost_fl_rmf),        
	.full_rmf                    (rd_out_full_rmf),             
	.almost_mt_rmf               (rd_out_almost_mt_rmf),        
	.empty_rmf                   (rd_out_empty_rmf), 
	.freq_lock                   (rd_out_freq_lock),
	.full_rx                     (rd_out_full_rx),
	.empty_rx                    (rd_out_empty_rx),
	.a1a2_k1k2_flag              (rd_out_a1a2_k1k2_flag),
	.byteord_flag                (rd_out_byteord_flag),
	.rx_pipe_clk                 (rd_out_rx_pipe_clk),
	.chnl_test_bus_out           (rd_out_chnl_test_bus_out),
	.rx_pipe_soft_reset          (rd_out_rx_pipe_soft_reset),
	.rskpsetbased                (cram_rskpsetbased),
	.rtruebac2bac                (cram_rtruebac2bac),
	.ralfull                     (cram_ralfull),
	.ralempty                    (cram_ralempty),
	.rcmpfifourst                (cram_rcmpfifourst),
	.rcomp_size                  (cram_rcomp_size),       
	.rcomp_pat                   (cram_rcomp_pat),        
	.rrundisp                    (cram_rrundisp),         
	.rib_inv_cd                  (cram_rib_inv_cd),       
	.rrlv_en                     (cram_rrlv_en),          
	.rsync_sm_dis                (cram_rsync_sm_dis),     
	.rautobtalg_dis              (cram_rautobtalg_dis),   
	.rdis_rx_disp                (cram_rdis_rx_disp),     
	.rmatchen                    (cram_rmatchen),         
	.rgenericfifo                (cram_rgenericfifo),     
	.rendec_rx                   (cram_rendec_rx),        
	.rdwidth_rx                  (cram_rdwidth_rx),       
	.rlp20ben                    (cram_rlp20ben),         
	.rrxfifo_dis                 (cram_rrxfifo_dis),      
	.rpmadwidth_rx               (cram_rpmadwidth_rx),
	.rpma_doublewidth_rx         (cram_rpma_doublewidth_rx),
	.renumber                    (cram_renumber),
	.rknumber                    (cram_rknumber),
	.renpolinv_rx                (cram_renpolinv_rx),
	.rgnumber                    (cram_rgnumber),
	.rclkcmpsqmd                 (cram_rclkcmpsqmd),
	.rclkcmpsq1p                 (cram_rclkcmpsq1p),
	.rclkcmpsq1n                 (cram_rclkcmpsq1n),
	.rclkcmppos                  (cram_rclkcmppos),
	.rosnumber                   (cram_rosnumber),
	.rosbased                    (cram_rosbased),
	.rkchar                      (cram_rkchar),
	.rcascaded_8b10b_en_rx       (cram_rcascaded_8b10b_en_rx),
	.resync_badcg_en             (cram_resync_badcg_en),      
	.rencdt_rising               (cram_rencdt_rising),        
	.rcomp_pat_porn              (cram_rcomp_pat_porn),       
	.rprbsen_rx                  (cram_rprbsen_rx),           
	.rprbs_clr_rslt_rx           (cram_rprbs_clr_rslt_rx),    
	.rbisten_rx                  (cram_rbisten_rx),           
	.rbist_clr_rx                (cram_rbist_clr_rx),         
	.rwa_6g_en                   (cram_rwa_6g_en),            
	.rbitslip_size               (cram_rbitslip_size),        
	.rbytord_2sym_en             (cram_rbytord_2sym_en),        
	.rbysync_polinv_en           (cram_rbysync_polinv_en),    
	.rbitloc_rev_en              (cram_rbitloc_rev_en),       
	.rbyte_rev_en                (cram_rbyte_rev_en),         
	.rbyteorden                  (cram_rbyteorden),           
	.rbytordplden                (cram_rbytordplden),         
	.rphfifopldenrx              (cram_rphfifopldenrx),       
	.rautoinsdis                 (cram_rautoinsdis),
	.rppmsel                     (cram_rppmsel),
	.rforce0_freqdet             (cram_rforce0_freqdet),
	.rforce1_freqdet             (cram_rforce1_freqdet),
	.rbytordpat                  (cram_rbytordpat),           
	.rbytordpad                  (cram_rbytordpad),           
	.rforce_sig_det_pcs          (cram_rforce_sig_det_pcs),
	.rfreerun_rx                 (cram_rfreerun_rx),   
	.rrcvd_clk_sel               (cram_rrcvd_clk_sel), 
	.rclk_1_sel                  (cram_rclk_1_sel),    
	.rclk_2_sel                  (cram_rclk_2_sel),    
	.rrx_rd_clk_sel              (cram_rrx_rd_clk_sel),
	.rall_one_dect_only          (cram_rall_one_dect_only),
	.rtest_bus_sel               (cram_rtest_bus_sel),
	.r8b10b_dec_ibm_en           (cram_r8b10b_dec_ibm_en),
	.rrxfifo_lowlatency_en       (cram_rrxfifo_lowlatency_en),
	.rppm_cnt_reset              (cram_rppm_cnt_reset),
	.sel_gp_md                   (cram_sel_gp_md),
	.rclkcmpinsertpad            (cram_rclkcmpinsertpad),
	.rindv_rx                    (cram_rindv_rx),         
	.dskwclksel                  (cram_dskwclksel),
	.rdskposdisp                 (cram_rdskposdisp), 
	.rdskchrp                    (cram_rdskchrp),
	.rendec_data_sel_rx          (cram_rendec_data_sel_rx),
	.rphfifo_master_sel_rx       (cram_rphfifo_master_sel_rx),
	.rprbs_sel                   (cram_rprbs_sel),            
	.rbist_sel                   (cram_rbist_sel),            
	.rcxpat_chnl_en              (cram_rcxpat_chnl_en)
);


endmodule

