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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file xil_8b10b_enc.v when simulating
// the core, xil_8b10b_enc. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module xil_8b10b_enc(
	din,
	kin,
	clk,
	dout,
	force_code,
	force_disp,
	disp_in,
	disp_out,
	kerr);


input [7 : 0] din;
input kin;
input clk;
output [9 : 0] dout;
input force_code;
input force_disp;
input disp_in;
output disp_out;
output kerr;

// synthesis translate_off
// synthesis translate_on

      ENCODE_8B10B_V5_0 #(
		.c_enable_rlocs(0),
		.c_encode_type(0),
		.c_force_code_disp(1),
		.c_force_code_disp_b(1),
		.c_force_code_val("1010101010"),
		.c_force_code_val_b("1010101010"),
		.c_has_bports(0),
		.c_has_ce(0),
		.c_has_ce_b(0),
		.c_has_disp_in(1),
		.c_has_disp_in_b(0),
		.c_has_disp_out(1),
		.c_has_disp_out_b(0),
		.c_has_force_code(1),
		.c_has_force_code_b(0),
		.c_has_kerr(1),
		.c_has_kerr_b(0),
		.c_has_nd(0),
		.c_has_nd_b(0))
	inst (
		.DIN(din),
		.KIN(kin),
		.CLK(clk),
		.DOUT(dout),
		.FORCE_CODE(force_code),
		.FORCE_DISP(force_disp),
		.DISP_IN(disp_in),
		.DISP_OUT(disp_out),
		.KERR(kerr),
		.CE(),
		.CE_B(),
		.DIN_B(),
		.KIN_B(),
		.CLK_B(),
		.DOUT_B(),
		.FORCE_CODE_B(),
		.FORCE_DISP_B(),
		.DISP_IN_B(),
		.DISP_OUT_B(),
		.ND(),
		.ND_B(),
		.KERR_B());



endmodule

