agx20_disp_dp2_vga

KEI-CQ-AGX20DPpSATAΉgTvłB

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҂쐬t@ĆA{I"as-is"CZXłB
gpɍۂĂ̐͂܂B
Agp̍ۂɕsĂȂۏ؂Ȃ܂B

 agx20_disp_dp2_vga
        DisplayPort͑Ή̃fBXvCŁAVGA𑜓x(640x480 27MHz)̕\Ȃ܂B
        x2[gp̂ŁASATAΉDPp̗gp\łB
        ̃vWFNg̎sɂ́ADisplayPort 1.1Ή̃fBXvCKvłB
        DisplayPort 1.1ȊÕo[Wł͐삵Ȃ\܂̂łB

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SATAΉ܂DPp̃Wp[DPɐݒ肵܂B
DisplayPortΉ̃fBXvCƂȂ܂B

QuartusIIN܂B

ProgrammerN܂B

RtBO[VȂ܂B

 Tv

DisplayPort640x480(VGA𑜓x)̃J[o[\Ȃ܂B

CN̓g162MHzłB

Tv̂߁AW[ėp₷`ɂ͍\Ă܂B
܂AV~[VAUX-CH̒ʐMe͂邽߂dp_aux_rx]ɓĂ܂B
NAbvdp_main_linkup2.ṽV[PT[Ȃ܂B
link_state_raux_cmd_code[35:0]Ŏw肳ꂽeɂē܂B
dp_main_linkup2.v̑Ƀ\tgRACPUȂǂŐ䂷΁ADisplayPort1.1ȊÕo[WłƎv܂B

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agx20_disp_dp2_vga.qpf      QuartusII 9.1 vWFNgt@C
agx20_disp_dp2_vga.qsf      QuartusII 9.1 t@C

agx20_disp_dp2_vga_tb.v     eXgx`
dp_sink_aux_tx.v            AUX-CH VN(fBXvC)M
dp_sink_aux_rx.v            AUX-CH VN(fBXvC)M
agx20_disp_dp2_vga.vtakprj  Veritak vWFNgt@C

agx20_disp_dp2_vga.v        TOPW[
alt_ddio_bidir.v            PLL΍p
alt_alt2gxb_tx2.v           ArriaGX alt2gxb MKrbggV[o[W[
dispgen.v                   eXgp^[\W[
dp_main_linkup2.v           x2[Ή AUX-CH NAbvpV[PT[
dp_aux_tx.v                 AUX-CH M
dp_aux_rx.v                 AUX-CH M
dp_main_crtc2.v             x2[Ή CN \^C~O
dp_main_tbc2.v              x2[Ή CN NbNhC
alt_ram_dp108x256.v         TBCp
dp_main_scramble.v          CN f[^XNu


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agx20_disp_dp2_vga_tb.v

