Release 12.2 par M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

LENOVO-A29837C5::  Sat Nov 12 11:34:47 2011

par -w -intstyle ise -ol high -xe n -mt 2 exp6t_disp_dp_map.ncd
exp6t_disp_dp.ncd exp6t_disp_dp.pcf 


Constraints file: exp6t_disp_dp.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\Xilinx\12.2\ISE_DS\ISE\.
   "exp6t_disp_dp" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.

----------------------------------------------------------------------

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRELIMINARY 1.10 2010-06-28".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                 2,767 out of  54,576    5%
    Number used as Flip Flops:               2,767
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      2,967 out of  27,288   10%
    Number used as logic:                    2,902 out of  27,288   10%
      Number using O6 output only:           2,752
      Number using O5 output only:              99
      Number using O5 and O6:                   51
      Number used as ROM:                        0
    Number used as Memory:                      12 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:            12
        Number using O6 output only:             6
        Number using O5 output only:             0
        Number using O5 and O6:                  6
    Number used exclusively as route-thrus:     53
      Number with same-slice register load:     43
      Number with same-slice carry load:        10
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 1,154 out of   6,822   16%
  Number of LUT Flip Flop pairs used:        3,173
    Number with an unused Flip Flop:           491 out of   3,173   15%
    Number with an unused LUT:                 206 out of   3,173    6%
    Number of fully used LUT-FF pairs:       2,476 out of   3,173   78%
    Number of slice register sites lost
      to control set restrictions:               0 out of  54,576    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       154 out of     296   52%
    Number of LOCed IOBs:                      154 out of     154  100%
    IOB Flip Flops:                              4
    IOB Master Pads:                             5
    IOB Slave Pads:                              5
    Number of bonded IPADs:                      6 out of      16   37%
    Number of bonded OPADs:                      4 out of       8   50%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         3 out of     116    2%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 2 out of      32    6%
    Number used as BUFIO2s:                      2
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       8 out of      16   50%
    Number used as BUFGs:                        8
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     1 out of       8   12%
    Number used as DCMs:                         1
    Number used as DCM_CLKGENs:                  0
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   4 out of     376    1%
    Number used as OLOGIC2s:                     4
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of GTPA1_DUALs:                         1 out of       2   50%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       4   25%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

PAR will use up to 2 processors
WARNING:Par:288 - The signal TMDS_CEC_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TMDS_HPD_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TMDS_SDA_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TMDS_SCL_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_CLKOUT_IP_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<10>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<11>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<12>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<10>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<13>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<11>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<14>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<12>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<15>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<13>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<14>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<15>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_LDQS_N_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_LDQS_P_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pushsw_ip<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pushsw_ip<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pushsw_ip<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_UDQS_N_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_UDQS_P_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dipsw_ip<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dipsw_ip<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dipsw_ip<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dipsw_ip<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO1C<22>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO1C<23>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO1C<24>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO1C<25>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO1C<26>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO1C<27>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO1C<28>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO1C<29>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<10>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<11>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<12>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<20>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<13>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<21>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<14>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<22>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<15>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<23>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<16>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<24>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<17>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<25>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<26>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<18>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<27>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<19>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<28>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<29>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FLAGA_IP_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FLAGB_IP_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FLAGC_IP_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<4>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<5>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<4>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<6>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<5>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<7>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<6>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<8>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<7>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD_BP<9>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<8>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DDR2_D<9>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<4>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<5>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<6>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<7>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<8>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<9>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CFG_MISO_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DP_RSV1_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DP_RSV2_IBUF has no load.  PAR will not attempt to route this signal.
Starting Multi-threaded Router


Phase  1  : 13810 unrouted;      REAL time: 12 secs 

Phase  2  : 11978 unrouted;      REAL time: 17 secs 

Phase  3  : 4412 unrouted;      REAL time: 23 secs 

Phase  4  : 4412 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 26 secs 

Updating file: exp6t_disp_dp.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 31 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 31 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 31 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 31 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 31 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 33 secs 
Total REAL time to Router completion: 33 secs 
Total CPU time to Router completion (all processors): 38 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|          CLK27_BUFG | BUFGMUX_X2Y11| No   |  140 |  0.041     |  1.384      |
+---------------------+--------------+------+------+------------+-------------+
|         PLL162_BUFG | BUFGMUX_X3Y14| No   |    1 |  0.000     |  1.396      |
+---------------------+--------------+------+------+------------+-------------+
|    GTPCLKOUT0_DCMx1 |  BUFGMUX_X2Y4| No   |    4 |  0.009     |  1.398      |
+---------------------+--------------+------+------+------------+-------------+
|    GTPCLKOUT1_DCMx1 |  BUFGMUX_X3Y7| No   |  771 |  0.080     |  1.398      |
+---------------------+--------------+------+------+------------+-------------+
|               CLK63 |  BUFGMUX_X3Y6| No   |  145 |  0.065     |  1.386      |
+---------------------+--------------+------+------+------------+-------------+
|               CLKx5 |  BUFGMUX_X2Y3| No   |   48 |  0.515     |  1.845      |
+---------------------+--------------+------+------+------------+-------------+
| tile1_gtp0_refclk_i |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|tile1_gtp0_refclk_ib |              |      |      |            |             |
|     ufds_i_ML_IBUF1 |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|tile1_gtp0_refclk_ib |              |      |      |            |             |
|     ufds_i_ML_IBUF2 |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 3

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIO | SETUP       |     0.129ns|     2.942ns|       0|           0
  D TIMEGRP         "clk_wiz_v1_6_50x62x312 | HOLD        |     0.125ns|            |       0|           0
  _clkout1" TS_xtalclk_ip * 6.25 HIGH 50%   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_GTPCLKOUT1_DCMx1 = PERIOD TIMEGRP "GTP | SETUP       |     0.181ns|     6.485ns|       0|           0
  CLKOUT1_DCMx1" 150 MHz HIGH 50%           | HOLD        |     0.198ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  TS_xtalclk_ip = PERIOD TIMEGRP "xtalclk_i | MINLOWPULSE |    15.000ns|     5.000ns|       0|           0
  p" 50 MHz HIGH 50%                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_PLL162 = PERIOD TIMEGRP "PLL162" TS_DP | MINPERIOD   |     2.972ns|     3.200ns|       0|           0
  _CLK1 * 6 HIGH 50%                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_DP_CLK1 = PERIOD TIMEGRP "DP_CLK1" 27  | MINLOWPULSE |    21.036ns|    16.000ns|       0|           0
  MHz HIGH 50%                              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIO | SETUP       |     8.639ns|     7.361ns|       0|           0
  D TIMEGRP         "clk_wiz_v1_6_50x62x312 | HOLD        |     0.399ns|            |       0|           0
  _clkout0" TS_xtalclk_ip * 1.25 HIGH 50%   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27  | SETUP       |    29.809ns|     7.228ns|       0|           0
  MHz HIGH 50%                              | HOLD        |     0.399ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_xtalclk_ip
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_xtalclk_ip                  |     20.000ns|      5.000ns|     18.387ns|            0|            0|            0|         6977|
| TS_clk_wiz_v1_6_50x62x312_clko|      3.200ns|      2.942ns|          N/A|            0|            0|          256|            0|
| ut1                           |             |             |             |             |             |             |             |
| TS_clk_wiz_v1_6_50x62x312_clko|     16.000ns|      7.361ns|          N/A|            0|            0|         6721|            0|
| ut0                           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_DP_CLK1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_DP_CLK1                     |     37.037ns|     16.000ns|     19.200ns|            0|            0|            0|            0|
| TS_PLL162                     |      6.173ns|      3.200ns|          N/A|            0|            0|            0|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 92 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 35 secs 
Total CPU time to PAR completion (all processors): 40 secs 

Peak Memory Usage:  273 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 94
Number of info messages: 0

Writing design to file exp6t_disp_dp.ncd



PAR done!
