Release 12.2 Map M.63c (nt)
Xilinx Mapping Report File for Design 'exp6t_disp_dp'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0
-register_duplication on -global_opt speed -retiming on -equivalent_register_removal on -mt 2 -ir off -pr off -lc off
-power off -o exp6t_disp_dp_map.ncd exp6t_disp_dp.ngd exp6t_disp_dp.pcf 
Target Device  : xc6slx45t
Target Package : fgg484
Target Speed   : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date    : SAT 12 NOV 11:31:58 2011

Design Summary
--------------
Number of errors:      0
Number of warnings:   94
Slice Logic Utilization:
  Number of Slice Registers:                 2,767 out of  54,576    5%
    Number used as Flip Flops:               2,767
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      2,967 out of  27,288   10%
    Number used as logic:                    2,902 out of  27,288   10%
      Number using O6 output only:           2,752
      Number using O5 output only:              99
      Number using O5 and O6:                   51
      Number used as ROM:                        0
    Number used as Memory:                      12 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:            12
        Number using O6 output only:             6
        Number using O5 output only:             0
        Number using O5 and O6:                  6
    Number used exclusively as route-thrus:     53
      Number with same-slice register load:     43
      Number with same-slice carry load:        10
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 1,154 out of   6,822   16%
  Number of LUT Flip Flop pairs used:        3,173
    Number with an unused Flip Flop:           491 out of   3,173   15%
    Number with an unused LUT:                 206 out of   3,173    6%
    Number of fully used LUT-FF pairs:       2,476 out of   3,173   78%
    Number of unique control sets:              57
    Number of slice register sites lost
      to control set restrictions:             223 out of  54,576    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       154 out of     296   52%
    Number of LOCed IOBs:                      154 out of     154  100%
    IOB Flip Flops:                              4
    IOB Master Pads:                             5
    IOB Slave Pads:                              5
    Number of bonded IPADs:                      6 out of      16   37%
    Number of bonded OPADs:                      4 out of       8   50%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         3 out of     116    2%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 2 out of      32    6%
    Number used as BUFIO2s:                      2
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       8 out of      16   50%
    Number used as BUFGs:                        8
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     1 out of       8   12%
    Number used as DCMs:                         1
    Number used as DCM_CLKGENs:                  0
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   4 out of     376    1%
    Number used as OLOGIC2s:                     4
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of GTPA1_DUALs:                         1 out of       2   50%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       4   25%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                3.45

Peak Memory Usage:  314 MB
Total REAL time to MAP completion:  2 mins 47 secs 
Total CPU time to MAP completion (all processors):   2 mins 54 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:Place:1137 - This design is not guaranteed to be routable! This design
   contains a global buffer instance, <clk_wiz_v1_6_50x62x312/clkout1_buf>,
   driving the net, <CLK63>, that is driving the following (first 30) non-clock
   source pins.
   < PIN: tx_dvi/tx_req_r_0.D; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. Please pay extra attention to the timing and routing of this path to
   ensure the design goals are met. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <clk_wiz_v1_6_50x62x312/clkout1_buf.O> allowing your design to continue. This
   constraint disables all clock placer rules related to the specified COMP.PIN.
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock
   IOB / BUFGMUX site pair. The clock IOB component <DP_CLK0> is placed at site <PAD233>. The corresponding BUFG
   component <CLK27_BUFG> is placed at site <BUFGMUX_X2Y11>. There is only a select set of IOBs that can use the fast
   path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct
   it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <DP_CLK0.PAD> allowing
   your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use
   of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error
   condition be corrected in the design.
WARNING:PhysDesignRules:367 - The signal <TMDS_CEC_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_HPD_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_SDA_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_SCL_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_CLKOUT_IP_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<10>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<11>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<12>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<10>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<13>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<11>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<14>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<12>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<15>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<13>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<14>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<15>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DDR2_LDQS_N_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_LDQS_P_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<0>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<1>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<2>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_UDQS_N_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_UDQS_P_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<0>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<1>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<2>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<3>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<22>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<23>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<24>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<25>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<26>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<27>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<28>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<29>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<10>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<11>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<12>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<20>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<13>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<21>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<14>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<22>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<15>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<23>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<16>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<24>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<17>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<25>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<26>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<18>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<27>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<19>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<28>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<29>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGA_IP_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGB_IP_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGC_IP_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<0>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<1>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<0>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<2>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<1>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<3>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<2>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<4>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<3>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<5>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<4>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<6>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<5>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<7>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<6>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<8>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<7>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<9>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<8>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<9>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<0>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<1>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<2>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<3>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<4>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<5>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<6>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<7>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<8>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<9>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <CFG_MISO_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DP_RSV1_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DP_RSV2_IBUF> is incomplete. The signal does not drive any load pins in the
   design.

Section 3 - Informational
-------------------------
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
   supports the use of up to 2 processors. Based on the the user options and
   machine load, Map will use 2 processors during this run.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:Xst:2261 - The FF/Latch <dp_main/aux_tx/aux_state_r_FSM_FFd3> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/aux_tx/aux_state_r_FSM_FFd3_1> 
INFO:Xst:2261 - The FF/Latch <dp_main/aux_tx/aux_state_r_FSM_FFd4> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/aux_tx/aux_state_r_FSM_FFd4_1> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_tbc/tbc_de_count_r_0> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/dp_main_tbc/tbc_de_count_r_0_1> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_tbc/tbc_de_count_r_1> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/dp_main_tbc/tbc_de_count_r_1_1> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_tbc/tbc_state_r_FSM_FFd2> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/dp_main_tbc/tbc_state_r_FSM_FFd2_1> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_linkup/aux_cmd_code_r_35> in Unit
   <exp6t_disp_dp> is equivalent to the following 3 FFs/Latches, which will be
   removed : <dp_main/dp_main_linkup/aux_cmd_code_r_34>
   <dp_main/dp_main_linkup/aux_cmd_code_r_33>
   <dp_main/dp_main_linkup/aux_cmd_code_r_32> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_tbc/tbc_state_r_FSM_FFd4> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/dp_main_tbc/tbc_state_r_FSM_FFd4_1> 
INFO:Xst:2261 - The FF/Latch <dp_main/aux_tx/aux_state_r_FSM_FFd2> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/aux_tx/aux_state_r_FSM_FFd2_1> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_tbc/tbc_count_r_0> in Unit
   <exp6t_disp_dp> is equivalent to the following 2 FFs/Latches, which will be
   removed : <dp_main/dp_main_tbc/tbc_count_r_0_1>
   <dp_main/dp_main_tbc/tbc_count_r_0_2> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_tbc/tbc_count_r_1> in Unit
   <exp6t_disp_dp> is equivalent to the following 2 FFs/Latches, which will be
   removed : <dp_main/dp_main_tbc/tbc_count_r_1_1>
   <dp_main/dp_main_tbc/tbc_count_r_1_2> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_22_BRB2> in Unit
   <exp6t_disp_dp> is equivalent to the following 3 FFs/Latches, which will be
   removed : <dispgen1/data_out_r_2_BRB1_BRB0> <dispgen1/data_out_r_1_BRB1_BRB0>
   <dispgen1/data_out_r_0_BRB1_BRB0> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_4_BRB5> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dispgen1/data_out_r_0_BRB1_BRB3> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_crtc/disp_htiming_r_3_BRB0> in
   Unit <exp6t_disp_dp> is equivalent to the following 3 FFs/Latches, which will
   be removed : <dp_main/dp_main_crtc/disp_htiming_r_0_BRB0>
   <dp_main/dp_main_crtc/disp_vtiming_r_3_BRB0>
   <dp_main/dp_main_crtc/disp_vtiming_r_1_BRB0> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_4_BRB2> in Unit
   <exp6t_disp_dp> is equivalent to the following 3 FFs/Latches, which will be
   removed : <dispgen1/data_out_r_2_BRB1_BRB1> <dispgen1/data_out_r_1_BRB1_BRB1>
   <dispgen1/data_out_r_0_BRB1_BRB1> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_4_BRB1> in Unit
   <exp6t_disp_dp> is equivalent to the following 3 FFs/Latches, which will be
   removed : <dispgen1/data_out_r_12_BRB3_BRB3>
   <dispgen1/data_out_r_20_BRB3_BRB4> <dispgen1/data_out_r_0_BRB1_BRB4> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_4_BRB3> in Unit
   <exp6t_disp_dp> is equivalent to the following 5 FFs/Latches, which will be
   removed : <dispgen1/data_out_r_12_BRB3_BRB2>
   <dispgen1/data_out_r_20_BRB3_BRB2> <dispgen1/data_out_r_2_BRB1_BRB2>
   <dispgen1/data_out_r_1_BRB1_BRB2> <dispgen1/data_out_r_0_BRB1_BRB2> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_tbc/tx_data_wr_r_8> in Unit
   <exp6t_disp_dp> is equivalent to the following 4 FFs/Latches, which will be
   removed : <dp_main/dp_main_tbc/tx_data_wr_r_6_BRB0>
   <dp_main/dp_main_tbc/tx_data_wr_r_4_BRB0>
   <dp_main/dp_main_tbc/tx_data_wr_r_2_BRB0>
   <dp_main/dp_main_tbc/tx_data_wr_r_0_BRB0> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_22_BRB2> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dispgen1/data_out_r_22_BRB3_BRB0> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_4_BRB2> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dispgen1/data_out_r_22_BRB3_BRB1> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_4_BRB1> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dispgen1/data_out_r_22_BRB3_BRB5> 
INFO:Xst:2261 - The FF/Latch <dispgen1/data_out_r_4_BRB3> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dispgen1/data_out_r_22_BRB3_BRB2> 
INFO:Xst:2260 - The FF/Latch <dp_main/dp_main_crtc/disp_htiming_r_3_BRB0> in
   Unit <exp6t_disp_dp> is equivalent to the following FF/Latch :
   <dp_main/dp_main_crtc/disp_vtiming_r_0_BRB0> 
INFO:Xst:2260 - The FF/Latch <tx_dvi/enc2/Msub__n0423_xor<4>11_FRB> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch :
   <tx_dvi/enc2/_n0423<5>1_FRB> 
INFO:Xst:2260 - The FF/Latch <dp_main/dp_main_tbc/tx_data_wr_r_8> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch :
   <dp_main/dp_main_tbc/tx_data_wr_r_7_BRB0> 
INFO:Xst:2260 - The FF/Latch <tx_dvi/enc1/Msub__n0423_xor<4>11_FRB> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch :
   <tx_dvi/enc1/_n0423<5>1_FRB> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_crtc/disp_htiming_r_3_BRB0> in
   Unit <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/dp_main_crtc/disp_vtiming_r_0_BRB0> 
INFO:Xst:2261 - The FF/Latch <tx_dvi/enc2/Msub__n0423_xor<4>11_FRB> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <tx_dvi/enc2/_n0423<5>1_FRB> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_tbc/tx_data_wr_r_8> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <dp_main/dp_main_tbc/tx_data_wr_r_7_BRB0> 
INFO:Xst:2261 - The FF/Latch <tx_dvi/enc1/Msub__n0423_xor<4>11_FRB> in Unit
   <exp6t_disp_dp> is equivalent to the following FF/Latch, which will be
   removed : <tx_dvi/enc1/_n0423<5>1_FRB> 
INFO:LIT:243 - Logical network dipsw_ip<3>_IBUF has no load.
INFO:LIT:395 - The above info message is repeated 93 more times for the
   following (max. 5 shown):
   dipsw_ip<2>_IBUF,
   dipsw_ip<1>_IBUF,
   dipsw_ip<0>_IBUF,
   pushsw_ip<2>_IBUF,
   pushsw_ip<1>_IBUF
   To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:854 - One or more Dual Data Rate register has been found in the
   design.  All instances have been converted from the Virtex-II based primitive
   (with two clocks) to the Virtex-5 based primitive (with one clock) because
   the C0 and C1 clocks have been confirmed to be 180 degrees out of phase, or
   environment variable XIL_MAP_ALWAYS_RETARGET_FDDR was set in which case map
   does not confirm C0 and C1 clocks to be 180 degrees out of phase.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
INFO:Pack:1650 - Map created a placed design.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
   the DCM comp ctm_27x162/dcm_sp_inst, consult the device Data Sheet.

Section 4 - Removed Logic Summary
---------------------------------
   3 block(s) removed
   2 block(s) optimized away
   2 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "clk_wiz_v1_6_50x62x312/pll_base_inst/N2" is sourceless and has been
removed.
The signal "clk_wiz_v1_6_50x62x312/pll_base_inst/N3" is sourceless and has been
removed.
Unused block "USB_RESET_BP_PULLUP" (PULLUP) removed.
Unused block "clk_wiz_v1_6_50x62x312/pll_base_inst/XST_GND" (ZERO) removed.
Unused block "clk_wiz_v1_6_50x62x312/pll_base_inst/XST_VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| CFG_CCLK                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| CFG_CSO                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| CFG_MISO                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| CFG_MOSI                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| DDR2_A<0>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<1>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<2>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<3>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<4>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<5>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<6>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<7>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<8>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<9>                          | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<10>                         | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<11>                         | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_A<12>                         | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_BA<0>                         | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_BA<1>                         | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_BA<2>                         | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_CAS                           | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_CKE                           | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_CK_N                          | IOB              | OUTPUT    | DIFF_SSTL18_II       |       |          |      |              |          |          |
| DDR2_CK_P                          | IOB              | OUTPUT    | DIFF_SSTL18_II       |       |          |      |              |          |          |
| DDR2_D<0>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<1>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<2>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<3>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<4>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<5>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<6>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<7>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<8>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<9>                          | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<10>                         | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<11>                         | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<12>                         | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<13>                         | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<14>                         | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_D<15>                         | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_LDM                           | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_LDQS_N                        | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_LDQS_P                        | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_ODT                           | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_RAS                           | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_UDM                           | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DDR2_UDQS_N                        | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_UDQS_P                        | IOB              | INPUT     | SSTL18_I             |       |          |      |              |          |          |
| DDR2_WEN                           | IOB              | OUTPUT    | SSTL18_I             |       |          |      |              |          |          |
| DP_AUXO_N                          | IOBS             | OUTPUT    | LVDS_33              |       |          |      |              |          |          |
| DP_AUXO_P                          | IOBM             | OUTPUT    | LVDS_33              |       |          |      |              |          |          |
| DP_AUX_N                           | IOB              | INPUT     | LVDS_33              | TRUE  |          |      |              |          |          |
| DP_AUX_P                           | IOB              | INPUT     | LVDS_33              | TRUE  |          |      |              |          |          |
| DP_CLK0                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_CLK1                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_HPD                             | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_RST_N                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_RSV1                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_RSV2                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<22>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<23>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<24>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<25>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<26>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<27>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<28>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<29>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<0>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<1>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<2>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<3>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<4>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<5>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<6>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<7>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<8>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<9>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<10>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<11>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<12>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<13>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<14>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<15>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<16>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<17>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<18>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<19>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<20>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<21>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<22>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<23>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<24>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<25>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<26>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<27>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<28>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<29>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| TMDS_CEC                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| TMDS_CH0_N                         | IOBS             | OUTPUT    | TMDS_33              |       |          |      |              |          |          |
| TMDS_CH0_P                         | IOBM             | OUTPUT    | TMDS_33              |       |          |      | ODDR         |          |          |
| TMDS_CH1_N                         | IOBS             | OUTPUT    | TMDS_33              |       |          |      |              |          |          |
| TMDS_CH1_P                         | IOBM             | OUTPUT    | TMDS_33              |       |          |      | ODDR         |          |          |
| TMDS_CH2_N                         | IOBS             | OUTPUT    | TMDS_33              |       |          |      |              |          |          |
| TMDS_CH2_P                         | IOBM             | OUTPUT    | TMDS_33              |       |          |      | ODDR         |          |          |
| TMDS_CLK_N                         | IOBS             | OUTPUT    | TMDS_33              |       |          |      |              |          |          |
| TMDS_CLK_P                         | IOBM             | OUTPUT    | TMDS_33              |       |          |      | ODDR         |          |          |
| TMDS_HPD                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| TMDS_SCL                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| TMDS_SDA                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_CLKOUT_IP                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<0>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<1>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<2>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<3>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<4>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<5>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<6>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<7>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<8>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<9>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<10>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<11>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<12>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<13>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<14>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD_BP<15>                      | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FIFOADR_OP<0>                  | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_FIFOADR_OP<1>                  | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_FLAGA_IP                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FLAGB_IP                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FLAGC_IP                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_IFCLK_OP                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_PKTEND_OP                      | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_RESET_BP                       | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_SLOE_OP                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_SLRD_OP                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_SLWR_OP                        | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| dipsw_ip<0>                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| dipsw_ip<1>                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| dipsw_ip<2>                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| dipsw_ip<3>                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| led_op<0>                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led_op<1>                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led_op<2>                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led_op<3>                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led_op<4>                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led_op<5>                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led_op<6>                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led_op<7>                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pushsw_ip<0>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| pushsw_ip<1>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| pushsw_ip<2>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| pushsw_ip<3>                       | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| sata_refclkn_ip                    | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_refclkp_ip                    | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_rxn0_ip                       | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_rxn1_ip                       | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_rxp0_ip                       | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_rxp1_ip                       | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_txn0_op                       | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| sata_txn1_op                       | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| sata_txp0_op                       | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| sata_txp1_op                       | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| xtalclk_ip                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.

For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.

Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
