vlib work
vmap work
vlog -work work $env(XILINX)/verilog/src/glbl.v
vlog -f board.f

vlog  $env(XILINX)/verilog/src/unisims/*.v
vlog -f $env(XILINX)/secureip/mti/pcie_internal_1_1_mti/pcie_internal_1_1_cell.list.f
vlog -f $env(XILINX)/secureip/mti/pcie_2_0_mti/pcie_2_0_cell.list.f
vlog -f $env(XILINX)/secureip/mti/pcie_a1_mti/pcie_a1_cell.list.f
vlog -f $env(XILINX)/secureip/mti/gtx_dual_fast_mti/gtx_dual_fast_cell.list.f
vlog -f $env(XILINX)/secureip/mti/gtp_dual_fast_mti/gtp_dual_fast_cell.list.f
vlog -f $env(XILINX)/secureip/mti/gtpa1_dual_mti/gtpa1_dual_cell.list.f
vlog -f $env(XILINX)/secureip/mti/gt11_mti/gt11_cell.list.f
vlog -f $env(XILINX)/secureip/mti/gtxe1_mti/gtxe1_cell.list.f
vlog -f $env(XILINX)/secureip/mti/gthe1_quad_mti/gthe1_quad_cell.list.f

vlog ../../../../exp6t_disp.v
vlog +define+simulation ../../../../exp6t_disp.v
vlog ../../../../xil_clk_wiz_v1_6_50x200.v
vlog ../../../../xt_crtc.v
vlog ../../../../xil_clk_wiz_v1_6_50x62x312.v
vlog ../../../../xil_blk_mem_gen_v4_2_1024x32.v
vlog ../../../../xil_blk_mem_gen_v4_2_1024x32B.v
vlog ../../../../pciesample/sp6wrap.v
vlog ../../../../LYNX/xil_dvi.v
vlog ../../../../LYNX/dvi_data_enc.v

vlog ../../../xil_mig_v3_5_ddr2/user_design/rtl/*.v
#vlog  $env(XILINX)/verilog/src/glbl.v
#vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/*.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/sim_tb_top.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/afifo.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/cmd_gen.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/cmd_prbs_gen.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/data_prbs_gen.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/ddr2_model_c3.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/init_mem_pattern_ctr.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/mcb_flow_control.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/mcb_traffic_gen.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/rd_data_gen.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/read_data_path.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/read_posted_fifo.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/sp6_data_gen.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/tg_status.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/v6_data_gen.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/wr_data_gen.v
vlog  ../../../xil_mig_v3_5_ddr2/user_design/sim/write_data_path.v
#vlog  ../../../../xil_clk_wiz_v1_6_50x200.v
#vlog  ../../../../xil_blk_mem_gen_v4_2_1024x32.v
vlog $env(XILINX)/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2.v
vlog -f $env(XILINX)/secureip/mti/mcb_mti/mcb_cell.list.f
#vlog  $env(XILINX)/verilog/src/unisims/*.v
vlog  +incdir+. +define+x512Mb +define+sg37E +define+x16 ../../../xil_mig_v3_5_ddr2/user_design/sim/ddr2_model_c3.v
#vsim -t ps -novopt +notimingchecks work.sim_tb_top glbl

#vsim -voptargs="+acc" +notimingchecks +TESTNAME=sample_smoke_test0 -L work -L secureip \#
#     -L unisims_ver \#
#     work.board glbl#

vsim -voptargs="+acc" +notimingchecks +TESTNAME=sample_smoke_test1 work.board glbl

#do wave.do

add wave -radix hexadecimal sim:/board/EP/*
add wave -radix hexadecimal sim:/board/EP/inst_sp6wrap/*
add wave -radix hexadecimal sim:/board/EP/inst_sp6wrap/app/*
add wave -radix hexadecimal sim:/board/EP/inst_sp6wrap/app/mem/*
add wave -radix hexadecimal sim:/board/EP/inst_sp6wrap/app/PIO/*
add wave -radix hexadecimal sim:/board/EP/inst_sp6wrap/app/PIO/PIO_EP/*
add wave -radix hexadecimal sim:/board/EP/inst_sp6wrap/app/PIO/PIO_EP/EP_RX/*
add wave -radix hexadecimal sim:/board/EP/inst_sp6wrap/app/PIO/PIO_EP/EP_TX/*
#add wave -radix hexadecimal sim:/board/RP/rx_usrapp/next_trn_rx_timeout

#vsim -t ps -novopt +notimingchecks work.sim_tb_top glbl
#add wave sim:/sim_tb_top/*


run -all

