##################################################################
# System clock and LEDs, SWs
##################################################################

NET "xtalclk_ip" TNM_NET = "xtalclk_ip";
TIMESPEC "TS_xtalclk_ip" = PERIOD "xtalclk_ip" 50 MHz HIGH 50 %;

NET "xtalclk_ip" LOC = "U12" | IOSTANDARD = LVCMOS33;
NET "dipsw_ip<0>" LOC = U22 | IOstandard = LVCMOS33;
NET "dipsw_ip<1>" LOC = V22 | IOstandard = LVCMOS33;
NET "dipsw_ip<2>" LOC = P21 | IOstandard = LVCMOS33;
NET "dipsw_ip<3>" LOC = P20 | IOstandard = LVCMOS33;
NET "pushsw_ip<0>"  LOC = Y22 | IOstandard = LVCMOS33;
NET "pushsw_ip<1>"  LOC = W22 | IOstandard = LVCMOS33;
NET "pushsw_ip<2>"  LOC = Y21 | IOstandard = LVCMOS33;
NET "pushsw_ip<3>"  LOC = W20 | IOstandard = LVCMOS33;

NET "led_op<0>"  LOC = R20 | IOstandard = LVCMOS33;
NET "led_op<1>"  LOC = R22 | IOstandard = LVCMOS33;
NET "led_op<2>"  LOC = T21 | IOstandard = LVCMOS33;
NET "led_op<3>"  LOC = T22 | IOstandard = LVCMOS33;
NET "led_op<4>"  LOC = U20 | IOstandard = LVCMOS33;
NET "led_op<5>"  LOC = V21 | IOstandard = LVCMOS33;
NET "led_op<6>"  LOC = P22 | IOstandard = LVCMOS33;
NET "led_op<7>"  LOC = T20 | IOstandard = LVCMOS33;

##################################################################
# Gigabit tranceiver channel
##################################################################

NET "GTPCLKOUT1_DCMx1" TNM_NET = GTPCLKOUT1_DCMx1;
TIMESPEC TS_GTPCLKOUT1_DCMx1 = PERIOD "GTPCLKOUT1_DCMx1" 150 MHz HIGH 50%;

##for PCIe CARD EDGE
#NET "epcie_txp_op" LOC = B8;
#NET "epcie_txn_op" LOC = A8;
#NET "epcie_rxp_ip" LOC = D9;
#NET "epcie_rxn_ip" LOC = C9;
#NET "epcie_refclkn_ip" LOC = D11; # EPCIE
#NET "epcie_refclkp_ip" LOC = C11; # EPCIE
#NET "epcie_perst_ip"    LOC = F15;
#NET "epcie_wake_op"     LOC = G13;

##for PCIe external cabling
#NET "cpcie_txp_op" LOC = B6;
#NET "cpcie_txn_op" LOC = A6;
#NET "cpcie_rxp_ip" LOC = D7;
#NET "cpcie_rxn_ip" LOC = C7;
#NET "cpcie_refclkn_ip" LOC = B10;
#NET "cpcie_refclkp_ip" LOC = A10;
#NET "cpcie_perst_ip"    LOC = A2;
#NET "cpcie_wake_op"     LOC = B3;

#for SATA
NET "sata_txp0_op" LOC = B14;
NET "sata_txn0_op" LOC = A14;
NET "sata_rxp0_ip" LOC = D13;
NET "sata_rxn0_ip" LOC = C13;
NET "sata_txp1_op" LOC = B16;
NET "sata_txn1_op" LOC = A16;
NET "sata_rxp1_ip" LOC = D15;
NET "sata_rxn1_ip" LOC = C15;
NET "sata_refclkn_ip" LOC = B12;
NET "sata_refclkp_ip" LOC = A12;

#NET inst_pipe/tile0_gtp0_refclk_i PERIOD = 10ns;

#NET inst_pipe/pipe_clk(0) TNM_NET = PIPE_CLK;
#TIMESPEC TS_PIPE_CLK = PERIOD PIPE_CLK 10ns HIGH 50 % ;

##################################################################
# DDR2 SDRAM
##################################################################

NET "DDR2_RAS"           LOC = "M5" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_CAS"           LOC = "M4" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_WEN"           LOC = "H2" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
#NET "DDR2_CS"            LOC = "" | IOSTANDARD = SSTL18_I;
NET "DDR2_CKE"           LOC = "F2" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<0>"          LOC = "K2" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<1>"          LOC = "K1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<2>"          LOC = "K5" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<3>"          LOC = "M6" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<4>"          LOC = "H3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<5>"          LOC = "M3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<6>"          LOC = "L4" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<7>"          LOC = "K6" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<8>"          LOC = "G3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<9>"          LOC = "G1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<10>"         LOC = "J4" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<11>"         LOC = "E1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_A<12>"         LOC = "F1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_BA<0>"         LOC = "J3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_BA<1>"         LOC = "J1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_BA<2>"         LOC = "H1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<0>"          LOC = "R1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<1>"          LOC = "M1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<2>"          LOC = "P2" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<3>"          LOC = "L1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<4>"          LOC = "L3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<5>"          LOC = "P1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<6>"          LOC = "M2" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<7>"          LOC = "R3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<8>"          LOC = "W3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<9>"          LOC = "T1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<10>"         LOC = "Y2" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<11>"         LOC = "U3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<12>"         LOC = "T2" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<13>"         LOC = "W1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<14>"         LOC = "U1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_D<15>"         LOC = "Y1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_LDM"           LOC = "N4" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_ODT"           LOC = "L6" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_CK_P"          LOC = "K4" | IOSTANDARD = DIFF_SSTL18_II | OUT_TERM = UNTUNED_25;
NET "DDR2_CK_N"          LOC = "K3" | IOSTANDARD = DIFF_SSTL18_II | OUT_TERM = UNTUNED_25;
NET "DDR2_LDQS_P"        LOC = "N3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_LDQS_N"        LOC = "N1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;

NET "DDR2_UDM"           LOC = "P3" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_UDQS_P"        LOC = "V2" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;
NET "DDR2_UDQS_N"        LOC = "V1" | IOSTANDARD = SSTL18_I | OUT_TERM = UNTUNED_50;

NET "DDR2_D<0>" IFD_DELAY_VALUE = 0;
NET "DDR2_D<1>" IFD_DELAY_VALUE = 0;
NET "DDR2_D<2>" IFD_DELAY_VALUE = 0;
NET "DDR2_D<3>" IFD_DELAY_VALUE = 0;
NET "DDR2_D<4>" IFD_DELAY_VALUE = 0;
NET "DDR2_D<5>" IFD_DELAY_VALUE = 0;
NET "DDR2_D<6>" IFD_DELAY_VALUE = 0;
NET "DDR2_D<7>" IFD_DELAY_VALUE = 0;

##################################################################
# GPIO
##################################################################

NET "DP_CLK1" CLOCK_DEDICATED_ROUTE = FALSE;
NET "DP_CLK0" CLOCK_DEDICATED_ROUTE = FALSE;

PIN "clk_wiz_v1_6_50x62x312/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;

NET "DP_CLK0" TNM_NET = DP_CLK0;
TIMESPEC TS_DP_CLK0 = PERIOD "DP_CLK0" 27 MHz HIGH 50%;
NET "DP_CLK1" TNM_NET = DP_CLK1;
TIMESPEC TS_DP_CLK1 = PERIOD "DP_CLK1" 27 MHz HIGH 50%;

NET "GPIO9C<0>" LOC = "AA18" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<1>" LOC = "AB18" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<2>" LOC = "Y17" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<3>" LOC = "AB17" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<4>" LOC = "AA16" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<5>" LOC = "AB16" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<6>" LOC = "Y15" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<7>" LOC = "AB15" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<8>" LOC = "AA14" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<9>" LOC = "AB14" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<10>" LOC = "Y13" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<11>" LOC = "AB13" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<12>" LOC = "AA12" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<13>" LOC = "AB12" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<14>" LOC = "Y11" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<15>" LOC = "AB11" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<16>" LOC = "AA10" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<17>" LOC = "AB10" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<18>" LOC = "Y9 " | IOSTANDARD = LVCMOS33;
NET "GPIO9C<19>" LOC = "AB9" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<20>" LOC = "AA8" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<21>" LOC = "AB8" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<22>" LOC = "Y7 " | IOSTANDARD = LVCMOS33;
NET "GPIO9C<23>" LOC = "AB7" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<24>" LOC = "AA6" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<25>" LOC = "AB6" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<26>" LOC = "Y5 " | IOSTANDARD = LVCMOS33;
NET "GPIO9C<27>" LOC = "AB5" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<28>" LOC = "AA4" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<29>" LOC = "AB4" | IOSTANDARD = LVCMOS33;
NET "TMDS_CH2_P" LOC = "W17" | IOSTANDARD = TMDS_33; # GPIO1C<0>
NET "TMDS_CH2_N" LOC = "Y18" | IOSTANDARD = TMDS_33;
NET "TMDS_CH1_P" LOC = "V17" | IOSTANDARD = TMDS_33;
NET "TMDS_CH1_N" LOC = "W18" | IOSTANDARD = TMDS_33;
NET "TMDS_CH0_P" LOC = "U16" | IOSTANDARD = TMDS_33;
NET "TMDS_CH0_N" LOC = "V15" | IOSTANDARD = TMDS_33;
NET "TMDS_CLK_P" LOC = "U14" | IOSTANDARD = TMDS_33;
NET "TMDS_CLK_N" LOC = "U13" | IOSTANDARD = TMDS_33;
NET "TMDS_CEC" LOC = "W14" | IOSTANDARD = LVCMOS33;
NET "TMDS_SCL" LOC = "Y14" | IOSTANDARD = LVCMOS33;
NET "TMDS_SDA" LOC = "V13" | IOSTANDARD = LVCMOS33;
NET "TMDS_HPD" LOC = "W13" | IOSTANDARD = LVCMOS33;
NET "DP_RSV1" LOC = "W12" | IOSTANDARD = LVCMOS33;
NET "DP_RSV2" LOC = "Y12" | IOSTANDARD = LVCMOS33;
NET "DP_AUX_P" LOC = "V11" | IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
NET "DP_AUX_N" LOC = "W11" | IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
NET "DP_AUXO_P" LOC = "W10" | IOSTANDARD = LVDS_33;
NET "DP_AUXO_N" LOC = "Y10" | IOSTANDARD = LVDS_33;
NET "DP_HPD" LOC = "W9" | IOSTANDARD = LVCMOS33;
NET "DP_RST_N" LOC = "Y8" | IOSTANDARD = LVCMOS33;
NET "DP_CLK0" LOC = "U9" | IOSTANDARD = LVCMOS33;
NET "DP_CLK1" LOC = "V9" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<22>" LOC = "T8" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<23>" LOC = "U8" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<24>" LOC = "W6" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<25>" LOC = "Y6" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<26>" LOC = "T7" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<27>" LOC = "U6" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<28>" LOC = "T10" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<29>" LOC = "U10" | IOSTANDARD = LVCMOS33;
#NET "GPIO_bp<*>" IOSTANDARD = LVCMOS33;

##################################################################
# EZ-USB FX2 Interface
##################################################################

NET "usb_clkout_ip" TNM_NET = "usb_clkout_ip";
TIMESPEC "TS_usb_clkout_ip" = PERIOD "usb_clkout_ip" 20 ns HIGH 50 %;

NET "USB_FD_BP<0>"      LOC = "E22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<1>"      LOC = "D22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<2>"      LOC = "D21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<3>"      LOC = "C22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<4>"      LOC = "F20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<5>"      LOC = "F22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<6>"      LOC = "F21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<7>"      LOC = "G22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<8>"      LOC = "N20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<9>"      LOC = "M20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<10>"     LOC = "K20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<11>"     LOC = "J20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<12>"     LOC = "H20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<13>"     LOC = "G20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<14>"     LOC = "E20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD_BP<15>"     LOC = "C20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FLAGA_IP"      LOC = "H22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FLAGB_IP"      LOC = "H21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FLAGC_IP"      LOC = "J22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_SLRD_OP"       LOC = "B21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_SLWR_OP"       LOC = "B22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_SLOE_OP"       LOC = "K22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FIFOADR_OP<0>" LOC = "K21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FIFOADR_OP<1>" LOC = "M22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_PKTEND_OP"     LOC = "M21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_CLKOUT_IP"     LOC = "L20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_IFCLK_OP"      LOC = "L22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_RESET_BP"      LOC = "N22" | PULLUP | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;

##################################################################
# SPI Configuration Memory
##################################################################

NET "CFG_CSO"           LOC = "AA3" | IOSTANDARD = LVCMOS33;
NET "CFG_CCLK"          LOC = "Y20" | IOSTANDARD = LVCMOS33;
NET "CFG_MISO"          LOC = "AA20" | IOSTANDARD = LVCMOS33;
NET "CFG_MOSI"          LOC = "AB20" | IOSTANDARD = LVCMOS33;
