<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
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<messages>
<msg type="info" file="Map" num="284" delta="old" >Map is running with the multi-threading option on. Map currently supports the use of up to 2 processors. Based on the the user options and machine load, Map will use 2 processors during this run.
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/aux_tx/aux_state_r_FSM_FFd3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/aux_tx/aux_state_r_FSM_FFd3_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/aux_tx/aux_state_r_FSM_FFd4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/aux_tx/aux_state_r_FSM_FFd4_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tbc_de_count_r_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tbc_de_count_r_0_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tbc_de_count_r_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tbc_de_count_r_1_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tbc_state_r_FSM_FFd2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tbc_state_r_FSM_FFd2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_linkup/aux_cmd_code_r_35</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">3 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_linkup/aux_cmd_code_r_34&gt; &lt;dp_main/dp_main_linkup/aux_cmd_code_r_33&gt; &lt;dp_main/dp_main_linkup/aux_cmd_code_r_32&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tbc_state_r_FSM_FFd4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tbc_state_r_FSM_FFd4_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/aux_tx/aux_state_r_FSM_FFd2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/aux_tx/aux_state_r_FSM_FFd2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tbc_count_r_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tbc_count_r_0_1&gt; &lt;dp_main/dp_main_tbc/tbc_count_r_0_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tbc_count_r_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tbc_count_r_1_1&gt; &lt;dp_main/dp_main_tbc/tbc_count_r_1_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_22_BRB2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">3 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_2_BRB1_BRB0&gt; &lt;dispgen1/data_out_r_1_BRB1_BRB0&gt; &lt;dispgen1/data_out_r_0_BRB1_BRB0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_4_BRB5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_0_BRB1_BRB3&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_crtc/disp_htiming_r_3_BRB0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">3 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_crtc/disp_htiming_r_0_BRB0&gt; &lt;dp_main/dp_main_crtc/disp_vtiming_r_3_BRB0&gt; &lt;dp_main/dp_main_crtc/disp_vtiming_r_1_BRB0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_4_BRB2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">3 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_2_BRB1_BRB1&gt; &lt;dispgen1/data_out_r_1_BRB1_BRB1&gt; &lt;dispgen1/data_out_r_0_BRB1_BRB1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_4_BRB1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">3 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_12_BRB3_BRB3&gt; &lt;dispgen1/data_out_r_20_BRB3_BRB4&gt; &lt;dispgen1/data_out_r_0_BRB1_BRB4&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_4_BRB3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">5 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_12_BRB3_BRB2&gt; &lt;dispgen1/data_out_r_20_BRB3_BRB2&gt; &lt;dispgen1/data_out_r_2_BRB1_BRB2&gt; &lt;dispgen1/data_out_r_1_BRB1_BRB2&gt; &lt;dispgen1/data_out_r_0_BRB1_BRB2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tx_data_wr_r_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tx_data_wr_r_6_BRB0&gt; &lt;dp_main/dp_main_tbc/tx_data_wr_r_4_BRB0&gt; &lt;dp_main/dp_main_tbc/tx_data_wr_r_2_BRB0&gt; &lt;dp_main/dp_main_tbc/tx_data_wr_r_0_BRB0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_22_BRB2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_22_BRB3_BRB0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_4_BRB2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_22_BRB3_BRB1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_4_BRB1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_22_BRB3_BRB5&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dispgen1/data_out_r_4_BRB3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dispgen1/data_out_r_22_BRB3_BRB2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_crtc/disp_htiming_r_3_BRB0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;dp_main/dp_main_crtc/disp_vtiming_r_0_BRB0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">tx_dvi/enc2/Msub__n0423_xor&lt;4&gt;11_FRB</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;tx_dvi/enc2/_n0423&lt;5&gt;1_FRB&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tx_data_wr_r_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tx_data_wr_r_7_BRB0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">tx_dvi/enc1/Msub__n0423_xor&lt;4&gt;11_FRB</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;tx_dvi/enc1/_n0423&lt;5&gt;1_FRB&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_crtc/disp_htiming_r_3_BRB0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_crtc/disp_vtiming_r_0_BRB0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">tx_dvi/enc2/Msub__n0423_xor&lt;4&gt;11_FRB</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;tx_dvi/enc2/_n0423&lt;5&gt;1_FRB&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">dp_main/dp_main_tbc/tx_data_wr_r_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;dp_main/dp_main_tbc/tx_data_wr_r_7_BRB0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">tx_dvi/enc1/Msub__n0423_xor&lt;4&gt;11_FRB</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">exp6t_disp_dp</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;tx_dvi/enc1/_n0423&lt;5&gt;1_FRB&gt; </arg>
</msg>

<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">dipsw_ip&lt;3&gt;_IBUF</arg> has no load.
</msg>

<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">93</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">dipsw_ip&lt;2&gt;_IBUF,
dipsw_ip&lt;1&gt;_IBUF,
dipsw_ip&lt;0&gt;_IBUF,
pushsw_ip&lt;2&gt;_IBUF,
pushsw_ip&lt;1&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>

<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>

<msg type="info" file="MapLib" num="854" delta="old" >One or more Dual Data Rate register has been found in the design.  All instances have been converted from the Virtex-II based primitive (with two clocks) to the Virtex-5 based primitive (with one clock) because the C0 and C1 clocks have been confirmed to be 180 degrees out of phase, or environment variable XIL_MAP_ALWAYS_RETARGET_FDDR was set in which case map does not confirm C0 and C1 clocks to be 180 degrees out of phase.
</msg>

<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>

<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>

<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>

<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>

<msg type="warning" file="Place" num="1137" delta="old" >This design is not guaranteed to be routable! This design contains a global buffer instance, &lt;<arg fmt="%s" index="1">clk_wiz_v1_6_50x62x312/clkout1_buf</arg>&gt;, driving the net, &lt;<arg fmt="%s" index="2">CLK63</arg>&gt;, that is driving the following (first <arg fmt="%d" index="3">30</arg>) non-clock source pins.
<arg fmt="%s" index="4">&lt; PIN: tx_dvi/tx_req_r_0.D; &gt;
</arg>This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations.  It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">clk_wiz_v1_6_50x62x312/clkout1_buf</arg>.<arg fmt="%s" index="6">O</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
</msg>

<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">DP_CLK0</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD233</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">CLK27_BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y11</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">DP_CLK0.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
</msg>

<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">TMDS_CEC_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">TMDS_HPD_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">TMDS_SDA_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">TMDS_SCL_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_CLKOUT_IP_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;10&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;11&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;12&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;10&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;13&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;11&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;14&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;12&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;15&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;13&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;14&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;15&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_LDQS_N_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_LDQS_P_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">pushsw_ip&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">pushsw_ip&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">pushsw_ip&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_UDQS_N_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_UDQS_P_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">dipsw_ip&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">dipsw_ip&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">dipsw_ip&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">dipsw_ip&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO1C&lt;22&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO1C&lt;23&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO1C&lt;24&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO1C&lt;25&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO1C&lt;26&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO1C&lt;27&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO1C&lt;28&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO1C&lt;29&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;10&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;11&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;12&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;20&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;13&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;21&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;14&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;22&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;15&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;23&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;16&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;24&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;17&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;25&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;26&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;18&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;27&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;19&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;28&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;29&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FLAGA_IP_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FLAGB_IP_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FLAGC_IP_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;4&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;5&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;4&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;5&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;7&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;8&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;7&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">USB_FD_BP&lt;9&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;8&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DDR2_D&lt;9&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;4&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;5&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;7&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;8&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">GPIO9C&lt;9&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">CFG_MISO_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DP_RSV1_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">DP_RSV2_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

<msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">ctm_27x162/dcm_sp_inst</arg>, consult the device Data Sheet.
</msg>

</messages>

