<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
					twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
							   NETDELAY | 
							   NETSKEW | 
							   PATH |
							   DEFPERIOD |
							   UNCONSTPATH |
							   DEFPATH | 
							   PATH2SETUP |
							   UNCONSTPATH2SETUP | 
							   PATHCLASS | 
							   PATHDELAY | 
							   PERIOD |
							   FREQUENCY |
							   PATHBLOCK |
							   OFFSET |
							   OFFSETIN |
							   OFFSETINCLOCK | 
							   UNCONSTOFFSETINCLOCK |
							   OFFSETINDELAY |
							   OFFSETINMOD |
							   OFFSETOUT |
							   OFFSETOUTCLOCK |
							   UNCONSTOFFSETOUTCLOCK | 
							   OFFSETOUTDELAY |
							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
					   twEndPtCnt?,
					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
						twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
					  fDCMJit CDATA #IMPLIED
					  fPhaseErr CDATA #IMPLIED
					  sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
					  best CDATA #IMPLIED requested CDATA #IMPLIED
					  errors CDATA #IMPLIED
					  score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 12.2 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml exp6t_disp_dp.twx exp6t_disp_dp.ncd -o exp6t_disp_dp.twr
exp6t_disp_dp.pcf

</twCmdLine><twDesign>exp6t_disp_dp.ncd</twDesign><twDesignPath>exp6t_disp_dp.ncd</twDesignPath><twPCF>exp6t_disp_dp.pcf</twPCF><twPcfPath>exp6t_disp_dp.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx45t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRELIMINARY 1.10 2010-06-28</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="4" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_xtalclk_ip = PERIOD TIMEGRP &quot;xtalclk_ip&quot; 50 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.000</twMinPer></twConstHead><twPinLimitRpt anchorID="5"><twPinLimitBanner>Component Switching Limit Checks: TS_xtalclk_ip = PERIOD TIMEGRP &quot;xtalclk_ip&quot; 50 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="6" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="2.249" period="3.200" constraintValue="3.200" deviceLimit="0.951" freqLimit="1051.525" physResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1" logResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1" locationPin="PLL_ADV_X0Y3.CLKOUT1" clockNet="clk_wiz_v1_6_50x62x312/clkout1"/><twPinLimit anchorID="7" type="MAXPERIOD" name="Tpllper_CLKFB" slack="12.630" period="40.000" constraintValue="40.000" deviceLimit="52.630" freqLimit="19.001" physResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKFBOUT" logResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKFBOUT" locationPin="PLL_ADV_X0Y3.CLKFBOUT" clockNet="clk_wiz_v1_6_50x62x312/clkfbout"/><twPinLimit anchorID="8" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="15.000" period="20.000" constraintValue="10.000" deviceLimit="2.500" physResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKIN1" logResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y3.CLKIN2" clockNet="clk_wiz_v1_6_50x62x312/clkin1"/></twPinLimitRpt></twConst><twConst anchorID="9" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_GTPCLKOUT1_DCMx1 = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCMx1&quot; 150 MHz HIGH 50%;</twConstName><twItemCnt>16163</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>6927</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>6.485</twMinPer></twConstHead><twPathRptBanner iPaths="15" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/tbc_rd_data03_r_50 (SLICE_X43Y41.CE), 15 paths
</twPathRptBanner><twPathRpt anchorID="10"><twConstPath anchorID="11" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.181</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_count_r_0</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_50</twDest><twTotPathDel>6.378</twTotPathDel><twClkSkew dest = "0.574" src = "0.646">0.072</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_count_r_0</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_50</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X41Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X41Y65.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;2&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_count_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y64.C6</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X40Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>N226</twComp><twBEL>lut3241_260</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.A4</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">0.943</twDelInfo><twComp>lut3241_260</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3356_288_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.535</twDelInfo><twComp>lut3356_2881</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_50</twBEL></twPathDel><twLogDel>1.591</twLogDel><twRouteDel>4.787</twRouteDel><twTotDel>6.378</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>24.9</twPctLog><twPctRoute>75.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.270</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/fsmfake10_2</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_50</twDest><twTotPathDel>6.290</twTotPathDel><twClkSkew dest = "0.574" src = "0.645">0.071</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/fsmfake10_2</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_50</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X38Y65.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;3&gt;</twComp><twBEL>dp_main/dp_main_tbc/fsmfake10_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y64.C2</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">0.882</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;1&gt;</twComp><twBEL>lut3341_282</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.218</twDelInfo><twComp>lut3341_282</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_50</twBEL></twPathDel><twLogDel>1.451</twLogDel><twRouteDel>4.839</twRouteDel><twTotDel>6.290</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>23.1</twPctLog><twPctRoute>76.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.285</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_count_r_1</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_50</twDest><twTotPathDel>6.274</twTotPathDel><twClkSkew dest = "0.574" src = "0.646">0.072</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_count_r_1</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_50</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X41Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X41Y65.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;2&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_count_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y64.C5</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.466</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X40Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>N226</twComp><twBEL>lut3241_260</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.A4</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">0.943</twDelInfo><twComp>lut3241_260</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3356_288_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.535</twDelInfo><twComp>lut3356_2881</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_50</twBEL></twPathDel><twLogDel>1.591</twLogDel><twRouteDel>4.683</twRouteDel><twTotDel>6.274</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>25.4</twPctLog><twPctRoute>74.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="15" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/tbc_rd_data03_r_49 (SLICE_X43Y41.CE), 15 paths
</twPathRptBanner><twPathRpt anchorID="16"><twConstPath anchorID="17" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.199</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_count_r_0</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_49</twDest><twTotPathDel>6.360</twTotPathDel><twClkSkew dest = "0.574" src = "0.646">0.072</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_count_r_0</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_49</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X41Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X41Y65.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;2&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_count_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y64.C6</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X40Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>N226</twComp><twBEL>lut3241_260</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.A4</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">0.943</twDelInfo><twComp>lut3241_260</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3356_288_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.535</twDelInfo><twComp>lut3356_2881</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_49</twBEL></twPathDel><twLogDel>1.573</twLogDel><twRouteDel>4.787</twRouteDel><twTotDel>6.360</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>24.7</twPctLog><twPctRoute>75.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="18"><twConstPath anchorID="19" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.288</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/fsmfake10_2</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_49</twDest><twTotPathDel>6.272</twTotPathDel><twClkSkew dest = "0.574" src = "0.645">0.071</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/fsmfake10_2</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_49</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X38Y65.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;3&gt;</twComp><twBEL>dp_main/dp_main_tbc/fsmfake10_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y64.C2</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">0.882</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;1&gt;</twComp><twBEL>lut3341_282</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.218</twDelInfo><twComp>lut3341_282</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_49</twBEL></twPathDel><twLogDel>1.433</twLogDel><twRouteDel>4.839</twRouteDel><twTotDel>6.272</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>22.8</twPctLog><twPctRoute>77.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="20"><twConstPath anchorID="21" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.303</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_count_r_1</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_49</twDest><twTotPathDel>6.256</twTotPathDel><twClkSkew dest = "0.574" src = "0.646">0.072</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_count_r_1</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_49</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X41Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X41Y65.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;2&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_count_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y64.C5</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.466</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X40Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>N226</twComp><twBEL>lut3241_260</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.A4</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">0.943</twDelInfo><twComp>lut3241_260</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3356_288_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.535</twDelInfo><twComp>lut3356_2881</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_49</twBEL></twPathDel><twLogDel>1.573</twLogDel><twRouteDel>4.683</twRouteDel><twTotDel>6.256</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>25.1</twPctLog><twPctRoute>74.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="15" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/tbc_rd_data03_r_51 (SLICE_X43Y41.CE), 15 paths
</twPathRptBanner><twPathRpt anchorID="22"><twConstPath anchorID="23" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.207</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_count_r_0</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_51</twDest><twTotPathDel>6.352</twTotPathDel><twClkSkew dest = "0.574" src = "0.646">0.072</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_count_r_0</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_51</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X41Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X41Y65.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;2&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_count_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y64.C6</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X40Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>N226</twComp><twBEL>lut3241_260</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.A4</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">0.943</twDelInfo><twComp>lut3241_260</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3356_288_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.535</twDelInfo><twComp>lut3356_2881</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.382</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_51</twBEL></twPathDel><twLogDel>1.565</twLogDel><twRouteDel>4.787</twRouteDel><twTotDel>6.352</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>24.6</twPctLog><twPctRoute>75.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="24"><twConstPath anchorID="25" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.296</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/fsmfake10_2</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_51</twDest><twTotPathDel>6.264</twTotPathDel><twClkSkew dest = "0.574" src = "0.645">0.071</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/fsmfake10_2</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_51</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X38Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X38Y65.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;3&gt;</twComp><twBEL>dp_main/dp_main_tbc/fsmfake10_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y64.C2</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">0.882</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/dp_main_tbc/fsmfake10&lt;1&gt;</twComp><twBEL>lut3341_282</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.218</twDelInfo><twComp>lut3341_282</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.382</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_51</twBEL></twPathDel><twLogDel>1.425</twLogDel><twRouteDel>4.839</twRouteDel><twTotDel>6.264</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>22.7</twPctLog><twPctRoute>77.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="26"><twConstPath anchorID="27" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.311</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_count_r_1</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_rd_data03_r_51</twDest><twTotPathDel>6.248</twTotPathDel><twClkSkew dest = "0.574" src = "0.646">0.072</twClkSkew><twDelConst>6.666</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_count_r_1</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_rd_data03_r_51</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X41Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X41Y65.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;2&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_count_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y64.C5</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.466</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_count_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X40Y64.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>N226</twComp><twBEL>lut3241_260</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.A4</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">0.943</twDelInfo><twComp>lut3241_260</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3356_288_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y59.C2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.535</twDelInfo><twComp>lut3356_2881</twComp></twPathDel><twPathDel><twSite>SLICE_X41Y59.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut3359_2902</twComp><twBEL>lut3359_290_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y41.CE</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.739</twDelInfo><twComp>lut3359_2901</twComp></twPathDel><twPathDel><twSite>SLICE_X43Y41.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.382</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_rd_data03_r&lt;51&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_rd_data03_r_51</twBEL></twPathDel><twLogDel>1.565</twLogDel><twRouteDel>4.683</twRouteDel><twTotDel>6.248</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>25.0</twPctLog><twPctRoute>75.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_GTPCLKOUT1_DCMx1 = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCMx1&quot; 150 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i (GTPA1_DUAL_X1Y0.TXCHARISK10), 1 path
</twPathRptBanner><twPathRpt anchorID="28"><twConstPath anchorID="29" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.198</twSlack><twSrc BELType="FF">dp_main/dp_main_scramble/sc_data0_out2_r_8</twSrc><twDest BELType="HSIO">xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i</twDest><twTotPathDel>0.250</twTotPathDel><twClkSkew dest = "0.120" src = "0.068">-0.052</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="27" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_scramble/sc_data0_out2_r_8</twSrc><twDest BELType='HSIO'>xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X52Y116.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X52Y116.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>dp_main/dp_main_scramble/sc_data0_out2_r&lt;8&gt;</twComp><twBEL>dp_main/dp_main_scramble/sc_data0_out2_r_8</twBEL></twPathDel><twPathDel><twSite>GTPA1_DUAL_X1Y0.TXCHARISK10</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.516</twDelInfo><twComp>dp_main/dp_main_scramble/sc_data0_out2_r&lt;8&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>GTPA1_DUAL_X1Y0.TXUSRCLK21</twSite><twDelType>Tgtpckc_TXCHARISK</twDelType><twDelInfo twEdge="twFalling">-0.500</twDelInfo><twComp>xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i</twComp><twBEL>xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i</twBEL></twPathDel><twLogDel>-0.266</twLogDel><twRouteDel>0.516</twRouteDel><twTotDel>0.250</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>-106.4</twPctLog><twPctRoute>206.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y28.DIA4), 1 path
</twPathRptBanner><twPathRpt anchorID="30"><twConstPath anchorID="31" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.265</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tx_data00_in_r_4</twSrc><twDest BELType="RAM">dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twTotPathDel>0.270</twTotPathDel><twClkSkew dest = "0.068" src = "0.063">-0.005</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tx_data00_in_r_4</twSrc><twDest BELType='RAM'>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X41Y56.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X41Y56.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data00_in_r&lt;5&gt;</twComp><twBEL>dp_main/dp_main_tbc/tx_data00_in_r_4</twBEL></twPathDel><twPathDel><twSite>RAMB16_X2Y28.DIA4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.125</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data00_in_r&lt;4&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X2Y28.CLKA</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.053</twDelInfo><twComp>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twComp><twBEL>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twLogDel>0.145</twLogDel><twRouteDel>0.125</twRouteDel><twTotDel>0.270</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>53.7</twPctLog><twPctRoute>46.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_scramble/sc_op_count_512_r_3 (SLICE_X44Y93.CE), 1 path
</twPathRptBanner><twPathRpt anchorID="32"><twConstPath anchorID="33" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.266</twSlack><twSrc BELType="FF">dp_main/dp_main_scramble/pack_data0_in_bs_r</twSrc><twDest BELType="FF">dp_main/dp_main_scramble/sc_op_count_512_r_3</twDest><twTotPathDel>0.272</twTotPathDel><twClkSkew dest = "0.044" src = "0.038">-0.006</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_scramble/pack_data0_in_bs_r</twSrc><twDest BELType='FF'>dp_main/dp_main_scramble/sc_op_count_512_r_3</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X44Y91.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X44Y91.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>dp_main/dp_main_scramble/pack_data0_in_bs_r</twComp><twBEL>dp_main/dp_main_scramble/pack_data0_in_bs_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X44Y93.CE</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twFalling">0.146</twDelInfo><twComp>dp_main/dp_main_scramble/pack_data0_in_bs_r</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X44Y93.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.108</twDelInfo><twComp>dp_main/dp_main_scramble/sc_op_count_512_r&lt;3&gt;</twComp><twBEL>dp_main/dp_main_scramble/sc_op_count_512_r_3</twBEL></twPathDel><twLogDel>0.126</twLogDel><twRouteDel>0.146</twRouteDel><twTotDel>0.272</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.666">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>46.3</twPctLog><twPctRoute>53.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="34"><twPinLimitBanner>Component Switching Limit Checks: TS_GTPCLKOUT1_DCMx1 = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCMx1&quot; 150 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="35" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.266" period="6.666" constraintValue="6.666" deviceLimit="6.400" freqLimit="156.250" physResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/RXUSRCLK21" logResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/RXUSRCLK21" locationPin="GTPA1_DUAL_X1Y0.RXUSRCLK21" clockNet="GTPCLKOUT1_DCMx1"/><twPinLimit anchorID="36" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="0.266" period="6.666" constraintValue="6.666" deviceLimit="6.400" freqLimit="156.250" physResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21" logResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21" locationPin="GTPA1_DUAL_X1Y0.TXUSRCLK21" clockNet="GTPCLKOUT1_DCMx1"/><twPinLimit anchorID="37" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="3.096" period="6.666" constraintValue="6.666" deviceLimit="3.570" freqLimit="280.112" physResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X2Y24.CLKA" clockNet="GTPCLKOUT1_DCMx1"/></twPinLimitRpt></twConst><twConst anchorID="38" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;</twConstName><twItemCnt>4368</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1196</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>7.228</twMinPer></twConstHead><twPathRptBanner iPaths="21" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB (SLICE_X1Y19.A1), 21 paths
</twPathRptBanner><twPathRpt anchorID="39"><twConstPath anchorID="40" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>29.809</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/aux_tx_req_r</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twDest><twTotPathDel>7.176</twTotPathDel><twClkSkew dest = "0.253" src = "0.270">0.017</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/aux_tx_req_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X16Y30.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X16Y30.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>dp_main/dp_main_linkup/aux_tx_req_r</twComp><twBEL>dp_main/dp_main_linkup/aux_tx_req_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B1</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.277</twDelInfo><twComp>dp_main/dp_main_linkup/aux_tx_req_r</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y19.A1</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.414</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y19.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twComp><twBEL>lut23753_4822</twBEL><twBEL>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twBEL></twPathDel><twLogDel>1.574</twLogDel><twRouteDel>5.602</twRouteDel><twTotDel>7.176</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>21.9</twPctLog><twPctRoute>78.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="41"><twConstPath anchorID="42" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.466</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_cmd_r_0</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twDest><twTotPathDel>6.531</twTotPathDel><twClkSkew dest = "0.253" src = "0.258">0.005</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_cmd_r_0</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X2Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X2Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_cmd_r&lt;3&gt;</twComp><twBEL>dp_main/aux_tx/aux_cmd_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.583</twDelInfo><twComp>dp_main/aux_tx/aux_cmd_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y19.A1</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.414</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y19.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twComp><twBEL>lut23753_4822</twBEL><twBEL>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twBEL></twPathDel><twLogDel>1.623</twLogDel><twRouteDel>4.908</twRouteDel><twTotDel>6.531</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>24.9</twPctLog><twPctRoute>75.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="43"><twConstPath anchorID="44" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>31.200</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_len8_r</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twDest><twTotPathDel>5.784</twTotPathDel><twClkSkew dest = "0.253" src = "0.271">0.018</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_len8_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X2Y18.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X2Y18.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp><twBEL>dp_main/aux_tx/aux_len8_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">0.836</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y19.A1</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.414</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y19.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twComp><twBEL>lut23753_4822</twBEL><twBEL>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB</twBEL></twPathDel><twLogDel>1.623</twLogDel><twRouteDel>4.161</twRouteDel><twTotDel>5.784</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>28.1</twPctLog><twPctRoute>71.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="21" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB (SLICE_X1Y19.D5), 21 paths
</twPathRptBanner><twPathRpt anchorID="45"><twConstPath anchorID="46" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.114</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/aux_tx_req_r</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twDest><twTotPathDel>6.871</twTotPathDel><twClkSkew dest = "0.253" src = "0.270">0.017</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/aux_tx_req_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X16Y30.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X16Y30.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>dp_main/dp_main_linkup/aux_tx_req_r</twComp><twBEL>dp_main/dp_main_linkup/aux_tx_req_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B1</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.277</twDelInfo><twComp>dp_main/dp_main_linkup/aux_tx_req_r</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y19.D5</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.109</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y19.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twComp><twBEL>lut23738_4814</twBEL><twBEL>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twBEL></twPathDel><twLogDel>1.574</twLogDel><twRouteDel>5.297</twRouteDel><twTotDel>6.871</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>22.9</twPctLog><twPctRoute>77.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="47"><twConstPath anchorID="48" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.771</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_cmd_r_0</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twDest><twTotPathDel>6.226</twTotPathDel><twClkSkew dest = "0.253" src = "0.258">0.005</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_cmd_r_0</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X2Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X2Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_cmd_r&lt;3&gt;</twComp><twBEL>dp_main/aux_tx/aux_cmd_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.583</twDelInfo><twComp>dp_main/aux_tx/aux_cmd_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y19.D5</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.109</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y19.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twComp><twBEL>lut23738_4814</twBEL><twBEL>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twBEL></twPathDel><twLogDel>1.623</twLogDel><twRouteDel>4.603</twRouteDel><twTotDel>6.226</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>26.1</twPctLog><twPctRoute>73.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="49"><twConstPath anchorID="50" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>31.505</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_len8_r</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twDest><twTotPathDel>5.479</twTotPathDel><twClkSkew dest = "0.253" src = "0.271">0.018</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_len8_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X2Y18.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X2Y18.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp><twBEL>dp_main/aux_tx/aux_len8_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">0.836</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y19.D5</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.109</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y19.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twComp><twBEL>lut23738_4814</twBEL><twBEL>dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB</twBEL></twPathDel><twLogDel>1.623</twLogDel><twRouteDel>3.856</twRouteDel><twTotDel>5.479</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>29.6</twPctLog><twPctRoute>70.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="21" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/Mmux_aux_count_w1517_FRB (SLICE_X2Y18.C2), 21 paths
</twPathRptBanner><twPathRpt anchorID="51"><twConstPath anchorID="52" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.114</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/aux_tx_req_r</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twDest><twTotPathDel>6.874</twTotPathDel><twClkSkew dest = "0.256" src = "0.270">0.014</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/aux_tx_req_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X16Y30.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X16Y30.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>dp_main/dp_main_linkup/aux_tx_req_r</twComp><twBEL>dp_main/dp_main_linkup/aux_tx_req_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B1</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">2.277</twDelInfo><twComp>dp_main/dp_main_linkup/aux_tx_req_r</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y18.C2</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.146</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y18.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp><twBEL>lut23758_4824</twBEL><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twBEL></twPathDel><twLogDel>1.540</twLogDel><twRouteDel>5.334</twRouteDel><twTotDel>6.874</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>22.4</twPctLog><twPctRoute>77.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="53"><twConstPath anchorID="54" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.771</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_cmd_r_0</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twDest><twTotPathDel>6.229</twTotPathDel><twClkSkew dest = "0.256" src = "0.258">0.002</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_cmd_r_0</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X2Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X2Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_cmd_r&lt;3&gt;</twComp><twBEL>dp_main/aux_tx/aux_cmd_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.583</twDelInfo><twComp>dp_main/aux_tx/aux_cmd_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y18.C2</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.146</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y18.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp><twBEL>lut23758_4824</twBEL><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twBEL></twPathDel><twLogDel>1.589</twLogDel><twRouteDel>4.640</twRouteDel><twTotDel>6.229</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>25.5</twPctLog><twPctRoute>74.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="55"><twConstPath anchorID="56" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>31.520</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_len8_r</twSrc><twDest BELType="FF">dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twDest><twTotPathDel>5.482</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_len8_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X2Y18.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X2Y18.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp><twBEL>dp_main/aux_tx/aux_len8_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">0.836</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>lut19263_4046</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.036</twDelInfo><twComp>lut19263_4046</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd1</twComp><twBEL>lut19264_4047</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y20.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>lut19264_4047</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y20.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp><twBEL>lut19265_4048</twBEL></twPathDel><twPathDel><twSite>SLICE_X2Y18.C2</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.146</twDelInfo><twComp>lut19265_4048</twComp></twPathDel><twPathDel><twSite>SLICE_X2Y18.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/aux_tx/aux_len8_r</twComp><twBEL>lut23758_4824</twBEL><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517_FRB</twBEL></twPathDel><twLogDel>1.589</twLogDel><twRouteDel>3.893</twRouteDel><twTotDel>5.482</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>29.0</twPctLog><twPctRoute>71.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_linkup/hpd_r_5 (SLICE_X17Y45.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="57"><twConstPath anchorID="58" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.399</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/hpd_r_4</twSrc><twDest BELType="FF">dp_main/dp_main_linkup/hpd_r_5</twDest><twTotPathDel>0.399</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/hpd_r_4</twSrc><twDest BELType='FF'>dp_main/dp_main_linkup/hpd_r_5</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X17Y45.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X17Y45.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>dp_main/dp_main_linkup/hpd_r&lt;7&gt;</twComp><twBEL>dp_main/dp_main_linkup/hpd_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y45.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.142</twDelInfo><twComp>dp_main/dp_main_linkup/hpd_r&lt;4&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X17Y45.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>dp_main/dp_main_linkup/hpd_r&lt;7&gt;</twComp><twBEL>dp_main/dp_main_linkup/hpd_r_5</twBEL></twPathDel><twLogDel>0.257</twLogDel><twRouteDel>0.142</twRouteDel><twTotDel>0.399</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>64.4</twPctLog><twPctRoute>35.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_rx/aux_rx_in_r_2 (SLICE_X23Y16.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="59"><twConstPath anchorID="60" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.408</twSlack><twSrc BELType="FF">dp_main/aux_rx/aux_rx_in_r_1</twSrc><twDest BELType="FF">dp_main/aux_rx/aux_rx_in_r_2</twDest><twTotPathDel>0.408</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/aux_rx/aux_rx_in_r_1</twSrc><twDest BELType='FF'>dp_main/aux_rx/aux_rx_in_r_2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X23Y16.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X23Y16.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>dp_main/aux_rx/aux_rx_in_r&lt;2&gt;</twComp><twBEL>dp_main/aux_rx/aux_rx_in_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y16.DX</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.151</twDelInfo><twComp>dp_main/aux_rx/aux_rx_in_r&lt;1&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X23Y16.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>dp_main/aux_rx/aux_rx_in_r&lt;2&gt;</twComp><twBEL>dp_main/aux_rx/aux_rx_in_r_2</twBEL></twPathDel><twLogDel>0.257</twLogDel><twRouteDel>0.151</twRouteDel><twTotDel>0.408</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>63.0</twPctLog><twPctRoute>37.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/aux_tx_data_r_6 (SLICE_X4Y22.A6), 1 path
</twPathRptBanner><twPathRpt anchorID="61"><twConstPath anchorID="62" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.415</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_tx_data_r_6</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_tx_data_r_6</twDest><twTotPathDel>0.415</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_tx_data_r_6</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_tx_data_r_6</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X4Y22.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27_BUFG</twSrcClk><twPathDel><twSite>SLICE_X4Y22.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;10&gt;</twComp><twBEL>dp_main/aux_tx/aux_tx_data_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y22.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.025</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;6&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X4Y22.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;10&gt;</twComp><twBEL>lut19733_4169</twBEL><twBEL>dp_main/aux_tx/aux_tx_data_r_6</twBEL></twPathDel><twLogDel>0.390</twLogDel><twRouteDel>0.025</twRouteDel><twTotDel>0.415</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27_BUFG</twDestClk><twPctLog>94.0</twPctLog><twPctRoute>6.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="63"><twPinLimitBanner>Component Switching Limit Checks: TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="64" type="MINPERIOD" name="Tbcper_I" slack="34.767" period="37.037" constraintValue="37.037" deviceLimit="2.270" freqLimit="440.529" physResource="CLK27_BUFG/I0" logResource="CLK27_BUFG/I0" locationPin="BUFGMUX_X2Y11.I0" clockNet="CLK27"/><twPinLimit anchorID="65" type="MINHIGHPULSE" name="Trpw" slack="36.557" period="37.037" constraintValue="18.518" deviceLimit="0.240" physResource="dp_main/aux_tx/aux_addr20_r/SR" logResource="dp_main/aux_tx/aux_addr20_r/SR" locationPin="SLICE_X2Y17.SR" clockNet="][15261_1"/><twPinLimit anchorID="66" type="MINHIGHPULSE" name="Trpw" slack="36.557" period="37.037" constraintValue="18.518" deviceLimit="0.240" physResource="dp_main/aux_tx/aux_len8_r/SR" logResource="dp_main/aux_tx/aux_sync_count10_r/SR" locationPin="SLICE_X2Y18.SR" clockNet="][15261_1"/></twPinLimitRpt></twConst><twConst anchorID="67" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPinLimitRpt anchorID="68"><twPinLimitBanner>Component Switching Limit Checks: TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="69" type="MINPERIOD" name="Tdcmper_CLKFX" slack="3.503" period="6.173" constraintValue="6.173" deviceLimit="2.670" freqLimit="374.532" physResource="ctm_27x162/dcm_sp_inst/CLKFX" logResource="ctm_27x162/dcm_sp_inst/CLKFX" locationPin="DCM_X0Y2.CLKFX" clockNet="PLL162"/><twPinLimit anchorID="70" type="MINLOWPULSE" name="Tdcmpw_CLKIN_25_50" slack="21.037" period="37.037" constraintValue="18.518" deviceLimit="8.000" physResource="ctm_27x162/dcm_sp_inst/CLKIN" logResource="ctm_27x162/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y2.CLKIN" clockNet="ctm_27x162/clkin1"/><twPinLimit anchorID="71" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_25_50" slack="21.037" period="37.037" constraintValue="18.518" deviceLimit="8.000" physResource="ctm_27x162/dcm_sp_inst/CLKIN" logResource="ctm_27x162/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y2.CLKIN" clockNet="ctm_27x162/clkin1"/></twPinLimitRpt></twConst><twConst anchorID="72" twConstType="PERIOD" ><twConstHead uID="5"><twConstName UCFConstName="" ScopeName="">TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk_ip * 6.25 HIGH 50%;</twConstName><twItemCnt>256</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>256</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.942</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/DDR_tx3_p (OLOGIC_X19Y3.D2), 1 path
</twPathRptBanner><twPathRpt anchorID="73"><twConstPath anchorID="74" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.129</twSlack><twSrc BELType="FF">tx_dvi/tx3_out_r_0</twSrc><twDest BELType="FF">tx_dvi/DDR_tx3_p</twDest><twTotPathDel>1.747</twTotPathDel><twClkSkew dest = "0.658" src = "0.268">-0.390</twClkSkew><twDelConst>1.600</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.217" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.114</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/tx3_out_r_0</twSrc><twDest BELType='FF'>tx_dvi/DDR_tx3_p</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X46Y1.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLKx5</twSrcClk><twPathDel><twSite>SLICE_X46Y1.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/tx3_out_r&lt;1&gt;</twComp><twBEL>tx_dvi/tx3_out_r_0</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X19Y3.D2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.607</twDelInfo><twComp>tx_dvi/tx3_out_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X19Y3.CLK1</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.664</twDelInfo><twComp>tx_dvi/tx_ck_ddr</twComp><twBEL>tx_dvi/DDR_tx3_p</twBEL></twPathDel><twLogDel>1.140</twLogDel><twRouteDel>0.607</twRouteDel><twTotDel>1.747</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="1.600">CLKx5</twDestClk><twPctLog>65.3</twPctLog><twPctRoute>34.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/DDR_tx2_p (OLOGIC_X24Y1.D2), 1 path
</twPathRptBanner><twPathRpt anchorID="75"><twConstPath anchorID="76" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.236</twSlack><twSrc BELType="FF">tx_dvi/tx2_out_r_0</twSrc><twDest BELType="FF">tx_dvi/DDR_tx2_p</twDest><twTotPathDel>1.646</twTotPathDel><twClkSkew dest = "0.570" src = "0.174">-0.396</twClkSkew><twDelConst>1.600</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.217" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.114</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/tx2_out_r_0</twSrc><twDest BELType='FF'>tx_dvi/DDR_tx2_p</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X54Y2.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLKx5</twSrcClk><twPathDel><twSite>SLICE_X54Y2.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/tx2_out_r&lt;0&gt;</twComp><twBEL>tx_dvi/tx2_out_r_0</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X24Y1.D2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.506</twDelInfo><twComp>tx_dvi/tx2_out_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X24Y1.CLK1</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.664</twDelInfo><twComp>tx_dvi/tx_ch2_ddr</twComp><twBEL>tx_dvi/DDR_tx2_p</twBEL></twPathDel><twLogDel>1.140</twLogDel><twRouteDel>0.506</twRouteDel><twTotDel>1.646</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="1.600">CLKx5</twDestClk><twPctLog>69.3</twPctLog><twPctRoute>30.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx1_r_5_BRB2 (SLICE_X55Y13.B4), 1 path
</twPathRptBanner><twPathRpt anchorID="77"><twConstPath anchorID="78" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.285</twSlack><twSrc BELType="FF">tx_dvi/ch1_enc_r_1_BRB2</twSrc><twDest BELType="FF">tx_dvi/tx1_r_5_BRB2</twDest><twTotPathDel>2.493</twTotPathDel><twClkSkew dest = "2.186" src = "2.340">0.154</twClkSkew><twDelConst>3.200</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/ch1_enc_r_1_BRB2</twSrc><twDest BELType='FF'>tx_dvi/tx1_r_5_BRB2</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X44Y12.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X44Y12.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>tx_dvi/ch1_enc_r_1_BRB4</twComp><twBEL>tx_dvi/ch1_enc_r_1_BRB2</twBEL></twPathDel><twPathDel><twSite>SLICE_X55Y13.B4</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">1.595</twDelInfo><twComp>tx_dvi/ch1_enc_r_1_BRB2</twComp></twPathDel><twPathDel><twSite>SLICE_X55Y13.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>tx_dvi/tx1_r_7_BRB2</twComp><twBEL>lut25387_5372</twBEL><twBEL>tx_dvi/tx1_r_5_BRB2</twBEL></twPathDel><twLogDel>0.898</twLogDel><twRouteDel>1.595</twRouteDel><twTotDel>2.493</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLKx5</twDestClk><twPctLog>36.0</twPctLog><twPctRoute>64.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk_ip * 6.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx2_r_9_BRB1 (SLICE_X50Y16.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="79"><twConstPath anchorID="80" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.125</twSlack><twSrc BELType="FF">tx_dvi/ch2_enc_r_9_BRB1</twSrc><twDest BELType="FF">tx_dvi/tx2_r_9_BRB1</twDest><twTotPathDel>0.448</twTotPathDel><twClkSkew dest = "1.115" src = "1.060">-0.055</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch2_enc_r_9_BRB1</twSrc><twDest BELType='FF'>tx_dvi/tx2_r_9_BRB1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X51Y16.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X51Y16.BMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twFalling">0.244</twDelInfo><twComp>tx_dvi/enc2/st1_qm_r_9_BRB1</twComp><twBEL>tx_dvi/ch2_enc_r_9_BRB1</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y16.D6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.014</twDelInfo><twComp>tx_dvi/ch2_enc_r_9_BRB1</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X50Y16.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>tx_dvi/tx2_r_9_BRB1</twComp><twBEL>lut25620_5441</twBEL><twBEL>tx_dvi/tx2_r_9_BRB1</twBEL></twPathDel><twLogDel>0.434</twLogDel><twRouteDel>0.014</twRouteDel><twTotDel>0.448</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLKx5</twDestClk><twPctLog>96.9</twPctLog><twPctRoute>3.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx0_r_8_BRB1 (SLICE_X47Y15.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="81"><twConstPath anchorID="82" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.126</twSlack><twSrc BELType="FF">tx_dvi/ch0_enc_r_8</twSrc><twDest BELType="FF">tx_dvi/tx0_r_8_BRB1</twDest><twTotPathDel>0.449</twTotPathDel><twClkSkew dest = "1.143" src = "1.088">-0.055</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch0_enc_r_8</twSrc><twDest BELType='FF'>tx_dvi/tx0_r_8_BRB1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X47Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X47Y14.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/ch0_enc_r&lt;8&gt;</twComp><twBEL>tx_dvi/ch0_enc_r_8</twBEL></twPathDel><twPathDel><twSite>SLICE_X47Y15.DX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.192</twDelInfo><twComp>tx_dvi/ch0_enc_r&lt;8&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X47Y15.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/tx0_r_8_BRB1</twComp><twBEL>tx_dvi/tx0_r_8_BRB1</twBEL></twPathDel><twLogDel>0.257</twLogDel><twRouteDel>0.192</twRouteDel><twTotDel>0.449</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLKx5</twDestClk><twPctLog>57.2</twPctLog><twPctRoute>42.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx1_r_8_BRB1 (SLICE_X51Y19.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="83"><twConstPath anchorID="84" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.220</twSlack><twSrc BELType="FF">tx_dvi/ch1_enc_r_8</twSrc><twDest BELType="FF">tx_dvi/tx1_r_8_BRB1</twDest><twTotPathDel>0.543</twTotPathDel><twClkSkew dest = "1.112" src = "1.057">-0.055</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch1_enc_r_8</twSrc><twDest BELType='FF'>tx_dvi/tx1_r_8_BRB1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X50Y19.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X50Y19.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>tx_dvi/ch1_enc_r&lt;8&gt;</twComp><twBEL>tx_dvi/ch1_enc_r_8</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y19.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.284</twDelInfo><twComp>tx_dvi/ch1_enc_r&lt;8&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X51Y19.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/tx1_r_8_BRB1</twComp><twBEL>tx_dvi/tx1_r_8_BRB1</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.284</twRouteDel><twTotDel>0.543</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLKx5</twDestClk><twPctLog>47.7</twPctLog><twPctRoute>52.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="85"><twPinLimitBanner>Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk_ip * 6.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="86" type="MINPERIOD" name="Tbcper_I" slack="0.930" period="3.200" constraintValue="3.200" deviceLimit="2.270" freqLimit="440.529" physResource="clk_wiz_v1_6_50x62x312/clkout2_buf/I0" logResource="clk_wiz_v1_6_50x62x312/clkout2_buf/I0" locationPin="BUFGMUX_X2Y3.I0" clockNet="clk_wiz_v1_6_50x62x312/clkout1"/><twPinLimit anchorID="87" type="MINPERIOD" name="Tockper" slack="1.444" period="3.200" constraintValue="3.200" deviceLimit="1.756" freqLimit="569.476" physResource="tx_dvi/tx_ch0_ddr/CLK0" logResource="tx_dvi/DDR_tx0_p/CK0" locationPin="OLOGIC_X25Y3.CLK0" clockNet="CLKx5"/><twPinLimit anchorID="88" type="MINPERIOD" name="Tockper" slack="1.444" period="3.200" constraintValue="3.200" deviceLimit="1.756" freqLimit="569.476" physResource="tx_dvi/tx_ch1_ddr/CLK0" logResource="tx_dvi/DDR_tx1_p/CK0" locationPin="OLOGIC_X26Y3.CLK0" clockNet="CLKx5"/></twPinLimitRpt></twConst><twConst anchorID="89" twConstType="PERIOD" ><twConstHead uID="6"><twConstName UCFConstName="" ScopeName="">TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk_ip * 1.25 HIGH 50%;</twConstName><twItemCnt>6721</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1189</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>7.361</twMinPer></twConstHead><twPathRptBanner iPaths="28" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc1/st1_cnt_r_1 (SLICE_X55Y11.A2), 28 paths
</twPathRptBanner><twPathRpt anchorID="90"><twConstPath anchorID="91" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>8.639</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_1</twDest><twTotPathDel>7.213</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_1</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X55Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X55Y11.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B1</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.973</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y12.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.358</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y12.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>tx_dvi/enc1/st1_qm_r_9_BRB1</twComp><twBEL>lut20739_4285</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y11.C1</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.375</twDelInfo><twComp>lut20739_4285</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y11.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;7&gt;</twComp><twBEL>lut20845_4319</twBEL></twPathDel><twPathDel><twSite>SLICE_X55Y11.A2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.956</twDelInfo><twComp>lut20845_4319</twComp></twPathDel><twPathDel><twSite>SLICE_X55Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>lut20846_4320</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_1</twBEL></twPathDel><twLogDel>1.551</twLogDel><twRouteDel>5.662</twRouteDel><twTotDel>7.213</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>21.5</twPctLog><twPctRoute>78.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="92"><twConstPath anchorID="93" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>9.132</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_1</twDest><twTotPathDel>6.720</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_1</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X55Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X55Y11.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B1</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.973</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y11.D6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.718</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y11.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;7&gt;</twComp><twBEL>lut20738_4284</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y11.C2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.517</twDelInfo><twComp>][15130_5772</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y11.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;7&gt;</twComp><twBEL>lut20845_4319</twBEL></twPathDel><twPathDel><twSite>SLICE_X55Y11.A2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.956</twDelInfo><twComp>lut20845_4319</twComp></twPathDel><twPathDel><twSite>SLICE_X55Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>lut20846_4320</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_1</twBEL></twPathDel><twLogDel>1.556</twLogDel><twRouteDel>5.164</twRouteDel><twTotDel>6.720</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>23.2</twPctLog><twPctRoute>76.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="94"><twConstPath anchorID="95" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>9.449</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_1</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_1</twDest><twTotPathDel>6.403</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_1</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_1</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X55Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X55Y11.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B2</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">1.163</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y12.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.358</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y12.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>tx_dvi/enc1/st1_qm_r_9_BRB1</twComp><twBEL>lut20739_4285</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y11.C1</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.375</twDelInfo><twComp>lut20739_4285</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y11.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;7&gt;</twComp><twBEL>lut20845_4319</twBEL></twPathDel><twPathDel><twSite>SLICE_X55Y11.A2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.956</twDelInfo><twComp>lut20845_4319</twComp></twPathDel><twPathDel><twSite>SLICE_X55Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>lut20846_4320</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_1</twBEL></twPathDel><twLogDel>1.551</twLogDel><twRouteDel>4.852</twRouteDel><twTotDel>6.403</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>24.2</twPctLog><twPctRoute>75.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="28" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB (SLICE_X56Y11.D2), 28 paths
</twPathRptBanner><twPathRpt anchorID="96"><twConstPath anchorID="97" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>9.064</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType="FF">tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twDest><twTotPathDel>6.773</twTotPathDel><twClkSkew dest = "0.249" src = "0.264">0.015</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType='FF'>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X55Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X55Y11.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B1</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.973</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y12.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.358</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y12.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>tx_dvi/enc1/st1_qm_r_9_BRB1</twComp><twBEL>lut20739_4285</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y11.C1</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.375</twDelInfo><twComp>lut20739_4285</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y11.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;7&gt;</twComp><twBEL>lut20845_4319</twBEL></twPathDel><twPathDel><twSite>SLICE_X56Y11.D2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>lut20845_4319</twComp></twPathDel><twPathDel><twSite>SLICE_X56Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.319</twDelInfo><twComp>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twComp><twBEL>lut23812_4846</twBEL><twBEL>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twBEL></twPathDel><twLogDel>1.497</twLogDel><twRouteDel>5.276</twRouteDel><twTotDel>6.773</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>22.1</twPctLog><twPctRoute>77.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="98"><twConstPath anchorID="99" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>9.557</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType="FF">tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twDest><twTotPathDel>6.280</twTotPathDel><twClkSkew dest = "0.249" src = "0.264">0.015</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType='FF'>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X55Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X55Y11.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B1</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.973</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y11.D6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.718</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y11.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;7&gt;</twComp><twBEL>lut20738_4284</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y11.C2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.517</twDelInfo><twComp>][15130_5772</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y11.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;7&gt;</twComp><twBEL>lut20845_4319</twBEL></twPathDel><twPathDel><twSite>SLICE_X56Y11.D2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>lut20845_4319</twComp></twPathDel><twPathDel><twSite>SLICE_X56Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.319</twDelInfo><twComp>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twComp><twBEL>lut23812_4846</twBEL><twBEL>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twBEL></twPathDel><twLogDel>1.502</twLogDel><twRouteDel>4.778</twRouteDel><twTotDel>6.280</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>23.9</twPctLog><twPctRoute>76.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="100"><twConstPath anchorID="101" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>9.874</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_1</twSrc><twDest BELType="FF">tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twDest><twTotPathDel>5.963</twTotPathDel><twClkSkew dest = "0.249" src = "0.264">0.015</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_1</twSrc><twDest BELType='FF'>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X55Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X55Y11.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B2</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">1.163</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y12.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.358</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y12.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>tx_dvi/enc1/st1_qm_r_9_BRB1</twComp><twBEL>lut20739_4285</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y11.C1</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.375</twDelInfo><twComp>lut20739_4285</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y11.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;7&gt;</twComp><twBEL>lut20845_4319</twBEL></twPathDel><twPathDel><twSite>SLICE_X56Y11.D2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>lut20845_4319</twComp></twPathDel><twPathDel><twSite>SLICE_X56Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.319</twDelInfo><twComp>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twComp><twBEL>lut23812_4846</twBEL><twBEL>tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut&lt;1&gt;11_FRB</twBEL></twPathDel><twLogDel>1.497</twLogDel><twRouteDel>4.466</twRouteDel><twTotDel>5.963</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>25.1</twPctLog><twPctRoute>74.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="63" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc1/st1_cnt_r_4 (SLICE_X58Y12.C5), 63 paths
</twPathRptBanner><twPathRpt anchorID="102"><twConstPath anchorID="103" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>9.169</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_4</twDest><twTotPathDel>6.670</twTotPathDel><twClkSkew dest = "0.251" src = "0.264">0.013</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_2</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_4</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X55Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X55Y11.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B1</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.973</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y12.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.358</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y12.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>tx_dvi/enc1/st1_qm_r_9_BRB1</twComp><twBEL>lut20739_4285</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y12.A4</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.185</twDelInfo><twComp>lut20739_4285</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y12.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut20792_4302</twComp><twBEL>lut20793_4303</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y12.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.627</twDelInfo><twComp>lut20793_4303</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y12.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;4&gt;</twComp><twBEL>lut20796_4306</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_4</twBEL></twPathDel><twLogDel>1.527</twLogDel><twRouteDel>5.143</twRouteDel><twTotDel>6.670</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>22.9</twPctLog><twPctRoute>77.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="104"><twConstPath anchorID="105" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>9.979</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_1</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_4</twDest><twTotPathDel>5.860</twTotPathDel><twClkSkew dest = "0.251" src = "0.264">0.013</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_1</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_4</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X55Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X55Y11.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B2</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">1.163</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y12.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.358</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y12.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>tx_dvi/enc1/st1_qm_r_9_BRB1</twComp><twBEL>lut20739_4285</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y12.A4</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.185</twDelInfo><twComp>lut20739_4285</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y12.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut20792_4302</twComp><twBEL>lut20793_4303</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y12.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.627</twDelInfo><twComp>lut20793_4303</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y12.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;4&gt;</twComp><twBEL>lut20796_4306</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_4</twBEL></twPathDel><twLogDel>1.527</twLogDel><twRouteDel>4.333</twRouteDel><twTotDel>5.860</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>26.1</twPctLog><twPctRoute>73.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="106"><twConstPath anchorID="107" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>10.315</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_cnt_r_5</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_4</twDest><twTotPathDel>5.520</twTotPathDel><twClkSkew dest = "0.251" src = "0.268">0.017</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_cnt_r_5</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_4</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X57Y13.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X57Y13.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc1/st1_cnt_r_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y14.B3</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.823</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y14.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut20776_4298</twComp><twBEL>lut20733_4279</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y12.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.358</twDelInfo><twComp>lut20733_4279</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y12.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>tx_dvi/enc1/st1_qm_r_9_BRB1</twComp><twBEL>lut20739_4285</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y12.A4</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.185</twDelInfo><twComp>lut20739_4285</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y12.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut20792_4302</twComp><twBEL>lut20793_4303</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y12.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.627</twDelInfo><twComp>lut20793_4303</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y12.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;4&gt;</twComp><twBEL>lut20796_4306</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_4</twBEL></twPathDel><twLogDel>1.527</twLogDel><twRouteDel>3.993</twRouteDel><twTotDel>5.520</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>27.7</twPctLog><twPctRoute>72.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk_ip * 1.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/ch0_in_r_9 (SLICE_X43Y8.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="108"><twConstPath anchorID="109" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.399</twSlack><twSrc BELType="FF">dispgen2/vsync_out_n_r_2</twSrc><twDest BELType="FF">tx_dvi/ch0_in_r_9</twDest><twTotPathDel>0.401</twTotPathDel><twClkSkew dest = "0.032" src = "0.030">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dispgen2/vsync_out_n_r_2</twSrc><twDest BELType='FF'>tx_dvi/ch0_in_r_9</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X42Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X42Y8.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>dispgen2/vsync_out_n_r&lt;2&gt;</twComp><twBEL>dispgen2/vsync_out_n_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y8.DX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.142</twDelInfo><twComp>dispgen2/vsync_out_n_r&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X43Y8.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/ch0_in_r&lt;9&gt;</twComp><twBEL>tx_dvi/ch0_in_r_9</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.142</twRouteDel><twTotDel>0.401</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>64.6</twPctLog><twPctRoute>35.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc0/st1_qm_r_2_BRB0 (SLICE_X48Y9.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="110"><twConstPath anchorID="111" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.401</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_2</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_2_BRB0</twDest><twTotPathDel>0.403</twTotPathDel><twClkSkew dest = "0.034" src = "0.032">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_2</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_2_BRB0</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X49Y9.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X49Y9.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;3&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y9.DX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.164</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X48Y9.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.041</twDelInfo><twComp>tx_dvi/enc0/st1_qm_r_2_BRB0</twComp><twBEL>tx_dvi/enc0/st1_qm_r_2_BRB0</twBEL></twPathDel><twLogDel>0.239</twLogDel><twRouteDel>0.164</twRouteDel><twTotDel>0.403</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>59.3</twPctLog><twPctRoute>40.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/crtc_de_r_BRB1 (SLICE_X16Y7.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="112"><twConstPath anchorID="113" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.408</twSlack><twSrc BELType="FF">crtc2/crtc_de_r_BRB1</twSrc><twDest BELType="FF">crtc2/crtc_de_r_BRB1</twDest><twTotPathDel>0.408</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>crtc2/crtc_de_r_BRB1</twSrc><twDest BELType='FF'>crtc2/crtc_de_r_BRB1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X16Y7.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X16Y7.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>crtc2/crtc_de_r_BRB1</twComp><twBEL>crtc2/crtc_de_r_BRB1</twBEL></twPathDel><twPathDel><twSite>SLICE_X16Y7.D6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.018</twDelInfo><twComp>crtc2/crtc_de_r_BRB1</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X16Y7.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>crtc2/crtc_de_r_BRB1</twComp><twBEL>lut23949_4896</twBEL><twBEL>crtc2/crtc_de_r_BRB1</twBEL></twPathDel><twLogDel>0.390</twLogDel><twRouteDel>0.018</twRouteDel><twTotDel>0.408</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>95.6</twPctLog><twPctRoute>4.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="114"><twPinLimitBanner>Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk_ip * 1.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="115" type="MINPERIOD" name="Tbcper_I" slack="13.730" period="16.000" constraintValue="16.000" deviceLimit="2.270" freqLimit="440.529" physResource="clk_wiz_v1_6_50x62x312/clkout1_buf/I0" logResource="clk_wiz_v1_6_50x62x312/clkout1_buf/I0" locationPin="BUFGMUX_X3Y6.I0" clockNet="clk_wiz_v1_6_50x62x312/clkout0"/><twPinLimit anchorID="116" type="MINPERIOD" name="Tcp" slack="14.601" period="16.000" constraintValue="16.000" deviceLimit="1.399" freqLimit="714.796" physResource="crtc2/crtc_ctrl_dl3_r_21/CLK" logResource="crtc2/Mshreg_crtc_ctrl_dl3_r_11/CLK" locationPin="SLICE_X18Y9.CLK" clockNet="CLK63"/><twPinLimit anchorID="117" type="MINPERIOD" name="Tcp" slack="14.601" period="16.000" constraintValue="16.000" deviceLimit="1.399" freqLimit="714.796" physResource="crtc2/crtc_ctrl_dl3_r_21/CLK" logResource="crtc2/Mshreg_crtc_ctrl_dl3_r_01/CLK" locationPin="SLICE_X18Y9.CLK" clockNet="CLK63"/></twPinLimitRpt></twConst><twConst anchorID="118" twConstType="PERIOD" ><twConstHead uID="7"><twConstName UCFConstName="" ScopeName="">TS_PLL162 = PERIOD TIMEGRP &quot;PLL162&quot; TS_DP_CLK1 * 6 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.200</twMinPer></twConstHead><twPinLimitRpt anchorID="119"><twPinLimitBanner>Component Switching Limit Checks: TS_PLL162 = PERIOD TIMEGRP &quot;PLL162&quot; TS_DP_CLK1 * 6 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="120" type="MINPERIOD" name="Tgtpcper_GCLK" slack="2.972" period="6.172" constraintValue="6.172" deviceLimit="3.200" freqLimit="312.500" physResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01" logResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01" locationPin="GTPA1_DUAL_X1Y0.GCLK01" clockNet="PLL162_BUFG"/><twPinLimit anchorID="121" type="MINPERIOD" name="Tbcper_I" slack="3.902" period="6.172" constraintValue="6.172" deviceLimit="2.270" freqLimit="440.529" physResource="PLL162_BUFG/I0" logResource="PLL162_BUFG/I0" locationPin="BUFGMUX_X3Y14.I0" clockNet="PLL162"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="122"><twConstRollup name="TS_xtalclk_ip" fullName="TS_xtalclk_ip = PERIOD TIMEGRP &quot;xtalclk_ip&quot; 50 MHz HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="5.000" actualRollup="18.387" errors="0" errorRollup="0" items="0" itemsRollup="6977"/><twConstRollup name="TS_clk_wiz_v1_6_50x62x312_clkout1" fullName="TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk_ip * 6.25 HIGH 50%;" type="child" depth="1" requirement="3.200" prefType="period" actual="2.942" actualRollup="N/A" errors="0" errorRollup="0" items="256" itemsRollup="0"/><twConstRollup name="TS_clk_wiz_v1_6_50x62x312_clkout0" fullName="TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk_ip * 1.25 HIGH 50%;" type="child" depth="1" requirement="16.000" prefType="period" actual="7.361" actualRollup="N/A" errors="0" errorRollup="0" items="6721" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="4" anchorID="123"><twConstRollup name="TS_DP_CLK1" fullName="TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;" type="origin" depth="0" requirement="37.037" prefType="period" actual="16.000" actualRollup="19.200" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_PLL162" fullName="TS_PLL162 = PERIOD TIMEGRP &quot;PLL162&quot; TS_DP_CLK1 * 6 HIGH 50%;" type="child" depth="1" requirement="6.173" prefType="period" actual="3.200" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="124">0</twUnmetConstCnt><twDataSheet anchorID="125" twNameLen="15"><twClk2SUList anchorID="126" twDestWidth="7"><twDest>DP_CLK0</twDest><twClk2SU><twSrc>DP_CLK0</twSrc><twRiseRise>7.228</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="127" twDestWidth="10"><twDest>xtalclk_ip</twDest><twClk2SU><twSrc>xtalclk_ip</twSrc><twRiseRise>7.361</twRiseRise><twRiseFall>1.471</twRiseFall></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="128"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>27508</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>12173</twConnCnt></twConstCov><twStats anchorID="129"><twMinPer>16.000</twMinPer><twFootnote number="1" /><twMaxFreq>62.500</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>SAT 12 NOV 11:35:36 2011 </twTimestamp></twFoot><twClientInfo anchorID="130"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 194 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
