<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated   -->
<!--     by the Xilinx ISE software.  Any direct editing or        -->
<!--     changes made to this file may result in unpredictable     -->
<!--     behavior or data corruption.  It is strongly advised that -->
<!--     users do not edit the contents of this file.              -->
<!--                                                               -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.    -->

<messages>
<msg type="info" file="ProjectMgmt" num="1574" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/PROJECT/EXP6T_DP3F/xt_crtc2.v\&quot; into library work</arg>
</msg>

</messages>

