Release 12.2 Map M.63c (nt)
Xilinx Map Application Log File for Design 'exp6t_disp_dp'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication on -global_opt speed -retiming on
-equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o
exp6t_disp_dp_map.ncd exp6t_disp_dp.ngd exp6t_disp_dp.pcf 
Target Device  : xc6slx45t
Target Package : fgg484
Target Speed   : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date    : SAT 12 NOV 11:31:58 2011

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Running global optimization...
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 1 mins 40 secs 
Total CPU  time at the beginning of Placer: 1 mins 40 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:bdd3cde7) REAL time: 1 mins 43 secs 

Phase 2.7  Design Feasibility Check
WARNING:Place:1137 - This design is not guaranteed to be routable! This design
   contains a global buffer instance, <clk_wiz_v1_6_50x62x312/clkout1_buf>,
   driving the net, <CLK63>, that is driving the following (first 30) non-clock
   source pins.
   < PIN: tx_dvi/tx_req_r_0.D; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. Please pay extra attention to the timing and routing of this path to
   ensure the design goals are met. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <clk_wiz_v1_6_50x62x312/clkout1_buf.O> allowing your design to continue. This
   constraint disables all clock placer rules related to the specified COMP.PIN.
Phase 2.7  Design Feasibility Check (Checksum:bdd3cde7) REAL time: 1 mins 43 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:bdd3cde7) REAL time: 1 mins 43 secs 

Phase 4.2  Initial Placement for Architecture Specific Features

.......
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock
   IOB / BUFGMUX site pair. The clock IOB component <DP_CLK0> is placed at site <PAD233>. The corresponding BUFG
   component <CLK27_BUFG> is placed at site <BUFGMUX_X2Y11>. There is only a select set of IOBs that can use the fast
   path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct
   it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <DP_CLK0.PAD> allowing
   your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use
   of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error
   condition be corrected in the design.
Phase 4.2  Initial Placement for Architecture Specific Features (Checksum:2e370ac8) REAL time: 1 mins 55 secs 

Phase 5.5  Local Placement Optimization
Phase 5.5  Local Placement Optimization (Checksum:2e370ac8) REAL time: 1 mins 56 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:2e370ac8) REAL time: 1 mins 56 secs 

Phase 7.30  Global Clock Region Assignment
Phase 7.30  Global Clock Region Assignment (Checksum:2e370ac8) REAL time: 1 mins 56 secs 

Phase 8.3  Local Placement Optimization
Phase 8.3  Local Placement Optimization (Checksum:2e370ac8) REAL time: 1 mins 56 secs 

Phase 9.5  Local Placement Optimization
Phase 9.5  Local Placement Optimization (Checksum:2e370ac8) REAL time: 1 mins 56 secs 

Phase 10.8  Global Placement
.................................................................................................
................................................................................................................................................................................................................
..........................................
...................
Phase 10.8  Global Placement (Checksum:740602af) REAL time: 2 mins 21 secs 

Phase 11.5  Local Placement Optimization
Phase 11.5  Local Placement Optimization (Checksum:740602af) REAL time: 2 mins 22 secs 

Phase 12.18  Placement Optimization
Phase 12.18  Placement Optimization (Checksum:5d3cc891) REAL time: 2 mins 32 secs 

Phase 13.5  Local Placement Optimization
Phase 13.5  Local Placement Optimization (Checksum:5d3cc891) REAL time: 2 mins 32 secs 

Phase 14.34  Placement Validation
Phase 14.34  Placement Validation (Checksum:ef5bb8bc) REAL time: 2 mins 33 secs 

Total REAL time to Placer completion: 2 mins 41 secs 
Total CPU  time to Placer completion: 2 mins 48 secs 
Running physical synthesis...

Physical synthesis completed.
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <TMDS_CEC_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_HPD_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_SDA_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_SCL_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_CLKOUT_IP_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<10>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<11>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<12>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<10>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<13>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<11>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<14>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<12>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<15>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<13>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<14>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<15>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DDR2_LDQS_N_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_LDQS_P_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<0>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<1>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<2>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_UDQS_N_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_UDQS_P_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<0>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<1>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<2>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<3>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<22>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<23>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<24>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<25>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<26>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<27>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<28>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<29>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<10>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<11>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<12>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<20>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<13>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<21>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<14>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<22>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<15>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<23>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<16>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<24>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<17>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<25>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<26>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<18>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<27>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<19>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<28>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<29>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGA_IP_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGB_IP_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGC_IP_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<0>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<1>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<0>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<2>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<1>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<3>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<2>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<4>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<3>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<5>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<4>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<6>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<5>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<7>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<6>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<8>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<7>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<9>_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<8>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<9>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<0>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<1>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<2>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<3>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<4>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<5>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<6>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<7>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<8>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<9>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <CFG_MISO_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DP_RSV1_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DP_RSV2_IBUF> is incomplete. The signal does not drive any load pins in the
   design.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:   94
Slice Logic Utilization:
  Number of Slice Registers:                 2,767 out of  54,576    5%
    Number used as Flip Flops:               2,767
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      2,967 out of  27,288   10%
    Number used as logic:                    2,902 out of  27,288   10%
      Number using O6 output only:           2,752
      Number using O5 output only:              99
      Number using O5 and O6:                   51
      Number used as ROM:                        0
    Number used as Memory:                      12 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:            12
        Number using O6 output only:             6
        Number using O5 output only:             0
        Number using O5 and O6:                  6
    Number used exclusively as route-thrus:     53
      Number with same-slice register load:     43
      Number with same-slice carry load:        10
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 1,154 out of   6,822   16%
  Number of LUT Flip Flop pairs used:        3,173
    Number with an unused Flip Flop:           491 out of   3,173   15%
    Number with an unused LUT:                 206 out of   3,173    6%
    Number of fully used LUT-FF pairs:       2,476 out of   3,173   78%
    Number of unique control sets:              57
    Number of slice register sites lost
      to control set restrictions:             223 out of  54,576    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       154 out of     296   52%
    Number of LOCed IOBs:                      154 out of     154  100%
    IOB Flip Flops:                              4
    IOB Master Pads:                             5
    IOB Slave Pads:                              5
    Number of bonded IPADs:                      6 out of      16   37%
    Number of bonded OPADs:                      4 out of       8   50%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         3 out of     116    2%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 2 out of      32    6%
    Number used as BUFIO2s:                      2
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       8 out of      16   50%
    Number used as BUFGs:                        8
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     1 out of       8   12%
    Number used as DCMs:                         1
    Number used as DCM_CLKGENs:                  0
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   4 out of     376    1%
    Number used as OLOGIC2s:                     4
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of GTPA1_DUALs:                         1 out of       2   50%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       4   25%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                3.45

Peak Memory Usage:  314 MB
Total REAL time to MAP completion:  2 mins 47 secs 
Total CPU time to MAP completion (all processors):   2 mins 54 secs 

Mapping completed.
See MAP report file "exp6t_disp_dp_map.mrp" for details.
