exp6t_disp_dp Project Status (11/12/2011 - 11:36:01)
Project File: | exp6t_disp_dp.xise | Parser Errors: | No Errors
Module Name: | exp6t_disp_dp | Implementation State: | Programming File Generated
Target Device: | xc6slx45t-3fgg484 | Errors: | No Errors
Product Version: | ISE 12.2 | Warnings: | 3285 Warnings (502 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 2,767 | 54,576 | 5% |
Number used as Flip Flops | 2,767 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 2,967 | 27,288 | 10% |
Number used as logic | 2,902 | 27,288 | 10% |
Number using O6 output only | 2,752 |  |  |
Number using O5 output only | 99 |  |  |
Number using O5 and O6 | 51 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 12 | 6,408 | 1% |
Number used as Dual Port RAM | 0 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 12 |  |  |
Number using O6 output only | 6 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 6 |  |  |
Number used exclusively as route-thrus | 53 |  |  |
Number with same-slice register load | 43 |  |  |
Number with same-slice carry load | 10 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 1,154 | 6,822 | 16% |
Number of LUT Flip Flop pairs used | 3,173 |  |  |
Number with an unused Flip Flop | 491 | 3,173 | 15% |
Number with an unused LUT | 206 | 3,173 | 6% |
Number of fully used LUT-FF pairs | 2,476 | 3,173 | 78% |
Number of unique control sets | 57 |  |  |
Number of slice register sites lost to control set restrictions | 223 | 54,576 | 1% |
Number of bonded IOBs | 154 | 296 | 52% |
Number of LOCed IOBs | 154 | 154 | 100% |
IOB Flip Flops | 4 |  |  |
IOB Master Pads | 5 |  |  |
IOB Slave Pads | 5 |  |  |
Number of bonded IPADs | 6 | 16 | 37% |
Number of bonded OPADs | 4 | 8 | 50% |
Number of RAMB16BWERs | 3 | 116 | 2% |
Number of RAMB8BWERs | 0 | 232 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 2 | 32 | 6% |
Number used as BUFIO2s | 2 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 8 | 16 | 50% |
Number used as BUFGs | 8 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 1 | 8 | 12% |
Number used as DCMs | 1 |  |  |
Number used as DCM_CLKGENs | 0 |  |  |
Number of ILOGIC2/ISERDES2s | 0 | 376 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 376 | 0% |
Number of OLOGIC2/OSERDES2s | 4 | 376 | 1% |
Number used as OLOGIC2s | 4 |  |  |
Number used as OSERDES2s | 0 |  |  |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 256 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 58 | 0% |
Number of GTPA1_DUALs | 1 | 2 | 50% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCIE_A1s | 0 | 1 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 1 | 4 | 25% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.45 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | “y 11 12 11:31:50 2011 | 0 | 2922 Warnings (502 new) | 230 Infos (39 new)
Translation Report | Current | “y 11 12 11:31:57 2011 | 0 | 83 Warnings (0 new) | 3 Infos (0 new)
Map Report | Current | “y 11 12 11:34:46 2011 | 0 | 94 Warnings (0 new) | 40 Infos (15 new)
Place and Route Report | Current | “y 11 12 11:35:23 2011 | 0 | 94 Warnings (0 new) | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | “y 11 12 11:35:36 2011 | 0 | 0 | 2 Infos (0 new)
Bitgen Report | Current | “y 11 12 11:35:59 2011 | 0 | 92 Warnings (0 new) | 1 Info (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
Physical Synthesis Report | Current | “y 11 12 11:34:46 2011
WebTalk Log File | Current | “y 11 12 11:36:00 2011

Date Generated: 11/12/2011 - 11:36:01