--------------------------------------------------------------------------------
Release 12.2 Trace  (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

C:\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml exp6t_disp_dp.twx exp6t_disp_dp.ncd -o exp6t_disp_dp.twr
exp6t_disp_dp.pcf

Design file:              exp6t_disp_dp.ncd
Physical constraint file: exp6t_disp_dp.pcf
Device,package,speed:     xc6slx45t,fgg484,C,-3 (PRELIMINARY 1.10 2010-06-28)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_xtalclk_ip = PERIOD TIMEGRP "xtalclk_ip" 50 MHz HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   5.000ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_xtalclk_ip = PERIOD TIMEGRP "xtalclk_ip" 50 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.249ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1
  Logical resource: clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1
  Location pin: PLL_ADV_X0Y3.CLKOUT1
  Clock network: clk_wiz_v1_6_50x62x312/clkout1
--------------------------------------------------------------------------------
Slack: 12.630ns (max period limit - period)
  Period: 40.000ns
  Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKFB)
  Physical resource: clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKFBOUT
  Logical resource: clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKFBOUT
  Location pin: PLL_ADV_X0Y3.CLKFBOUT
  Clock network: clk_wiz_v1_6_50x62x312/clkfbout
--------------------------------------------------------------------------------
Slack: 15.000ns (period - (min low pulse limit / (low pulse / period)))
  Period: 20.000ns
  Low pulse: 10.000ns
  Low pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100)
  Physical resource: clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKIN1
  Logical resource: clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y3.CLKIN2
  Clock network: clk_wiz_v1_6_50x62x312/clkin1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_GTPCLKOUT1_DCMx1 = PERIOD TIMEGRP "GTPCLKOUT1_DCMx1" 150 
MHz HIGH 50%;

 16163 paths analyzed, 6927 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   6.485ns.
--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_tbc/tbc_rd_data03_r_50 (SLICE_X43Y41.CE), 15 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.181ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/tbc_count_r_0 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_50 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.378ns (Levels of Logic = 3)
  Clock Path Skew:      -0.072ns (0.574 - 0.646)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/tbc_count_r_0 to dp_main/dp_main_tbc/tbc_rd_data03_r_50
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y65.AQ      Tcko                  0.430   dp_main/dp_main_tbc/tbc_count_r<2>
                                                       dp_main/dp_main_tbc/tbc_count_r_0
    SLICE_X40Y64.C6      net (fanout=11)       0.570   dp_main/dp_main_tbc/tbc_count_r<0>
    SLICE_X40Y64.C       Tilo                  0.235   N226
                                                       lut3241_260
    SLICE_X41Y59.A4      net (fanout=16)       0.943   lut3241_260
    SLICE_X41Y59.A       Tilo                  0.259   lut3359_2902
                                                       lut3356_288_1
    SLICE_X41Y59.C2      net (fanout=3)        0.535   lut3356_2881
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.408   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_50
    -------------------------------------------------  ---------------------------
    Total                                      6.378ns (1.591ns logic, 4.787ns route)
                                                       (24.9% logic, 75.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.270ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/fsmfake10_2 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_50 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.290ns (Levels of Logic = 2)
  Clock Path Skew:      -0.071ns (0.574 - 0.645)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/fsmfake10_2 to dp_main/dp_main_tbc/tbc_rd_data03_r_50
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y65.AQ      Tcko                  0.525   dp_main/dp_main_tbc/fsmfake10<3>
                                                       dp_main/dp_main_tbc/fsmfake10_2
    SLICE_X39Y64.C2      net (fanout=8)        0.882   dp_main/dp_main_tbc/fsmfake10<2>
    SLICE_X39Y64.C       Tilo                  0.259   dp_main/dp_main_tbc/fsmfake10<1>
                                                       lut3341_282
    SLICE_X41Y59.C1      net (fanout=10)       1.218   lut3341_282
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.408   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_50
    -------------------------------------------------  ---------------------------
    Total                                      6.290ns (1.451ns logic, 4.839ns route)
                                                       (23.1% logic, 76.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.285ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/tbc_count_r_1 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_50 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.274ns (Levels of Logic = 3)
  Clock Path Skew:      -0.072ns (0.574 - 0.646)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/tbc_count_r_1 to dp_main/dp_main_tbc/tbc_rd_data03_r_50
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y65.BQ      Tcko                  0.430   dp_main/dp_main_tbc/tbc_count_r<2>
                                                       dp_main/dp_main_tbc/tbc_count_r_1
    SLICE_X40Y64.C5      net (fanout=10)       0.466   dp_main/dp_main_tbc/tbc_count_r<1>
    SLICE_X40Y64.C       Tilo                  0.235   N226
                                                       lut3241_260
    SLICE_X41Y59.A4      net (fanout=16)       0.943   lut3241_260
    SLICE_X41Y59.A       Tilo                  0.259   lut3359_2902
                                                       lut3356_288_1
    SLICE_X41Y59.C2      net (fanout=3)        0.535   lut3356_2881
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.408   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_50
    -------------------------------------------------  ---------------------------
    Total                                      6.274ns (1.591ns logic, 4.683ns route)
                                                       (25.4% logic, 74.6% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_tbc/tbc_rd_data03_r_49 (SLICE_X43Y41.CE), 15 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.199ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/tbc_count_r_0 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_49 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.360ns (Levels of Logic = 3)
  Clock Path Skew:      -0.072ns (0.574 - 0.646)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/tbc_count_r_0 to dp_main/dp_main_tbc/tbc_rd_data03_r_49
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y65.AQ      Tcko                  0.430   dp_main/dp_main_tbc/tbc_count_r<2>
                                                       dp_main/dp_main_tbc/tbc_count_r_0
    SLICE_X40Y64.C6      net (fanout=11)       0.570   dp_main/dp_main_tbc/tbc_count_r<0>
    SLICE_X40Y64.C       Tilo                  0.235   N226
                                                       lut3241_260
    SLICE_X41Y59.A4      net (fanout=16)       0.943   lut3241_260
    SLICE_X41Y59.A       Tilo                  0.259   lut3359_2902
                                                       lut3356_288_1
    SLICE_X41Y59.C2      net (fanout=3)        0.535   lut3356_2881
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.390   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_49
    -------------------------------------------------  ---------------------------
    Total                                      6.360ns (1.573ns logic, 4.787ns route)
                                                       (24.7% logic, 75.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.288ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/fsmfake10_2 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_49 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.272ns (Levels of Logic = 2)
  Clock Path Skew:      -0.071ns (0.574 - 0.645)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/fsmfake10_2 to dp_main/dp_main_tbc/tbc_rd_data03_r_49
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y65.AQ      Tcko                  0.525   dp_main/dp_main_tbc/fsmfake10<3>
                                                       dp_main/dp_main_tbc/fsmfake10_2
    SLICE_X39Y64.C2      net (fanout=8)        0.882   dp_main/dp_main_tbc/fsmfake10<2>
    SLICE_X39Y64.C       Tilo                  0.259   dp_main/dp_main_tbc/fsmfake10<1>
                                                       lut3341_282
    SLICE_X41Y59.C1      net (fanout=10)       1.218   lut3341_282
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.390   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_49
    -------------------------------------------------  ---------------------------
    Total                                      6.272ns (1.433ns logic, 4.839ns route)
                                                       (22.8% logic, 77.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.303ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/tbc_count_r_1 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_49 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.256ns (Levels of Logic = 3)
  Clock Path Skew:      -0.072ns (0.574 - 0.646)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/tbc_count_r_1 to dp_main/dp_main_tbc/tbc_rd_data03_r_49
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y65.BQ      Tcko                  0.430   dp_main/dp_main_tbc/tbc_count_r<2>
                                                       dp_main/dp_main_tbc/tbc_count_r_1
    SLICE_X40Y64.C5      net (fanout=10)       0.466   dp_main/dp_main_tbc/tbc_count_r<1>
    SLICE_X40Y64.C       Tilo                  0.235   N226
                                                       lut3241_260
    SLICE_X41Y59.A4      net (fanout=16)       0.943   lut3241_260
    SLICE_X41Y59.A       Tilo                  0.259   lut3359_2902
                                                       lut3356_288_1
    SLICE_X41Y59.C2      net (fanout=3)        0.535   lut3356_2881
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.390   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_49
    -------------------------------------------------  ---------------------------
    Total                                      6.256ns (1.573ns logic, 4.683ns route)
                                                       (25.1% logic, 74.9% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_tbc/tbc_rd_data03_r_51 (SLICE_X43Y41.CE), 15 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.207ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/tbc_count_r_0 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_51 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.352ns (Levels of Logic = 3)
  Clock Path Skew:      -0.072ns (0.574 - 0.646)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/tbc_count_r_0 to dp_main/dp_main_tbc/tbc_rd_data03_r_51
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y65.AQ      Tcko                  0.430   dp_main/dp_main_tbc/tbc_count_r<2>
                                                       dp_main/dp_main_tbc/tbc_count_r_0
    SLICE_X40Y64.C6      net (fanout=11)       0.570   dp_main/dp_main_tbc/tbc_count_r<0>
    SLICE_X40Y64.C       Tilo                  0.235   N226
                                                       lut3241_260
    SLICE_X41Y59.A4      net (fanout=16)       0.943   lut3241_260
    SLICE_X41Y59.A       Tilo                  0.259   lut3359_2902
                                                       lut3356_288_1
    SLICE_X41Y59.C2      net (fanout=3)        0.535   lut3356_2881
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.382   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_51
    -------------------------------------------------  ---------------------------
    Total                                      6.352ns (1.565ns logic, 4.787ns route)
                                                       (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.296ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/fsmfake10_2 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_51 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.264ns (Levels of Logic = 2)
  Clock Path Skew:      -0.071ns (0.574 - 0.645)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/fsmfake10_2 to dp_main/dp_main_tbc/tbc_rd_data03_r_51
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y65.AQ      Tcko                  0.525   dp_main/dp_main_tbc/fsmfake10<3>
                                                       dp_main/dp_main_tbc/fsmfake10_2
    SLICE_X39Y64.C2      net (fanout=8)        0.882   dp_main/dp_main_tbc/fsmfake10<2>
    SLICE_X39Y64.C       Tilo                  0.259   dp_main/dp_main_tbc/fsmfake10<1>
                                                       lut3341_282
    SLICE_X41Y59.C1      net (fanout=10)       1.218   lut3341_282
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.382   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_51
    -------------------------------------------------  ---------------------------
    Total                                      6.264ns (1.425ns logic, 4.839ns route)
                                                       (22.7% logic, 77.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.311ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/tbc_count_r_1 (FF)
  Destination:          dp_main/dp_main_tbc/tbc_rd_data03_r_51 (FF)
  Requirement:          6.666ns
  Data Path Delay:      6.248ns (Levels of Logic = 3)
  Clock Path Skew:      -0.072ns (0.574 - 0.646)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/tbc_count_r_1 to dp_main/dp_main_tbc/tbc_rd_data03_r_51
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y65.BQ      Tcko                  0.430   dp_main/dp_main_tbc/tbc_count_r<2>
                                                       dp_main/dp_main_tbc/tbc_count_r_1
    SLICE_X40Y64.C5      net (fanout=10)       0.466   dp_main/dp_main_tbc/tbc_count_r<1>
    SLICE_X40Y64.C       Tilo                  0.235   N226
                                                       lut3241_260
    SLICE_X41Y59.A4      net (fanout=16)       0.943   lut3241_260
    SLICE_X41Y59.A       Tilo                  0.259   lut3359_2902
                                                       lut3356_288_1
    SLICE_X41Y59.C2      net (fanout=3)        0.535   lut3356_2881
    SLICE_X41Y59.C       Tilo                  0.259   lut3359_2902
                                                       lut3359_290_1
    SLICE_X43Y41.CE      net (fanout=8)        2.739   lut3359_2901
    SLICE_X43Y41.CLK     Tceck                 0.382   dp_main/dp_main_tbc/tbc_rd_data03_r<51>
                                                       dp_main/dp_main_tbc/tbc_rd_data03_r_51
    -------------------------------------------------  ---------------------------
    Total                                      6.248ns (1.565ns logic, 4.683ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------

Hold Paths: TS_GTPCLKOUT1_DCMx1 = PERIOD TIMEGRP "GTPCLKOUT1_DCMx1" 150 MHz HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i (GTPA1_DUAL_X1Y0.TXCHARISK10), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.198ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_scramble/sc_data0_out2_r_8 (FF)
  Destination:          xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i (HSIO)
  Requirement:          0.000ns
  Data Path Delay:      0.250ns (Levels of Logic = 0)
  Clock Path Skew:      0.052ns (0.120 - 0.068)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_scramble/sc_data0_out2_r_8 to xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i
    Location                    Delay type         Delay(ns)  Physical Resource
                                                              Logical Resource(s)
    --------------------------------------------------------  -------------------
    SLICE_X52Y116.DQ            Tcko                  0.234   dp_main/dp_main_scramble/sc_data0_out2_r<8>
                                                              dp_main/dp_main_scramble/sc_data0_out2_r_8
    GTPA1_DUAL_X1Y0.TXCHARISK10 net (fanout=1)        0.516   dp_main/dp_main_scramble/sc_data0_out2_r<8>
    GTPA1_DUAL_X1Y0.TXUSRCLK21  Tgtpckc_TXCHARISK(-Th)     0.500   xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i
                                                              xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i
    --------------------------------------------------------  ---------------------------
    Total                                             0.250ns (-0.266ns logic, 0.516ns route)
                                                              (-106.4% logic, 206.4% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y28.DIA4), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.265ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_tbc/tx_data00_in_r_4 (FF)
  Destination:          dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.270ns (Levels of Logic = 0)
  Clock Path Skew:      0.005ns (0.068 - 0.063)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_tbc/tx_data00_in_r_4 to dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y56.CQ      Tcko                  0.198   dp_main/dp_main_tbc/tx_data00_in_r<5>
                                                       dp_main/dp_main_tbc/tx_data00_in_r_4
    RAMB16_X2Y28.DIA4    net (fanout=1)        0.125   dp_main/dp_main_tbc/tx_data00_in_r<4>
    RAMB16_X2Y28.CLKA    Trckd_DIA   (-Th)     0.053   dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.270ns (0.145ns logic, 0.125ns route)
                                                       (53.7% logic, 46.3% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_scramble/sc_op_count_512_r_3 (SLICE_X44Y93.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.266ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_scramble/pack_data0_in_bs_r (FF)
  Destination:          dp_main/dp_main_scramble/sc_op_count_512_r_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.272ns (Levels of Logic = 0)
  Clock Path Skew:      0.006ns (0.044 - 0.038)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.666ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_scramble/pack_data0_in_bs_r to dp_main/dp_main_scramble/sc_op_count_512_r_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X44Y91.CQ      Tcko                  0.234   dp_main/dp_main_scramble/pack_data0_in_bs_r
                                                       dp_main/dp_main_scramble/pack_data0_in_bs_r
    SLICE_X44Y93.CE      net (fanout=5)        0.146   dp_main/dp_main_scramble/pack_data0_in_bs_r
    SLICE_X44Y93.CLK     Tckce       (-Th)     0.108   dp_main/dp_main_scramble/sc_op_count_512_r<3>
                                                       dp_main/dp_main_scramble/sc_op_count_512_r_3
    -------------------------------------------------  ---------------------------
    Total                                      0.272ns (0.126ns logic, 0.146ns route)
                                                       (46.3% logic, 53.7% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_GTPCLKOUT1_DCMx1 = PERIOD TIMEGRP "GTPCLKOUT1_DCMx1" 150 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.266ns (period - min period limit)
  Period: 6.666ns
  Min period limit: 6.400ns (156.250MHz) (Tgtpcper_RXUSRCLK)
  Physical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/RXUSRCLK21
  Logical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/RXUSRCLK21
  Location pin: GTPA1_DUAL_X1Y0.RXUSRCLK21
  Clock network: GTPCLKOUT1_DCMx1
--------------------------------------------------------------------------------
Slack: 0.266ns (period - min period limit)
  Period: 6.666ns
  Min period limit: 6.400ns (156.250MHz) (Tgtpcper_TXUSRCLK)
  Physical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21
  Logical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21
  Location pin: GTPA1_DUAL_X1Y0.TXUSRCLK21
  Clock network: GTPCLKOUT1_DCMx1
--------------------------------------------------------------------------------
Slack: 3.096ns (period - min period limit)
  Period: 6.666ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X2Y24.CLKA
  Clock network: GTPCLKOUT1_DCMx1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27 MHz HIGH 50%;

 4368 paths analyzed, 1196 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.228ns.
--------------------------------------------------------------------------------

Paths for end point dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB (SLICE_X1Y19.A1), 21 paths
--------------------------------------------------------------------------------
Slack (setup path):     29.809ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_linkup/aux_tx_req_r (FF)
  Destination:          dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      7.176ns (Levels of Logic = 4)
  Clock Path Skew:      -0.017ns (0.253 - 0.270)
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_linkup/aux_tx_req_r to dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y30.CQ      Tcko                  0.476   dp_main/dp_main_linkup/aux_tx_req_r
                                                       dp_main/dp_main_linkup/aux_tx_req_r
    SLICE_X4Y18.B1       net (fanout=8)        2.277   dp_main/dp_main_linkup/aux_tx_req_r
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X1Y19.A1       net (fanout=12)       1.414   lut19265_4048
    SLICE_X1Y19.CLK      Tas                   0.373   dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
                                                       lut23753_4822
                                                       dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB
    -------------------------------------------------  ---------------------------
    Total                                      7.176ns (1.574ns logic, 5.602ns route)
                                                       (21.9% logic, 78.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     30.466ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_cmd_r_0 (FF)
  Destination:          dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      6.531ns (Levels of Logic = 4)
  Clock Path Skew:      -0.005ns (0.253 - 0.258)
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_cmd_r_0 to dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y24.AQ       Tcko                  0.525   dp_main/aux_tx/aux_cmd_r<3>
                                                       dp_main/aux_tx/aux_cmd_r_0
    SLICE_X4Y18.B4       net (fanout=3)        1.583   dp_main/aux_tx/aux_cmd_r<0>
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X1Y19.A1       net (fanout=12)       1.414   lut19265_4048
    SLICE_X1Y19.CLK      Tas                   0.373   dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
                                                       lut23753_4822
                                                       dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB
    -------------------------------------------------  ---------------------------
    Total                                      6.531ns (1.623ns logic, 4.908ns route)
                                                       (24.9% logic, 75.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     31.200ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_len8_r (FF)
  Destination:          dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      5.784ns (Levels of Logic = 4)
  Clock Path Skew:      -0.018ns (0.253 - 0.271)
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_len8_r to dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y18.DQ       Tcko                  0.525   dp_main/aux_tx/aux_len8_r
                                                       dp_main/aux_tx/aux_len8_r
    SLICE_X4Y18.B3       net (fanout=9)        0.836   dp_main/aux_tx/aux_len8_r
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X1Y19.A1       net (fanout=12)       1.414   lut19265_4048
    SLICE_X1Y19.CLK      Tas                   0.373   dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
                                                       lut23753_4822
                                                       dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2116_FRB
    -------------------------------------------------  ---------------------------
    Total                                      5.784ns (1.623ns logic, 4.161ns route)
                                                       (28.1% logic, 71.9% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB (SLICE_X1Y19.D5), 21 paths
--------------------------------------------------------------------------------
Slack (setup path):     30.114ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_linkup/aux_tx_req_r (FF)
  Destination:          dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      6.871ns (Levels of Logic = 4)
  Clock Path Skew:      -0.017ns (0.253 - 0.270)
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_linkup/aux_tx_req_r to dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y30.CQ      Tcko                  0.476   dp_main/dp_main_linkup/aux_tx_req_r
                                                       dp_main/dp_main_linkup/aux_tx_req_r
    SLICE_X4Y18.B1       net (fanout=8)        2.277   dp_main/dp_main_linkup/aux_tx_req_r
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X1Y19.D5       net (fanout=12)       1.109   lut19265_4048
    SLICE_X1Y19.CLK      Tas                   0.373   dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
                                                       lut23738_4814
                                                       dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
    -------------------------------------------------  ---------------------------
    Total                                      6.871ns (1.574ns logic, 5.297ns route)
                                                       (22.9% logic, 77.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     30.771ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_cmd_r_0 (FF)
  Destination:          dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      6.226ns (Levels of Logic = 4)
  Clock Path Skew:      -0.005ns (0.253 - 0.258)
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_cmd_r_0 to dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y24.AQ       Tcko                  0.525   dp_main/aux_tx/aux_cmd_r<3>
                                                       dp_main/aux_tx/aux_cmd_r_0
    SLICE_X4Y18.B4       net (fanout=3)        1.583   dp_main/aux_tx/aux_cmd_r<0>
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X1Y19.D5       net (fanout=12)       1.109   lut19265_4048
    SLICE_X1Y19.CLK      Tas                   0.373   dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
                                                       lut23738_4814
                                                       dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
    -------------------------------------------------  ---------------------------
    Total                                      6.226ns (1.623ns logic, 4.603ns route)
                                                       (26.1% logic, 73.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     31.505ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_len8_r (FF)
  Destination:          dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      5.479ns (Levels of Logic = 4)
  Clock Path Skew:      -0.018ns (0.253 - 0.271)
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_len8_r to dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y18.DQ       Tcko                  0.525   dp_main/aux_tx/aux_len8_r
                                                       dp_main/aux_tx/aux_len8_r
    SLICE_X4Y18.B3       net (fanout=9)        0.836   dp_main/aux_tx/aux_len8_r
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X1Y19.D5       net (fanout=12)       1.109   lut19265_4048
    SLICE_X1Y19.CLK      Tas                   0.373   dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
                                                       lut23738_4814
                                                       dp_main/aux_tx/Mmux_GND_103_o_GND_103_o_mux_150_OUT2111_FRB
    -------------------------------------------------  ---------------------------
    Total                                      5.479ns (1.623ns logic, 3.856ns route)
                                                       (29.6% logic, 70.4% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/aux_tx/Mmux_aux_count_w1517_FRB (SLICE_X2Y18.C2), 21 paths
--------------------------------------------------------------------------------
Slack (setup path):     30.114ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_linkup/aux_tx_req_r (FF)
  Destination:          dp_main/aux_tx/Mmux_aux_count_w1517_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      6.874ns (Levels of Logic = 4)
  Clock Path Skew:      -0.014ns (0.256 - 0.270)
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_linkup/aux_tx_req_r to dp_main/aux_tx/Mmux_aux_count_w1517_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y30.CQ      Tcko                  0.476   dp_main/dp_main_linkup/aux_tx_req_r
                                                       dp_main/dp_main_linkup/aux_tx_req_r
    SLICE_X4Y18.B1       net (fanout=8)        2.277   dp_main/dp_main_linkup/aux_tx_req_r
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X2Y18.C2       net (fanout=12)       1.146   lut19265_4048
    SLICE_X2Y18.CLK      Tas                   0.339   dp_main/aux_tx/aux_len8_r
                                                       lut23758_4824
                                                       dp_main/aux_tx/Mmux_aux_count_w1517_FRB
    -------------------------------------------------  ---------------------------
    Total                                      6.874ns (1.540ns logic, 5.334ns route)
                                                       (22.4% logic, 77.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     30.771ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_cmd_r_0 (FF)
  Destination:          dp_main/aux_tx/Mmux_aux_count_w1517_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      6.229ns (Levels of Logic = 4)
  Clock Path Skew:      -0.002ns (0.256 - 0.258)
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_cmd_r_0 to dp_main/aux_tx/Mmux_aux_count_w1517_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y24.AQ       Tcko                  0.525   dp_main/aux_tx/aux_cmd_r<3>
                                                       dp_main/aux_tx/aux_cmd_r_0
    SLICE_X4Y18.B4       net (fanout=3)        1.583   dp_main/aux_tx/aux_cmd_r<0>
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X2Y18.C2       net (fanout=12)       1.146   lut19265_4048
    SLICE_X2Y18.CLK      Tas                   0.339   dp_main/aux_tx/aux_len8_r
                                                       lut23758_4824
                                                       dp_main/aux_tx/Mmux_aux_count_w1517_FRB
    -------------------------------------------------  ---------------------------
    Total                                      6.229ns (1.589ns logic, 4.640ns route)
                                                       (25.5% logic, 74.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     31.520ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_len8_r (FF)
  Destination:          dp_main/aux_tx/Mmux_aux_count_w1517_FRB (FF)
  Requirement:          37.037ns
  Data Path Delay:      5.482ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_len8_r to dp_main/aux_tx/Mmux_aux_count_w1517_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y18.DQ       Tcko                  0.525   dp_main/aux_tx/aux_len8_r
                                                       dp_main/aux_tx/aux_len8_r
    SLICE_X4Y18.B3       net (fanout=9)        0.836   dp_main/aux_tx/aux_len8_r
    SLICE_X4Y18.B        Tilo                  0.235   dp_main/aux_tx/aux_clk_one_r
                                                       lut19263_4046
    SLICE_X2Y21.C5       net (fanout=1)        1.036   lut19263_4046
    SLICE_X2Y21.C        Tilo                  0.255   dp_main/aux_tx/aux_state_r_FSM_FFd1
                                                       lut19264_4047
    SLICE_X4Y20.D5       net (fanout=1)        0.875   lut19264_4047
    SLICE_X4Y20.D        Tilo                  0.235   dp_main/aux_tx/aux_state_r_FSM_FFd4
                                                       lut19265_4048
    SLICE_X2Y18.C2       net (fanout=12)       1.146   lut19265_4048
    SLICE_X2Y18.CLK      Tas                   0.339   dp_main/aux_tx/aux_len8_r
                                                       lut23758_4824
                                                       dp_main/aux_tx/Mmux_aux_count_w1517_FRB
    -------------------------------------------------  ---------------------------
    Total                                      5.482ns (1.589ns logic, 3.893ns route)
                                                       (29.0% logic, 71.0% route)

--------------------------------------------------------------------------------

Hold Paths: TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27 MHz HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_linkup/hpd_r_5 (SLICE_X17Y45.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.399ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_linkup/hpd_r_4 (FF)
  Destination:          dp_main/dp_main_linkup/hpd_r_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.399ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_linkup/hpd_r_4 to dp_main/dp_main_linkup/hpd_r_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y45.AQ      Tcko                  0.198   dp_main/dp_main_linkup/hpd_r<7>
                                                       dp_main/dp_main_linkup/hpd_r_4
    SLICE_X17Y45.BX      net (fanout=1)        0.142   dp_main/dp_main_linkup/hpd_r<4>
    SLICE_X17Y45.CLK     Tckdi       (-Th)    -0.059   dp_main/dp_main_linkup/hpd_r<7>
                                                       dp_main/dp_main_linkup/hpd_r_5
    -------------------------------------------------  ---------------------------
    Total                                      0.399ns (0.257ns logic, 0.142ns route)
                                                       (64.4% logic, 35.6% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/aux_rx/aux_rx_in_r_2 (SLICE_X23Y16.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.408ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/aux_rx/aux_rx_in_r_1 (FF)
  Destination:          dp_main/aux_rx/aux_rx_in_r_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.408ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/aux_rx/aux_rx_in_r_1 to dp_main/aux_rx/aux_rx_in_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y16.CQ      Tcko                  0.198   dp_main/aux_rx/aux_rx_in_r<2>
                                                       dp_main/aux_rx/aux_rx_in_r_1
    SLICE_X23Y16.DX      net (fanout=3)        0.151   dp_main/aux_rx/aux_rx_in_r<1>
    SLICE_X23Y16.CLK     Tckdi       (-Th)    -0.059   dp_main/aux_rx/aux_rx_in_r<2>
                                                       dp_main/aux_rx/aux_rx_in_r_2
    -------------------------------------------------  ---------------------------
    Total                                      0.408ns (0.257ns logic, 0.151ns route)
                                                       (63.0% logic, 37.0% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/aux_tx/aux_tx_data_r_6 (SLICE_X4Y22.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.415ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/aux_tx/aux_tx_data_r_6 (FF)
  Destination:          dp_main/aux_tx/aux_tx_data_r_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.415ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK27_BUFG rising at 0.000ns
  Destination Clock:    CLK27_BUFG rising at 37.037ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/aux_tx/aux_tx_data_r_6 to dp_main/aux_tx/aux_tx_data_r_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X4Y22.AQ       Tcko                  0.200   dp_main/aux_tx/aux_tx_data_r<10>
                                                       dp_main/aux_tx/aux_tx_data_r_6
    SLICE_X4Y22.A6       net (fanout=2)        0.025   dp_main/aux_tx/aux_tx_data_r<6>
    SLICE_X4Y22.CLK      Tah         (-Th)    -0.190   dp_main/aux_tx/aux_tx_data_r<10>
                                                       lut19733_4169
                                                       dp_main/aux_tx/aux_tx_data_r_6
    -------------------------------------------------  ---------------------------
    Total                                      0.415ns (0.390ns logic, 0.025ns route)
                                                       (94.0% logic, 6.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 34.767ns (period - min period limit)
  Period: 37.037ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: CLK27_BUFG/I0
  Logical resource: CLK27_BUFG/I0
  Location pin: BUFGMUX_X2Y11.I0
  Clock network: CLK27
--------------------------------------------------------------------------------
Slack: 36.557ns (period - (min high pulse limit / (high pulse / period)))
  Period: 37.037ns
  High pulse: 18.518ns
  High pulse limit: 0.240ns (Trpw)
  Physical resource: dp_main/aux_tx/aux_addr20_r/SR
  Logical resource: dp_main/aux_tx/aux_addr20_r/SR
  Location pin: SLICE_X2Y17.SR
  Clock network: ][15261_1
--------------------------------------------------------------------------------
Slack: 36.557ns (period - (min high pulse limit / (high pulse / period)))
  Period: 37.037ns
  High pulse: 18.518ns
  High pulse limit: 0.240ns (Trpw)
  Physical resource: dp_main/aux_tx/aux_len8_r/SR
  Logical resource: dp_main/aux_tx/aux_sync_count10_r/SR
  Location pin: SLICE_X2Y18.SR
  Clock network: ][15261_1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_DP_CLK1 = PERIOD TIMEGRP "DP_CLK1" 27 MHz HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is  16.000ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_DP_CLK1 = PERIOD TIMEGRP "DP_CLK1" 27 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 3.503ns (period - min period limit)
  Period: 6.173ns
  Min period limit: 2.670ns (374.532MHz) (Tdcmper_CLKFX)
  Physical resource: ctm_27x162/dcm_sp_inst/CLKFX
  Logical resource: ctm_27x162/dcm_sp_inst/CLKFX
  Location pin: DCM_X0Y2.CLKFX
  Clock network: PLL162
--------------------------------------------------------------------------------
Slack: 21.037ns (period - (min low pulse limit / (low pulse / period)))
  Period: 37.037ns
  Low pulse: 18.518ns
  Low pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50)
  Physical resource: ctm_27x162/dcm_sp_inst/CLKIN
  Logical resource: ctm_27x162/dcm_sp_inst/CLKIN
  Location pin: DCM_X0Y2.CLKIN
  Clock network: ctm_27x162/clkin1
--------------------------------------------------------------------------------
Slack: 21.037ns (period - (min high pulse limit / (high pulse / period)))
  Period: 37.037ns
  High pulse: 18.518ns
  High pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50)
  Physical resource: ctm_27x162/dcm_sp_inst/CLKIN
  Logical resource: ctm_27x162/dcm_sp_inst/CLKIN
  Location pin: DCM_X0Y2.CLKIN
  Clock network: ctm_27x162/clkin1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP         
"clk_wiz_v1_6_50x62x312_clkout1" TS_xtalclk_ip * 6.25 HIGH 50%;

 256 paths analyzed, 256 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   2.942ns.
--------------------------------------------------------------------------------

Paths for end point tx_dvi/DDR_tx3_p (OLOGIC_X19Y3.D2), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.129ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/tx3_out_r_0 (FF)
  Destination:          tx_dvi/DDR_tx3_p (FF)
  Requirement:          1.600ns
  Data Path Delay:      1.747ns (Levels of Logic = 0)
  Clock Path Skew:      0.390ns (0.658 - 0.268)
  Source Clock:         CLKx5 rising at 0.000ns
  Destination Clock:    CLKx5 falling at 1.600ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/tx3_out_r_0 to tx_dvi/DDR_tx3_p
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y1.AQ       Tcko                  0.476   tx_dvi/tx3_out_r<1>
                                                       tx_dvi/tx3_out_r_0
    OLOGIC_X19Y3.D2      net (fanout=1)        0.607   tx_dvi/tx3_out_r<0>
    OLOGIC_X19Y3.CLK1    Todck                 0.664   tx_dvi/tx_ck_ddr
                                                       tx_dvi/DDR_tx3_p
    -------------------------------------------------  ---------------------------
    Total                                      1.747ns (1.140ns logic, 0.607ns route)
                                                       (65.3% logic, 34.7% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/DDR_tx2_p (OLOGIC_X24Y1.D2), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.236ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/tx2_out_r_0 (FF)
  Destination:          tx_dvi/DDR_tx2_p (FF)
  Requirement:          1.600ns
  Data Path Delay:      1.646ns (Levels of Logic = 0)
  Clock Path Skew:      0.396ns (0.570 - 0.174)
  Source Clock:         CLKx5 rising at 0.000ns
  Destination Clock:    CLKx5 falling at 1.600ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/tx2_out_r_0 to tx_dvi/DDR_tx2_p
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X54Y2.AQ       Tcko                  0.476   tx_dvi/tx2_out_r<0>
                                                       tx_dvi/tx2_out_r_0
    OLOGIC_X24Y1.D2      net (fanout=1)        0.506   tx_dvi/tx2_out_r<0>
    OLOGIC_X24Y1.CLK1    Todck                 0.664   tx_dvi/tx_ch2_ddr
                                                       tx_dvi/DDR_tx2_p
    -------------------------------------------------  ---------------------------
    Total                                      1.646ns (1.140ns logic, 0.506ns route)
                                                       (69.3% logic, 30.7% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx1_r_5_BRB2 (SLICE_X55Y13.B4), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.285ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/ch1_enc_r_1_BRB2 (FF)
  Destination:          tx_dvi/tx1_r_5_BRB2 (FF)
  Requirement:          3.200ns
  Data Path Delay:      2.493ns (Levels of Logic = 1)
  Clock Path Skew:      -0.154ns (2.186 - 2.340)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLKx5 rising at 3.200ns
  Clock Uncertainty:    0.268ns

  Clock Uncertainty:          0.268ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.120ns

  Maximum Data Path at Slow Process Corner: tx_dvi/ch1_enc_r_1_BRB2 to tx_dvi/tx1_r_5_BRB2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X44Y12.BQ      Tcko                  0.525   tx_dvi/ch1_enc_r_1_BRB4
                                                       tx_dvi/ch1_enc_r_1_BRB2
    SLICE_X55Y13.B4      net (fanout=8)        1.595   tx_dvi/ch1_enc_r_1_BRB2
    SLICE_X55Y13.CLK     Tas                   0.373   tx_dvi/tx1_r_7_BRB2
                                                       lut25387_5372
                                                       tx_dvi/tx1_r_5_BRB2
    -------------------------------------------------  ---------------------------
    Total                                      2.493ns (0.898ns logic, 1.595ns route)
                                                       (36.0% logic, 64.0% route)

--------------------------------------------------------------------------------

Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        "clk_wiz_v1_6_50x62x312_clkout1" TS_xtalclk_ip * 6.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx2_r_9_BRB1 (SLICE_X50Y16.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.125ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/ch2_enc_r_9_BRB1 (FF)
  Destination:          tx_dvi/tx2_r_9_BRB1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.448ns (Levels of Logic = 1)
  Clock Path Skew:      0.055ns (1.115 - 1.060)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLKx5 rising at 3.200ns
  Clock Uncertainty:    0.268ns

  Clock Uncertainty:          0.268ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: tx_dvi/ch2_enc_r_9_BRB1 to tx_dvi/tx2_r_9_BRB1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X51Y16.BMUX    Tshcko                0.244   tx_dvi/enc2/st1_qm_r_9_BRB1
                                                       tx_dvi/ch2_enc_r_9_BRB1
    SLICE_X50Y16.D6      net (fanout=1)        0.014   tx_dvi/ch2_enc_r_9_BRB1
    SLICE_X50Y16.CLK     Tah         (-Th)    -0.190   tx_dvi/tx2_r_9_BRB1
                                                       lut25620_5441
                                                       tx_dvi/tx2_r_9_BRB1
    -------------------------------------------------  ---------------------------
    Total                                      0.448ns (0.434ns logic, 0.014ns route)
                                                       (96.9% logic, 3.1% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx0_r_8_BRB1 (SLICE_X47Y15.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.126ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/ch0_enc_r_8 (FF)
  Destination:          tx_dvi/tx0_r_8_BRB1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.449ns (Levels of Logic = 0)
  Clock Path Skew:      0.055ns (1.143 - 1.088)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLKx5 rising at 3.200ns
  Clock Uncertainty:    0.268ns

  Clock Uncertainty:          0.268ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: tx_dvi/ch0_enc_r_8 to tx_dvi/tx0_r_8_BRB1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X47Y14.DQ      Tcko                  0.198   tx_dvi/ch0_enc_r<8>
                                                       tx_dvi/ch0_enc_r_8
    SLICE_X47Y15.DX      net (fanout=1)        0.192   tx_dvi/ch0_enc_r<8>
    SLICE_X47Y15.CLK     Tckdi       (-Th)    -0.059   tx_dvi/tx0_r_8_BRB1
                                                       tx_dvi/tx0_r_8_BRB1
    -------------------------------------------------  ---------------------------
    Total                                      0.449ns (0.257ns logic, 0.192ns route)
                                                       (57.2% logic, 42.8% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx1_r_8_BRB1 (SLICE_X51Y19.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.220ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/ch1_enc_r_8 (FF)
  Destination:          tx_dvi/tx1_r_8_BRB1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.543ns (Levels of Logic = 0)
  Clock Path Skew:      0.055ns (1.112 - 1.057)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLKx5 rising at 3.200ns
  Clock Uncertainty:    0.268ns

  Clock Uncertainty:          0.268ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: tx_dvi/ch1_enc_r_8 to tx_dvi/tx1_r_8_BRB1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y19.AQ      Tcko                  0.200   tx_dvi/ch1_enc_r<8>
                                                       tx_dvi/ch1_enc_r_8
    SLICE_X51Y19.AX      net (fanout=1)        0.284   tx_dvi/ch1_enc_r<8>
    SLICE_X51Y19.CLK     Tckdi       (-Th)    -0.059   tx_dvi/tx1_r_8_BRB1
                                                       tx_dvi/tx1_r_8_BRB1
    -------------------------------------------------  ---------------------------
    Total                                      0.543ns (0.259ns logic, 0.284ns route)
                                                       (47.7% logic, 52.3% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        "clk_wiz_v1_6_50x62x312_clkout1" TS_xtalclk_ip * 6.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.930ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: clk_wiz_v1_6_50x62x312/clkout2_buf/I0
  Logical resource: clk_wiz_v1_6_50x62x312/clkout2_buf/I0
  Location pin: BUFGMUX_X2Y3.I0
  Clock network: clk_wiz_v1_6_50x62x312/clkout1
--------------------------------------------------------------------------------
Slack: 1.444ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 1.756ns (569.476MHz) (Tockper)
  Physical resource: tx_dvi/tx_ch0_ddr/CLK0
  Logical resource: tx_dvi/DDR_tx0_p/CK0
  Location pin: OLOGIC_X25Y3.CLK0
  Clock network: CLKx5
--------------------------------------------------------------------------------
Slack: 1.444ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 1.756ns (569.476MHz) (Tockper)
  Physical resource: tx_dvi/tx_ch1_ddr/CLK0
  Logical resource: tx_dvi/DDR_tx1_p/CK0
  Location pin: OLOGIC_X26Y3.CLK0
  Clock network: CLKx5
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP         
"clk_wiz_v1_6_50x62x312_clkout0" TS_xtalclk_ip * 1.25 HIGH 50%;

 6721 paths analyzed, 1189 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.361ns.
--------------------------------------------------------------------------------

Paths for end point tx_dvi/enc1/st1_cnt_r_1 (SLICE_X55Y11.A2), 28 paths
--------------------------------------------------------------------------------
Slack (setup path):     8.639ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_2 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_1 (FF)
  Requirement:          16.000ns
  Data Path Delay:      7.213ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_2 to tx_dvi/enc1/st1_cnt_r_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y11.CQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/st1_cnt_r_2
    SLICE_X58Y14.B1      net (fanout=12)       1.973   tx_dvi/enc1/st1_cnt_r<2>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X52Y12.B1      net (fanout=4)        1.358   lut20733_4279
    SLICE_X52Y12.B       Tilo                  0.254   tx_dvi/enc1/st1_qm_r_9_BRB1
                                                       lut20739_4285
    SLICE_X57Y11.C1      net (fanout=9)        1.375   lut20739_4285
    SLICE_X57Y11.C       Tilo                  0.259   tx_dvi/enc1/st1_cnt_r<7>
                                                       lut20845_4319
    SLICE_X55Y11.A2      net (fanout=2)        0.956   lut20845_4319
    SLICE_X55Y11.CLK     Tas                   0.373   tx_dvi/enc1/st1_cnt_r<2>
                                                       lut20846_4320
                                                       tx_dvi/enc1/st1_cnt_r_1
    -------------------------------------------------  ---------------------------
    Total                                      7.213ns (1.551ns logic, 5.662ns route)
                                                       (21.5% logic, 78.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     9.132ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_2 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_1 (FF)
  Requirement:          16.000ns
  Data Path Delay:      6.720ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_2 to tx_dvi/enc1/st1_cnt_r_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y11.CQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/st1_cnt_r_2
    SLICE_X58Y14.B1      net (fanout=12)       1.973   tx_dvi/enc1/st1_cnt_r<2>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X57Y11.D6      net (fanout=4)        0.718   lut20733_4279
    SLICE_X57Y11.D       Tilo                  0.259   tx_dvi/enc1/st1_cnt_r<7>
                                                       lut20738_4284
    SLICE_X57Y11.C2      net (fanout=9)        1.517   ][15130_5772
    SLICE_X57Y11.C       Tilo                  0.259   tx_dvi/enc1/st1_cnt_r<7>
                                                       lut20845_4319
    SLICE_X55Y11.A2      net (fanout=2)        0.956   lut20845_4319
    SLICE_X55Y11.CLK     Tas                   0.373   tx_dvi/enc1/st1_cnt_r<2>
                                                       lut20846_4320
                                                       tx_dvi/enc1/st1_cnt_r_1
    -------------------------------------------------  ---------------------------
    Total                                      6.720ns (1.556ns logic, 5.164ns route)
                                                       (23.2% logic, 76.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     9.449ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_1 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_1 (FF)
  Requirement:          16.000ns
  Data Path Delay:      6.403ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_1 to tx_dvi/enc1/st1_cnt_r_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y11.AQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/st1_cnt_r_1
    SLICE_X58Y14.B2      net (fanout=13)       1.163   tx_dvi/enc1/st1_cnt_r<1>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X52Y12.B1      net (fanout=4)        1.358   lut20733_4279
    SLICE_X52Y12.B       Tilo                  0.254   tx_dvi/enc1/st1_qm_r_9_BRB1
                                                       lut20739_4285
    SLICE_X57Y11.C1      net (fanout=9)        1.375   lut20739_4285
    SLICE_X57Y11.C       Tilo                  0.259   tx_dvi/enc1/st1_cnt_r<7>
                                                       lut20845_4319
    SLICE_X55Y11.A2      net (fanout=2)        0.956   lut20845_4319
    SLICE_X55Y11.CLK     Tas                   0.373   tx_dvi/enc1/st1_cnt_r<2>
                                                       lut20846_4320
                                                       tx_dvi/enc1/st1_cnt_r_1
    -------------------------------------------------  ---------------------------
    Total                                      6.403ns (1.551ns logic, 4.852ns route)
                                                       (24.2% logic, 75.8% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB (SLICE_X56Y11.D2), 28 paths
--------------------------------------------------------------------------------
Slack (setup path):     9.064ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_2 (FF)
  Destination:          tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB (FF)
  Requirement:          16.000ns
  Data Path Delay:      6.773ns (Levels of Logic = 4)
  Clock Path Skew:      -0.015ns (0.249 - 0.264)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_2 to tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y11.CQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/st1_cnt_r_2
    SLICE_X58Y14.B1      net (fanout=12)       1.973   tx_dvi/enc1/st1_cnt_r<2>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X52Y12.B1      net (fanout=4)        1.358   lut20733_4279
    SLICE_X52Y12.B       Tilo                  0.254   tx_dvi/enc1/st1_qm_r_9_BRB1
                                                       lut20739_4285
    SLICE_X57Y11.C1      net (fanout=9)        1.375   lut20739_4285
    SLICE_X57Y11.C       Tilo                  0.259   tx_dvi/enc1/st1_cnt_r<7>
                                                       lut20845_4319
    SLICE_X56Y11.D2      net (fanout=2)        0.570   lut20845_4319
    SLICE_X56Y11.CLK     Tas                   0.319   tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
                                                       lut23812_4846
                                                       tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
    -------------------------------------------------  ---------------------------
    Total                                      6.773ns (1.497ns logic, 5.276ns route)
                                                       (22.1% logic, 77.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     9.557ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_2 (FF)
  Destination:          tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB (FF)
  Requirement:          16.000ns
  Data Path Delay:      6.280ns (Levels of Logic = 4)
  Clock Path Skew:      -0.015ns (0.249 - 0.264)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_2 to tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y11.CQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/st1_cnt_r_2
    SLICE_X58Y14.B1      net (fanout=12)       1.973   tx_dvi/enc1/st1_cnt_r<2>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X57Y11.D6      net (fanout=4)        0.718   lut20733_4279
    SLICE_X57Y11.D       Tilo                  0.259   tx_dvi/enc1/st1_cnt_r<7>
                                                       lut20738_4284
    SLICE_X57Y11.C2      net (fanout=9)        1.517   ][15130_5772
    SLICE_X57Y11.C       Tilo                  0.259   tx_dvi/enc1/st1_cnt_r<7>
                                                       lut20845_4319
    SLICE_X56Y11.D2      net (fanout=2)        0.570   lut20845_4319
    SLICE_X56Y11.CLK     Tas                   0.319   tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
                                                       lut23812_4846
                                                       tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
    -------------------------------------------------  ---------------------------
    Total                                      6.280ns (1.502ns logic, 4.778ns route)
                                                       (23.9% logic, 76.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     9.874ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_1 (FF)
  Destination:          tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB (FF)
  Requirement:          16.000ns
  Data Path Delay:      5.963ns (Levels of Logic = 4)
  Clock Path Skew:      -0.015ns (0.249 - 0.264)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_1 to tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y11.AQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/st1_cnt_r_1
    SLICE_X58Y14.B2      net (fanout=13)       1.163   tx_dvi/enc1/st1_cnt_r<1>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X52Y12.B1      net (fanout=4)        1.358   lut20733_4279
    SLICE_X52Y12.B       Tilo                  0.254   tx_dvi/enc1/st1_qm_r_9_BRB1
                                                       lut20739_4285
    SLICE_X57Y11.C1      net (fanout=9)        1.375   lut20739_4285
    SLICE_X57Y11.C       Tilo                  0.259   tx_dvi/enc1/st1_cnt_r<7>
                                                       lut20845_4319
    SLICE_X56Y11.D2      net (fanout=2)        0.570   lut20845_4319
    SLICE_X56Y11.CLK     Tas                   0.319   tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
                                                       lut23812_4846
                                                       tx_dvi/enc1/Madd_st1_cnt_r[7]_GND_87_o_add_199_OUT_lut<1>11_FRB
    -------------------------------------------------  ---------------------------
    Total                                      5.963ns (1.497ns logic, 4.466ns route)
                                                       (25.1% logic, 74.9% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/enc1/st1_cnt_r_4 (SLICE_X58Y12.C5), 63 paths
--------------------------------------------------------------------------------
Slack (setup path):     9.169ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_2 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_4 (FF)
  Requirement:          16.000ns
  Data Path Delay:      6.670ns (Levels of Logic = 4)
  Clock Path Skew:      -0.013ns (0.251 - 0.264)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_2 to tx_dvi/enc1/st1_cnt_r_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y11.CQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/st1_cnt_r_2
    SLICE_X58Y14.B1      net (fanout=12)       1.973   tx_dvi/enc1/st1_cnt_r<2>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X52Y12.B1      net (fanout=4)        1.358   lut20733_4279
    SLICE_X52Y12.B       Tilo                  0.254   tx_dvi/enc1/st1_qm_r_9_BRB1
                                                       lut20739_4285
    SLICE_X57Y12.A4      net (fanout=9)        1.185   lut20739_4285
    SLICE_X57Y12.A       Tilo                  0.259   lut20792_4302
                                                       lut20793_4303
    SLICE_X58Y12.C5      net (fanout=1)        0.627   lut20793_4303
    SLICE_X58Y12.CLK     Tas                   0.349   tx_dvi/enc1/st1_cnt_r<4>
                                                       lut20796_4306
                                                       tx_dvi/enc1/st1_cnt_r_4
    -------------------------------------------------  ---------------------------
    Total                                      6.670ns (1.527ns logic, 5.143ns route)
                                                       (22.9% logic, 77.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     9.979ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_1 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_4 (FF)
  Requirement:          16.000ns
  Data Path Delay:      5.860ns (Levels of Logic = 4)
  Clock Path Skew:      -0.013ns (0.251 - 0.264)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_1 to tx_dvi/enc1/st1_cnt_r_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y11.AQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/st1_cnt_r_1
    SLICE_X58Y14.B2      net (fanout=13)       1.163   tx_dvi/enc1/st1_cnt_r<1>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X52Y12.B1      net (fanout=4)        1.358   lut20733_4279
    SLICE_X52Y12.B       Tilo                  0.254   tx_dvi/enc1/st1_qm_r_9_BRB1
                                                       lut20739_4285
    SLICE_X57Y12.A4      net (fanout=9)        1.185   lut20739_4285
    SLICE_X57Y12.A       Tilo                  0.259   lut20792_4302
                                                       lut20793_4303
    SLICE_X58Y12.C5      net (fanout=1)        0.627   lut20793_4303
    SLICE_X58Y12.CLK     Tas                   0.349   tx_dvi/enc1/st1_cnt_r<4>
                                                       lut20796_4306
                                                       tx_dvi/enc1/st1_cnt_r_4
    -------------------------------------------------  ---------------------------
    Total                                      5.860ns (1.527ns logic, 4.333ns route)
                                                       (26.1% logic, 73.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     10.315ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st1_cnt_r_5 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_4 (FF)
  Requirement:          16.000ns
  Data Path Delay:      5.520ns (Levels of Logic = 4)
  Clock Path Skew:      -0.017ns (0.251 - 0.268)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st1_cnt_r_5 to tx_dvi/enc1/st1_cnt_r_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X57Y13.AQ      Tcko                  0.430   tx_dvi/enc1/st1_cnt_r<6>
                                                       tx_dvi/enc1/st1_cnt_r_5
    SLICE_X58Y14.B3      net (fanout=13)       0.823   tx_dvi/enc1/st1_cnt_r<5>
    SLICE_X58Y14.B       Tilo                  0.235   lut20776_4298
                                                       lut20733_4279
    SLICE_X52Y12.B1      net (fanout=4)        1.358   lut20733_4279
    SLICE_X52Y12.B       Tilo                  0.254   tx_dvi/enc1/st1_qm_r_9_BRB1
                                                       lut20739_4285
    SLICE_X57Y12.A4      net (fanout=9)        1.185   lut20739_4285
    SLICE_X57Y12.A       Tilo                  0.259   lut20792_4302
                                                       lut20793_4303
    SLICE_X58Y12.C5      net (fanout=1)        0.627   lut20793_4303
    SLICE_X58Y12.CLK     Tas                   0.349   tx_dvi/enc1/st1_cnt_r<4>
                                                       lut20796_4306
                                                       tx_dvi/enc1/st1_cnt_r_4
    -------------------------------------------------  ---------------------------
    Total                                      5.520ns (1.527ns logic, 3.993ns route)
                                                       (27.7% logic, 72.3% route)

--------------------------------------------------------------------------------

Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        "clk_wiz_v1_6_50x62x312_clkout0" TS_xtalclk_ip * 1.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point tx_dvi/ch0_in_r_9 (SLICE_X43Y8.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.399ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dispgen2/vsync_out_n_r_2 (FF)
  Destination:          tx_dvi/ch0_in_r_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.401ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.032 - 0.030)
  Source Clock:         CLK63 rising at 16.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dispgen2/vsync_out_n_r_2 to tx_dvi/ch0_in_r_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X42Y8.CQ       Tcko                  0.200   dispgen2/vsync_out_n_r<2>
                                                       dispgen2/vsync_out_n_r_2
    SLICE_X43Y8.DX       net (fanout=1)        0.142   dispgen2/vsync_out_n_r<2>
    SLICE_X43Y8.CLK      Tckdi       (-Th)    -0.059   tx_dvi/ch0_in_r<9>
                                                       tx_dvi/ch0_in_r_9
    -------------------------------------------------  ---------------------------
    Total                                      0.401ns (0.259ns logic, 0.142ns route)
                                                       (64.6% logic, 35.4% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/enc0/st1_qm_r_2_BRB0 (SLICE_X48Y9.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.401ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/enc0/st0_qm_r_2 (FF)
  Destination:          tx_dvi/enc0/st1_qm_r_2_BRB0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.403ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.034 - 0.032)
  Source Clock:         CLK63 rising at 16.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: tx_dvi/enc0/st0_qm_r_2 to tx_dvi/enc0/st1_qm_r_2_BRB0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X49Y9.CQ       Tcko                  0.198   tx_dvi/enc0/st0_qm_r<3>
                                                       tx_dvi/enc0/st0_qm_r_2
    SLICE_X48Y9.DX       net (fanout=1)        0.164   tx_dvi/enc0/st0_qm_r<2>
    SLICE_X48Y9.CLK      Tckdi       (-Th)    -0.041   tx_dvi/enc0/st1_qm_r_2_BRB0
                                                       tx_dvi/enc0/st1_qm_r_2_BRB0
    -------------------------------------------------  ---------------------------
    Total                                      0.403ns (0.239ns logic, 0.164ns route)
                                                       (59.3% logic, 40.7% route)

--------------------------------------------------------------------------------

Paths for end point crtc2/crtc_de_r_BRB1 (SLICE_X16Y7.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.408ns (requirement - (clock path skew + uncertainty - data path))
  Source:               crtc2/crtc_de_r_BRB1 (FF)
  Destination:          crtc2/crtc_de_r_BRB1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.408ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK63 rising at 16.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: crtc2/crtc_de_r_BRB1 to crtc2/crtc_de_r_BRB1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y7.DQ       Tcko                  0.200   crtc2/crtc_de_r_BRB1
                                                       crtc2/crtc_de_r_BRB1
    SLICE_X16Y7.D6       net (fanout=1)        0.018   crtc2/crtc_de_r_BRB1
    SLICE_X16Y7.CLK      Tah         (-Th)    -0.190   crtc2/crtc_de_r_BRB1
                                                       lut23949_4896
                                                       crtc2/crtc_de_r_BRB1
    -------------------------------------------------  ---------------------------
    Total                                      0.408ns (0.390ns logic, 0.018ns route)
                                                       (95.6% logic, 4.4% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        "clk_wiz_v1_6_50x62x312_clkout0" TS_xtalclk_ip * 1.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 13.730ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: clk_wiz_v1_6_50x62x312/clkout1_buf/I0
  Logical resource: clk_wiz_v1_6_50x62x312/clkout1_buf/I0
  Location pin: BUFGMUX_X3Y6.I0
  Clock network: clk_wiz_v1_6_50x62x312/clkout0
--------------------------------------------------------------------------------
Slack: 14.601ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: crtc2/crtc_ctrl_dl3_r_21/CLK
  Logical resource: crtc2/Mshreg_crtc_ctrl_dl3_r_11/CLK
  Location pin: SLICE_X18Y9.CLK
  Clock network: CLK63
--------------------------------------------------------------------------------
Slack: 14.601ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: crtc2/crtc_ctrl_dl3_r_21/CLK
  Logical resource: crtc2/Mshreg_crtc_ctrl_dl3_r_01/CLK
  Location pin: SLICE_X18Y9.CLK
  Clock network: CLK63
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_PLL162 = PERIOD TIMEGRP "PLL162" TS_DP_CLK1 * 6 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   3.200ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_PLL162 = PERIOD TIMEGRP "PLL162" TS_DP_CLK1 * 6 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.972ns (period - min period limit)
  Period: 6.172ns
  Min period limit: 3.200ns (312.500MHz) (Tgtpcper_GCLK)
  Physical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01
  Logical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01
  Location pin: GTPA1_DUAL_X1Y0.GCLK01
  Clock network: PLL162_BUFG
--------------------------------------------------------------------------------
Slack: 3.902ns (period - min period limit)
  Period: 6.172ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: PLL162_BUFG/I0
  Logical resource: PLL162_BUFG/I0
  Location pin: BUFGMUX_X3Y14.I0
  Clock network: PLL162
--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_xtalclk_ip
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_xtalclk_ip                  |     20.000ns|      5.000ns|     18.387ns|            0|            0|            0|         6977|
| TS_clk_wiz_v1_6_50x62x312_clko|      3.200ns|      2.942ns|          N/A|            0|            0|          256|            0|
| ut1                           |             |             |             |             |             |             |             |
| TS_clk_wiz_v1_6_50x62x312_clko|     16.000ns|      7.361ns|          N/A|            0|            0|         6721|            0|
| ut0                           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_DP_CLK1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_DP_CLK1                     |     37.037ns|     16.000ns|     19.200ns|            0|            0|            0|            0|
| TS_PLL162                     |      6.173ns|      3.200ns|          N/A|            0|            0|            0|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock DP_CLK0
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
DP_CLK0        |    7.228|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock xtalclk_ip
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
xtalclk_ip     |    7.361|         |    1.471|         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 27508 paths, 0 nets, and 12173 connections

Design statistics:
   Minimum period:  16.000ns{1}   (Maximum frequency:  62.500MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed SAT 12 NOV 11:35:36 2011 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 194 MB



