Release 12.2 Drc M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

SAT 12 NOV 11:35:43 2011

drc -z exp6t_disp_dp.ncd exp6t_disp_dp.pcf

WARNING:PhysDesignRules:367 - The signal <TMDS_CEC_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TMDS_HPD_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TMDS_SDA_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <TMDS_SCL_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_CLKOUT_IP_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<10>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<11>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<12>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<10>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<13>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<11>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<14>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<12>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<15>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<13>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<14>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<15>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_LDQS_N_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_LDQS_P_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<0>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <pushsw_ip<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_UDQS_N_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_UDQS_P_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<0>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <dipsw_ip<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<22>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<23>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<24>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<25>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<26>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<27>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<28>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO1C<29>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<10>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<11>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<12>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<20>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<13>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<21>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<14>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<22>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<15>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<23>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<16>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<24>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<17>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<25>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<26>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<18>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<27>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<19>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<28>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<29>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGA_IP_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGB_IP_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGC_IP_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<0>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<0>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<4>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<5>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<4>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<6>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<5>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<7>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<6>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<8>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<7>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <USB_FD_BP<9>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<8>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DDR2_D<9>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<0>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<4>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<5>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<6>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<7>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<8>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<9>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <CFG_MISO_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DP_RSV1_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DP_RSV2_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp ctm_27x162/dcm_sp_inst,
   consult the device Data Sheet.
DRC detected 0 errors and 92 warnings.  Please see the previously displayed
individual error or warning messages for more details.
