--------------------------------------------------------------------------------
Release 12.2 Trace  (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

C:\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml exp6t_disp.twx exp6t_disp.ncd -o exp6t_disp.twr
exp6t_disp.pcf

Design file:              exp6t_disp.ncd
Physical constraint file: exp6t_disp.pcf
Device,package,speed:     xc6slx45t,fgg484,C,-3 (PRELIMINARY 1.10 2010-06-28)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_xtalclk = PERIOD TIMEGRP "xtalclk" 20 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   8.000ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_xtalclk = PERIOD TIMEGRP "xtalclk" 20 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.249ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1
  Logical resource: clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1
  Location pin: PLL_ADV_X0Y3.CLKOUT1
  Clock network: clk_wiz_v1_6_50x62x312/clkout1
--------------------------------------------------------------------------------
Slack: 2.330ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 2.670ns (374.532MHz) (Tdcmper_CLKFX)
  Physical resource: clk_wiz_v1_6_50x200/dcm_sp_inst/CLKFX
  Logical resource: clk_wiz_v1_6_50x200/dcm_sp_inst/CLKFX
  Location pin: DCM_X0Y6.CLKFX
  Clock network: clk_wiz_v1_6_50x200/clkfx
--------------------------------------------------------------------------------
Slack: 12.000ns (period - (min low pulse limit / (low pulse / period)))
  Period: 20.000ns
  Low pulse: 10.000ns
  Low pulse limit: 4.000ns (Tdcmpw_CLKIN_50_100)
  Physical resource: clk_wiz_v1_6_50x200/dcm_sp_inst/CLKIN
  Logical resource: clk_wiz_v1_6_50x200/dcm_sp_inst/CLKIN
  Location pin: DCM_X0Y6.CLKIN
  Clock network: clk_wiz_v1_6_50x200/clkin1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP "GTPCLKOUT1<0>" 162 MHz 
HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.904ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP "GTPCLKOUT1<0>" 162 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.268ns (period - min period limit)
  Period: 6.172ns
  Min period limit: 1.904ns (525.210MHz) (Tbufper_I)
  Physical resource: gtpclkout1_0_dcm2_bufio2_i/I
  Logical resource: gtpclkout1_0_dcm2_bufio2_i/I
  Location pin: BUFIO2_X4Y26.I
  Clock network: GTPCLKOUT1<0>
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_epcie_refclkn = PERIOD TIMEGRP "epcie_refclkn" 100 MHz 
HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   3.200ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_epcie_refclkn = PERIOD TIMEGRP "epcie_refclkn" 100 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 6.800ns (period - min period limit)
  Period: 10.000ns
  Min period limit: 3.200ns (312.500MHz) (Tgtpcper_CLK)
  Physical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/CLK01
  Logical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/CLK01
  Location pin: GTPA1_DUAL_X0Y0.CLK11
  Clock network: inst_sp6wrap/sys_clk_c
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD TIMEGRP   
      "inst_sp6wrap/eptest_i/gt_refclk_out<0>" 8 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.904ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD TIMEGRP
        "inst_sp6wrap/eptest_i/gt_refclk_out<0>" 8 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 6.096ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 1.904ns (525.210MHz) (Tbufper_I)
  Physical resource: inst_sp6wrap/eptest_i/gt_refclk_bufio2/I
  Logical resource: inst_sp6wrap/eptest_i/gt_refclk_bufio2/I
  Location pin: BUFIO2_X2Y26.I
  Clock network: inst_sp6wrap/eptest_i/gt_refclk_out<0>
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_DP_CLK1 = PERIOD TIMEGRP "DP_CLK1" 27 MHz HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is  16.000ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_DP_CLK1 = PERIOD TIMEGRP "DP_CLK1" 27 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 3.503ns (period - min period limit)
  Period: 6.173ns
  Min period limit: 2.670ns (374.532MHz) (Tdcmper_CLKFX)
  Physical resource: ctm_27x162/dcm_sp_inst/CLKFX
  Logical resource: ctm_27x162/dcm_sp_inst/CLKFX
  Location pin: DCM_X0Y7.CLKFX
  Clock network: ctm_27x162/clkfx
--------------------------------------------------------------------------------
Slack: 21.037ns (period - (min low pulse limit / (low pulse / period)))
  Period: 37.037ns
  Low pulse: 18.518ns
  Low pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50)
  Physical resource: ctm_27x162/dcm_sp_inst/CLKIN
  Logical resource: ctm_27x162/dcm_sp_inst/CLKIN
  Location pin: DCM_X0Y7.CLKIN
  Clock network: ctm_27x162/clkin1
--------------------------------------------------------------------------------
Slack: 21.037ns (period - (min high pulse limit / (high pulse / period)))
  Period: 37.037ns
  High pulse: 18.518ns
  High pulse limit: 8.000ns (Tdcmpw_CLKIN_25_50)
  Physical resource: ctm_27x162/dcm_sp_inst/CLKIN
  Logical resource: ctm_27x162/dcm_sp_inst/CLKIN
  Location pin: DCM_X0Y7.CLKIN
  Clock network: ctm_27x162/clkin1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27 MHz HIGH 50%;

 2956 paths analyzed, 1022 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   8.392ns.
--------------------------------------------------------------------------------

Paths for end point dp_main/aux_tx/aux_count_r_4 (SLICE_X13Y1.B1), 45 paths
--------------------------------------------------------------------------------
Slack (setup path):     28.645ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_clk_one_r (FF)
  Destination:          dp_main/aux_tx/aux_count_r_4 (FF)
  Requirement:          37.037ns
  Data Path Delay:      7.539ns (Levels of Logic = 5)
  Clock Path Skew:      -0.818ns (0.521 - 1.339)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_clk_one_r to dp_main/aux_tx/aux_count_r_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y8.BQ        Tcko                  0.525   dp_main/aux_tx/aux_clk_one_r
                                                       dp_main/aux_tx/aux_clk_one_r
    SLICE_X19Y7.A6       net (fanout=35)       2.101   dp_main/aux_tx/aux_clk_one_r
    SLICE_X19Y7.A        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29944_388
    SLICE_X15Y7.C4       net (fanout=2)        0.949   lut29944_388
    SLICE_X15Y7.C        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       lut30137_391
    SLICE_X15Y7.D4       net (fanout=1)        0.487   lut30137_391
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y1.B1       net (fanout=5)        0.983   dp_main/aux_tx/N119
    SLICE_X13Y1.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<4>
                                                       lut30170_6523
                                                       dp_main/aux_tx/aux_count_r_4
    -------------------------------------------------  ---------------------------
    Total                                      7.539ns (1.857ns logic, 5.682ns route)
                                                       (24.6% logic, 75.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     28.727ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_state_r_FSM_FFd2 (FF)
  Destination:          dp_main/aux_tx/aux_count_r_4 (FF)
  Requirement:          37.037ns
  Data Path Delay:      7.100ns (Levels of Logic = 5)
  Clock Path Skew:      -1.175ns (0.521 - 1.696)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_state_r_FSM_FFd2 to dp_main/aux_tx/aux_count_r_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y8.CQ       Tcko                  0.430   dp_main/aux_tx/aux_data8_r
                                                       dp_main/aux_tx/aux_state_r_FSM_FFd2
    SLICE_X22Y8.B3       net (fanout=33)       1.810   dp_main/aux_tx/aux_state_r_FSM_FFd2
    SLICE_X22Y8.B        Tilo                  0.254   dp_main/aux_tx/aux_tx_data_r<2>
                                                       lut29533_370
    SLICE_X22Y8.A5       net (fanout=7)        0.268   lut29533_370
    SLICE_X22Y8.A        Tilo                  0.254   dp_main/aux_tx/aux_tx_data_r<2>
                                                       lut29534_394
    SLICE_X15Y7.D1       net (fanout=5)        1.125   lut29534_394
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y1.B1       net (fanout=5)        0.983   dp_main/aux_tx/N119
    SLICE_X13Y1.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<4>
                                                       lut30170_6523
                                                       dp_main/aux_tx/aux_count_r_4
    -------------------------------------------------  ---------------------------
    Total                                      7.100ns (1.752ns logic, 5.348ns route)
                                                       (24.7% logic, 75.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     28.763ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_state_r_FSM_FFd4 (FF)
  Destination:          dp_main/aux_tx/aux_count_r_4 (FF)
  Requirement:          37.037ns
  Data Path Delay:      7.497ns (Levels of Logic = 6)
  Clock Path Skew:      -0.742ns (0.521 - 1.263)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_state_r_FSM_FFd4 to dp_main/aux_tx/aux_count_r_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y6.AQ       Tcko                  0.525   dp_main/aux_tx/aux_state_r_FSM_FFd3
                                                       dp_main/aux_tx/aux_state_r_FSM_FFd4
    SLICE_X19Y7.B2       net (fanout=34)       1.570   dp_main/aux_tx/aux_state_r_FSM_FFd4
    SLICE_X19Y7.B        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29943_387
    SLICE_X19Y7.A5       net (fanout=2)        0.230   lut29943_387
    SLICE_X19Y7.A        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29944_388
    SLICE_X15Y7.C4       net (fanout=2)        0.949   lut29944_388
    SLICE_X15Y7.C        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       lut30137_391
    SLICE_X15Y7.D4       net (fanout=1)        0.487   lut30137_391
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y1.B1       net (fanout=5)        0.983   dp_main/aux_tx/N119
    SLICE_X13Y1.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<4>
                                                       lut30170_6523
                                                       dp_main/aux_tx/aux_count_r_4
    -------------------------------------------------  ---------------------------
    Total                                      7.497ns (2.116ns logic, 5.381ns route)
                                                       (28.2% logic, 71.8% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/aux_tx/aux_count_r_0 (SLICE_X13Y2.A4), 45 paths
--------------------------------------------------------------------------------
Slack (setup path):     29.055ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_clk_one_r (FF)
  Destination:          dp_main/aux_tx/aux_count_r_0 (FF)
  Requirement:          37.037ns
  Data Path Delay:      7.337ns (Levels of Logic = 5)
  Clock Path Skew:      -0.610ns (0.729 - 1.339)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_clk_one_r to dp_main/aux_tx/aux_count_r_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y8.BQ        Tcko                  0.525   dp_main/aux_tx/aux_clk_one_r
                                                       dp_main/aux_tx/aux_clk_one_r
    SLICE_X19Y7.A6       net (fanout=35)       2.101   dp_main/aux_tx/aux_clk_one_r
    SLICE_X19Y7.A        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29944_388
    SLICE_X15Y7.C4       net (fanout=2)        0.949   lut29944_388
    SLICE_X15Y7.C        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       lut30137_391
    SLICE_X15Y7.D4       net (fanout=1)        0.487   lut30137_391
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y2.A4       net (fanout=5)        0.781   dp_main/aux_tx/N119
    SLICE_X13Y2.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<3>
                                                       lut30149_6510
                                                       dp_main/aux_tx/aux_count_r_0
    -------------------------------------------------  ---------------------------
    Total                                      7.337ns (1.857ns logic, 5.480ns route)
                                                       (25.3% logic, 74.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     29.137ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_state_r_FSM_FFd2 (FF)
  Destination:          dp_main/aux_tx/aux_count_r_0 (FF)
  Requirement:          37.037ns
  Data Path Delay:      6.898ns (Levels of Logic = 5)
  Clock Path Skew:      -0.967ns (0.729 - 1.696)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_state_r_FSM_FFd2 to dp_main/aux_tx/aux_count_r_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y8.CQ       Tcko                  0.430   dp_main/aux_tx/aux_data8_r
                                                       dp_main/aux_tx/aux_state_r_FSM_FFd2
    SLICE_X22Y8.B3       net (fanout=33)       1.810   dp_main/aux_tx/aux_state_r_FSM_FFd2
    SLICE_X22Y8.B        Tilo                  0.254   dp_main/aux_tx/aux_tx_data_r<2>
                                                       lut29533_370
    SLICE_X22Y8.A5       net (fanout=7)        0.268   lut29533_370
    SLICE_X22Y8.A        Tilo                  0.254   dp_main/aux_tx/aux_tx_data_r<2>
                                                       lut29534_394
    SLICE_X15Y7.D1       net (fanout=5)        1.125   lut29534_394
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y2.A4       net (fanout=5)        0.781   dp_main/aux_tx/N119
    SLICE_X13Y2.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<3>
                                                       lut30149_6510
                                                       dp_main/aux_tx/aux_count_r_0
    -------------------------------------------------  ---------------------------
    Total                                      6.898ns (1.752ns logic, 5.146ns route)
                                                       (25.4% logic, 74.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     29.173ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_state_r_FSM_FFd4 (FF)
  Destination:          dp_main/aux_tx/aux_count_r_0 (FF)
  Requirement:          37.037ns
  Data Path Delay:      7.295ns (Levels of Logic = 6)
  Clock Path Skew:      -0.534ns (0.729 - 1.263)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_state_r_FSM_FFd4 to dp_main/aux_tx/aux_count_r_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y6.AQ       Tcko                  0.525   dp_main/aux_tx/aux_state_r_FSM_FFd3
                                                       dp_main/aux_tx/aux_state_r_FSM_FFd4
    SLICE_X19Y7.B2       net (fanout=34)       1.570   dp_main/aux_tx/aux_state_r_FSM_FFd4
    SLICE_X19Y7.B        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29943_387
    SLICE_X19Y7.A5       net (fanout=2)        0.230   lut29943_387
    SLICE_X19Y7.A        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29944_388
    SLICE_X15Y7.C4       net (fanout=2)        0.949   lut29944_388
    SLICE_X15Y7.C        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       lut30137_391
    SLICE_X15Y7.D4       net (fanout=1)        0.487   lut30137_391
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y2.A4       net (fanout=5)        0.781   dp_main/aux_tx/N119
    SLICE_X13Y2.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<3>
                                                       lut30149_6510
                                                       dp_main/aux_tx/aux_count_r_0
    -------------------------------------------------  ---------------------------
    Total                                      7.295ns (2.116ns logic, 5.179ns route)
                                                       (29.0% logic, 71.0% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/aux_tx/aux_count_r_3 (SLICE_X13Y2.D3), 45 paths
--------------------------------------------------------------------------------
Slack (setup path):     29.167ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_clk_one_r (FF)
  Destination:          dp_main/aux_tx/aux_count_r_3 (FF)
  Requirement:          37.037ns
  Data Path Delay:      7.225ns (Levels of Logic = 5)
  Clock Path Skew:      -0.610ns (0.729 - 1.339)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_clk_one_r to dp_main/aux_tx/aux_count_r_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y8.BQ        Tcko                  0.525   dp_main/aux_tx/aux_clk_one_r
                                                       dp_main/aux_tx/aux_clk_one_r
    SLICE_X19Y7.A6       net (fanout=35)       2.101   dp_main/aux_tx/aux_clk_one_r
    SLICE_X19Y7.A        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29944_388
    SLICE_X15Y7.C4       net (fanout=2)        0.949   lut29944_388
    SLICE_X15Y7.C        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       lut30137_391
    SLICE_X15Y7.D4       net (fanout=1)        0.487   lut30137_391
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y2.D3       net (fanout=5)        0.669   dp_main/aux_tx/N119
    SLICE_X13Y2.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<3>
                                                       lut30165_6520
                                                       dp_main/aux_tx/aux_count_r_3
    -------------------------------------------------  ---------------------------
    Total                                      7.225ns (1.857ns logic, 5.368ns route)
                                                       (25.7% logic, 74.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     29.249ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_state_r_FSM_FFd2 (FF)
  Destination:          dp_main/aux_tx/aux_count_r_3 (FF)
  Requirement:          37.037ns
  Data Path Delay:      6.786ns (Levels of Logic = 5)
  Clock Path Skew:      -0.967ns (0.729 - 1.696)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_state_r_FSM_FFd2 to dp_main/aux_tx/aux_count_r_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y8.CQ       Tcko                  0.430   dp_main/aux_tx/aux_data8_r
                                                       dp_main/aux_tx/aux_state_r_FSM_FFd2
    SLICE_X22Y8.B3       net (fanout=33)       1.810   dp_main/aux_tx/aux_state_r_FSM_FFd2
    SLICE_X22Y8.B        Tilo                  0.254   dp_main/aux_tx/aux_tx_data_r<2>
                                                       lut29533_370
    SLICE_X22Y8.A5       net (fanout=7)        0.268   lut29533_370
    SLICE_X22Y8.A        Tilo                  0.254   dp_main/aux_tx/aux_tx_data_r<2>
                                                       lut29534_394
    SLICE_X15Y7.D1       net (fanout=5)        1.125   lut29534_394
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y2.D3       net (fanout=5)        0.669   dp_main/aux_tx/N119
    SLICE_X13Y2.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<3>
                                                       lut30165_6520
                                                       dp_main/aux_tx/aux_count_r_3
    -------------------------------------------------  ---------------------------
    Total                                      6.786ns (1.752ns logic, 5.034ns route)
                                                       (25.8% logic, 74.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     29.285ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/aux_tx/aux_state_r_FSM_FFd4 (FF)
  Destination:          dp_main/aux_tx/aux_count_r_3 (FF)
  Requirement:          37.037ns
  Data Path Delay:      7.183ns (Levels of Logic = 6)
  Clock Path Skew:      -0.534ns (0.729 - 1.263)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/aux_tx/aux_state_r_FSM_FFd4 to dp_main/aux_tx/aux_count_r_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y6.AQ       Tcko                  0.525   dp_main/aux_tx/aux_state_r_FSM_FFd3
                                                       dp_main/aux_tx/aux_state_r_FSM_FFd4
    SLICE_X19Y7.B2       net (fanout=34)       1.570   dp_main/aux_tx/aux_state_r_FSM_FFd4
    SLICE_X19Y7.B        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29943_387
    SLICE_X19Y7.A5       net (fanout=2)        0.230   lut29943_387
    SLICE_X19Y7.A        Tilo                  0.259   dp_main/link_aux_tx_done
                                                       lut29944_388
    SLICE_X15Y7.C4       net (fanout=2)        0.949   lut29944_388
    SLICE_X15Y7.C        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       lut30137_391
    SLICE_X15Y7.D4       net (fanout=1)        0.487   lut30137_391
    SLICE_X15Y7.D        Tilo                  0.259   dp_main/aux_tx/Mmux_aux_count_w1516
                                                       dp_main/aux_tx/Mmux_aux_count_w1517
    SLICE_X14Y3.CX       net (fanout=1)        1.162   dp_main/aux_tx/Mmux_aux_count_w1516
    SLICE_X14Y3.CMUX     Tcxc                  0.182   dp_main/aux_tx/N119
                                                       dp_main/aux_tx/Mmux_aux_count_w1518
    SLICE_X13Y2.D3       net (fanout=5)        0.669   dp_main/aux_tx/N119
    SLICE_X13Y2.CLK      Tas                   0.373   dp_main/aux_tx/aux_count_r<3>
                                                       lut30165_6520
                                                       dp_main/aux_tx/aux_count_r_3
    -------------------------------------------------  ---------------------------
    Total                                      7.183ns (2.116ns logic, 5.067ns route)
                                                       (29.5% logic, 70.5% route)

--------------------------------------------------------------------------------

Hold Paths: TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27 MHz HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point dp_main/aux_tx/aux_data8_r (SLICE_X15Y8.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.254ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/aux_tx/aux_count_r_2 (FF)
  Destination:          dp_main/aux_tx/aux_data8_r (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.845ns (Levels of Logic = 1)
  Clock Path Skew:      0.591ns (0.950 - 0.359)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/aux_tx/aux_count_r_2 to dp_main/aux_tx/aux_data8_r
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y2.CQ       Tcko                  0.198   dp_main/aux_tx/aux_count_r<3>
                                                       dp_main/aux_tx/aux_count_r_2
    SLICE_X15Y8.D6       net (fanout=9)        0.432   dp_main/aux_tx/aux_count_r<2>
    SLICE_X15Y8.CLK      Tah         (-Th)    -0.215   dp_main/aux_tx/aux_data8_r
                                                       lut30097_6503
                                                       dp_main/aux_tx/aux_data8_r
    -------------------------------------------------  ---------------------------
    Total                                      0.845ns (0.413ns logic, 0.432ns route)
                                                       (48.9% logic, 51.1% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_linkup/aux_stat_algn_r (SLICE_X26Y15.A3), 6 paths
--------------------------------------------------------------------------------
Slack (hold path):      0.275ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_linkup/aux_cmd_code_r_17 (FF)
  Destination:          dp_main/dp_main_linkup/aux_stat_algn_r (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.939ns (Levels of Logic = 2)
  Clock Path Skew:      0.664ns (1.355 - 0.691)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_linkup/aux_cmd_code_r_17 to dp_main/dp_main_linkup/aux_stat_algn_r
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y15.CQ      Tcko                  0.198   dp_main/link_aux_tx_addr<9>
                                                       dp_main/dp_main_linkup/aux_cmd_code_r_17
    SLICE_X26Y15.B5      net (fanout=2)        0.176   dp_main/link_aux_tx_addr<9>
    SLICE_X26Y15.B       Tilo                  0.156   dp_main/dp_main_linkup/aux_stat_algn_r
                                                       lut27254_5906
    SLICE_X26Y15.A3      net (fanout=2)        0.212   lut27254_5906
    SLICE_X26Y15.CLK     Tah         (-Th)    -0.197   dp_main/dp_main_linkup/aux_stat_algn_r
                                                       dp_main/dp_main_linkup/aux_stat_algn_r_rstpot
                                                       dp_main/dp_main_linkup/aux_stat_algn_r
    -------------------------------------------------  ---------------------------
    Total                                      0.939ns (0.551ns logic, 0.388ns route)
                                                       (58.7% logic, 41.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.303ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_linkup/aux_cmd_code_r_28 (FF)
  Destination:          dp_main/dp_main_linkup/aux_stat_algn_r (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.968ns (Levels of Logic = 2)
  Clock Path Skew:      0.665ns (1.355 - 0.690)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_linkup/aux_cmd_code_r_28 to dp_main/dp_main_linkup/aux_stat_algn_r
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y15.AQ      Tcko                  0.234   dp_main/link_aux_tx_cmd<3>
                                                       dp_main/dp_main_linkup/aux_cmd_code_r_28
    SLICE_X26Y15.B6      net (fanout=2)        0.169   dp_main/link_aux_tx_cmd<0>
    SLICE_X26Y15.B       Tilo                  0.156   dp_main/dp_main_linkup/aux_stat_algn_r
                                                       lut27254_5906
    SLICE_X26Y15.A3      net (fanout=2)        0.212   lut27254_5906
    SLICE_X26Y15.CLK     Tah         (-Th)    -0.197   dp_main/dp_main_linkup/aux_stat_algn_r
                                                       dp_main/dp_main_linkup/aux_stat_algn_r_rstpot
                                                       dp_main/dp_main_linkup/aux_stat_algn_r
    -------------------------------------------------  ---------------------------
    Total                                      0.968ns (0.587ns logic, 0.381ns route)
                                                       (60.6% logic, 39.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.387ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_linkup/aux_cmd_code_r_16 (FF)
  Destination:          dp_main/dp_main_linkup/aux_stat_algn_r (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.051ns (Levels of Logic = 2)
  Clock Path Skew:      0.664ns (1.355 - 0.691)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_linkup/aux_cmd_code_r_16 to dp_main/dp_main_linkup/aux_stat_algn_r
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y15.AQ      Tcko                  0.198   dp_main/link_aux_tx_addr<9>
                                                       dp_main/dp_main_linkup/aux_cmd_code_r_16
    SLICE_X26Y15.B3      net (fanout=2)        0.288   dp_main/link_aux_tx_addr<8>
    SLICE_X26Y15.B       Tilo                  0.156   dp_main/dp_main_linkup/aux_stat_algn_r
                                                       lut27254_5906
    SLICE_X26Y15.A3      net (fanout=2)        0.212   lut27254_5906
    SLICE_X26Y15.CLK     Tah         (-Th)    -0.197   dp_main/dp_main_linkup/aux_stat_algn_r
                                                       dp_main/dp_main_linkup/aux_stat_algn_r_rstpot
                                                       dp_main/dp_main_linkup/aux_stat_algn_r
    -------------------------------------------------  ---------------------------
    Total                                      1.051ns (0.551ns logic, 0.500ns route)
                                                       (52.4% logic, 47.6% route)

--------------------------------------------------------------------------------

Paths for end point aux_hpd_count_r_2 (SLICE_X13Y10.C6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.283ns (requirement - (clock path skew + uncertainty - data path))
  Source:               aux_hpd_in_r_1 (FF)
  Destination:          aux_hpd_count_r_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.845ns (Levels of Logic = 1)
  Clock Path Skew:      0.562ns (0.932 - 0.370)
  Source Clock:         CLK27 rising at 0.000ns
  Destination Clock:    CLK27 rising at 37.037ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: aux_hpd_in_r_1 to aux_hpd_count_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y2.DQ       Tcko                  0.200   aux_hpd_in_r<1>
                                                       aux_hpd_in_r_1
    SLICE_X13Y10.C6      net (fanout=16)       0.430   aux_hpd_in_r<1>
    SLICE_X13Y10.CLK     Tah         (-Th)    -0.215   aux_hpd_count_r<3>
                                                       lut6125_893
                                                       aux_hpd_count_r_2
    -------------------------------------------------  ---------------------------
    Total                                      0.845ns (0.415ns logic, 0.430ns route)
                                                       (49.1% logic, 50.9% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 35.638ns (period - min period limit)
  Period: 37.037ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: dp_main/dp_main_linkup/hpd_r_5_BRB1/CLK
  Logical resource: dp_main/dp_main_linkup/Mshreg_hpd_r_5_BRB1/CLK
  Location pin: SLICE_X44Y49.CLK
  Clock network: CLK27
--------------------------------------------------------------------------------
Slack: 36.557ns (period - (min high pulse limit / (high pulse / period)))
  Period: 37.037ns
  High pulse: 18.518ns
  High pulse limit: 0.240ns (Trpw)
  Physical resource: dp_main/aux_tx/aux_clk_one_r/SR
  Logical resource: dp_main/aux_tx/aux_clk_one_r/SR
  Location pin: SLICE_X6Y8.SR
  Clock network: ][24489_9
--------------------------------------------------------------------------------
Slack: 36.557ns (period - (min high pulse limit / (high pulse / period)))
  Period: 37.037ns
  High pulse: 18.518ns
  High pulse limit: 0.240ns (Trpw)
  Physical resource: dp_main/aux_tx/aux_clk_r<3>/SR
  Logical resource: dp_main/aux_tx/aux_clk_r_0/SR
  Location pin: SLICE_X6Y10.SR
  Clock network: ][24489_9
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 5 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.800ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.549ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Logical resource: memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Location pin: PLL_ADV_X0Y0.CLKOUT0
  Clock network: memc3_infrastructure_inst/clk_2x_0
--------------------------------------------------------------------------------
Slack: 1.549ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: memc3_infrastructure_inst/u_pll_adv/CLKOUT1
  Logical resource: memc3_infrastructure_inst/u_pll_adv/CLKOUT1
  Location pin: PLL_ADV_X0Y0.CLKOUT1
  Clock network: memc3_infrastructure_inst/clk_2x_180
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.000ns
  Low pulse: 2.500ns
  Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: CLK200
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIMEGRP 
"clk_wiz_v1_6_50x200_clkfx"         TS_xtalclk / 4 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.800ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIMEGRP "clk_wiz_v1_6_50x200_clkfx"
        TS_xtalclk / 4 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.549ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Logical resource: memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Location pin: PLL_ADV_X0Y0.CLKOUT0
  Clock network: memc3_infrastructure_inst/clk_2x_0
--------------------------------------------------------------------------------
Slack: 1.549ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: memc3_infrastructure_inst/u_pll_adv/CLKOUT1
  Logical resource: memc3_infrastructure_inst/u_pll_adv/CLKOUT1
  Location pin: PLL_ADV_X0Y0.CLKOUT1
  Clock network: memc3_infrastructure_inst/clk_2x_180
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.000ns
  Low pulse: 2.500ns
  Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: CLK200
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP         
"clk_wiz_v1_6_50x62x312_clkout1" TS_xtalclk / 6.25 HIGH 50%;

 133 paths analyzed, 133 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   3.130ns.
--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx2_out_r_0 (SLICE_X54Y2.A5), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.070ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/tx3_r_3 (FF)
  Destination:          tx_dvi/tx2_out_r_0 (FF)
  Requirement:          3.200ns
  Data Path Delay:      3.009ns (Levels of Logic = 1)
  Clock Path Skew:      -0.007ns (0.252 - 0.259)
  Source Clock:         CLK63x5 rising at 0.000ns
  Destination Clock:    CLK63x5 rising at 3.200ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/tx3_r_3 to tx_dvi/tx2_out_r_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X43Y9.BQ       Tcko                  0.430   tx_dvi/tx3_r<3>
                                                       tx_dvi/tx3_r_3
    SLICE_X54Y2.A5       net (fanout=33)       2.230   tx_dvi/tx3_r<3>
    SLICE_X54Y2.CLK      Tas                   0.349   tx_dvi/tx2_out_r<0>
                                                       lut13420_2136
                                                       tx_dvi/tx2_out_r_0
    -------------------------------------------------  ---------------------------
    Total                                      3.009ns (0.779ns logic, 2.230ns route)
                                                       (25.9% logic, 74.1% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx0_r_5_BRB1 (SLICE_X31Y16.D6), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.143ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/tx3_r_3 (FF)
  Destination:          tx_dvi/tx0_r_5_BRB1 (FF)
  Requirement:          3.200ns
  Data Path Delay:      2.900ns (Levels of Logic = 1)
  Clock Path Skew:      -0.043ns (0.496 - 0.539)
  Source Clock:         CLK63x5 rising at 0.000ns
  Destination Clock:    CLK63x5 rising at 3.200ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/tx3_r_3 to tx_dvi/tx0_r_5_BRB1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X43Y9.BQ       Tcko                  0.430   tx_dvi/tx3_r<3>
                                                       tx_dvi/tx3_r_3
    SLICE_X31Y16.D6      net (fanout=33)       2.097   tx_dvi/tx3_r<3>
    SLICE_X31Y16.CLK     Tas                   0.373   tx_dvi/tx0_r_5_BRB1
                                                       lut13164_2079
                                                       tx_dvi/tx0_r_5_BRB1
    -------------------------------------------------  ---------------------------
    Total                                      2.900ns (0.803ns logic, 2.097ns route)
                                                       (27.7% logic, 72.3% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/DDR_tx2_p (OLOGIC_X24Y1.D2), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.246ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/tx2_out_r_0 (FF)
  Destination:          tx_dvi/DDR_tx2_p (FF)
  Requirement:          1.600ns
  Data Path Delay:      1.646ns (Levels of Logic = 0)
  Clock Path Skew:      0.406ns (0.580 - 0.174)
  Source Clock:         CLK63x5 rising at 0.000ns
  Destination Clock:    CLK63x5 falling at 1.600ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/tx2_out_r_0 to tx_dvi/DDR_tx2_p
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X54Y2.AQ       Tcko                  0.476   tx_dvi/tx2_out_r<0>
                                                       tx_dvi/tx2_out_r_0
    OLOGIC_X24Y1.D2      net (fanout=1)        0.506   tx_dvi/tx2_out_r<0>
    OLOGIC_X24Y1.CLK1    Todck                 0.664   tx_dvi/tx_ch2_ddr
                                                       tx_dvi/DDR_tx2_p
    -------------------------------------------------  ---------------------------
    Total                                      1.646ns (1.140ns logic, 0.506ns route)
                                                       (69.3% logic, 30.7% route)

--------------------------------------------------------------------------------

Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        "clk_wiz_v1_6_50x62x312_clkout1" TS_xtalclk / 6.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx2_r_9_BRB1 (SLICE_X22Y11.A5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.076ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/ch2_enc_r_9 (FF)
  Destination:          tx_dvi/tx2_r_9_BRB1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.399ns (Levels of Logic = 1)
  Clock Path Skew:      0.055ns (1.161 - 1.106)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63x5 rising at 3.200ns
  Clock Uncertainty:    0.268ns

  Clock Uncertainty:          0.268ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: tx_dvi/ch2_enc_r_9 to tx_dvi/tx2_r_9_BRB1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y11.BQ      Tcko                  0.198   tx_dvi/ch2_enc<9>
                                                       tx_dvi/ch2_enc_r_9
    SLICE_X22Y11.A5      net (fanout=1)        0.070   tx_dvi/ch2_enc_r<9>
    SLICE_X22Y11.CLK     Tah         (-Th)    -0.131   tx_dvi/tx2_r_8_BRB1
                                                       tx_dvi/ch2_enc_r<9>_rt
                                                       tx_dvi/tx2_r_9_BRB1
    -------------------------------------------------  ---------------------------
    Total                                      0.399ns (0.329ns logic, 0.070ns route)
                                                       (82.5% logic, 17.5% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx2_r_7_BRB2 (SLICE_X27Y8.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.297ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/ch2_enc_r_7 (FF)
  Destination:          tx_dvi/tx2_r_7_BRB2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.621ns (Levels of Logic = 0)
  Clock Path Skew:      0.056ns (1.155 - 1.099)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63x5 rising at 3.200ns
  Clock Uncertainty:    0.268ns

  Clock Uncertainty:          0.268ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: tx_dvi/ch2_enc_r_7 to tx_dvi/tx2_r_7_BRB2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y8.DQ       Tcko                  0.200   tx_dvi/ch2_enc_r<7>
                                                       tx_dvi/ch2_enc_r_7
    SLICE_X27Y8.AX       net (fanout=1)        0.362   tx_dvi/ch2_enc_r<7>
    SLICE_X27Y8.CLK      Tckdi       (-Th)    -0.059   tx_dvi/tx2_r_6_BRB2
                                                       tx_dvi/tx2_r_7_BRB2
    -------------------------------------------------  ---------------------------
    Total                                      0.621ns (0.259ns logic, 0.362ns route)
                                                       (41.7% logic, 58.3% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/tx2_r_6_BRB2 (SLICE_X27Y8.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.298ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/ch2_enc_r_6 (FF)
  Destination:          tx_dvi/tx2_r_6_BRB2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.622ns (Levels of Logic = 0)
  Clock Path Skew:      0.056ns (1.155 - 1.099)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63x5 rising at 3.200ns
  Clock Uncertainty:    0.268ns

  Clock Uncertainty:          0.268ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: tx_dvi/ch2_enc_r_6 to tx_dvi/tx2_r_6_BRB2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y8.CQ       Tcko                  0.200   tx_dvi/ch2_enc_r<7>
                                                       tx_dvi/ch2_enc_r_6
    SLICE_X27Y8.DX       net (fanout=1)        0.363   tx_dvi/ch2_enc_r<6>
    SLICE_X27Y8.CLK      Tckdi       (-Th)    -0.059   tx_dvi/tx2_r_6_BRB2
                                                       tx_dvi/tx2_r_6_BRB2
    -------------------------------------------------  ---------------------------
    Total                                      0.622ns (0.259ns logic, 0.363ns route)
                                                       (41.6% logic, 58.4% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        "clk_wiz_v1_6_50x62x312_clkout1" TS_xtalclk / 6.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.930ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: clk_wiz_v1_6_50x62x312/clkout2_buf/I0
  Logical resource: clk_wiz_v1_6_50x62x312/clkout2_buf/I0
  Location pin: BUFGMUX_X3Y16.I0
  Clock network: clk_wiz_v1_6_50x62x312/clkout1
--------------------------------------------------------------------------------
Slack: 1.444ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 1.756ns (569.476MHz) (Tockper)
  Physical resource: tx_dvi/tx_ch0_ddr/CLK0
  Logical resource: tx_dvi/DDR_tx0_p/CK0
  Location pin: OLOGIC_X25Y3.CLK0
  Clock network: CLK63x5
--------------------------------------------------------------------------------
Slack: 1.444ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 1.756ns (569.476MHz) (Tockper)
  Physical resource: tx_dvi/tx_ch1_ddr/CLK0
  Logical resource: tx_dvi/DDR_tx1_p/CK0
  Location pin: OLOGIC_X26Y3.CLK0
  Clock network: CLK63x5
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP         
"clk_wiz_v1_6_50x62x312_clkout0" TS_xtalclk / 1.25 HIGH 50%;

 22498 paths analyzed, 1227 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   9.210ns.
--------------------------------------------------------------------------------

Paths for end point tx_dvi/enc1/st1_cnt_r_5 (SLICE_X4Y21.C6), 137 paths
--------------------------------------------------------------------------------
Slack (setup path):     6.790ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_7 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_5 (FF)
  Requirement:          16.000ns
  Data Path Delay:      9.051ns (Levels of Logic = 6)
  Clock Path Skew:      -0.011ns (0.246 - 0.257)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_7 to tx_dvi/enc1/st1_cnt_r_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y24.AQ      Tcko                  0.430   tx_dvi/enc1/st0_qm_r<8>
                                                       tx_dvi/enc1/st0_qm_r_7
    SLICE_X5Y18.D2       net (fanout=9)        2.082   tx_dvi/enc1/st0_qm_r<7>
    SLICE_X5Y18.D        Tilo                  0.259   lut11662_571
                                                       lut11662_571
    SLICE_X6Y21.B3       net (fanout=7)        0.896   lut11662_571
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X12Y18.B3      net (fanout=11)       1.416   lut11669_605
    SLICE_X12Y18.B       Tilo                  0.235   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X4Y21.B2       net (fanout=24)       1.968   tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X4Y21.B        Tilo                  0.235   tx_dvi/enc1/st1_cnt_r<5>
                                                       lut12062_602
    SLICE_X4Y21.C6       net (fanout=1)        0.253   lut12062_602
    SLICE_X4Y21.CLK      Tas                   0.433   tx_dvi/enc1/st1_cnt_r<5>
                                                       tx_dvi/enc1/Mmux_st1_cnt_w125_G
                                                       tx_dvi/enc1/Mmux_st1_cnt_w125
                                                       tx_dvi/enc1/st1_cnt_r_5
    -------------------------------------------------  ---------------------------
    Total                                      9.051ns (2.101ns logic, 6.950ns route)
                                                       (23.2% logic, 76.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     7.220ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_4 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_5 (FF)
  Requirement:          16.000ns
  Data Path Delay:      8.621ns (Levels of Logic = 6)
  Clock Path Skew:      -0.011ns (0.246 - 0.257)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_4 to tx_dvi/enc1/st1_cnt_r_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y24.AQ      Tcko                  0.525   tx_dvi/enc1/st0_qm_r<6>
                                                       tx_dvi/enc1/st0_qm_r_4
    SLICE_X5Y18.D3       net (fanout=9)        1.557   tx_dvi/enc1/st0_qm_r<4>
    SLICE_X5Y18.D        Tilo                  0.259   lut11662_571
                                                       lut11662_571
    SLICE_X6Y21.B3       net (fanout=7)        0.896   lut11662_571
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X12Y18.B3      net (fanout=11)       1.416   lut11669_605
    SLICE_X12Y18.B       Tilo                  0.235   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X4Y21.B2       net (fanout=24)       1.968   tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X4Y21.B        Tilo                  0.235   tx_dvi/enc1/st1_cnt_r<5>
                                                       lut12062_602
    SLICE_X4Y21.C6       net (fanout=1)        0.253   lut12062_602
    SLICE_X4Y21.CLK      Tas                   0.433   tx_dvi/enc1/st1_cnt_r<5>
                                                       tx_dvi/enc1/Mmux_st1_cnt_w125_G
                                                       tx_dvi/enc1/Mmux_st1_cnt_w125
                                                       tx_dvi/enc1/st1_cnt_r_5
    -------------------------------------------------  ---------------------------
    Total                                      8.621ns (2.196ns logic, 6.425ns route)
                                                       (25.5% logic, 74.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     7.262ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_6 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_5 (FF)
  Requirement:          16.000ns
  Data Path Delay:      8.579ns (Levels of Logic = 6)
  Clock Path Skew:      -0.011ns (0.246 - 0.257)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_6 to tx_dvi/enc1/st1_cnt_r_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y24.DQ      Tcko                  0.525   tx_dvi/enc1/st0_qm_r<6>
                                                       tx_dvi/enc1/st0_qm_r_6
    SLICE_X7Y18.C2       net (fanout=9)        1.666   tx_dvi/enc1/st0_qm_r<6>
    SLICE_X7Y18.C        Tilo                  0.259   lut11857_573
                                                       lut11663_567
    SLICE_X6Y21.B4       net (fanout=19)       0.745   lut11663_567
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X12Y18.B3      net (fanout=11)       1.416   lut11669_605
    SLICE_X12Y18.B       Tilo                  0.235   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X4Y21.B2       net (fanout=24)       1.968   tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X4Y21.B        Tilo                  0.235   tx_dvi/enc1/st1_cnt_r<5>
                                                       lut12062_602
    SLICE_X4Y21.C6       net (fanout=1)        0.253   lut12062_602
    SLICE_X4Y21.CLK      Tas                   0.433   tx_dvi/enc1/st1_cnt_r<5>
                                                       tx_dvi/enc1/Mmux_st1_cnt_w125_G
                                                       tx_dvi/enc1/Mmux_st1_cnt_w125
                                                       tx_dvi/enc1/st1_cnt_r_5
    -------------------------------------------------  ---------------------------
    Total                                      8.579ns (2.196ns logic, 6.383ns route)
                                                       (25.6% logic, 74.4% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/enc1/st1_qm_r_2 (SLICE_X29Y11.C2), 55 paths
--------------------------------------------------------------------------------
Slack (setup path):     6.967ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_7 (FF)
  Destination:          tx_dvi/enc1/st1_qm_r_2 (FF)
  Requirement:          16.000ns
  Data Path Delay:      8.895ns (Levels of Logic = 5)
  Clock Path Skew:      0.010ns (0.540 - 0.530)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_7 to tx_dvi/enc1/st1_qm_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y24.AQ      Tcko                  0.430   tx_dvi/enc1/st0_qm_r<8>
                                                       tx_dvi/enc1/st0_qm_r_7
    SLICE_X5Y18.D2       net (fanout=9)        2.082   tx_dvi/enc1/st0_qm_r<7>
    SLICE_X5Y18.D        Tilo                  0.259   lut11662_571
                                                       lut11662_571
    SLICE_X6Y21.B3       net (fanout=7)        0.896   lut11662_571
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X7Y19.B4       net (fanout=11)       0.570   lut11669_605
    SLICE_X7Y19.B        Tilo                  0.259   lut12060_582
                                                       tx_dvi/enc1/st0_abort_r_st1_case_cnt_ne_AND_496_o1
    SLICE_X29Y11.C2      net (fanout=23)       3.182   tx_dvi/enc1/N63
    SLICE_X29Y11.CLK     Tas                   0.373   tx_dvi/ch1_enc<3>
                                                       lut11706_1935
                                                       tx_dvi/enc1/st1_qm_r_2
    -------------------------------------------------  ---------------------------
    Total                                      8.895ns (1.830ns logic, 7.065ns route)
                                                       (20.6% logic, 79.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     7.397ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_4 (FF)
  Destination:          tx_dvi/enc1/st1_qm_r_2 (FF)
  Requirement:          16.000ns
  Data Path Delay:      8.465ns (Levels of Logic = 5)
  Clock Path Skew:      0.010ns (0.540 - 0.530)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_4 to tx_dvi/enc1/st1_qm_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y24.AQ      Tcko                  0.525   tx_dvi/enc1/st0_qm_r<6>
                                                       tx_dvi/enc1/st0_qm_r_4
    SLICE_X5Y18.D3       net (fanout=9)        1.557   tx_dvi/enc1/st0_qm_r<4>
    SLICE_X5Y18.D        Tilo                  0.259   lut11662_571
                                                       lut11662_571
    SLICE_X6Y21.B3       net (fanout=7)        0.896   lut11662_571
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X7Y19.B4       net (fanout=11)       0.570   lut11669_605
    SLICE_X7Y19.B        Tilo                  0.259   lut12060_582
                                                       tx_dvi/enc1/st0_abort_r_st1_case_cnt_ne_AND_496_o1
    SLICE_X29Y11.C2      net (fanout=23)       3.182   tx_dvi/enc1/N63
    SLICE_X29Y11.CLK     Tas                   0.373   tx_dvi/ch1_enc<3>
                                                       lut11706_1935
                                                       tx_dvi/enc1/st1_qm_r_2
    -------------------------------------------------  ---------------------------
    Total                                      8.465ns (1.925ns logic, 6.540ns route)
                                                       (22.7% logic, 77.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     7.439ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_6 (FF)
  Destination:          tx_dvi/enc1/st1_qm_r_2 (FF)
  Requirement:          16.000ns
  Data Path Delay:      8.423ns (Levels of Logic = 5)
  Clock Path Skew:      0.010ns (0.540 - 0.530)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_6 to tx_dvi/enc1/st1_qm_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y24.DQ      Tcko                  0.525   tx_dvi/enc1/st0_qm_r<6>
                                                       tx_dvi/enc1/st0_qm_r_6
    SLICE_X7Y18.C2       net (fanout=9)        1.666   tx_dvi/enc1/st0_qm_r<6>
    SLICE_X7Y18.C        Tilo                  0.259   lut11857_573
                                                       lut11663_567
    SLICE_X6Y21.B4       net (fanout=19)       0.745   lut11663_567
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X7Y19.B4       net (fanout=11)       0.570   lut11669_605
    SLICE_X7Y19.B        Tilo                  0.259   lut12060_582
                                                       tx_dvi/enc1/st0_abort_r_st1_case_cnt_ne_AND_496_o1
    SLICE_X29Y11.C2      net (fanout=23)       3.182   tx_dvi/enc1/N63
    SLICE_X29Y11.CLK     Tas                   0.373   tx_dvi/ch1_enc<3>
                                                       lut11706_1935
                                                       tx_dvi/enc1/st1_qm_r_2
    -------------------------------------------------  ---------------------------
    Total                                      8.423ns (1.925ns logic, 6.498ns route)
                                                       (22.9% logic, 77.1% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/enc1/st1_cnt_r_2 (SLICE_X6Y18.D5), 245 paths
--------------------------------------------------------------------------------
Slack (setup path):     7.069ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_7 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_2 (FF)
  Requirement:          16.000ns
  Data Path Delay:      8.779ns (Levels of Logic = 6)
  Clock Path Skew:      -0.004ns (0.253 - 0.257)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_7 to tx_dvi/enc1/st1_cnt_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y24.AQ      Tcko                  0.430   tx_dvi/enc1/st0_qm_r<8>
                                                       tx_dvi/enc1/st0_qm_r_7
    SLICE_X5Y18.D2       net (fanout=9)        2.082   tx_dvi/enc1/st0_qm_r<7>
    SLICE_X5Y18.D        Tilo                  0.259   lut11662_571
                                                       lut11662_571
    SLICE_X6Y21.B3       net (fanout=7)        0.896   lut11662_571
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X12Y18.B3      net (fanout=11)       1.416   lut11669_605
    SLICE_X12Y18.B       Tilo                  0.235   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X12Y18.D1      net (fanout=24)       0.552   tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X12Y18.CMUX    Topdc                 0.402   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/Mmux_st1_cnt_w62_F
                                                       tx_dvi/enc1/Mmux_st1_cnt_w62
    SLICE_X6Y18.D5       net (fanout=2)        1.214   tx_dvi/enc1/Mmux_st1_cnt_w61
    SLICE_X6Y18.CLK      Tas                   0.449   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/Mmux_st1_cnt_w64_F
                                                       tx_dvi/enc1/Mmux_st1_cnt_w64
                                                       tx_dvi/enc1/st1_cnt_r_2
    -------------------------------------------------  ---------------------------
    Total                                      8.779ns (2.284ns logic, 6.495ns route)
                                                       (26.0% logic, 74.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     7.349ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_7 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_2 (FF)
  Requirement:          16.000ns
  Data Path Delay:      8.499ns (Levels of Logic = 6)
  Clock Path Skew:      -0.004ns (0.253 - 0.257)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_7 to tx_dvi/enc1/st1_cnt_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y24.AQ      Tcko                  0.430   tx_dvi/enc1/st0_qm_r<8>
                                                       tx_dvi/enc1/st0_qm_r_7
    SLICE_X5Y18.D2       net (fanout=9)        2.082   tx_dvi/enc1/st0_qm_r<7>
    SLICE_X5Y18.D        Tilo                  0.259   lut11662_571
                                                       lut11662_571
    SLICE_X6Y21.B3       net (fanout=7)        0.896   lut11662_571
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X12Y18.B3      net (fanout=11)       1.416   lut11669_605
    SLICE_X12Y18.B       Tilo                  0.235   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X12Y18.C6      net (fanout=24)       0.271   tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X12Y18.CMUX    Tilo                  0.403   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/Mmux_st1_cnt_w62_G
                                                       tx_dvi/enc1/Mmux_st1_cnt_w62
    SLICE_X6Y18.D5       net (fanout=2)        1.214   tx_dvi/enc1/Mmux_st1_cnt_w61
    SLICE_X6Y18.CLK      Tas                   0.449   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/Mmux_st1_cnt_w64_F
                                                       tx_dvi/enc1/Mmux_st1_cnt_w64
                                                       tx_dvi/enc1/st1_cnt_r_2
    -------------------------------------------------  ---------------------------
    Total                                      8.499ns (2.285ns logic, 6.214ns route)
                                                       (26.9% logic, 73.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     7.499ns (requirement - (data path - clock path skew + uncertainty))
  Source:               tx_dvi/enc1/st0_qm_r_4 (FF)
  Destination:          tx_dvi/enc1/st1_cnt_r_2 (FF)
  Requirement:          16.000ns
  Data Path Delay:      8.349ns (Levels of Logic = 6)
  Clock Path Skew:      -0.004ns (0.253 - 0.257)
  Source Clock:         CLK63 rising at 0.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.148ns

  Clock Uncertainty:          0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.287ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: tx_dvi/enc1/st0_qm_r_4 to tx_dvi/enc1/st1_cnt_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y24.AQ      Tcko                  0.525   tx_dvi/enc1/st0_qm_r<6>
                                                       tx_dvi/enc1/st0_qm_r_4
    SLICE_X5Y18.D3       net (fanout=9)        1.557   tx_dvi/enc1/st0_qm_r<4>
    SLICE_X5Y18.D        Tilo                  0.259   lut11662_571
                                                       lut11662_571
    SLICE_X6Y21.B3       net (fanout=7)        0.896   lut11662_571
    SLICE_X6Y21.B        Tilo                  0.254   lut11668_578
                                                       lut11666_576
    SLICE_X6Y21.C4       net (fanout=7)        0.335   lut11666_576
    SLICE_X6Y21.C        Tilo                  0.255   lut11668_578
                                                       lut11669_605
    SLICE_X12Y18.B3      net (fanout=11)       1.416   lut11669_605
    SLICE_X12Y18.B       Tilo                  0.235   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X12Y18.D1      net (fanout=24)       0.552   tx_dvi/enc1/st1_case_cnt_eq
    SLICE_X12Y18.CMUX    Topdc                 0.402   tx_dvi/enc1/st1_case_cnt_eq
                                                       tx_dvi/enc1/Mmux_st1_cnt_w62_F
                                                       tx_dvi/enc1/Mmux_st1_cnt_w62
    SLICE_X6Y18.D5       net (fanout=2)        1.214   tx_dvi/enc1/Mmux_st1_cnt_w61
    SLICE_X6Y18.CLK      Tas                   0.449   tx_dvi/enc1/st1_cnt_r<2>
                                                       tx_dvi/enc1/Mmux_st1_cnt_w64_F
                                                       tx_dvi/enc1/Mmux_st1_cnt_w64
                                                       tx_dvi/enc1/st1_cnt_r_2
    -------------------------------------------------  ---------------------------
    Total                                      8.349ns (2.379ns logic, 5.970ns route)
                                                       (28.5% logic, 71.5% route)

--------------------------------------------------------------------------------

Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        "clk_wiz_v1_6_50x62x312_clkout0" TS_xtalclk / 1.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point tx_dvi/ch2_enc_r_6 (SLICE_X20Y8.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.381ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/enc2/st1_qm_r_6 (FF)
  Destination:          tx_dvi/ch2_enc_r_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.383ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.031 - 0.029)
  Source Clock:         CLK63 rising at 16.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: tx_dvi/enc2/st1_qm_r_6 to tx_dvi/ch2_enc_r_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X21Y8.CQ       Tcko                  0.198   tx_dvi/ch2_enc<7>
                                                       tx_dvi/enc2/st1_qm_r_6
    SLICE_X20Y8.CX       net (fanout=1)        0.137   tx_dvi/ch2_enc<6>
    SLICE_X20Y8.CLK      Tckdi       (-Th)    -0.048   tx_dvi/ch2_enc_r<7>
                                                       tx_dvi/ch2_enc_r_6
    -------------------------------------------------  ---------------------------
    Total                                      0.383ns (0.246ns logic, 0.137ns route)
                                                       (64.2% logic, 35.8% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/ch0_enc_r_6 (SLICE_X20Y19.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.381ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/enc0/st1_qm_r_6 (FF)
  Destination:          tx_dvi/ch0_enc_r_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.383ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.041 - 0.039)
  Source Clock:         CLK63 rising at 16.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: tx_dvi/enc0/st1_qm_r_6 to tx_dvi/ch0_enc_r_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X21Y19.CQ      Tcko                  0.198   tx_dvi/ch0_enc<7>
                                                       tx_dvi/enc0/st1_qm_r_6
    SLICE_X20Y19.CX      net (fanout=1)        0.137   tx_dvi/ch0_enc<6>
    SLICE_X20Y19.CLK     Tckdi       (-Th)    -0.048   tx_dvi/ch0_enc_r<7>
                                                       tx_dvi/ch0_enc_r_6
    -------------------------------------------------  ---------------------------
    Total                                      0.383ns (0.246ns logic, 0.137ns route)
                                                       (64.2% logic, 35.8% route)

--------------------------------------------------------------------------------

Paths for end point tx_dvi/ch1_enc_r_2 (SLICE_X28Y11.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.381ns (requirement - (clock path skew + uncertainty - data path))
  Source:               tx_dvi/enc1/st1_qm_r_2 (FF)
  Destination:          tx_dvi/ch1_enc_r_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.383ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.039 - 0.037)
  Source Clock:         CLK63 rising at 16.000ns
  Destination Clock:    CLK63 rising at 16.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: tx_dvi/enc1/st1_qm_r_2 to tx_dvi/ch1_enc_r_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X29Y11.CQ      Tcko                  0.198   tx_dvi/ch1_enc<3>
                                                       tx_dvi/enc1/st1_qm_r_2
    SLICE_X28Y11.CX      net (fanout=1)        0.137   tx_dvi/ch1_enc<2>
    SLICE_X28Y11.CLK     Tckdi       (-Th)    -0.048   tx_dvi/ch1_enc_r<3>
                                                       tx_dvi/ch1_enc_r_2
    -------------------------------------------------  ---------------------------
    Total                                      0.383ns (0.246ns logic, 0.137ns route)
                                                       (64.2% logic, 35.8% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        "clk_wiz_v1_6_50x62x312_clkout0" TS_xtalclk / 1.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 12.430ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  Logical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  Location pin: RAMB16_X0Y20.CLKB
  Clock network: CLK63
--------------------------------------------------------------------------------
Slack: 12.430ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  Logical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  Location pin: RAMB16_X0Y18.CLKB
  Clock network: CLK63
--------------------------------------------------------------------------------
Slack: 13.730ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: clk_wiz_v1_6_50x62x312/clkout1_buf/I0
  Logical resource: clk_wiz_v1_6_50x62x312/clkout1_buf/I0
  Location pin: BUFGMUX_X3Y5.I0
  Clock network: clk_wiz_v1_6_50x62x312/clkout0
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP "GTPCLKOUT1_DCM" 
TS_GTPCLKOUT1_0_ HIGH 50%;

 12309 paths analyzed, 6683 endpoints analyzed, 0 failing endpoints
 1 timing error detected. (0 setup errors, 0 hold errors, 1 component switching limit error)
 Minimum period is   6.400ns.
--------------------------------------------------------------------------------

Paths for end point crtc2/crtc_data_dl2_r_22_BRB3 (SLICE_X18Y44.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.052ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_crtc/disp_dclk_sync_r (FF)
  Destination:          crtc2/crtc_data_dl2_r_22_BRB3 (FF)
  Requirement:          6.172ns
  Data Path Delay:      6.053ns (Levels of Logic = 1)
  Clock Path Skew:      -0.032ns (0.603 - 0.635)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.172ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_crtc/disp_dclk_sync_r to crtc2/crtc_data_dl2_r_22_BRB3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y74.BQ      Tcko                  0.476   TX2_CLK
                                                       dp_main/dp_main_crtc/disp_dclk_sync_r
    SLICE_X19Y52.D6      net (fanout=95)       3.364   TX2_CLK
    SLICE_X19Y52.D       Tilo                  0.259   crtc2/crtc_ctrl_dl1_r<2>
                                                       lut6584_958
    SLICE_X18Y44.CE      net (fanout=10)       1.641   lut6584_958
    SLICE_X18Y44.CLK     Tceck                 0.313   crtc2/crtc_data_dl2_r_19_BRB3
                                                       crtc2/crtc_data_dl2_r_22_BRB3
    -------------------------------------------------  ---------------------------
    Total                                      6.053ns (1.048ns logic, 5.005ns route)
                                                       (17.3% logic, 82.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.576ns (requirement - (data path - clock path skew + uncertainty))
  Source:               crtc2/crtc_cclk_r (FF)
  Destination:          crtc2/crtc_data_dl2_r_22_BRB3 (FF)
  Requirement:          6.172ns
  Data Path Delay:      3.512ns (Levels of Logic = 1)
  Clock Path Skew:      -0.049ns (0.511 - 0.560)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.172ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: crtc2/crtc_cclk_r to crtc2/crtc_data_dl2_r_22_BRB3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y52.DQ      Tcko                  0.430   crtc2/crtc_cclk_r
                                                       crtc2/crtc_cclk_r
    SLICE_X19Y52.D5      net (fanout=13)       0.869   crtc2/crtc_cclk_r
    SLICE_X19Y52.D       Tilo                  0.259   crtc2/crtc_ctrl_dl1_r<2>
                                                       lut6584_958
    SLICE_X18Y44.CE      net (fanout=10)       1.641   lut6584_958
    SLICE_X18Y44.CLK     Tceck                 0.313   crtc2/crtc_data_dl2_r_19_BRB3
                                                       crtc2/crtc_data_dl2_r_22_BRB3
    -------------------------------------------------  ---------------------------
    Total                                      3.512ns (1.002ns logic, 2.510ns route)
                                                       (28.5% logic, 71.5% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_tbc/tbc_data00_out_r_48 (SLICE_X44Y81.D4), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.070ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_tbc/tbc_data_req_r (FF)
  Destination:          dp_main/dp_main_tbc/tbc_data00_out_r_48 (FF)
  Requirement:          6.172ns
  Data Path Delay:      6.017ns (Levels of Logic = 1)
  Clock Path Skew:      -0.050ns (0.583 - 0.633)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.172ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_tbc/tbc_data_req_r to dp_main/dp_main_tbc/tbc_data00_out_r_48
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X38Y54.CQ      Tcko                  0.525   dp_main/dp_main_tbc/tbc_data_req_r
                                                       dp_main/dp_main_tbc/tbc_data_req_r
    SLICE_X44Y81.D4      net (fanout=338)      5.153   dp_main/dp_main_tbc/tbc_data_req_r
    SLICE_X44Y81.CLK     Tas                   0.339   dp_main/dp_main_tbc/tbc_data00_out_r<48>
                                                       lut20746_3717
                                                       dp_main/dp_main_tbc/tbc_data00_out_r_48
    -------------------------------------------------  ---------------------------
    Total                                      6.017ns (0.864ns logic, 5.153ns route)
                                                       (14.4% logic, 85.6% route)

--------------------------------------------------------------------------------

Paths for end point crtc2/crtc_data_dl2_r_18_BRB3 (SLICE_X18Y44.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.077ns (requirement - (data path - clock path skew + uncertainty))
  Source:               dp_main/dp_main_crtc/disp_dclk_sync_r (FF)
  Destination:          crtc2/crtc_data_dl2_r_18_BRB3 (FF)
  Requirement:          6.172ns
  Data Path Delay:      6.028ns (Levels of Logic = 1)
  Clock Path Skew:      -0.032ns (0.603 - 0.635)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.172ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: dp_main/dp_main_crtc/disp_dclk_sync_r to crtc2/crtc_data_dl2_r_18_BRB3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y74.BQ      Tcko                  0.476   TX2_CLK
                                                       dp_main/dp_main_crtc/disp_dclk_sync_r
    SLICE_X19Y52.D6      net (fanout=95)       3.364   TX2_CLK
    SLICE_X19Y52.D       Tilo                  0.259   crtc2/crtc_ctrl_dl1_r<2>
                                                       lut6584_958
    SLICE_X18Y44.CE      net (fanout=10)       1.641   lut6584_958
    SLICE_X18Y44.CLK     Tceck                 0.288   crtc2/crtc_data_dl2_r_19_BRB3
                                                       crtc2/crtc_data_dl2_r_18_BRB3
    -------------------------------------------------  ---------------------------
    Total                                      6.028ns (1.023ns logic, 5.005ns route)
                                                       (17.0% logic, 83.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.601ns (requirement - (data path - clock path skew + uncertainty))
  Source:               crtc2/crtc_cclk_r (FF)
  Destination:          crtc2/crtc_data_dl2_r_18_BRB3 (FF)
  Requirement:          6.172ns
  Data Path Delay:      3.487ns (Levels of Logic = 1)
  Clock Path Skew:      -0.049ns (0.511 - 0.560)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.172ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: crtc2/crtc_cclk_r to crtc2/crtc_data_dl2_r_18_BRB3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y52.DQ      Tcko                  0.430   crtc2/crtc_cclk_r
                                                       crtc2/crtc_cclk_r
    SLICE_X19Y52.D5      net (fanout=13)       0.869   crtc2/crtc_cclk_r
    SLICE_X19Y52.D       Tilo                  0.259   crtc2/crtc_ctrl_dl1_r<2>
                                                       lut6584_958
    SLICE_X18Y44.CE      net (fanout=10)       1.641   lut6584_958
    SLICE_X18Y44.CLK     Tceck                 0.288   crtc2/crtc_data_dl2_r_19_BRB3
                                                       crtc2/crtc_data_dl2_r_18_BRB3
    -------------------------------------------------  ---------------------------
    Total                                      3.487ns (0.977ns logic, 2.510ns route)
                                                       (28.0% logic, 72.0% route)

--------------------------------------------------------------------------------

Hold Paths: TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP "GTPCLKOUT1_DCM" TS_GTPCLKOUT1_0_ HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y22.DIA0), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.295ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_tbc/tx_data00_in_r_0 (FF)
  Destination:          dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.298ns (Levels of Logic = 0)
  Clock Path Skew:      0.003ns (0.077 - 0.074)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.172ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_tbc/tx_data00_in_r_0 to dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y45.AQ      Tcko                  0.200   dp_main/dp_main_tbc/tx_data00_in_r<3>
                                                       dp_main/dp_main_tbc/tx_data00_in_r_0
    RAMB16_X2Y22.DIA0    net (fanout=1)        0.151   dp_main/dp_main_tbc/tx_data00_in_r<0>
    RAMB16_X2Y22.CLKA    Trckd_DIA   (-Th)     0.053   dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.298ns (0.147ns logic, 0.151ns route)
                                                       (49.3% logic, 50.7% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y22.DIA23), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.295ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_tbc/tx_data01_in_r_1 (FF)
  Destination:          dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.296ns (Levels of Logic = 0)
  Clock Path Skew:      0.001ns (0.077 - 0.076)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.172ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_tbc/tx_data01_in_r_1 to dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y47.BQ      Tcko                  0.198   dp_main/dp_main_tbc/tx_data01_in_r<3>
                                                       dp_main/dp_main_tbc/tx_data01_in_r_1
    RAMB16_X2Y22.DIA23   net (fanout=1)        0.151   dp_main/dp_main_tbc/tx_data01_in_r<1>
    RAMB16_X2Y22.CLKA    Trckd_DIA   (-Th)     0.053   dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.296ns (0.145ns logic, 0.151ns route)
                                                       (49.0% logic, 51.0% route)

--------------------------------------------------------------------------------

Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X3Y26.DIA23), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.298ns (requirement - (clock path skew + uncertainty - data path))
  Source:               dp_main/dp_main_tbc/tx_data02_in_r_13 (FF)
  Destination:          dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.304ns (Levels of Logic = 0)
  Clock Path Skew:      0.006ns (0.069 - 0.063)
  Source Clock:         GTPCLKOUT1_DCMx1 rising at 0.000ns
  Destination Clock:    GTPCLKOUT1_DCMx1 rising at 6.172ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: dp_main/dp_main_tbc/tx_data02_in_r_13 to dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X53Y54.BQ      Tcko                  0.198   dp_main/dp_main_tbc/tx_data02_in_r<15>
                                                       dp_main/dp_main_tbc/tx_data02_in_r_13
    RAMB16_X3Y26.DIA23   net (fanout=1)        0.159   dp_main/dp_main_tbc/tx_data02_in_r<13>
    RAMB16_X3Y26.CLKA    Trckd_DIA   (-Th)     0.053   dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.304ns (0.145ns logic, 0.159ns route)
                                                       (47.7% logic, 52.3% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP "GTPCLKOUT1_DCM" TS_GTPCLKOUT1_0_ HIGH 50%;
--------------------------------------------------------------------------------
Slack: -0.228ns (period - min period limit)
  Period: 6.172ns
  Min period limit: 6.400ns (156.250MHz) (Tgtpcper_TXUSRCLK)
  Physical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21
  Logical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21
  Location pin: GTPA1_DUAL_X1Y0.TXUSRCLK21
  Clock network: GTPCLKOUT1_DCMx1
--------------------------------------------------------------------------------
Slack: 2.602ns (period - min period limit)
  Period: 6.172ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X3Y24.CLKA
  Clock network: GTPCLKOUT1_DCMx1
--------------------------------------------------------------------------------
Slack: 2.602ns (period - min period limit)
  Period: 6.172ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  Logical resource: dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  Location pin: RAMB16_X3Y24.CLKB
  Clock network: GTPCLKOUT1_DCMx1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_inst_sp6wrap_eptest_i_gt_refclk_buf = PERIOD TIMEGRP      
   "inst_sp6wrap_eptest_i_gt_refclk_buf"         
TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   3.334ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_gt_refclk_buf = PERIOD TIMEGRP
        "inst_sp6wrap_eptest_i_gt_refclk_buf"
        TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.249ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKOUT0
  Logical resource: inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKOUT0
  Location pin: PLL_ADV_X0Y2.CLKOUT0
  Clock network: inst_sp6wrap/eptest_i/clk_250
--------------------------------------------------------------------------------
Slack: 4.666ns (period - (min low pulse limit / (low pulse / period)))
  Period: 8.000ns
  Low pulse: 4.000ns
  Low pulse limit: 1.667ns (Tdcmpw_CLKIN_100_150)
  Physical resource: inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1
  Logical resource: inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y2.CLKIN1
  Clock network: inst_sp6wrap/eptest_i/gt_refclk_buf
--------------------------------------------------------------------------------
Slack: 4.666ns (period - (min high pulse limit / (high pulse / period)))
  Period: 8.000ns
  High pulse: 4.000ns
  High pulse limit: 1.667ns (Tdcmpw_CLKIN_100_150)
  Physical resource: inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1
  Logical resource: inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y2.CLKIN1
  Clock network: inst_sp6wrap/eptest_i/gt_refclk_buf
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_ctm_27x162_clkfx = PERIOD TIMEGRP "ctm_27x162_clkfx" 
TS_DP_CLK1 * 6 HIGH         50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   3.200ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_ctm_27x162_clkfx = PERIOD TIMEGRP "ctm_27x162_clkfx" TS_DP_CLK1 * 6 HIGH
        50%;
--------------------------------------------------------------------------------
Slack: 2.972ns (period - min period limit)
  Period: 6.172ns
  Min period limit: 3.200ns (312.500MHz) (Tgtpcper_GCLK)
  Physical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01
  Logical resource: xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01
  Location pin: GTPA1_DUAL_X1Y0.GCLK01
  Clock network: PLL162
--------------------------------------------------------------------------------
Slack: 3.902ns (period - min period limit)
  Period: 6.172ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: ctm_27x162/clkout1_buf/I0
  Logical resource: ctm_27x162/clkout1_buf/I0
  Location pin: BUFGMUX_X2Y11.I0
  Clock network: ctm_27x162/clkfx
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD 
TIMEGRP         "memc3_infrastructure_inst_mcb_drp_clk_bufg_in" TS_SYS_CLK3 / 
0.25         HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.270ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD TIMEGRP
        "memc3_infrastructure_inst_mcb_drp_clk_bufg_in" TS_SYS_CLK3 / 0.25
        HIGH 50%;
--------------------------------------------------------------------------------
Slack: 17.730ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Logical resource: memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Location pin: BUFGMUX_X3Y8.I0
  Clock network: memc3_infrastructure_inst/mcb_drp_clk_bufg_in
--------------------------------------------------------------------------------
Slack: 18.601ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1/CLK
  Logical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2/CLK
  Location pin: SLICE_X26Y83.CLK
  Clock network: c3_mcb_drp_clk
--------------------------------------------------------------------------------
Slack: 19.000ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 1.000ns (1000.000MHz) (Tmcbcper_UICLK)
  Physical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Logical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Location pin: MCB_X0Y1.UICLK
  Clock network: c3_mcb_drp_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP     
    "memc3_infrastructure_inst_clk_2x_180" TS_SYS_CLK3 / 2 PHASE 1.25 ns        
 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP
        "memc3_infrastructure_inst_clk_2x_180" TS_SYS_CLK3 / 2 PHASE 1.25 ns
        HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.001ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Logical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Location pin: MCB_X0Y1.PLLCLK1
  Clock network: c3_sysclk_2x_180
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP       
  "memc3_infrastructure_inst_clk_2x_0" TS_SYS_CLK3 / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP
        "memc3_infrastructure_inst_clk_2x_0" TS_SYS_CLK3 / 2 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.001ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Logical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Location pin: MCB_X0Y1.PLLCLK0
  Clock network: c3_sysclk_2x
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP   
      "memc3_infrastructure_inst_clk0_bufg_in" TS_SYS_CLK3 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   3.570ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP
        "memc3_infrastructure_inst_clk0_bufg_in" TS_SYS_CLK3 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X0Y20.CLKA
  Clock network: c3_clk0
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X0Y18.CLKA
  Clock network: c3_clk0
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X0Y24.CLKA
  Clock network: c3_clk0
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD 
TIMEGRP         "memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0"         
TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;

 30415 paths analyzed, 1292 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  13.340ns.
--------------------------------------------------------------------------------

Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15 (SLICE_X38Y85.SR), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.665ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_infrastructure_inst/powerup_pll_locked (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15 (FF)
  Requirement:          5.000ns
  Data Path Delay:      2.950ns (Levels of Logic = 1)
  Clock Path Skew:      -0.171ns (2.052 - 2.223)
  Source Clock:         c3_clk0 rising at 15.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.214ns

  Clock Uncertainty:          0.214ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.174ns
    Phase Error (PE):           0.120ns

  Maximum Data Path at Slow Process Corner: memc3_infrastructure_inst/powerup_pll_locked to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y83.AQ      Tcko                  0.476   memc3_infrastructure_inst/powerup_pll_locked
                                                       memc3_infrastructure_inst/powerup_pll_locked
    SLICE_X27Y83.B5      net (fanout=4)        0.448   memc3_infrastructure_inst/powerup_pll_locked
    SLICE_X27Y83.B       Tilo                  0.259   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1
    SLICE_X38Y85.SR      net (fanout=16)       1.546   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0
    SLICE_X38Y85.CLK     Trck                  0.221   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor<15>_rt
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15
    -------------------------------------------------  ---------------------------
    Total                                      2.950ns (0.956ns logic, 1.994ns route)
                                                       (32.4% logic, 67.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     16.586ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15 (FF)
  Requirement:          20.000ns
  Data Path Delay:      3.266ns (Levels of Logic = 1)
  Clock Path Skew:      -0.054ns (0.485 - 0.539)
  Source Clock:         c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.094ns

  Clock Uncertainty:          0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.174ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y82.AQ      Tcko                  0.476   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X27Y83.B1      net (fanout=4)        0.764   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X27Y83.B       Tilo                  0.259   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1
    SLICE_X38Y85.SR      net (fanout=16)       1.546   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0
    SLICE_X38Y85.CLK     Trck                  0.221   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor<15>_rt
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15
    -------------------------------------------------  ---------------------------
    Total                                      3.266ns (0.956ns logic, 2.310ns route)
                                                       (29.3% logic, 70.7% route)

--------------------------------------------------------------------------------

Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14 (SLICE_X38Y85.SR), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.674ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_infrastructure_inst/powerup_pll_locked (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14 (FF)
  Requirement:          5.000ns
  Data Path Delay:      2.941ns (Levels of Logic = 1)
  Clock Path Skew:      -0.171ns (2.052 - 2.223)
  Source Clock:         c3_clk0 rising at 15.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.214ns

  Clock Uncertainty:          0.214ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.174ns
    Phase Error (PE):           0.120ns

  Maximum Data Path at Slow Process Corner: memc3_infrastructure_inst/powerup_pll_locked to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y83.AQ      Tcko                  0.476   memc3_infrastructure_inst/powerup_pll_locked
                                                       memc3_infrastructure_inst/powerup_pll_locked
    SLICE_X27Y83.B5      net (fanout=4)        0.448   memc3_infrastructure_inst/powerup_pll_locked
    SLICE_X27Y83.B       Tilo                  0.259   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1
    SLICE_X38Y85.SR      net (fanout=16)       1.546   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0
    SLICE_X38Y85.CLK     Trck                  0.212   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor<15>_rt
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14
    -------------------------------------------------  ---------------------------
    Total                                      2.941ns (0.947ns logic, 1.994ns route)
                                                       (32.2% logic, 67.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     16.595ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14 (FF)
  Requirement:          20.000ns
  Data Path Delay:      3.257ns (Levels of Logic = 1)
  Clock Path Skew:      -0.054ns (0.485 - 0.539)
  Source Clock:         c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.094ns

  Clock Uncertainty:          0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.174ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y82.AQ      Tcko                  0.476   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X27Y83.B1      net (fanout=4)        0.764   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X27Y83.B       Tilo                  0.259   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1
    SLICE_X38Y85.SR      net (fanout=16)       1.546   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0
    SLICE_X38Y85.CLK     Trck                  0.212   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor<15>_rt
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14
    -------------------------------------------------  ---------------------------
    Total                                      3.257ns (0.947ns logic, 2.310ns route)
                                                       (29.1% logic, 70.9% route)

--------------------------------------------------------------------------------

Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13 (SLICE_X38Y85.SR), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.685ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_infrastructure_inst/powerup_pll_locked (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13 (FF)
  Requirement:          5.000ns
  Data Path Delay:      2.930ns (Levels of Logic = 1)
  Clock Path Skew:      -0.171ns (2.052 - 2.223)
  Source Clock:         c3_clk0 rising at 15.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.214ns

  Clock Uncertainty:          0.214ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.174ns
    Phase Error (PE):           0.120ns

  Maximum Data Path at Slow Process Corner: memc3_infrastructure_inst/powerup_pll_locked to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y83.AQ      Tcko                  0.476   memc3_infrastructure_inst/powerup_pll_locked
                                                       memc3_infrastructure_inst/powerup_pll_locked
    SLICE_X27Y83.B5      net (fanout=4)        0.448   memc3_infrastructure_inst/powerup_pll_locked
    SLICE_X27Y83.B       Tilo                  0.259   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1
    SLICE_X38Y85.SR      net (fanout=16)       1.546   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0
    SLICE_X38Y85.CLK     Trck                  0.201   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor<15>_rt
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13
    -------------------------------------------------  ---------------------------
    Total                                      2.930ns (0.936ns logic, 1.994ns route)
                                                       (31.9% logic, 68.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     16.606ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13 (FF)
  Requirement:          20.000ns
  Data Path Delay:      3.246ns (Levels of Logic = 1)
  Clock Path Skew:      -0.054ns (0.485 - 0.539)
  Source Clock:         c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.094ns

  Clock Uncertainty:          0.094ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.174ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y82.AQ      Tcko                  0.476   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X27Y83.B1      net (fanout=4)        0.764   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock
    SLICE_X27Y83.B       Tilo                  0.259   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1
    SLICE_X38Y85.SR      net (fanout=16)       1.546   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0
    SLICE_X38Y85.CLK     Trck                  0.201   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor<15>_rt
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13
    -------------------------------------------------  ---------------------------
    Total                                      3.246ns (0.936ns logic, 2.310ns route)
                                                       (28.8% logic, 71.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP
        "memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0"
        TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3 (SLICE_X10Y41.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.414ns (requirement - (clock path skew + uncertainty - data path))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd5 (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.416ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.033 - 0.031)
  Source Clock:         c3_mcb_drp_clk rising at 20.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd5 to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y41.AQ      Tcko                  0.198   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3-In
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd5
    SLICE_X10Y41.AX      net (fanout=2)        0.177   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3-In
    SLICE_X10Y41.CLK     Tckdi       (-Th)    -0.041   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd2-In
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3
    -------------------------------------------------  ---------------------------
    Total                                      0.416ns (0.239ns logic, 0.177ns route)
                                                       (57.5% logic, 42.5% route)

--------------------------------------------------------------------------------

Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9 (SLICE_X40Y82.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.414ns (requirement - (clock path skew + uncertainty - data path))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9 (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.414ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         c3_mcb_drp_clk rising at 20.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9 to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y82.AQ      Tcko                  0.200   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter<9>
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9
    SLICE_X40Y82.A6      net (fanout=3)        0.024   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter<9>
    SLICE_X40Y82.CLK     Tah         (-Th)    -0.190   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter<9>
                                                       lut31066_6707
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9
    -------------------------------------------------  ---------------------------
    Total                                      0.414ns (0.390ns logic, 0.024ns route)
                                                       (94.2% logic, 5.8% route)

--------------------------------------------------------------------------------

Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN (SLICE_X4Y56.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.418ns (requirement - (clock path skew + uncertainty - data path))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN (FF)
  Destination:          memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.418ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         c3_mcb_drp_clk rising at 20.000ns
  Destination Clock:    c3_mcb_drp_clk rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN to memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X4Y56.AQ       Tcko                  0.200   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/mcb_ui_cmd_en
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
    SLICE_X4Y56.A6       net (fanout=2)        0.028   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/mcb_ui_cmd_en
    SLICE_X4Y56.CLK      Tah         (-Th)    -0.190   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/mcb_ui_cmd_en
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN_rstpot
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
    -------------------------------------------------  ---------------------------
    Total                                      0.418ns (0.390ns logic, 0.028ns route)
                                                       (93.3% logic, 6.7% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP
        "memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0"
        TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 17.730ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Logical resource: memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Location pin: BUFGMUX_X3Y8.I0
  Clock network: memc3_infrastructure_inst/mcb_drp_clk_bufg_in
--------------------------------------------------------------------------------
Slack: 18.601ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1/CLK
  Logical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2/CLK
  Location pin: SLICE_X26Y83.CLK
  Clock network: c3_mcb_drp_clk
--------------------------------------------------------------------------------
Slack: 19.000ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 1.000ns (1000.000MHz) (Tmcbcper_UICLK)
  Physical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Logical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Location pin: MCB_X0Y1.UICLK
  Clock network: c3_mcb_drp_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_memc3_infrastructure_inst_clk_2x_180_0 = PERIOD TIMEGRP   
      "memc3_infrastructure_inst_clk_2x_180_0" TS_clk_wiz_v1_6_50x200_clkfx     
    / 2 PHASE 1.25 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_180_0 = PERIOD TIMEGRP
        "memc3_infrastructure_inst_clk_2x_180_0" TS_clk_wiz_v1_6_50x200_clkfx
        / 2 PHASE 1.25 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.001ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Logical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Location pin: MCB_X0Y1.PLLCLK1
  Clock network: c3_sysclk_2x_180
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_memc3_infrastructure_inst_clk_2x_0_0 = PERIOD TIMEGRP     
    "memc3_infrastructure_inst_clk_2x_0_0" TS_clk_wiz_v1_6_50x200_clkfx /       
  2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_0_0 = PERIOD TIMEGRP
        "memc3_infrastructure_inst_clk_2x_0_0" TS_clk_wiz_v1_6_50x200_clkfx /
        2 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.001ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Logical resource: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Location pin: MCB_X0Y1.PLLCLK0
  Clock network: c3_sysclk_2x
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP 
        "memc3_infrastructure_inst_clk0_bufg_in_0"         
TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;

 947 paths analyzed, 573 endpoints analyzed, 14 failing endpoints
 14 timing errors detected. (0 setup errors, 14 hold errors, 0 component switching limit errors)
 Minimum period is   4.927ns.
--------------------------------------------------------------------------------

Paths for end point crtc2/fsmfake4_0 (SLICE_X0Y43.A6), 4 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.073ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (CPU)
  Destination:          crtc2/fsmfake4_0 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.801ns (Levels of Logic = 2)
  Clock Path Skew:      -0.051ns (0.602 - 0.653)
  Source Clock:         c3_clk0 rising at 0.000ns
  Destination Clock:    c3_clk0 rising at 5.000ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 to crtc2/fsmfake4_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    MCB_X0Y1.P5CMDEMPTY  Tmcbcko_CMDEMPTY      1.080   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
    SLICE_X0Y49.A4       net (fanout=3)        2.553   c3_p5_cmd_empty
    SLICE_X0Y49.A        Tilo                  0.235   lut9907_1662
                                                       lut7295_1177
    SLICE_X0Y43.A6       net (fanout=1)        0.584   lut7295_1177
    SLICE_X0Y43.CLK      Tas                   0.349   crtc2/mem_state_r_FSM_FFd22
                                                       ][6794_1180
                                                       crtc2/fsmfake4_0
    -------------------------------------------------  ---------------------------
    Total                                      4.801ns (1.664ns logic, 3.137ns route)
                                                       (34.7% logic, 65.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.765ns (requirement - (data path - clock path skew + uncertainty))
  Source:               crtc2/fsmfake4_1 (FF)
  Destination:          crtc2/fsmfake4_0 (FF)
  Requirement:          5.000ns
  Data Path Delay:      3.156ns (Levels of Logic = 2)
  Clock Path Skew:      -0.004ns (0.162 - 0.166)
  Source Clock:         c3_clk0 rising at 0.000ns
  Destination Clock:    c3_clk0 rising at 5.000ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: crtc2/fsmfake4_1 to crtc2/fsmfake4_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y41.CQ       Tcko                  0.476   crtc2/fsmfake4<1>
                                                       crtc2/fsmfake4_1
    SLICE_X0Y49.A1       net (fanout=9)        1.512   crtc2/fsmfake4<1>
    SLICE_X0Y49.A        Tilo                  0.235   lut9907_1662
                                                       lut7295_1177
    SLICE_X0Y43.A6       net (fanout=1)        0.584   lut7295_1177
    SLICE_X0Y43.CLK      Tas                   0.349   crtc2/mem_state_r_FSM_FFd22
                                                       ][6794_1180
                                                       crtc2/fsmfake4_0
    -------------------------------------------------  ---------------------------
    Total                                      3.156ns (1.060ns logic, 2.096ns route)
                                                       (33.6% logic, 66.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.233ns (requirement - (data path - clock path skew + uncertainty))
  Source:               crtc2/fsmfake4_0 (FF)
  Destination:          crtc2/fsmfake4_0 (FF)
  Requirement:          5.000ns
  Data Path Delay:      2.692ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         c3_clk0 rising at 0.000ns
  Destination Clock:    c3_clk0 rising at 5.000ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: crtc2/fsmfake4_0 to crtc2/fsmfake4_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y43.AQ       Tcko                  0.476   crtc2/mem_state_r_FSM_FFd22
                                                       crtc2/fsmfake4_0
    SLICE_X0Y49.A5       net (fanout=10)       1.048   crtc2/fsmfake4<0>
    SLICE_X0Y49.A        Tilo                  0.235   lut9907_1662
                                                       lut7295_1177
    SLICE_X0Y43.A6       net (fanout=1)        0.584   lut7295_1177
    SLICE_X0Y43.CLK      Tas                   0.349   crtc2/mem_state_r_FSM_FFd22
                                                       ][6794_1180
                                                       crtc2/fsmfake4_0
    -------------------------------------------------  ---------------------------
    Total                                      2.692ns (1.060ns logic, 1.632ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------

Paths for end point crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X0Y24.DIA7), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.121ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (CPU)
  Destination:          crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          5.000ns
  Data Path Delay:      4.814ns (Levels of Logic = 0)
  Clock Path Skew:      0.010ns (0.538 - 0.528)
  Source Clock:         c3_clk0 rising at 0.000ns
  Destination Clock:    c3_clk0 rising at 5.000ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 to crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    MCB_X0Y1.P5RDDATA7   Tmcbcko_RDDATA        2.700   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
    RAMB16_X0Y24.DIA7    net (fanout=1)        1.814   c3_p5_rd_data<7>
    RAMB16_X0Y24.CLKA    Trdck_DIA             0.300   crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      4.814ns (3.000ns logic, 1.814ns route)
                                                       (62.3% logic, 37.7% route)

--------------------------------------------------------------------------------

Paths for end point crtc2/mem_state_r_FSM_FFd3_1 (SLICE_X1Y43.AX), 9 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.126ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (CPU)
  Destination:          crtc2/mem_state_r_FSM_FFd3_1 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.793ns (Levels of Logic = 2)
  Clock Path Skew:      -0.006ns (0.252 - 0.258)
  Source Clock:         c3_clk0 rising at 0.000ns
  Destination Clock:    c3_clk0 rising at 5.000ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 to crtc2/mem_state_r_FSM_FFd3_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    MCB_X0Y1.P5EMPTY     Tmcbcko_EMPTY         2.270   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
    SLICE_X1Y43.B4       net (fanout=8)        0.954   c3_p5_rd_empty
    SLICE_X1Y43.B        Tilo                  0.259   crtc2/mem_state_r_FSM_FFd3
                                                       lut7021_1117
    SLICE_X1Y43.C4       net (fanout=1)        0.312   lut7021_1117
    SLICE_X1Y43.C        Tilo                  0.259   crtc2/mem_state_r_FSM_FFd3
                                                       lut7022_1118
    SLICE_X1Y43.AX       net (fanout=1)        0.625   lut7022_1118
    SLICE_X1Y43.CLK      Tdick                 0.114   crtc2/mem_state_r_FSM_FFd3
                                                       crtc2/mem_state_r_FSM_FFd3_1
    -------------------------------------------------  ---------------------------
    Total                                      4.793ns (2.902ns logic, 1.891ns route)
                                                       (60.5% logic, 39.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.369ns (requirement - (data path - clock path skew + uncertainty))
  Source:               memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (CPU)
  Destination:          crtc2/mem_state_r_FSM_FFd3_1 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.505ns (Levels of Logic = 1)
  Clock Path Skew:      -0.051ns (0.602 - 0.653)
  Source Clock:         c3_clk0 rising at 0.000ns
  Destination Clock:    c3_clk0 rising at 5.000ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 to crtc2/mem_state_r_FSM_FFd3_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    MCB_X0Y1.P5CMDEMPTY  Tmcbcko_CMDEMPTY      1.080   memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
                                                       memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
    SLICE_X1Y43.C6       net (fanout=3)        2.427   c3_p5_cmd_empty
    SLICE_X1Y43.C        Tilo                  0.259   crtc2/mem_state_r_FSM_FFd3
                                                       lut7022_1118
    SLICE_X1Y43.AX       net (fanout=1)        0.625   lut7022_1118
    SLICE_X1Y43.CLK      Tdick                 0.114   crtc2/mem_state_r_FSM_FFd3
                                                       crtc2/mem_state_r_FSM_FFd3_1
    -------------------------------------------------  ---------------------------
    Total                                      4.505ns (1.453ns logic, 3.052ns route)
                                                       (32.3% logic, 67.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.965ns (requirement - (data path - clock path skew + uncertainty))
  Source:               crtc2/mem_init_done_r (FF)
  Destination:          crtc2/mem_state_r_FSM_FFd3_1 (FF)
  Requirement:          5.000ns
  Data Path Delay:      3.906ns (Levels of Logic = 2)
  Clock Path Skew:      -0.054ns (0.510 - 0.564)
  Source Clock:         c3_clk0 rising at 0.000ns
  Destination Clock:    c3_clk0 rising at 5.000ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: crtc2/mem_init_done_r to crtc2/mem_state_r_FSM_FFd3_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y49.CQ      Tcko                  0.525   crtc1/mem_init_done_r
                                                       crtc2/mem_init_done_r
    SLICE_X1Y43.B5       net (fanout=4)        1.812   crtc1/mem_init_done_r
    SLICE_X1Y43.B        Tilo                  0.259   crtc2/mem_state_r_FSM_FFd3
                                                       lut7021_1117
    SLICE_X1Y43.C4       net (fanout=1)        0.312   lut7021_1117
    SLICE_X1Y43.C        Tilo                  0.259   crtc2/mem_state_r_FSM_FFd3
                                                       lut7022_1118
    SLICE_X1Y43.AX       net (fanout=1)        0.625   lut7022_1118
    SLICE_X1Y43.CLK      Tdick                 0.114   crtc2/mem_state_r_FSM_FFd3
                                                       crtc2/mem_state_r_FSM_FFd3_1
    -------------------------------------------------  ---------------------------
    Total                                      3.906ns (1.157ns logic, 2.749ns route)
                                                       (29.6% logic, 70.4% route)

--------------------------------------------------------------------------------

Hold Paths: TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP
        "memc3_infrastructure_inst_clk0_bufg_in_0"
        TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point crtc1/fb_rd_req_r_0 (SLICE_X22Y66.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      -7.234ns (requirement - (clock path skew + uncertainty - data path))
  Source:               crtc1/crtc_rd_reqf_r (FF)
  Destination:          crtc1/fb_rd_req_r_0 (FF)
  Requirement:          1.000ns
  Data Path Delay:      1.053ns (Levels of Logic = 0)
  Clock Path Skew:      8.749ns (10.939 - 2.190)
  Source Clock:         CLK63 rising at 64.000ns
  Destination Clock:    c3_clk0 rising at 65.000ns
  Clock Uncertainty:    0.538ns

  Clock Uncertainty:          0.538ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.419ns
    Phase Error (PE):           0.325ns

  Minimum Data Path at Slow Process Corner: crtc1/crtc_rd_reqf_r to crtc1/fb_rd_req_r_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y66.CQ      Tcko                  0.405   crtc1/crtc_rd_reqf_r
                                                       crtc1/crtc_rd_reqf_r
    SLICE_X22Y66.AX      net (fanout=2)        0.638   crtc1/crtc_rd_reqf_r
    SLICE_X22Y66.CLK     Tckdi       (-Th)    -0.010   crtc1/fb_rd_req_r<3>
                                                       crtc1/fb_rd_req_r_0
    -------------------------------------------------  ---------------------------
    Total                                      1.053ns (0.415ns logic, 0.638ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------

Paths for end point crtc1/fb_rd_addr_r_4 (SLICE_X14Y67.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      -6.829ns (requirement - (clock path skew + uncertainty - data path))
  Source:               crtc1/crtc_rd_vpos_r_4 (FF)
  Destination:          crtc1/fb_rd_addr_r_4 (FF)
  Requirement:          1.000ns
  Data Path Delay:      1.463ns (Levels of Logic = 0)
  Clock Path Skew:      8.754ns (10.936 - 2.182)
  Source Clock:         CLK63 rising at 64.000ns
  Destination Clock:    c3_clk0 rising at 65.000ns
  Clock Uncertainty:    0.538ns

  Clock Uncertainty:          0.538ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.419ns
    Phase Error (PE):           0.325ns

  Minimum Data Path at Slow Process Corner: crtc1/crtc_rd_vpos_r_4 to crtc1/fb_rd_addr_r_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y70.AQ      Tcko                  0.405   crtc1/crtc_rd_vpos_r<7>
                                                       crtc1/crtc_rd_vpos_r_4
    SLICE_X14Y67.AX      net (fanout=1)        1.048   crtc1/crtc_rd_vpos_r<4>
    SLICE_X14Y67.CLK     Tckdi       (-Th)    -0.010   crtc1/fb_rd_addr_r<7>
                                                       crtc1/fb_rd_addr_r_4
    -------------------------------------------------  ---------------------------
    Total                                      1.463ns (0.415ns logic, 1.048ns route)
                                                       (28.4% logic, 71.6% route)

--------------------------------------------------------------------------------

Paths for end point crtc1/fb_rd_addr_r_11 (SLICE_X14Y70.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      -6.773ns (requirement - (clock path skew + uncertainty - data path))
  Source:               crtc1/crtc_rd_vpos_r_11 (FF)
  Destination:          crtc1/fb_rd_addr_r_11 (FF)
  Requirement:          1.000ns
  Data Path Delay:      1.514ns (Levels of Logic = 0)
  Clock Path Skew:      8.749ns (10.929 - 2.180)
  Source Clock:         CLK63 rising at 64.000ns
  Destination Clock:    c3_clk0 rising at 65.000ns
  Clock Uncertainty:    0.538ns

  Clock Uncertainty:          0.538ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.419ns
    Phase Error (PE):           0.325ns

  Minimum Data Path at Slow Process Corner: crtc1/crtc_rd_vpos_r_11 to crtc1/fb_rd_addr_r_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y71.DQ      Tcko                  0.495   crtc1/crtc_rd_vpos_r<11>
                                                       crtc1/crtc_rd_vpos_r_11
    SLICE_X14Y70.DX      net (fanout=1)        1.009   crtc1/crtc_rd_vpos_r<11>
    SLICE_X14Y70.CLK     Tckdi       (-Th)    -0.010   crtc1/fb_rd_addr_r<11>
                                                       crtc1/fb_rd_addr_r_11
    -------------------------------------------------  ---------------------------
    Total                                      1.514ns (0.505ns logic, 1.009ns route)
                                                       (33.4% logic, 66.6% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP
        "memc3_infrastructure_inst_clk0_bufg_in_0"
        TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X0Y20.CLKA
  Clock network: c3_clk0
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X0Y18.CLKA
  Clock network: c3_clk0
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X0Y24.CLKA
  Clock network: c3_clk0
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP         
"inst_sp6wrap_eptest_i_clk_125" TS_inst_sp6wrap_eptest_i_gt_refclk_buf         
/ 1.25 HIGH 50%;

 45 paths analyzed, 45 endpoints analyzed, 0 failing endpoints
 1 timing error detected. (0 setup errors, 0 hold errors, 1 component switching limit error)
 Minimum period is   8.000ns.
--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXCHARISKB0), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.312ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i (HSIO)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          6.400ns
  Data Path Delay:      3.885ns (Levels of Logic = 0)
  Clock Path Skew:      -0.110ns (0.496 - 0.606)
  Source Clock:         inst_sp6wrap/eptest_i/mgt_clk rising at 0.000ns
  Destination Clock:    inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Clock Uncertainty:    0.093ns

  Clock Uncertainty:          0.093ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.172ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i to inst_sp6wrap/eptest_i/PCIE_A1
    Location                    Delay type         Delay(ns)  Physical Resource
                                                              Logical Resource(s)
    --------------------------------------------------------  -------------------
    GTPA1_DUAL_X0Y0.RXCHARISK11 Tgtpcko_RXCHARISK     1.220   inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
                                                              inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
    PCIE_X0Y0.PIPERXCHARISKB0   net (fanout=1)        1.225   inst_sp6wrap/eptest_i/rx_char_is_k<1>
    PCIE_X0Y0.MGTCLK            Tpcicck_MGT           1.440   inst_sp6wrap/eptest_i/PCIE_A1
                                                              inst_sp6wrap/eptest_i/PCIE_A1
    --------------------------------------------------------  ---------------------------
    Total                                             3.885ns (2.660ns logic, 1.225ns route)
                                                              (68.5% logic, 31.5% route)

--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXSTATUSB1), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.354ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i (HSIO)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          6.400ns
  Data Path Delay:      3.843ns (Levels of Logic = 0)
  Clock Path Skew:      -0.110ns (0.496 - 0.606)
  Source Clock:         inst_sp6wrap/eptest_i/mgt_clk rising at 0.000ns
  Destination Clock:    inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Clock Uncertainty:    0.093ns

  Clock Uncertainty:          0.093ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.172ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i to inst_sp6wrap/eptest_i/PCIE_A1
    Location                   Delay type         Delay(ns)  Physical Resource
                                                             Logical Resource(s)
    -------------------------------------------------------  -------------------
    GTPA1_DUAL_X0Y0.RXSTATUS11 Tgtpcko_RXSTATUS      1.220   inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
                                                             inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
    PCIE_X0Y0.PIPERXSTATUSB1   net (fanout=1)        1.183   inst_sp6wrap/eptest_i/rx_status<1>
    PCIE_X0Y0.MGTCLK           Tpcicck_MGT           1.440   inst_sp6wrap/eptest_i/PCIE_A1
                                                             inst_sp6wrap/eptest_i/PCIE_A1
    -------------------------------------------------------  ---------------------------
    Total                                            3.843ns (2.660ns logic, 1.183ns route)
                                                             (69.2% logic, 30.8% route)

--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXSTATUSB2), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     2.423ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i (HSIO)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          6.400ns
  Data Path Delay:      3.774ns (Levels of Logic = 0)
  Clock Path Skew:      -0.110ns (0.496 - 0.606)
  Source Clock:         inst_sp6wrap/eptest_i/mgt_clk rising at 0.000ns
  Destination Clock:    inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Clock Uncertainty:    0.093ns

  Clock Uncertainty:          0.093ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.172ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i to inst_sp6wrap/eptest_i/PCIE_A1
    Location                   Delay type         Delay(ns)  Physical Resource
                                                             Logical Resource(s)
    -------------------------------------------------------  -------------------
    GTPA1_DUAL_X0Y0.RXSTATUS12 Tgtpcko_RXSTATUS      1.220   inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
                                                             inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
    PCIE_X0Y0.PIPERXSTATUSB2   net (fanout=1)        1.114   inst_sp6wrap/eptest_i/rx_status<2>
    PCIE_X0Y0.MGTCLK           Tpcicck_MGT           1.440   inst_sp6wrap/eptest_i/PCIE_A1
                                                             inst_sp6wrap/eptest_i/PCIE_A1
    -------------------------------------------------------  ---------------------------
    Total                                            3.774ns (2.660ns logic, 1.114ns route)
                                                             (70.5% logic, 29.5% route)

--------------------------------------------------------------------------------

Hold Paths: TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP
        "inst_sp6wrap_eptest_i_clk_125" TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 1.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPEPHYSTATUSB), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.129ns (requirement - (clock path skew + uncertainty - data path))
  Source:               inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i (HSIO)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          0.000ns
  Data Path Delay:      0.056ns (Levels of Logic = 0)
  Clock Path Skew:      -0.073ns (0.201 - 0.274)
  Source Clock:         inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Destination Clock:    inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i to inst_sp6wrap/eptest_i/PCIE_A1
    Location                   Delay type         Delay(ns)  Physical Resource
                                                             Logical Resource(s)
    -------------------------------------------------------  -------------------
    GTPA1_DUAL_X0Y0.PHYSTATUS1 Tgtpcko_PHYSTATUS     0.565   inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
                                                             inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
    PCIE_X0Y0.PIPEPHYSTATUSB   net (fanout=1)        0.341   inst_sp6wrap/eptest_i/phystatus
    PCIE_X0Y0.MGTCLK           Tpcickc_MGT (-Th)     0.850   inst_sp6wrap/eptest_i/PCIE_A1
                                                             inst_sp6wrap/eptest_i/PCIE_A1
    -------------------------------------------------------  ---------------------------
    Total                                            0.056ns (-0.285ns logic, 0.341ns route)
                                                             (-508.9% logic, 608.9% route)

--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB0), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.129ns (requirement - (clock path skew + uncertainty - data path))
  Source:               inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i (HSIO)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          0.000ns
  Data Path Delay:      0.056ns (Levels of Logic = 0)
  Clock Path Skew:      -0.073ns (0.201 - 0.274)
  Source Clock:         inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Destination Clock:    inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i to inst_sp6wrap/eptest_i/PCIE_A1
    Location                 Delay type         Delay(ns)  Physical Resource
                                                           Logical Resource(s)
    -----------------------------------------------------  -------------------
    GTPA1_DUAL_X0Y0.RXDATA18 Tgtpcko_RXDATA        0.565   inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
                                                           inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
    PCIE_X0Y0.PIPERXDATAB0   net (fanout=1)        0.341   inst_sp6wrap/eptest_i/rx_data<8>
    PCIE_X0Y0.MGTCLK         Tpcickc_MGT (-Th)     0.850   inst_sp6wrap/eptest_i/PCIE_A1
                                                           inst_sp6wrap/eptest_i/PCIE_A1
    -----------------------------------------------------  ---------------------------
    Total                                          0.056ns (-0.285ns logic, 0.341ns route)
                                                           (-508.9% logic, 608.9% route)

--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB1), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.129ns (requirement - (clock path skew + uncertainty - data path))
  Source:               inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i (HSIO)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          0.000ns
  Data Path Delay:      0.056ns (Levels of Logic = 0)
  Clock Path Skew:      -0.073ns (0.201 - 0.274)
  Source Clock:         inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Destination Clock:    inst_sp6wrap/eptest_i/mgt_clk rising at 6.400ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i to inst_sp6wrap/eptest_i/PCIE_A1
    Location                 Delay type         Delay(ns)  Physical Resource
                                                           Logical Resource(s)
    -----------------------------------------------------  -------------------
    GTPA1_DUAL_X0Y0.RXDATA19 Tgtpcko_RXDATA        0.565   inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
                                                           inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i
    PCIE_X0Y0.PIPERXDATAB1   net (fanout=1)        0.341   inst_sp6wrap/eptest_i/rx_data<9>
    PCIE_X0Y0.MGTCLK         Tpcickc_MGT (-Th)     0.850   inst_sp6wrap/eptest_i/PCIE_A1
                                                           inst_sp6wrap/eptest_i/PCIE_A1
    -----------------------------------------------------  ---------------------------
    Total                                          0.056ns (-0.285ns logic, 0.341ns route)
                                                           (-508.9% logic, 608.9% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP
        "inst_sp6wrap_eptest_i_clk_125" TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 1.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: -1.600ns (period - min period limit)
  Period: 6.400ns
  Min period limit: 8.000ns (125.000MHz) (Tpciper_MGTCLK)
  Physical resource: inst_sp6wrap/eptest_i/PCIE_A1/MGTCLK
  Logical resource: inst_sp6wrap/eptest_i/PCIE_A1/MGTCLK
  Location pin: PCIE_X0Y0.MGTCLK
  Clock network: inst_sp6wrap/eptest_i/mgt_clk
--------------------------------------------------------------------------------
Slack: 0.000ns (period - min period limit)
  Period: 6.400ns
  Min period limit: 6.400ns (156.250MHz) (Tgtpcper_RXUSRCLK)
  Physical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK21
  Logical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK21
  Location pin: GTPA1_DUAL_X0Y0.RXUSRCLK21
  Clock network: inst_sp6wrap/eptest_i/mgt_clk
--------------------------------------------------------------------------------
Slack: 0.000ns (period - min period limit)
  Period: 6.400ns
  Min period limit: 6.400ns (156.250MHz) (Tgtpcper_TXUSRCLK)
  Physical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK21
  Logical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK21
  Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK21
  Clock network: inst_sp6wrap/eptest_i/mgt_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD TIMEGRP         
"inst_sp6wrap_eptest_i_clk_250" TS_inst_sp6wrap_eptest_i_gt_refclk_buf         
/ 2.5 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   3.200ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD TIMEGRP
        "inst_sp6wrap_eptest_i_clk_250" TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 2.5 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.000ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 3.200ns (312.500MHz) (Tgtpcper_RXUSRCLK)
  Physical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK1
  Logical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK1
  Location pin: GTPA1_DUAL_X0Y0.RXUSRCLK1
  Clock network: inst_sp6wrap/eptest_i/mgt_clk_2x
--------------------------------------------------------------------------------
Slack: 0.000ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 3.200ns (312.500MHz) (Tgtpcper_TXUSRCLK)
  Physical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK1
  Logical resource: inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK1
  Location pin: GTPA1_DUAL_X0Y0.TXUSRCLK1
  Clock network: inst_sp6wrap/eptest_i/mgt_clk_2x
--------------------------------------------------------------------------------
Slack: 0.930ns (period - min period limit)
  Period: 3.200ns
  Min period limit: 2.270ns (440.529MHz) (Tbcper_I)
  Physical resource: inst_sp6wrap/eptest_i/mgt2x_bufg/I0
  Logical resource: inst_sp6wrap/eptest_i/mgt2x_bufg/I0
  Location pin: BUFGMUX_X2Y9.I0
  Clock network: inst_sp6wrap/eptest_i/clk_250
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP         
"inst_sp6wrap_eptest_i_clk_62_5"         TS_inst_sp6wrap_eptest_i_gt_refclk_buf 
/ 0.625 HIGH 50%;

 9375 paths analyzed, 3865 endpoints analyzed, 0 failing endpoints
 1 timing error detected. (0 setup errors, 0 hold errors, 1 component switching limit error)
 Minimum period is  16.000ns.
--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/app/mem/mem_wr_data_out2_r_24 (SLICE_X36Y90.A2), 6 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.463ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_24 (FF)
  Requirement:          12.800ns
  Data Path Delay:      11.189ns (Levels of Logic = 3)
  Clock Path Skew:      -0.043ns (0.485 - 0.528)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r to inst_sp6wrap/app/mem/mem_wr_data_out2_r_24
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y98.AQ      Tcko                  0.476   inst_sp6wrap/app/PIO/PIO_EP/EP_RX/tlp_type_iowr_r
                                                       inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r
    SLICE_X3Y72.B4       net (fanout=65)       4.343   GPIO1C_28_OBUF
    SLICE_X3Y72.B        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35998_112
    SLICE_X3Y72.A5       net (fanout=5)        0.231   lut35998_112
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.A2      net (fanout=117)      5.272   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37052_8302
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_24
    -------------------------------------------------  ---------------------------
    Total                                     11.189ns (1.343ns logic, 9.846ns route)
                                                       (12.0% logic, 88.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.663ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3 (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_24 (FF)
  Requirement:          12.800ns
  Data Path Delay:      9.988ns (Levels of Logic = 3)
  Clock Path Skew:      -0.044ns (0.485 - 0.529)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3 to inst_sp6wrap/app/mem/mem_wr_data_out2_r_24
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y89.AQ       Tcko                  0.430   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd4
                                                       inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3
    SLICE_X12Y80.D4      net (fanout=38)       1.762   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3
    SLICE_X12Y80.D       Tilo                  0.235   inst_sp6wrap/app/mem/mem_wr_mask1_r<3>
                                                       lut35942_111
    SLICE_X3Y72.A4       net (fanout=49)       1.681   lut35942_111
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.A2      net (fanout=117)      5.272   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37052_8302
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_24
    -------------------------------------------------  ---------------------------
    Total                                      9.988ns (1.273ns logic, 8.715ns route)
                                                       (12.7% logic, 87.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.693ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2 (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_24 (FF)
  Requirement:          12.800ns
  Data Path Delay:      9.960ns (Levels of Logic = 3)
  Clock Path Skew:      -0.042ns (0.485 - 0.527)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2 to inst_sp6wrap/app/mem/mem_wr_data_out2_r_24
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y87.BQ       Tcko                  0.525   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
                                                       inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
    SLICE_X12Y80.D6      net (fanout=40)       1.639   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
    SLICE_X12Y80.D       Tilo                  0.235   inst_sp6wrap/app/mem/mem_wr_mask1_r<3>
                                                       lut35942_111
    SLICE_X3Y72.A4       net (fanout=49)       1.681   lut35942_111
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.A2      net (fanout=117)      5.272   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37052_8302
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_24
    -------------------------------------------------  ---------------------------
    Total                                      9.960ns (1.368ns logic, 8.592ns route)
                                                       (13.7% logic, 86.3% route)

--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/app/mem/mem_wr_data_out2_r_26 (SLICE_X36Y90.C4), 6 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.588ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_26 (FF)
  Requirement:          12.800ns
  Data Path Delay:      11.064ns (Levels of Logic = 3)
  Clock Path Skew:      -0.043ns (0.485 - 0.528)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r to inst_sp6wrap/app/mem/mem_wr_data_out2_r_26
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y98.AQ      Tcko                  0.476   inst_sp6wrap/app/PIO/PIO_EP/EP_RX/tlp_type_iowr_r
                                                       inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r
    SLICE_X3Y72.B4       net (fanout=65)       4.343   GPIO1C_28_OBUF
    SLICE_X3Y72.B        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35998_112
    SLICE_X3Y72.A5       net (fanout=5)        0.231   lut35998_112
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.C4      net (fanout=117)      5.147   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37026_8298
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_26
    -------------------------------------------------  ---------------------------
    Total                                     11.064ns (1.343ns logic, 9.721ns route)
                                                       (12.1% logic, 87.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.788ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3 (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_26 (FF)
  Requirement:          12.800ns
  Data Path Delay:      9.863ns (Levels of Logic = 3)
  Clock Path Skew:      -0.044ns (0.485 - 0.529)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3 to inst_sp6wrap/app/mem/mem_wr_data_out2_r_26
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y89.AQ       Tcko                  0.430   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd4
                                                       inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3
    SLICE_X12Y80.D4      net (fanout=38)       1.762   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3
    SLICE_X12Y80.D       Tilo                  0.235   inst_sp6wrap/app/mem/mem_wr_mask1_r<3>
                                                       lut35942_111
    SLICE_X3Y72.A4       net (fanout=49)       1.681   lut35942_111
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.C4      net (fanout=117)      5.147   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37026_8298
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_26
    -------------------------------------------------  ---------------------------
    Total                                      9.863ns (1.273ns logic, 8.590ns route)
                                                       (12.9% logic, 87.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.818ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2 (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_26 (FF)
  Requirement:          12.800ns
  Data Path Delay:      9.835ns (Levels of Logic = 3)
  Clock Path Skew:      -0.042ns (0.485 - 0.527)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2 to inst_sp6wrap/app/mem/mem_wr_data_out2_r_26
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y87.BQ       Tcko                  0.525   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
                                                       inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
    SLICE_X12Y80.D6      net (fanout=40)       1.639   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
    SLICE_X12Y80.D       Tilo                  0.235   inst_sp6wrap/app/mem/mem_wr_mask1_r<3>
                                                       lut35942_111
    SLICE_X3Y72.A4       net (fanout=49)       1.681   lut35942_111
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.C4      net (fanout=117)      5.147   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37026_8298
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_26
    -------------------------------------------------  ---------------------------
    Total                                      9.835ns (1.368ns logic, 8.467ns route)
                                                       (13.9% logic, 86.1% route)

--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/app/mem/mem_wr_data_out2_r_27 (SLICE_X36Y90.D4), 6 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.677ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_27 (FF)
  Requirement:          12.800ns
  Data Path Delay:      10.975ns (Levels of Logic = 3)
  Clock Path Skew:      -0.043ns (0.485 - 0.528)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r to inst_sp6wrap/app/mem/mem_wr_data_out2_r_27
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y98.AQ      Tcko                  0.476   inst_sp6wrap/app/PIO/PIO_EP/EP_RX/tlp_type_iowr_r
                                                       inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r
    SLICE_X3Y72.B4       net (fanout=65)       4.343   GPIO1C_28_OBUF
    SLICE_X3Y72.B        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35998_112
    SLICE_X3Y72.A5       net (fanout=5)        0.231   lut35998_112
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.D4      net (fanout=117)      5.058   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37013_8296
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_27
    -------------------------------------------------  ---------------------------
    Total                                     10.975ns (1.343ns logic, 9.632ns route)
                                                       (12.2% logic, 87.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.877ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3 (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_27 (FF)
  Requirement:          12.800ns
  Data Path Delay:      9.774ns (Levels of Logic = 3)
  Clock Path Skew:      -0.044ns (0.485 - 0.529)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3 to inst_sp6wrap/app/mem/mem_wr_data_out2_r_27
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y89.AQ       Tcko                  0.430   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd4
                                                       inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3
    SLICE_X12Y80.D4      net (fanout=38)       1.762   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3
    SLICE_X12Y80.D       Tilo                  0.235   inst_sp6wrap/app/mem/mem_wr_mask1_r<3>
                                                       lut35942_111
    SLICE_X3Y72.A4       net (fanout=49)       1.681   lut35942_111
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.D4      net (fanout=117)      5.058   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37013_8296
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_27
    -------------------------------------------------  ---------------------------
    Total                                      9.774ns (1.273ns logic, 8.501ns route)
                                                       (13.0% logic, 87.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.907ns (requirement - (data path - clock path skew + uncertainty))
  Source:               inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2 (FF)
  Destination:          inst_sp6wrap/app/mem/mem_wr_data_out2_r_27 (FF)
  Requirement:          12.800ns
  Data Path Delay:      9.746ns (Levels of Logic = 3)
  Clock Path Skew:      -0.042ns (0.485 - 0.527)
  Source Clock:         pclk rising at 0.000ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.198ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2 to inst_sp6wrap/app/mem/mem_wr_data_out2_r_27
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y87.BQ       Tcko                  0.525   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
                                                       inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
    SLICE_X12Y80.D6      net (fanout=40)       1.639   inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2
    SLICE_X12Y80.D       Tilo                  0.235   inst_sp6wrap/app/mem/mem_wr_mask1_r<3>
                                                       lut35942_111
    SLICE_X3Y72.A4       net (fanout=49)       1.681   lut35942_111
    SLICE_X3Y72.A        Tilo                  0.259   inst_sp6wrap/app/mem/mem_wr_req_out_r<2>
                                                       lut35999_113
    SLICE_X36Y90.D4      net (fanout=117)      5.058   lut35999_113
    SLICE_X36Y90.CLK     Tas                   0.349   inst_sp6wrap/app/mem/mem_wr_data_out2_r<27>
                                                       lut37013_8296
                                                       inst_sp6wrap/app/mem/mem_wr_data_out2_r_27
    -------------------------------------------------  ---------------------------
    Total                                      9.746ns (1.368ns logic, 8.378ns route)
                                                       (14.0% logic, 86.0% route)

--------------------------------------------------------------------------------

Hold Paths: TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP
        "inst_sp6wrap_eptest_i_clk_62_5"
        TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD21), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.138ns (requirement - (clock path skew + uncertainty - data path))
  Source:               inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_21 (FF)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          0.000ns
  Data Path Delay:      0.144ns (Levels of Logic = 0)
  Clock Path Skew:      0.006ns (0.068 - 0.062)
  Source Clock:         pclk rising at 12.800ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_21 to inst_sp6wrap/eptest_i/PCIE_A1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y105.BQ     Tcko                  0.200   inst_sp6wrap/trn_td<19>
                                                       inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_21
    PCIE_X0Y0.TRNTD21    net (fanout=2)        0.794   inst_sp6wrap/trn_td<21>
    PCIE_X0Y0.USERCLK    Tpcickd_TRNTD(-Th)     0.850   inst_sp6wrap/eptest_i/PCIE_A1
                                                       inst_sp6wrap/eptest_i/PCIE_A1
    -------------------------------------------------  ---------------------------
    Total                                      0.144ns (-0.650ns logic, 0.794ns route)
                                                       (-451.4% logic, 551.4% route)

--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD3), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.228ns (requirement - (clock path skew + uncertainty - data path))
  Source:               inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_3 (FF)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          0.000ns
  Data Path Delay:      0.225ns (Levels of Logic = 0)
  Clock Path Skew:      -0.003ns (0.068 - 0.071)
  Source Clock:         pclk rising at 12.800ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_3 to inst_sp6wrap/eptest_i/PCIE_A1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y99.CQ      Tcko                  0.200   inst_sp6wrap/trn_td<4>
                                                       inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_3
    PCIE_X0Y0.TRNTD3     net (fanout=2)        0.875   inst_sp6wrap/trn_td<3>
    PCIE_X0Y0.USERCLK    Tpcickd_TRNTD(-Th)     0.850   inst_sp6wrap/eptest_i/PCIE_A1
                                                       inst_sp6wrap/eptest_i/PCIE_A1
    -------------------------------------------------  ---------------------------
    Total                                      0.225ns (-0.650ns logic, 0.875ns route)
                                                       (-288.9% logic, 388.9% route)

--------------------------------------------------------------------------------

Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD18), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.230ns (requirement - (clock path skew + uncertainty - data path))
  Source:               inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_18 (FF)
  Destination:          inst_sp6wrap/eptest_i/PCIE_A1 (OTHER)
  Requirement:          0.000ns
  Data Path Delay:      0.232ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.068 - 0.066)
  Source Clock:         pclk rising at 12.800ns
  Destination Clock:    pclk rising at 12.800ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_18 to inst_sp6wrap/eptest_i/PCIE_A1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y101.CQ     Tcko                  0.200   inst_sp6wrap/trn_td<18>
                                                       inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_18
    PCIE_X0Y0.TRNTD18    net (fanout=3)        0.882   inst_sp6wrap/trn_td<18>
    PCIE_X0Y0.USERCLK    Tpcickd_TRNTD(-Th)     0.850   inst_sp6wrap/eptest_i/PCIE_A1
                                                       inst_sp6wrap/eptest_i/PCIE_A1
    -------------------------------------------------  ---------------------------
    Total                                      0.232ns (-0.650ns logic, 0.882ns route)
                                                       (-280.2% logic, 380.2% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP
        "inst_sp6wrap_eptest_i_clk_62_5"
        TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;
--------------------------------------------------------------------------------
Slack: -3.200ns (period - min period limit)
  Period: 12.800ns
  Min period limit: 16.000ns (62.500MHz) (Tpciper_USERCLK)
  Physical resource: inst_sp6wrap/eptest_i/PCIE_A1/USERCLK
  Logical resource: inst_sp6wrap/eptest_i/PCIE_A1/USERCLK
  Location pin: PCIE_X0Y0.USERCLK
  Clock network: pclk
--------------------------------------------------------------------------------
Slack: 9.230ns (period - min period limit)
  Period: 12.800ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKA
  Logical resource: inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKA
  Location pin: RAMB16_X0Y52.CLKA
  Clock network: pclk
--------------------------------------------------------------------------------
Slack: 9.230ns (period - min period limit)
  Period: 12.800ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB)
  Physical resource: inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKB
  Logical resource: inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKB
  Location pin: RAMB16_X0Y52.CLKB
  Clock network: pclk
--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_xtalclk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_xtalclk                     |     20.000ns|      8.000ns|     19.708ns|            0|           14|            0|        53993|
| TS_clk_wiz_v1_6_50x200_clkfx  |      5.000ns|      2.800ns|      4.927ns|            0|           14|            0|        31362|
|  TS_memc3_infrastructure_inst_|     20.000ns|     13.340ns|          N/A|            0|            0|        30415|            0|
|  mcb_drp_clk_bufg_in_0        |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  clk_2x_180_0                 |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  clk_2x_0_0                   |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      5.000ns|      4.927ns|          N/A|           14|            0|          947|            0|
|  clk0_bufg_in_0               |             |             |             |             |             |             |             |
| TS_clk_wiz_v1_6_50x62x312_clko|      3.200ns|      3.130ns|          N/A|            0|            0|          133|            0|
| ut1                           |             |             |             |             |             |             |             |
| TS_clk_wiz_v1_6_50x62x312_clko|     16.000ns|      9.210ns|          N/A|            0|            0|        22498|            0|
| ut0                           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_GTPCLKOUT1_0_
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_GTPCLKOUT1_0_               |      6.173ns|      1.904ns|      6.400ns|            0|            1|            0|        12309|
| TS_GTPCLKOUT1_DCM             |      6.173ns|      6.400ns|          N/A|            1|            0|        12309|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_inst_sp6wrap_eptest_i_gt_ref|      8.000ns|      1.904ns|     10.000ns|            0|            2|            0|         9420|
|clk_out_0_                     |             |             |             |             |             |             |             |
| TS_inst_sp6wrap_eptest_i_gt_re|      8.000ns|      3.334ns|     10.000ns|            0|            2|            0|         9420|
| fclk_buf                      |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|      6.400ns|      8.000ns|          N/A|            1|            0|           45|            0|
|  125                          |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|      3.200ns|      3.200ns|          N/A|            0|            0|            0|            0|
|  250                          |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|     12.800ns|     16.000ns|          N/A|            1|            0|         9375|            0|
|  62_5                         |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_DP_CLK1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_DP_CLK1                     |     37.037ns|     16.000ns|     19.200ns|            0|            0|            0|            0|
| TS_ctm_27x162_clkfx           |      6.173ns|      3.200ns|          N/A|            0|            0|            0|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_SYS_CLK3
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK3                    |      5.000ns|      2.800ns|      3.570ns|            0|            0|            0|            0|
| TS_memc3_infrastructure_inst_m|     20.000ns|      2.270ns|          N/A|            0|            0|            0|            0|
| cb_drp_clk_bufg_in            |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
| lk_2x_180                     |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
| lk_2x_0                       |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      5.000ns|      3.570ns|          N/A|            0|            0|            0|            0|
| lk0_bufg_in                   |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

4 constraints not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock DP_CLK0
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
DP_CLK0        |    8.392|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock xtalclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
xtalclk        |   10.846|         |    1.354|         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 17  Score: 97058  (Setup/Max: 0, Hold: 92030, Component Switching Limit: 5028)

Constraints cover 78678 paths, 0 nets, and 18250 connections

Design statistics:
   Minimum period:  16.000ns{1}   (Maximum frequency:  62.500MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed SAT 12 NOV 14:12:32 2011 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 208 MB



