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## Project    : Spartan-6 Integrated Block for PCI Express
## File       : xilinx_pcie_1_lane_ep_xc6slx45t-fgg484-3.ucf
## Description: Example User Constraints File
##
## Use this file only with the device listed below.  Any other
## combination is invalid.  Do not modify this file except in
## regions designated for "User" constraints.
##-----------------------------------------------------------------------------

###############################################################################
# Define Device, Package And Speed Grade
###############################################################################

CONFIG PART = xc6slx45t-fgg484-3;

###############################################################################
# User Time Names / User Time Groups / Time Specs
###############################################################################

###############################################################################
# User Physical Constraints
###############################################################################

###############################################################################
# Pinout and Related I/O Constraints
###############################################################################

#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
#

#NET sys_reset_n      LOC = XXX  | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY;

# SYS clock 100 or 125 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Spartan-6 GTP
# Transceiver architecture requires the use of dedicated clock
# resources (FPGA input pins) associated with each GTP Transceiver Tile.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in the example design.
# Please refer to the Spartan-6 GTP Transceiver User Guide
# for guidelines regarding clock resource selection.
#

NET  sys_clk_n       LOC = D11;
NET  sys_clk_p       LOC = C11;

#
# Transceiver instance placement.  This constraint selects the
# transceiver to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Spartan-6 GTP Transceiver User Guide for more
# information.
#
# PCIe Lane 0
INST eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i LOC = GTPA1_DUAL_X0Y0;
NET   pci_exp_txp  LOC = B8;
NET   pci_exp_txn  LOC = A8;
NET   pci_exp_rxp  LOC = D9;
NET   pci_exp_rxn  LOC = C9;


###############################################################################
# Physical Constraints
###############################################################################

###############################################################################
# Timing Constraints
###############################################################################

#
# Ignore timing on asynchronous signals.
#
NET sys_reset_n TIG;

#
# Timing requirements and related constraints.
#
NET sys_clk_c PERIOD = 10ns;

NET eptest_i/gt_refclk_out(0) TNM_NET = GT_REFCLK_OUT;
TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 10ns HIGH 50 % ;

###############################################################################
# End
###############################################################################
