<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
					twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
							   NETDELAY | 
							   NETSKEW | 
							   PATH |
							   DEFPERIOD |
							   UNCONSTPATH |
							   DEFPATH | 
							   PATH2SETUP |
							   UNCONSTPATH2SETUP | 
							   PATHCLASS | 
							   PATHDELAY | 
							   PERIOD |
							   FREQUENCY |
							   PATHBLOCK |
							   OFFSET |
							   OFFSETIN |
							   OFFSETINCLOCK | 
							   UNCONSTOFFSETINCLOCK |
							   OFFSETINDELAY |
							   OFFSETINMOD |
							   OFFSETOUT |
							   OFFSETOUTCLOCK |
							   UNCONSTOFFSETOUTCLOCK | 
							   OFFSETOUTDELAY |
							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
					   twEndPtCnt?,
					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
						twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
					  fDCMJit CDATA #IMPLIED
					  fPhaseErr CDATA #IMPLIED
					  sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
					  best CDATA #IMPLIED requested CDATA #IMPLIED
					  errors CDATA #IMPLIED
					  score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 12.2 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml exp6t_disp.twx exp6t_disp.ncd -o exp6t_disp.twr
exp6t_disp.pcf

</twCmdLine><twDesign>exp6t_disp.ncd</twDesign><twDesignPath>exp6t_disp.ncd</twDesignPath><twPCF>exp6t_disp.pcf</twPCF><twPcfPath>exp6t_disp.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx45t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRELIMINARY 1.10 2010-06-28</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_xtalclk = PERIOD TIMEGRP &quot;xtalclk&quot; 20 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>8.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: TS_xtalclk = PERIOD TIMEGRP &quot;xtalclk&quot; 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="7" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="2.249" period="3.200" constraintValue="3.200" deviceLimit="0.951" freqLimit="1051.525" physResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1" logResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1" locationPin="PLL_ADV_X0Y3.CLKOUT1" clockNet="clk_wiz_v1_6_50x62x312/clkout1"/><twPinLimit anchorID="8" type="MINPERIOD" name="Tdcmper_CLKFX" slack="2.330" period="5.000" constraintValue="5.000" deviceLimit="2.670" freqLimit="374.532" physResource="clk_wiz_v1_6_50x200/dcm_sp_inst/CLKFX" logResource="clk_wiz_v1_6_50x200/dcm_sp_inst/CLKFX" locationPin="DCM_X0Y6.CLKFX" clockNet="clk_wiz_v1_6_50x200/clkfx"/><twPinLimit anchorID="9" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="12.000" period="20.000" constraintValue="10.000" deviceLimit="4.000" physResource="clk_wiz_v1_6_50x200/dcm_sp_inst/CLKIN" logResource="clk_wiz_v1_6_50x200/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y6.CLKIN" clockNet="clk_wiz_v1_6_50x200/clkin1"/></twPinLimitRpt></twConst><twConst anchorID="10" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP &quot;GTPCLKOUT1&lt;0&gt;&quot; 162 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.904</twMinPer></twConstHead><twPinLimitRpt anchorID="11"><twPinLimitBanner>Component Switching Limit Checks: TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP &quot;GTPCLKOUT1&lt;0&gt;&quot; 162 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="12" type="MINPERIOD" name="Tbufper_I" slack="4.268" period="6.172" constraintValue="6.172" deviceLimit="1.904" freqLimit="525.210" physResource="gtpclkout1_0_dcm2_bufio2_i/I" logResource="gtpclkout1_0_dcm2_bufio2_i/I" locationPin="BUFIO2_X4Y26.I" clockNet="GTPCLKOUT1&lt;0&gt;"/></twPinLimitRpt></twConst><twConst anchorID="13" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_epcie_refclkn = PERIOD TIMEGRP &quot;epcie_refclkn&quot; 100 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.200</twMinPer></twConstHead><twPinLimitRpt anchorID="14"><twPinLimitBanner>Component Switching Limit Checks: TS_epcie_refclkn = PERIOD TIMEGRP &quot;epcie_refclkn&quot; 100 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="15" type="MINPERIOD" name="Tgtpcper_CLK" slack="6.800" period="10.000" constraintValue="10.000" deviceLimit="3.200" freqLimit="312.500" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/CLK01" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/CLK01" locationPin="GTPA1_DUAL_X0Y0.CLK11" clockNet="inst_sp6wrap/sys_clk_c"/></twPinLimitRpt></twConst><twConst anchorID="16" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD TIMEGRP         &quot;inst_sp6wrap/eptest_i/gt_refclk_out&lt;0&gt;&quot; 8 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.904</twMinPer></twConstHead><twPinLimitRpt anchorID="17"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD TIMEGRP
        &quot;inst_sp6wrap/eptest_i/gt_refclk_out&lt;0&gt;&quot; 8 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="18" type="MINPERIOD" name="Tbufper_I" slack="6.096" period="8.000" constraintValue="8.000" deviceLimit="1.904" freqLimit="525.210" physResource="inst_sp6wrap/eptest_i/gt_refclk_bufio2/I" logResource="inst_sp6wrap/eptest_i/gt_refclk_bufio2/I" locationPin="BUFIO2_X2Y26.I" clockNet="inst_sp6wrap/eptest_i/gt_refclk_out&lt;0&gt;"/></twPinLimitRpt></twConst><twConst anchorID="19" twConstType="PERIOD" ><twConstHead uID="5"><twConstName UCFConstName="" ScopeName="">TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPinLimitRpt anchorID="20"><twPinLimitBanner>Component Switching Limit Checks: TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="21" type="MINPERIOD" name="Tdcmper_CLKFX" slack="3.503" period="6.173" constraintValue="6.173" deviceLimit="2.670" freqLimit="374.532" physResource="ctm_27x162/dcm_sp_inst/CLKFX" logResource="ctm_27x162/dcm_sp_inst/CLKFX" locationPin="DCM_X0Y7.CLKFX" clockNet="ctm_27x162/clkfx"/><twPinLimit anchorID="22" type="MINLOWPULSE" name="Tdcmpw_CLKIN_25_50" slack="21.037" period="37.037" constraintValue="18.518" deviceLimit="8.000" physResource="ctm_27x162/dcm_sp_inst/CLKIN" logResource="ctm_27x162/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y7.CLKIN" clockNet="ctm_27x162/clkin1"/><twPinLimit anchorID="23" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_25_50" slack="21.037" period="37.037" constraintValue="18.518" deviceLimit="8.000" physResource="ctm_27x162/dcm_sp_inst/CLKIN" logResource="ctm_27x162/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y7.CLKIN" clockNet="ctm_27x162/clkin1"/></twPinLimitRpt></twConst><twConst anchorID="24" twConstType="PERIOD" ><twConstHead uID="6"><twConstName UCFConstName="" ScopeName="">TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;</twConstName><twItemCnt>2956</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1022</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>8.392</twMinPer></twConstHead><twPathRptBanner iPaths="45" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/aux_count_r_4 (SLICE_X13Y1.B1), 45 paths
</twPathRptBanner><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>28.645</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_clk_one_r</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_4</twDest><twTotPathDel>7.539</twTotPathDel><twClkSkew dest = "0.521" src = "1.339">0.818</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_clk_one_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_4</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X6Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X6Y8.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>dp_main/aux_tx/aux_clk_one_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.A6</twSite><twDelType>net</twDelType><twFanCnt>35</twFanCnt><twDelInfo twEdge="twRising">2.101</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29944_388</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.C4</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.949</twDelInfo><twComp>lut29944_388</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>lut30137_391</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.487</twDelInfo><twComp>lut30137_391</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y1.B1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.983</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y1.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;4&gt;</twComp><twBEL>lut30170_6523</twBEL><twBEL>dp_main/aux_tx/aux_count_r_4</twBEL></twPathDel><twLogDel>1.857</twLogDel><twRouteDel>5.682</twRouteDel><twTotDel>7.539</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>24.6</twPctLog><twPctRoute>75.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>28.727</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_4</twDest><twTotPathDel>7.100</twTotPathDel><twClkSkew dest = "0.521" src = "1.696">1.175</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_4</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X15Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X15Y8.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/aux_tx/aux_data8_r</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y8.B3</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">1.810</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y8.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;2&gt;</twComp><twBEL>lut29533_370</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y8.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.268</twDelInfo><twComp>lut29533_370</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y8.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;2&gt;</twComp><twBEL>lut29534_394</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.125</twDelInfo><twComp>lut29534_394</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y1.B1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.983</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y1.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;4&gt;</twComp><twBEL>lut30170_6523</twBEL><twBEL>dp_main/aux_tx/aux_count_r_4</twBEL></twPathDel><twLogDel>1.752</twLogDel><twRouteDel>5.348</twRouteDel><twTotDel>7.100</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>24.7</twPctLog><twPctRoute>75.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="29"><twConstPath anchorID="30" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>28.763</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_4</twDest><twTotPathDel>7.497</twTotPathDel><twClkSkew dest = "0.521" src = "1.263">0.742</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_4</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X14Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X14Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd4</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.B2</twSite><twDelType>net</twDelType><twFanCnt>34</twFanCnt><twDelInfo twEdge="twRising">1.570</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29943_387</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.230</twDelInfo><twComp>lut29943_387</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29944_388</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.C4</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.949</twDelInfo><twComp>lut29944_388</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>lut30137_391</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.487</twDelInfo><twComp>lut30137_391</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y1.B1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.983</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y1.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;4&gt;</twComp><twBEL>lut30170_6523</twBEL><twBEL>dp_main/aux_tx/aux_count_r_4</twBEL></twPathDel><twLogDel>2.116</twLogDel><twRouteDel>5.381</twRouteDel><twTotDel>7.497</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>28.2</twPctLog><twPctRoute>71.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="45" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/aux_count_r_0 (SLICE_X13Y2.A4), 45 paths
</twPathRptBanner><twPathRpt anchorID="31"><twConstPath anchorID="32" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>29.055</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_clk_one_r</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_0</twDest><twTotPathDel>7.337</twTotPathDel><twClkSkew dest = "0.729" src = "1.339">0.610</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_clk_one_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_0</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X6Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X6Y8.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>dp_main/aux_tx/aux_clk_one_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.A6</twSite><twDelType>net</twDelType><twFanCnt>35</twFanCnt><twDelInfo twEdge="twRising">2.101</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29944_388</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.C4</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.949</twDelInfo><twComp>lut29944_388</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>lut30137_391</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.487</twDelInfo><twComp>lut30137_391</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y2.A4</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.781</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y2.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;3&gt;</twComp><twBEL>lut30149_6510</twBEL><twBEL>dp_main/aux_tx/aux_count_r_0</twBEL></twPathDel><twLogDel>1.857</twLogDel><twRouteDel>5.480</twRouteDel><twTotDel>7.337</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>25.3</twPctLog><twPctRoute>74.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="33"><twConstPath anchorID="34" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>29.137</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_0</twDest><twTotPathDel>6.898</twTotPathDel><twClkSkew dest = "0.729" src = "1.696">0.967</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_0</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X15Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X15Y8.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/aux_tx/aux_data8_r</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y8.B3</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">1.810</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y8.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;2&gt;</twComp><twBEL>lut29533_370</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y8.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.268</twDelInfo><twComp>lut29533_370</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y8.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;2&gt;</twComp><twBEL>lut29534_394</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.125</twDelInfo><twComp>lut29534_394</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y2.A4</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.781</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y2.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;3&gt;</twComp><twBEL>lut30149_6510</twBEL><twBEL>dp_main/aux_tx/aux_count_r_0</twBEL></twPathDel><twLogDel>1.752</twLogDel><twRouteDel>5.146</twRouteDel><twTotDel>6.898</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>25.4</twPctLog><twPctRoute>74.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="35"><twConstPath anchorID="36" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>29.173</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_0</twDest><twTotPathDel>7.295</twTotPathDel><twClkSkew dest = "0.729" src = "1.263">0.534</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_0</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X14Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X14Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd4</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.B2</twSite><twDelType>net</twDelType><twFanCnt>34</twFanCnt><twDelInfo twEdge="twRising">1.570</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29943_387</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.230</twDelInfo><twComp>lut29943_387</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29944_388</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.C4</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.949</twDelInfo><twComp>lut29944_388</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>lut30137_391</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.487</twDelInfo><twComp>lut30137_391</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y2.A4</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.781</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y2.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;3&gt;</twComp><twBEL>lut30149_6510</twBEL><twBEL>dp_main/aux_tx/aux_count_r_0</twBEL></twPathDel><twLogDel>2.116</twLogDel><twRouteDel>5.179</twRouteDel><twTotDel>7.295</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>29.0</twPctLog><twPctRoute>71.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="45" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/aux_count_r_3 (SLICE_X13Y2.D3), 45 paths
</twPathRptBanner><twPathRpt anchorID="37"><twConstPath anchorID="38" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>29.167</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_clk_one_r</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_3</twDest><twTotPathDel>7.225</twTotPathDel><twClkSkew dest = "0.729" src = "1.339">0.610</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_clk_one_r</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_3</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X6Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X6Y8.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp><twBEL>dp_main/aux_tx/aux_clk_one_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.A6</twSite><twDelType>net</twDelType><twFanCnt>35</twFanCnt><twDelInfo twEdge="twRising">2.101</twDelInfo><twComp>dp_main/aux_tx/aux_clk_one_r</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29944_388</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.C4</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.949</twDelInfo><twComp>lut29944_388</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>lut30137_391</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.487</twDelInfo><twComp>lut30137_391</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y2.D3</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.669</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y2.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;3&gt;</twComp><twBEL>lut30165_6520</twBEL><twBEL>dp_main/aux_tx/aux_count_r_3</twBEL></twPathDel><twLogDel>1.857</twLogDel><twRouteDel>5.368</twRouteDel><twTotDel>7.225</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>25.7</twPctLog><twPctRoute>74.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="39"><twConstPath anchorID="40" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>29.249</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_3</twDest><twTotPathDel>6.786</twTotPathDel><twClkSkew dest = "0.729" src = "1.696">0.967</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_3</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X15Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X15Y8.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/aux_tx/aux_data8_r</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y8.B3</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">1.810</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y8.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;2&gt;</twComp><twBEL>lut29533_370</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y8.A5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.268</twDelInfo><twComp>lut29533_370</twComp></twPathDel><twPathDel><twSite>SLICE_X22Y8.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>dp_main/aux_tx/aux_tx_data_r&lt;2&gt;</twComp><twBEL>lut29534_394</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D1</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.125</twDelInfo><twComp>lut29534_394</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y2.D3</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.669</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y2.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;3&gt;</twComp><twBEL>lut30165_6520</twBEL><twBEL>dp_main/aux_tx/aux_count_r_3</twBEL></twPathDel><twLogDel>1.752</twLogDel><twRouteDel>5.034</twRouteDel><twTotDel>6.786</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>25.8</twPctLog><twPctRoute>74.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="41"><twConstPath anchorID="42" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>29.285</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_3</twDest><twTotPathDel>7.183</twTotPathDel><twClkSkew dest = "0.729" src = "1.263">0.534</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_3</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X14Y6.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X14Y6.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd4</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.B2</twSite><twDelType>net</twDelType><twFanCnt>34</twFanCnt><twDelInfo twEdge="twRising">1.570</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29943_387</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y7.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.230</twDelInfo><twComp>lut29943_387</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y7.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_done</twComp><twBEL>lut29944_388</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.C4</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.949</twDelInfo><twComp>lut29944_388</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>lut30137_391</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y7.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.487</twDelInfo><twComp>lut30137_391</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y7.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1517</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y3.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.162</twDelInfo><twComp>dp_main/aux_tx/Mmux_aux_count_w1516</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y3.CMUX</twSite><twDelType>Tcxc</twDelType><twDelInfo twEdge="twRising">0.182</twDelInfo><twComp>dp_main/aux_tx/N119</twComp><twBEL>dp_main/aux_tx/Mmux_aux_count_w1518</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y2.D3</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.669</twDelInfo><twComp>dp_main/aux_tx/N119</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y2.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;3&gt;</twComp><twBEL>lut30165_6520</twBEL><twBEL>dp_main/aux_tx/aux_count_r_3</twBEL></twPathDel><twLogDel>2.116</twLogDel><twRouteDel>5.067</twRouteDel><twTotDel>7.183</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>29.5</twPctLog><twPctRoute>70.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/aux_data8_r (SLICE_X15Y8.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="43"><twConstPath anchorID="44" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.254</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_count_r_2</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_data8_r</twDest><twTotPathDel>0.845</twTotPathDel><twClkSkew dest = "0.950" src = "0.359">-0.591</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_count_r_2</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_data8_r</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X13Y2.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X13Y2.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;3&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y8.D6</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twFalling">0.432</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X15Y8.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>dp_main/aux_tx/aux_data8_r</twComp><twBEL>lut30097_6503</twBEL><twBEL>dp_main/aux_tx/aux_data8_r</twBEL></twPathDel><twLogDel>0.413</twLogDel><twRouteDel>0.432</twRouteDel><twTotDel>0.845</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>48.9</twPctLog><twPctRoute>51.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="6" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_linkup/aux_stat_algn_r (SLICE_X26Y15.A3), 6 paths
</twPathRptBanner><twPathRpt anchorID="45"><twConstPath anchorID="46" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.275</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/aux_cmd_code_r_17</twSrc><twDest BELType="FF">dp_main/dp_main_linkup/aux_stat_algn_r</twDest><twTotPathDel>0.939</twTotPathDel><twClkSkew dest = "1.355" src = "0.691">-0.664</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/aux_cmd_code_r_17</twSrc><twDest BELType='FF'>dp_main/dp_main_linkup/aux_stat_algn_r</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X25Y15.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X25Y15.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.198</twDelInfo><twComp>dp_main/link_aux_tx_addr&lt;9&gt;</twComp><twBEL>dp_main/dp_main_linkup/aux_cmd_code_r_17</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y15.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.176</twDelInfo><twComp>dp_main/link_aux_tx_addr&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y15.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.156</twDelInfo><twComp>dp_main/dp_main_linkup/aux_stat_algn_r</twComp><twBEL>lut27254_5906</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y15.A3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.212</twDelInfo><twComp>lut27254_5906</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X26Y15.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.197</twDelInfo><twComp>dp_main/dp_main_linkup/aux_stat_algn_r</twComp><twBEL>dp_main/dp_main_linkup/aux_stat_algn_r_rstpot</twBEL><twBEL>dp_main/dp_main_linkup/aux_stat_algn_r</twBEL></twPathDel><twLogDel>0.551</twLogDel><twRouteDel>0.388</twRouteDel><twTotDel>0.939</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>58.7</twPctLog><twPctRoute>41.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="47"><twConstPath anchorID="48" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.303</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/aux_cmd_code_r_28</twSrc><twDest BELType="FF">dp_main/dp_main_linkup/aux_stat_algn_r</twDest><twTotPathDel>0.968</twTotPathDel><twClkSkew dest = "1.355" src = "0.690">-0.665</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/aux_cmd_code_r_28</twSrc><twDest BELType='FF'>dp_main/dp_main_linkup/aux_stat_algn_r</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X22Y15.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X22Y15.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.234</twDelInfo><twComp>dp_main/link_aux_tx_cmd&lt;3&gt;</twComp><twBEL>dp_main/dp_main_linkup/aux_cmd_code_r_28</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y15.B6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.169</twDelInfo><twComp>dp_main/link_aux_tx_cmd&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y15.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.156</twDelInfo><twComp>dp_main/dp_main_linkup/aux_stat_algn_r</twComp><twBEL>lut27254_5906</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y15.A3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.212</twDelInfo><twComp>lut27254_5906</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X26Y15.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.197</twDelInfo><twComp>dp_main/dp_main_linkup/aux_stat_algn_r</twComp><twBEL>dp_main/dp_main_linkup/aux_stat_algn_r_rstpot</twBEL><twBEL>dp_main/dp_main_linkup/aux_stat_algn_r</twBEL></twPathDel><twLogDel>0.587</twLogDel><twRouteDel>0.381</twRouteDel><twTotDel>0.968</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>60.6</twPctLog><twPctRoute>39.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="49"><twConstPath anchorID="50" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.387</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/aux_cmd_code_r_16</twSrc><twDest BELType="FF">dp_main/dp_main_linkup/aux_stat_algn_r</twDest><twTotPathDel>1.051</twTotPathDel><twClkSkew dest = "1.355" src = "0.691">-0.664</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/aux_cmd_code_r_16</twSrc><twDest BELType='FF'>dp_main/dp_main_linkup/aux_stat_algn_r</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X25Y15.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X25Y15.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.198</twDelInfo><twComp>dp_main/link_aux_tx_addr&lt;9&gt;</twComp><twBEL>dp_main/dp_main_linkup/aux_cmd_code_r_16</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y15.B3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.288</twDelInfo><twComp>dp_main/link_aux_tx_addr&lt;8&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y15.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.156</twDelInfo><twComp>dp_main/dp_main_linkup/aux_stat_algn_r</twComp><twBEL>lut27254_5906</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y15.A3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.212</twDelInfo><twComp>lut27254_5906</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X26Y15.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.197</twDelInfo><twComp>dp_main/dp_main_linkup/aux_stat_algn_r</twComp><twBEL>dp_main/dp_main_linkup/aux_stat_algn_r_rstpot</twBEL><twBEL>dp_main/dp_main_linkup/aux_stat_algn_r</twBEL></twPathDel><twLogDel>0.551</twLogDel><twRouteDel>0.500</twRouteDel><twTotDel>1.051</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>52.4</twPctLog><twPctRoute>47.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point aux_hpd_count_r_2 (SLICE_X13Y10.C6), 1 path
</twPathRptBanner><twPathRpt anchorID="51"><twConstPath anchorID="52" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.283</twSlack><twSrc BELType="FF">aux_hpd_in_r_1</twSrc><twDest BELType="FF">aux_hpd_count_r_2</twDest><twTotPathDel>0.845</twTotPathDel><twClkSkew dest = "0.932" src = "0.370">-0.562</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>aux_hpd_in_r_1</twSrc><twDest BELType='FF'>aux_hpd_count_r_2</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X16Y2.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X16Y2.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>aux_hpd_in_r&lt;1&gt;</twComp><twBEL>aux_hpd_in_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y10.C6</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twFalling">0.430</twDelInfo><twComp>aux_hpd_in_r&lt;1&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X13Y10.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>aux_hpd_count_r&lt;3&gt;</twComp><twBEL>lut6125_893</twBEL><twBEL>aux_hpd_count_r_2</twBEL></twPathDel><twLogDel>0.415</twLogDel><twRouteDel>0.430</twRouteDel><twTotDel>0.845</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>49.1</twPctLog><twPctRoute>50.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="53"><twPinLimitBanner>Component Switching Limit Checks: TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="54" type="MINPERIOD" name="Tcp" slack="35.638" period="37.037" constraintValue="37.037" deviceLimit="1.399" freqLimit="714.796" physResource="dp_main/dp_main_linkup/hpd_r_5_BRB1/CLK" logResource="dp_main/dp_main_linkup/Mshreg_hpd_r_5_BRB1/CLK" locationPin="SLICE_X44Y49.CLK" clockNet="CLK27"/><twPinLimit anchorID="55" type="MINHIGHPULSE" name="Trpw" slack="36.557" period="37.037" constraintValue="18.518" deviceLimit="0.240" physResource="dp_main/aux_tx/aux_clk_one_r/SR" logResource="dp_main/aux_tx/aux_clk_one_r/SR" locationPin="SLICE_X6Y8.SR" clockNet="][24489_9"/><twPinLimit anchorID="56" type="MINHIGHPULSE" name="Trpw" slack="36.557" period="37.037" constraintValue="18.518" deviceLimit="0.240" physResource="dp_main/aux_tx/aux_clk_r&lt;3&gt;/SR" logResource="dp_main/aux_tx/aux_clk_r_0/SR" locationPin="SLICE_X6Y10.SR" clockNet="][24489_9"/></twPinLimitRpt></twConst><twConst anchorID="57" twConstType="PERIOD" ><twConstHead uID="7"><twConstName UCFConstName="" ScopeName="">TS_SYS_CLK3 = PERIOD TIMEGRP &quot;SYS_CLK3&quot; 5 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.800</twMinPer></twConstHead><twPinLimitRpt anchorID="58"><twPinLimitBanner>Component Switching Limit Checks: TS_SYS_CLK3 = PERIOD TIMEGRP &quot;SYS_CLK3&quot; 5 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="59" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="1.549" period="2.500" constraintValue="2.500" deviceLimit="0.951" freqLimit="1051.525" physResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT0" logResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT0" locationPin="PLL_ADV_X0Y0.CLKOUT0" clockNet="memc3_infrastructure_inst/clk_2x_0"/><twPinLimit anchorID="60" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="1.549" period="2.500" constraintValue="2.500" deviceLimit="0.951" freqLimit="1051.525" physResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT1" logResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT1" locationPin="PLL_ADV_X0Y0.CLKOUT1" clockNet="memc3_infrastructure_inst/clk_2x_180"/><twPinLimit anchorID="61" type="MINLOWPULSE" name="Tdcmpw_CLKIN_200_250" slack="2.200" period="5.000" constraintValue="2.500" deviceLimit="1.400" physResource="memc3_infrastructure_inst/u_pll_adv/CLKIN1" logResource="memc3_infrastructure_inst/u_pll_adv/CLKIN1" locationPin="PLL_ADV_X0Y0.CLKIN2" clockNet="CLK200"/></twPinLimitRpt></twConst><twConst anchorID="62" twConstType="PERIOD" ><twConstHead uID="8"><twConstName UCFConstName="" ScopeName="">TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIMEGRP &quot;clk_wiz_v1_6_50x200_clkfx&quot;         TS_xtalclk / 4 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.800</twMinPer></twConstHead><twPinLimitRpt anchorID="63"><twPinLimitBanner>Component Switching Limit Checks: TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIMEGRP &quot;clk_wiz_v1_6_50x200_clkfx&quot;
        TS_xtalclk / 4 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="64" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="1.549" period="2.500" constraintValue="2.500" deviceLimit="0.951" freqLimit="1051.525" physResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT0" logResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT0" locationPin="PLL_ADV_X0Y0.CLKOUT0" clockNet="memc3_infrastructure_inst/clk_2x_0"/><twPinLimit anchorID="65" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="1.549" period="2.500" constraintValue="2.500" deviceLimit="0.951" freqLimit="1051.525" physResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT1" logResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT1" locationPin="PLL_ADV_X0Y0.CLKOUT1" clockNet="memc3_infrastructure_inst/clk_2x_180"/><twPinLimit anchorID="66" type="MINLOWPULSE" name="Tdcmpw_CLKIN_200_250" slack="2.200" period="5.000" constraintValue="2.500" deviceLimit="1.400" physResource="memc3_infrastructure_inst/u_pll_adv/CLKIN1" logResource="memc3_infrastructure_inst/u_pll_adv/CLKIN1" locationPin="PLL_ADV_X0Y0.CLKIN2" clockNet="CLK200"/></twPinLimitRpt></twConst><twConst anchorID="67" twConstType="PERIOD" ><twConstHead uID="9"><twConstName UCFConstName="" ScopeName="">TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk / 6.25 HIGH 50%;</twConstName><twItemCnt>133</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>133</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.130</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx2_out_r_0 (SLICE_X54Y2.A5), 1 path
</twPathRptBanner><twPathRpt anchorID="68"><twConstPath anchorID="69" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.070</twSlack><twSrc BELType="FF">tx_dvi/tx3_r_3</twSrc><twDest BELType="FF">tx_dvi/tx2_out_r_0</twDest><twTotPathDel>3.009</twTotPathDel><twClkSkew dest = "0.252" src = "0.259">0.007</twClkSkew><twDelConst>3.200</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.217" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.114</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/tx3_r_3</twSrc><twDest BELType='FF'>tx_dvi/tx2_out_r_0</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X43Y9.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63x5</twSrcClk><twPathDel><twSite>SLICE_X43Y9.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/tx3_r&lt;3&gt;</twComp><twBEL>tx_dvi/tx3_r_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y2.A5</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">2.230</twDelInfo><twComp>tx_dvi/tx3_r&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y2.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>tx_dvi/tx2_out_r&lt;0&gt;</twComp><twBEL>lut13420_2136</twBEL><twBEL>tx_dvi/tx2_out_r_0</twBEL></twPathDel><twLogDel>0.779</twLogDel><twRouteDel>2.230</twRouteDel><twTotDel>3.009</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLK63x5</twDestClk><twPctLog>25.9</twPctLog><twPctRoute>74.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx0_r_5_BRB1 (SLICE_X31Y16.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="70"><twConstPath anchorID="71" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.143</twSlack><twSrc BELType="FF">tx_dvi/tx3_r_3</twSrc><twDest BELType="FF">tx_dvi/tx0_r_5_BRB1</twDest><twTotPathDel>2.900</twTotPathDel><twClkSkew dest = "0.496" src = "0.539">0.043</twClkSkew><twDelConst>3.200</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.217" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.114</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/tx3_r_3</twSrc><twDest BELType='FF'>tx_dvi/tx0_r_5_BRB1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X43Y9.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63x5</twSrcClk><twPathDel><twSite>SLICE_X43Y9.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/tx3_r&lt;3&gt;</twComp><twBEL>tx_dvi/tx3_r_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X31Y16.D6</twSite><twDelType>net</twDelType><twFanCnt>33</twFanCnt><twDelInfo twEdge="twRising">2.097</twDelInfo><twComp>tx_dvi/tx3_r&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X31Y16.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>tx_dvi/tx0_r_5_BRB1</twComp><twBEL>lut13164_2079</twBEL><twBEL>tx_dvi/tx0_r_5_BRB1</twBEL></twPathDel><twLogDel>0.803</twLogDel><twRouteDel>2.097</twRouteDel><twTotDel>2.900</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLK63x5</twDestClk><twPctLog>27.7</twPctLog><twPctRoute>72.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/DDR_tx2_p (OLOGIC_X24Y1.D2), 1 path
</twPathRptBanner><twPathRpt anchorID="72"><twConstPath anchorID="73" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.246</twSlack><twSrc BELType="FF">tx_dvi/tx2_out_r_0</twSrc><twDest BELType="FF">tx_dvi/DDR_tx2_p</twDest><twTotPathDel>1.646</twTotPathDel><twClkSkew dest = "0.580" src = "0.174">-0.406</twClkSkew><twDelConst>1.600</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.217" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.114</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/tx2_out_r_0</twSrc><twDest BELType='FF'>tx_dvi/DDR_tx2_p</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X54Y2.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63x5</twSrcClk><twPathDel><twSite>SLICE_X54Y2.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/tx2_out_r&lt;0&gt;</twComp><twBEL>tx_dvi/tx2_out_r_0</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X24Y1.D2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.506</twDelInfo><twComp>tx_dvi/tx2_out_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X24Y1.CLK1</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.664</twDelInfo><twComp>tx_dvi/tx_ch2_ddr</twComp><twBEL>tx_dvi/DDR_tx2_p</twBEL></twPathDel><twLogDel>1.140</twLogDel><twRouteDel>0.506</twRouteDel><twTotDel>1.646</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="1.600">CLK63x5</twDestClk><twPctLog>69.3</twPctLog><twPctRoute>30.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk / 6.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx2_r_9_BRB1 (SLICE_X22Y11.A5), 1 path
</twPathRptBanner><twPathRpt anchorID="74"><twConstPath anchorID="75" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.076</twSlack><twSrc BELType="FF">tx_dvi/ch2_enc_r_9</twSrc><twDest BELType="FF">tx_dvi/tx2_r_9_BRB1</twDest><twTotPathDel>0.399</twTotPathDel><twClkSkew dest = "1.161" src = "1.106">-0.055</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch2_enc_r_9</twSrc><twDest BELType='FF'>tx_dvi/tx2_r_9_BRB1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X23Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X23Y11.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/ch2_enc&lt;9&gt;</twComp><twBEL>tx_dvi/ch2_enc_r_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y11.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.070</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;9&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X22Y11.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.131</twDelInfo><twComp>tx_dvi/tx2_r_8_BRB1</twComp><twBEL>tx_dvi/ch2_enc_r&lt;9&gt;_rt</twBEL><twBEL>tx_dvi/tx2_r_9_BRB1</twBEL></twPathDel><twLogDel>0.329</twLogDel><twRouteDel>0.070</twRouteDel><twTotDel>0.399</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLK63x5</twDestClk><twPctLog>82.5</twPctLog><twPctRoute>17.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx2_r_7_BRB2 (SLICE_X27Y8.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="76"><twConstPath anchorID="77" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.297</twSlack><twSrc BELType="FF">tx_dvi/ch2_enc_r_7</twSrc><twDest BELType="FF">tx_dvi/tx2_r_7_BRB2</twDest><twTotPathDel>0.621</twTotPathDel><twClkSkew dest = "1.155" src = "1.099">-0.056</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch2_enc_r_7</twSrc><twDest BELType='FF'>tx_dvi/tx2_r_7_BRB2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X20Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X20Y8.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;7&gt;</twComp><twBEL>tx_dvi/ch2_enc_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y8.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.362</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;7&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X27Y8.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/tx2_r_6_BRB2</twComp><twBEL>tx_dvi/tx2_r_7_BRB2</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.362</twRouteDel><twTotDel>0.621</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLK63x5</twDestClk><twPctLog>41.7</twPctLog><twPctRoute>58.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx2_r_6_BRB2 (SLICE_X27Y8.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="78"><twConstPath anchorID="79" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.298</twSlack><twSrc BELType="FF">tx_dvi/ch2_enc_r_6</twSrc><twDest BELType="FF">tx_dvi/tx2_r_6_BRB2</twDest><twTotPathDel>0.622</twTotPathDel><twClkSkew dest = "1.155" src = "1.099">-0.056</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch2_enc_r_6</twSrc><twDest BELType='FF'>tx_dvi/tx2_r_6_BRB2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X20Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X20Y8.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;7&gt;</twComp><twBEL>tx_dvi/ch2_enc_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y8.DX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.363</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;6&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X27Y8.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/tx2_r_6_BRB2</twComp><twBEL>tx_dvi/tx2_r_6_BRB2</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.363</twRouteDel><twTotDel>0.622</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLK63x5</twDestClk><twPctLog>41.6</twPctLog><twPctRoute>58.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="80"><twPinLimitBanner>Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk / 6.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="81" type="MINPERIOD" name="Tbcper_I" slack="0.930" period="3.200" constraintValue="3.200" deviceLimit="2.270" freqLimit="440.529" physResource="clk_wiz_v1_6_50x62x312/clkout2_buf/I0" logResource="clk_wiz_v1_6_50x62x312/clkout2_buf/I0" locationPin="BUFGMUX_X3Y16.I0" clockNet="clk_wiz_v1_6_50x62x312/clkout1"/><twPinLimit anchorID="82" type="MINPERIOD" name="Tockper" slack="1.444" period="3.200" constraintValue="3.200" deviceLimit="1.756" freqLimit="569.476" physResource="tx_dvi/tx_ch0_ddr/CLK0" logResource="tx_dvi/DDR_tx0_p/CK0" locationPin="OLOGIC_X25Y3.CLK0" clockNet="CLK63x5"/><twPinLimit anchorID="83" type="MINPERIOD" name="Tockper" slack="1.444" period="3.200" constraintValue="3.200" deviceLimit="1.756" freqLimit="569.476" physResource="tx_dvi/tx_ch1_ddr/CLK0" logResource="tx_dvi/DDR_tx1_p/CK0" locationPin="OLOGIC_X26Y3.CLK0" clockNet="CLK63x5"/></twPinLimitRpt></twConst><twConst anchorID="84" twConstType="PERIOD" ><twConstHead uID="10"><twConstName UCFConstName="" ScopeName="">TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk / 1.25 HIGH 50%;</twConstName><twItemCnt>22498</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1227</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>9.210</twMinPer></twConstHead><twPathRptBanner iPaths="137" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc1/st1_cnt_r_5 (SLICE_X4Y21.C6), 137 paths
</twPathRptBanner><twPathRpt anchorID="85"><twConstPath anchorID="86" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.790</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_7</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_5</twDest><twTotPathDel>9.051</twTotPathDel><twClkSkew dest = "0.246" src = "0.257">0.011</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_7</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_5</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X11Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X11Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;8&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y18.D2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">2.082</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11662_571</twComp><twBEL>lut11662_571</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.896</twDelInfo><twComp>lut11662_571</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.416</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y21.B2</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">1.968</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;5&gt;</twComp><twBEL>lut12062_602</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y21.C6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.253</twDelInfo><twComp>lut12062_602</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y21.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.433</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;5&gt;</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w125_G</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w125</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_5</twBEL></twPathDel><twLogDel>2.101</twLogDel><twRouteDel>6.950</twRouteDel><twTotDel>9.051</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>23.2</twPctLog><twPctRoute>76.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="87"><twConstPath anchorID="88" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>7.220</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_4</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_5</twDest><twTotPathDel>8.621</twTotPathDel><twClkSkew dest = "0.246" src = "0.257">0.011</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_4</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_5</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X10Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X10Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y18.D3</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.557</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11662_571</twComp><twBEL>lut11662_571</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.896</twDelInfo><twComp>lut11662_571</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.416</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y21.B2</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">1.968</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;5&gt;</twComp><twBEL>lut12062_602</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y21.C6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.253</twDelInfo><twComp>lut12062_602</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y21.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.433</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;5&gt;</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w125_G</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w125</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_5</twBEL></twPathDel><twLogDel>2.196</twLogDel><twRouteDel>6.425</twRouteDel><twTotDel>8.621</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>25.5</twPctLog><twPctRoute>74.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="89"><twConstPath anchorID="90" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>7.262</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_6</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_5</twDest><twTotPathDel>8.579</twTotPathDel><twClkSkew dest = "0.246" src = "0.257">0.011</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_6</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_5</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X10Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X10Y24.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y18.C2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.666</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y18.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11857_573</twComp><twBEL>lut11663_567</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B4</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">0.745</twDelInfo><twComp>lut11663_567</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.416</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y21.B2</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">1.968</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;5&gt;</twComp><twBEL>lut12062_602</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y21.C6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.253</twDelInfo><twComp>lut12062_602</twComp></twPathDel><twPathDel><twSite>SLICE_X4Y21.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.433</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;5&gt;</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w125_G</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w125</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_5</twBEL></twPathDel><twLogDel>2.196</twLogDel><twRouteDel>6.383</twRouteDel><twTotDel>8.579</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>25.6</twPctLog><twPctRoute>74.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="55" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc1/st1_qm_r_2 (SLICE_X29Y11.C2), 55 paths
</twPathRptBanner><twPathRpt anchorID="91"><twConstPath anchorID="92" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.967</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_7</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_qm_r_2</twDest><twTotPathDel>8.895</twTotPathDel><twClkSkew dest = "0.540" src = "0.530">-0.010</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_7</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_qm_r_2</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X11Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X11Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;8&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y18.D2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">2.082</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11662_571</twComp><twBEL>lut11662_571</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.896</twDelInfo><twComp>lut11662_571</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y19.B4</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y19.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12060_582</twComp><twBEL>tx_dvi/enc1/st0_abort_r_st1_case_cnt_ne_AND_496_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y11.C2</twSite><twDelType>net</twDelType><twFanCnt>23</twFanCnt><twDelInfo twEdge="twRising">3.182</twDelInfo><twComp>tx_dvi/enc1/N63</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>tx_dvi/ch1_enc&lt;3&gt;</twComp><twBEL>lut11706_1935</twBEL><twBEL>tx_dvi/enc1/st1_qm_r_2</twBEL></twPathDel><twLogDel>1.830</twLogDel><twRouteDel>7.065</twRouteDel><twTotDel>8.895</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>20.6</twPctLog><twPctRoute>79.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="93"><twConstPath anchorID="94" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>7.397</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_4</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_qm_r_2</twDest><twTotPathDel>8.465</twTotPathDel><twClkSkew dest = "0.540" src = "0.530">-0.010</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_4</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_qm_r_2</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X10Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X10Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y18.D3</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.557</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11662_571</twComp><twBEL>lut11662_571</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.896</twDelInfo><twComp>lut11662_571</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y19.B4</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y19.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12060_582</twComp><twBEL>tx_dvi/enc1/st0_abort_r_st1_case_cnt_ne_AND_496_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y11.C2</twSite><twDelType>net</twDelType><twFanCnt>23</twFanCnt><twDelInfo twEdge="twRising">3.182</twDelInfo><twComp>tx_dvi/enc1/N63</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>tx_dvi/ch1_enc&lt;3&gt;</twComp><twBEL>lut11706_1935</twBEL><twBEL>tx_dvi/enc1/st1_qm_r_2</twBEL></twPathDel><twLogDel>1.925</twLogDel><twRouteDel>6.540</twRouteDel><twTotDel>8.465</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>22.7</twPctLog><twPctRoute>77.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="95"><twConstPath anchorID="96" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>7.439</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_6</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_qm_r_2</twDest><twTotPathDel>8.423</twTotPathDel><twClkSkew dest = "0.540" src = "0.530">-0.010</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_6</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_qm_r_2</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X10Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X10Y24.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y18.C2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.666</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y18.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11857_573</twComp><twBEL>lut11663_567</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B4</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">0.745</twDelInfo><twComp>lut11663_567</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y19.B4</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">0.570</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y19.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12060_582</twComp><twBEL>tx_dvi/enc1/st0_abort_r_st1_case_cnt_ne_AND_496_o1</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y11.C2</twSite><twDelType>net</twDelType><twFanCnt>23</twFanCnt><twDelInfo twEdge="twRising">3.182</twDelInfo><twComp>tx_dvi/enc1/N63</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y11.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>tx_dvi/ch1_enc&lt;3&gt;</twComp><twBEL>lut11706_1935</twBEL><twBEL>tx_dvi/enc1/st1_qm_r_2</twBEL></twPathDel><twLogDel>1.925</twLogDel><twRouteDel>6.498</twRouteDel><twTotDel>8.423</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>22.9</twPctLog><twPctRoute>77.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="245" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc1/st1_cnt_r_2 (SLICE_X6Y18.D5), 245 paths
</twPathRptBanner><twPathRpt anchorID="97"><twConstPath anchorID="98" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>7.069</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_7</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_2</twDest><twTotPathDel>8.779</twTotPathDel><twClkSkew dest = "0.253" src = "0.257">0.004</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_7</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_2</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X11Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X11Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;8&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y18.D2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">2.082</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11662_571</twComp><twBEL>lut11662_571</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.896</twDelInfo><twComp>lut11662_571</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.416</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.D1</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">0.552</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.402</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w62_F</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w62</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y18.D5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.214</twDelInfo><twComp>tx_dvi/enc1/Mmux_st1_cnt_w61</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y18.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.449</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w64_F</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w64</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_2</twBEL></twPathDel><twLogDel>2.284</twLogDel><twRouteDel>6.495</twRouteDel><twTotDel>8.779</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>26.0</twPctLog><twPctRoute>74.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="99"><twConstPath anchorID="100" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>7.349</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_7</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_2</twDest><twTotPathDel>8.499</twTotPathDel><twClkSkew dest = "0.253" src = "0.257">0.004</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_7</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_2</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X11Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X11Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;8&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y18.D2</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">2.082</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11662_571</twComp><twBEL>lut11662_571</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.896</twDelInfo><twComp>lut11662_571</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.416</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.C6</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">0.271</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.403</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w62_G</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w62</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y18.D5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.214</twDelInfo><twComp>tx_dvi/enc1/Mmux_st1_cnt_w61</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y18.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.449</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w64_F</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w64</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_2</twBEL></twPathDel><twLogDel>2.285</twLogDel><twRouteDel>6.214</twRouteDel><twTotDel>8.499</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>26.9</twPctLog><twPctRoute>73.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="101"><twConstPath anchorID="102" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>7.499</twSlack><twSrc BELType="FF">tx_dvi/enc1/st0_qm_r_4</twSrc><twDest BELType="FF">tx_dvi/enc1/st1_cnt_r_2</twDest><twTotPathDel>8.349</twTotPathDel><twClkSkew dest = "0.253" src = "0.257">0.004</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st0_qm_r_4</twSrc><twDest BELType='FF'>tx_dvi/enc1/st1_cnt_r_2</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X10Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X10Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc1/st0_qm_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y18.D3</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.557</twDelInfo><twComp>tx_dvi/enc1/st0_qm_r&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y18.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut11662_571</twComp><twBEL>lut11662_571</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.896</twDelInfo><twComp>lut11662_571</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11666_576</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y21.C4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.335</twDelInfo><twComp>lut11666_576</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y21.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.255</twDelInfo><twComp>lut11668_578</twComp><twBEL>lut11669_605</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.B3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.416</twDelInfo><twComp>lut11669_605</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y18.D1</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">0.552</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y18.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.402</twDelInfo><twComp>tx_dvi/enc1/st1_case_cnt_eq</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w62_F</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w62</twBEL></twPathDel><twPathDel><twSite>SLICE_X6Y18.D5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.214</twDelInfo><twComp>tx_dvi/enc1/Mmux_st1_cnt_w61</twComp></twPathDel><twPathDel><twSite>SLICE_X6Y18.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.449</twDelInfo><twComp>tx_dvi/enc1/st1_cnt_r&lt;2&gt;</twComp><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w64_F</twBEL><twBEL>tx_dvi/enc1/Mmux_st1_cnt_w64</twBEL><twBEL>tx_dvi/enc1/st1_cnt_r_2</twBEL></twPathDel><twLogDel>2.379</twLogDel><twRouteDel>5.970</twRouteDel><twTotDel>8.349</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>28.5</twPctLog><twPctRoute>71.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk / 1.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/ch2_enc_r_6 (SLICE_X20Y8.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="103"><twConstPath anchorID="104" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.381</twSlack><twSrc BELType="FF">tx_dvi/enc2/st1_qm_r_6</twSrc><twDest BELType="FF">tx_dvi/ch2_enc_r_6</twDest><twTotPathDel>0.383</twTotPathDel><twClkSkew dest = "0.031" src = "0.029">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/enc2/st1_qm_r_6</twSrc><twDest BELType='FF'>tx_dvi/ch2_enc_r_6</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X21Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X21Y8.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/ch2_enc&lt;7&gt;</twComp><twBEL>tx_dvi/enc2/st1_qm_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y8.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.137</twDelInfo><twComp>tx_dvi/ch2_enc&lt;6&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X20Y8.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;7&gt;</twComp><twBEL>tx_dvi/ch2_enc_r_6</twBEL></twPathDel><twLogDel>0.246</twLogDel><twRouteDel>0.137</twRouteDel><twTotDel>0.383</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>64.2</twPctLog><twPctRoute>35.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/ch0_enc_r_6 (SLICE_X20Y19.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="105"><twConstPath anchorID="106" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.381</twSlack><twSrc BELType="FF">tx_dvi/enc0/st1_qm_r_6</twSrc><twDest BELType="FF">tx_dvi/ch0_enc_r_6</twDest><twTotPathDel>0.383</twTotPathDel><twClkSkew dest = "0.041" src = "0.039">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st1_qm_r_6</twSrc><twDest BELType='FF'>tx_dvi/ch0_enc_r_6</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X21Y19.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X21Y19.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/ch0_enc&lt;7&gt;</twComp><twBEL>tx_dvi/enc0/st1_qm_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y19.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.137</twDelInfo><twComp>tx_dvi/ch0_enc&lt;6&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X20Y19.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>tx_dvi/ch0_enc_r&lt;7&gt;</twComp><twBEL>tx_dvi/ch0_enc_r_6</twBEL></twPathDel><twLogDel>0.246</twLogDel><twRouteDel>0.137</twRouteDel><twTotDel>0.383</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>64.2</twPctLog><twPctRoute>35.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/ch1_enc_r_2 (SLICE_X28Y11.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="107"><twConstPath anchorID="108" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.381</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_qm_r_2</twSrc><twDest BELType="FF">tx_dvi/ch1_enc_r_2</twDest><twTotPathDel>0.383</twTotPathDel><twClkSkew dest = "0.039" src = "0.037">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_qm_r_2</twSrc><twDest BELType='FF'>tx_dvi/ch1_enc_r_2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X29Y11.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X29Y11.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/ch1_enc&lt;3&gt;</twComp><twBEL>tx_dvi/enc1/st1_qm_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y11.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.137</twDelInfo><twComp>tx_dvi/ch1_enc&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X28Y11.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>tx_dvi/ch1_enc_r&lt;3&gt;</twComp><twBEL>tx_dvi/ch1_enc_r_2</twBEL></twPathDel><twLogDel>0.246</twLogDel><twRouteDel>0.137</twRouteDel><twTotDel>0.383</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>64.2</twPctLog><twPctRoute>35.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="109"><twPinLimitBanner>Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk / 1.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="110" type="MINPERIOD" name="Trper_CLKB(Fmax)" slack="12.430" period="16.000" constraintValue="16.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" locationPin="RAMB16_X0Y20.CLKB" clockNet="CLK63"/><twPinLimit anchorID="111" type="MINPERIOD" name="Trper_CLKB(Fmax)" slack="12.430" period="16.000" constraintValue="16.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" locationPin="RAMB16_X0Y18.CLKB" clockNet="CLK63"/><twPinLimit anchorID="112" type="MINPERIOD" name="Tbcper_I" slack="13.730" period="16.000" constraintValue="16.000" deviceLimit="2.270" freqLimit="440.529" physResource="clk_wiz_v1_6_50x62x312/clkout1_buf/I0" logResource="clk_wiz_v1_6_50x62x312/clkout1_buf/I0" locationPin="BUFGMUX_X3Y5.I0" clockNet="clk_wiz_v1_6_50x62x312/clkout0"/></twPinLimitRpt></twConst><twConst anchorID="113" twConstType="PERIOD" ><twConstHead uID="11"><twConstName UCFConstName="" ScopeName="">TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCM&quot; TS_GTPCLKOUT1_0_ HIGH 50%;</twConstName><twItemCnt>12309</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>1</twErrCntPinLimit><twEndPtCnt>6683</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>6.400</twMinPer></twConstHead><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/crtc_data_dl2_r_22_BRB3 (SLICE_X18Y44.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="114"><twConstPath anchorID="115" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.052</twSlack><twSrc BELType="FF">dp_main/dp_main_crtc/disp_dclk_sync_r</twSrc><twDest BELType="FF">crtc2/crtc_data_dl2_r_22_BRB3</twDest><twTotPathDel>6.053</twTotPathDel><twClkSkew dest = "0.603" src = "0.635">0.032</twClkSkew><twDelConst>6.172</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_crtc/disp_dclk_sync_r</twSrc><twDest BELType='FF'>crtc2/crtc_data_dl2_r_22_BRB3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X36Y74.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X36Y74.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>TX2_CLK</twComp><twBEL>dp_main/dp_main_crtc/disp_dclk_sync_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y52.D6</twSite><twDelType>net</twDelType><twFanCnt>95</twFanCnt><twDelInfo twEdge="twRising">3.364</twDelInfo><twComp>TX2_CLK</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y52.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/crtc_ctrl_dl1_r&lt;2&gt;</twComp><twBEL>lut6584_958</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y44.CE</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.641</twDelInfo><twComp>lut6584_958</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y44.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.313</twDelInfo><twComp>crtc2/crtc_data_dl2_r_19_BRB3</twComp><twBEL>crtc2/crtc_data_dl2_r_22_BRB3</twBEL></twPathDel><twLogDel>1.048</twLogDel><twRouteDel>5.005</twRouteDel><twTotDel>6.053</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.172">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>17.3</twPctLog><twPctRoute>82.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="116"><twConstPath anchorID="117" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.576</twSlack><twSrc BELType="FF">crtc2/crtc_cclk_r</twSrc><twDest BELType="FF">crtc2/crtc_data_dl2_r_22_BRB3</twDest><twTotPathDel>3.512</twTotPathDel><twClkSkew dest = "0.511" src = "0.560">0.049</twClkSkew><twDelConst>6.172</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/crtc_cclk_r</twSrc><twDest BELType='FF'>crtc2/crtc_data_dl2_r_22_BRB3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X17Y52.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X17Y52.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>crtc2/crtc_cclk_r</twComp><twBEL>crtc2/crtc_cclk_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y52.D5</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.869</twDelInfo><twComp>crtc2/crtc_cclk_r</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y52.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/crtc_ctrl_dl1_r&lt;2&gt;</twComp><twBEL>lut6584_958</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y44.CE</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.641</twDelInfo><twComp>lut6584_958</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y44.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.313</twDelInfo><twComp>crtc2/crtc_data_dl2_r_19_BRB3</twComp><twBEL>crtc2/crtc_data_dl2_r_22_BRB3</twBEL></twPathDel><twLogDel>1.002</twLogDel><twRouteDel>2.510</twRouteDel><twTotDel>3.512</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.172">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>28.5</twPctLog><twPctRoute>71.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/tbc_data00_out_r_48 (SLICE_X44Y81.D4), 1 path
</twPathRptBanner><twPathRpt anchorID="118"><twConstPath anchorID="119" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.070</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_data_req_r</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_data00_out_r_48</twDest><twTotPathDel>6.017</twTotPathDel><twClkSkew dest = "0.583" src = "0.633">0.050</twClkSkew><twDelConst>6.172</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_data_req_r</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_data00_out_r_48</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X38Y54.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X38Y54.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_req_r</twComp><twBEL>dp_main/dp_main_tbc/tbc_data_req_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X44Y81.D4</twSite><twDelType>net</twDelType><twFanCnt>338</twFanCnt><twDelInfo twEdge="twRising">5.153</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_req_r</twComp></twPathDel><twPathDel><twSite>SLICE_X44Y81.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_out_r&lt;48&gt;</twComp><twBEL>lut20746_3717</twBEL><twBEL>dp_main/dp_main_tbc/tbc_data00_out_r_48</twBEL></twPathDel><twLogDel>0.864</twLogDel><twRouteDel>5.153</twRouteDel><twTotDel>6.017</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.172">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>14.4</twPctLog><twPctRoute>85.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/crtc_data_dl2_r_18_BRB3 (SLICE_X18Y44.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="120"><twConstPath anchorID="121" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.077</twSlack><twSrc BELType="FF">dp_main/dp_main_crtc/disp_dclk_sync_r</twSrc><twDest BELType="FF">crtc2/crtc_data_dl2_r_18_BRB3</twDest><twTotPathDel>6.028</twTotPathDel><twClkSkew dest = "0.603" src = "0.635">0.032</twClkSkew><twDelConst>6.172</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_crtc/disp_dclk_sync_r</twSrc><twDest BELType='FF'>crtc2/crtc_data_dl2_r_18_BRB3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X36Y74.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X36Y74.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>TX2_CLK</twComp><twBEL>dp_main/dp_main_crtc/disp_dclk_sync_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y52.D6</twSite><twDelType>net</twDelType><twFanCnt>95</twFanCnt><twDelInfo twEdge="twRising">3.364</twDelInfo><twComp>TX2_CLK</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y52.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/crtc_ctrl_dl1_r&lt;2&gt;</twComp><twBEL>lut6584_958</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y44.CE</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.641</twDelInfo><twComp>lut6584_958</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y44.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.288</twDelInfo><twComp>crtc2/crtc_data_dl2_r_19_BRB3</twComp><twBEL>crtc2/crtc_data_dl2_r_18_BRB3</twBEL></twPathDel><twLogDel>1.023</twLogDel><twRouteDel>5.005</twRouteDel><twTotDel>6.028</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.172">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>17.0</twPctLog><twPctRoute>83.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="122"><twConstPath anchorID="123" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.601</twSlack><twSrc BELType="FF">crtc2/crtc_cclk_r</twSrc><twDest BELType="FF">crtc2/crtc_data_dl2_r_18_BRB3</twDest><twTotPathDel>3.487</twTotPathDel><twClkSkew dest = "0.511" src = "0.560">0.049</twClkSkew><twDelConst>6.172</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/crtc_cclk_r</twSrc><twDest BELType='FF'>crtc2/crtc_data_dl2_r_18_BRB3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X17Y52.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X17Y52.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>crtc2/crtc_cclk_r</twComp><twBEL>crtc2/crtc_cclk_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y52.D5</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">0.869</twDelInfo><twComp>crtc2/crtc_cclk_r</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y52.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/crtc_ctrl_dl1_r&lt;2&gt;</twComp><twBEL>lut6584_958</twBEL></twPathDel><twPathDel><twSite>SLICE_X18Y44.CE</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.641</twDelInfo><twComp>lut6584_958</twComp></twPathDel><twPathDel><twSite>SLICE_X18Y44.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.288</twDelInfo><twComp>crtc2/crtc_data_dl2_r_19_BRB3</twComp><twBEL>crtc2/crtc_data_dl2_r_18_BRB3</twBEL></twPathDel><twLogDel>0.977</twLogDel><twRouteDel>2.510</twRouteDel><twTotDel>3.487</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.172">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>28.0</twPctLog><twPctRoute>72.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCM&quot; TS_GTPCLKOUT1_0_ HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y22.DIA0), 1 path
</twPathRptBanner><twPathRpt anchorID="124"><twConstPath anchorID="125" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.295</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tx_data00_in_r_0</twSrc><twDest BELType="RAM">dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twTotPathDel>0.298</twTotPathDel><twClkSkew dest = "0.077" src = "0.074">-0.003</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tx_data00_in_r_0</twSrc><twDest BELType='RAM'>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X40Y45.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X40Y45.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data00_in_r&lt;3&gt;</twComp><twBEL>dp_main/dp_main_tbc/tx_data00_in_r_0</twBEL></twPathDel><twPathDel><twSite>RAMB16_X2Y22.DIA0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.151</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data00_in_r&lt;0&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X2Y22.CLKA</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.053</twDelInfo><twComp>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twComp><twBEL>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twLogDel>0.147</twLogDel><twRouteDel>0.151</twRouteDel><twTotDel>0.298</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.172">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>49.3</twPctLog><twPctRoute>50.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y22.DIA23), 1 path
</twPathRptBanner><twPathRpt anchorID="126"><twConstPath anchorID="127" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.295</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tx_data01_in_r_1</twSrc><twDest BELType="RAM">dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twTotPathDel>0.296</twTotPathDel><twClkSkew dest = "0.077" src = "0.076">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tx_data01_in_r_1</twSrc><twDest BELType='RAM'>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X41Y47.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X41Y47.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data01_in_r&lt;3&gt;</twComp><twBEL>dp_main/dp_main_tbc/tx_data01_in_r_1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X2Y22.DIA23</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.151</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data01_in_r&lt;1&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X2Y22.CLKA</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.053</twDelInfo><twComp>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twComp><twBEL>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twLogDel>0.145</twLogDel><twRouteDel>0.151</twRouteDel><twTotDel>0.296</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.172">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>49.0</twPctLog><twPctRoute>51.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X3Y26.DIA23), 1 path
</twPathRptBanner><twPathRpt anchorID="128"><twConstPath anchorID="129" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.298</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tx_data02_in_r_13</twSrc><twDest BELType="RAM">dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twTotPathDel>0.304</twTotPathDel><twClkSkew dest = "0.069" src = "0.063">-0.006</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tx_data02_in_r_13</twSrc><twDest BELType='RAM'>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X53Y54.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X53Y54.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data02_in_r&lt;15&gt;</twComp><twBEL>dp_main/dp_main_tbc/tx_data02_in_r_13</twBEL></twPathDel><twPathDel><twSite>RAMB16_X3Y26.DIA23</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.159</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data02_in_r&lt;13&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X3Y26.CLKA</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.053</twDelInfo><twComp>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twComp><twBEL>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twLogDel>0.145</twLogDel><twRouteDel>0.159</twRouteDel><twTotDel>0.304</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.172">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>47.7</twPctLog><twPctRoute>52.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="130"><twPinLimitBanner>Component Switching Limit Checks: TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCM&quot; TS_GTPCLKOUT1_0_ HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="131" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="-0.228" period="6.172" constraintValue="6.172" deviceLimit="6.400" freqLimit="156.250" physResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21" logResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21" locationPin="GTPA1_DUAL_X1Y0.TXUSRCLK21" clockNet="GTPCLKOUT1_DCMx1"/><twPinLimit anchorID="132" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="2.602" period="6.172" constraintValue="6.172" deviceLimit="3.570" freqLimit="280.112" physResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X3Y24.CLKA" clockNet="GTPCLKOUT1_DCMx1"/><twPinLimit anchorID="133" type="MINPERIOD" name="Trper_CLKB(Fmax)" slack="2.602" period="6.172" constraintValue="6.172" deviceLimit="3.570" freqLimit="280.112" physResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" logResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" locationPin="RAMB16_X3Y24.CLKB" clockNet="GTPCLKOUT1_DCMx1"/></twPinLimitRpt></twConst><twConst anchorID="134" twConstType="PERIOD" ><twConstHead uID="12"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_gt_refclk_buf = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_gt_refclk_buf&quot;         TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.334</twMinPer></twConstHead><twPinLimitRpt anchorID="135"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_gt_refclk_buf = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_gt_refclk_buf&quot;
        TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="136" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="2.249" period="3.200" constraintValue="3.200" deviceLimit="0.951" freqLimit="1051.525" physResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKOUT0" logResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y2.CLKOUT0" clockNet="inst_sp6wrap/eptest_i/clk_250"/><twPinLimit anchorID="137" type="MINLOWPULSE" name="Tdcmpw_CLKIN_100_150" slack="4.666" period="8.000" constraintValue="4.000" deviceLimit="1.667" physResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1" logResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y2.CLKIN1" clockNet="inst_sp6wrap/eptest_i/gt_refclk_buf"/><twPinLimit anchorID="138" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_100_150" slack="4.666" period="8.000" constraintValue="4.000" deviceLimit="1.667" physResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1" logResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y2.CLKIN1" clockNet="inst_sp6wrap/eptest_i/gt_refclk_buf"/></twPinLimitRpt></twConst><twConst anchorID="139" twConstType="PERIOD" ><twConstHead uID="13"><twConstName UCFConstName="" ScopeName="">TS_ctm_27x162_clkfx = PERIOD TIMEGRP &quot;ctm_27x162_clkfx&quot; TS_DP_CLK1 * 6 HIGH         50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.200</twMinPer></twConstHead><twPinLimitRpt anchorID="140"><twPinLimitBanner>Component Switching Limit Checks: TS_ctm_27x162_clkfx = PERIOD TIMEGRP &quot;ctm_27x162_clkfx&quot; TS_DP_CLK1 * 6 HIGH
        50%;</twPinLimitBanner><twPinLimit anchorID="141" type="MINPERIOD" name="Tgtpcper_GCLK" slack="2.972" period="6.172" constraintValue="6.172" deviceLimit="3.200" freqLimit="312.500" physResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01" logResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01" locationPin="GTPA1_DUAL_X1Y0.GCLK01" clockNet="PLL162"/><twPinLimit anchorID="142" type="MINPERIOD" name="Tbcper_I" slack="3.902" period="6.172" constraintValue="6.172" deviceLimit="2.270" freqLimit="440.529" physResource="ctm_27x162/clkout1_buf/I0" logResource="ctm_27x162/clkout1_buf/I0" locationPin="BUFGMUX_X2Y11.I0" clockNet="ctm_27x162/clkfx"/></twPinLimitRpt></twConst><twConst anchorID="143" twConstType="PERIOD" ><twConstHead uID="14"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in&quot; TS_SYS_CLK3 / 0.25         HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.270</twMinPer></twConstHead><twPinLimitRpt anchorID="144"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in&quot; TS_SYS_CLK3 / 0.25
        HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="145" type="MINPERIOD" name="Tbcper_I" slack="17.730" period="20.000" constraintValue="20.000" deviceLimit="2.270" freqLimit="440.529" physResource="memc3_infrastructure_inst/U_BUFG_CLK1/I0" logResource="memc3_infrastructure_inst/U_BUFG_CLK1/I0" locationPin="BUFGMUX_X3Y8.I0" clockNet="memc3_infrastructure_inst/mcb_drp_clk_bufg_in"/><twPinLimit anchorID="146" type="MINPERIOD" name="Tcp" slack="18.601" period="20.000" constraintValue="20.000" deviceLimit="1.399" freqLimit="714.796" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1/CLK" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2/CLK" locationPin="SLICE_X26Y83.CLK" clockNet="c3_mcb_drp_clk"/><twPinLimit anchorID="147" type="MINPERIOD" name="Tmcbcper_UICLK" slack="19.000" period="20.000" constraintValue="20.000" deviceLimit="1.000" freqLimit="1000.000" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK" locationPin="MCB_X0Y1.UICLK" clockNet="c3_mcb_drp_clk"/></twPinLimitRpt></twConst><twConst anchorID="148" twConstType="PERIOD" ><twConstHead uID="15"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_180&quot; TS_SYS_CLK3 / 2 PHASE 1.25 ns         HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.499</twMinPer></twConstHead><twPinLimitRpt anchorID="149"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk_2x_180&quot; TS_SYS_CLK3 / 2 PHASE 1.25 ns
        HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="150" type="MINPERIOD" name="Tmcbcper_PLLCLK" slack="1.001" period="2.500" constraintValue="2.500" deviceLimit="1.499" freqLimit="667.111" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1" locationPin="MCB_X0Y1.PLLCLK1" clockNet="c3_sysclk_2x_180"/></twPinLimitRpt></twConst><twConst anchorID="151" twConstType="PERIOD" ><twConstHead uID="16"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_0&quot; TS_SYS_CLK3 / 2 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.499</twMinPer></twConstHead><twPinLimitRpt anchorID="152"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk_2x_0&quot; TS_SYS_CLK3 / 2 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="153" type="MINPERIOD" name="Tmcbcper_PLLCLK" slack="1.001" period="2.500" constraintValue="2.500" deviceLimit="1.499" freqLimit="667.111" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0" locationPin="MCB_X0Y1.PLLCLK0" clockNet="c3_sysclk_2x"/></twPinLimitRpt></twConst><twConst anchorID="154" twConstType="PERIOD" ><twConstHead uID="17"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk0_bufg_in&quot; TS_SYS_CLK3 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.570</twMinPer></twConstHead><twPinLimitRpt anchorID="155"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk0_bufg_in&quot; TS_SYS_CLK3 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="156" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y20.CLKA" clockNet="c3_clk0"/><twPinLimit anchorID="157" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y18.CLKA" clockNet="c3_clk0"/><twPinLimit anchorID="158" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y24.CLKA" clockNet="c3_clk0"/></twPinLimitRpt></twConst><twConst anchorID="159" twConstType="PERIOD" ><twConstHead uID="18"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0&quot;         TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;</twConstName><twItemCnt>30415</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1292</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>13.340</twMinPer></twConstHead><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15 (SLICE_X38Y85.SR), 2 paths
</twPathRptBanner><twPathRpt anchorID="160"><twConstPath anchorID="161" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.665</twSlack><twSrc BELType="FF">memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15</twDest><twTotPathDel>2.950</twTotPathDel><twClkSkew dest = "2.052" src = "2.223">0.171</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.214</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X24Y83.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="15.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X24Y83.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp><twBEL>memc3_infrastructure_inst/powerup_pll_locked</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y83.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.448</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y83.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y85.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.546</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y85.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.221</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor&lt;15&gt;_rt</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15</twBEL></twPathDel><twLogDel>0.956</twLogDel><twRouteDel>1.994</twRouteDel><twTotDel>2.950</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>32.4</twPctLog><twPctRoute>67.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="162"><twConstPath anchorID="163" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.586</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15</twDest><twTotPathDel>3.266</twTotPathDel><twClkSkew dest = "0.485" src = "0.539">0.054</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.094</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X24Y82.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X24Y82.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y83.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.764</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y83.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y85.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.546</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y85.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.221</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor&lt;15&gt;_rt</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_15</twBEL></twPathDel><twLogDel>0.956</twLogDel><twRouteDel>2.310</twRouteDel><twTotDel>3.266</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>29.3</twPctLog><twPctRoute>70.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14 (SLICE_X38Y85.SR), 2 paths
</twPathRptBanner><twPathRpt anchorID="164"><twConstPath anchorID="165" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.674</twSlack><twSrc BELType="FF">memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14</twDest><twTotPathDel>2.941</twTotPathDel><twClkSkew dest = "2.052" src = "2.223">0.171</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.214</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X24Y83.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="15.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X24Y83.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp><twBEL>memc3_infrastructure_inst/powerup_pll_locked</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y83.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.448</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y83.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y85.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.546</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y85.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.212</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor&lt;15&gt;_rt</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14</twBEL></twPathDel><twLogDel>0.947</twLogDel><twRouteDel>1.994</twRouteDel><twTotDel>2.941</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>32.2</twPctLog><twPctRoute>67.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="166"><twConstPath anchorID="167" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.595</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14</twDest><twTotPathDel>3.257</twTotPathDel><twClkSkew dest = "0.485" src = "0.539">0.054</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.094</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X24Y82.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X24Y82.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y83.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.764</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y83.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y85.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.546</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y85.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.212</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor&lt;15&gt;_rt</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_14</twBEL></twPathDel><twLogDel>0.947</twLogDel><twRouteDel>2.310</twRouteDel><twTotDel>3.257</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>29.1</twPctLog><twPctRoute>70.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13 (SLICE_X38Y85.SR), 2 paths
</twPathRptBanner><twPathRpt anchorID="168"><twConstPath anchorID="169" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.685</twSlack><twSrc BELType="FF">memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13</twDest><twTotPathDel>2.930</twTotPathDel><twClkSkew dest = "2.052" src = "2.223">0.171</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.214</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X24Y83.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="15.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X24Y83.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp><twBEL>memc3_infrastructure_inst/powerup_pll_locked</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y83.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.448</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y83.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y85.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.546</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y85.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.201</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor&lt;15&gt;_rt</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13</twBEL></twPathDel><twLogDel>0.936</twLogDel><twRouteDel>1.994</twRouteDel><twTotDel>2.930</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>31.9</twPctLog><twPctRoute>68.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="170"><twConstPath anchorID="171" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.606</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13</twDest><twTotPathDel>3.246</twTotPathDel><twClkSkew dest = "0.485" src = "0.539">0.054</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.094</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X24Y82.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X24Y82.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y83.B1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.764</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y83.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y85.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.546</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y85.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.201</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mcount_WAIT_200us_COUNTER_xor&lt;15&gt;_rt</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_13</twBEL></twPathDel><twLogDel>0.936</twLogDel><twRouteDel>2.310</twRouteDel><twTotDel>3.246</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>28.8</twPctLog><twPctRoute>71.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0&quot;
        TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3 (SLICE_X10Y41.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="172"><twConstPath anchorID="173" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.414</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd5</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3</twDest><twTotPathDel>0.416</twTotPathDel><twClkSkew dest = "0.033" src = "0.031">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd5</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X11Y41.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X11Y41.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3-In</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd5</twBEL></twPathDel><twPathDel><twSite>SLICE_X10Y41.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.177</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3-In</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X10Y41.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.041</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd2-In</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/state_FSM_FFd3</twBEL></twPathDel><twLogDel>0.239</twLogDel><twRouteDel>0.177</twRouteDel><twTotDel>0.416</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>57.5</twPctLog><twPctRoute>42.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9 (SLICE_X40Y82.A6), 1 path
</twPathRptBanner><twPathRpt anchorID="174"><twConstPath anchorID="175" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.414</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9</twDest><twTotPathDel>0.414</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X40Y82.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X40Y82.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter&lt;9&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y82.A6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.024</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter&lt;9&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X40Y82.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter&lt;9&gt;</twComp><twBEL>lut31066_6707</twBEL><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_9</twBEL></twPathDel><twLogDel>0.390</twLogDel><twRouteDel>0.024</twRouteDel><twTotDel>0.414</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>94.2</twPctLog><twPctRoute>5.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN (SLICE_X4Y56.A6), 1 path
</twPathRptBanner><twPathRpt anchorID="176"><twConstPath anchorID="177" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.418</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN</twDest><twTotPathDel>0.418</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X4Y56.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X4Y56.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/mcb_ui_cmd_en</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN</twBEL></twPathDel><twPathDel><twSite>SLICE_X4Y56.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/mcb_ui_cmd_en</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X4Y56.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/mcb_ui_cmd_en</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN_rstpot</twBEL><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN</twBEL></twPathDel><twLogDel>0.390</twLogDel><twRouteDel>0.028</twRouteDel><twTotDel>0.418</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>93.3</twPctLog><twPctRoute>6.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="178"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0&quot;
        TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="179" type="MINPERIOD" name="Tbcper_I" slack="17.730" period="20.000" constraintValue="20.000" deviceLimit="2.270" freqLimit="440.529" physResource="memc3_infrastructure_inst/U_BUFG_CLK1/I0" logResource="memc3_infrastructure_inst/U_BUFG_CLK1/I0" locationPin="BUFGMUX_X3Y8.I0" clockNet="memc3_infrastructure_inst/mcb_drp_clk_bufg_in"/><twPinLimit anchorID="180" type="MINPERIOD" name="Tcp" slack="18.601" period="20.000" constraintValue="20.000" deviceLimit="1.399" freqLimit="714.796" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1/CLK" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2/CLK" locationPin="SLICE_X26Y83.CLK" clockNet="c3_mcb_drp_clk"/><twPinLimit anchorID="181" type="MINPERIOD" name="Tmcbcper_UICLK" slack="19.000" period="20.000" constraintValue="20.000" deviceLimit="1.000" freqLimit="1000.000" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK" locationPin="MCB_X0Y1.UICLK" clockNet="c3_mcb_drp_clk"/></twPinLimitRpt></twConst><twConst anchorID="182" twConstType="PERIOD" ><twConstHead uID="19"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk_2x_180_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_180_0&quot; TS_clk_wiz_v1_6_50x200_clkfx         / 2 PHASE 1.25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.499</twMinPer></twConstHead><twPinLimitRpt anchorID="183"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_180_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk_2x_180_0&quot; TS_clk_wiz_v1_6_50x200_clkfx
        / 2 PHASE 1.25 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="184" type="MINPERIOD" name="Tmcbcper_PLLCLK" slack="1.001" period="2.500" constraintValue="2.500" deviceLimit="1.499" freqLimit="667.111" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1" locationPin="MCB_X0Y1.PLLCLK1" clockNet="c3_sysclk_2x_180"/></twPinLimitRpt></twConst><twConst anchorID="185" twConstType="PERIOD" ><twConstHead uID="20"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk_2x_0_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_0_0&quot; TS_clk_wiz_v1_6_50x200_clkfx /         2 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.499</twMinPer></twConstHead><twPinLimitRpt anchorID="186"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_0_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk_2x_0_0&quot; TS_clk_wiz_v1_6_50x200_clkfx /
        2 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="187" type="MINPERIOD" name="Tmcbcper_PLLCLK" slack="1.001" period="2.500" constraintValue="2.500" deviceLimit="1.499" freqLimit="667.111" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0" locationPin="MCB_X0Y1.PLLCLK0" clockNet="c3_sysclk_2x"/></twPinLimitRpt></twConst><twConst anchorID="188" twConstType="PERIOD" ><twConstHead uID="21"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk0_bufg_in_0&quot;         TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;</twConstName><twItemCnt>947</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>14</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">14</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>573</twEndPtCnt><twPathErrCnt>14</twPathErrCnt><twMinPer>4.927</twMinPer></twConstHead><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/fsmfake4_0 (SLICE_X0Y43.A6), 4 paths
</twPathRptBanner><twPathRpt anchorID="189"><twConstPath anchorID="190" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.073</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="FF">crtc2/fsmfake4_0</twDest><twTotPathDel>4.801</twTotPathDel><twClkSkew dest = "0.602" src = "0.653">0.051</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="19" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='FF'>crtc2/fsmfake4_0</twDest><twLogLvls>2</twLogLvls><twSrcSite>MCB_X0Y1.P5CMDCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>MCB_X0Y1.P5CMDEMPTY</twSite><twDelType>Tmcbcko_CMDEMPTY</twDelType><twDelInfo twEdge="twRising">1.080</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y49.A4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">2.553</twDelInfo><twComp>c3_p5_cmd_empty</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y49.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut9907_1662</twComp><twBEL>lut7295_1177</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.584</twDelInfo><twComp>lut7295_1177</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd22</twComp><twBEL>][6794_1180</twBEL><twBEL>crtc2/fsmfake4_0</twBEL></twPathDel><twLogDel>1.664</twLogDel><twRouteDel>3.137</twRouteDel><twTotDel>4.801</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>34.7</twPctLog><twPctRoute>65.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="191"><twConstPath anchorID="192" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.765</twSlack><twSrc BELType="FF">crtc2/fsmfake4_1</twSrc><twDest BELType="FF">crtc2/fsmfake4_0</twDest><twTotPathDel>3.156</twTotPathDel><twClkSkew dest = "0.162" src = "0.166">0.004</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/fsmfake4_1</twSrc><twDest BELType='FF'>crtc2/fsmfake4_0</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X0Y41.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X0Y41.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp><twBEL>crtc2/fsmfake4_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y49.A1</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.512</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y49.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut9907_1662</twComp><twBEL>lut7295_1177</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.584</twDelInfo><twComp>lut7295_1177</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd22</twComp><twBEL>][6794_1180</twBEL><twBEL>crtc2/fsmfake4_0</twBEL></twPathDel><twLogDel>1.060</twLogDel><twRouteDel>2.096</twRouteDel><twTotDel>3.156</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>33.6</twPctLog><twPctRoute>66.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="193"><twConstPath anchorID="194" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.233</twSlack><twSrc BELType="FF">crtc2/fsmfake4_0</twSrc><twDest BELType="FF">crtc2/fsmfake4_0</twDest><twTotPathDel>2.692</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/fsmfake4_0</twSrc><twDest BELType='FF'>crtc2/fsmfake4_0</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X0Y43.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X0Y43.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd22</twComp><twBEL>crtc2/fsmfake4_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y49.A5</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.048</twDelInfo><twComp>crtc2/fsmfake4&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y49.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>lut9907_1662</twComp><twBEL>lut7295_1177</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.584</twDelInfo><twComp>lut7295_1177</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd22</twComp><twBEL>][6794_1180</twBEL><twBEL>crtc2/fsmfake4_0</twBEL></twPathDel><twLogDel>1.060</twLogDel><twRouteDel>1.632</twRouteDel><twTotDel>2.692</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>39.4</twPctLog><twPctRoute>60.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X0Y24.DIA7), 1 path
</twPathRptBanner><twPathRpt anchorID="195"><twConstPath anchorID="196" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.121</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="RAM">crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twTotPathDel>4.814</twTotPathDel><twClkSkew dest = "0.538" src = "0.528">-0.010</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='RAM'>crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>MCB_X0Y1.P5CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>MCB_X0Y1.P5RDDATA7</twSite><twDelType>Tmcbcko_RDDATA</twDelType><twDelInfo twEdge="twRising">2.700</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>RAMB16_X0Y24.DIA7</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.814</twDelInfo><twComp>c3_p5_rd_data&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X0Y24.CLKA</twSite><twDelType>Trdck_DIA</twDelType><twDelInfo twEdge="twRising">0.300</twDelInfo><twComp>crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twComp><twBEL>crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twLogDel>3.000</twLogDel><twRouteDel>1.814</twRouteDel><twTotDel>4.814</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>62.3</twPctLog><twPctRoute>37.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="9" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/mem_state_r_FSM_FFd3_1 (SLICE_X1Y43.AX), 9 paths
</twPathRptBanner><twPathRpt anchorID="197"><twConstPath anchorID="198" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.126</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="FF">crtc2/mem_state_r_FSM_FFd3_1</twDest><twTotPathDel>4.793</twTotPathDel><twClkSkew dest = "0.252" src = "0.258">0.006</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='FF'>crtc2/mem_state_r_FSM_FFd3_1</twDest><twLogLvls>2</twLogLvls><twSrcSite>MCB_X0Y1.P5CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>MCB_X0Y1.P5EMPTY</twSite><twDelType>Tmcbcko_EMPTY</twDelType><twDelInfo twEdge="twRising">2.270</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.B4</twSite><twDelType>net</twDelType><twFanCnt>8</twFanCnt><twDelInfo twEdge="twRising">0.954</twDelInfo><twComp>c3_p5_rd_empty</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd3</twComp><twBEL>lut7021_1117</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.312</twDelInfo><twComp>lut7021_1117</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd3</twComp><twBEL>lut7022_1118</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.625</twDelInfo><twComp>lut7022_1118</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.114</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd3</twComp><twBEL>crtc2/mem_state_r_FSM_FFd3_1</twBEL></twPathDel><twLogDel>2.902</twLogDel><twRouteDel>1.891</twRouteDel><twTotDel>4.793</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>60.5</twPctLog><twPctRoute>39.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="199"><twConstPath anchorID="200" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.369</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="FF">crtc2/mem_state_r_FSM_FFd3_1</twDest><twTotPathDel>4.505</twTotPathDel><twClkSkew dest = "0.602" src = "0.653">0.051</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="19" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='FF'>crtc2/mem_state_r_FSM_FFd3_1</twDest><twLogLvls>1</twLogLvls><twSrcSite>MCB_X0Y1.P5CMDCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>MCB_X0Y1.P5CMDEMPTY</twSite><twDelType>Tmcbcko_CMDEMPTY</twDelType><twDelInfo twEdge="twRising">1.080</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">2.427</twDelInfo><twComp>c3_p5_cmd_empty</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd3</twComp><twBEL>lut7022_1118</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.625</twDelInfo><twComp>lut7022_1118</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.114</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd3</twComp><twBEL>crtc2/mem_state_r_FSM_FFd3_1</twBEL></twPathDel><twLogDel>1.453</twLogDel><twRouteDel>3.052</twRouteDel><twTotDel>4.505</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>32.3</twPctLog><twPctRoute>67.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="201"><twConstPath anchorID="202" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.965</twSlack><twSrc BELType="FF">crtc2/mem_init_done_r</twSrc><twDest BELType="FF">crtc2/mem_state_r_FSM_FFd3_1</twDest><twTotPathDel>3.906</twTotPathDel><twClkSkew dest = "0.510" src = "0.564">0.054</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/mem_init_done_r</twSrc><twDest BELType='FF'>crtc2/mem_state_r_FSM_FFd3_1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X10Y49.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X10Y49.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>crtc1/mem_init_done_r</twComp><twBEL>crtc2/mem_init_done_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.812</twDelInfo><twComp>crtc1/mem_init_done_r</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd3</twComp><twBEL>lut7021_1117</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.312</twDelInfo><twComp>lut7021_1117</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd3</twComp><twBEL>lut7022_1118</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.625</twDelInfo><twComp>lut7022_1118</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.114</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd3</twComp><twBEL>crtc2/mem_state_r_FSM_FFd3_1</twBEL></twPathDel><twLogDel>1.157</twLogDel><twRouteDel>2.749</twRouteDel><twTotDel>3.906</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>29.6</twPctLog><twPctRoute>70.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk0_bufg_in_0&quot;
        TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point crtc1/fb_rd_req_r_0 (SLICE_X22Y66.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="203"><twConstPath anchorID="204" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-7.234</twSlack><twSrc BELType="FF">crtc1/crtc_rd_reqf_r</twSrc><twDest BELType="FF">crtc1/fb_rd_req_r_0</twDest><twTotPathDel>1.053</twTotPathDel><twClkSkew dest = "10.939" src = "2.190">-8.749</twClkSkew><twDelConst>1.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.419" fPhaseErr="0.325" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.538</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc1/crtc_rd_reqf_r</twSrc><twDest BELType='FF'>crtc1/fb_rd_req_r_0</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X23Y66.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="64.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X23Y66.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.405</twDelInfo><twComp>crtc1/crtc_rd_reqf_r</twComp><twBEL>crtc1/crtc_rd_reqf_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y66.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.638</twDelInfo><twComp>crtc1/crtc_rd_reqf_r</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X22Y66.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.010</twDelInfo><twComp>crtc1/fb_rd_req_r&lt;3&gt;</twComp><twBEL>crtc1/fb_rd_req_r_0</twBEL></twPathDel><twLogDel>0.415</twLogDel><twRouteDel>0.638</twRouteDel><twTotDel>1.053</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="65.000">c3_clk0</twDestClk><twPctLog>39.4</twPctLog><twPctRoute>60.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point crtc1/fb_rd_addr_r_4 (SLICE_X14Y67.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="205"><twConstPath anchorID="206" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-6.829</twSlack><twSrc BELType="FF">crtc1/crtc_rd_vpos_r_4</twSrc><twDest BELType="FF">crtc1/fb_rd_addr_r_4</twDest><twTotPathDel>1.463</twTotPathDel><twClkSkew dest = "10.936" src = "2.182">-8.754</twClkSkew><twDelConst>1.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.419" fPhaseErr="0.325" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.538</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc1/crtc_rd_vpos_r_4</twSrc><twDest BELType='FF'>crtc1/fb_rd_addr_r_4</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X23Y70.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="64.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X23Y70.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.405</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;7&gt;</twComp><twBEL>crtc1/crtc_rd_vpos_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y67.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">1.048</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;4&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X14Y67.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.010</twDelInfo><twComp>crtc1/fb_rd_addr_r&lt;7&gt;</twComp><twBEL>crtc1/fb_rd_addr_r_4</twBEL></twPathDel><twLogDel>0.415</twLogDel><twRouteDel>1.048</twRouteDel><twTotDel>1.463</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="65.000">c3_clk0</twDestClk><twPctLog>28.4</twPctLog><twPctRoute>71.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point crtc1/fb_rd_addr_r_11 (SLICE_X14Y70.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="207"><twConstPath anchorID="208" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-6.773</twSlack><twSrc BELType="FF">crtc1/crtc_rd_vpos_r_11</twSrc><twDest BELType="FF">crtc1/fb_rd_addr_r_11</twDest><twTotPathDel>1.514</twTotPathDel><twClkSkew dest = "10.929" src = "2.180">-8.749</twClkSkew><twDelConst>1.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.419" fPhaseErr="0.325" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.538</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc1/crtc_rd_vpos_r_11</twSrc><twDest BELType='FF'>crtc1/fb_rd_addr_r_11</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X22Y71.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="64.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X22Y71.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.495</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;11&gt;</twComp><twBEL>crtc1/crtc_rd_vpos_r_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y70.DX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">1.009</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;11&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X14Y70.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.010</twDelInfo><twComp>crtc1/fb_rd_addr_r&lt;11&gt;</twComp><twBEL>crtc1/fb_rd_addr_r_11</twBEL></twPathDel><twLogDel>0.505</twLogDel><twRouteDel>1.009</twRouteDel><twTotDel>1.514</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="65.000">c3_clk0</twDestClk><twPctLog>33.4</twPctLog><twPctRoute>66.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="209"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk0_bufg_in_0&quot;
        TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="210" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y20.CLKA" clockNet="c3_clk0"/><twPinLimit anchorID="211" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y18.CLKA" clockNet="c3_clk0"/><twPinLimit anchorID="212" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y24.CLKA" clockNet="c3_clk0"/></twPinLimitRpt></twConst><twConst anchorID="213" twConstType="PERIOD" ><twConstHead uID="22"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_125&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf         / 1.25 HIGH 50%;</twConstName><twItemCnt>45</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>1</twErrCntPinLimit><twEndPtCnt>45</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>8.000</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXCHARISKB0), 1 path
</twPathRptBanner><twPathRpt anchorID="214"><twConstPath anchorID="215" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.312</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>3.885</twTotPathDel><twClkSkew dest = "0.496" src = "0.606">0.110</twClkSkew><twDelConst>6.400</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.172" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.093</twClkUncert><twDetPath maxSiteLen="27" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXCHARISK11</twSite><twDelType>Tgtpcko_RXCHARISK</twDelType><twDelInfo twEdge="twRising">1.220</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXCHARISKB0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.225</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_char_is_k&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcicck_MGT</twDelType><twDelInfo twEdge="twRising">1.440</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>2.660</twLogDel><twRouteDel>1.225</twRouteDel><twTotDel>3.885</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>68.5</twPctLog><twPctRoute>31.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXSTATUSB1), 1 path
</twPathRptBanner><twPathRpt anchorID="216"><twConstPath anchorID="217" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.354</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>3.843</twTotPathDel><twClkSkew dest = "0.496" src = "0.606">0.110</twClkSkew><twDelConst>6.400</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.172" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.093</twClkUncert><twDetPath maxSiteLen="26" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXSTATUS11</twSite><twDelType>Tgtpcko_RXSTATUS</twDelType><twDelInfo twEdge="twRising">1.220</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXSTATUSB1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.183</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_status&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcicck_MGT</twDelType><twDelInfo twEdge="twRising">1.440</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>2.660</twLogDel><twRouteDel>1.183</twRouteDel><twTotDel>3.843</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>69.2</twPctLog><twPctRoute>30.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXSTATUSB2), 1 path
</twPathRptBanner><twPathRpt anchorID="218"><twConstPath anchorID="219" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.423</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>3.774</twTotPathDel><twClkSkew dest = "0.496" src = "0.606">0.110</twClkSkew><twDelConst>6.400</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.172" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.093</twClkUncert><twDetPath maxSiteLen="26" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXSTATUS12</twSite><twDelType>Tgtpcko_RXSTATUS</twDelType><twDelInfo twEdge="twRising">1.220</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXSTATUSB2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.114</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_status&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcicck_MGT</twDelType><twDelInfo twEdge="twRising">1.440</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>2.660</twLogDel><twRouteDel>1.114</twRouteDel><twTotDel>3.774</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>70.5</twPctLog><twPctRoute>29.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_125&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 1.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPEPHYSTATUSB), 1 path
</twPathRptBanner><twPathRpt anchorID="220"><twConstPath anchorID="221" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.129</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.056</twTotPathDel><twClkSkew dest = "0.201" src = "0.274">0.073</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="26" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.PHYSTATUS1</twSite><twDelType>Tgtpcko_PHYSTATUS</twDelType><twDelInfo twEdge="twFalling">0.565</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPEPHYSTATUSB</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.341</twDelInfo><twComp>inst_sp6wrap/eptest_i/phystatus</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcickc_MGT</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.285</twLogDel><twRouteDel>0.341</twRouteDel><twTotDel>0.056</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>-508.9</twPctLog><twPctRoute>608.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB0), 1 path
</twPathRptBanner><twPathRpt anchorID="222"><twConstPath anchorID="223" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.129</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.056</twTotPathDel><twClkSkew dest = "0.201" src = "0.274">0.073</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="24" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXDATA18</twSite><twDelType>Tgtpcko_RXDATA</twDelType><twDelInfo twEdge="twFalling">0.565</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXDATAB0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.341</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_data&lt;8&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcickc_MGT</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.285</twLogDel><twRouteDel>0.341</twRouteDel><twTotDel>0.056</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>-508.9</twPctLog><twPctRoute>608.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB1), 1 path
</twPathRptBanner><twPathRpt anchorID="224"><twConstPath anchorID="225" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.129</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.056</twTotPathDel><twClkSkew dest = "0.201" src = "0.274">0.073</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="24" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXDATA19</twSite><twDelType>Tgtpcko_RXDATA</twDelType><twDelInfo twEdge="twFalling">0.565</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXDATAB1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.341</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_data&lt;9&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcickc_MGT</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.285</twLogDel><twRouteDel>0.341</twRouteDel><twTotDel>0.056</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>-508.9</twPctLog><twPctRoute>608.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="226"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_125&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 1.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="227" type="MINPERIOD" name="Tpciper_MGTCLK" slack="-1.600" period="6.400" constraintValue="6.400" deviceLimit="8.000" freqLimit="125.000" physResource="inst_sp6wrap/eptest_i/PCIE_A1/MGTCLK" logResource="inst_sp6wrap/eptest_i/PCIE_A1/MGTCLK" locationPin="PCIE_X0Y0.MGTCLK" clockNet="inst_sp6wrap/eptest_i/mgt_clk"/><twPinLimit anchorID="228" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="6.400" constraintValue="6.400" deviceLimit="6.400" freqLimit="156.250" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK21" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK21" locationPin="GTPA1_DUAL_X0Y0.RXUSRCLK21" clockNet="inst_sp6wrap/eptest_i/mgt_clk"/><twPinLimit anchorID="229" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="0.000" period="6.400" constraintValue="6.400" deviceLimit="6.400" freqLimit="156.250" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK21" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK21" locationPin="GTPA1_DUAL_X0Y0.TXUSRCLK21" clockNet="inst_sp6wrap/eptest_i/mgt_clk"/></twPinLimitRpt></twConst><twConst anchorID="230" twConstType="PERIOD" ><twConstHead uID="23"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_250&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf         / 2.5 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.200</twMinPer></twConstHead><twPinLimitRpt anchorID="231"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_250&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 2.5 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="232" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="3.200" constraintValue="3.200" deviceLimit="3.200" freqLimit="312.500" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK1" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK1" locationPin="GTPA1_DUAL_X0Y0.RXUSRCLK1" clockNet="inst_sp6wrap/eptest_i/mgt_clk_2x"/><twPinLimit anchorID="233" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="0.000" period="3.200" constraintValue="3.200" deviceLimit="3.200" freqLimit="312.500" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK1" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK1" locationPin="GTPA1_DUAL_X0Y0.TXUSRCLK1" clockNet="inst_sp6wrap/eptest_i/mgt_clk_2x"/><twPinLimit anchorID="234" type="MINPERIOD" name="Tbcper_I" slack="0.930" period="3.200" constraintValue="3.200" deviceLimit="2.270" freqLimit="440.529" physResource="inst_sp6wrap/eptest_i/mgt2x_bufg/I0" logResource="inst_sp6wrap/eptest_i/mgt2x_bufg/I0" locationPin="BUFGMUX_X2Y9.I0" clockNet="inst_sp6wrap/eptest_i/clk_250"/></twPinLimitRpt></twConst><twConst anchorID="235" twConstType="PERIOD" ><twConstHead uID="24"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_62_5&quot;         TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;</twConstName><twItemCnt>9375</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>1</twErrCntPinLimit><twEndPtCnt>3865</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPathRptBanner iPaths="6" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/app/mem/mem_wr_data_out2_r_24 (SLICE_X36Y90.A2), 6 paths
</twPathRptBanner><twPathRpt anchorID="236"><twConstPath anchorID="237" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.463</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twDest><twTotPathDel>11.189</twTotPathDel><twClkSkew dest = "0.485" src = "0.528">0.043</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X24Y98.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X24Y98.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/tlp_type_iowr_r</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.B4</twSite><twDelType>net</twDelType><twFanCnt>65</twFanCnt><twDelInfo twEdge="twRising">4.343</twDelInfo><twComp>GPIO1C_28_OBUF</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35998_112</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.231</twDelInfo><twComp>lut35998_112</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.A2</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.272</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37052_8302</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twBEL></twPathDel><twLogDel>1.343</twLogDel><twRouteDel>9.846</twRouteDel><twTotDel>11.189</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>12.0</twPctLog><twPctRoute>88.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="238"><twConstPath anchorID="239" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.663</twSlack><twSrc BELType="FF">inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twDest><twTotPathDel>9.988</twTotPathDel><twClkSkew dest = "0.485" src = "0.529">0.044</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X7Y89.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X7Y89.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd4</twComp><twBEL>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y80.D4</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">1.762</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y80.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_mask1_r&lt;3&gt;</twComp><twBEL>lut35942_111</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">1.681</twDelInfo><twComp>lut35942_111</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.A2</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.272</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37052_8302</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twBEL></twPathDel><twLogDel>1.273</twLogDel><twRouteDel>8.715</twRouteDel><twTotDel>9.988</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>12.7</twPctLog><twPctRoute>87.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="240"><twConstPath anchorID="241" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.693</twSlack><twSrc BELType="FF">inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twDest><twTotPathDel>9.960</twTotPathDel><twClkSkew dest = "0.485" src = "0.527">0.042</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X6Y87.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X6Y87.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twComp><twBEL>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y80.D6</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">1.639</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y80.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_mask1_r&lt;3&gt;</twComp><twBEL>lut35942_111</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">1.681</twDelInfo><twComp>lut35942_111</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.A2</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.272</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37052_8302</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_24</twBEL></twPathDel><twLogDel>1.368</twLogDel><twRouteDel>8.592</twRouteDel><twTotDel>9.960</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>13.7</twPctLog><twPctRoute>86.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="6" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/app/mem/mem_wr_data_out2_r_26 (SLICE_X36Y90.C4), 6 paths
</twPathRptBanner><twPathRpt anchorID="242"><twConstPath anchorID="243" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.588</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twDest><twTotPathDel>11.064</twTotPathDel><twClkSkew dest = "0.485" src = "0.528">0.043</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X24Y98.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X24Y98.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/tlp_type_iowr_r</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.B4</twSite><twDelType>net</twDelType><twFanCnt>65</twFanCnt><twDelInfo twEdge="twRising">4.343</twDelInfo><twComp>GPIO1C_28_OBUF</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35998_112</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.231</twDelInfo><twComp>lut35998_112</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.C4</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.147</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37026_8298</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twBEL></twPathDel><twLogDel>1.343</twLogDel><twRouteDel>9.721</twRouteDel><twTotDel>11.064</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>12.1</twPctLog><twPctRoute>87.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="244"><twConstPath anchorID="245" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.788</twSlack><twSrc BELType="FF">inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twDest><twTotPathDel>9.863</twTotPathDel><twClkSkew dest = "0.485" src = "0.529">0.044</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X7Y89.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X7Y89.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd4</twComp><twBEL>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y80.D4</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">1.762</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y80.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_mask1_r&lt;3&gt;</twComp><twBEL>lut35942_111</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">1.681</twDelInfo><twComp>lut35942_111</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.C4</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.147</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37026_8298</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twBEL></twPathDel><twLogDel>1.273</twLogDel><twRouteDel>8.590</twRouteDel><twTotDel>9.863</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>12.9</twPctLog><twPctRoute>87.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="246"><twConstPath anchorID="247" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.818</twSlack><twSrc BELType="FF">inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twDest><twTotPathDel>9.835</twTotPathDel><twClkSkew dest = "0.485" src = "0.527">0.042</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X6Y87.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X6Y87.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twComp><twBEL>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y80.D6</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">1.639</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y80.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_mask1_r&lt;3&gt;</twComp><twBEL>lut35942_111</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">1.681</twDelInfo><twComp>lut35942_111</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.C4</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.147</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37026_8298</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_26</twBEL></twPathDel><twLogDel>1.368</twLogDel><twRouteDel>8.467</twRouteDel><twTotDel>9.835</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>13.9</twPctLog><twPctRoute>86.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="6" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/app/mem/mem_wr_data_out2_r_27 (SLICE_X36Y90.D4), 6 paths
</twPathRptBanner><twPathRpt anchorID="248"><twConstPath anchorID="249" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.677</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twDest><twTotPathDel>10.975</twTotPathDel><twClkSkew dest = "0.485" src = "0.528">0.043</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X24Y98.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X24Y98.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/tlp_type_iowr_r</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/wen_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.B4</twSite><twDelType>net</twDelType><twFanCnt>65</twFanCnt><twDelInfo twEdge="twRising">4.343</twDelInfo><twComp>GPIO1C_28_OBUF</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35998_112</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">0.231</twDelInfo><twComp>lut35998_112</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.D4</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.058</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37013_8296</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twBEL></twPathDel><twLogDel>1.343</twLogDel><twRouteDel>9.632</twRouteDel><twTotDel>10.975</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>12.2</twPctLog><twPctRoute>87.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="250"><twConstPath anchorID="251" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.877</twSlack><twSrc BELType="FF">inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twDest><twTotPathDel>9.774</twTotPathDel><twClkSkew dest = "0.485" src = "0.529">0.044</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X7Y89.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X7Y89.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd4</twComp><twBEL>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y80.D4</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">1.762</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd3</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y80.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_mask1_r&lt;3&gt;</twComp><twBEL>lut35942_111</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">1.681</twDelInfo><twComp>lut35942_111</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.D4</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.058</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37013_8296</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twBEL></twPathDel><twLogDel>1.273</twLogDel><twRouteDel>8.501</twRouteDel><twTotDel>9.774</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>13.0</twPctLog><twPctRoute>87.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="252"><twConstPath anchorID="253" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.907</twSlack><twSrc BELType="FF">inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twSrc><twDest BELType="FF">inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twDest><twTotPathDel>9.746</twTotPathDel><twClkSkew dest = "0.485" src = "0.527">0.042</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X6Y87.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X6Y87.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twComp><twBEL>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y80.D6</twSite><twDelType>net</twDelType><twFanCnt>40</twFanCnt><twDelInfo twEdge="twRising">1.639</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y80.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_mask1_r&lt;3&gt;</twComp><twBEL>lut35942_111</twBEL></twPathDel><twPathDel><twSite>SLICE_X3Y72.A4</twSite><twDelType>net</twDelType><twFanCnt>49</twFanCnt><twDelInfo twEdge="twRising">1.681</twDelInfo><twComp>lut35942_111</twComp></twPathDel><twPathDel><twSite>SLICE_X3Y72.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_req_out_r&lt;2&gt;</twComp><twBEL>lut35999_113</twBEL></twPathDel><twPathDel><twSite>SLICE_X36Y90.D4</twSite><twDelType>net</twDelType><twFanCnt>117</twFanCnt><twDelInfo twEdge="twRising">5.058</twDelInfo><twComp>lut35999_113</twComp></twPathDel><twPathDel><twSite>SLICE_X36Y90.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/app/mem/mem_wr_data_out2_r&lt;27&gt;</twComp><twBEL>lut37013_8296</twBEL><twBEL>inst_sp6wrap/app/mem/mem_wr_data_out2_r_27</twBEL></twPathDel><twLogDel>1.368</twLogDel><twRouteDel>8.378</twRouteDel><twTotDel>9.746</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>14.0</twPctLog><twPctRoute>86.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_62_5&quot;
        TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD21), 1 path
</twPathRptBanner><twPathRpt anchorID="254"><twConstPath anchorID="255" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.138</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_21</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.144</twTotPathDel><twClkSkew dest = "0.068" src = "0.062">-0.006</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_21</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X12Y105.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.800">pclk</twSrcClk><twPathDel><twSite>SLICE_X12Y105.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;19&gt;</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_21</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.TRNTD21</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.794</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;21&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.USERCLK</twSite><twDelType>Tpcickd_TRNTD</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.650</twLogDel><twRouteDel>0.794</twRouteDel><twTotDel>0.144</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>-451.4</twPctLog><twPctRoute>551.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD3), 1 path
</twPathRptBanner><twPathRpt anchorID="256"><twConstPath anchorID="257" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.228</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_3</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.225</twTotPathDel><twClkSkew dest = "0.068" src = "0.071">0.003</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_3</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X12Y99.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.800">pclk</twSrcClk><twPathDel><twSite>SLICE_X12Y99.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;4&gt;</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_3</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.TRNTD3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.875</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;3&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.USERCLK</twSite><twDelType>Tpcickd_TRNTD</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.650</twLogDel><twRouteDel>0.875</twRouteDel><twTotDel>0.225</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>-288.9</twPctLog><twPctRoute>388.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD18), 1 path
</twPathRptBanner><twPathRpt anchorID="258"><twConstPath anchorID="259" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.230</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_18</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.232</twTotPathDel><twClkSkew dest = "0.068" src = "0.066">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_18</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X24Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.800">pclk</twSrcClk><twPathDel><twSite>SLICE_X24Y101.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;18&gt;</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_18</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.TRNTD18</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.882</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;18&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.USERCLK</twSite><twDelType>Tpcickd_TRNTD</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.650</twLogDel><twRouteDel>0.882</twRouteDel><twTotDel>0.232</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>-280.2</twPctLog><twPctRoute>380.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="260"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_62_5&quot;
        TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="261" type="MINPERIOD" name="Tpciper_USERCLK" slack="-3.200" period="12.800" constraintValue="12.800" deviceLimit="16.000" freqLimit="62.500" physResource="inst_sp6wrap/eptest_i/PCIE_A1/USERCLK" logResource="inst_sp6wrap/eptest_i/PCIE_A1/USERCLK" locationPin="PCIE_X0Y0.USERCLK" clockNet="pclk"/><twPinLimit anchorID="262" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="9.230" period="12.800" constraintValue="12.800" deviceLimit="3.570" freqLimit="280.112" physResource="inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKA" logResource="inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKA" locationPin="RAMB16_X0Y52.CLKA" clockNet="pclk"/><twPinLimit anchorID="263" type="MINPERIOD" name="Trper_CLKB" slack="9.230" period="12.800" constraintValue="12.800" deviceLimit="3.570" freqLimit="280.112" physResource="inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKB" logResource="inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKB" locationPin="RAMB16_X0Y52.CLKB" clockNet="pclk"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="264"><twConstRollup name="TS_xtalclk" fullName="TS_xtalclk = PERIOD TIMEGRP &quot;xtalclk&quot; 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="8.000" actualRollup="19.708" errors="0" errorRollup="14" items="0" itemsRollup="53993"/><twConstRollup name="TS_clk_wiz_v1_6_50x200_clkfx" fullName="TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIMEGRP &quot;clk_wiz_v1_6_50x200_clkfx&quot;         TS_xtalclk / 4 HIGH 50%;" type="child" depth="1" requirement="5.000" prefType="period" actual="2.800" actualRollup="4.927" errors="0" errorRollup="14" items="0" itemsRollup="31362"/><twConstRollup name="TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0" fullName="TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0&quot;         TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;" type="child" depth="2" requirement="20.000" prefType="period" actual="13.340" actualRollup="N/A" errors="0" errorRollup="0" items="30415" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk_2x_180_0" fullName="TS_memc3_infrastructure_inst_clk_2x_180_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_180_0&quot; TS_clk_wiz_v1_6_50x200_clkfx         / 2 PHASE 1.25 ns HIGH 50%;" type="child" depth="2" requirement="2.500" prefType="period" actual="1.499" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk_2x_0_0" fullName="TS_memc3_infrastructure_inst_clk_2x_0_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_0_0&quot; TS_clk_wiz_v1_6_50x200_clkfx /         2 HIGH 50%;" type="child" depth="2" requirement="2.500" prefType="period" actual="1.499" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk0_bufg_in_0" fullName="TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk0_bufg_in_0&quot;         TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;" type="child" depth="2" requirement="5.000" prefType="period" actual="4.927" actualRollup="N/A" errors="14" errorRollup="0" items="947" itemsRollup="0"/><twConstRollup name="TS_clk_wiz_v1_6_50x62x312_clkout1" fullName="TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk / 6.25 HIGH 50%;" type="child" depth="1" requirement="3.200" prefType="period" actual="3.130" actualRollup="N/A" errors="0" errorRollup="0" items="133" itemsRollup="0"/><twConstRollup name="TS_clk_wiz_v1_6_50x62x312_clkout0" fullName="TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk / 1.25 HIGH 50%;" type="child" depth="1" requirement="16.000" prefType="period" actual="9.210" actualRollup="N/A" errors="0" errorRollup="0" items="22498" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="2" anchorID="265"><twConstRollup name="TS_GTPCLKOUT1_0_" fullName="TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP &quot;GTPCLKOUT1&lt;0&gt;&quot; 162 MHz HIGH 50%;" type="origin" depth="0" requirement="6.173" prefType="period" actual="1.904" actualRollup="6.400" errors="0" errorRollup="1" items="0" itemsRollup="12309"/><twConstRollup name="TS_GTPCLKOUT1_DCM" fullName="TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCM&quot; TS_GTPCLKOUT1_0_ HIGH 50%;" type="child" depth="1" requirement="6.173" prefType="period" actual="6.400" actualRollup="N/A" errors="1" errorRollup="0" items="12309" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="4" anchorID="266"><twConstRollup name="TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_" fullName="TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD TIMEGRP         &quot;inst_sp6wrap/eptest_i/gt_refclk_out&lt;0&gt;&quot; 8 ns HIGH 50%;" type="origin" depth="0" requirement="8.000" prefType="period" actual="1.904" actualRollup="10.000" errors="0" errorRollup="2" items="0" itemsRollup="9420"/><twConstRollup name="TS_inst_sp6wrap_eptest_i_gt_refclk_buf" fullName="TS_inst_sp6wrap_eptest_i_gt_refclk_buf = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_gt_refclk_buf&quot;         TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ HIGH 50%;" type="child" depth="1" requirement="8.000" prefType="period" actual="3.334" actualRollup="10.000" errors="0" errorRollup="2" items="0" itemsRollup="9420"/><twConstRollup name="TS_inst_sp6wrap_eptest_i_clk_125" fullName="TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_125&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf         / 1.25 HIGH 50%;" type="child" depth="2" requirement="6.400" prefType="period" actual="8.000" actualRollup="N/A" errors="1" errorRollup="0" items="45" itemsRollup="0"/><twConstRollup name="TS_inst_sp6wrap_eptest_i_clk_250" fullName="TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_250&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf         / 2.5 HIGH 50%;" type="child" depth="2" requirement="3.200" prefType="period" actual="3.200" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_inst_sp6wrap_eptest_i_clk_62_5" fullName="TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_62_5&quot;         TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;" type="child" depth="2" requirement="12.800" prefType="period" actual="16.000" actualRollup="N/A" errors="1" errorRollup="0" items="9375" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="5" anchorID="267"><twConstRollup name="TS_DP_CLK1" fullName="TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;" type="origin" depth="0" requirement="37.037" prefType="period" actual="16.000" actualRollup="19.200" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_ctm_27x162_clkfx" fullName="TS_ctm_27x162_clkfx = PERIOD TIMEGRP &quot;ctm_27x162_clkfx&quot; TS_DP_CLK1 * 6 HIGH         50%;" type="child" depth="1" requirement="6.173" prefType="period" actual="3.200" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="7" anchorID="268"><twConstRollup name="TS_SYS_CLK3" fullName="TS_SYS_CLK3 = PERIOD TIMEGRP &quot;SYS_CLK3&quot; 5 ns HIGH 50%;" type="origin" depth="0" requirement="5.000" prefType="period" actual="2.800" actualRollup="3.570" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in" fullName="TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in&quot; TS_SYS_CLK3 / 0.25         HIGH 50%;" type="child" depth="1" requirement="20.000" prefType="period" actual="2.270" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk_2x_180" fullName="TS_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_180&quot; TS_SYS_CLK3 / 2 PHASE 1.25 ns         HIGH 50%;" type="child" depth="1" requirement="2.500" prefType="period" actual="1.499" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk_2x_0" fullName="TS_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_0&quot; TS_SYS_CLK3 / 2 HIGH 50%;" type="child" depth="1" requirement="2.500" prefType="period" actual="1.499" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk0_bufg_in" fullName="TS_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk0_bufg_in&quot; TS_SYS_CLK3 HIGH 50%;" type="child" depth="1" requirement="5.000" prefType="period" actual="3.570" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="269">4</twUnmetConstCnt><twDataSheet anchorID="270" twNameLen="15"><twClk2SUList anchorID="271" twDestWidth="7"><twDest>DP_CLK0</twDest><twClk2SU><twSrc>DP_CLK0</twSrc><twRiseRise>8.392</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="272" twDestWidth="7"><twDest>xtalclk</twDest><twClk2SU><twSrc>xtalclk</twSrc><twRiseRise>10.846</twRiseRise><twRiseFall>1.354</twRiseFall></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="273"><twErrCnt>17</twErrCnt><twScore>97058</twScore><twSetupScore>0</twSetupScore><twHoldScore>92030</twHoldScore><twPinLimitScore>5028</twPinLimitScore><twConstCov><twPathCnt>78678</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>18250</twConnCnt></twConstCov><twStats anchorID="274"><twMinPer>16.000</twMinPer><twFootnote number="1" /><twMaxFreq>62.500</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>SAT 12 NOV 14:12:32 2011 </twTimestamp></twFoot><twClientInfo anchorID="275"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 208 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
