##############################################################
#
# Xilinx Core Generator version 11.1
# Date: Wed Mar 11 07:09:11 2009
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = verilog
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
# END Select
# BEGIN Parameters
CSET component_name=icon
CSET enable_jtag_bufg=true
CSET number_control_ports=2
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
GENERATE
# CRC: 7da1f376

