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###############################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor             : Xilinx
## \   \   \/     Version            : 3.5
##  \   \         Application	     : MIG
##  /   /         Filename           : sim.do
## /___/   /\     Date Last Modified : $Date: 2010/04/06 08:14:47 $
## \   \  /  \    Date Created       : Mon Mar 2 2009
##  \___\/\___\
##
## Device: Spartan-6
## Design Name : DDR/DDR2/DDR3/LPDDR
## Purpose:
##    Sample sim .do file to compile and simulate memory interface
##    design and run the simulation for specified period of time. Display the
##    waveforms that are listed with "add wave" command.
##    Assumptions:
##      - Simulation takes place in \sim folder of MIG output directory
## Reference:
## Revision History:
###############################################################################

vlib work

#Map the required libraries here.#
#vmap unisims_ver <unisims_ver lib path>
#vmap secureip <secureip lib path> 

#Compile all rtl modules#
vlog  ../rtl/*.v

#Compile files in sim folder (excluding model parameter file)#
#$XILINX variable must be set
vlog  $env(XILINX)/verilog/src/glbl.v
vlog  ../sim/*.v
vlog  ../../../xil_clk_wiz_v1_6_50x200.v
vlog  ../../../xil_blk_mem_gen_v4_2_1024x32.v
vlog  ../../../xil_blk_mem_gen_v4_2_1024x36.v
vlog $env(XILINX)/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2.v
vlog -f $env(XILINX)/secureip/mti/mcb_mti/mcb_cell.list.f
vlog  $env(XILINX)/verilog/src/unisims/*.v

vlog  ../../../../xt_crtc.v
vlog  ../../../../dispgen_vga.v
vlog  ../../../../xt_capt.v
#vlog  ../../../../xt_mem.v
vlog  ../../../../coregen/eptest/example_design/xt_mem.v

#Pass the parameters for memory model parameter file#
vlog  +incdir+. +define+x512Mb +define+sg37E +define+x16 ddr2_model_c3.v

#Load the design. Use required libraries.#
#vsim -t ps -novopt +notimingchecks -L unisims_ver -L secureip work.sim_tb_top glbl
vsim -t ps -novopt +notimingchecks work.sim_tb_top glbl

onerror {resume}

#Log all the objects in design. These will appear in .wlf file#
log -r /*

#View sim_tb_top signals in waveform#
add wave -radix hexadecimal sim:/sim_tb_top/*
add wave -radix hexadecimal sim:/sim_tb_top/mem/*

#Change radix to Hexadecimal#
radix hex
#Supress Numeric Std package and Arith package warnings.#
#For VHDL designs we get some warnings due to unknown values on some signals at startup#
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
#We may also get some Arithmetic packeage warnings because of unknown values on#
#some of the signals that are used in an Arithmetic operation.#
#In order to suppress these warnings, we use following two commands#
set NumericStdNoWarnings 1
set StdArithNoWarnings 1

#Choose simulation run time by inserting a breakpoint and then run for specified #
#period. Refer simulation_help file.#
when {/sim_tb_top/calib_done = 1} {
echo "Calibration Done"
  if {[when -label a_100] == ""} {
    when -label a_100 { $now = 5000 us } {
      nowhen a_100
      report simulator control
      report simulator state
      if {[examine /sim_tb_top/error] == 0} {
        echo "TEST PASSED"
        stop
        }
      if {[examine /sim_tb_top/error] != 0} {
        echo "TEST FAILED: DATA ERROR"
        stop
        }
      }
    }
  }

#In case calibration fails to complete, choose the run time and then quit#
when {$now = @20000 us and /sim_tb_top/calib_done != 1} {
echo "TEST FAILED: INITIALIZATION DID NOT COMPLETE"
stop
}
run -all
stop
