//IP Functional Simulation Model
//VERSION_BEGIN 9.1 cbx_mgl 2009:10:21:21:37:49:SJ cbx_simgen 2009:10:21:21:22:16:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = arriagx_hssi_calibration_block 1 arriagx_hssi_central_management_unit 1 arriagx_hssi_cmu_pll 1 arriagx_hssi_transmitter 2 
`timescale 1 ps / 1 ps
module  alt_alt2gxb_tx2
	( 
	cal_blk_clk,
	gxb_enable,
	gxb_powerdown,
	pll_inclk,
	pll_locked,
	tx_clkout,
	tx_ctrlenable,
	tx_datain,
	tx_dataout,
	tx_digitalreset,
	tx_dispval,
	tx_forcedisp) /* synthesis synthesis_clearbox=1 */;
	input   cal_blk_clk;
	input   [0:0]  gxb_enable;
	input   [0:0]  gxb_powerdown;
	input   pll_inclk;
	output   [0:0]  pll_locked;
	output   [1:0]  tx_clkout;
	input   [1:0]  tx_ctrlenable;
	input   [15:0]  tx_datain;
	output   [1:0]  tx_dataout;
	input   [1:0]  tx_digitalreset;
	input   [1:0]  tx_dispval;
	input   [1:0]  tx_forcedisp;

	wire  [119:0]   wire_nilO_cmuplldprioout;
	wire  wire_nilO_dpriodisableout;
	wire  [2:0]   wire_nilO_pllpowerdn;
	wire  [2:0]   wire_nilO_pllresetout;
	wire  wire_nilO_quadresetout;
	wire  [3:0]   wire_nilO_txanalogresetout;
	wire  [3:0]   wire_nilO_txctrlout;
	wire  [31:0]   wire_nilO_txdataout;
	wire  [3:0]   wire_nilO_txdetectrxpowerdn;
	wire  [3:0]   wire_nilO_txdigitalresetout;
	wire  [3:0]   wire_nilO_txdividerpowerdn;
	wire  [3:0]   wire_nilO_txobpowerdn;
	wire  wire_nill_clkout;
	wire  wire_nill_locked;
	wire  wire_niiO_dataout;
	wire  wire_nili_clkout;
	wire  wire_nili_dataout;

	arriagx_hssi_calibration_block   niil
	( 
	.calibrationstatus(),
	.clk(cal_blk_clk),
	.powerdn(1'b1));
	arriagx_hssi_central_management_unit   nilO
	( 
	.adet({4{1'b0}}),
	.alignstatus(),
	.clkdivpowerdn(),
	.cmudividerdprioin({30{1'b0}}),
	.cmudividerdprioout(),
	.cmuplldprioin({120{1'b0}}),
	.cmuplldprioout(wire_nilO_cmuplldprioout),
	.dpclk(1'b0),
	.dpriodisable(1'b1),
	.dpriodisableout(wire_nilO_dpriodisableout),
	.dprioin(1'b0),
	.dprioload(1'b0),
	.dpriooe(),
	.dprioout(),
	.enabledeskew(),
	.fiforesetrd(),
	.fixedclk({4{1'b0}}),
	.pllpowerdn(wire_nilO_pllpowerdn),
	.pllresetout(wire_nilO_pllresetout),
	.quadenable(gxb_enable[0]),
	.quadreset(gxb_powerdown[0]),
	.quadresetout(wire_nilO_quadresetout),
	.rdalign({4{1'b0}}),
	.rdenablesync(1'b0),
	.recovclk(1'b0),
	.refclkdividerdprioin({2{1'b0}}),
	.rxadcepowerdn(),
	.rxadceresetout(),
	.rxanalogreset({4{1'b0}}),
	.rxanalogresetout(),
	.rxclk(1'b0),
	.rxcrupowerdn(),
	.rxcruresetout(),
	.rxctrl({4{1'b0}}),
	.rxctrlout(),
	.rxdatain({32{1'b0}}),
	.rxdataout(),
	.rxdatavalid({4{1'b0}}),
	.rxdigitalreset({4{1'b0}}),
	.rxdigitalresetout(),
	.rxdprioin({1200{1'b0}}),
	.rxdprioout(),
	.rxibpowerdn(),
	.rxpowerdown({4{1'b0}}),
	.rxrunningdisp({4{1'b0}}),
	.syncstatus({4{1'b0}}),
	.txanalogresetout(wire_nilO_txanalogresetout),
	.txclk(1'b0),
	.txctrl({4{1'b0}}),
	.txctrlout(wire_nilO_txctrlout),
	.txdatain({32{1'b0}}),
	.txdataout(wire_nilO_txdataout),
	.txdetectrxpowerdn(wire_nilO_txdetectrxpowerdn),
	.txdigitalreset({{2{1'b0}}, tx_digitalreset[1:0]}),
	.txdigitalresetout(wire_nilO_txdigitalresetout),
	.txdividerpowerdn(wire_nilO_txdividerpowerdn),
	.txdprioin({600{1'b0}}),
	.txdprioout(),
	.txobpowerdn(wire_nilO_txobpowerdn));
	defparam
		nilO.analog_test_bus_enable = "false",
		nilO.bonded_quad_mode = "none",
		nilO.devaddr = 1,
		nilO.dprio_config_mode = 0,
		nilO.in_xaui_mode = "false",
		nilO.lpm_type = "stratixiigx_hssi_central_management_unit",
		nilO.offset_all_errors_align = "false",
		nilO.pll0_inclk0_logical_to_physical_mapping = "iq0",
		nilO.pll0_inclk1_logical_to_physical_mapping = "iq1",
		nilO.pll0_inclk2_logical_to_physical_mapping = "iq2",
		nilO.pll0_inclk3_logical_to_physical_mapping = "iq3",
		nilO.pll0_inclk4_logical_to_physical_mapping = "iq4",
		nilO.pll0_inclk5_logical_to_physical_mapping = "pld_clk",
		nilO.pll0_inclk6_logical_to_physical_mapping = "clkrefclk0",
		nilO.pll0_inclk7_logical_to_physical_mapping = "clkrefclk1",
		nilO.pll1_inclk0_logical_to_physical_mapping = "iq0",
		nilO.pll1_inclk1_logical_to_physical_mapping = "iq1",
		nilO.pll1_inclk2_logical_to_physical_mapping = "iq2",
		nilO.pll1_inclk3_logical_to_physical_mapping = "iq3",
		nilO.pll1_inclk4_logical_to_physical_mapping = "iq4",
		nilO.pll1_inclk5_logical_to_physical_mapping = "pld_clk",
		nilO.pll1_inclk6_logical_to_physical_mapping = "clkrefclk0",
		nilO.pll1_inclk7_logical_to_physical_mapping = "clkrefclk1",
		nilO.portaddr = 1,
		nilO.rx0_cru_clock0_physical_mapping = "iq0",
		nilO.rx0_cru_clock1_physical_mapping = "iq1",
		nilO.rx0_cru_clock2_physical_mapping = "iq2",
		nilO.rx0_cru_clock3_physical_mapping = "iq3",
		nilO.rx0_cru_clock4_physical_mapping = "iq4",
		nilO.rx0_cru_clock5_physical_mapping = "pld_cru_clk",
		nilO.rx0_cru_clock6_physical_mapping = "refclk0",
		nilO.rx0_cru_clock7_physical_mapping = "refclk1",
		nilO.rx0_cru_clock8_physical_mapping = "cmu_div_clk",
		nilO.rx1_cru_clock0_physical_mapping = "iq0",
		nilO.rx1_cru_clock1_physical_mapping = "iq1",
		nilO.rx1_cru_clock2_physical_mapping = "iq2",
		nilO.rx1_cru_clock3_physical_mapping = "iq3",
		nilO.rx1_cru_clock4_physical_mapping = "iq4",
		nilO.rx1_cru_clock5_physical_mapping = "pld_cru_clk",
		nilO.rx1_cru_clock6_physical_mapping = "refclk0",
		nilO.rx1_cru_clock7_physical_mapping = "refclk1",
		nilO.rx1_cru_clock8_physical_mapping = "cmu_div_clk",
		nilO.rx2_cru_clock0_physical_mapping = "iq0",
		nilO.rx2_cru_clock1_physical_mapping = "iq1",
		nilO.rx2_cru_clock2_physical_mapping = "iq2",
		nilO.rx2_cru_clock3_physical_mapping = "iq3",
		nilO.rx2_cru_clock4_physical_mapping = "iq4",
		nilO.rx2_cru_clock5_physical_mapping = "pld_cru_clk",
		nilO.rx2_cru_clock6_physical_mapping = "refclk0",
		nilO.rx2_cru_clock7_physical_mapping = "refclk1",
		nilO.rx2_cru_clock8_physical_mapping = "cmu_div_clk",
		nilO.rx3_cru_clock0_physical_mapping = "iq0",
		nilO.rx3_cru_clock1_physical_mapping = "iq1",
		nilO.rx3_cru_clock2_physical_mapping = "iq2",
		nilO.rx3_cru_clock3_physical_mapping = "iq3",
		nilO.rx3_cru_clock4_physical_mapping = "iq4",
		nilO.rx3_cru_clock5_physical_mapping = "pld_cru_clk",
		nilO.rx3_cru_clock6_physical_mapping = "refclk0",
		nilO.rx3_cru_clock7_physical_mapping = "refclk1",
		nilO.rx3_cru_clock8_physical_mapping = "cmu_div_clk",
		nilO.rx_dprio_width = 1200,
		nilO.sim_dump_dprio_internal_reg_at_time = 0,
		nilO.sim_dump_filename = "sim_dprio_dump.txt",
		nilO.tx0_pll_fast_clk0_physical_mapping = "pll0",
		nilO.tx0_pll_fast_clk1_physical_mapping = "pll1",
		nilO.tx1_pll_fast_clk0_physical_mapping = "pll0",
		nilO.tx1_pll_fast_clk1_physical_mapping = "pll1",
		nilO.tx2_pll_fast_clk0_physical_mapping = "pll0",
		nilO.tx2_pll_fast_clk1_physical_mapping = "pll1",
		nilO.tx3_pll_fast_clk0_physical_mapping = "pll0",
		nilO.tx3_pll_fast_clk1_physical_mapping = "pll1",
		nilO.tx_dprio_width = 600,
		nilO.use_deskew_fifo = "false";
	arriagx_hssi_cmu_pll   nill
	( 
	.clk({{5{1'b0}}, pll_inclk, {2{1'b0}}}),
	.clkout(wire_nill_clkout),
	.dpriodisable(wire_nilO_dpriodisableout),
	.dprioin({wire_nilO_cmuplldprioout[39:0]}),
	.dprioout(),
	.locked(wire_nill_locked),
	.pllpowerdn(wire_nilO_pllpowerdn[0]),
	.pllreset(wire_nilO_pllresetout[0]));
	defparam
		nill.charge_pump_current_control = 2,
		nill.divide_by = 1,
		nill.dprio_config_mode = 0,
		nill.enable_pll_cascade = "false",
		nill.inclk0_period = 0,
		nill.inclk1_period = 6173,
		nill.inclk2_period = 6173,
		nill.inclk3_period = 0,
		nill.inclk4_period = 0,
		nill.inclk5_period = 0,
		nill.inclk6_period = 0,
		nill.loop_filter_resistor_control = 3,
		nill.low_speed_test_sel = 0,
		nill.multiply_by = 5,
		nill.pfd_clk_select = 2,
		nill.pll_number = 0,
		nill.pll_type = "normal",
		nill.protocol_hint = "basic",
		nill.remapped_to_new_loop_filter_charge_pump_settings = "false",
		nill.sim_clkout_phase_shift = 0,
		nill.vco_range = "low";
	arriagx_hssi_transmitter   niiO
	( 
	.analogreset(wire_nilO_txanalogresetout[1]),
	.analogx4fastrefclk(1'b0),
	.analogx4refclk(1'b0),
	.analogx8fastrefclk(1'b0),
	.analogx8refclk(1'b0),
	.clkout(),
	.coreclk(wire_nili_clkout),
	.ctrlenable({tx_ctrlenable[1]}),
	.datain({tx_datain[15:8]}),
	.datainfull({44{1'b0}}),
	.dataout(wire_niiO_dataout),
	.detectrxloop(1'b0),
	.detectrxpowerdn(wire_nilO_txdetectrxpowerdn[1]),
	.digitalreset(wire_nilO_txdigitalresetout[1]),
	.dispval({tx_dispval[1]}),
	.dividerpowerdn(wire_nilO_txdividerpowerdn[1]),
	.dpriodisable(1'b1),
	.dprioin({150{1'b0}}),
	.dprioout(),
	.enrevparallellpbk(1'b0),
	.forcedisp({tx_forcedisp[1]}),
	.forcedispcompliance(1'b0),
	.forceelecidle(1'b0),
	.invpol(1'b0),
	.obpowerdn(wire_nilO_txobpowerdn[1]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifooverflow(),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfifordenableout(),
	.phfiforeset(1'b0),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b1),
	.phfifox4rdenable(1'b1),
	.phfifox4wrenable(1'b1),
	.phfifox8bytesel(1'b0),
	.phfifox8rdclk(1'b1),
	.phfifox8rdenable(1'b1),
	.phfifox8wrenable(1'b1),
	.pipepowerdownout(),
	.pipepowerstateout(),
	.pipestatetransdone(1'b0),
	.pllfastclk({1'b0, wire_nill_clkout}),
	.powerdn({2{1'b0}}),
	.quadreset(wire_nilO_quadresetout),
	.rdenablesync(),
	.refclk(1'b0),
	.refclkout(),
	.revparallelfdbk({20{1'b0}}),
	.revserialfdbk(1'b0),
	.rxdetectvalidout(),
	.rxfoundout(),
	.serialfdbkout(),
	.xgmctrl(wire_nilO_txctrlout[1]),
	.xgmctrlenable(),
	.xgmdatain({wire_nilO_txdataout[15:8]}),
	.xgmdataout());
	defparam
		niiO.allow_polarity_inversion = "false",
		niiO.analog_power = "1.2v",
		niiO.channel_bonding = "none",
		niiO.channel_number = 1,
		niiO.channel_width = 8,
		niiO.common_mode = "0.6v",
		niiO.disable_ph_low_latency_mode = "false",
		niiO.disparity_mode = "new",
		niiO.divider_refclk_select_pll_fast_clk0 = "true",
		niiO.dprio_config_mode = 0,
		niiO.dprio_mode = "none",
		niiO.dprio_width = 150,
		niiO.enable_bit_reversal = "false",
		niiO.enable_idle_selection = "false",
		niiO.enable_reverse_parallel_loopback = "false",
		niiO.enable_reverse_serial_loopback = "false",
		niiO.enable_self_test_mode = "false",
		niiO.enable_slew_rate = "false",
		niiO.enable_symbol_swap = "false",
		niiO.enc_8b_10b_compatibility_mode = "true",
		niiO.enc_8b_10b_mode = "normal",
		niiO.force_echar = "false",
		niiO.force_kchar = "false",
		niiO.low_speed_test_select = 0,
		niiO.preemp_pretap = 0,
		niiO.preemp_pretap_inv = "false",
		niiO.preemp_tap_1 = 4,
		niiO.preemp_tap_2 = 0,
		niiO.preemp_tap_2_inv = "false",
		niiO.protocol_hint = "basic",
		niiO.refclk_divide_by = 1,
		niiO.refclk_select = "local",
		niiO.rxdetect_ctrl = 0,
		niiO.self_test_mode = "incremental",
		niiO.serializer_clk_select = "local",
		niiO.termination = "oct_100_ohms",
		niiO.transmit_protocol = "basic",
		niiO.use_double_data_mode = "false",
		niiO.use_serializer_double_data_mode = "false",
		niiO.use_termvoltage_signal = "false",
		niiO.vod_selection = 4,
		niiO.wr_clk_mux_select = "core_clk";
	arriagx_hssi_transmitter   nili
	( 
	.analogreset(wire_nilO_txanalogresetout[0]),
	.analogx4fastrefclk(1'b0),
	.analogx4refclk(1'b0),
	.analogx8fastrefclk(1'b0),
	.analogx8refclk(1'b0),
	.clkout(wire_nili_clkout),
	.coreclk(wire_nili_clkout),
	.ctrlenable({tx_ctrlenable[0]}),
	.datain({tx_datain[7:0]}),
	.datainfull({44{1'b0}}),
	.dataout(wire_nili_dataout),
	.detectrxloop(1'b0),
	.detectrxpowerdn(wire_nilO_txdetectrxpowerdn[0]),
	.digitalreset(wire_nilO_txdigitalresetout[0]),
	.dispval({tx_dispval[0]}),
	.dividerpowerdn(wire_nilO_txdividerpowerdn[0]),
	.dpriodisable(1'b1),
	.dprioin({150{1'b0}}),
	.dprioout(),
	.enrevparallellpbk(1'b0),
	.forcedisp({tx_forcedisp[0]}),
	.forcedispcompliance(1'b0),
	.forceelecidle(1'b0),
	.invpol(1'b0),
	.obpowerdn(wire_nilO_txobpowerdn[0]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifooverflow(),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfifordenableout(),
	.phfiforeset(1'b0),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b1),
	.phfifox4rdenable(1'b1),
	.phfifox4wrenable(1'b1),
	.phfifox8bytesel(1'b0),
	.phfifox8rdclk(1'b1),
	.phfifox8rdenable(1'b1),
	.phfifox8wrenable(1'b1),
	.pipepowerdownout(),
	.pipepowerstateout(),
	.pipestatetransdone(1'b0),
	.pllfastclk({1'b0, wire_nill_clkout}),
	.powerdn({2{1'b0}}),
	.quadreset(wire_nilO_quadresetout),
	.rdenablesync(),
	.refclk(1'b0),
	.refclkout(),
	.revparallelfdbk({20{1'b0}}),
	.revserialfdbk(1'b0),
	.rxdetectvalidout(),
	.rxfoundout(),
	.serialfdbkout(),
	.xgmctrl(wire_nilO_txctrlout[0]),
	.xgmctrlenable(),
	.xgmdatain({wire_nilO_txdataout[7:0]}),
	.xgmdataout());
	defparam
		nili.allow_polarity_inversion = "false",
		nili.analog_power = "1.2v",
		nili.channel_bonding = "none",
		nili.channel_number = 0,
		nili.channel_width = 8,
		nili.common_mode = "0.6v",
		nili.disable_ph_low_latency_mode = "false",
		nili.disparity_mode = "new",
		nili.divider_refclk_select_pll_fast_clk0 = "true",
		nili.dprio_config_mode = 0,
		nili.dprio_mode = "none",
		nili.dprio_width = 150,
		nili.enable_bit_reversal = "false",
		nili.enable_idle_selection = "false",
		nili.enable_reverse_parallel_loopback = "false",
		nili.enable_reverse_serial_loopback = "false",
		nili.enable_self_test_mode = "false",
		nili.enable_slew_rate = "false",
		nili.enable_symbol_swap = "false",
		nili.enc_8b_10b_compatibility_mode = "true",
		nili.enc_8b_10b_mode = "normal",
		nili.force_echar = "false",
		nili.force_kchar = "false",
		nili.low_speed_test_select = 0,
		nili.preemp_pretap = 0,
		nili.preemp_pretap_inv = "false",
		nili.preemp_tap_1 = 4,
		nili.preemp_tap_2 = 0,
		nili.preemp_tap_2_inv = "false",
		nili.protocol_hint = "basic",
		nili.refclk_divide_by = 1,
		nili.refclk_select = "local",
		nili.rxdetect_ctrl = 0,
		nili.self_test_mode = "incremental",
		nili.serializer_clk_select = "local",
		nili.termination = "oct_100_ohms",
		nili.transmit_protocol = "basic",
		nili.use_double_data_mode = "false",
		nili.use_serializer_double_data_mode = "false",
		nili.use_termvoltage_signal = "false",
		nili.vod_selection = 4,
		nili.wr_clk_mux_select = "core_clk";
	assign
		pll_locked = {wire_nill_locked},
		tx_clkout = {2{wire_nili_clkout}},
		tx_dataout = {wire_niiO_dataout, wire_nili_dataout};
endmodule //alt_alt2gxb_tx2
//synopsys translate_on
//VALID FILE
