verilog work "../source/eptest.v"
verilog work "../source/pcie_bram_top_s6.v"
verilog work "../source/pcie_brams_s6.v"
verilog work "../source/pcie_bram_s6.v"
verilog work "../source/gtpa1_dual_wrapper_tile.v"
verilog work "../source/gtpa1_dual_wrapper.v"
verilog work "../example_design/xilinx_pcie_1_1_ep_s6.v"
verilog work "../example_design/pcie_app_s6.v"
verilog work "../example_design/PIO_EP.v"
verilog work "../example_design/PIO_EP_MEM_ACCESS.v"
verilog work "../example_design/PIO_EP_MEM.v"
verilog work "../example_design/PIO_32_RX_ENGINE.v"
verilog work "../example_design/PIO_32_TX_ENGINE.v"
verilog work "../example_design/PIO_TO_CTRL.v"
verilog work "../example_design/PIO.v"

