//IP Functional Simulation Model
//VERSION_BEGIN 9.1SP2 cbx_mgl 2010:03:24:21:01:05:SJ cbx_simgen 2010:03:24:20:43:43:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2010 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).


//synopsys translate_off

//synthesis_resources = arriagx_hssi_calibration_block 1 arriagx_hssi_central_management_unit 1 arriagx_hssi_cmu_pll 1 arriagx_hssi_transmitter 4 
`timescale 1 ps / 1 ps
module  alt_alt2gxb_raw_x4
	( 
	cal_blk_clk,
	gxb_powerdown,
	pll_inclk,
	tx_clkout,
	tx_datain,
	tx_dataout,
	tx_digitalreset) /* synthesis synthesis_clearbox=1 */;
	input   cal_blk_clk;
	input   [0:0]  gxb_powerdown;
	input   pll_inclk;
	output   [3:0]  tx_clkout;
	input   [39:0]  tx_datain;
	output   [3:0]  tx_dataout;
	input   [3:0]  tx_digitalreset;

	wire  [119:0]   wire_n00l_cmuplldprioout;
	wire  wire_n00l_dpriodisableout;
	wire  [2:0]   wire_n00l_pllpowerdn;
	wire  [2:0]   wire_n00l_pllresetout;
	wire  wire_n00l_quadresetout;
	wire  [3:0]   wire_n00l_txanalogresetout;
	wire  [3:0]   wire_n00l_txctrlout;
	wire  [31:0]   wire_n00l_txdataout;
	wire  [3:0]   wire_n00l_txdetectrxpowerdn;
	wire  [3:0]   wire_n00l_txdigitalresetout;
	wire  [3:0]   wire_n00l_txdividerpowerdn;
	wire  [3:0]   wire_n00l_txobpowerdn;
	wire  wire_n00i_clkout;
	wire  wire_n01i_dataout;
	wire  wire_n01l_dataout;
	wire  wire_n01O_clkout;
	wire  wire_n01O_dataout;
	wire  wire_n1OO_dataout;

	arriagx_hssi_calibration_block   n1Ol
	( 
	.calibrationstatus(),
	.clk(cal_blk_clk),
	.powerdn(1'b1));
	arriagx_hssi_central_management_unit   n00l
	( 
	.adet({4{1'b0}}),
	.alignstatus(),
	.clkdivpowerdn(),
	.cmudividerdprioin({30{1'b0}}),
	.cmudividerdprioout(),
	.cmuplldprioin({120{1'b0}}),
	.cmuplldprioout(wire_n00l_cmuplldprioout),
	.dpclk(1'b0),
	.dpriodisable(1'b1),
	.dpriodisableout(wire_n00l_dpriodisableout),
	.dprioin(1'b0),
	.dprioload(1'b0),
	.dpriooe(),
	.dprioout(),
	.enabledeskew(),
	.fiforesetrd(),
	.fixedclk({4{1'b0}}),
	.pllpowerdn(wire_n00l_pllpowerdn),
	.pllresetout(wire_n00l_pllresetout),
	.quadenable(1'b1),
	.quadreset(gxb_powerdown[0]),
	.quadresetout(wire_n00l_quadresetout),
	.rdalign({4{1'b0}}),
	.rdenablesync(1'b0),
	.recovclk(1'b0),
	.refclkdividerdprioin({2{1'b0}}),
	.rxadcepowerdn(),
	.rxadceresetout(),
	.rxanalogreset({4{1'b0}}),
	.rxanalogresetout(),
	.rxclk(1'b0),
	.rxcrupowerdn(),
	.rxcruresetout(),
	.rxctrl({4{1'b0}}),
	.rxctrlout(),
	.rxdatain({32{1'b0}}),
	.rxdataout(),
	.rxdatavalid({4{1'b0}}),
	.rxdigitalreset({4{1'b0}}),
	.rxdigitalresetout(),
	.rxdprioin({1200{1'b0}}),
	.rxdprioout(),
	.rxibpowerdn(),
	.rxpowerdown({4{1'b0}}),
	.rxrunningdisp({4{1'b0}}),
	.syncstatus({4{1'b0}}),
	.txanalogresetout(wire_n00l_txanalogresetout),
	.txclk(1'b0),
	.txctrl({4{1'b0}}),
	.txctrlout(wire_n00l_txctrlout),
	.txdatain({32{1'b0}}),
	.txdataout(wire_n00l_txdataout),
	.txdetectrxpowerdn(wire_n00l_txdetectrxpowerdn),
	.txdigitalreset({tx_digitalreset[3:0]}),
	.txdigitalresetout(wire_n00l_txdigitalresetout),
	.txdividerpowerdn(wire_n00l_txdividerpowerdn),
	.txdprioin({600{1'b0}}),
	.txdprioout(),
	.txobpowerdn(wire_n00l_txobpowerdn));
	defparam
		n00l.analog_test_bus_enable = "false",
		n00l.bonded_quad_mode = "none",
		n00l.devaddr = 1,
		n00l.dprio_config_mode = 0,
		n00l.in_xaui_mode = "false",
		n00l.lpm_type = "stratixiigx_hssi_central_management_unit",
		n00l.offset_all_errors_align = "false",
		n00l.pll0_inclk0_logical_to_physical_mapping = "iq0",
		n00l.pll0_inclk1_logical_to_physical_mapping = "iq1",
		n00l.pll0_inclk2_logical_to_physical_mapping = "iq2",
		n00l.pll0_inclk3_logical_to_physical_mapping = "iq3",
		n00l.pll0_inclk4_logical_to_physical_mapping = "iq4",
		n00l.pll0_inclk5_logical_to_physical_mapping = "pld_clk",
		n00l.pll0_inclk6_logical_to_physical_mapping = "clkrefclk0",
		n00l.pll0_inclk7_logical_to_physical_mapping = "clkrefclk1",
		n00l.pll1_inclk0_logical_to_physical_mapping = "iq0",
		n00l.pll1_inclk1_logical_to_physical_mapping = "iq1",
		n00l.pll1_inclk2_logical_to_physical_mapping = "iq2",
		n00l.pll1_inclk3_logical_to_physical_mapping = "iq3",
		n00l.pll1_inclk4_logical_to_physical_mapping = "iq4",
		n00l.pll1_inclk5_logical_to_physical_mapping = "pld_clk",
		n00l.pll1_inclk6_logical_to_physical_mapping = "clkrefclk0",
		n00l.pll1_inclk7_logical_to_physical_mapping = "clkrefclk1",
		n00l.portaddr = 1,
		n00l.rx0_cru_clock0_physical_mapping = "iq0",
		n00l.rx0_cru_clock1_physical_mapping = "iq1",
		n00l.rx0_cru_clock2_physical_mapping = "iq2",
		n00l.rx0_cru_clock3_physical_mapping = "iq3",
		n00l.rx0_cru_clock4_physical_mapping = "iq4",
		n00l.rx0_cru_clock5_physical_mapping = "pld_cru_clk",
		n00l.rx0_cru_clock6_physical_mapping = "refclk0",
		n00l.rx0_cru_clock7_physical_mapping = "refclk1",
		n00l.rx0_cru_clock8_physical_mapping = "cmu_div_clk",
		n00l.rx1_cru_clock0_physical_mapping = "iq0",
		n00l.rx1_cru_clock1_physical_mapping = "iq1",
		n00l.rx1_cru_clock2_physical_mapping = "iq2",
		n00l.rx1_cru_clock3_physical_mapping = "iq3",
		n00l.rx1_cru_clock4_physical_mapping = "iq4",
		n00l.rx1_cru_clock5_physical_mapping = "pld_cru_clk",
		n00l.rx1_cru_clock6_physical_mapping = "refclk0",
		n00l.rx1_cru_clock7_physical_mapping = "refclk1",
		n00l.rx1_cru_clock8_physical_mapping = "cmu_div_clk",
		n00l.rx2_cru_clock0_physical_mapping = "iq0",
		n00l.rx2_cru_clock1_physical_mapping = "iq1",
		n00l.rx2_cru_clock2_physical_mapping = "iq2",
		n00l.rx2_cru_clock3_physical_mapping = "iq3",
		n00l.rx2_cru_clock4_physical_mapping = "iq4",
		n00l.rx2_cru_clock5_physical_mapping = "pld_cru_clk",
		n00l.rx2_cru_clock6_physical_mapping = "refclk0",
		n00l.rx2_cru_clock7_physical_mapping = "refclk1",
		n00l.rx2_cru_clock8_physical_mapping = "cmu_div_clk",
		n00l.rx3_cru_clock0_physical_mapping = "iq0",
		n00l.rx3_cru_clock1_physical_mapping = "iq1",
		n00l.rx3_cru_clock2_physical_mapping = "iq2",
		n00l.rx3_cru_clock3_physical_mapping = "iq3",
		n00l.rx3_cru_clock4_physical_mapping = "iq4",
		n00l.rx3_cru_clock5_physical_mapping = "pld_cru_clk",
		n00l.rx3_cru_clock6_physical_mapping = "refclk0",
		n00l.rx3_cru_clock7_physical_mapping = "refclk1",
		n00l.rx3_cru_clock8_physical_mapping = "cmu_div_clk",
		n00l.rx_dprio_width = 1200,
		n00l.sim_dump_dprio_internal_reg_at_time = 0,
		n00l.sim_dump_filename = "sim_dprio_dump.txt",
		n00l.tx0_pll_fast_clk0_physical_mapping = "pll0",
		n00l.tx0_pll_fast_clk1_physical_mapping = "pll1",
		n00l.tx1_pll_fast_clk0_physical_mapping = "pll0",
		n00l.tx1_pll_fast_clk1_physical_mapping = "pll1",
		n00l.tx2_pll_fast_clk0_physical_mapping = "pll0",
		n00l.tx2_pll_fast_clk1_physical_mapping = "pll1",
		n00l.tx3_pll_fast_clk0_physical_mapping = "pll0",
		n00l.tx3_pll_fast_clk1_physical_mapping = "pll1",
		n00l.tx_dprio_width = 600,
		n00l.use_deskew_fifo = "false";
	arriagx_hssi_cmu_pll   n00i
	( 
	.clk({{5{1'b0}}, pll_inclk, {2{1'b0}}}),
	.clkout(wire_n00i_clkout),
	.dpriodisable(wire_n00l_dpriodisableout),
	.dprioin({wire_n00l_cmuplldprioout[39:0]}),
	.dprioout(),
	.locked(),
	.pllpowerdn(wire_n00l_pllpowerdn[0]),
	.pllreset(wire_n00l_pllresetout[0]));
	defparam
		n00i.charge_pump_current_control = 2,
		n00i.divide_by = 1,
		n00i.dprio_config_mode = 0,
		n00i.enable_pll_cascade = "false",
		n00i.inclk0_period = 0,
		n00i.inclk1_period = 7407,
		n00i.inclk2_period = 7407,
		n00i.inclk3_period = 0,
		n00i.inclk4_period = 0,
		n00i.inclk5_period = 0,
		n00i.inclk6_period = 0,
		n00i.loop_filter_resistor_control = 3,
		n00i.low_speed_test_sel = 0,
		n00i.multiply_by = 5,
		n00i.pfd_clk_select = 2,
		n00i.pll_number = 0,
		n00i.pll_type = "normal",
		n00i.protocol_hint = "basic",
		n00i.remapped_to_new_loop_filter_charge_pump_settings = "false",
		n00i.sim_clkout_phase_shift = 0,
		n00i.vco_range = "low";
	arriagx_hssi_transmitter   n01i
	( 
	.analogreset(wire_n00l_txanalogresetout[2]),
	.analogx4fastrefclk(1'b0),
	.analogx4refclk(1'b0),
	.analogx8fastrefclk(1'b0),
	.analogx8refclk(1'b0),
	.clkout(),
	.coreclk(wire_n01O_clkout),
	.ctrlenable({1'b0}),
	.datain({tx_datain[29:20]}),
	.datainfull({44{1'b0}}),
	.dataout(wire_n01i_dataout),
	.detectrxloop(1'b0),
	.detectrxpowerdn(wire_n00l_txdetectrxpowerdn[2]),
	.digitalreset(wire_n00l_txdigitalresetout[2]),
	.dispval({1'b0}),
	.dividerpowerdn(wire_n00l_txdividerpowerdn[2]),
	.dpriodisable(1'b1),
	.dprioin({150{1'b0}}),
	.dprioout(),
	.enrevparallellpbk(1'b0),
	.forcedisp({1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidle(1'b0),
	.invpol(1'b0),
	.obpowerdn(wire_n00l_txobpowerdn[2]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifooverflow(),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfifordenableout(),
	.phfiforeset(1'b0),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b1),
	.phfifox4rdenable(1'b1),
	.phfifox4wrenable(1'b1),
	.phfifox8bytesel(1'b0),
	.phfifox8rdclk(1'b1),
	.phfifox8rdenable(1'b1),
	.phfifox8wrenable(1'b1),
	.pipepowerdownout(),
	.pipepowerstateout(),
	.pipestatetransdone(1'b0),
	.pllfastclk({1'b0, wire_n00i_clkout}),
	.powerdn({2{1'b0}}),
	.quadreset(wire_n00l_quadresetout),
	.rdenablesync(),
	.refclk(1'b0),
	.refclkout(),
	.revparallelfdbk({20{1'b0}}),
	.revserialfdbk(1'b0),
	.rxdetectvalidout(),
	.rxfoundout(),
	.serialfdbkout(),
	.xgmctrl(wire_n00l_txctrlout[2]),
	.xgmctrlenable(),
	.xgmdatain({wire_n00l_txdataout[23:16]}),
	.xgmdataout());
	defparam
		n01i.allow_polarity_inversion = "false",
		n01i.analog_power = "1.2v",
		n01i.channel_bonding = "none",
		n01i.channel_number = 2,
		n01i.channel_width = 10,
		n01i.common_mode = "0.6v",
		n01i.disable_ph_low_latency_mode = "false",
		n01i.disparity_mode = "none",
		n01i.divider_refclk_select_pll_fast_clk0 = "true",
		n01i.dprio_config_mode = 0,
		n01i.dprio_mode = "none",
		n01i.dprio_width = 150,
		n01i.enable_bit_reversal = "false",
		n01i.enable_idle_selection = "false",
		n01i.enable_reverse_parallel_loopback = "false",
		n01i.enable_reverse_serial_loopback = "false",
		n01i.enable_self_test_mode = "false",
		n01i.enable_slew_rate = "false",
		n01i.enable_symbol_swap = "false",
		n01i.enc_8b_10b_compatibility_mode = "false",
		n01i.enc_8b_10b_mode = "none",
		n01i.force_echar = "false",
		n01i.force_kchar = "false",
		n01i.low_speed_test_select = 0,
		n01i.preemp_pretap = 0,
		n01i.preemp_pretap_inv = "false",
		n01i.preemp_tap_1 = 5,
		n01i.preemp_tap_2 = 0,
		n01i.preemp_tap_2_inv = "false",
		n01i.protocol_hint = "basic",
		n01i.refclk_divide_by = 1,
		n01i.refclk_select = "local",
		n01i.rxdetect_ctrl = 0,
		n01i.self_test_mode = "incremental",
		n01i.serializer_clk_select = "local",
		n01i.termination = "oct_100_ohms",
		n01i.transmit_protocol = "basic",
		n01i.use_double_data_mode = "false",
		n01i.use_serializer_double_data_mode = "false",
		n01i.use_termvoltage_signal = "false",
		n01i.vod_selection = 4,
		n01i.wr_clk_mux_select = "core_clk";
	arriagx_hssi_transmitter   n01l
	( 
	.analogreset(wire_n00l_txanalogresetout[1]),
	.analogx4fastrefclk(1'b0),
	.analogx4refclk(1'b0),
	.analogx8fastrefclk(1'b0),
	.analogx8refclk(1'b0),
	.clkout(),
	.coreclk(wire_n01O_clkout),
	.ctrlenable({1'b0}),
	.datain({tx_datain[19:10]}),
	.datainfull({44{1'b0}}),
	.dataout(wire_n01l_dataout),
	.detectrxloop(1'b0),
	.detectrxpowerdn(wire_n00l_txdetectrxpowerdn[1]),
	.digitalreset(wire_n00l_txdigitalresetout[1]),
	.dispval({1'b0}),
	.dividerpowerdn(wire_n00l_txdividerpowerdn[1]),
	.dpriodisable(1'b1),
	.dprioin({150{1'b0}}),
	.dprioout(),
	.enrevparallellpbk(1'b0),
	.forcedisp({1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidle(1'b0),
	.invpol(1'b0),
	.obpowerdn(wire_n00l_txobpowerdn[1]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifooverflow(),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfifordenableout(),
	.phfiforeset(1'b0),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b1),
	.phfifox4rdenable(1'b1),
	.phfifox4wrenable(1'b1),
	.phfifox8bytesel(1'b0),
	.phfifox8rdclk(1'b1),
	.phfifox8rdenable(1'b1),
	.phfifox8wrenable(1'b1),
	.pipepowerdownout(),
	.pipepowerstateout(),
	.pipestatetransdone(1'b0),
	.pllfastclk({1'b0, wire_n00i_clkout}),
	.powerdn({2{1'b0}}),
	.quadreset(wire_n00l_quadresetout),
	.rdenablesync(),
	.refclk(1'b0),
	.refclkout(),
	.revparallelfdbk({20{1'b0}}),
	.revserialfdbk(1'b0),
	.rxdetectvalidout(),
	.rxfoundout(),
	.serialfdbkout(),
	.xgmctrl(wire_n00l_txctrlout[1]),
	.xgmctrlenable(),
	.xgmdatain({wire_n00l_txdataout[15:8]}),
	.xgmdataout());
	defparam
		n01l.allow_polarity_inversion = "false",
		n01l.analog_power = "1.2v",
		n01l.channel_bonding = "none",
		n01l.channel_number = 1,
		n01l.channel_width = 10,
		n01l.common_mode = "0.6v",
		n01l.disable_ph_low_latency_mode = "false",
		n01l.disparity_mode = "none",
		n01l.divider_refclk_select_pll_fast_clk0 = "true",
		n01l.dprio_config_mode = 0,
		n01l.dprio_mode = "none",
		n01l.dprio_width = 150,
		n01l.enable_bit_reversal = "false",
		n01l.enable_idle_selection = "false",
		n01l.enable_reverse_parallel_loopback = "false",
		n01l.enable_reverse_serial_loopback = "false",
		n01l.enable_self_test_mode = "false",
		n01l.enable_slew_rate = "false",
		n01l.enable_symbol_swap = "false",
		n01l.enc_8b_10b_compatibility_mode = "false",
		n01l.enc_8b_10b_mode = "none",
		n01l.force_echar = "false",
		n01l.force_kchar = "false",
		n01l.low_speed_test_select = 0,
		n01l.preemp_pretap = 0,
		n01l.preemp_pretap_inv = "false",
		n01l.preemp_tap_1 = 5,
		n01l.preemp_tap_2 = 0,
		n01l.preemp_tap_2_inv = "false",
		n01l.protocol_hint = "basic",
		n01l.refclk_divide_by = 1,
		n01l.refclk_select = "local",
		n01l.rxdetect_ctrl = 0,
		n01l.self_test_mode = "incremental",
		n01l.serializer_clk_select = "local",
		n01l.termination = "oct_100_ohms",
		n01l.transmit_protocol = "basic",
		n01l.use_double_data_mode = "false",
		n01l.use_serializer_double_data_mode = "false",
		n01l.use_termvoltage_signal = "false",
		n01l.vod_selection = 4,
		n01l.wr_clk_mux_select = "core_clk";
	arriagx_hssi_transmitter   n01O
	( 
	.analogreset(wire_n00l_txanalogresetout[0]),
	.analogx4fastrefclk(1'b0),
	.analogx4refclk(1'b0),
	.analogx8fastrefclk(1'b0),
	.analogx8refclk(1'b0),
	.clkout(wire_n01O_clkout),
	.coreclk(wire_n01O_clkout),
	.ctrlenable({1'b0}),
	.datain({tx_datain[9:0]}),
	.datainfull({44{1'b0}}),
	.dataout(wire_n01O_dataout),
	.detectrxloop(1'b0),
	.detectrxpowerdn(wire_n00l_txdetectrxpowerdn[0]),
	.digitalreset(wire_n00l_txdigitalresetout[0]),
	.dispval({1'b0}),
	.dividerpowerdn(wire_n00l_txdividerpowerdn[0]),
	.dpriodisable(1'b1),
	.dprioin({150{1'b0}}),
	.dprioout(),
	.enrevparallellpbk(1'b0),
	.forcedisp({1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidle(1'b0),
	.invpol(1'b0),
	.obpowerdn(wire_n00l_txobpowerdn[0]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifooverflow(),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfifordenableout(),
	.phfiforeset(1'b0),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b1),
	.phfifox4rdenable(1'b1),
	.phfifox4wrenable(1'b1),
	.phfifox8bytesel(1'b0),
	.phfifox8rdclk(1'b1),
	.phfifox8rdenable(1'b1),
	.phfifox8wrenable(1'b1),
	.pipepowerdownout(),
	.pipepowerstateout(),
	.pipestatetransdone(1'b0),
	.pllfastclk({1'b0, wire_n00i_clkout}),
	.powerdn({2{1'b0}}),
	.quadreset(wire_n00l_quadresetout),
	.rdenablesync(),
	.refclk(1'b0),
	.refclkout(),
	.revparallelfdbk({20{1'b0}}),
	.revserialfdbk(1'b0),
	.rxdetectvalidout(),
	.rxfoundout(),
	.serialfdbkout(),
	.xgmctrl(wire_n00l_txctrlout[0]),
	.xgmctrlenable(),
	.xgmdatain({wire_n00l_txdataout[7:0]}),
	.xgmdataout());
	defparam
		n01O.allow_polarity_inversion = "false",
		n01O.analog_power = "1.2v",
		n01O.channel_bonding = "none",
		n01O.channel_number = 0,
		n01O.channel_width = 10,
		n01O.common_mode = "0.6v",
		n01O.disable_ph_low_latency_mode = "false",
		n01O.disparity_mode = "none",
		n01O.divider_refclk_select_pll_fast_clk0 = "true",
		n01O.dprio_config_mode = 0,
		n01O.dprio_mode = "none",
		n01O.dprio_width = 150,
		n01O.enable_bit_reversal = "false",
		n01O.enable_idle_selection = "false",
		n01O.enable_reverse_parallel_loopback = "false",
		n01O.enable_reverse_serial_loopback = "false",
		n01O.enable_self_test_mode = "false",
		n01O.enable_slew_rate = "false",
		n01O.enable_symbol_swap = "false",
		n01O.enc_8b_10b_compatibility_mode = "false",
		n01O.enc_8b_10b_mode = "none",
		n01O.force_echar = "false",
		n01O.force_kchar = "false",
		n01O.low_speed_test_select = 0,
		n01O.preemp_pretap = 0,
		n01O.preemp_pretap_inv = "false",
		n01O.preemp_tap_1 = 5,
		n01O.preemp_tap_2 = 0,
		n01O.preemp_tap_2_inv = "false",
		n01O.protocol_hint = "basic",
		n01O.refclk_divide_by = 1,
		n01O.refclk_select = "local",
		n01O.rxdetect_ctrl = 0,
		n01O.self_test_mode = "incremental",
		n01O.serializer_clk_select = "local",
		n01O.termination = "oct_100_ohms",
		n01O.transmit_protocol = "basic",
		n01O.use_double_data_mode = "false",
		n01O.use_serializer_double_data_mode = "false",
		n01O.use_termvoltage_signal = "false",
		n01O.vod_selection = 4,
		n01O.wr_clk_mux_select = "core_clk";
	arriagx_hssi_transmitter   n1OO
	( 
	.analogreset(wire_n00l_txanalogresetout[3]),
	.analogx4fastrefclk(1'b0),
	.analogx4refclk(1'b0),
	.analogx8fastrefclk(1'b0),
	.analogx8refclk(1'b0),
	.clkout(),
	.coreclk(wire_n01O_clkout),
	.ctrlenable({1'b0}),
	.datain({tx_datain[39:30]}),
	.datainfull({44{1'b0}}),
	.dataout(wire_n1OO_dataout),
	.detectrxloop(1'b0),
	.detectrxpowerdn(wire_n00l_txdetectrxpowerdn[3]),
	.digitalreset(wire_n00l_txdigitalresetout[3]),
	.dispval({1'b0}),
	.dividerpowerdn(wire_n00l_txdividerpowerdn[3]),
	.dpriodisable(1'b1),
	.dprioin({150{1'b0}}),
	.dprioout(),
	.enrevparallellpbk(1'b0),
	.forcedisp({1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidle(1'b0),
	.invpol(1'b0),
	.obpowerdn(wire_n00l_txobpowerdn[3]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifooverflow(),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfifordenableout(),
	.phfiforeset(1'b0),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b1),
	.phfifox4rdenable(1'b1),
	.phfifox4wrenable(1'b1),
	.phfifox8bytesel(1'b0),
	.phfifox8rdclk(1'b1),
	.phfifox8rdenable(1'b1),
	.phfifox8wrenable(1'b1),
	.pipepowerdownout(),
	.pipepowerstateout(),
	.pipestatetransdone(1'b0),
	.pllfastclk({1'b0, wire_n00i_clkout}),
	.powerdn({2{1'b0}}),
	.quadreset(wire_n00l_quadresetout),
	.rdenablesync(),
	.refclk(1'b0),
	.refclkout(),
	.revparallelfdbk({20{1'b0}}),
	.revserialfdbk(1'b0),
	.rxdetectvalidout(),
	.rxfoundout(),
	.serialfdbkout(),
	.xgmctrl(wire_n00l_txctrlout[3]),
	.xgmctrlenable(),
	.xgmdatain({wire_n00l_txdataout[31:24]}),
	.xgmdataout());
	defparam
		n1OO.allow_polarity_inversion = "false",
		n1OO.analog_power = "1.2v",
		n1OO.channel_bonding = "none",
		n1OO.channel_number = 3,
		n1OO.channel_width = 10,
		n1OO.common_mode = "0.6v",
		n1OO.disable_ph_low_latency_mode = "false",
		n1OO.disparity_mode = "none",
		n1OO.divider_refclk_select_pll_fast_clk0 = "true",
		n1OO.dprio_config_mode = 0,
		n1OO.dprio_mode = "none",
		n1OO.dprio_width = 150,
		n1OO.enable_bit_reversal = "false",
		n1OO.enable_idle_selection = "false",
		n1OO.enable_reverse_parallel_loopback = "false",
		n1OO.enable_reverse_serial_loopback = "false",
		n1OO.enable_self_test_mode = "false",
		n1OO.enable_slew_rate = "false",
		n1OO.enable_symbol_swap = "false",
		n1OO.enc_8b_10b_compatibility_mode = "false",
		n1OO.enc_8b_10b_mode = "none",
		n1OO.force_echar = "false",
		n1OO.force_kchar = "false",
		n1OO.low_speed_test_select = 0,
		n1OO.preemp_pretap = 0,
		n1OO.preemp_pretap_inv = "false",
		n1OO.preemp_tap_1 = 5,
		n1OO.preemp_tap_2 = 0,
		n1OO.preemp_tap_2_inv = "false",
		n1OO.protocol_hint = "basic",
		n1OO.refclk_divide_by = 1,
		n1OO.refclk_select = "local",
		n1OO.rxdetect_ctrl = 0,
		n1OO.self_test_mode = "incremental",
		n1OO.serializer_clk_select = "local",
		n1OO.termination = "oct_100_ohms",
		n1OO.transmit_protocol = "basic",
		n1OO.use_double_data_mode = "false",
		n1OO.use_serializer_double_data_mode = "false",
		n1OO.use_termvoltage_signal = "false",
		n1OO.vod_selection = 4,
		n1OO.wr_clk_mux_select = "core_clk";
	assign
		tx_clkout = {4{wire_n01O_clkout}},
		tx_dataout = {wire_n1OO_dataout, wire_n01i_dataout, wire_n01l_dataout, wire_n01O_dataout};
endmodule //alt_alt2gxb_raw_x4
//synopsys translate_on
//VALID FILE
