##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Thu Sep 01 00:42:00 2011
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT MIG family Xilinx,_Inc. 3.5
# END Select
# BEGIN Parameters
CSET component_name=xil_mig_v3_5_ddr2
CSET xml_input_file=./xil_mig_v3_5_ddr2/user_design/mig.prj
# END Parameters
GENERATE
# CRC: dd64eca0
