################################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 1.6
##  \   \         Application : Spartan-6 FPGA GTP Transceiver Wizard
##  /   /         Filename : synplify.prj 
## /___/   /\     Timestamp :
## \   \  /  \
##  \___\/\___\
##
##
## synplify.prj
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##

add_file -verilog "../example_design/mgt_usrclk_source.v"
add_file -verilog "../example_design/frame_gen.v"
add_file -verilog "../example_design/frame_check.v"
add_file -verilog "../../xil_s6_gtpwizard_v1_6_dp_tile.v"
add_file -verilog "../../xil_s6_gtpwizard_v1_6_dp.v"
add_file -verilog "../example_design/xil_s6_gtpwizard_v1_6_dp_top.v"

project -result_file "xil_s6_gtpwizard_v1_6_dp_top.edf"
set_option -top_module XIL_S6_GTPWIZARD_V1_6_DP_TOP
set_option -technology spartan6
set_option -part xc6slx45t
set_option -package fgg484
set_option -speed_grade -3

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 160.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -vlog_std v2001

#Do not generate ncf constraints file
set_option -write_apr_constraint 0

