Release 12.2 par M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

LENOVO-A29837C5::  Sat Nov 12 14:11:18 2011

par -w -intstyle ise -ol high -xe n -mt 2 exp6t_disp_map.ncd exp6t_disp.ncd
exp6t_disp.pcf 


Constraints file: exp6t_disp.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\Xilinx\12.2\ISE_DS\ISE\.
   "exp6t_disp" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.

----------------------------------------------------------------------

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRELIMINARY 1.10 2010-06-28".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                 3,435 out of  54,576    6%
    Number used as Flip Flops:               3,433
    Number used as Latches:                      0
    Number used as Latch-thrus:                  2
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      3,931 out of  27,288   14%
    Number used as logic:                    3,816 out of  27,288   13%
      Number using O6 output only:           3,589
      Number using O5 output only:             161
      Number using O5 and O6:                   66
      Number used as ROM:                        0
    Number used as Memory:                      37 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:            37
        Number using O6 output only:            17
        Number using O5 output only:             0
        Number using O5 and O6:                 20
    Number used exclusively as route-thrus:     78
      Number with same-slice register load:     54
      Number with same-slice carry load:        24
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 1,395 out of   6,822   20%
  Number of LUT Flip Flop pairs used:        4,391
    Number with an unused Flip Flop:         1,080 out of   4,391   24%
    Number with an unused LUT:                 460 out of   4,391   10%
    Number of fully used LUT-FF pairs:       2,851 out of   4,391   64%
    Number of slice register sites lost
      to control set restrictions:               0 out of  54,576    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       160 out of     296   54%
    Number of LOCed IOBs:                      160 out of     160  100%
    IOB Flip Flops:                              5
    IOB Master Pads:                             5
    IOB Slave Pads:                              5
    Number of bonded IPADs:                     10 out of      16   62%
    Number of bonded OPADs:                      6 out of       8   75%

Specific Feature Utilization:
  Number of RAMB16BWERs:                        11 out of     116    9%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 2 out of      32    6%
    Number used as BUFIO2s:                      2
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                      15 out of      16   93%
    Number used as BUFGs:                       15
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     2 out of       8   25%
    Number used as DCMs:                         2
    Number used as DCM_CLKGENs:                  0
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:        24 out of     376    6%
    Number used as IODELAY2s:                    0
    Number used as IODRP2s:                      2
    Number used as IODRP2_MCBs:                 22
  Number of OLOGIC2/OSERDES2s:                  49 out of     376   13%
    Number used as OLOGIC2s:                     5
    Number used as OSERDES2s:                   44
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         1 out of       4   25%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of GTPA1_DUALs:                         2 out of       2  100%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                1 out of       2   50%
  Number of PCIE_A1s:                            1 out of       1  100%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            3 out of       4   75%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

PAR will use up to 2 processors
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx
   Command Line Tools User Guide for information on generating a TSI report.
WARNING:Par:288 - The signal TMDS_CEC_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TMDS_HPD_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TMDS_SDA_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TMDS_SCL_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<4>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<5>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<6>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<7>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<8>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<9>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FLAGA_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FLAGB_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FLAGC_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<10>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<11>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<12>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<13>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<14>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_FD<15>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal USB_CLKOUT_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CFG_RESET_N_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<10>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<11>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<12>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<20>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<13>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<21>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<14>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<22>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<15>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<23>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<16>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<24>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<17>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<25>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<26>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<18>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<27>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<19>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<28>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<29>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CFG_RESET_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dipsw<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dipsw<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dipsw<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dipsw<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<4>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<5>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<6>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<7>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<8>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO9C<9>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pushsw<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pushsw<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pushsw<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CFG_MISO_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DP_RSV1_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DP_RSV2_IBUF has no load.  PAR will not attempt to route this signal.
Starting Multi-threaded Router


Phase  1  : 22321 unrouted;      REAL time: 14 secs 

Phase  2  : 18649 unrouted;      REAL time: 20 secs 

Phase  3  : 7474 unrouted;      REAL time: 30 secs 

Phase  4  : 7471 unrouted; (Setup:0, Hold:110208, Component Switching Limit:5028)     REAL time: 33 secs 

Updating file: exp6t_disp.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:102222, Component Switching Limit:5028)     REAL time: 48 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:102222, Component Switching Limit:5028)     REAL time: 48 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:102222, Component Switching Limit:5028)     REAL time: 48 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:102222, Component Switching Limit:5028)     REAL time: 48 secs 
WARNING:Route:522 - Unusually high hold time violation detected among 14 connections.The router will continue and try to fix it 
	crtc1/crtc_rd_reqf_r:CQ -> crtc1/fb_rd_req_r<3>:AX -7315
	crtc1/crtc_rd_vpos_r<7>:AQ -> crtc1/fb_rd_addr_r<7>:AX -6910
	crtc1/crtc_rd_vpos_r<11>:DQ -> crtc1/fb_rd_addr_r<11>:DX -6854
	crtc1/crtc_rd_vpos_r<7>:CQ -> crtc1/fb_rd_addr_r<7>:CX -6820
	crtc1/crtc_rd_vpos_r<7>:DQ -> crtc1/fb_rd_addr_r<7>:DX -6803
	crtc1/crtc_rd_vpos_r<7>:BQ -> crtc1/fb_rd_addr_r<7>:BX -6795
	crtc1/crtc_rd_vpos_r<11>:AQ -> crtc1/fb_rd_addr_r<11>:AX -6695
	crtc1/crtc_rd_vpos_r<11>:CQ -> crtc1/fb_rd_addr_r<11>:CX -6688
	crtc1/crtc_rd_vpos_r<11>:BQ -> crtc1/fb_rd_addr_r<11>:BX -6672
	crtc1/crtc_rd_vpos_r<3>:AQ -> crtc1/fb_rd_addr_r<3>:AX -6420
	crtc1/crtc_rd_vpos_r<3>:CQ -> crtc1/fb_rd_addr_r<3>:CX -6402
	crtc1/crtc_rd_vpos_r<3>:BQ -> crtc1/fb_rd_addr_r<3>:BX -6371
	crtc1/crtc_rd_vpos_r<3>:DQ -> crtc1/fb_rd_addr_r<3>:DX -6232
	crtc1/crtc_cclk_r:AQ -> crtc1/fb_rd_len_r<6>:AX -6187


Phase  9  : 0 unrouted; (Setup:0, Hold:93164, Component Switching Limit:5028)     REAL time: 51 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:92030, Component Switching Limit:5028)     REAL time: 53 secs 
WARNING:Route:452 - 
    Not all timing constraints have been achieved.  Please consult the `Post-Place & Route Static Timing Report' to determine the actual
   timing results.  For suggestions on how to work around this problem go to http://support.xilinx.com and `Search Answers Database' using
   the text of this message.

Total REAL time to Router completion: 53 secs 
Total CPU time to Router completion (all processors): 1 mins 6 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|    GTPCLKOUT1_DCMx1 |  BUFGMUX_X3Y7| No   |  504 |  0.071     |  1.389      |
+---------------------+--------------+------+------+------------+-------------+
|                pclk |  BUFGMUX_X2Y2| No   |  243 |  0.581     |  1.901      |
+---------------------+--------------+------+------+------------+-------------+
|      c3_mcb_drp_clk |  BUFGMUX_X3Y8| No   |  102 |  0.094     |  1.419      |
+---------------------+--------------+------+------+------------+-------------+
|               CLK63 |  BUFGMUX_X3Y5| No   |  117 |  0.049     |  1.384      |
+---------------------+--------------+------+------+------------+-------------+
|             c3_clk0 |  BUFGMUX_X2Y1| No   |   64 |  0.040     |  1.381      |
+---------------------+--------------+------+------+------------+-------------+
|             CLK63x5 | BUFGMUX_X3Y16| No   |   57 |  0.507     |  1.841      |
+---------------------+--------------+------+------+------------+-------------+
|inst_sp6wrap/eptest_ |              |      |      |            |             |
|           i/mgt_clk |  BUFGMUX_X3Y6| No   |    3 |  0.083     |  1.419      |
+---------------------+--------------+------+------+------------+-------------+
|              PLL162 | BUFGMUX_X2Y11| No   |    1 |  0.000     |  1.396      |
+---------------------+--------------+------+------+------------+-------------+
|inst_sp6wrap/eptest_ |              |      |      |            |             |
|        i/mgt_clk_2x |  BUFGMUX_X2Y9| No   |    2 |  0.008     |  1.419      |
+---------------------+--------------+------+------+------------+-------------+
|               CLK27 |         Local|      |  118 |  8.291     | 10.353      |
+---------------------+--------------+------+------+------------+-------------+
|tile1_gtp0_refclk_ib |              |      |      |            |             |
|     ufds_i_ML_IBUF2 |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|tile1_gtp0_refclk_ib |              |      |      |            |             |
|     ufds_i_ML_IBUF1 |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|inst_sp6wrap/refclk_ |              |      |      |            |             |
|       ibuf_ML_IBUF2 |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|inst_sp6wrap/refclk_ |              |      |      |            |             |
|       ibuf_ML_IBUF1 |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|        c3_sysclk_2x |         Local|      |   33 |  0.571     |  1.543      |
+---------------------+--------------+------+------+------------+-------------+
|    c3_sysclk_2x_180 |         Local|      |   37 |  0.590     |  1.562      |
+---------------------+--------------+------+------+------------+-------------+
|memc3_wrapper_inst/m |              |      |      |            |             |
|emc3_mcb_raw_wrapper |              |      |      |            |             |
|   _inst/ioi_drp_clk |         Local|      |   22 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|memc3_wrapper_inst/m |              |      |      |            |             |
|emc3_mcb_raw_wrapper |              |      |      |            |             |
|_inst/idelay_dqs_ioi |              |      |      |            |             |
|                  _s |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|memc3_wrapper_inst/m |              |      |      |            |             |
|emc3_mcb_raw_wrapper |              |      |      |            |             |
|_inst/idelay_dqs_ioi |              |      |      |            |             |
|                  _m |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|memc3_wrapper_inst/m |              |      |      |            |             |
|emc3_mcb_raw_wrapper |              |      |      |            |             |
|_inst/idelay_udqs_io |              |      |      |            |             |
|                 i_s |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|memc3_wrapper_inst/m |              |      |      |            |             |
|emc3_mcb_raw_wrapper |              |      |      |            |             |
|_inst/idelay_udqs_io |              |      |      |            |             |
|                 i_m |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
| tile1_gtp0_refclk_i |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|           GTPRXCLK0 |         Local|      |    2 |  0.000     |  0.761      |
+---------------------+--------------+------+------+------------+-------------+
|           GTPRXCLK1 |         Local|      |    2 |  0.000     |  1.041      |
+---------------------+--------------+------+------+------------+-------------+
|        GTPTXCLKOUT0 |         Local|      |    2 |  0.000     |  1.463      |
+---------------------+--------------+------+------+------------+-------------+
|inst_sp6wrap/sys_clk |              |      |      |            |             |
|                  _c |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 97058 (Setup: 0, Hold: 92030, Component Switching Limit: 5028)

WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.

   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.

   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
   are set in the tools for timing closure.

   Use the Xilinx "SmartXplorer" script to try special combinations of
   options known to produce very good results.

   Visit the Xilinx technical support web at http://support.xilinx.com and go to
   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
   in your design.

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
Number of Timing Constraints that were not applied: 16

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
* TS_memc3_infrastructure_inst_clk0_bufg_in | SETUP       |     0.073ns|     4.927ns|       0|           0
  _0 = PERIOD TIMEGRP         "memc3_infras | HOLD        |    -7.234ns|            |      14|       92030
  tructure_inst_clk0_bufg_in_0"         TS_ |             |            |            |        |            
  clk_wiz_v1_6_50x200_clkfx HIGH 50%        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIO | SETUP       |     1.463ns|    11.337ns|       0|           0
  D TIMEGRP         "inst_sp6wrap_eptest_i_ | HOLD        |     0.138ns|            |       0|           0
  clk_62_5"         TS_inst_sp6wrap_eptest_ | MINPERIOD   |    -3.200ns|    16.000ns|       1|        3200
  i_gt_refclk_buf / 0.625 HIGH 50%          |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD | SETUP       |     2.312ns|     4.088ns|       0|           0
   TIMEGRP         "inst_sp6wrap_eptest_i_c | HOLD        |     0.129ns|            |       0|           0
  lk_125" TS_inst_sp6wrap_eptest_i_gt_refcl | MINPERIOD   |    -1.600ns|     8.000ns|       1|        1600
  k_buf         / 1.25 HIGH 50%             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP "GTPCL | SETUP       |     0.052ns|     6.120ns|       0|           0
  KOUT1_DCM" TS_GTPCLKOUT1_0_ HIGH 50%      | HOLD        |     0.295ns|            |       0|           0
                                            | MINPERIOD   |    -0.228ns|     6.400ns|       1|         228
----------------------------------------------------------------------------------------------------------
  TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD | MINPERIOD   |     0.000ns|     3.200ns|       0|           0
   TIMEGRP         "inst_sp6wrap_eptest_i_c |             |            |            |        |            
  lk_250" TS_inst_sp6wrap_eptest_i_gt_refcl |             |            |            |        |            
  k_buf         / 2.5 HIGH 50%              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIO | SETUP       |     0.070ns|     3.130ns|       0|           0
  D TIMEGRP         "clk_wiz_v1_6_50x62x312 | HOLD        |     0.076ns|            |       0|           0
  _clkout1" TS_xtalclk / 6.25 HIGH 50%      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk_2x_0_0 = | MINPERIOD   |     1.001ns|     1.499ns|       0|           0
   PERIOD TIMEGRP         "memc3_infrastruc |             |            |            |        |            
  ture_inst_clk_2x_0_0" TS_clk_wiz_v1_6_50x |             |            |            |        |            
  200_clkfx /         2 HIGH 50%            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk_2x_180_0 | MINPERIOD   |     1.001ns|     1.499ns|       0|           0
   = PERIOD TIMEGRP         "memc3_infrastr |             |            |            |        |            
  ucture_inst_clk_2x_180_0" TS_clk_wiz_v1_6 |             |            |            |        |            
  _50x200_clkfx         / 2 PHASE 1.25 ns H |             |            |            |        |            
  IGH 50%                                   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk_2x_0 = P | MINPERIOD   |     1.001ns|     1.499ns|       0|           0
  ERIOD TIMEGRP         "memc3_infrastructu |             |            |            |        |            
  re_inst_clk_2x_0" TS_SYS_CLK3 / 2 HIGH 50 |             |            |            |        |            
  %                                         |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk_2x_180 = | MINPERIOD   |     1.001ns|     1.499ns|       0|           0
   PERIOD TIMEGRP         "memc3_infrastruc |             |            |            |        |            
  ture_inst_clk_2x_180" TS_SYS_CLK3 / 2 PHA |             |            |            |        |            
  SE 1.25 ns         HIGH 50%               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk0_bufg_in | MINPERIOD   |     1.430ns|     3.570ns|       0|           0
   = PERIOD TIMEGRP         "memc3_infrastr |             |            |            |        |            
  ucture_inst_clk0_bufg_in" TS_SYS_CLK3 HIG |             |            |            |        |            
  H 50%                                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 5 | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
   ns HIGH 50%                              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIM | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
  EGRP "clk_wiz_v1_6_50x200_clkfx"          |             |            |            |        |            
  TS_xtalclk / 4 HIGH 50%                   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_mcb_drp_clk_ | SETUP       |     1.665ns|    13.340ns|       0|           0
  bufg_in_0 = PERIOD TIMEGRP         "memc3 | HOLD        |     0.414ns|            |       0|           0
  _infrastructure_inst_mcb_drp_clk_bufg_in_ |             |            |            |        |            
  0"         TS_clk_wiz_v1_6_50x200_clkfx / |             |            |            |        |            
   0.25 HIGH 50%                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_inst_sp6wrap_eptest_i_gt_refclk_buf =  | MINLOWPULSE |     4.666ns|     3.334ns|       0|           0
  PERIOD TIMEGRP         "inst_sp6wrap_epte |             |            |            |        |            
  st_i_gt_refclk_buf"         TS_inst_sp6wr |             |            |            |        |            
  ap_eptest_i_gt_refclk_out_0_ HIGH 50%     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_xtalclk = PERIOD TIMEGRP "xtalclk" 20  | MINLOWPULSE |    12.000ns|     8.000ns|       0|           0
  ns HIGH 50%                               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ctm_27x162_clkfx = PERIOD TIMEGRP "ctm | MINPERIOD   |     2.972ns|     3.200ns|       0|           0
  _27x162_clkfx" TS_DP_CLK1 * 6 HIGH        |             |            |            |        |            
    50%                                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_DP_CLK1 = PERIOD TIMEGRP "DP_CLK1" 27  | MINLOWPULSE |    21.036ns|    16.000ns|       0|           0
  MHz HIGH 50%                              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP "GTPCLK | MINPERIOD   |     4.268ns|     1.904ns|       0|           0
  OUT1<0>" 162 MHz HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ | MINPERIOD   |     6.096ns|     1.904ns|       0|           0
   = PERIOD TIMEGRP         "inst_sp6wrap/e |             |            |            |        |            
  ptest_i/gt_refclk_out<0>" 8 ns HIGH 50%   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIO | SETUP       |     6.790ns|     9.210ns|       0|           0
  D TIMEGRP         "clk_wiz_v1_6_50x62x312 | HOLD        |     0.381ns|            |       0|           0
  _clkout0" TS_xtalclk / 1.25 HIGH 50%      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_epcie_refclkn = PERIOD TIMEGRP "epcie_ | MINPERIOD   |     6.800ns|     3.200ns|       0|           0
  refclkn" 100 MHz HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_mcb_drp_clk_ | MINPERIOD   |    17.730ns|     2.270ns|       0|           0
  bufg_in = PERIOD TIMEGRP         "memc3_i |             |            |            |        |            
  nfrastructure_inst_mcb_drp_clk_bufg_in" T |             |            |            |        |            
  S_SYS_CLK3 / 0.25         HIGH 50%        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27  | SETUP       |    28.645ns|     8.392ns|       0|           0
  MHz HIGH 50%                              | HOLD        |     0.254ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_xtalclk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_xtalclk                     |     20.000ns|      8.000ns|     19.708ns|            0|           14|            0|        53993|
| TS_clk_wiz_v1_6_50x200_clkfx  |      5.000ns|      2.800ns|      4.927ns|            0|           14|            0|        31362|
|  TS_memc3_infrastructure_inst_|     20.000ns|     13.340ns|          N/A|            0|            0|        30415|            0|
|  mcb_drp_clk_bufg_in_0        |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  clk_2x_180_0                 |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  clk_2x_0_0                   |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      5.000ns|      4.927ns|          N/A|           14|            0|          947|            0|
|  clk0_bufg_in_0               |             |             |             |             |             |             |             |
| TS_clk_wiz_v1_6_50x62x312_clko|      3.200ns|      3.130ns|          N/A|            0|            0|          133|            0|
| ut1                           |             |             |             |             |             |             |             |
| TS_clk_wiz_v1_6_50x62x312_clko|     16.000ns|      9.210ns|          N/A|            0|            0|        22498|            0|
| ut0                           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_GTPCLKOUT1_0_
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_GTPCLKOUT1_0_               |      6.173ns|      1.904ns|      6.400ns|            0|            1|            0|        12309|
| TS_GTPCLKOUT1_DCM             |      6.173ns|      6.400ns|          N/A|            1|            0|        12309|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_inst_sp6wrap_eptest_i_gt_ref|      8.000ns|      1.904ns|     10.000ns|            0|            2|            0|         9420|
|clk_out_0_                     |             |             |             |             |             |             |             |
| TS_inst_sp6wrap_eptest_i_gt_re|      8.000ns|      3.334ns|     10.000ns|            0|            2|            0|         9420|
| fclk_buf                      |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|      6.400ns|      8.000ns|          N/A|            1|            0|           45|            0|
|  125                          |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|      3.200ns|      3.200ns|          N/A|            0|            0|            0|            0|
|  250                          |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|     12.800ns|     16.000ns|          N/A|            1|            0|         9375|            0|
|  62_5                         |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_DP_CLK1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_DP_CLK1                     |     37.037ns|     16.000ns|     19.200ns|            0|            0|            0|            0|
| TS_ctm_27x162_clkfx           |      6.173ns|      3.200ns|          N/A|            0|            0|            0|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_SYS_CLK3
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK3                    |      5.000ns|      2.800ns|      3.570ns|            0|            0|            0|            0|
| TS_memc3_infrastructure_inst_m|     20.000ns|      2.270ns|          N/A|            0|            0|            0|            0|
| cb_drp_clk_bufg_in            |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
| lk_2x_180                     |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
| lk_2x_0                       |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      5.000ns|      3.570ns|          N/A|            0|            0|            0|            0|
| lk0_bufg_in                   |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

4 constraints not met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 66 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 56 secs 
Total CPU time to PAR completion (all processors): 1 mins 9 secs 

Peak Memory Usage:  314 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 20 errors found.

Number of error messages: 0
Number of warning messages: 71
Number of info messages: 1

Writing design to file exp6t_disp.ncd



PAR done!
