                                                          Log file                                                       

Generated by MIG Version 3.5 on –Ø 9 1 09:41:58 2011


Reading design libraries of xc6slx45t-fgg484... successful !
Creating the temp directory C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_designCreating the directory C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design...successful.
...successful!
Creating the directory C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/par...successful!
Creating the directory C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/docs ...successful! 
Creating the directory C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/synth ...successful! 
Creating the directory C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/sim ...successful! 
Creating the directory C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/rtl ...successful! 

/*******************************************************/
/*                    Controller 3                                                 
/*******************************************************/
Checking pins allocated to Data bits ...
Checking pins allocated to Strobe bits ... 
Checking pins allocated to Mask bits ...
Checking pins allocated to Clock bits ... 
Checking pins allocated to Other_signals bits ...
Checking pins allocated to Other_signals bits ...
Checking pins allocated to Other_signals bits ...
Checking pins allocated to Other_signals bits ...
Checking pins allocated to Control bits ...
Checking pins allocated to Control bits ...
Checking pins allocated to Address bits ...
Checking pins allocated to BankAddress bits ...
Writing the file C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/par/xil_mig_v3_5_ddr2_docinfo_2.xml ...Copying all the files from docs ...
Generating the file C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/rtl/memc3_wrapper.v ...successful!
Generating the file C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/rtl/memc3_infrastructure.v ...successful!
Generating the file C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/sim/ddr2_model_parameters_c3.vh ...successful!
Generating the file C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/sim/ddr2_model_c3.v ...successful!
 ...successful!
Generating the file C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/rtl/memc3_wrapper.v ...successful!
Generating the file C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/sim/memc3_tb_top.v ...successful!
Generating the file C:/PROJECT/EXP6T_DDR2/coregen/tmp/_cg/xil_mig_v3_5_ddr2/user_design/rtl/xil_mig_v3_5_ddr2.v......successful! 


Result:
        Successful!
The design output files are located in C:/PROJECT/EXP6T_DDR2/coregen/xil_mig_v3_5_ddr2/user_design/rtl and ..user_design/par for rtl & ucf files respectively.