################################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 1.6
##  \   \         Application : Spartan-6 FPGA GTP Transceiver Wizard
##  /   /         Filename : xst.scr 
## /___/   /\     Timestamp :
## \   \  /  \
##  \___\/\___\
##
##
## xst.scr 
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##

run
-ifn xst.prj
-ifmt mixed 
-ofn xil_s6_gtpwizard_v1_6_dp_top.ngc 
-ofmt NGC
-p xc6slx45t-3fgg484
-top XIL_S6_GTPWIZARD_V1_6_DP_TOP
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter []
-case maintain
-slice_utilization_ratio 100
-fsm_extract YES
-fsm_encoding Auto
-ram_extract No
-ram_style Auto
-rom_extract No
-rom_style Auto
-shreg_extract YES
-resource_sharing YES
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 16
-register_duplication YES
-equivalent_register_removal YES
-register_balancing No
-signal_encoding user
-iob true
-slice_utilization_ratio_maxmargin 5

