#NET "crtc/crtc_reg10_r[*]" TIG;
#NET "crtc/crtc_reg11_r[*]" TIG;
#NET "crtc/crtc_reg00_r[*]" TIG;
#NET "crtc/crtc_reg01_r[*]" TIG;
#NET "crtc/crtc_reg02_r[*]" TIG;
#NET "crtc/crtc_reg03_r[*]" TIG;
#NET "crtc/crtc_reg04_r[*]" TIG;
#NET "crtc/crtc_reg05_r[*]" TIG;
#NET "crtc/crtc_reg06_r[*]" TIG;
#NET "crtc/crtc_reg07_r[*]" TIG;

CONFIG VCCAUX=3.3; # Valid values are 2.5 and 3.3

##################################################################
# System clock and LEDs, SWs
##################################################################

NET "xtalclk" TNM_NET = "xtalclk";
TIMESPEC TS_xtalclk = PERIOD "xtalclk" 20 ns HIGH 50 %;

NET "xtalclk" CLOCK_DEDICATED_ROUTE = FALSE;

NET "dipsw[*]" TIG;
NET "pushsw[*]" TIG;
NET "led[*]" TIG;
#NET "GPIO9C[*]" TIG;
NET "GPIO1C[*]" TIG;

NET "xtalclk" LOC = "U12" | IOSTANDARD = LVCMOS33;
NET "dipsw<0>" LOC = U22 | IOstandard = LVCMOS33;
NET "dipsw<1>" LOC = V22 | IOstandard = LVCMOS33;
NET "dipsw<2>" LOC = P21 | IOstandard = LVCMOS33;
NET "dipsw<3>" LOC = P20 | IOstandard = LVCMOS33;
NET "pushsw<0>"  LOC = Y22 | IOstandard = LVCMOS33;
NET "pushsw<1>"  LOC = W22 | IOstandard = LVCMOS33;
NET "pushsw<2>"  LOC = Y21 | IOstandard = LVCMOS33;
NET "pushsw<3>"  LOC = W20 | IOstandard = LVCMOS33;

NET "led<0>"  LOC = R20 | IOstandard = LVCMOS33;
NET "led<1>"  LOC = R22 | IOstandard = LVCMOS33;
NET "led<2>"  LOC = T21 | IOstandard = LVCMOS33;
NET "led<3>"  LOC = T22 | IOstandard = LVCMOS33;
NET "led<4>"  LOC = U20 | IOstandard = LVCMOS33;
NET "led<5>"  LOC = V21 | IOstandard = LVCMOS33;
NET "led<6>"  LOC = P22 | IOstandard = LVCMOS33;
NET "led<7>"  LOC = T20 | IOstandard = LVCMOS33;

##################################################################
# Gigabit tranceiver channel
##################################################################

#for PCIe CARD EDGE
NET "epcie_txp" LOC = B8;
NET "epcie_txn" LOC = A8;
NET "epcie_rxp" LOC = D9;
NET "epcie_rxn" LOC = C9;
NET "epcie_refclkn" LOC = D11; # EPCIE
NET "epcie_refclkp" LOC = C11; # EPCIE
NET "epcie_perst"    LOC = F15;
NET "epcie_wake"     LOC = G13;

##for PCIe external cabling
#NET "cpcie_txp" LOC = B6;
#NET "cpcie_txn" LOC = A6;
#NET "cpcie_rxp" LOC = D7;
#NET "cpcie_rxn" LOC = C7;
#NET "cpcie_refclkn" LOC = B10;
#NET "cpcie_refclkp" LOC = A10;
#NET "cpcie_perst"    LOC = A2;
#NET "cpcie_wake"     LOC = B3;

#for SATA
NET "sata_txp0" LOC = B14;
NET "sata_txn0" LOC = A14;
NET "sata_rxp0" LOC = D13;
NET "sata_rxn0" LOC = C13;
NET "sata_txp1" LOC = B16;
NET "sata_txn1" LOC = A16;
NET "sata_rxp1" LOC = D15;
NET "sata_rxn1" LOC = C15;
NET "sata_refclkn" LOC = B12;
NET "sata_refclkp" LOC = A12;


NET "GTPCLKOUT1<0>" TNM_NET = GTPCLKOUT1<0>;
TIMESPEC TS_GTPCLKOUT1_0_ = PERIOD "GTPCLKOUT1<0>" 162 MHz HIGH 50%;

#NET "GTPCLKOUT0<0>" TNM_NET = GTPCLKOUT0<0>;
#TIMESPEC TS_GTPCLKOUT0_0_ = PERIOD "GTPCLKOUT0<0>" 150 MHz HIGH 50%;

NET "epcie_refclkn" TNM_NET = epcie_refclkn;
TIMESPEC TS_epcie_refclkn = PERIOD "epcie_refclkn" 100 MHz HIGH 50%;
NET "inst_sp6wrap/eptest_i/gt_refclk_out<0>" TNM_NET = inst_sp6wrap/eptest_i/gt_refclk_out<0>;
TIMESPEC TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD "inst_sp6wrap/eptest_i/gt_refclk_out<0>" 8 ns HIGH 50%;


##################################################################
# GPIO
##################################################################

NET "DP_CLK1" TNM_NET = "DP_CLK1";
TIMESPEC TS_DP_CLK1 = PERIOD "DP_CLK1" 27 MHz HIGH 50 %;
NET "DP_CLK0" TNM_NET = "DP_CLK0";
TIMESPEC TS_DP_CLK0 = PERIOD "DP_CLK0" 27 MHz HIGH 50 %;

NET "DP_CLK1" CLOCK_DEDICATED_ROUTE = FALSE;
NET "DP_CLK0" CLOCK_DEDICATED_ROUTE = "FALSE";

PIN "clk_wiz_v1_6_50x62x312/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;

NET "GPIO9C<0>" LOC = "AA18" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<1>" LOC = "AB18" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<2>" LOC = "Y17" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<3>" LOC = "AB17" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<4>" LOC = "AA16" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<5>" LOC = "AB16" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<6>" LOC = "Y15" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<7>" LOC = "AB15" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<8>" LOC = "AA14" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<9>" LOC = "AB14" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<10>" LOC = "Y13" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<11>" LOC = "AB13" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<12>" LOC = "AA12" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<13>" LOC = "AB12" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<14>" LOC = "Y11" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<15>" LOC = "AB11" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<16>" LOC = "AA10" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<17>" LOC = "AB10" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<18>" LOC = "Y9 " | IOSTANDARD = LVCMOS33;
NET "GPIO9C<19>" LOC = "AB9" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<20>" LOC = "AA8" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<21>" LOC = "AB8" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<22>" LOC = "Y7 " | IOSTANDARD = LVCMOS33;
NET "GPIO9C<23>" LOC = "AB7" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<24>" LOC = "AA6" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<25>" LOC = "AB6" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<26>" LOC = "Y5 " | IOSTANDARD = LVCMOS33;
NET "GPIO9C<27>" LOC = "AB5" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<28>" LOC = "AA4" | IOSTANDARD = LVCMOS33;
NET "GPIO9C<29>" LOC = "AB4" | IOSTANDARD = LVCMOS33;

NET "TMDS_CH2_P" LOC = "W17" | IOSTANDARD = TMDS_33; # GPIO1C<0>
NET "TMDS_CH2_N" LOC = "Y18" | IOSTANDARD = TMDS_33;
NET "TMDS_CH1_P" LOC = "V17" | IOSTANDARD = TMDS_33;
NET "TMDS_CH1_N" LOC = "W18" | IOSTANDARD = TMDS_33;
NET "TMDS_CH0_P" LOC = "U16" | IOSTANDARD = TMDS_33;
NET "TMDS_CH0_N" LOC = "V15" | IOSTANDARD = TMDS_33;
NET "TMDS_CLK_P" LOC = "U14" | IOSTANDARD = TMDS_33;
NET "TMDS_CLK_N" LOC = "U13" | IOSTANDARD = TMDS_33;
NET "TMDS_CEC" LOC = "W14" | IOSTANDARD = LVCMOS33;
NET "TMDS_SCL" LOC = "Y14" | IOSTANDARD = LVCMOS33;
NET "TMDS_SDA" LOC = "V13" | IOSTANDARD = LVCMOS33;
NET "TMDS_HPD" LOC = "W13" | IOSTANDARD = LVCMOS33;
NET "DP_RSV1" LOC = "W12" | IOSTANDARD = LVCMOS33;
NET "DP_RSV2" LOC = "Y12" | IOSTANDARD = LVCMOS33;
NET "DP_AUX_P" LOC = "V11" | IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
NET "DP_AUX_N" LOC = "W11" | IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
NET "DP_AUXO_P" LOC = "W10" | IOSTANDARD = LVDS_33;
NET "DP_AUXO_N" LOC = "Y10" | IOSTANDARD = LVDS_33;
NET "DP_HPD" LOC = "W9" | IOSTANDARD = LVCMOS33;
NET "DP_RST_N" LOC = "Y8" | IOSTANDARD = LVCMOS33;
NET "DP_CLK0" LOC = "U9" | IOSTANDARD = LVCMOS33;
NET "DP_CLK1" LOC = "V9" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<22>" LOC = "T8" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<23>" LOC = "U8" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<24>" LOC = "W6" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<25>" LOC = "Y6" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<26>" LOC = "T7" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<27>" LOC = "U6" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<28>" LOC = "T10" | IOSTANDARD = LVCMOS33;
NET "GPIO1C<29>" LOC = "U10" | IOSTANDARD = LVCMOS33;
#NET "GPIO<*>" IOSTANDARD = LVCMOS33;

##################################################################
# EZ-USB FX2 Interface
##################################################################

NET "usb_clkout" TNM_NET = "usb_clkout";
TIMESPEC "TS_usb_clkout" = PERIOD "usb_clkout" 20 ns HIGH 50 %;

NET "USB_FD<0>"      LOC = "E22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<1>"      LOC = "D22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<2>"      LOC = "D21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<3>"      LOC = "C22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<4>"      LOC = "F20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<5>"      LOC = "F22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<6>"      LOC = "F21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<7>"      LOC = "G22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<8>"      LOC = "N20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<9>"      LOC = "M20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<10>"     LOC = "K20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<11>"     LOC = "J20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<12>"     LOC = "H20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<13>"     LOC = "G20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<14>"     LOC = "E20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FD<15>"     LOC = "C20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FLAGA"      LOC = "H22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FLAGB"      LOC = "H21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FLAGC"      LOC = "J22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_SLRD"       LOC = "B21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_SLWR"       LOC = "B22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_SLOE"       LOC = "K22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FIFOADR<0>" LOC = "K21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_FIFOADR<1>" LOC = "M22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_PKTEND"     LOC = "M21" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_CLKOUT"     LOC = "L20" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_IFCLK"      LOC = "L22" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "USB_RESET"      LOC = "N22" | PULLUP | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;

##################################################################
# SPI Configuration Memory
##################################################################

NET "CFG_CSO"           LOC = "AA3" | IOSTANDARD = LVCMOS33;
NET "CFG_CCLK"          LOC = "Y20" | IOSTANDARD = LVCMOS33;
NET "CFG_MISO"          LOC = "AA20" | IOSTANDARD = LVCMOS33;
NET "CFG_MOSI"          LOC = "AB20" | IOSTANDARD = LVCMOS33;

#NET "CFG_M0"          LOC = "AA21" | IOSTANDARD = LVCMOS33;
#NET "CFG_M1"          LOC = "Y19" | IOSTANDARD = LVCMOS33;
NET "CFG_RESET_N"      LOC = "AA21" | IOSTANDARD = LVCMOS33;
NET "CFG_RESET"        LOC = "Y19" | IOSTANDARD = LVCMOS33;

############################################################################
## 
##  Xilinx, Inc. 2006            www.xilinx.com 
##  “y 8 13 23:52:15 2011
##  Generated by MIG Version 3.5
##  
############################################################################
##  File name :       example_top.ucf
## 
##  Details :     Constraints file
##                    FPGA family:       spartan6
##                    FPGA:              xc6slx45t-fgg484
##                    Speedgrade:        -3
##                    Design Entry:      VERILOG
##                    Design:            with Test bench
##                    DCM Used:          Enable
##                    No.Of Memory Controllers: 1
##
############################################################################ 

############################################################################
# Extended MCB performance mode requires a different Vccint specification to
# achieve higher maximum frequencies for DDR2 and DDR3.Consult the Spartan-6
#datasheet (DS162) table 2 and 24 for more information 
############################################################################
CONFIG MCB_PERFORMANCE= STANDARD;


##################################################################################
# Timing Ignore constraints for paths crossing the clock domain 
##################################################################################
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c?_pll_lock" TIG;
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG;
     

############################################################################
## Memory Controller 3                               
## Memory Device: DDR2_SDRAM->MT47H32M16XX-37E 
## Frequency: 200.000 MHz
## Time Period: 5000 ps
## Supported Part Numbers: MT47H32M16BN-37E;MT47H32M16CC-37E;MT47H32M16FN-37E;MT47H32M16GC-37E;MT47H32M16BN-37E-L
############################################################################

############################################################################
## Clock constraints                                                        
############################################################################
NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3"  5  ns HIGH 50 %;

############################################################################

############################################################################
## I/O TERMINATION                                                          
############################################################################
NET "mcb3_dram_dq[*]"                                 IN_TERM = NONE;
NET "mcb3_dram_dqs"                                   IN_TERM = NONE;
NET "mcb3_dram_dqs_n"                                 IN_TERM = NONE;
NET "mcb3_dram_udqs"                                  IN_TERM = NONE;
NET "mcb3_dram_udqs_n"                                IN_TERM = NONE;

############################################################################
# Status Signals 
############################################################################

############################################################################
# I/O STANDARDS 
############################################################################

NET  "mcb3_dram_dq[*]"                               IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_a[*]"                                IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_ba[*]"                               IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_ba2"                                 IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_dqs"                                 IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_udqs"                                IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_dqs_n"                               IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_udqs_n"                              IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_ck"                                  IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_ck_n"                                IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_cke"                                 IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_ras_n"                               IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_cas_n"                               IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_we_n"                                IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_odt"                                 IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_dm"                                  IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_udm"                                 IOSTANDARD = SSTL18_II;
NET  "mcb3_rzq"                                      IOSTANDARD = SSTL18_II;
NET  "mcb3_zio"                                      IOSTANDARD = SSTL18_II;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################

NET  "mcb3_dram_a[0]"                            LOC = "K2" ;
NET  "mcb3_dram_a[10]"                           LOC = "J4" ;
NET  "mcb3_dram_a[11]"                           LOC = "E1" ;
NET  "mcb3_dram_a[12]"                           LOC = "F1" ;
NET  "mcb3_dram_a[1]"                            LOC = "K1" ;
NET  "mcb3_dram_a[2]"                            LOC = "K5" ;
NET  "mcb3_dram_a[3]"                            LOC = "M6" ;
NET  "mcb3_dram_a[4]"                            LOC = "H3" ;
NET  "mcb3_dram_a[5]"                            LOC = "M3" ;
NET  "mcb3_dram_a[6]"                            LOC = "L4" ;
NET  "mcb3_dram_a[7]"                            LOC = "K6" ;
NET  "mcb3_dram_a[8]"                            LOC = "G3" ;
NET  "mcb3_dram_a[9]"                            LOC = "G1" ;
NET  "mcb3_dram_ba[0]"                           LOC = "J3" ;
NET  "mcb3_dram_ba[1]"                           LOC = "J1" ;
NET  "mcb3_dram_ba2"                             LOC = "H1" ;
NET  "mcb3_dram_cas_n"                           LOC = "M4" ;
NET  "mcb3_dram_ck"                              LOC = "K4" ;
NET  "mcb3_dram_ck_n"                            LOC = "K3" ;
NET  "mcb3_dram_cke"                             LOC = "F2" ;
NET  "mcb3_dram_dm"                              LOC = "N4" ;
NET  "mcb3_dram_dqs"                             LOC = "N3" ;
NET  "mcb3_dram_dqs_n"                           LOC = "N1" ;
NET  "mcb3_dram_odt"                             LOC = "L6" ;
NET  "mcb3_dram_ras_n"                           LOC = "M5" ;
NET  "mcb3_dram_udm"                             LOC = "P3" ;
NET  "mcb3_dram_udqs"                            LOC = "V2" ;
NET  "mcb3_dram_udqs_n"                          LOC = "V1" ;
NET  "mcb3_dram_we_n"                            LOC = "H2" ;

NET  "mcb3_dram_dq[0]"                           LOC = "R3" ;
NET  "mcb3_dram_dq[1]"                           LOC = "R1" ;
NET  "mcb3_dram_dq[2]"                           LOC = "P2" ;
NET  "mcb3_dram_dq[3]"                           LOC = "P1" ;
NET  "mcb3_dram_dq[4]"                           LOC = "L3" ;
NET  "mcb3_dram_dq[5]"                           LOC = "L1" ;
NET  "mcb3_dram_dq[6]"                           LOC = "M2" ;
NET  "mcb3_dram_dq[7]"                           LOC = "M1" ;
NET  "mcb3_dram_dq[8]"                           LOC = "T2" ;
NET  "mcb3_dram_dq[9]"                           LOC = "T1" ;
NET  "mcb3_dram_dq[10]"                          LOC = "U3" ;
NET  "mcb3_dram_dq[11]"                          LOC = "U1" ;
NET  "mcb3_dram_dq[12]"                          LOC = "W3" ;
NET  "mcb3_dram_dq[13]"                          LOC = "W1" ;
NET  "mcb3_dram_dq[14]"                          LOC = "Y2" ;
NET  "mcb3_dram_dq[15]"                          LOC = "Y1" ;

##################################################################################
#RZQ is required for all MCB designs.   Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value.  Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET  "mcb3_rzq"                                  LOC = "R7" ;
##################################################################################
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
##################################################################################
NET  "mcb3_zio"                                  LOC = "W4" ;

