################################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 1.6
##  \   \         Application : Spartan-6 FPGA GTP Transceiver Wizard
##  /   /         Filename : gtp_attributes.ucf
## /___/   /\     Timestamp : 
## \   \  /  \ 
##  \___\/\___\
##
##
## GTP ATTRIBUTES 
## This file contains the attributes for the active GTP transceivers in the
## design. If you would like to use this file in your design, please make
## sure that the path to the GTPA1_DUAL instance is correct.
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##

############################## Active GTP Attributes #######################
 
##_____________________ Attributes for GTPA1_DUAL 0___________________
 

##PLL Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLKINDC_B_0                            = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLKRCV_TRST_0                          = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i OOB_CLK_DIVIDER_0                      = 6;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_COM_CFG_0                          = 24'h21680a;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_CP_CFG_0                           = 8'h00;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_RXDIVSEL_OUT_0                     = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_SATA_0                             = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_SOURCE_0                           = "PLL0";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_TXDIVSEL_OUT_0                     = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLLLKDET_CFG_0                         = 3'b111;

##
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLKINDC_B_1                            = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLKRCV_TRST_1                          = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i OOB_CLK_DIVIDER_1                      = 4;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_COM_CFG_1                          = 24'h21680a;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_CP_CFG_1                           = 8'h00;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_RXDIVSEL_OUT_1                     = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_SATA_1                             = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_SOURCE_1                           = "PLL1";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLL_TXDIVSEL_OUT_1                     = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PLLLKDET_CFG_1                         = 3'b111;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_COM_CFG_EAST                       = 36'h000008000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_COM_CFG_WEST                       = 36'h00000a000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TST_ATTR_0                             = 32'h00000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TST_ATTR_1                             = 32'h00000000;

##TX Interface Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_OUT_GTP_SEL_0                      = "TXOUTCLK0";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_TDCC_CFG_0                          = 2'b11;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_OUT_GTP_SEL_1                      = "TXOUTCLK1";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_TDCC_CFG_1                          = 2'b11;

##TX Buffer and Phase Alignment Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_TX_CFG_0                           = 20'h00082;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_BUFFER_USE_0                        = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_XCLK_SEL_0                          = "TXOUT";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TXRX_INVERT_0                          = 3'b011;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_TX_CFG_1                           = 20'h00082;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_BUFFER_USE_1                        = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_XCLK_SEL_1                          = "TXOUT";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TXRX_INVERT_1                          = 3'b111;

##TX Driver and OOB signalling Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CM_TRIM_0                              = 2'b00;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_IDLE_DELAY_0                        = 3'b011;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CM_TRIM_1                              = 2'b00;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_IDLE_DELAY_1                        = 3'b011;

##TX PIPE/SATA Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i COM_BURST_VAL_0                        = 4'b1111;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i COM_BURST_VAL_1                        = 4'b1111;

##RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i AC_CAP_DIS_0                           = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i OOBDETECT_THRESHOLD_0                  = 3'b110;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_CDR_SCAN_0                         = 27'h6404040;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_RX_CFG_0                           = 25'h05ce089;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_RXSYNC_CFG_0                       = 7'h00;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RCV_TERM_GND_0                         = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RCV_TERM_VTTRX_0                       = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RXEQ_CFG_0                             = 8'b01111011;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TERMINATION_CTRL_0                     = 5'b10100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TERMINATION_OVRD_0                     = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_DETECT_RX_CFG_0                     = 14'h1832;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i AC_CAP_DIS_1                           = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i OOBDETECT_THRESHOLD_1                  = 3'b110;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_CDR_SCAN_1                         = 27'h6404040;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_RX_CFG_1                           = 25'h05ce004;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PMA_RXSYNC_CFG_1                       = 7'h00;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RCV_TERM_GND_1                         = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RCV_TERM_VTTRX_1                       = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RXEQ_CFG_1                             = 8'b01111011;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TERMINATION_CTRL_1                     = 5'b10100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TERMINATION_OVRD_1                     = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TX_DETECT_RX_CFG_1                     = 14'h1832;

##PRBS Detection Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RXPRBSERR_LOOPBACK_0                   = 1'b0;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RXPRBSERR_LOOPBACK_1                   = 1'b0;

##Comma Detection and Alignment Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i ALIGN_COMMA_WORD_0                     = 2;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i COMMA_10B_ENABLE_0                     = 10'b1111111111;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i DEC_MCOMMA_DETECT_0                    = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i DEC_PCOMMA_DETECT_0                    = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i DEC_VALID_COMMA_ONLY_0                 = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i MCOMMA_10B_VALUE_0                     = 10'b1010000011;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i MCOMMA_DETECT_0                        = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PCOMMA_10B_VALUE_0                     = 10'b0101111100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PCOMMA_DETECT_0                        = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_SLIDE_MODE_0                        = "PCS";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i ALIGN_COMMA_WORD_1                     = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i COMMA_10B_ENABLE_1                     = 10'b1111111111;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i DEC_MCOMMA_DETECT_1                    = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i DEC_PCOMMA_DETECT_1                    = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i DEC_VALID_COMMA_ONLY_1                 = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i MCOMMA_10B_VALUE_1                     = 10'b1010000011;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i MCOMMA_DETECT_1                        = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PCOMMA_10B_VALUE_1                     = 10'b0101111100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PCOMMA_DETECT_1                        = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_SLIDE_MODE_1                        = "PCS";

##RX Loss-of-sync State Machine Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_LOS_INVALID_INCR_0                  = 8;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_LOS_THRESHOLD_0                     = 128;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_LOSS_OF_SYNC_FSM_0                  = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_LOS_INVALID_INCR_1                  = 8;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_LOS_THRESHOLD_1                     = 128;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_LOSS_OF_SYNC_FSM_1                  = "TRUE";

##RX Elastic Buffer and Phase alignment Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_BUFFER_USE_0                        = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_IDLE_RESET_BUF_0                 = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_IDLE_HI_CNT_0                       = 4'b1000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_IDLE_LO_CNT_0                       = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_XCLK_SEL_0                          = "RXREC";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_BUFFER_USE_1                        = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_IDLE_RESET_BUF_1                 = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_IDLE_HI_CNT_1                       = 4'b1000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_IDLE_LO_CNT_1                       = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_XCLK_SEL_1                          = "RXREC";

##Clock Correction Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_ADJ_LEN_0                      = 4;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_DET_LEN_0                      = 4;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_INSERT_IDLE_FLAG_0             = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_KEEP_IDLE_0                    = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_MAX_LAT_0                      = 18;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_MIN_LAT_0                      = 16;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_PRECEDENCE_0                   = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_REPEAT_WAIT_0                  = 0;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_1_0                      = 10'b0110111100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_2_0                      = 10'b0001001010;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_3_0                      = 10'b0001001010;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_4_0                      = 10'b0001111011;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_ENABLE_0                 = 4'b1111;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_1_0                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_2_0                      = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_3_0                      = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_4_0                      = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_ENABLE_0                 = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_USE_0                    = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_CORRECT_USE_0                      = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_DECODE_SEQ_MATCH_0                  = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_ADJ_LEN_1                      = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_DET_LEN_1                      = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_INSERT_IDLE_FLAG_1             = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_KEEP_IDLE_1                    = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_MAX_LAT_1                      = 18;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_MIN_LAT_1                      = 16;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_PRECEDENCE_1                   = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_REPEAT_WAIT_1                  = 5;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_1_1                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_2_1                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_3_1                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_4_1                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_1_ENABLE_1                 = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_1_1                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_2_1                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_3_1                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_4_1                      = 10'b0100000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_ENABLE_1                 = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_COR_SEQ_2_USE_1                    = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CLK_CORRECT_USE_1                      = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_DECODE_SEQ_MATCH_1                  = "TRUE";

##Channel Bonding Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_1_MAX_SKEW_0                 = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_2_MAX_SKEW_0                 = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_KEEP_ALIGN_0                 = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_1_0                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_2_0                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_3_0                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_4_0                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_ENABLE_0               = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_1_0                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_2_0                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_3_0                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_4_0                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_ENABLE_0               = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_USE_0                  = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_LEN_0                    = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_MODE_RESET_BUF_0                 = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_1_MAX_SKEW_1                 = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_2_MAX_SKEW_1                 = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_KEEP_ALIGN_1                 = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_1_1                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_2_1                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_3_1                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_4_1                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_1_ENABLE_1               = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_1_1                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_2_1                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_3_1                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_4_1                    = 10'b0000000000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_ENABLE_1               = 4'b0000;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_2_USE_1                  = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CHAN_BOND_SEQ_LEN_1                    = 1;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_MODE_RESET_BUF_1                 = "FALSE";

##RX PCI Express Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CB2_INH_CC_PERIOD_0                    = 8;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CDR_PH_ADJ_TIME_0                      = 5'b01010;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PCI_EXPRESS_MODE_0                     = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_IDLE_HOLD_CDR_0                  = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_IDLE_RESET_FR_0                  = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_IDLE_RESET_PH_0                  = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_STATUS_FMT_0                        = "SATA";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TRANS_TIME_FROM_P2_0                   = 12'h03c;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TRANS_TIME_NON_P2_0                    = 8'h19;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TRANS_TIME_TO_P2_0                     = 10'h064;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CB2_INH_CC_PERIOD_1                    = 8;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i CDR_PH_ADJ_TIME_1                      = 5'b01010;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i PCI_EXPRESS_MODE_1                     = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_IDLE_HOLD_CDR_1                  = "FALSE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_IDLE_RESET_FR_1                  = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_EN_IDLE_RESET_PH_1                  = "TRUE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i RX_STATUS_FMT_1                        = "PCIE";
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TRANS_TIME_FROM_P2_1                   = 12'h03c;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TRANS_TIME_NON_P2_1                    = 8'h19;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i TRANS_TIME_TO_P2_1                     = 10'h064;

##RX SATA Attributes
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_BURST_VAL_0                       = 3'b100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_IDLE_VAL_0                        = 3'b100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MAX_BURST_0                       = 7;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MAX_INIT_0                        = 22;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MAX_WAKE_0                        = 7;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MIN_BURST_0                       = 4;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MIN_INIT_0                        = 12;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MIN_WAKE_0                        = 4;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_BURST_VAL_1                       = 3'b100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_IDLE_VAL_1                        = 3'b100;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MAX_BURST_1                       = 10;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MAX_INIT_1                        = 29;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MAX_WAKE_1                        = 10;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MIN_BURST_1                       = 5;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MIN_INIT_1                        = 16;
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i SATA_MIN_WAKE_1                        = 5;



