<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
					twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
							   NETDELAY | 
							   NETSKEW | 
							   PATH |
							   DEFPERIOD |
							   UNCONSTPATH |
							   DEFPATH | 
							   PATH2SETUP |
							   UNCONSTPATH2SETUP | 
							   PATHCLASS | 
							   PATHDELAY | 
							   PERIOD |
							   FREQUENCY |
							   PATHBLOCK |
							   OFFSET |
							   OFFSETIN |
							   OFFSETINCLOCK | 
							   UNCONSTOFFSETINCLOCK |
							   OFFSETINDELAY |
							   OFFSETINMOD |
							   OFFSETOUT |
							   OFFSETOUTCLOCK |
							   UNCONSTOFFSETOUTCLOCK | 
							   OFFSETOUTDELAY |
							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
					   twEndPtCnt?,
					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
						twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
					  fDCMJit CDATA #IMPLIED
					  fPhaseErr CDATA #IMPLIED
					  sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
					  best CDATA #IMPLIED requested CDATA #IMPLIED
					  errors CDATA #IMPLIED
					  score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 12.2 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml exp6t_disp.twx exp6t_disp.ncd -o exp6t_disp.twr
exp6t_disp.pcf

</twCmdLine><twDesign>exp6t_disp.ncd</twDesign><twDesignPath>exp6t_disp.ncd</twDesignPath><twPCF>exp6t_disp.pcf</twPCF><twPcfPath>exp6t_disp.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx45t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRELIMINARY 1.10 2010-06-28</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_xtalclk = PERIOD TIMEGRP &quot;xtalclk&quot; 20 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>8.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: TS_xtalclk = PERIOD TIMEGRP &quot;xtalclk&quot; 20 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="7" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="2.249" period="3.200" constraintValue="3.200" deviceLimit="0.951" freqLimit="1051.525" physResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1" logResource="clk_wiz_v1_6_50x62x312/pll_base_inst/PLL_ADV/CLKOUT1" locationPin="PLL_ADV_X0Y3.CLKOUT1" clockNet="clk_wiz_v1_6_50x62x312/clkout1"/><twPinLimit anchorID="8" type="MINPERIOD" name="Tdcmper_CLKFX" slack="2.330" period="5.000" constraintValue="5.000" deviceLimit="2.670" freqLimit="374.532" physResource="clk_wiz_v1_6_50x200/dcm_sp_inst/CLKFX" logResource="clk_wiz_v1_6_50x200/dcm_sp_inst/CLKFX" locationPin="DCM_X0Y6.CLKFX" clockNet="clk_wiz_v1_6_50x200/clkfx"/><twPinLimit anchorID="9" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="12.000" period="20.000" constraintValue="10.000" deviceLimit="4.000" physResource="clk_wiz_v1_6_50x200/dcm_sp_inst/CLKIN" logResource="clk_wiz_v1_6_50x200/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y6.CLKIN" clockNet="clk_wiz_v1_6_50x200/clkin1"/></twPinLimitRpt></twConst><twConst anchorID="10" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP &quot;GTPCLKOUT1&lt;0&gt;&quot; 180 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.904</twMinPer></twConstHead><twPinLimitRpt anchorID="11"><twPinLimitBanner>Component Switching Limit Checks: TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP &quot;GTPCLKOUT1&lt;0&gt;&quot; 180 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="12" type="MINPERIOD" name="Tbufper_I" slack="3.651" period="5.555" constraintValue="5.555" deviceLimit="1.904" freqLimit="525.210" physResource="gtpclkout1_0_dcm2_bufio2_i/I" logResource="gtpclkout1_0_dcm2_bufio2_i/I" locationPin="BUFIO2_X4Y26.I" clockNet="GTPCLKOUT1&lt;0&gt;"/></twPinLimitRpt></twConst><twConst anchorID="13" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_epcie_refclkn = PERIOD TIMEGRP &quot;epcie_refclkn&quot; 100 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.200</twMinPer></twConstHead><twPinLimitRpt anchorID="14"><twPinLimitBanner>Component Switching Limit Checks: TS_epcie_refclkn = PERIOD TIMEGRP &quot;epcie_refclkn&quot; 100 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="15" type="MINPERIOD" name="Tgtpcper_CLK" slack="6.800" period="10.000" constraintValue="10.000" deviceLimit="3.200" freqLimit="312.500" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/CLK01" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/CLK01" locationPin="GTPA1_DUAL_X0Y0.CLK11" clockNet="inst_sp6wrap/sys_clk_c"/></twPinLimitRpt></twConst><twConst anchorID="16" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD TIMEGRP         &quot;inst_sp6wrap/eptest_i/gt_refclk_out&lt;0&gt;&quot; 8 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.904</twMinPer></twConstHead><twPinLimitRpt anchorID="17"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD TIMEGRP
        &quot;inst_sp6wrap/eptest_i/gt_refclk_out&lt;0&gt;&quot; 8 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="18" type="MINPERIOD" name="Tbufper_I" slack="6.096" period="8.000" constraintValue="8.000" deviceLimit="1.904" freqLimit="525.210" physResource="inst_sp6wrap/eptest_i/gt_refclk_bufio2/I" logResource="inst_sp6wrap/eptest_i/gt_refclk_bufio2/I" locationPin="BUFIO2_X2Y26.I" clockNet="inst_sp6wrap/eptest_i/gt_refclk_out&lt;0&gt;"/></twPinLimitRpt></twConst><twConst anchorID="19" twConstType="PERIOD" ><twConstHead uID="5"><twConstName UCFConstName="" ScopeName="">TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPinLimitRpt anchorID="20"><twPinLimitBanner>Component Switching Limit Checks: TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="21" type="MINPERIOD" name="Tdcmper_CLKFX" slack="3.503" period="6.173" constraintValue="6.173" deviceLimit="2.670" freqLimit="374.532" physResource="ctm_27x162/dcm_sp_inst/CLKFX" logResource="ctm_27x162/dcm_sp_inst/CLKFX" locationPin="DCM_X0Y7.CLKFX" clockNet="ctm_27x162/clkfx"/><twPinLimit anchorID="22" type="MINLOWPULSE" name="Tdcmpw_CLKIN_25_50" slack="21.037" period="37.037" constraintValue="18.518" deviceLimit="8.000" physResource="ctm_27x162/dcm_sp_inst/CLKIN" logResource="ctm_27x162/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y7.CLKIN" clockNet="ctm_27x162/clkin1"/><twPinLimit anchorID="23" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_25_50" slack="21.037" period="37.037" constraintValue="18.518" deviceLimit="8.000" physResource="ctm_27x162/dcm_sp_inst/CLKIN" logResource="ctm_27x162/dcm_sp_inst/CLKIN" locationPin="DCM_X0Y7.CLKIN" clockNet="ctm_27x162/clkin1"/></twPinLimitRpt></twConst><twConst anchorID="24" twConstType="PERIOD" ><twConstHead uID="6"><twConstName UCFConstName="" ScopeName="">TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;</twConstName><twItemCnt>2935</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1035</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>6.578</twMinPer></twConstHead><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/aux_count_r_2 (SLICE_X11Y18.CE), 4 paths
</twPathRptBanner><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.459</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_2</twDest><twTotPathDel>6.739</twTotPathDel><twClkSkew dest = "0.561" src = "0.365">-0.196</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_2</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X10Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X10Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd4</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D3</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">2.554</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y18.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.647</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y18.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;2&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_2</twBEL></twPathDel><twLogDel>1.427</twLogDel><twRouteDel>5.312</twRouteDel><twTotDel>6.739</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>21.2</twPctLog><twPctRoute>78.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.585</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_2</twDest><twTotPathDel>6.843</twTotPathDel><twClkSkew dest = "1.245" src = "0.819">-0.426</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_2</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X15Y19.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X15Y19.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y17.D3</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">1.266</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y17.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/aux_sync_count10_r</twComp><twBEL>lut29936_6704</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.228</twDelInfo><twComp>lut29936_6704</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y18.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.647</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y18.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;2&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_2</twBEL></twPathDel><twLogDel>1.591</twLogDel><twRouteDel>5.252</twRouteDel><twTotDel>6.843</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>23.3</twPctLog><twPctRoute>76.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="29"><twConstPath anchorID="30" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>31.262</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd3</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_2</twDest><twTotPathDel>5.936</twTotPathDel><twClkSkew dest = "0.561" src = "0.365">-0.196</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd3</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_2</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X10Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X10Y17.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd3</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y17.D5</twSite><twDelType>net</twDelType><twFanCnt>35</twFanCnt><twDelInfo twEdge="twRising">0.264</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y17.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/aux_sync_count10_r</twComp><twBEL>lut29936_6704</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.228</twDelInfo><twComp>lut29936_6704</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y18.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.647</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y18.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;2&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_2</twBEL></twPathDel><twLogDel>1.686</twLogDel><twRouteDel>4.250</twRouteDel><twTotDel>5.936</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>28.4</twPctLog><twPctRoute>71.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/aux_count_r_4 (SLICE_X9Y17.CE), 4 paths
</twPathRptBanner><twPathRpt anchorID="31"><twConstPath anchorID="32" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.466</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_4</twDest><twTotPathDel>6.491</twTotPathDel><twClkSkew dest = "1.042" src = "1.087">0.045</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_4</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X10Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X10Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd4</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D3</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">2.554</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y17.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.417</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y17.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;4&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_4</twBEL></twPathDel><twLogDel>1.409</twLogDel><twRouteDel>5.082</twRouteDel><twTotDel>6.491</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>21.7</twPctLog><twPctRoute>78.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="33"><twConstPath anchorID="34" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.630</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_4</twDest><twTotPathDel>6.595</twTotPathDel><twClkSkew dest = "1.042" src = "0.819">-0.223</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_4</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X15Y19.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X15Y19.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y17.D3</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">1.266</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y17.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/aux_sync_count10_r</twComp><twBEL>lut29936_6704</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.228</twDelInfo><twComp>lut29936_6704</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y17.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.417</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y17.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;4&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_4</twBEL></twPathDel><twLogDel>1.573</twLogDel><twRouteDel>5.022</twRouteDel><twTotDel>6.595</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>23.9</twPctLog><twPctRoute>76.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="35"><twConstPath anchorID="36" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>31.269</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd3</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_4</twDest><twTotPathDel>5.688</twTotPathDel><twClkSkew dest = "1.042" src = "1.087">0.045</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd3</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_4</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X10Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X10Y17.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd3</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y17.D5</twSite><twDelType>net</twDelType><twFanCnt>35</twFanCnt><twDelInfo twEdge="twRising">0.264</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y17.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/aux_sync_count10_r</twComp><twBEL>lut29936_6704</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.228</twDelInfo><twComp>lut29936_6704</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y17.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.417</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y17.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;4&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_4</twBEL></twPathDel><twLogDel>1.668</twLogDel><twRouteDel>4.020</twRouteDel><twTotDel>5.688</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>29.3</twPctLog><twPctRoute>70.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_tx/aux_count_r_1 (SLICE_X11Y18.CE), 4 paths
</twPathRptBanner><twPathRpt anchorID="37"><twConstPath anchorID="38" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.477</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_1</twDest><twTotPathDel>6.721</twTotPathDel><twClkSkew dest = "0.561" src = "0.365">-0.196</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd4</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X10Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X10Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd4</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D3</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">2.554</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd4</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y18.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.647</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y18.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;2&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_1</twBEL></twPathDel><twLogDel>1.409</twLogDel><twRouteDel>5.312</twRouteDel><twTotDel>6.721</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>21.0</twPctLog><twPctRoute>79.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="39"><twConstPath anchorID="40" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>30.603</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_1</twDest><twTotPathDel>6.825</twTotPathDel><twClkSkew dest = "1.245" src = "0.819">-0.426</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_1</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X15Y19.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X15Y19.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y17.D3</twSite><twDelType>net</twDelType><twFanCnt>38</twFanCnt><twDelInfo twEdge="twRising">1.266</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y17.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/aux_sync_count10_r</twComp><twBEL>lut29936_6704</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.228</twDelInfo><twComp>lut29936_6704</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y18.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.647</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y18.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;2&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_1</twBEL></twPathDel><twLogDel>1.573</twLogDel><twRouteDel>5.252</twRouteDel><twTotDel>6.825</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>23.0</twPctLog><twPctRoute>77.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="41"><twConstPath anchorID="42" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>31.280</twSlack><twSrc BELType="FF">dp_main/aux_tx/aux_state_r_FSM_FFd3</twSrc><twDest BELType="FF">dp_main/aux_tx/aux_count_r_1</twDest><twTotPathDel>5.918</twTotPathDel><twClkSkew dest = "0.561" src = "0.365">-0.196</twClkSkew><twDelConst>37.037</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/aux_tx/aux_state_r_FSM_FFd3</twSrc><twDest BELType='FF'>dp_main/aux_tx/aux_count_r_1</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X10Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X10Y17.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp><twBEL>dp_main/aux_tx/aux_state_r_FSM_FFd3</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y17.D5</twSite><twDelType>net</twDelType><twFanCnt>35</twFanCnt><twDelInfo twEdge="twRising">0.264</twDelInfo><twComp>dp_main/aux_tx/aux_state_r_FSM_FFd3</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y17.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/aux_tx/aux_sync_count10_r</twComp><twBEL>lut29936_6704</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y22.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.228</twDelInfo><twComp>lut29936_6704</twComp></twPathDel><twPathDel><twSite>SLICE_X25Y22.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>dp_main/link_aux_tx_ack</twComp><twBEL>lut29937_6705</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y17.A3</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">2.111</twDelInfo><twComp>lut29937_6705</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>][19206_6778</twComp><twBEL>lut30155_6777</twBEL></twPathDel><twPathDel><twSite>SLICE_X11Y18.CE</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.647</twDelInfo><twComp>][19206_6778</twComp></twPathDel><twPathDel><twSite>SLICE_X11Y18.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.390</twDelInfo><twComp>dp_main/aux_tx/aux_count_r&lt;2&gt;</twComp><twBEL>dp_main/aux_tx/aux_count_r_1</twBEL></twPathDel><twLogDel>1.668</twLogDel><twRouteDel>4.250</twRouteDel><twTotDel>5.918</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>28.2</twPctLog><twPctRoute>71.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_linkup/link_main_mode_r_2 (SLICE_X57Y52.A6), 1 path
</twPathRptBanner><twPathRpt anchorID="43"><twConstPath anchorID="44" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.188</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/link_state_r_FSM_FFd5</twSrc><twDest BELType="FF">dp_main/dp_main_linkup/link_main_mode_r_2</twDest><twTotPathDel>2.083</twTotPathDel><twClkSkew dest = "2.679" src = "0.784">-1.895</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/link_state_r_FSM_FFd5</twSrc><twDest BELType='FF'>dp_main/dp_main_linkup/link_main_mode_r_2</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X35Y35.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X35Y35.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>dp_main/dp_main_linkup/link_state_r_FSM_FFd5</twComp><twBEL>dp_main/dp_main_linkup/link_state_r_FSM_FFd5</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y52.A6</twSite><twDelType>net</twDelType><twFanCnt>22</twFanCnt><twDelInfo twEdge="twFalling">1.670</twDelInfo><twComp>dp_main/dp_main_linkup/link_state_r_FSM_FFd5</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X57Y52.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>led_7_OBUF</twComp><twBEL>lut27405_6220</twBEL><twBEL>dp_main/dp_main_linkup/link_main_mode_r_2</twBEL></twPathDel><twLogDel>0.413</twLogDel><twRouteDel>1.670</twRouteDel><twTotDel>2.083</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>19.8</twPctLog><twPctRoute>80.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_linkup/link_main_mode_r_3 (SLICE_X56Y43.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="45"><twConstPath anchorID="46" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.224</twSlack><twSrc BELType="FF">dp_main/dp_main_linkup/link_state_r_FSM_FFd4</twSrc><twDest BELType="FF">dp_main/dp_main_linkup/link_main_mode_r_3</twDest><twTotPathDel>1.726</twTotPathDel><twClkSkew dest = "2.324" src = "0.822">-1.502</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_linkup/link_state_r_FSM_FFd4</twSrc><twDest BELType='FF'>dp_main/dp_main_linkup/link_main_mode_r_3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X32Y37.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X32Y37.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>dp_main/dp_main_linkup/link_state_r_FSM_FFd4</twComp><twBEL>dp_main/dp_main_linkup/link_state_r_FSM_FFd4</twBEL></twPathDel><twPathDel><twSite>SLICE_X56Y43.D6</twSite><twDelType>net</twDelType><twFanCnt>22</twFanCnt><twDelInfo twEdge="twFalling">1.329</twDelInfo><twComp>dp_main/dp_main_linkup/link_state_r_FSM_FFd4</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X56Y43.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.197</twDelInfo><twComp>led_5_OBUF</twComp><twBEL>lut27410_6222</twBEL><twBEL>dp_main/dp_main_linkup/link_main_mode_r_3</twBEL></twPathDel><twLogDel>0.397</twLogDel><twRouteDel>1.329</twRouteDel><twTotDel>1.726</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>23.0</twPctLog><twPctRoute>77.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/aux_rx/aux_cmd_r_1 (SLICE_X41Y15.B6), 1 path
</twPathRptBanner><twPathRpt anchorID="47"><twConstPath anchorID="48" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.291</twSlack><twSrc BELType="FF">dp_main/aux_rx/aux_clk8_r</twSrc><twDest BELType="FF">dp_main/aux_rx/aux_cmd_r_1</twDest><twTotPathDel>0.848</twTotPathDel><twClkSkew dest = "0.704" src = "0.147">-0.557</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/aux_rx/aux_clk8_r</twSrc><twDest BELType='FF'>dp_main/aux_rx/aux_cmd_r_1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X36Y10.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK27</twSrcClk><twPathDel><twSite>SLICE_X36Y10.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>dp_main/aux_rx/aux_clk8_r</twComp><twBEL>dp_main/aux_rx/aux_clk8_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y15.B6</twSite><twDelType>net</twDelType><twFanCnt>29</twFanCnt><twDelInfo twEdge="twFalling">0.433</twDelInfo><twComp>dp_main/aux_rx/aux_clk8_r</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X41Y15.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>dp_main/link_aux_rx_cmd&lt;3&gt;</twComp><twBEL>lut26861_6080</twBEL><twBEL>dp_main/aux_rx/aux_cmd_r_1</twBEL></twPathDel><twLogDel>0.415</twLogDel><twRouteDel>0.433</twRouteDel><twTotDel>0.848</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="37.037">CLK27</twDestClk><twPctLog>48.9</twPctLog><twPctRoute>51.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="49"><twPinLimitBanner>Component Switching Limit Checks: TS_DP_CLK0 = PERIOD TIMEGRP &quot;DP_CLK0&quot; 27 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="50" type="MINPERIOD" name="Tcp" slack="35.638" period="37.037" constraintValue="37.037" deviceLimit="1.399" freqLimit="714.796" physResource="dp_main/dp_main_linkup/hpd_r_5_BRB1/CLK" logResource="dp_main/dp_main_linkup/Mshreg_hpd_r_5_BRB1/CLK" locationPin="SLICE_X44Y49.CLK" clockNet="CLK27"/><twPinLimit anchorID="51" type="MINHIGHPULSE" name="Trpw" slack="36.557" period="37.037" constraintValue="18.518" deviceLimit="0.240" physResource="dp_main/aux_tx/aux_state_r_FSM_FFd3/SR" logResource="dp_main/aux_tx/aux_state_r_FSM_FFd4/SR" locationPin="SLICE_X10Y17.SR" clockNet="][24489_9"/><twPinLimit anchorID="52" type="MINHIGHPULSE" name="Trpw" slack="36.557" period="37.037" constraintValue="18.518" deviceLimit="0.240" physResource="dp_main/aux_tx/aux_state_r_FSM_FFd3/SR" logResource="dp_main/aux_tx/aux_state_r_FSM_FFd3/SR" locationPin="SLICE_X10Y17.SR" clockNet="][24489_9"/></twPinLimitRpt></twConst><twConst anchorID="53" twConstType="PERIOD" ><twConstHead uID="7"><twConstName UCFConstName="" ScopeName="">TS_SYS_CLK3 = PERIOD TIMEGRP &quot;SYS_CLK3&quot; 5 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.800</twMinPer></twConstHead><twPinLimitRpt anchorID="54"><twPinLimitBanner>Component Switching Limit Checks: TS_SYS_CLK3 = PERIOD TIMEGRP &quot;SYS_CLK3&quot; 5 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="55" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="1.549" period="2.500" constraintValue="2.500" deviceLimit="0.951" freqLimit="1051.525" physResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT0" logResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT0" locationPin="PLL_ADV_X0Y0.CLKOUT0" clockNet="memc3_infrastructure_inst/clk_2x_0"/><twPinLimit anchorID="56" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="1.549" period="2.500" constraintValue="2.500" deviceLimit="0.951" freqLimit="1051.525" physResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT1" logResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT1" locationPin="PLL_ADV_X0Y0.CLKOUT1" clockNet="memc3_infrastructure_inst/clk_2x_180"/><twPinLimit anchorID="57" type="MINLOWPULSE" name="Tdcmpw_CLKIN_200_250" slack="2.200" period="5.000" constraintValue="2.500" deviceLimit="1.400" physResource="memc3_infrastructure_inst/u_pll_adv/CLKIN1" logResource="memc3_infrastructure_inst/u_pll_adv/CLKIN1" locationPin="PLL_ADV_X0Y0.CLKIN2" clockNet="CLK200"/></twPinLimitRpt></twConst><twConst anchorID="58" twConstType="PERIOD" ><twConstHead uID="8"><twConstName UCFConstName="" ScopeName="">TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIMEGRP &quot;clk_wiz_v1_6_50x200_clkfx&quot;         TS_xtalclk / 4 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.800</twMinPer></twConstHead><twPinLimitRpt anchorID="59"><twPinLimitBanner>Component Switching Limit Checks: TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIMEGRP &quot;clk_wiz_v1_6_50x200_clkfx&quot;
        TS_xtalclk / 4 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="60" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="1.549" period="2.500" constraintValue="2.500" deviceLimit="0.951" freqLimit="1051.525" physResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT0" logResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT0" locationPin="PLL_ADV_X0Y0.CLKOUT0" clockNet="memc3_infrastructure_inst/clk_2x_0"/><twPinLimit anchorID="61" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="1.549" period="2.500" constraintValue="2.500" deviceLimit="0.951" freqLimit="1051.525" physResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT1" logResource="memc3_infrastructure_inst/u_pll_adv/CLKOUT1" locationPin="PLL_ADV_X0Y0.CLKOUT1" clockNet="memc3_infrastructure_inst/clk_2x_180"/><twPinLimit anchorID="62" type="MINLOWPULSE" name="Tdcmpw_CLKIN_200_250" slack="2.200" period="5.000" constraintValue="2.500" deviceLimit="1.400" physResource="memc3_infrastructure_inst/u_pll_adv/CLKIN1" logResource="memc3_infrastructure_inst/u_pll_adv/CLKIN1" locationPin="PLL_ADV_X0Y0.CLKIN2" clockNet="CLK200"/></twPinLimitRpt></twConst><twConst anchorID="63" twConstType="PERIOD" ><twConstHead uID="9"><twConstName UCFConstName="" ScopeName="">TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk / 6.25 HIGH 50%;</twConstName><twItemCnt>133</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>133</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.708</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/DDR_tx2_p (OLOGIC_X24Y1.D2), 1 path
</twPathRptBanner><twPathRpt anchorID="64"><twConstPath anchorID="65" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.246</twSlack><twSrc BELType="FF">tx_dvi/tx2_out_r_0</twSrc><twDest BELType="FF">tx_dvi/DDR_tx2_p</twDest><twTotPathDel>1.646</twTotPathDel><twClkSkew dest = "0.580" src = "0.174">-0.406</twClkSkew><twDelConst>1.600</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.217" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.114</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/tx2_out_r_0</twSrc><twDest BELType='FF'>tx_dvi/DDR_tx2_p</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X54Y2.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63x5</twSrcClk><twPathDel><twSite>SLICE_X54Y2.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/tx2_out_r&lt;0&gt;</twComp><twBEL>tx_dvi/tx2_out_r_0</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X24Y1.D2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.506</twDelInfo><twComp>tx_dvi/tx2_out_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X24Y1.CLK1</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.664</twDelInfo><twComp>tx_dvi/tx_ch2_ddr</twComp><twBEL>tx_dvi/DDR_tx2_p</twBEL></twPathDel><twLogDel>1.140</twLogDel><twRouteDel>0.506</twRouteDel><twTotDel>1.646</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="1.600">CLK63x5</twDestClk><twPctLog>69.3</twPctLog><twPctRoute>30.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/DDR_tx0_p (OLOGIC_X25Y3.D2), 1 path
</twPathRptBanner><twPathRpt anchorID="66"><twConstPath anchorID="67" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.351</twSlack><twSrc BELType="FF">tx_dvi/tx0_out_r_0</twSrc><twDest BELType="FF">tx_dvi/DDR_tx0_p</twDest><twTotPathDel>1.542</twTotPathDel><twClkSkew dest = "0.579" src = "0.172">-0.407</twClkSkew><twDelConst>1.600</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.217" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.114</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/tx0_out_r_0</twSrc><twDest BELType='FF'>tx_dvi/DDR_tx0_p</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X56Y3.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63x5</twSrcClk><twPathDel><twSite>SLICE_X56Y3.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.525</twDelInfo><twComp>tx_dvi/tx0_out_r&lt;0&gt;</twComp><twBEL>tx_dvi/tx0_out_r_0</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X25Y3.D2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.353</twDelInfo><twComp>tx_dvi/tx0_out_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X25Y3.CLK1</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.664</twDelInfo><twComp>tx_dvi/tx_ch0_ddr</twComp><twBEL>tx_dvi/DDR_tx0_p</twBEL></twPathDel><twLogDel>1.189</twLogDel><twRouteDel>0.353</twRouteDel><twTotDel>1.542</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="1.600">CLK63x5</twDestClk><twPctLog>77.1</twPctLog><twPctRoute>22.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/DDR_tx1_p (OLOGIC_X26Y3.D2), 1 path
</twPathRptBanner><twPathRpt anchorID="68"><twConstPath anchorID="69" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.475</twSlack><twSrc BELType="FF">tx_dvi/tx1_out_r_0</twSrc><twDest BELType="FF">tx_dvi/DDR_tx1_p</twDest><twTotPathDel>1.416</twTotPathDel><twClkSkew dest = "0.579" src = "0.174">-0.405</twClkSkew><twDelConst>1.600</twDelConst><tw2Phase></tw2Phase><twClkUncert fSysJit="0.070" fDCMJit="0.217" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.114</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/tx1_out_r_0</twSrc><twDest BELType='FF'>tx_dvi/DDR_tx1_p</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X59Y2.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63x5</twSrcClk><twPathDel><twSite>SLICE_X59Y2.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/tx1_out_r&lt;0&gt;</twComp><twBEL>tx_dvi/tx1_out_r_0</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X26Y3.D2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.322</twDelInfo><twComp>tx_dvi/tx1_out_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X26Y3.CLK1</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.664</twDelInfo><twComp>tx_dvi/tx_ch1_ddr</twComp><twBEL>tx_dvi/DDR_tx1_p</twBEL></twPathDel><twLogDel>1.094</twLogDel><twRouteDel>0.322</twRouteDel><twTotDel>1.416</twTotDel><twDestClk twEdge ="twFalling" twArriveTime ="1.600">CLK63x5</twDestClk><twPctLog>77.3</twPctLog><twPctRoute>22.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk / 6.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx1_r_8_BRB1 (SLICE_X46Y13.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="70"><twConstPath anchorID="71" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.161</twSlack><twSrc BELType="FF">tx_dvi/ch1_enc_r_8</twSrc><twDest BELType="FF">tx_dvi/tx1_r_8_BRB1</twDest><twTotPathDel>0.483</twTotPathDel><twClkSkew dest = "1.142" src = "1.088">-0.054</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch1_enc_r_8</twSrc><twDest BELType='FF'>tx_dvi/tx1_r_8_BRB1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X45Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X45Y14.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/ch1_enc_r&lt;9&gt;</twComp><twBEL>tx_dvi/ch1_enc_r_8</twBEL></twPathDel><twPathDel><twSite>SLICE_X46Y13.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.237</twDelInfo><twComp>tx_dvi/ch1_enc_r&lt;8&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X46Y13.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>tx_dvi/tx1_r_8_BRB1</twComp><twBEL>tx_dvi/tx1_r_8_BRB1</twBEL></twPathDel><twLogDel>0.246</twLogDel><twRouteDel>0.237</twRouteDel><twTotDel>0.483</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLK63x5</twDestClk><twPctLog>50.9</twPctLog><twPctRoute>49.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx2_r_4_BRB2 (SLICE_X41Y8.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="72"><twConstPath anchorID="73" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.211</twSlack><twSrc BELType="FF">tx_dvi/ch2_enc_r_4</twSrc><twDest BELType="FF">tx_dvi/tx2_r_4_BRB2</twDest><twTotPathDel>0.534</twTotPathDel><twClkSkew dest = "1.133" src = "1.078">-0.055</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch2_enc_r_4</twSrc><twDest BELType='FF'>tx_dvi/tx2_r_4_BRB2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X39Y8.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X39Y8.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;7&gt;</twComp><twBEL>tx_dvi/ch2_enc_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y8.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.277</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;4&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X41Y8.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/tx2_r_5_BRB2</twComp><twBEL>tx_dvi/tx2_r_4_BRB2</twBEL></twPathDel><twLogDel>0.257</twLogDel><twRouteDel>0.277</twRouteDel><twTotDel>0.534</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLK63x5</twDestClk><twPctLog>48.1</twPctLog><twPctRoute>51.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/tx1_r_2_BRB2 (SLICE_X51Y15.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="74"><twConstPath anchorID="75" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.227</twSlack><twSrc BELType="FF">tx_dvi/ch1_enc_r_2</twSrc><twDest BELType="FF">tx_dvi/tx1_r_2_BRB2</twDest><twTotPathDel>0.582</twTotPathDel><twClkSkew dest = "1.144" src = "1.057">-0.087</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.268</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/ch1_enc_r_2</twSrc><twDest BELType='FF'>tx_dvi/tx1_r_2_BRB2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X50Y19.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X50Y19.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>tx_dvi/ch1_enc_r&lt;3&gt;</twComp><twBEL>tx_dvi/ch1_enc_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X51Y15.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.323</twDelInfo><twComp>tx_dvi/ch1_enc_r&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X51Y15.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/tx1_r_2_BRB2</twComp><twBEL>tx_dvi/tx1_r_2_BRB2</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.323</twRouteDel><twTotDel>0.582</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.200">CLK63x5</twDestClk><twPctLog>44.5</twPctLog><twPctRoute>55.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="76"><twPinLimitBanner>Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk / 6.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="77" type="MINPERIOD" name="Tbcper_I" slack="0.930" period="3.200" constraintValue="3.200" deviceLimit="2.270" freqLimit="440.529" physResource="clk_wiz_v1_6_50x62x312/clkout2_buf/I0" logResource="clk_wiz_v1_6_50x62x312/clkout2_buf/I0" locationPin="BUFGMUX_X3Y16.I0" clockNet="clk_wiz_v1_6_50x62x312/clkout1"/><twPinLimit anchorID="78" type="MINPERIOD" name="Tockper" slack="1.444" period="3.200" constraintValue="3.200" deviceLimit="1.756" freqLimit="569.476" physResource="tx_dvi/tx_ch0_ddr/CLK0" logResource="tx_dvi/DDR_tx0_p/CK0" locationPin="OLOGIC_X25Y3.CLK0" clockNet="CLK63x5"/><twPinLimit anchorID="79" type="MINPERIOD" name="Tockper" slack="1.444" period="3.200" constraintValue="3.200" deviceLimit="1.756" freqLimit="569.476" physResource="tx_dvi/tx_ch1_ddr/CLK0" logResource="tx_dvi/DDR_tx1_p/CK0" locationPin="OLOGIC_X26Y3.CLK0" clockNet="CLK63x5"/></twPinLimitRpt></twConst><twConst anchorID="80" twConstType="PERIOD" ><twConstHead uID="10"><twConstName UCFConstName="" ScopeName="">TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk / 1.25 HIGH 50%;</twConstName><twItemCnt>21736</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1228</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>9.891</twMinPer></twConstHead><twPathRptBanner iPaths="55" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc0/st1_qm_r_2 (SLICE_X38Y7.C2), 55 paths
</twPathRptBanner><twPathRpt anchorID="81"><twConstPath anchorID="82" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.109</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_6</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_2</twDest><twTotPathDel>9.685</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_6</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_2</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X12Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X12Y14.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.216</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.C2</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.261</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12418_2033</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_2</twBEL></twPathDel><twLogDel>1.827</twLogDel><twRouteDel>7.858</twRouteDel><twTotDel>9.685</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>18.9</twPctLog><twPctRoute>81.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="83"><twConstPath anchorID="84" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.772</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_4</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_2</twDest><twTotPathDel>9.022</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_4</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_2</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X12Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X12Y14.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.553</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.C2</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.261</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12418_2033</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_2</twBEL></twPathDel><twLogDel>1.827</twLogDel><twRouteDel>7.195</twRouteDel><twTotDel>9.022</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>20.3</twPctLog><twPctRoute>79.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="85"><twConstPath anchorID="86" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.804</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_7</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_2</twDest><twTotPathDel>8.990</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_7</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_2</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X13Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X13Y14.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;9&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.567</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.C2</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.261</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12418_2033</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_2</twBEL></twPathDel><twLogDel>1.781</twLogDel><twRouteDel>7.209</twRouteDel><twTotDel>8.990</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>19.8</twPctLog><twPctRoute>80.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="55" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc0/st1_qm_r_1 (SLICE_X38Y7.B3), 55 paths
</twPathRptBanner><twPathRpt anchorID="87"><twConstPath anchorID="88" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.201</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_6</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_1</twDest><twTotPathDel>9.593</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_6</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_1</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X12Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X12Y14.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.216</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.B3</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.169</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12409_2031</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_1</twBEL></twPathDel><twLogDel>1.827</twLogDel><twRouteDel>7.766</twRouteDel><twTotDel>9.593</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>19.0</twPctLog><twPctRoute>81.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="89"><twConstPath anchorID="90" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.864</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_4</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_1</twDest><twTotPathDel>8.930</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_4</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_1</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X12Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X12Y14.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.553</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.B3</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.169</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12409_2031</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_1</twBEL></twPathDel><twLogDel>1.827</twLogDel><twRouteDel>7.103</twRouteDel><twTotDel>8.930</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>20.5</twPctLog><twPctRoute>79.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="91"><twConstPath anchorID="92" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.896</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_7</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_1</twDest><twTotPathDel>8.898</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_7</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_1</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X13Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X13Y14.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;9&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.567</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.B3</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.169</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12409_2031</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_1</twBEL></twPathDel><twLogDel>1.781</twLogDel><twRouteDel>7.117</twRouteDel><twTotDel>8.898</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>20.0</twPctLog><twPctRoute>80.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="55" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/enc0/st1_qm_r_3 (SLICE_X38Y7.D1), 55 paths
</twPathRptBanner><twPathRpt anchorID="93"><twConstPath anchorID="94" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.227</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_6</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_3</twDest><twTotPathDel>9.567</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_6</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_3</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X12Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X12Y14.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.216</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.D1</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.143</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12427_2035</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_3</twBEL></twPathDel><twLogDel>1.827</twLogDel><twRouteDel>7.740</twRouteDel><twTotDel>9.567</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>19.1</twPctLog><twPctRoute>80.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="95"><twConstPath anchorID="96" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.890</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_4</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_3</twDest><twTotPathDel>8.904</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_4</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_3</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X12Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X12Y14.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;6&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B3</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.553</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.D1</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.143</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12427_2035</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_3</twBEL></twPathDel><twLogDel>1.827</twLogDel><twRouteDel>7.077</twRouteDel><twTotDel>8.904</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>20.5</twPctLog><twPctRoute>79.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="97"><twConstPath anchorID="98" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.922</twSlack><twSrc BELType="FF">tx_dvi/enc0/st0_qm_r_7</twSrc><twDest BELType="FF">tx_dvi/enc0/st1_qm_r_3</twDest><twTotPathDel>8.872</twTotPathDel><twClkSkew dest = "0.511" src = "0.569">0.058</twClkSkew><twDelConst>16.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.287" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.148</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>tx_dvi/enc0/st0_qm_r_7</twSrc><twDest BELType='FF'>tx_dvi/enc0/st1_qm_r_3</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X13Y14.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X13Y14.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;9&gt;</twComp><twBEL>tx_dvi/enc0/st0_qm_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y9.B5</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.567</twDelInfo><twComp>tx_dvi/enc0/st0_qm_r&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X7Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut12383_482</twComp><twBEL>lut12374_481</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.A1</twSite><twDelType>net</twDelType><twFanCnt>18</twFanCnt><twDelInfo twEdge="twRising">1.086</twDelInfo><twComp>lut12374_481</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12377_492</twBEL></twPathDel><twPathDel><twSite>SLICE_X9Y10.C2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.527</twDelInfo><twComp>lut12377_492</twComp></twPathDel><twPathDel><twSite>SLICE_X9Y10.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>tx_dvi/enc0/N63</twComp><twBEL>lut12381_536</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y9.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">0.768</twDelInfo><twComp>lut12381_536</twComp></twPathDel><twPathDel><twSite>SLICE_X8Y9.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>tx_dvi/enc0/st1_cnt_r&lt;1&gt;</twComp><twBEL>tx_dvi/enc0/st1_case_cnt_eq</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y7.D1</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.143</twDelInfo><twComp>tx_dvi/enc0/st1_case_cnt_eq</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y7.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>tx_dvi/ch0_enc&lt;3&gt;</twComp><twBEL>lut12427_2035</twBEL><twBEL>tx_dvi/enc0/st1_qm_r_3</twBEL></twPathDel><twLogDel>1.781</twLogDel><twRouteDel>7.091</twRouteDel><twTotDel>8.872</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>20.1</twPctLog><twPctRoute>79.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk / 1.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/ch2_enc_r_0 (SLICE_X41Y5.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="99"><twConstPath anchorID="100" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.398</twSlack><twSrc BELType="FF">tx_dvi/enc2/st1_qm_r_0</twSrc><twDest BELType="FF">tx_dvi/ch2_enc_r_0</twDest><twTotPathDel>0.400</twTotPathDel><twClkSkew dest = "0.036" src = "0.034">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/enc2/st1_qm_r_0</twSrc><twDest BELType='FF'>tx_dvi/ch2_enc_r_0</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X40Y5.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X40Y5.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>tx_dvi/ch2_enc&lt;3&gt;</twComp><twBEL>tx_dvi/enc2/st1_qm_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y5.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.141</twDelInfo><twComp>tx_dvi/ch2_enc&lt;0&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X41Y5.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;3&gt;</twComp><twBEL>tx_dvi/ch2_enc_r_0</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.141</twRouteDel><twTotDel>0.400</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>64.8</twPctLog><twPctRoute>35.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/ch2_enc_r_2 (SLICE_X41Y5.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="101"><twConstPath anchorID="102" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.401</twSlack><twSrc BELType="FF">tx_dvi/enc2/st1_qm_r_2</twSrc><twDest BELType="FF">tx_dvi/ch2_enc_r_2</twDest><twTotPathDel>0.403</twTotPathDel><twClkSkew dest = "0.036" src = "0.034">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/enc2/st1_qm_r_2</twSrc><twDest BELType='FF'>tx_dvi/ch2_enc_r_2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X40Y5.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X40Y5.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>tx_dvi/ch2_enc&lt;3&gt;</twComp><twBEL>tx_dvi/enc2/st1_qm_r_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X41Y5.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.144</twDelInfo><twComp>tx_dvi/ch2_enc&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X41Y5.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>tx_dvi/ch2_enc_r&lt;3&gt;</twComp><twBEL>tx_dvi/ch2_enc_r_2</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.144</twRouteDel><twTotDel>0.403</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>64.3</twPctLog><twPctRoute>35.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point tx_dvi/ch1_enc_r_6 (SLICE_X48Y20.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="103"><twConstPath anchorID="104" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.403</twSlack><twSrc BELType="FF">tx_dvi/enc1/st1_qm_r_6</twSrc><twDest BELType="FF">tx_dvi/ch1_enc_r_6</twDest><twTotPathDel>0.405</twTotPathDel><twClkSkew dest = "0.038" src = "0.036">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>tx_dvi/enc1/st1_qm_r_6</twSrc><twDest BELType='FF'>tx_dvi/ch1_enc_r_6</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X49Y20.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X49Y20.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>tx_dvi/ch1_enc&lt;7&gt;</twComp><twBEL>tx_dvi/enc1/st1_qm_r_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y20.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.166</twDelInfo><twComp>tx_dvi/ch1_enc&lt;6&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X48Y20.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.041</twDelInfo><twComp>tx_dvi/ch1_enc_r&lt;7&gt;</twComp><twBEL>tx_dvi/ch1_enc_r_6</twBEL></twPathDel><twLogDel>0.239</twLogDel><twRouteDel>0.166</twRouteDel><twTotDel>0.405</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="16.000">CLK63</twDestClk><twPctLog>59.0</twPctLog><twPctRoute>41.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="105"><twPinLimitBanner>Component Switching Limit Checks: TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP
        &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk / 1.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="106" type="MINPERIOD" name="Trper_CLKB(Fmax)" slack="12.430" period="16.000" constraintValue="16.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" locationPin="RAMB16_X0Y22.CLKB" clockNet="CLK63"/><twPinLimit anchorID="107" type="MINPERIOD" name="Trper_CLKB(Fmax)" slack="12.430" period="16.000" constraintValue="16.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" locationPin="RAMB16_X0Y24.CLKB" clockNet="CLK63"/><twPinLimit anchorID="108" type="MINPERIOD" name="Tbcper_I" slack="13.730" period="16.000" constraintValue="16.000" deviceLimit="2.270" freqLimit="440.529" physResource="clk_wiz_v1_6_50x62x312/clkout1_buf/I0" logResource="clk_wiz_v1_6_50x62x312/clkout1_buf/I0" locationPin="BUFGMUX_X3Y5.I0" clockNet="clk_wiz_v1_6_50x62x312/clkout0"/></twPinLimitRpt></twConst><twConst anchorID="109" twConstType="PERIOD" ><twConstHead uID="11"><twConstName UCFConstName="" ScopeName="">TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCM&quot; TS_GTPCLKOUT1_0_ HIGH 50%;</twConstName><twItemCnt>12509</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>1</twErrCntPinLimit><twEndPtCnt>6684</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>6.400</twMinPer></twConstHead><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/tbc_data00_r_66 (SLICE_X48Y98.B3), 2 paths
</twPathRptBanner><twPathRpt anchorID="110"><twConstPath anchorID="111" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.048</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_data_sel_r_0</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_data00_r_66</twDest><twTotPathDel>5.427</twTotPathDel><twClkSkew dest = "0.492" src = "0.537">0.045</twClkSkew><twDelConst>5.555</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_data_sel_r_0</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_data00_r_66</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X49Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X49Y69.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_data_sel_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y70.C6</twSite><twDelType>net</twDelType><twFanCnt>56</twFanCnt><twDelInfo twEdge="twRising">0.555</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y70.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;27&gt;</twComp><twBEL>lut17899_3086</twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y98.B3</twSite><twDelType>net</twDelType><twFanCnt>207</twFanCnt><twDelInfo twEdge="twRising">3.868</twDelInfo><twComp>lut17899_3086</twComp></twPathDel><twPathDel><twSite>SLICE_X48Y98.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;68&gt;</twComp><twBEL>lut18174_3147</twBEL><twBEL>dp_main/dp_main_tbc/tbc_data00_r_66</twBEL></twPathDel><twLogDel>1.004</twLogDel><twRouteDel>4.423</twRouteDel><twTotDel>5.427</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>18.5</twPctLog><twPctRoute>81.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="112"><twConstPath anchorID="113" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.115</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_data_sel_r_1</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_data00_r_66</twDest><twTotPathDel>5.360</twTotPathDel><twClkSkew dest = "0.492" src = "0.537">0.045</twClkSkew><twDelConst>5.555</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_data_sel_r_1</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_data00_r_66</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X49Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X49Y69.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_data_sel_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y70.C5</twSite><twDelType>net</twDelType><twFanCnt>54</twFanCnt><twDelInfo twEdge="twRising">0.488</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y70.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;27&gt;</twComp><twBEL>lut17899_3086</twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y98.B3</twSite><twDelType>net</twDelType><twFanCnt>207</twFanCnt><twDelInfo twEdge="twRising">3.868</twDelInfo><twComp>lut17899_3086</twComp></twPathDel><twPathDel><twSite>SLICE_X48Y98.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;68&gt;</twComp><twBEL>lut18174_3147</twBEL><twBEL>dp_main/dp_main_tbc/tbc_data00_r_66</twBEL></twPathDel><twLogDel>1.004</twLogDel><twRouteDel>4.356</twRouteDel><twTotDel>5.360</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>18.7</twPctLog><twPctRoute>81.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/tbc_data00_r_56 (SLICE_X52Y97.A4), 2 paths
</twPathRptBanner><twPathRpt anchorID="114"><twConstPath anchorID="115" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.068</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_data_sel_r_0</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_data00_r_56</twDest><twTotPathDel>5.409</twTotPathDel><twClkSkew dest = "0.494" src = "0.537">0.043</twClkSkew><twDelConst>5.555</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_data_sel_r_0</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_data00_r_56</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X49Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X49Y69.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_data_sel_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y70.C6</twSite><twDelType>net</twDelType><twFanCnt>56</twFanCnt><twDelInfo twEdge="twRising">0.555</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y70.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;27&gt;</twComp><twBEL>lut17899_3086</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y97.A4</twSite><twDelType>net</twDelType><twFanCnt>207</twFanCnt><twDelInfo twEdge="twRising">3.850</twDelInfo><twComp>lut17899_3086</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y97.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;59&gt;</twComp><twBEL>lut18093_3129</twBEL><twBEL>dp_main/dp_main_tbc/tbc_data00_r_56</twBEL></twPathDel><twLogDel>1.004</twLogDel><twRouteDel>4.405</twRouteDel><twTotDel>5.409</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>18.6</twPctLog><twPctRoute>81.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="116"><twConstPath anchorID="117" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.135</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_data_sel_r_1</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_data00_r_56</twDest><twTotPathDel>5.342</twTotPathDel><twClkSkew dest = "0.494" src = "0.537">0.043</twClkSkew><twDelConst>5.555</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_data_sel_r_1</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_data00_r_56</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X49Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X49Y69.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_data_sel_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y70.C5</twSite><twDelType>net</twDelType><twFanCnt>54</twFanCnt><twDelInfo twEdge="twRising">0.488</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y70.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;27&gt;</twComp><twBEL>lut17899_3086</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y97.A4</twSite><twDelType>net</twDelType><twFanCnt>207</twFanCnt><twDelInfo twEdge="twRising">3.850</twDelInfo><twComp>lut17899_3086</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y97.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;59&gt;</twComp><twBEL>lut18093_3129</twBEL><twBEL>dp_main/dp_main_tbc/tbc_data00_r_56</twBEL></twPathDel><twLogDel>1.004</twLogDel><twRouteDel>4.338</twRouteDel><twTotDel>5.342</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>18.8</twPctLog><twPctRoute>81.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/tbc_data00_r_57 (SLICE_X52Y97.B4), 2 paths
</twPathRptBanner><twPathRpt anchorID="118"><twConstPath anchorID="119" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.068</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_data_sel_r_0</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_data00_r_57</twDest><twTotPathDel>5.409</twTotPathDel><twClkSkew dest = "0.494" src = "0.537">0.043</twClkSkew><twDelConst>5.555</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_data_sel_r_0</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_data00_r_57</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X49Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X49Y69.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_data_sel_r_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y70.C6</twSite><twDelType>net</twDelType><twFanCnt>56</twFanCnt><twDelInfo twEdge="twRising">0.555</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y70.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;27&gt;</twComp><twBEL>lut17899_3086</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y97.B4</twSite><twDelType>net</twDelType><twFanCnt>207</twFanCnt><twDelInfo twEdge="twRising">3.850</twDelInfo><twComp>lut17899_3086</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y97.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;59&gt;</twComp><twBEL>lut18102_3131</twBEL><twBEL>dp_main/dp_main_tbc/tbc_data00_r_57</twBEL></twPathDel><twLogDel>1.004</twLogDel><twRouteDel>4.405</twRouteDel><twTotDel>5.409</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>18.6</twPctLog><twPctRoute>81.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="120"><twConstPath anchorID="121" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.135</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tbc_data_sel_r_1</twSrc><twDest BELType="FF">dp_main/dp_main_tbc/tbc_data00_r_57</twDest><twTotPathDel>5.342</twTotPathDel><twClkSkew dest = "0.494" src = "0.537">0.043</twClkSkew><twDelConst>5.555</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tbc_data_sel_r_1</twSrc><twDest BELType='FF'>dp_main/dp_main_tbc/tbc_data00_r_57</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X49Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X49Y69.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp><twBEL>dp_main/dp_main_tbc/tbc_data_sel_r_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y70.C5</twSite><twDelType>net</twDelType><twFanCnt>54</twFanCnt><twDelInfo twEdge="twRising">0.488</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data_sel_r&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X50Y70.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;27&gt;</twComp><twBEL>lut17899_3086</twBEL></twPathDel><twPathDel><twSite>SLICE_X52Y97.B4</twSite><twDelType>net</twDelType><twFanCnt>207</twFanCnt><twDelInfo twEdge="twRising">3.850</twDelInfo><twComp>lut17899_3086</twComp></twPathDel><twPathDel><twSite>SLICE_X52Y97.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.339</twDelInfo><twComp>dp_main/dp_main_tbc/tbc_data00_r&lt;59&gt;</twComp><twBEL>lut18102_3131</twBEL><twBEL>dp_main/dp_main_tbc/tbc_data00_r_57</twBEL></twPathDel><twLogDel>1.004</twLogDel><twRouteDel>4.338</twRouteDel><twTotDel>5.342</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>18.8</twPctLog><twPctRoute>81.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCM&quot; TS_GTPCLKOUT1_0_ HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y32.DIPA2), 1 path
</twPathRptBanner><twPathRpt anchorID="122"><twConstPath anchorID="123" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.269</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tx_data01_in_r_2</twSrc><twDest BELType="RAM">dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twTotPathDel>0.272</twTotPathDel><twClkSkew dest = "0.078" src = "0.075">-0.003</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tx_data01_in_r_2</twSrc><twDest BELType='RAM'>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X40Y66.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X40Y66.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data01_in_r&lt;3&gt;</twComp><twBEL>dp_main/dp_main_tbc/tx_data01_in_r_2</twBEL></twPathDel><twPathDel><twSite>RAMB16_X2Y32.DIPA2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.125</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data01_in_r&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X2Y32.CLKA</twSite><twDelType>Trckd_DIPA</twDelType><twDelInfo twEdge="twFalling">-0.053</twDelInfo><twComp>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twComp><twBEL>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twLogDel>0.147</twLogDel><twRouteDel>0.125</twRouteDel><twTotDel>0.272</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>54.0</twPctLog><twPctRoute>46.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y32.DIA6), 1 path
</twPathRptBanner><twPathRpt anchorID="124"><twConstPath anchorID="125" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.271</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tx_data00_in_r_6</twSrc><twDest BELType="RAM">dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twTotPathDel>0.272</twTotPathDel><twClkSkew dest = "0.078" src = "0.077">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tx_data00_in_r_6</twSrc><twDest BELType='RAM'>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X40Y64.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X40Y64.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data00_in_r&lt;7&gt;</twComp><twBEL>dp_main/dp_main_tbc/tx_data00_in_r_6</twBEL></twPathDel><twPathDel><twSite>RAMB16_X2Y32.DIA6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.125</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data00_in_r&lt;6&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X2Y32.CLKA</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.053</twDelInfo><twComp>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twComp><twBEL>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twLogDel>0.147</twLogDel><twRouteDel>0.125</twRouteDel><twTotDel>0.272</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>54.0</twPctLog><twPctRoute>46.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y32.DIA18), 1 path
</twPathRptBanner><twPathRpt anchorID="126"><twConstPath anchorID="127" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.296</twSlack><twSrc BELType="FF">dp_main/dp_main_tbc/tx_data00_in_r_20</twSrc><twDest BELType="RAM">dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twTotPathDel>0.298</twTotPathDel><twClkSkew dest = "0.078" src = "0.076">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>dp_main/dp_main_tbc/tx_data00_in_r_20</twSrc><twDest BELType='RAM'>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X40Y65.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">GTPCLKOUT1_DCMx1</twSrcClk><twPathDel><twSite>SLICE_X40Y65.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data00_in_r&lt;23&gt;</twComp><twBEL>dp_main/dp_main_tbc/tx_data00_in_r_20</twBEL></twPathDel><twPathDel><twSite>RAMB16_X2Y32.DIA18</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.151</twDelInfo><twComp>dp_main/dp_main_tbc/tx_data00_in_r&lt;20&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X2Y32.CLKA</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.053</twDelInfo><twComp>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twComp><twBEL>dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram</twBEL></twPathDel><twLogDel>0.147</twLogDel><twRouteDel>0.151</twRouteDel><twTotDel>0.298</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.555">GTPCLKOUT1_DCMx1</twDestClk><twPctLog>49.3</twPctLog><twPctRoute>50.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="128"><twPinLimitBanner>Component Switching Limit Checks: TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCM&quot; TS_GTPCLKOUT1_0_ HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="129" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="-0.845" period="5.555" constraintValue="5.555" deviceLimit="6.400" freqLimit="156.250" physResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21" logResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/TXUSRCLK21" locationPin="GTPA1_DUAL_X1Y0.TXUSRCLK21" clockNet="GTPCLKOUT1_DCMx1"/><twPinLimit anchorID="130" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.985" period="5.555" constraintValue="5.555" deviceLimit="3.570" freqLimit="280.112" physResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X3Y36.CLKA" clockNet="GTPCLKOUT1_DCMx1"/><twPinLimit anchorID="131" type="MINPERIOD" name="Trper_CLKB(Fmax)" slack="1.985" period="5.555" constraintValue="5.555" deviceLimit="3.570" freqLimit="280.112" physResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" logResource="dp_main/dp_main_tbc/ram00_dp108x256/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB" locationPin="RAMB16_X3Y36.CLKB" clockNet="GTPCLKOUT1_DCMx1"/></twPinLimitRpt></twConst><twConst anchorID="132" twConstType="PERIOD" ><twConstHead uID="12"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_gt_refclk_buf = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_gt_refclk_buf&quot;         TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.334</twMinPer></twConstHead><twPinLimitRpt anchorID="133"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_gt_refclk_buf = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_gt_refclk_buf&quot;
        TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="134" type="MINPERIOD" name="Tpllper_CLKOUT(Foutmax)" slack="2.249" period="3.200" constraintValue="3.200" deviceLimit="0.951" freqLimit="1051.525" physResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKOUT0" logResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKOUT0" locationPin="PLL_ADV_X0Y2.CLKOUT0" clockNet="inst_sp6wrap/eptest_i/clk_250"/><twPinLimit anchorID="135" type="MINLOWPULSE" name="Tdcmpw_CLKIN_100_150" slack="4.666" period="8.000" constraintValue="4.000" deviceLimit="1.667" physResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1" logResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y2.CLKIN1" clockNet="inst_sp6wrap/eptest_i/gt_refclk_buf"/><twPinLimit anchorID="136" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_100_150" slack="4.666" period="8.000" constraintValue="4.000" deviceLimit="1.667" physResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1" logResource="inst_sp6wrap/eptest_i/pll_base_i/PLL_ADV/CLKIN1" locationPin="PLL_ADV_X0Y2.CLKIN1" clockNet="inst_sp6wrap/eptest_i/gt_refclk_buf"/></twPinLimitRpt></twConst><twConst anchorID="137" twConstType="PERIOD" ><twConstHead uID="13"><twConstName UCFConstName="" ScopeName="">TS_ctm_27x162_clkfx = PERIOD TIMEGRP &quot;ctm_27x162_clkfx&quot; TS_DP_CLK1 * 6 HIGH         50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.200</twMinPer></twConstHead><twPinLimitRpt anchorID="138"><twPinLimitBanner>Component Switching Limit Checks: TS_ctm_27x162_clkfx = PERIOD TIMEGRP &quot;ctm_27x162_clkfx&quot; TS_DP_CLK1 * 6 HIGH
        50%;</twPinLimitBanner><twPinLimit anchorID="139" type="MINPERIOD" name="Tgtpcper_GCLK" slack="2.972" period="6.172" constraintValue="6.172" deviceLimit="3.200" freqLimit="312.500" physResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01" logResource="xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i/GCLK01" locationPin="GTPA1_DUAL_X1Y0.GCLK01" clockNet="PLL162"/><twPinLimit anchorID="140" type="MINPERIOD" name="Tbcper_I" slack="3.902" period="6.172" constraintValue="6.172" deviceLimit="2.270" freqLimit="440.529" physResource="ctm_27x162/clkout1_buf/I0" logResource="ctm_27x162/clkout1_buf/I0" locationPin="BUFGMUX_X2Y11.I0" clockNet="ctm_27x162/clkfx"/></twPinLimitRpt></twConst><twConst anchorID="141" twConstType="PERIOD" ><twConstHead uID="14"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in&quot; TS_SYS_CLK3 / 0.25         HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.270</twMinPer></twConstHead><twPinLimitRpt anchorID="142"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in&quot; TS_SYS_CLK3 / 0.25
        HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="143" type="MINPERIOD" name="Tbcper_I" slack="17.730" period="20.000" constraintValue="20.000" deviceLimit="2.270" freqLimit="440.529" physResource="memc3_infrastructure_inst/U_BUFG_CLK1/I0" logResource="memc3_infrastructure_inst/U_BUFG_CLK1/I0" locationPin="BUFGMUX_X3Y8.I0" clockNet="memc3_infrastructure_inst/mcb_drp_clk_bufg_in"/><twPinLimit anchorID="144" type="MINPERIOD" name="Tcp" slack="18.601" period="20.000" constraintValue="20.000" deviceLimit="1.399" freqLimit="714.796" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1/CLK" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2/CLK" locationPin="SLICE_X22Y82.CLK" clockNet="c3_mcb_drp_clk"/><twPinLimit anchorID="145" type="MINPERIOD" name="Tmcbcper_UICLK" slack="19.000" period="20.000" constraintValue="20.000" deviceLimit="1.000" freqLimit="1000.000" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK" locationPin="MCB_X0Y1.UICLK" clockNet="c3_mcb_drp_clk"/></twPinLimitRpt></twConst><twConst anchorID="146" twConstType="PERIOD" ><twConstHead uID="15"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_180&quot; TS_SYS_CLK3 / 2 PHASE 1.25 ns         HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.499</twMinPer></twConstHead><twPinLimitRpt anchorID="147"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk_2x_180&quot; TS_SYS_CLK3 / 2 PHASE 1.25 ns
        HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="148" type="MINPERIOD" name="Tmcbcper_PLLCLK" slack="1.001" period="2.500" constraintValue="2.500" deviceLimit="1.499" freqLimit="667.111" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1" locationPin="MCB_X0Y1.PLLCLK1" clockNet="c3_sysclk_2x_180"/></twPinLimitRpt></twConst><twConst anchorID="149" twConstType="PERIOD" ><twConstHead uID="16"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_0&quot; TS_SYS_CLK3 / 2 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.499</twMinPer></twConstHead><twPinLimitRpt anchorID="150"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk_2x_0&quot; TS_SYS_CLK3 / 2 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="151" type="MINPERIOD" name="Tmcbcper_PLLCLK" slack="1.001" period="2.500" constraintValue="2.500" deviceLimit="1.499" freqLimit="667.111" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0" locationPin="MCB_X0Y1.PLLCLK0" clockNet="c3_sysclk_2x"/></twPinLimitRpt></twConst><twConst anchorID="152" twConstType="PERIOD" ><twConstHead uID="17"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk0_bufg_in&quot; TS_SYS_CLK3 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.570</twMinPer></twConstHead><twPinLimitRpt anchorID="153"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk0_bufg_in&quot; TS_SYS_CLK3 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="154" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y22.CLKA" clockNet="c3_clk0"/><twPinLimit anchorID="155" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y24.CLKA" clockNet="c3_clk0"/><twPinLimit anchorID="156" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y20.CLKA" clockNet="c3_clk0"/></twPinLimitRpt></twConst><twConst anchorID="157" twConstType="PERIOD" ><twConstHead uID="18"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0&quot;         TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;</twConstName><twItemCnt>30405</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1287</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>13.832</twMinPer></twConstHead><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_7 (SLICE_X30Y79.SR), 2 paths
</twPathRptBanner><twPathRpt anchorID="158"><twConstPath anchorID="159" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.542</twSlack><twSrc BELType="FF">memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_7</twDest><twTotPathDel>3.104</twTotPathDel><twClkSkew dest = "2.086" src = "2.226">0.140</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.214</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_7</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X23Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="15.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X23Y80.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp><twBEL>memc3_infrastructure_inst/powerup_pll_locked</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y82.B4</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.576</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y82.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X30Y79.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.618</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X30Y79.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.221</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER&lt;7&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_7</twBEL></twPathDel><twLogDel>0.910</twLogDel><twRouteDel>2.194</twRouteDel><twTotDel>3.104</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>29.3</twPctLog><twPctRoute>70.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="160"><twConstPath anchorID="161" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.730</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_7</twDest><twTotPathDel>3.153</twTotPathDel><twClkSkew dest = "0.519" src = "0.542">0.023</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.094</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_7</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X22Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X22Y80.AMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.576</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y82.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.479</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y82.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X30Y79.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.618</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X30Y79.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.221</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER&lt;7&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_7</twBEL></twPathDel><twLogDel>1.056</twLogDel><twRouteDel>2.097</twRouteDel><twTotDel>3.153</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>33.5</twPctLog><twPctRoute>66.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_3 (SLICE_X30Y78.SR), 2 paths
</twPathRptBanner><twPathRpt anchorID="162"><twConstPath anchorID="163" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.545</twSlack><twSrc BELType="FF">memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_3</twDest><twTotPathDel>3.100</twTotPathDel><twClkSkew dest = "2.085" src = "2.226">0.141</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.214</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X23Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="15.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X23Y80.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp><twBEL>memc3_infrastructure_inst/powerup_pll_locked</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y82.B4</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.576</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y82.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X30Y78.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.614</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X30Y78.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.221</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER&lt;3&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_3</twBEL></twPathDel><twLogDel>0.910</twLogDel><twRouteDel>2.190</twRouteDel><twTotDel>3.100</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>29.4</twPctLog><twPctRoute>70.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="164"><twConstPath anchorID="165" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.733</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_3</twDest><twTotPathDel>3.149</twTotPathDel><twClkSkew dest = "0.518" src = "0.542">0.024</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.094</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X22Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X22Y80.AMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.576</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y82.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.479</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y82.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X30Y78.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.614</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X30Y78.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.221</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER&lt;3&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_3</twBEL></twPathDel><twLogDel>1.056</twLogDel><twRouteDel>2.093</twRouteDel><twTotDel>3.149</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>33.5</twPctLog><twPctRoute>66.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_6 (SLICE_X30Y79.SR), 2 paths
</twPathRptBanner><twPathRpt anchorID="166"><twConstPath anchorID="167" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.551</twSlack><twSrc BELType="FF">memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_6</twDest><twTotPathDel>3.095</twTotPathDel><twClkSkew dest = "2.086" src = "2.226">0.140</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.120" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.214</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_infrastructure_inst/powerup_pll_locked</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_6</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X23Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="15.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X23Y80.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp><twBEL>memc3_infrastructure_inst/powerup_pll_locked</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y82.B4</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.576</twDelInfo><twComp>memc3_infrastructure_inst/powerup_pll_locked</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y82.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X30Y79.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.618</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X30Y79.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.212</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER&lt;7&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_6</twBEL></twPathDel><twLogDel>0.901</twLogDel><twRouteDel>2.194</twRouteDel><twTotDel>3.095</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>29.1</twPctLog><twPctRoute>70.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="168"><twConstPath anchorID="169" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>16.739</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_6</twDest><twTotPathDel>3.144</twTotPathDel><twClkSkew dest = "0.519" src = "0.542">0.023</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.174" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.094</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_6</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X22Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X22Y80.AMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.576</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y82.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.479</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/syn_uiclk_pll_lock</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y82.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_SELFREFRESH_EXIT_DQS_CAL</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X30Y79.SR</twSite><twDelType>net</twDelType><twFanCnt>16</twFanCnt><twDelInfo twEdge="twRising">1.618</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0</twComp></twPathDel><twPathDel><twSite>SLICE_X30Y79.CLK</twSite><twDelType>Trck</twDelType><twDelInfo twEdge="twRising">0.212</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER&lt;7&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/WAIT_200us_COUNTER_6</twBEL></twPathDel><twLogDel>1.047</twLogDel><twRouteDel>2.097</twRouteDel><twTotDel>3.144</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>33.3</twPctLog><twPctRoute>66.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0&quot;
        TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg_0 (SLICE_X17Y45.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="170"><twConstPath anchorID="171" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.403</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR_0</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg_0</twDest><twTotPathDel>0.405</twTotPathDel><twClkSkew dest = "0.043" src = "0.041">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR_0</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg_0</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X16Y45.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X16Y45.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR&lt;7&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y45.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.146</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR&lt;0&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X17Y45.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg&lt;7&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg_0</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.146</twRouteDel><twTotDel>0.405</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>64.0</twPctLog><twPctRoute>36.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg_3 (SLICE_X17Y45.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="172"><twConstPath anchorID="173" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.406</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR_3</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg_3</twDest><twTotPathDel>0.408</twTotPathDel><twClkSkew dest = "0.043" src = "0.041">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR_3</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg_3</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X16Y45.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X16Y45.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR&lt;7&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X17Y45.CX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.149</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR&lt;3&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X17Y45.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.059</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg&lt;7&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller/memcell_addr_reg_3</twBEL></twPathDel><twLogDel>0.259</twLogDel><twRouteDel>0.149</twRouteDel><twTotDel>0.408</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>63.5</twPctLog><twPctRoute>36.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_3 (SLICE_X24Y81.A6), 1 path
</twPathRptBanner><twPathRpt anchorID="174"><twConstPath anchorID="175" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.415</twSlack><twSrc BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_3</twSrc><twDest BELType="FF">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_3</twDest><twTotPathDel>0.415</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_3</twSrc><twDest BELType='FF'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X24Y81.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twSrcClk><twPathDel><twSite>SLICE_X24Y81.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter&lt;5&gt;</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y81.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.025</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter&lt;3&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X24Y81.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter&lt;5&gt;</twComp><twBEL>lut31041_6963</twBEL><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_3</twBEL></twPathDel><twLogDel>0.390</twLogDel><twRouteDel>0.025</twRouteDel><twTotDel>0.415</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">c3_mcb_drp_clk</twDestClk><twPctLog>94.0</twPctLog><twPctRoute>6.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="176"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0&quot;
        TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="177" type="MINPERIOD" name="Tbcper_I" slack="17.730" period="20.000" constraintValue="20.000" deviceLimit="2.270" freqLimit="440.529" physResource="memc3_infrastructure_inst/U_BUFG_CLK1/I0" logResource="memc3_infrastructure_inst/U_BUFG_CLK1/I0" locationPin="BUFGMUX_X3Y8.I0" clockNet="memc3_infrastructure_inst/mcb_drp_clk_bufg_in"/><twPinLimit anchorID="178" type="MINPERIOD" name="Tcp" slack="18.601" period="20.000" constraintValue="20.000" deviceLimit="1.399" freqLimit="714.796" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1/CLK" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2/CLK" locationPin="SLICE_X22Y82.CLK" clockNet="c3_mcb_drp_clk"/><twPinLimit anchorID="179" type="MINPERIOD" name="Tmcbcper_UICLK" slack="19.000" period="20.000" constraintValue="20.000" deviceLimit="1.000" freqLimit="1000.000" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK" locationPin="MCB_X0Y1.UICLK" clockNet="c3_mcb_drp_clk"/></twPinLimitRpt></twConst><twConst anchorID="180" twConstType="PERIOD" ><twConstHead uID="19"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk_2x_180_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_180_0&quot; TS_clk_wiz_v1_6_50x200_clkfx         / 2 PHASE 1.25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.499</twMinPer></twConstHead><twPinLimitRpt anchorID="181"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_180_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk_2x_180_0&quot; TS_clk_wiz_v1_6_50x200_clkfx
        / 2 PHASE 1.25 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="182" type="MINPERIOD" name="Tmcbcper_PLLCLK" slack="1.001" period="2.500" constraintValue="2.500" deviceLimit="1.499" freqLimit="667.111" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1" locationPin="MCB_X0Y1.PLLCLK1" clockNet="c3_sysclk_2x_180"/></twPinLimitRpt></twConst><twConst anchorID="183" twConstType="PERIOD" ><twConstHead uID="20"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk_2x_0_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_0_0&quot; TS_clk_wiz_v1_6_50x200_clkfx /         2 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.499</twMinPer></twConstHead><twPinLimitRpt anchorID="184"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk_2x_0_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk_2x_0_0&quot; TS_clk_wiz_v1_6_50x200_clkfx /
        2 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="185" type="MINPERIOD" name="Tmcbcper_PLLCLK" slack="1.001" period="2.500" constraintValue="2.500" deviceLimit="1.499" freqLimit="667.111" physResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0" logResource="memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0" locationPin="MCB_X0Y1.PLLCLK0" clockNet="c3_sysclk_2x"/></twPinLimitRpt></twConst><twConst anchorID="186" twConstType="PERIOD" ><twConstHead uID="21"><twConstName UCFConstName="" ScopeName="">TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk0_bufg_in_0&quot;         TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;</twConstName><twItemCnt>994</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>14</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">14</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>573</twEndPtCnt><twPathErrCnt>14</twPathErrCnt><twMinPer>4.948</twMinPer></twConstHead><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/fsmfake4_0 (SLICE_X0Y43.A6), 4 paths
</twPathRptBanner><twPathRpt anchorID="187"><twConstPath anchorID="188" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.052</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="FF">crtc2/fsmfake4_0</twDest><twTotPathDel>4.822</twTotPathDel><twClkSkew dest = "0.602" src = "0.653">0.051</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="19" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='FF'>crtc2/fsmfake4_0</twDest><twLogLvls>2</twLogLvls><twSrcSite>MCB_X0Y1.P5CMDCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>MCB_X0Y1.P5CMDEMPTY</twSite><twDelType>Tmcbcko_CMDEMPTY</twDelType><twDelInfo twEdge="twRising">1.080</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y57.A5</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.777</twDelInfo><twComp>c3_p5_cmd_empty</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y57.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>mig4_cmd_byte_addr&lt;10&gt;</twComp><twBEL>lut7294_1204</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.381</twDelInfo><twComp>lut7294_1204</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp><twBEL>][6794_1207</twBEL><twBEL>crtc2/fsmfake4_0</twBEL></twPathDel><twLogDel>1.664</twLogDel><twRouteDel>3.158</twRouteDel><twTotDel>4.822</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>34.5</twPctLog><twPctRoute>65.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="189"><twConstPath anchorID="190" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.317</twSlack><twSrc BELType="FF">crtc2/fsmfake4_2</twSrc><twDest BELType="FF">crtc2/fsmfake4_0</twDest><twTotPathDel>4.602</twTotPathDel><twClkSkew dest = "0.252" src = "0.258">0.006</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/fsmfake4_2</twSrc><twDest BELType='FF'>crtc2/fsmfake4_0</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X1Y39.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X1Y39.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>crtc2/fsmfake4&lt;2&gt;</twComp><twBEL>crtc2/fsmfake4_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y57.A4</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">2.207</twDelInfo><twComp>crtc2/fsmfake4&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y57.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>mig4_cmd_byte_addr&lt;10&gt;</twComp><twBEL>lut7294_1204</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.381</twDelInfo><twComp>lut7294_1204</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp><twBEL>][6794_1207</twBEL><twBEL>crtc2/fsmfake4_0</twBEL></twPathDel><twLogDel>1.014</twLogDel><twRouteDel>3.588</twRouteDel><twTotDel>4.602</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>22.0</twPctLog><twPctRoute>78.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="191"><twConstPath anchorID="192" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.660</twSlack><twSrc BELType="FF">crtc2/fsmfake4_0</twSrc><twDest BELType="FF">crtc2/fsmfake4_0</twDest><twTotPathDel>4.265</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/fsmfake4_0</twSrc><twDest BELType='FF'>crtc2/fsmfake4_0</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X0Y43.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X0Y43.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp><twBEL>crtc2/fsmfake4_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y57.A6</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.824</twDelInfo><twComp>crtc2/fsmfake4&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y57.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>mig4_cmd_byte_addr&lt;10&gt;</twComp><twBEL>lut7294_1204</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.381</twDelInfo><twComp>lut7294_1204</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp><twBEL>][6794_1207</twBEL><twBEL>crtc2/fsmfake4_0</twBEL></twPathDel><twLogDel>1.060</twLogDel><twRouteDel>3.205</twRouteDel><twTotDel>4.265</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>24.9</twPctLog><twPctRoute>75.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="4" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/mem_rd_count8_r_6 (SLICE_X1Y43.A6), 4 paths
</twPathRptBanner><twPathRpt anchorID="193"><twConstPath anchorID="194" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.105</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="FF">crtc2/mem_rd_count8_r_6</twDest><twTotPathDel>4.814</twTotPathDel><twClkSkew dest = "0.252" src = "0.258">0.006</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='FF'>crtc2/mem_rd_count8_r_6</twDest><twLogLvls>2</twLogLvls><twSrcSite>MCB_X0Y1.P5CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>MCB_X0Y1.P5FULL</twSite><twDelType>Tmcbcko_FULL</twDelType><twDelInfo twEdge="twRising">2.310</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.D6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.997</twDelInfo><twComp>c3_p5_rd_full</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp><twBEL>lut7007_1140</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.899</twDelInfo><twComp>lut7007_1140</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>crtc2/mem_rd_count8_r_61</twComp><twBEL>][7436_14161</twBEL><twBEL>crtc2/mem_rd_count8_r_6</twBEL></twPathDel><twLogDel>2.918</twLogDel><twRouteDel>1.896</twRouteDel><twTotDel>4.814</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>60.6</twPctLog><twPctRoute>39.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="195"><twConstPath anchorID="196" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.877</twSlack><twSrc BELType="FF">crtc2/mem_state_r_FSM_FFd1</twSrc><twDest BELType="FF">crtc2/mem_rd_count8_r_6</twDest><twTotPathDel>3.033</twTotPathDel><twClkSkew dest = "0.162" src = "0.177">0.015</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/mem_state_r_FSM_FFd1</twSrc><twDest BELType='FF'>crtc2/mem_rd_count8_r_6</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X1Y46.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X1Y46.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd11</twComp><twBEL>crtc2/mem_state_r_FSM_FFd1</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.D4</twSite><twDelType>net</twDelType><twFanCnt>26</twFanCnt><twDelInfo twEdge="twRising">1.096</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd1</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp><twBEL>lut7007_1140</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.899</twDelInfo><twComp>lut7007_1140</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>crtc2/mem_rd_count8_r_61</twComp><twBEL>][7436_14161</twBEL><twBEL>crtc2/mem_rd_count8_r_6</twBEL></twPathDel><twLogDel>1.038</twLogDel><twRouteDel>1.995</twRouteDel><twTotDel>3.033</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>34.2</twPctLog><twPctRoute>65.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="197"><twConstPath anchorID="198" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.929</twSlack><twSrc BELType="FF">crtc2/mem_state_r_FSM_FFd2</twSrc><twDest BELType="FF">crtc2/mem_rd_count8_r_6</twDest><twTotPathDel>2.982</twTotPathDel><twClkSkew dest = "0.162" src = "0.176">0.014</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/mem_state_r_FSM_FFd2</twSrc><twDest BELType='FF'>crtc2/mem_rd_count8_r_6</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X1Y45.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X1Y45.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd21</twComp><twBEL>crtc2/mem_state_r_FSM_FFd2</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y43.D3</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">1.045</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd2</twComp></twPathDel><twPathDel><twSite>SLICE_X0Y43.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>crtc2/fsmfake4&lt;1&gt;</twComp><twBEL>lut7007_1140</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y43.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.899</twDelInfo><twComp>lut7007_1140</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>crtc2/mem_rd_count8_r_61</twComp><twBEL>][7436_14161</twBEL><twBEL>crtc2/mem_rd_count8_r_6</twBEL></twPathDel><twLogDel>1.038</twLogDel><twRouteDel>1.944</twRouteDel><twTotDel>2.982</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>34.8</twPctLog><twPctRoute>65.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="9" iCriticalPaths="0" sType="EndPoint">Paths for end point crtc2/mem_state_r_FSM_FFd3 (SLICE_X1Y44.CX), 9 paths
</twPathRptBanner><twPathRpt anchorID="199"><twConstPath anchorID="200" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.106</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="FF">crtc2/mem_state_r_FSM_FFd3</twDest><twTotPathDel>4.815</twTotPathDel><twClkSkew dest = "0.254" src = "0.258">0.004</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='FF'>crtc2/mem_state_r_FSM_FFd3</twDest><twLogLvls>2</twLogLvls><twSrcSite>MCB_X0Y1.P5CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>MCB_X0Y1.P5EMPTY</twSite><twDelType>Tmcbcko_EMPTY</twDelType><twDelInfo twEdge="twRising">2.270</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y44.C6</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">0.929</twDelInfo><twComp>c3_p5_rd_empty</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y44.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd31</twComp><twBEL>lut7022_1145</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y44.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.226</twDelInfo><twComp>lut7022_1145</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y44.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd31</twComp><twBEL>lut7023_1146</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y44.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.758</twDelInfo><twComp>lut7023_1146</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y44.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.114</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd31</twComp><twBEL>crtc2/mem_state_r_FSM_FFd3</twBEL></twPathDel><twLogDel>2.902</twLogDel><twRouteDel>1.913</twRouteDel><twTotDel>4.815</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>60.3</twPctLog><twPctRoute>39.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="201"><twConstPath anchorID="202" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.249</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="FF">crtc2/mem_state_r_FSM_FFd3</twDest><twTotPathDel>4.627</twTotPathDel><twClkSkew dest = "0.604" src = "0.653">0.049</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="19" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='FF'>crtc2/mem_state_r_FSM_FFd3</twDest><twLogLvls>1</twLogLvls><twSrcSite>MCB_X0Y1.P5CMDCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>MCB_X0Y1.P5CMDEMPTY</twSite><twDelType>Tmcbcko_CMDEMPTY</twDelType><twDelInfo twEdge="twRising">1.080</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y44.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">2.416</twDelInfo><twComp>c3_p5_cmd_empty</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y44.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd31</twComp><twBEL>lut7023_1146</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y44.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.758</twDelInfo><twComp>lut7023_1146</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y44.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.114</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd31</twComp><twBEL>crtc2/mem_state_r_FSM_FFd3</twBEL></twPathDel><twLogDel>1.453</twLogDel><twRouteDel>3.174</twRouteDel><twTotDel>4.627</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>31.4</twPctLog><twPctRoute>68.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="203"><twConstPath anchorID="204" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.404</twSlack><twSrc BELType="FF">crtc2/mem_init_done_r</twSrc><twDest BELType="FF">crtc2/mem_state_r_FSM_FFd3</twDest><twTotPathDel>3.470</twTotPathDel><twClkSkew dest = "0.512" src = "0.563">0.051</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.132" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.075</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc2/mem_init_done_r</twSrc><twDest BELType='FF'>crtc2/mem_state_r_FSM_FFd3</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X4Y50.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">c3_clk0</twSrcClk><twPathDel><twSite>SLICE_X4Y50.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>crtc1/mem_init_done_r</twComp><twBEL>crtc2/mem_init_done_r</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y44.C3</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">1.378</twDelInfo><twComp>crtc1/mem_init_done_r</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y44.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd31</twComp><twBEL>lut7022_1145</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y44.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.226</twDelInfo><twComp>lut7022_1145</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y44.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd31</twComp><twBEL>lut7023_1146</twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y44.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.758</twDelInfo><twComp>lut7023_1146</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y44.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.114</twDelInfo><twComp>crtc2/mem_state_r_FSM_FFd31</twComp><twBEL>crtc2/mem_state_r_FSM_FFd3</twBEL></twPathDel><twLogDel>1.108</twLogDel><twRouteDel>2.362</twRouteDel><twTotDel>3.470</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">c3_clk0</twDestClk><twPctLog>31.9</twPctLog><twPctRoute>68.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk0_bufg_in_0&quot;
        TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point crtc1/fb_rd_addr_r_7 (SLICE_X8Y69.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="205"><twConstPath anchorID="206" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-7.294</twSlack><twSrc BELType="FF">crtc1/crtc_rd_vpos_r_7</twSrc><twDest BELType="FF">crtc1/fb_rd_addr_r_7</twDest><twTotPathDel>0.992</twTotPathDel><twClkSkew dest = "10.931" src = "2.183">-8.748</twClkSkew><twDelConst>1.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.419" fPhaseErr="0.325" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.538</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc1/crtc_rd_vpos_r_7</twSrc><twDest BELType='FF'>crtc1/fb_rd_addr_r_7</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X15Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="64.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X15Y69.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.405</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;7&gt;</twComp><twBEL>crtc1/crtc_rd_vpos_r_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y69.DX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.680</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;7&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X8Y69.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">-0.093</twDelInfo><twComp>crtc1/fb_rd_addr_r&lt;7&gt;</twComp><twBEL>crtc1/fb_rd_addr_r_7</twBEL></twPathDel><twLogDel>0.312</twLogDel><twRouteDel>0.680</twRouteDel><twTotDel>0.992</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="65.000">c3_clk0</twDestClk><twPctLog>31.5</twPctLog><twPctRoute>68.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point crtc1/fb_rd_addr_r_4 (SLICE_X8Y69.AX), 1 path
</twPathRptBanner><twPathRpt anchorID="207"><twConstPath anchorID="208" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-7.274</twSlack><twSrc BELType="FF">crtc1/crtc_rd_vpos_r_4</twSrc><twDest BELType="FF">crtc1/fb_rd_addr_r_4</twDest><twTotPathDel>1.012</twTotPathDel><twClkSkew dest = "10.931" src = "2.183">-8.748</twClkSkew><twDelConst>1.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.419" fPhaseErr="0.325" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.538</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc1/crtc_rd_vpos_r_4</twSrc><twDest BELType='FF'>crtc1/fb_rd_addr_r_4</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X15Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="64.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X15Y69.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.405</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;7&gt;</twComp><twBEL>crtc1/crtc_rd_vpos_r_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y69.AX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.700</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;4&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X8Y69.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">-0.093</twDelInfo><twComp>crtc1/fb_rd_addr_r&lt;7&gt;</twComp><twBEL>crtc1/fb_rd_addr_r_4</twBEL></twPathDel><twLogDel>0.312</twLogDel><twRouteDel>0.700</twRouteDel><twTotDel>1.012</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="65.000">c3_clk0</twDestClk><twPctLog>30.8</twPctLog><twPctRoute>69.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point crtc1/fb_rd_addr_r_5 (SLICE_X8Y69.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="209"><twConstPath anchorID="210" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-7.147</twSlack><twSrc BELType="FF">crtc1/crtc_rd_vpos_r_5</twSrc><twDest BELType="FF">crtc1/fb_rd_addr_r_5</twDest><twTotPathDel>1.139</twTotPathDel><twClkSkew dest = "10.931" src = "2.183">-8.748</twClkSkew><twDelConst>1.000</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.419" fPhaseErr="0.325" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.538</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>crtc1/crtc_rd_vpos_r_5</twSrc><twDest BELType='FF'>crtc1/fb_rd_addr_r_5</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X15Y69.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="64.000">CLK63</twSrcClk><twPathDel><twSite>SLICE_X15Y69.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.405</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;7&gt;</twComp><twBEL>crtc1/crtc_rd_vpos_r_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X8Y69.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.827</twDelInfo><twComp>crtc1/crtc_rd_vpos_r&lt;5&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X8Y69.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">-0.093</twDelInfo><twComp>crtc1/fb_rd_addr_r&lt;7&gt;</twComp><twBEL>crtc1/fb_rd_addr_r_5</twBEL></twPathDel><twLogDel>0.312</twLogDel><twRouteDel>0.827</twRouteDel><twTotDel>1.139</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="65.000">c3_clk0</twDestClk><twPctLog>27.4</twPctLog><twPctRoute>72.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="211"><twPinLimitBanner>Component Switching Limit Checks: TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP
        &quot;memc3_infrastructure_inst_clk0_bufg_in_0&quot;
        TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="212" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y22.CLKA" clockNet="c3_clk0"/><twPinLimit anchorID="213" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc1/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y24.CLKA" clockNet="c3_clk0"/><twPinLimit anchorID="214" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="1.430" period="5.000" constraintValue="5.000" deviceLimit="3.570" freqLimit="280.112" physResource="crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" logResource="crtc2/linebuf0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA" locationPin="RAMB16_X0Y20.CLKA" clockNet="c3_clk0"/></twPinLimitRpt></twConst><twConst anchorID="215" twConstType="PERIOD" ><twConstHead uID="22"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_125&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf         / 1.25 HIGH 50%;</twConstName><twItemCnt>45</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>1</twErrCntPinLimit><twEndPtCnt>45</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>8.000</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB10), 1 path
</twPathRptBanner><twPathRpt anchorID="216"><twConstPath anchorID="217" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.325</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>3.872</twTotPathDel><twClkSkew dest = "0.496" src = "0.606">0.110</twClkSkew><twDelConst>6.400</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.172" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.093</twClkUncert><twDetPath maxSiteLen="24" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXDATA12</twSite><twDelType>Tgtpcko_RXDATA</twDelType><twDelInfo twEdge="twRising">1.220</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXDATAB10</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.212</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_data&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcicck_MGT</twDelType><twDelInfo twEdge="twRising">1.440</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>2.660</twLogDel><twRouteDel>1.212</twRouteDel><twTotDel>3.872</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>68.7</twPctLog><twPctRoute>31.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB11), 1 path
</twPathRptBanner><twPathRpt anchorID="218"><twConstPath anchorID="219" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.354</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>3.843</twTotPathDel><twClkSkew dest = "0.496" src = "0.606">0.110</twClkSkew><twDelConst>6.400</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.172" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.093</twClkUncert><twDetPath maxSiteLen="24" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXDATA13</twSite><twDelType>Tgtpcko_RXDATA</twDelType><twDelInfo twEdge="twRising">1.220</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXDATAB11</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.183</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_data&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcicck_MGT</twDelType><twDelInfo twEdge="twRising">1.440</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>2.660</twLogDel><twRouteDel>1.183</twRouteDel><twTotDel>3.843</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>69.2</twPctLog><twPctRoute>30.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB1), 1 path
</twPathRptBanner><twPathRpt anchorID="220"><twConstPath anchorID="221" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.423</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>3.774</twTotPathDel><twClkSkew dest = "0.496" src = "0.606">0.110</twClkSkew><twDelConst>6.400</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.172" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.093</twClkUncert><twDetPath maxSiteLen="24" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXDATA19</twSite><twDelType>Tgtpcko_RXDATA</twDelType><twDelInfo twEdge="twRising">1.220</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXDATAB1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.114</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_data&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcicck_MGT</twDelType><twDelInfo twEdge="twRising">1.440</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>2.660</twLogDel><twRouteDel>1.114</twRouteDel><twTotDel>3.774</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>70.5</twPctLog><twPctRoute>29.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_125&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 1.25 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPEPHYSTATUSB), 1 path
</twPathRptBanner><twPathRpt anchorID="222"><twConstPath anchorID="223" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.129</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.056</twTotPathDel><twClkSkew dest = "0.201" src = "0.274">0.073</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="26" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.PHYSTATUS1</twSite><twDelType>Tgtpcko_PHYSTATUS</twDelType><twDelInfo twEdge="twFalling">0.565</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPEPHYSTATUSB</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.341</twDelInfo><twComp>inst_sp6wrap/eptest_i/phystatus</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcickc_MGT</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.285</twLogDel><twRouteDel>0.341</twRouteDel><twTotDel>0.056</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>-508.9</twPctLog><twPctRoute>608.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB0), 1 path
</twPathRptBanner><twPathRpt anchorID="224"><twConstPath anchorID="225" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.129</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.056</twTotPathDel><twClkSkew dest = "0.201" src = "0.274">0.073</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="24" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXDATA18</twSite><twDelType>Tgtpcko_RXDATA</twDelType><twDelInfo twEdge="twFalling">0.565</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXDATAB0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.341</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_data&lt;8&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcickc_MGT</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.285</twLogDel><twRouteDel>0.341</twRouteDel><twTotDel>0.056</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>-508.9</twPctLog><twPctRoute>608.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.PIPERXDATAB3), 1 path
</twPathRptBanner><twPathRpt anchorID="226"><twConstPath anchorID="227" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.129</twSlack><twSrc BELType="HSIO">inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.056</twTotPathDel><twClkSkew dest = "0.201" src = "0.274">0.073</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="25" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='HSIO'>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>GTPA1_DUAL_X0Y0.RXUSRCLK21</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twSrcClk><twPathDel><twSite>GTPA1_DUAL_X0Y0.RXDATA111</twSite><twDelType>Tgtpcko_RXDATA</twDelType><twDelInfo twEdge="twFalling">0.565</twDelInfo><twComp>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twComp><twBEL>inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.PIPERXDATAB3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.341</twDelInfo><twComp>inst_sp6wrap/eptest_i/rx_data&lt;11&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.MGTCLK</twSite><twDelType>Tpcickc_MGT</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.285</twLogDel><twRouteDel>0.341</twRouteDel><twTotDel>0.056</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.400">inst_sp6wrap/eptest_i/mgt_clk</twDestClk><twPctLog>-508.9</twPctLog><twPctRoute>608.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="228"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_125&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 1.25 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="229" type="MINPERIOD" name="Tpciper_MGTCLK" slack="-1.600" period="6.400" constraintValue="6.400" deviceLimit="8.000" freqLimit="125.000" physResource="inst_sp6wrap/eptest_i/PCIE_A1/MGTCLK" logResource="inst_sp6wrap/eptest_i/PCIE_A1/MGTCLK" locationPin="PCIE_X0Y0.MGTCLK" clockNet="inst_sp6wrap/eptest_i/mgt_clk"/><twPinLimit anchorID="230" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="6.400" constraintValue="6.400" deviceLimit="6.400" freqLimit="156.250" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK21" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK21" locationPin="GTPA1_DUAL_X0Y0.RXUSRCLK21" clockNet="inst_sp6wrap/eptest_i/mgt_clk"/><twPinLimit anchorID="231" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="0.000" period="6.400" constraintValue="6.400" deviceLimit="6.400" freqLimit="156.250" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK21" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK21" locationPin="GTPA1_DUAL_X0Y0.TXUSRCLK21" clockNet="inst_sp6wrap/eptest_i/mgt_clk"/></twPinLimitRpt></twConst><twConst anchorID="232" twConstType="PERIOD" ><twConstHead uID="23"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_250&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf         / 2.5 HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.200</twMinPer></twConstHead><twPinLimitRpt anchorID="233"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_250&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf
        / 2.5 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="234" type="MINPERIOD" name="Tgtpcper_RXUSRCLK" slack="0.000" period="3.200" constraintValue="3.200" deviceLimit="3.200" freqLimit="312.500" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK1" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/RXUSRCLK1" locationPin="GTPA1_DUAL_X0Y0.RXUSRCLK1" clockNet="inst_sp6wrap/eptest_i/mgt_clk_2x"/><twPinLimit anchorID="235" type="MINPERIOD" name="Tgtpcper_TXUSRCLK" slack="0.000" period="3.200" constraintValue="3.200" deviceLimit="3.200" freqLimit="312.500" physResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK1" logResource="inst_sp6wrap/eptest_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i/TXUSRCLK1" locationPin="GTPA1_DUAL_X0Y0.TXUSRCLK1" clockNet="inst_sp6wrap/eptest_i/mgt_clk_2x"/><twPinLimit anchorID="236" type="MINPERIOD" name="Tbcper_I" slack="0.930" period="3.200" constraintValue="3.200" deviceLimit="2.270" freqLimit="440.529" physResource="inst_sp6wrap/eptest_i/mgt2x_bufg/I0" logResource="inst_sp6wrap/eptest_i/mgt2x_bufg/I0" locationPin="BUFGMUX_X2Y9.I0" clockNet="inst_sp6wrap/eptest_i/clk_250"/></twPinLimitRpt></twConst><twConst anchorID="237" twConstType="PERIOD" ><twConstHead uID="24"><twConstName UCFConstName="" ScopeName="">TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_62_5&quot;         TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;</twConstName><twItemCnt>9414</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>1</twErrCntPinLimit><twEndPtCnt>3807</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPathRptBanner iPaths="37" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r (SLICE_X12Y104.A1), 37 paths
</twPathRptBanner><twPathRpt anchorID="238"><twConstPath anchorID="239" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.596</twSlack><twSrc BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twSrc><twDest BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twTotPathDel>11.081</twTotPathDel><twClkSkew dest = "0.241" src = "0.259">0.018</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="21" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twSrc><twDest BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twLogLvls>5</twLogLvls><twSrcSite>PCIE_X0Y0.USERCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>PCIE_X0Y0.TRNRSRCRDYN</twSite><twDelType>Tpcicko_TRN</twDelType><twDelInfo twEdge="twRising">2.080</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y100.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">2.341</twDelInfo><twComp>inst_sp6wrap/trn_rsrc_rdy_n</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y100.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut33845_7790</twComp><twBEL>lut33818_161</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y95.D5</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.621</twDelInfo><twComp>lut33818_161</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y95.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;3&gt;</twComp><twBEL>lut33823_166</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y103.C3</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">2.382</twDelInfo><twComp>lut33823_166</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y103.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.403</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634_G</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.C3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.628</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33950_7821</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.A1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.524</twDelInfo><twComp>lut33950_7821</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33952_7823</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twBEL></twPathDel><twLogDel>3.585</twLogDel><twRouteDel>7.496</twRouteDel><twTotDel>11.081</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>32.4</twPctLog><twPctRoute>67.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="240"><twConstPath anchorID="241" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>1.643</twSlack><twSrc BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twSrc><twDest BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twTotPathDel>11.034</twTotPathDel><twClkSkew dest = "0.241" src = "0.259">0.018</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="21" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twSrc><twDest BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twLogLvls>5</twLogLvls><twSrcSite>PCIE_X0Y0.USERCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>PCIE_X0Y0.TRNRSRCRDYN</twSite><twDelType>Tpcicko_TRN</twDelType><twDelInfo twEdge="twRising">2.080</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y100.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">2.341</twDelInfo><twComp>inst_sp6wrap/trn_rsrc_rdy_n</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y100.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut33845_7790</twComp><twBEL>lut33818_161</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y95.D5</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.621</twDelInfo><twComp>lut33818_161</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y95.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;3&gt;</twComp><twBEL>lut33823_166</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y103.D3</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">2.336</twDelInfo><twComp>lut33823_166</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y103.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.402</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634_F</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.C3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.628</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33950_7821</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.A1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.524</twDelInfo><twComp>lut33950_7821</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33952_7823</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twBEL></twPathDel><twLogDel>3.584</twLogDel><twRouteDel>7.450</twRouteDel><twTotDel>11.034</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>32.5</twPctLog><twPctRoute>67.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="242"><twConstPath anchorID="243" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.759</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state_0</twSrc><twDest BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twTotPathDel>8.920</twTotPathDel><twClkSkew dest = "0.241" src = "0.257">0.016</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state_0</twSrc><twDest BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X13Y103.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X13Y103.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;1&gt;</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y94.A2</twSite><twDelType>net</twDelType><twFanCnt>44</twFanCnt><twDelInfo twEdge="twRising">2.336</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y94.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut33533_164</twComp><twBEL>lut33533_164</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y93.D4</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>lut33533_164</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y93.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>user_be&lt;3&gt;</twComp><twBEL>lut33534_165</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y95.D6</twSite><twDelType>net</twDelType><twFanCnt>34</twFanCnt><twDelInfo twEdge="twRising">0.384</twDelInfo><twComp>lut33534_165</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y95.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;3&gt;</twComp><twBEL>lut33823_166</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y103.C3</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">2.382</twDelInfo><twComp>lut33823_166</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y103.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.403</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634_G</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.C3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.628</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33950_7821</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.A1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.524</twDelInfo><twComp>lut33950_7821</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33952_7823</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twBEL></twPathDel><twLogDel>2.194</twLogDel><twRouteDel>6.726</twRouteDel><twTotDel>8.920</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>24.6</twPctLog><twPctRoute>75.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="34" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r (SLICE_X12Y104.A5), 34 paths
</twPathRptBanner><twPathRpt anchorID="244"><twConstPath anchorID="245" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.177</twSlack><twSrc BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twSrc><twDest BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twTotPathDel>10.500</twTotPathDel><twClkSkew dest = "0.241" src = "0.259">0.018</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="21" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twSrc><twDest BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twLogLvls>5</twLogLvls><twSrcSite>PCIE_X0Y0.USERCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>PCIE_X0Y0.TRNRSRCRDYN</twSite><twDelType>Tpcicko_TRN</twDelType><twDelInfo twEdge="twRising">2.080</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y100.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">2.341</twDelInfo><twComp>inst_sp6wrap/trn_rsrc_rdy_n</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y100.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut33845_7790</twComp><twBEL>lut33818_161</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y95.D5</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.621</twDelInfo><twComp>lut33818_161</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y95.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;3&gt;</twComp><twBEL>lut33823_166</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y103.C3</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">2.382</twDelInfo><twComp>lut33823_166</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y103.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.403</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634_G</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.B6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.383</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33951_7822</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.188</twDelInfo><twComp>lut33951_7822</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33952_7823</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twBEL></twPathDel><twLogDel>3.585</twLogDel><twRouteDel>6.915</twRouteDel><twTotDel>10.500</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>34.1</twPctLog><twPctRoute>65.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="246"><twConstPath anchorID="247" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>2.224</twSlack><twSrc BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twSrc><twDest BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twTotPathDel>10.453</twTotPathDel><twClkSkew dest = "0.241" src = "0.259">0.018</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="21" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twSrc><twDest BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twLogLvls>5</twLogLvls><twSrcSite>PCIE_X0Y0.USERCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>PCIE_X0Y0.TRNRSRCRDYN</twSite><twDelType>Tpcicko_TRN</twDelType><twDelInfo twEdge="twRising">2.080</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y100.B5</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">2.341</twDelInfo><twComp>inst_sp6wrap/trn_rsrc_rdy_n</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y100.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut33845_7790</twComp><twBEL>lut33818_161</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y95.D5</twSite><twDelType>net</twDelType><twFanCnt>12</twFanCnt><twDelInfo twEdge="twRising">1.621</twDelInfo><twComp>lut33818_161</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y95.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;3&gt;</twComp><twBEL>lut33823_166</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y103.D3</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">2.336</twDelInfo><twComp>lut33823_166</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y103.CMUX</twSite><twDelType>Topdc</twDelType><twDelInfo twEdge="twRising">0.402</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634_F</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.B6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.383</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33951_7822</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.188</twDelInfo><twComp>lut33951_7822</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33952_7823</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twBEL></twPathDel><twLogDel>3.584</twLogDel><twRouteDel>6.869</twRouteDel><twTotDel>10.453</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>34.3</twPctLog><twPctRoute>65.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="248"><twConstPath anchorID="249" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>4.340</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state_0</twSrc><twDest BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twTotPathDel>8.339</twTotPathDel><twClkSkew dest = "0.241" src = "0.257">0.016</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state_0</twSrc><twDest BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X13Y103.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>SLICE_X13Y103.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;1&gt;</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y94.A2</twSite><twDelType>net</twDelType><twFanCnt>44</twFanCnt><twDelInfo twEdge="twRising">2.336</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y94.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>lut33533_164</twComp><twBEL>lut33533_164</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y93.D4</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>lut33533_164</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y93.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>user_be&lt;3&gt;</twComp><twBEL>lut33534_165</twBEL></twPathDel><twPathDel><twSite>SLICE_X23Y95.D6</twSite><twDelType>net</twDelType><twFanCnt>34</twFanCnt><twDelInfo twEdge="twRising">0.384</twDelInfo><twComp>lut33534_165</twComp></twPathDel><twPathDel><twSite>SLICE_X23Y95.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/state&lt;3&gt;</twComp><twBEL>lut33823_166</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y103.C3</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">2.382</twDelInfo><twComp>lut33823_166</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y103.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.403</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634_G</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035634</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.B6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.383</twDelInfo><twComp>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/Mmux_n035633</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33951_7822</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y104.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.188</twDelInfo><twComp>lut33951_7822</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y104.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.349</twDelInfo><twComp>inst_sp6wrap/trn_rdst_rdy_n</twComp><twBEL>lut33952_7823</twBEL><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_RX/rdst_rdy_n_r</twBEL></twPathDel><twLogDel>2.194</twLogDel><twRouteDel>6.145</twRouteDel><twTotDel>8.339</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>26.3</twPctLog><twPctRoute>73.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (MCB_X0Y1.P0RDEN), 1 path
</twPathRptBanner><twPathRpt anchorID="250"><twConstPath anchorID="251" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.272</twSlack><twSrc BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType="CPU">memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twDest><twTotPathDel>9.423</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>12.800</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.198" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twSrc><twDest BELType='CPU'>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twDest><twLogLvls>1</twLogLvls><twSrcSite>MCB_X0Y1.P0RDCLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">pclk</twSrcClk><twPathDel><twSite>MCB_X0Y1.P0RDEMPTY</twSite><twDelType>Tmcbcko_RDEMPTY</twDelType><twDelInfo twEdge="twRising">2.270</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y89.A6</twSite><twDelType>net</twDelType><twFanCnt>24</twFanCnt><twDelInfo twEdge="twRising">3.392</twDelInfo><twComp>c3_p0_rd_empty</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y89.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>inst_sp6wrap/app/buff_wr_req_r</twComp><twBEL>][24657_10_INV_0</twBEL></twPathDel><twPathDel><twSite>MCB_X0Y1.P0RDEN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">3.119</twDelInfo><twComp>][24657_10</twComp></twPathDel><twPathDel><twSite>MCB_X0Y1.P0RDCLK</twSite><twDelType>Tmcbdck_RDEN</twDelType><twDelInfo twEdge="twRising">0.407</twDelInfo><twComp>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twComp><twBEL>memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0</twBEL></twPathDel><twLogDel>2.912</twLogDel><twRouteDel>6.511</twRouteDel><twTotDel>9.423</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>30.9</twPctLog><twPctRoute>69.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_62_5&quot;
        TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD0), 1 path
</twPathRptBanner><twPathRpt anchorID="252"><twConstPath anchorID="253" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.274</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_0</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.268</twTotPathDel><twClkSkew dest = "0.068" src = "0.074">0.006</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_0</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X26Y96.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.800">pclk</twSrcClk><twPathDel><twSite>SLICE_X26Y96.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;0&gt;</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_0</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.TRNTD0</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.884</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;0&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.USERCLK</twSite><twDelType>Tpcickd_TRNTD</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.616</twLogDel><twRouteDel>0.884</twRouteDel><twTotDel>0.268</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>-229.9</twPctLog><twPctRoute>329.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD1), 1 path
</twPathRptBanner><twPathRpt anchorID="254"><twConstPath anchorID="255" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.352</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_1</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.351</twTotPathDel><twClkSkew dest = "0.068" src = "0.069">0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_1</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X25Y100.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.800">pclk</twSrcClk><twPathDel><twSite>SLICE_X25Y100.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;4&gt;</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_1</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.TRNTD1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">1.003</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;1&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.USERCLK</twSite><twDelType>Tpcickd_TRNTD</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.652</twLogDel><twRouteDel>1.003</twRouteDel><twTotDel>0.351</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>-185.8</twPctLog><twPctRoute>285.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point inst_sp6wrap/eptest_i/PCIE_A1 (PCIE_X0Y0.TRNTD2), 1 path
</twPathRptBanner><twPathRpt anchorID="256"><twConstPath anchorID="257" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.363</twSlack><twSrc BELType="FF">inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_2</twSrc><twDest BELType="OTHER">inst_sp6wrap/eptest_i/PCIE_A1</twDest><twTotPathDel>0.362</twTotPathDel><twClkSkew dest = "0.068" src = "0.069">0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_2</twSrc><twDest BELType='OTHER'>inst_sp6wrap/eptest_i/PCIE_A1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X25Y100.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="12.800">pclk</twSrcClk><twPathDel><twSite>SLICE_X25Y100.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;4&gt;</twComp><twBEL>inst_sp6wrap/app/PIO/PIO_EP/EP_TX/td_r_2</twBEL></twPathDel><twPathDel><twSite>PCIE_X0Y0.TRNTD2</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">1.014</twDelInfo><twComp>inst_sp6wrap/trn_td&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>PCIE_X0Y0.USERCLK</twSite><twDelType>Tpcickd_TRNTD</twDelType><twDelInfo twEdge="twFalling">-0.850</twDelInfo><twComp>inst_sp6wrap/eptest_i/PCIE_A1</twComp><twBEL>inst_sp6wrap/eptest_i/PCIE_A1</twBEL></twPathDel><twLogDel>-0.652</twLogDel><twRouteDel>1.014</twRouteDel><twTotDel>0.362</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="12.800">pclk</twDestClk><twPctLog>-180.1</twPctLog><twPctRoute>280.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="258"><twPinLimitBanner>Component Switching Limit Checks: TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP
        &quot;inst_sp6wrap_eptest_i_clk_62_5&quot;
        TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="259" type="MINPERIOD" name="Tpciper_USERCLK" slack="-3.200" period="12.800" constraintValue="12.800" deviceLimit="16.000" freqLimit="62.500" physResource="inst_sp6wrap/eptest_i/PCIE_A1/USERCLK" logResource="inst_sp6wrap/eptest_i/PCIE_A1/USERCLK" locationPin="PCIE_X0Y0.USERCLK" clockNet="pclk"/><twPinLimit anchorID="260" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="9.230" period="12.800" constraintValue="12.800" deviceLimit="3.570" freqLimit="280.112" physResource="inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKA" logResource="inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKA" locationPin="RAMB16_X0Y52.CLKA" clockNet="pclk"/><twPinLimit anchorID="261" type="MINPERIOD" name="Trper_CLKB" slack="9.230" period="12.800" constraintValue="12.800" deviceLimit="3.570" freqLimit="280.112" physResource="inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKB" logResource="inst_sp6wrap/eptest_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/ramb16/CLKB" locationPin="RAMB16_X0Y52.CLKB" clockNet="pclk"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="262"><twConstRollup name="TS_xtalclk" fullName="TS_xtalclk = PERIOD TIMEGRP &quot;xtalclk&quot; 20 ns HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="8.000" actualRollup="19.792" errors="0" errorRollup="14" items="0" itemsRollup="53268"/><twConstRollup name="TS_clk_wiz_v1_6_50x200_clkfx" fullName="TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIMEGRP &quot;clk_wiz_v1_6_50x200_clkfx&quot;         TS_xtalclk / 4 HIGH 50%;" type="child" depth="1" requirement="5.000" prefType="period" actual="2.800" actualRollup="4.948" errors="0" errorRollup="14" items="0" itemsRollup="31399"/><twConstRollup name="TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0" fullName="TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0&quot;         TS_clk_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%;" type="child" depth="2" requirement="20.000" prefType="period" actual="13.832" actualRollup="N/A" errors="0" errorRollup="0" items="30405" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk_2x_180_0" fullName="TS_memc3_infrastructure_inst_clk_2x_180_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_180_0&quot; TS_clk_wiz_v1_6_50x200_clkfx         / 2 PHASE 1.25 ns HIGH 50%;" type="child" depth="2" requirement="2.500" prefType="period" actual="1.499" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk_2x_0_0" fullName="TS_memc3_infrastructure_inst_clk_2x_0_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_0_0&quot; TS_clk_wiz_v1_6_50x200_clkfx /         2 HIGH 50%;" type="child" depth="2" requirement="2.500" prefType="period" actual="1.499" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk0_bufg_in_0" fullName="TS_memc3_infrastructure_inst_clk0_bufg_in_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk0_bufg_in_0&quot;         TS_clk_wiz_v1_6_50x200_clkfx HIGH 50%;" type="child" depth="2" requirement="5.000" prefType="period" actual="4.948" actualRollup="N/A" errors="14" errorRollup="0" items="994" itemsRollup="0"/><twConstRollup name="TS_clk_wiz_v1_6_50x62x312_clkout1" fullName="TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout1&quot; TS_xtalclk / 6.25 HIGH 50%;" type="child" depth="1" requirement="3.200" prefType="period" actual="2.708" actualRollup="N/A" errors="0" errorRollup="0" items="133" itemsRollup="0"/><twConstRollup name="TS_clk_wiz_v1_6_50x62x312_clkout0" fullName="TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIOD TIMEGRP         &quot;clk_wiz_v1_6_50x62x312_clkout0&quot; TS_xtalclk / 1.25 HIGH 50%;" type="child" depth="1" requirement="16.000" prefType="period" actual="9.891" actualRollup="N/A" errors="0" errorRollup="0" items="21736" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="2" anchorID="263"><twConstRollup name="TS_GTPCLKOUT1_0_" fullName="TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP &quot;GTPCLKOUT1&lt;0&gt;&quot; 180 MHz HIGH 50%;" type="origin" depth="0" requirement="5.556" prefType="period" actual="1.904" actualRollup="6.400" errors="0" errorRollup="1" items="0" itemsRollup="12509"/><twConstRollup name="TS_GTPCLKOUT1_DCM" fullName="TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP &quot;GTPCLKOUT1_DCM&quot; TS_GTPCLKOUT1_0_ HIGH 50%;" type="child" depth="1" requirement="5.556" prefType="period" actual="6.400" actualRollup="N/A" errors="1" errorRollup="0" items="12509" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="4" anchorID="264"><twConstRollup name="TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_" fullName="TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ = PERIOD TIMEGRP         &quot;inst_sp6wrap/eptest_i/gt_refclk_out&lt;0&gt;&quot; 8 ns HIGH 50%;" type="origin" depth="0" requirement="8.000" prefType="period" actual="1.904" actualRollup="10.000" errors="0" errorRollup="2" items="0" itemsRollup="9459"/><twConstRollup name="TS_inst_sp6wrap_eptest_i_gt_refclk_buf" fullName="TS_inst_sp6wrap_eptest_i_gt_refclk_buf = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_gt_refclk_buf&quot;         TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ HIGH 50%;" type="child" depth="1" requirement="8.000" prefType="period" actual="3.334" actualRollup="10.000" errors="0" errorRollup="2" items="0" itemsRollup="9459"/><twConstRollup name="TS_inst_sp6wrap_eptest_i_clk_125" fullName="TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_125&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf         / 1.25 HIGH 50%;" type="child" depth="2" requirement="6.400" prefType="period" actual="8.000" actualRollup="N/A" errors="1" errorRollup="0" items="45" itemsRollup="0"/><twConstRollup name="TS_inst_sp6wrap_eptest_i_clk_250" fullName="TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_250&quot; TS_inst_sp6wrap_eptest_i_gt_refclk_buf         / 2.5 HIGH 50%;" type="child" depth="2" requirement="3.200" prefType="period" actual="3.200" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_inst_sp6wrap_eptest_i_clk_62_5" fullName="TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIOD TIMEGRP         &quot;inst_sp6wrap_eptest_i_clk_62_5&quot;         TS_inst_sp6wrap_eptest_i_gt_refclk_buf / 0.625 HIGH 50%;" type="child" depth="2" requirement="12.800" prefType="period" actual="16.000" actualRollup="N/A" errors="1" errorRollup="0" items="9414" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="5" anchorID="265"><twConstRollup name="TS_DP_CLK1" fullName="TS_DP_CLK1 = PERIOD TIMEGRP &quot;DP_CLK1&quot; 27 MHz HIGH 50%;" type="origin" depth="0" requirement="37.037" prefType="period" actual="16.000" actualRollup="19.200" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_ctm_27x162_clkfx" fullName="TS_ctm_27x162_clkfx = PERIOD TIMEGRP &quot;ctm_27x162_clkfx&quot; TS_DP_CLK1 * 6 HIGH         50%;" type="child" depth="1" requirement="6.173" prefType="period" actual="3.200" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twConstRollupTable uID="7" anchorID="266"><twConstRollup name="TS_SYS_CLK3" fullName="TS_SYS_CLK3 = PERIOD TIMEGRP &quot;SYS_CLK3&quot; 5 ns HIGH 50%;" type="origin" depth="0" requirement="5.000" prefType="period" actual="2.800" actualRollup="3.570" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in" fullName="TS_memc3_infrastructure_inst_mcb_drp_clk_bufg_in = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_mcb_drp_clk_bufg_in&quot; TS_SYS_CLK3 / 0.25         HIGH 50%;" type="child" depth="1" requirement="20.000" prefType="period" actual="2.270" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk_2x_180" fullName="TS_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_180&quot; TS_SYS_CLK3 / 2 PHASE 1.25 ns         HIGH 50%;" type="child" depth="1" requirement="2.500" prefType="period" actual="1.499" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk_2x_0" fullName="TS_memc3_infrastructure_inst_clk_2x_0 = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk_2x_0&quot; TS_SYS_CLK3 / 2 HIGH 50%;" type="child" depth="1" requirement="2.500" prefType="period" actual="1.499" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/><twConstRollup name="TS_memc3_infrastructure_inst_clk0_bufg_in" fullName="TS_memc3_infrastructure_inst_clk0_bufg_in = PERIOD TIMEGRP         &quot;memc3_infrastructure_inst_clk0_bufg_in&quot; TS_SYS_CLK3 HIGH 50%;" type="child" depth="1" requirement="5.000" prefType="period" actual="3.570" actualRollup="N/A" errors="0" errorRollup="0" items="0" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="267">4</twUnmetConstCnt><twDataSheet anchorID="268" twNameLen="15"><twClk2SUList anchorID="269" twDestWidth="7"><twDest>DP_CLK0</twDest><twClk2SU><twSrc>DP_CLK0</twSrc><twRiseRise>6.578</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="270" twDestWidth="7"><twDest>xtalclk</twDest><twClk2SU><twSrc>xtalclk</twSrc><twRiseRise>10.554</twRiseRise><twRiseFall>1.354</twRiseFall></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="271"><twErrCnt>17</twErrCnt><twScore>102808</twScore><twSetupScore>0</twSetupScore><twHoldScore>97163</twHoldScore><twPinLimitScore>5645</twPinLimitScore><twConstCov><twPathCnt>78171</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>18283</twConnCnt></twConstCov><twStats anchorID="272"><twMinPer>16.000</twMinPer><twFootnote number="1" /><twMaxFreq>62.500</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>SAT 12 NOV 13:23:23 2011 </twTimestamp></twFoot><twClientInfo anchorID="273"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 209 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
