Release 12.2 Map M.63c (nt)
Xilinx Mapping Report File for Design 'exp6t_disp'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -xe n -t 1 -xt 0
-register_duplication on -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o
exp6t_disp_map.ncd exp6t_disp.ngd exp6t_disp.pcf 
Target Device  : xc6slx45t
Target Package : fgg484
Target Speed   : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date    : SAT 12 NOV 14:7:14 2011

Design Summary
--------------
Number of errors:      0
Number of warnings:   70
Slice Logic Utilization:
  Number of Slice Registers:                 3,435 out of  54,576    6%
    Number used as Flip Flops:               3,433
    Number used as Latches:                      0
    Number used as Latch-thrus:                  2
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      3,931 out of  27,288   14%
    Number used as logic:                    3,816 out of  27,288   13%
      Number using O6 output only:           3,589
      Number using O5 output only:             161
      Number using O5 and O6:                   66
      Number used as ROM:                        0
    Number used as Memory:                      37 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:            37
        Number using O6 output only:            17
        Number using O5 output only:             0
        Number using O5 and O6:                 20
    Number used exclusively as route-thrus:     78
      Number with same-slice register load:     54
      Number with same-slice carry load:        24
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 1,395 out of   6,822   20%
  Number of LUT Flip Flop pairs used:        4,391
    Number with an unused Flip Flop:         1,080 out of   4,391   24%
    Number with an unused LUT:                 460 out of   4,391   10%
    Number of fully used LUT-FF pairs:       2,851 out of   4,391   64%
    Number of unique control sets:             103
    Number of slice register sites lost
      to control set restrictions:             326 out of  54,576    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       160 out of     296   54%
    Number of LOCed IOBs:                      160 out of     160  100%
    IOB Flip Flops:                              5
    IOB Master Pads:                             5
    IOB Slave Pads:                              5
    Number of bonded IPADs:                     10 out of      16   62%
    Number of bonded OPADs:                      6 out of       8   75%

Specific Feature Utilization:
  Number of RAMB16BWERs:                        11 out of     116    9%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 2 out of      32    6%
    Number used as BUFIO2s:                      2
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                      15 out of      16   93%
    Number used as BUFGs:                       15
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     2 out of       8   25%
    Number used as DCMs:                         2
    Number used as DCM_CLKGENs:                  0
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:        24 out of     376    6%
    Number used as IODELAY2s:                    0
    Number used as IODRP2s:                      2
    Number used as IODRP2_MCBs:                 22
  Number of OLOGIC2/OSERDES2s:                  49 out of     376   13%
    Number used as OLOGIC2s:                     5
    Number used as OSERDES2s:                   44
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         1 out of       4   25%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of GTPA1_DUALs:                         2 out of       2  100%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                1 out of       2   50%
  Number of PCIE_A1s:                            1 out of       1  100%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            3 out of       4   75%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                3.92

Peak Memory Usage:  342 MB
Total REAL time to MAP completion:  4 mins 
Total CPU time to MAP completion (all processors):   4 mins 4 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:Xst:387 - The KEEP property attached to the net
   <memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_0> may hinder
   timing optimization.
   You may achieve better results by removing this property
WARNING:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
   constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
   (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
   alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
   components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
   environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.


   For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE,
   consult the Xilinx Command Line Tools User Guide "TRACE" chapter.
WARNING:Place:1137 - This design is not guaranteed to be routable! This design
   contains a global buffer instance, <clk_wiz_v1_6_50x62x312/clkout1_buf>,
   driving the net, <CLK63>, that is driving the following (first 30) non-clock
   source pins.
   < PIN: tx_dvi/tx_req_r_0.D; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. Please pay extra attention to the timing and routing of this path to
   ensure the design goals are met. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <clk_wiz_v1_6_50x62x312/clkout1_buf.O> allowing your design to continue. This
   constraint disables all clock placer rules related to the specified COMP.PIN.
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock
   IOB / BUFGMUX site pair. The clock IOB component <xtalclk> is placed at site <PAD206>. The corresponding BUFG
   component <clk_wiz_v1_6_50x200/clkin1_buf> is placed at site <BUFGMUX_X3Y14>. There is only a select set of IOBs that
   can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem
   exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <xtalclk.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the
   specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is
   recommended that this error condition be corrected in the design.
WARNING:PhysDesignRules:367 - The signal <TMDS_CEC_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_HPD_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_SDA_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <TMDS_SCL_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<0>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<1>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<2>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<3>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<4>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<5>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<6>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<7>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<8>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<9>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGA_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGB_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FLAGC_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<10>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<11>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<12>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<13>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<14>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_FD<15>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <USB_CLKOUT_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <CFG_RESET_N_IBUF> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<10>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<11>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<12>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<20>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<13>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<21>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<14>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<22>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<15>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<23>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<16>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<24>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<17>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<25>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<26>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<18>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<27>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<19>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<28>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<29>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <CFG_RESET_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <dipsw<0>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <dipsw<1>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <dipsw<2>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <dipsw<3>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<0>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<1>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<2>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<3>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<4>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<5>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<6>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<7>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<8>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <GPIO9C<9>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <pushsw<0>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <pushsw<1>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <pushsw<2>_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <CFG_MISO_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DP_RSV1_IBUF> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal <DP_RSV2_IBUF> is incomplete. The signal does not drive any load pins in the
   design.

Section 3 - Informational
-------------------------
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
   supports the use of up to 2 processors. Based on the the user options and
   machine load, Map will use 2 processors during this run.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:Xst:2261 - The FF/Latch <tx_dvi/enc2/st0_abort_r> in Unit <exp6t_disp> is
   equivalent to the following 4 FFs/Latches, which will be removed :
   <tx_dvi/enc2/st0_qm_r_9> <tx_dvi/enc1/st0_abort_r> <tx_dvi/enc1/st0_qm_r_9>
   <tx_dvi/enc0/st0_abort_r> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_crtc/disp_reg_dclk_r> in Unit
   <exp6t_disp> is equivalent to the following FF/Latch, which will be removed :
   <dp_main/dp_main_scramble/sc_tr_data_out_r_3> 
INFO:Xst:2261 - The FF/Latch <crtc2/mem_init_done_r> in Unit <exp6t_disp> is
   equivalent to the following FF/Latch, which will be removed :
   <crtc1/mem_init_done_r> 
INFO:Xst:2261 - The FF/Latch <crtc2/mem_cmd_addr_pre_r> in Unit <exp6t_disp> is
   equivalent to the following FF/Latch, which will be removed :
   <crtc1/mem_cmd_addr_pre_r> 
INFO:Xst:2261 - The FF/Latch
   <memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibr
   ation_top_inst/mcb_soft_calibration_inst/Pre_SYSRST> in Unit <exp6t_disp> is
   equivalent to the following 2 FFs/Latches, which will be removed :
   <memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibr
   ation_top_inst/mcb_soft_calibration_inst/Pre_SYSRST_1>
   <memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibr
   ation_top_inst/mcb_soft_calibration_inst/Pre_SYSRST_2> 
INFO:Xst:2261 - The FF/Latch <dp_main/dp_main_linkup/aux_cmd_code_r_32> in Unit
   <exp6t_disp> is equivalent to the following 3 FFs/Latches, which will be
   removed : <dp_main/dp_main_linkup/aux_cmd_code_r_33>
   <dp_main/dp_main_linkup/aux_cmd_code_r_34>
   <dp_main/dp_main_linkup/aux_cmd_code_r_35> 
INFO:LIT:243 - Logical network dipsw<3>_IBUF has no load.
INFO:LIT:395 - The above info message is repeated 183 more times for the
   following (max. 5 shown):
   dipsw<2>_IBUF,
   dipsw<1>_IBUF,
   dipsw<0>_IBUF,
   pushsw<2>_IBUF,
   pushsw<1>_IBUF
   To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:854 - One or more Dual Data Rate register has been found in the
   design.  All instances have been converted from the Virtex-II based primitive
   (with two clocks) to the Virtex-5 based primitive (with one clock) because
   the C0 and C1 clocks have been confirmed to be 180 degrees out of phase, or
   environment variable XIL_MAP_ALWAYS_RETARGET_FDDR was set in which case map
   does not confirm C0 and C1 clocks to be 180 degrees out of phase.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx
   Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
INFO:Pack:1650 - Map created a placed design.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
   the DCM comp clk_wiz_v1_6_50x200/dcm_sp_inst, consult the device Data Sheet.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
   the DCM comp ctm_27x162/dcm_sp_inst, consult the device Data Sheet.

Section 4 - Removed Logic Summary
---------------------------------
 120 block(s) removed
   2 block(s) optimized away
 119 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_1" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_2"
(ROM) removed.
  The signal "][2475_290" is loadless and has been removed.
   Loadless block "][2475_290" (ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_2" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_3"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_3" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_4"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_4" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_5"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_5" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_6"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_6" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_7"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_7" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_8"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_8" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_9"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_9" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_10"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_10" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_11"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_11" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_12"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_12" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_13"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_13" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_14"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_14" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_15"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_15" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_16"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_16" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_17"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_17" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_18"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_18" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_19"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_19" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_20"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_20" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_21"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_21" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_22"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_22" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_23"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_23" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_24"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_24" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_25"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_25" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_26"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_26" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_27"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_27" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_28"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_28" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_29"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_29" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_30"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_30" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_31"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_31" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_32"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_32" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_33"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_33" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_34"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_34" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_35"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_35" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_36"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_36" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_37"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_37" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_38"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_38" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_39"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_39" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_40"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_40" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_41"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_41" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_42"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_42" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_43"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_43" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_44"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_44" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_45"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_45" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_46"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_46" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_47"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_47" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_48"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_48" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_49"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_49" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_50"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_50" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_51"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_51" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_52"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_52" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_53"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_53" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_54"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_54" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_55"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_55" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_56"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_56" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_57"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_57" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_58"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_58" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_59"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_59" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_60"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_60" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_61"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_61" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_62"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_62" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_63"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_63" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_64"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_64" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_65"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_65" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_66"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_66" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_67"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_67" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_68"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_68" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_69"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_69" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_70"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_70" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_71"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_71" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_72"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_72" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_73"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_73" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_74"
(ROM) removed.
The signal "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst_74" is
loadless and has been removed.
 Loadless block "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1_75"
(ROM) removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_udqs_iobufds.iob_udqs/N2" is
sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_udqs_iobufds.iob_udqs/N3" is
sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dqs_iobufds.iob_dqs/N2" is
sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dqs_iobufds.iob_dqs/N3" is
sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[14].gen_iob_dq_inst
/N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[14].gen_iob_dq_inst
/N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[15].gen_iob_dq_inst
/N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[15].gen_iob_dq_inst
/N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[12].gen_iob_dq_inst
/N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[12].gen_iob_dq_inst
/N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[13].gen_iob_dq_inst
/N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[13].gen_iob_dq_inst
/N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[10].gen_iob_dq_inst
/N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[10].gen_iob_dq_inst
/N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[11].gen_iob_dq_inst
/N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[11].gen_iob_dq_inst
/N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[8].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[8].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[9].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[9].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[0].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[0].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[1].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[1].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[2].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[2].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[3].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[3].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[6].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[6].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[7].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[7].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[4].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[4].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[5].gen_iob_dq_inst/
N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[5].gen_iob_dq_inst/
N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibrati
on_top_inst/gen_zio.IOBUF_ZIO/N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibrati
on_top_inst/gen_zio.IOBUF_ZIO/N3" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibrati
on_top_inst/IOBUF_RZQ/N2" is sourceless and has been removed.
The signal
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibrati
on_top_inst/IOBUF_RZQ/N3" is sourceless and has been removed.
The signal "clk_wiz_v1_6_50x62x312/pll_base_inst/N2" is sourceless and has been
removed.
The signal "clk_wiz_v1_6_50x62x312/pll_base_inst/N3" is sourceless and has been
removed.
The signal "inst_sp6wrap/eptest_i/pll_base_i/N2" is sourceless and has been
removed.
The signal "inst_sp6wrap/eptest_i/pll_base_i/N3" is sourceless and has been
removed.
Unused block "USB_RESET_PULLUP" (PULLUP) removed.
Unused block "clk_wiz_v1_6_50x62x312/pll_base_inst/XST_GND" (ZERO) removed.
Unused block "clk_wiz_v1_6_50x62x312/pll_base_inst/XST_VCC" (ONE) removed.
Unused block "inst_sp6wrap/eptest_i/pll_base_i/XST_GND" (ZERO) removed.
Unused block "inst_sp6wrap/eptest_i/pll_base_i/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[0].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[0].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[10].gen_iob_dq_inst
/XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[10].gen_iob_dq_inst
/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[11].gen_iob_dq_inst
/XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[11].gen_iob_dq_inst
/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[12].gen_iob_dq_inst
/XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[12].gen_iob_dq_inst
/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[13].gen_iob_dq_inst
/XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[13].gen_iob_dq_inst
/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[14].gen_iob_dq_inst
/XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[14].gen_iob_dq_inst
/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[15].gen_iob_dq_inst
/XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[15].gen_iob_dq_inst
/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[1].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[1].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[2].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[2].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[3].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[3].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[4].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[4].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[5].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[5].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[6].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[6].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[7].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[7].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[8].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[8].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[9].gen_iob_dq_inst/
XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dq_iobuft[9].gen_iob_dq_inst/
XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dqs_iobufds.iob_dqs/XST_GND"
(ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_dqs_iobufds.iob_dqs/XST_VCC"
(ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibrati
on_top_inst/IOBUF_RZQ/XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibrati
on_top_inst/IOBUF_RZQ/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibrati
on_top_inst/gen_zio.IOBUF_ZIO/XST_GND" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibrati
on_top_inst/gen_zio.IOBUF_ZIO/XST_VCC" (ONE) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_udqs_iobufds.iob_udqs/XST_GND
" (ZERO) removed.
Unused block
"memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_udqs_iobufds.iob_udqs/XST_VCC
" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 11 - Timing Report
--------------------------
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:3284 - This timing report was generated using estimated delay 
   information.  For accurate numbers, please refer to the post Place and Route 
   timing report.
Number of Timing Constraints that were not applied: 16

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
* TS_inst_sp6wrap_eptest_i_clk_62_5 = PERIO | SETUP       |     8.865ns|     3.935ns|       0|           0
  D TIMEGRP "inst_sp6wrap_eptest_i_clk_62_5 | HOLD        |    -0.652ns|            |     107|       27917
  " TS_inst_sp6wrap_eptest_i_gt_refclk_buf  | MINPERIOD   |    -3.200ns|    16.000ns|       1|        3200
  / 0.625 HIGH 50%                          |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_inst_sp6wrap_eptest_i_clk_125 = PERIOD | SETUP       |     3.647ns|     2.753ns|       0|           0
   TIMEGRP "inst_sp6wrap_eptest_i_clk_125"  | HOLD        |    -0.285ns|            |      22|        6270
  TS_inst_sp6wrap_eptest_i_gt_refclk_buf /  | MINPERIOD   |    -1.600ns|     8.000ns|       1|        1600
  1.25 HIGH 50%                             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_GTPCLKOUT1_DCM = PERIOD TIMEGRP "GTPCL | SETUP       |     3.664ns|     2.508ns|       0|           0
  KOUT1_DCM" TS_GTPCLKOUT1_0_ HIGH 50%      | HOLD        |    -0.595ns|            |      11|        6545
                                            | MINPERIOD   |    -0.228ns|     6.400ns|       1|         228
----------------------------------------------------------------------------------------------------------
* TS_memc3_infrastructure_inst_clk0_bufg_in | SETUP       |     0.847ns|     3.076ns|       0|           0
  _0 = PERIOD TIMEGRP "memc3_infrastructure | HOLD        |    -0.098ns|            |      14|        1372
  _inst_clk0_bufg_in_0" TS_clk_wiz_v1_6_50x | MINPERIOD   |     1.430ns|     3.570ns|       0|           0
  200_clkfx HIGH 50%                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
* TS_clk_wiz_v1_6_50x62x312_clkout1 = PERIO | SETUP       |     0.392ns|     2.416ns|       0|           0
  D TIMEGRP "clk_wiz_v1_6_50x62x312_clkout1 | HOLD        |    -0.015ns|            |      30|         450
  " TS_xtalclk / 6.25 HIGH 50%              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_inst_sp6wrap_eptest_i_clk_250 = PERIOD | MINPERIOD   |     0.000ns|     3.200ns|       0|           0
   TIMEGRP "inst_sp6wrap_eptest_i_clk_250"  |             |            |            |        |            
  TS_inst_sp6wrap_eptest_i_gt_refclk_buf /  |             |            |            |        |            
  2.5 HIGH 50%                              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk_2x_0_0 = | MINPERIOD   |     1.001ns|     1.499ns|       0|           0
   PERIOD TIMEGRP "memc3_infrastructure_ins |             |            |            |        |            
  t_clk_2x_0_0" TS_clk_wiz_v1_6_50x200_clkf |             |            |            |        |            
  x / 2 HIGH 50%                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk_2x_180_0 | MINPERIOD   |     1.001ns|     1.499ns|       0|           0
   = PERIOD TIMEGRP "memc3_infrastructure_i |             |            |            |        |            
  nst_clk_2x_180_0" TS_clk_wiz_v1_6_50x200_ |             |            |            |        |            
  clkfx / 2 PHASE 1.25 ns HIGH 50%          |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk_2x_0 = P | MINPERIOD   |     1.001ns|     1.499ns|       0|           0
  ERIOD TIMEGRP "memc3_infrastructure_inst_ |             |            |            |        |            
  clk_2x_0" TS_SYS_CLK3 / 2 HIGH 50%        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk_2x_180 = | MINPERIOD   |     1.001ns|     1.499ns|       0|           0
   PERIOD TIMEGRP "memc3_infrastructure_ins |             |            |            |        |            
  t_clk_2x_180" TS_SYS_CLK3 / 2 PHASE 1.25  |             |            |            |        |            
  ns HIGH 50%                               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_clk0_bufg_in | MINPERIOD   |     1.430ns|     3.570ns|       0|           0
   = PERIOD TIMEGRP "memc3_infrastructure_i |             |            |            |        |            
  nst_clk0_bufg_in" TS_SYS_CLK3 HIGH 50%    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 5 | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
   ns HIGH 50%                              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_wiz_v1_6_50x200_clkfx = PERIOD TIM | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
  EGRP "clk_wiz_v1_6_50x200_clkfx" TS_xtalc |             |            |            |        |            
  lk / 4 HIGH 50%                           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_inst_sp6wrap_eptest_i_gt_refclk_buf =  | MINLOWPULSE |     4.666ns|     3.334ns|       0|           0
  PERIOD TIMEGRP "inst_sp6wrap_eptest_i_gt_ |             |            |            |        |            
  refclk_buf" TS_inst_sp6wrap_eptest_i_gt_r |             |            |            |        |            
  efclk_out_0_ HIGH 50%                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_xtalclk = PERIOD TIMEGRP "xtalclk" 20  | MINLOWPULSE |    12.000ns|     8.000ns|       0|           0
  ns HIGH 50%                               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ctm_27x162_clkfx = PERIOD TIMEGRP "ctm | MINPERIOD   |     2.972ns|     3.200ns|       0|           0
  _27x162_clkfx" TS_DP_CLK1 * 6 HIGH 50%    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_mcb_drp_clk_ | SETUP       |     3.447ns|     6.212ns|       0|           0
  bufg_in_0 = PERIOD TIMEGRP "memc3_infrast | HOLD        |     0.071ns|            |       0|           0
  ructure_inst_mcb_drp_clk_bufg_in_0" TS_cl |             |            |            |        |            
  k_wiz_v1_6_50x200_clkfx / 0.25 HIGH 50%   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_DP_CLK1 = PERIOD TIMEGRP "DP_CLK1" 27  | MINLOWPULSE |    21.036ns|    16.000ns|       0|           0
  MHz HIGH 50%                              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_GTPCLKOUT1_0_ = PERIOD TIMEGRP "GTPCLK | MINPERIOD   |     4.268ns|     1.904ns|       0|           0
  OUT1<0>" 162 MHz HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_ | MINPERIOD   |     6.096ns|     1.904ns|       0|           0
   = PERIOD TIMEGRP "inst_sp6wrap/eptest_i/ |             |            |            |        |            
  gt_refclk_out<0>" 8 ns HIGH 50%           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_epcie_refclkn = PERIOD TIMEGRP "epcie_ | MINPERIOD   |     6.800ns|     3.200ns|       0|           0
  refclkn" 100 MHz HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clk_wiz_v1_6_50x62x312_clkout0 = PERIO | SETUP       |    13.550ns|     2.450ns|       0|           0
  D TIMEGRP "clk_wiz_v1_6_50x62x312_clkout0 | HOLD        |     0.013ns|            |       0|           0
  " TS_xtalclk / 1.25 HIGH 50%              | MINPERIOD   |    12.430ns|     3.570ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TS_memc3_infrastructure_inst_mcb_drp_clk_ | MINPERIOD   |    17.730ns|     2.270ns|       0|           0
  bufg_in = PERIOD TIMEGRP "memc3_infrastru |             |            |            |        |            
  cture_inst_mcb_drp_clk_bufg_in" TS_SYS_CL |             |            |            |        |            
  K3 / 0.25 HIGH 50%                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_DP_CLK0 = PERIOD TIMEGRP "DP_CLK0" 27  | SETUP       |    34.925ns|     2.112ns|       0|           0
  MHz HIGH 50%                              | HOLD        |     0.257ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_xtalclk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_xtalclk                     |     20.000ns|      8.000ns|     15.100ns|            0|           44|            0|        53993|
| TS_clk_wiz_v1_6_50x200_clkfx  |      5.000ns|      2.800ns|      3.570ns|            0|           14|            0|        31362|
|  TS_memc3_infrastructure_inst_|     20.000ns|      6.212ns|          N/A|            0|            0|        30415|            0|
|  mcb_drp_clk_bufg_in_0        |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  clk_2x_180_0                 |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  clk_2x_0_0                   |             |             |             |             |             |             |             |
|  TS_memc3_infrastructure_inst_|      5.000ns|      3.570ns|          N/A|           14|            0|          947|            0|
|  clk0_bufg_in_0               |             |             |             |             |             |             |             |
| TS_clk_wiz_v1_6_50x62x312_clko|      3.200ns|      2.416ns|          N/A|           30|            0|          133|            0|
| ut1                           |             |             |             |             |             |             |             |
| TS_clk_wiz_v1_6_50x62x312_clko|     16.000ns|      3.570ns|          N/A|            0|            0|        22498|            0|
| ut0                           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_GTPCLKOUT1_0_
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_GTPCLKOUT1_0_               |      6.173ns|      1.904ns|      6.400ns|            0|           12|            0|        12309|
| TS_GTPCLKOUT1_DCM             |      6.173ns|      6.400ns|          N/A|           12|            0|        12309|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_inst_sp6wrap_eptest_i_gt_refclk_out_0_
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_inst_sp6wrap_eptest_i_gt_ref|      8.000ns|      1.904ns|     10.000ns|            0|          131|            0|         9420|
|clk_out_0_                     |             |             |             |             |             |             |             |
| TS_inst_sp6wrap_eptest_i_gt_re|      8.000ns|      3.334ns|     10.000ns|            0|          131|            0|         9420|
| fclk_buf                      |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|      6.400ns|      8.000ns|          N/A|           23|            0|           45|            0|
|  125                          |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|      3.200ns|      3.200ns|          N/A|            0|            0|            0|            0|
|  250                          |             |             |             |             |             |             |             |
|  TS_inst_sp6wrap_eptest_i_clk_|     12.800ns|     16.000ns|          N/A|          108|            0|         9375|            0|
|  62_5                         |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_DP_CLK1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_DP_CLK1                     |     37.037ns|     16.000ns|     19.200ns|            0|            0|            0|            0|
| TS_ctm_27x162_clkfx           |      6.173ns|      3.200ns|          N/A|            0|            0|            0|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_SYS_CLK3
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK3                    |      5.000ns|      2.800ns|      3.570ns|            0|            0|            0|            0|
| TS_memc3_infrastructure_inst_m|     20.000ns|      2.270ns|          N/A|            0|            0|            0|            0|
| cb_drp_clk_bufg_in            |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
| lk_2x_180                     |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      2.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
| lk_2x_0                       |             |             |             |             |             |             |             |
| TS_memc3_infrastructure_inst_c|      5.000ns|      3.570ns|          N/A|            0|            0|            0|            0|
| lk0_bufg_in                   |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

5 constraints not met.



Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| CFG_CCLK                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| CFG_CSO                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| CFG_MISO                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| CFG_MOSI                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| CFG_RESET                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| CFG_RESET_N                        | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_AUXO_N                          | IOBS             | OUTPUT    | LVDS_33              |       |          |      |              |          |          |
| DP_AUXO_P                          | IOBM             | OUTPUT    | LVDS_33              |       |          |      |              |          |          |
| DP_AUX_N                           | IOB              | INPUT     | LVDS_33              | TRUE  |          |      |              |          |          |
| DP_AUX_P                           | IOB              | INPUT     | LVDS_33              | TRUE  |          |      |              |          |          |
| DP_CLK0                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_CLK1                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_HPD                             | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_RST_N                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_RSV1                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| DP_RSV2                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO1C<22>                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW | ODDR         |          |          |
| GPIO1C<23>                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| GPIO1C<24>                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| GPIO1C<25>                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| GPIO1C<26>                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| GPIO1C<27>                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| GPIO1C<28>                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| GPIO1C<29>                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| GPIO9C<0>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<1>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<2>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<3>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<4>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<5>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<6>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<7>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<8>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<9>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<10>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<11>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<12>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<13>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<14>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<15>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<16>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<17>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<18>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<19>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<20>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<21>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<22>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<23>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<24>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<25>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<26>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<27>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<28>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| GPIO9C<29>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| TMDS_CEC                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| TMDS_CH0_N                         | IOBS             | OUTPUT    | TMDS_33              |       |          |      |              |          |          |
| TMDS_CH0_P                         | IOBM             | OUTPUT    | TMDS_33              |       |          |      | ODDR         |          |          |
| TMDS_CH1_N                         | IOBS             | OUTPUT    | TMDS_33              |       |          |      |              |          |          |
| TMDS_CH1_P                         | IOBM             | OUTPUT    | TMDS_33              |       |          |      | ODDR         |          |          |
| TMDS_CH2_N                         | IOBS             | OUTPUT    | TMDS_33              |       |          |      |              |          |          |
| TMDS_CH2_P                         | IOBM             | OUTPUT    | TMDS_33              |       |          |      | ODDR         |          |          |
| TMDS_CLK_N                         | IOBS             | OUTPUT    | TMDS_33              |       |          |      |              |          |          |
| TMDS_CLK_P                         | IOBM             | OUTPUT    | TMDS_33              |       |          |      | ODDR         |          |          |
| TMDS_HPD                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| TMDS_SCL                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| TMDS_SDA                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_CLKOUT                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<0>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<1>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<2>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<3>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<4>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<5>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<6>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<7>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<8>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<9>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<10>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<11>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<12>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<13>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<14>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FD<15>                         | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FIFOADR<0>                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_FIFOADR<1>                     | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_FLAGA                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FLAGB                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_FLAGC                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| USB_IFCLK                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_PKTEND                         | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_RESET                          | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_SLOE                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_SLRD                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| USB_SLWR                           | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| dipsw<0>                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| dipsw<1>                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| dipsw<2>                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| dipsw<3>                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| epcie_perst                        | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| epcie_refclkn                      | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| epcie_refclkp                      | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| epcie_rxn                          | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| epcie_rxp                          | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| epcie_txn                          | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| epcie_txp                          | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| epcie_wake                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| led<0>                             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led<1>                             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led<2>                             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led<3>                             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led<4>                             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led<5>                             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led<6>                             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| led<7>                             | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| mcb3_dram_a<0>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<1>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<2>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<3>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<4>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<5>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<6>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<7>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<8>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<9>                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<10>                    | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<11>                    | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_a<12>                    | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_ba2                      | IOB              | OUTPUT    | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_ba<0>                    | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_ba<1>                    | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_cas_n                    | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_ck                       | IOB              | OUTPUT    | DIFF_SSTL18_II       |       |          |      | OSERDES      |          |          |
| mcb3_dram_ck_n                     | IOB              | OUTPUT    | DIFF_SSTL18_II       |       |          |      | OSERDES      |          |          |
| mcb3_dram_cke                      | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_dm                       | IOB              | OUTPUT    | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<0>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<1>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<2>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<3>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<4>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<5>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<6>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<7>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<8>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<9>                    | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<10>                   | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<11>                   | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<12>                   | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<13>                   | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<14>                   | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dq<15>                   | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_dqs                      | IOB              | BIDIR     | DIFF_SSTL18_II       |       |          |      |              | PULLDOWN |          |
| mcb3_dram_dqs_n                    | IOB              | BIDIR     | DIFF_SSTL18_II       |       |          |      |              | PULLUP   |          |
| mcb3_dram_odt                      | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_ras_n                    | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_dram_udm                      | IOB              | OUTPUT    | SSTL18_II            |       |          |      |              |          |          |
| mcb3_dram_udqs                     | IOB              | BIDIR     | DIFF_SSTL18_II       |       |          |      |              | PULLDOWN |          |
| mcb3_dram_udqs_n                   | IOB              | BIDIR     | DIFF_SSTL18_II       |       |          |      |              | PULLUP   |          |
| mcb3_dram_we_n                     | IOB              | OUTPUT    | SSTL18_II            |       |          |      | OSERDES      |          |          |
| mcb3_rzq                           | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| mcb3_zio                           | IOB              | BIDIR     | SSTL18_II            |       |          |      |              |          |          |
| pushsw<0>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| pushsw<1>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| pushsw<2>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| pushsw<3>                          | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| sata_refclkn                       | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_refclkp                       | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_rxn0                          | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_rxn1                          | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_rxp0                          | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_rxp1                          | IPAD             | INPUT     |                      |       |          |      |              |          |          |
| sata_txn0                          | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| sata_txn1                          | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| sata_txp0                          | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| sata_txp1                          | OPAD             | OUTPUT    |                      |       |          |      |              |          |          |
| xtalclk                            | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.

For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.

Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
