################################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 1.6
##  \   \         Application : Spartan-6 FPGA GTP Transceiver Wizard
##  /   /         Filename : xil_s6_gtpwizard_v1_6_dp_top.ucf
## /___/   /\     Timestamp :
## \   \  /  \ 
##  \___\/\___\
##
##
## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
## Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
##
## Device:  xc6slx45t
## Package: fgg484

################################## Clock Constraints ##########################


# User Clock Constraints
NET "tile0_txusrclk20_i" TNM_NET = "tile0_txusrclk20_i";
TIMESPEC "TS_tile0_txusrclk20_i" = PERIOD "tile0_txusrclk20_i" 6.667;

NET "tile0_txusrclk0_i" TNM_NET = "tile0_txusrclk0_i";
TIMESPEC "TS_tile0_txusrclk0_i" = PERIOD "tile0_txusrclk0_i" 3.333;

NET "tile0_rxusrclk20_i" TNM_NET = "tile0_rxusrclk20_i";
TIMESPEC "TS_tile0_rxusrclk20_i" = PERIOD "tile0_rxusrclk20_i" 6.667;

NET "tile0_rxusrclk0_i" TNM_NET = "tile0_rxusrclk0_i";
TIMESPEC "TS_tile0_rxusrclk0_i" = PERIOD "tile0_rxusrclk0_i" 3.333;

NET "tile0_txusrclk21_i" TNM_NET = "tile0_txusrclk21_i";
TIMESPEC "TS_tile0_txusrclk21_i" = PERIOD "tile0_txusrclk21_i" 7.407;

NET "tile0_txusrclk1_i" TNM_NET = "tile0_txusrclk1_i";
TIMESPEC "TS_tile0_txusrclk1_i" = PERIOD "tile0_txusrclk1_i" 3.704;

NET "tile0_rxusrclk21_i" TNM_NET = "tile0_rxusrclk21_i";
TIMESPEC "TS_tile0_rxusrclk21_i" = PERIOD "tile0_rxusrclk21_i" 7.407;

NET "tile0_rxusrclk1_i" TNM_NET = "tile0_rxusrclk1_i";
TIMESPEC "TS_tile0_rxusrclk1_i" = PERIOD "tile0_rxusrclk1_i" 3.704;




######################## locs for top level ports ######################


######################### mgt clock module constraints ########################

NET TILE0_GTP0_REFCLK_PAD_N_IN  LOC=B12;
NET TILE0_GTP0_REFCLK_PAD_P_IN  LOC=A12;
NET TILE0_GTP1_REFCLK_PAD_N_IN  LOC=F12;
NET TILE0_GTP1_REFCLK_PAD_P_IN  LOC=E12;

################################# mgt wrapper constraints #####################

##---------- Set placement for tile0_rocketio_wrapper_i/GTPA1_DUAL ------
INST xil_s6_gtpwizard_v1_6_dp_i/tile0_xil_s6_gtpwizard_v1_6_dp_i/gtpa1_dual_i LOC=GTPA1_DUAL_X1Y0;



