System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
Path C:\Xilinx\12.2\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.2\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.2\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.2\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.2\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.2\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.2\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.2\ISE_DS\common\bin\nt;
C:\Xilinx\12.2\ISE_DS\common\lib\nt;
C:\Xilinx\11.1\common\bin\nt;
C:\Program Files\ThinkPad\Utilities;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Diskeeper Corporation\Diskeeper\;
C:\Program Files\ThinkPad\ConnectUtilities;
C:\Program Files\Common Files\Lenovo;
C:\Program Files\Lenovo\Client Security Solution;
c:\altera\91sp2\quartus\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\altera\91sp2\modelsim_ase\win32aloem		 C:\Xilinx\12.2\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.2\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.2\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.2\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.2\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.2\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.2\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.2\ISE_DS\common\bin\nt;
C:\Xilinx\12.2\ISE_DS\common\lib\nt;
C:\Xilinx\11.1\common\bin\nt;
C:\Program Files\ThinkPad\Utilities;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Diskeeper Corporation\Diskeeper\;
C:\Program Files\ThinkPad\ConnectUtilities;
C:\Program Files\Common Files\Lenovo;
C:\Program Files\Lenovo\Client Security Solution;
c:\altera\91sp2\quartus\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\altera\91sp2\modelsim_ase\win32aloem		 C:\Xilinx\12.2\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.2\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.2\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.2\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.2\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.2\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.2\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.2\ISE_DS\common\bin\nt;
C:\Xilinx\12.2\ISE_DS\common\lib\nt;
C:\Xilinx\11.1\common\bin\nt;
C:\Program Files\ThinkPad\Utilities;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Diskeeper Corporation\Diskeeper\;
C:\Program Files\ThinkPad\ConnectUtilities;
C:\Program Files\Common Files\Lenovo;
C:\Program Files\Lenovo\Client Security Solution;
c:\altera\91sp2\quartus\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\altera\91sp2\modelsim_ase\win32aloem		 C:\Xilinx\12.2\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.2\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.2\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.2\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.2\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.2\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.2\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.2\ISE_DS\common\bin\nt;
C:\Xilinx\12.2\ISE_DS\common\lib\nt;
C:\Xilinx\11.1\common\bin\nt;
C:\Program Files\ThinkPad\Utilities;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Diskeeper Corporation\Diskeeper\;
C:\Program Files\ThinkPad\ConnectUtilities;
C:\Program Files\Common Files\Lenovo;
C:\Program Files\Lenovo\Client Security Solution;
c:\altera\91sp2\quartus\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\altera\91sp2\modelsim_ase\win32aloem
XILINX C:\Xilinx\12.2\ISE_DS\ISE\ C:\Xilinx\12.2\ISE_DS\ISE\ C:\Xilinx\12.2\ISE_DS\ISE\ C:\Xilinx\12.2\ISE_DS\ISE\
XILINX11_1 C:\Xilinx\11.1\ProgrammingTools C:\Xilinx\11.1\ProgrammingTools C:\Xilinx\11.1\ProgrammingTools C:\Xilinx\11.1\ProgrammingTools
XILINXD_LICENSE_FILE C:\Xilinx\Xilinx.lic C:\Xilinx\Xilinx.lic C:\Xilinx\Xilinx.lic C:\Xilinx\Xilinx.lic
XILINX_DSP C:\Xilinx\12.2\ISE_DS\ISE C:\Xilinx\12.2\ISE_DS\ISE C:\Xilinx\12.2\ISE_DS\ISE C:\Xilinx\12.2\ISE_DS\ISE
XILINX_EDK C:\Xilinx\12.2\ISE_DS\EDK C:\Xilinx\12.2\ISE_DS\EDK C:\Xilinx\12.2\ISE_DS\EDK C:\Xilinx\12.2\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\12.2\ISE_DS\PlanAhead C:\Xilinx\12.2\ISE_DS\PlanAhead C:\Xilinx\12.2\ISE_DS\PlanAhead C:\Xilinx\12.2\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   exp6t_disp.prj  
-ifmt   mixed Mixed
-ofn   exp6t_disp  
-ofmt   NGC NGC
-p   xc6slx45t-3-fgg484  
-top   exp6t_disp  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 2 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-lso Library Search Order "C:/PROJECT/EXP6T_PCIE3F/xise/exp6t_disp.lso"  
-keep_hierarchy Keep Hierarchy Soft No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-sd Cores Search Directories {".." }  
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   500 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   Yes No
-move_first_stage   YES Yes
-move_last_stage   YES Yes
-optimize_primitives   NO No
-use_clock_enable   Yes Auto
-use_sync_set   Yes Auto
-use_sync_reset   Yes Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc6slx45t-fgg484-3 None
-sd Macro Search Path .. None
-uc   C:/PROJECT/EXP6T_PCIE3F/exp6t_disp.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-xe Placer Extra Effort Map NORMAL  
-xt Extra Cost Tables 0 0
-global_opt Global Optimization map TRUE FALSE
-ir Use RLOC Constraints OFF OFF
-mt Enable Multi-Threading 2 0
-t Starting Placer Cost Table (1-100) Map 1 0
-equivalent_register_removal Equivalent Register Removal TRUE TRUE
-register_duplication Register Duplication Map TRUE FALSE
-intstyle   ise None
-lc LUT Combining off off
-o   exp6t_disp_map.ncd None
-w   true false
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc6slx45t-fgg484-3 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-xe   n None
-intstyle   ise  
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 CPU T7600 @ 2.33GHz/2326 MHz Intel(R) Core(TM)2 CPU T7600 @ 2.33GHz/2326 MHz Intel(R) Core(TM)2 CPU T7600 @ 2.33GHz/2326 MHz Intel(R) Core(TM)2 CPU T7600 @ 2.33GHz/2326 MHz
Host LENOVO-A29837C5 LENOVO-A29837C5 LENOVO-A29837C5 LENOVO-A29837C5
OS Name Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional
OS Release Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600)