| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
3,435 |
54,576 |
6% |
|
| Number used as Flip Flops |
3,433 |
|
|
|
| Number used as Latches |
0 |
|
|
|
| Number used as Latch-thrus |
2 |
|
|
|
| Number used as AND/OR logics |
0 |
|
|
|
| Number of Slice LUTs |
3,931 |
27,288 |
14% |
|
| Number used as logic |
3,816 |
27,288 |
13% |
|
| Number using O6 output only |
3,589 |
|
|
|
| Number using O5 output only |
161 |
|
|
|
| Number using O5 and O6 |
66 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
37 |
6,408 |
1% |
|
| Number used as Dual Port RAM |
0 |
|
|
|
| Number used as Single Port RAM |
0 |
|
|
|
| Number used as Shift Register |
37 |
|
|
|
| Number using O6 output only |
17 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
20 |
|
|
|
| Number used exclusively as route-thrus |
78 |
|
|
|
| Number with same-slice register load |
54 |
|
|
|
| Number with same-slice carry load |
24 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
1,395 |
6,822 |
20% |
|
| Number of LUT Flip Flop pairs used |
4,391 |
|
|
|
| Number with an unused Flip Flop |
1,080 |
4,391 |
24% |
|
| Number with an unused LUT |
460 |
4,391 |
10% |
|
| Number of fully used LUT-FF pairs |
2,851 |
4,391 |
64% |
|
| Number of unique control sets |
103 |
|
|
|
Number of slice register sites lost
to control set restrictions |
326 |
54,576 |
1% |
|
| Number of bonded IOBs |
160 |
296 |
54% |
|
| Number of LOCed IOBs |
160 |
160 |
100% |
|
| IOB Flip Flops |
5 |
|
|
|
| IOB Master Pads |
5 |
|
|
|
| IOB Slave Pads |
5 |
|
|
|
| Number of bonded IPADs |
10 |
16 |
62% |
|
| Number of bonded OPADs |
6 |
8 |
75% |
|
| Number of RAMB16BWERs |
11 |
116 |
9% |
|
| Number of RAMB8BWERs |
0 |
232 |
0% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
2 |
32 |
6% |
|
| Number used as BUFIO2s |
2 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
| Number of BUFG/BUFGMUXs |
15 |
16 |
93% |
|
| Number used as BUFGs |
15 |
|
|
|
| Number used as BUFGMUX |
0 |
|
|
|
| Number of DCM/DCM_CLKGENs |
2 |
8 |
25% |
|
| Number used as DCMs |
2 |
|
|
|
| Number used as DCM_CLKGENs |
0 |
|
|
|
| Number of ILOGIC2/ISERDES2s |
0 |
376 |
0% |
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
24 |
376 |
6% |
|
| Number used as IODELAY2s |
0 |
|
|
|
| Number used as IODRP2s |
2 |
|
|
|
| Number used as IODRP2_MCBs |
22 |
|
|
|
| Number of OLOGIC2/OSERDES2s |
49 |
376 |
13% |
|
| Number used as OLOGIC2s |
5 |
|
|
|
| Number used as OSERDES2s |
44 |
|
|
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHs |
0 |
256 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
1 |
4 |
25% |
|
| Number of DSP48A1s |
0 |
58 |
0% |
|
| Number of GTPA1_DUALs |
2 |
2 |
100% |
|
| Number of ICAPs |
0 |
1 |
0% |
|
| Number of MCBs |
1 |
2 |
50% |
|
| Number of PCIE_A1s |
1 |
1 |
100% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
3 |
4 |
75% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
3.92 |
|
|
|