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                 Template Project for MB9BF61xT
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                  (C) 2011 FUJITSU SEMICONDUCTOR LIMITED                
                                                                        
   The following software deliverable is intended for and must only be  
   used for reference and in an evaluation laboratory environment.      
   It is provided on an as-is basis without charge and is subject to    
   alterations.                                                         
   It is the user's obligation to fully test the software in its        
   environment and to ensure proper functionality, qualification and    
   compliance with component specifications.                            
                                                                        
   In the event the software deliverable includes the use of open       
   source components, the provisions of the governing open source       
   license agreement shall apply with respect to such software          
   deliverable.                                                         
   FUJITSU SEMICONDUCTOR LIMITED ("FSL")
   does not warrant that the deliverables do not infringe any       
   third party intellectual property right (IPR). In the event that     
   the deliverables infringe a third party IPR it is the sole           
   responsibility of the customer to obtain necessary licenses to       
   continue the usage of the deliverable.                               
                                                                        
   To the maximum extent permitted by applicable law FSL disclaims all  
   warranties, whether express or implied, in particular, but not       
   limited to, warranties of merchantability and fitness for a          
   particular purpose for which the deliverable is not designated.      
                                                                        
   To the maximum extent permitted by applicable law, FSL's liability   
   is restricted to intention and gross negligence.                     
   FSL is not liable for consequential damages.                         
 
   (V1.0)                                                    
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History
Date       Ver AE IAR    ARM   Description
2011-07-20 1.0 YI 6.20.0 4.20  Initial
2012-01-10 1.1 EH 6.21.1 4.20  - Template project unified for every pin count
                               - Bus clock setting of APB0-2 changed from 4
                                 division to 2 divison
2012-02-24 1.2 EH 6.21.1 4.20  Updated IO definition

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This is a project template for MB9BF61xT. It includes some
basic settings for e.g. Linker, C-Compiler.



Clock settings:
---------------
Crystal:  4 MHz
HCLK:   144 MHz
PCLK0:   72 MHz
PCLK1:   72 MHz
PCLK2:   72 MHz
