av6lx9_lcd Project Status
Project File: lcd.xise Parser Errors: No Errors
Module Name: av6lx9_lcd Implementation State: Programming File Generated
Target Device: xc6slx9-3csg324
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
218 Warnings (171 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 2 Failing Constraints
Environment: System Settings
  • Final Timing Score:
333243  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 296 11,440 2%  
    Number used as Flip Flops 296      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 306 5,720 5%  
    Number used as logic 287 5,720 5%  
        Number using O6 output only 215      
        Number using O5 output only 56      
        Number using O5 and O6 16      
        Number used as ROM 0      
    Number used as Memory 2 1,440 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 2      
            Number using O6 output only 2      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 17      
        Number with same-slice register load 13      
        Number with same-slice carry load 4      
        Number with other load 0      
Number of occupied Slices 149 1,430 10%  
Number of LUT Flip Flop pairs used 356      
    Number with an unused Flip Flop 90 356 25%  
    Number with an unused LUT 50 356 14%  
    Number of fully used LUT-FF pairs 216 356 60%  
    Number of unique control sets 29      
    Number of slice register sites lost
        to control set restrictions
134 11,440 1%  
Number of bonded IOBs 33 200 16%  
    Number of LOCed IOBs 33 33 100%  
    IOB Flip Flops 12      
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 8 16 50%  
    Number used as BUFGs 8      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 3 4 75%  
    Number used as DCMs 3      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 12 200 6%  
    Number used as OLOGIC2s 12      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.80      
 
Performance Summary [-]
Final Timing Score: 333243 (Setup: 315594, Hold: 17649, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 2 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent日 4 8 10:24:22 20120154 Warnings (154 new)48 Infos (48 new)
Translation ReportCurrent日 4 8 10:26:21 2012010 Warnings (0 new)4 Infos (0 new)
Map ReportCurrent日 4 8 10:26:49 2012021 Warnings (16 new)15 Infos (3 new)
Place and Route ReportCurrent日 4 8 10:27:02 2012018 Warnings (1 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent日 4 8 10:27:08 2012003 Infos (0 new)
Bitgen ReportCurrent日 4 8 10:27:18 2012015 Warnings (0 new)2 Infos (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportCurrent日 4 8 10:26:49 2012
WebTalk Log FileCurrent日 4 8 10:27:18 2012

Date Generated: 04/22/2012 - 11:41:23