nexys3_disp Project Status (03/20/2012 - 00:08:07)
Project File: disp.xise Parser Errors: No Errors
Module Name: nexys3_disp Implementation State: Programming File Generated
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
426 Warnings (11 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 2 Failing Constraints
Environment: System Settings
  • Final Timing Score:
849924  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 251 18,224 1%  
    Number used as Flip Flops 251      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 236 9,112 2%  
    Number used as logic 217 9,112 2%  
        Number using O6 output only 64      
        Number using O5 output only 70      
        Number using O5 and O6 83      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 19      
        Number with same-slice register load 15      
        Number with same-slice carry load 4      
        Number with other load 0      
Number of occupied Slices 75 2,278 3%  
Number of LUT Flip Flop pairs used 243      
    Number with an unused Flip Flop 69 243 28%  
    Number with an unused LUT 7 243 2%  
    Number of fully used LUT-FF pairs 167 243 68%  
    Number of unique control sets 10      
    Number of slice register sites lost
        to control set restrictions
45 18,224 1%  
Number of bonded IOBs 96 232 41%  
    Number of LOCed IOBs 96 96 100%  
    IOB Flip Flops 26      
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 9 16 56%  
    Number used as BUFGs 9      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 3 4 75%  
    Number used as DCMs 3      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 26 248 10%  
    Number used as OLOGIC2s 26      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.29      
 
Performance Summary [-]
Final Timing Score: 849924 (Setup: 849924, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 2 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent‰Î 3 20 00:06:50 20120151 Warnings (11 new)41 Infos (0 new)
Translation ReportCurrent‰Î 3 20 00:06:54 2012066 Warnings (0 new)4 Infos (0 new)
Map ReportCurrent‰Î 3 20 00:07:37 2012070 Warnings (0 new)13 Infos (0 new)
Place and Route ReportCurrent‰Î 3 20 00:07:49 2012071 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrent‰Î 3 20 00:07:56 2012002 Infos (0 new)
Bitgen ReportCurrent‰Î 3 20 00:08:07 2012068 Warnings (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportCurrent‰Î 3 20 00:07:37 2012
WebTalk Log FileCurrent‰Î 3 20 00:08:07 2012

Date Generated: 03/20/2012 - 00:08:07