/************************************************************************/
/* CQBBEL GNU CC Common Control Software / (C) Toshio MURAI 2011, 2012	*/
/*      This is Free Software;   You can redistribute this software     */
/*      and/or modify it under the terms of the GNU General Public      */
/*      License version 3, or (at your option) any later version.       */
/************************************************************************/

struct str_fgpio {
	volatile unsigned long FIO_DIR;	
	volatile unsigned long NONE1;
	volatile unsigned long NONE2;
	volatile unsigned long NONE3;
	volatile unsigned long FIO_MASK;	/* +0x10*/
	volatile unsigned long FIO_PIN;		/* +0x14*/
	volatile unsigned long FIO_SET;		/* +0x18*/
	volatile unsigned long FIO_CLR;		/* +0x1c*/
};
#define FGPIO_0 ((struct str_fgpio *) 0x3FFFC000)
#define FGPIO_1 ((struct str_fgpio *) 0x3FFFC020)
#define FGPIO_2 ((struct str_fgpio *) 0x3FFFC040)
#define FGPIO_3 ((struct str_fgpio *) 0x3FFFC060)
#define FGPIO_4 ((struct str_fgpio *) 0x3FFFC080)

struct str_gpioir {
	volatile unsigned int	IntStatus;	//80 -- GPIO overall Interrupt Status.
	volatile unsigned int	IntStatR;	//84 A4 GPIO Interrupt Status for Rising edge.
	volatile unsigned int	IntStatF;	//88 A8 GPIO Interrupt Status for Falling edge.
	volatile unsigned int	IntClr;	//8C AC GPIO Interrupt Clear.
	volatile unsigned int	IntEnR;	//90 B0 GPIO Interrupt Enable for Rising edge.
	volatile unsigned int	IntEnF;	//94 B4 GPIO Interrupt Enable for Falling edge.
};
#define	IO0IntEnR	((struct str_gpioir *)0xE0028080)
#define	IO2IntEnR	((struct str_gpioir *)0xE00280A0)

struct str_sysscs {
	volatile unsigned int	SCS;	//SCS System Control and Status R/W 0x00 0xE01F C1A0
};
#define	SYSSCS	((struct str_sysscs*)0xE01FC1A0)

struct str_clksel {
	volatile unsigned int	IRCTRIM;	//IRCTRIM IRC Trim Register R/W 0xA0 0xE01FC1A4
	volatile unsigned int	PCLKSEL0;	//PCLKSEL0 Peripheral Clock Selection register 0. R/W 0 0xE01F C1A8
	volatile unsigned int	PCLKSEL1;	//PCLKSEL1 Peripheral Clock Selection register 1. R/W 0 0xE01F C1AC
};
#define	CLKSEL	((struct str_clksel*)0xE01FC1A4)

struct str_power {
	volatile unsigned int	PCON;	//0xE01FC0C0	Power Control Register
	volatile unsigned int	PCONP;	//0xE01FC0C4	Power Control for Peripherals Register
};
#define	 POWERCTL	((struct str_power *) 0xE01FC0C0)

struct str_timer {
	volatile unsigned long	IR;	//IR Interrupt Register. 0xE0004000
	volatile unsigned long	TCR;	//TCR Timer Control Register. T
	volatile unsigned long	TC;	//TC Timer Counter. 
	volatile unsigned long	PR;	//PR Prescale Register. 
	volatile unsigned long	PC;	//PC Prescale Counter. 
	volatile unsigned long	MCR;	//MCR Match Control Register. 
	volatile unsigned long	MR0;	//MR0 Match Register 0 0x0xE0004018
	volatile unsigned long	MR1;	//MR1 Match Register 1
	volatile unsigned long	MR2;	//MR2 Match Register 2	0xE0004020
	volatile unsigned long	MR3;	//MR3 Match Register 2	0xE0004024
	volatile unsigned long	CCR;	//CCR Capture Control Register. The CCR	0xE0004028
	volatile unsigned long	CR0;	//CR0 	Capture Register	 0xE000 402C
	volatile unsigned long	CR1;	//CR1 	Capture Register	 0xE000 4030
	volatile unsigned long	EMR;	//EMR External Match Register.	 0xE000 403C
	volatile unsigned long	CTCR;	//CTCR Count Control Register. 0xE000 4070
};
#define	TIMER0	((struct str_timer*)0xE0004000)
#define	TIMER1	((struct str_timer*)0xE0008000)
#define	TIMER2	((struct str_timer*)0xE0070000)
#define	TIMER3	((struct str_timer*)0xE0074000)

struct str_vicr {
	volatile unsigned int	IRQStatus;
	volatile unsigned int	FIQStatus;
	volatile unsigned int	RawIntr;
	volatile unsigned int	IntSelect;
	volatile unsigned int	IntEnable;
	volatile unsigned int	IntEnClr;
};

#define	VIC	((struct str_vicr *) 0xFFFFF000)
struct str_adc {
	volatile unsigned long	AD0CR;//AD0CR A/D Control Register. R/W 0x0000 0001 0xE003 4000
	volatile unsigned long	AD0GDR;//AD0GDR A/D Global Data Register. R/W NA 0xE003 4004
	volatile unsigned long	DUMM;
	volatile unsigned long	AD0STAT;//AD0INTEN A/D Interrupt Enable R/W 0x0000 0100 0xE003 400C
	volatile unsigned long	AD0DR0;//AD0DR0 A/D Channel 0 R/W NA 0xE003 4010
	volatile unsigned long	AD0DR1;//AD0DR1 A/D Channel 1 R/W NA 0xE003 4014
	volatile unsigned long	AD0DR2;//AD0DR2 A/D Channel 2 R/W NA 0xE003 4018
	volatile unsigned long	AD0DR3;//AD0DR3 A/D Channel 3 R/W NA 0xE003 401C
	volatile unsigned long	AD0DR4;//AD0DR4 A/D Channel 4 /R/W NA 0xE003 4020
	volatile unsigned long	AD0DR5;//AD0DR5 A/D Channel 5 R/W NA 0xE003 4024
	volatile unsigned long	AD0DR6;//AD0DR6 A/D Channel 6 R/W NA 0xE003 4028
	volatile unsigned long	AD0DR7;//AD0DR7 A/D Channel 7 R/W NA 0xE003 402C
	volatile unsigned long	AD0ST;//AD0STAT A/D Status Register. RO 0 0xE003 4030
};

#define	AD0	((struct str_adc*)0xE0034000)

//Table 104. Pin Connect Block Register Map
struct str_pinsel {
	volatile unsigned long	PINSEL0;	//PINSEL0 Pin function select register 0. R/W 0x0000 0000 0xE002 C000
	volatile unsigned long	PINSEL1;	//PINSEL1 Pin function select register 1. R/W 0x0000 0000 0xE002 C004
	volatile unsigned long	PINSEL2;	//PINSEL2 Pin function select register 2. R/W 0x0000 0000 0xE002 C008
	volatile unsigned long	PINSEL3;	//PINSEL3 Pin function select register 3. R/W 0x0000 0000 0xE002 C00C
	volatile unsigned long	PINSEL4;	//PINSEL4 Pin function select register 4. R/W 0x0000 0000 0xE002 C010
	volatile unsigned long	PINSEL5;	//PINSEL5 Pin function select register 5. R/W 0x0000 0000 0xE002 C014
	volatile unsigned long	PINSEL6;	//PINSEL6 Pin function select register 6. R/W 0x0000 0000 0xE002 C018
	volatile unsigned long	PINSEL7;	//PINSEL7 Pin function select register 7. R/W 0x0000 0000 0xE002 C01C
	volatile unsigned long	PINSEL8;	//PINSEL8 Pin function select register 8. R/W 0x0000 0000 0xE002 C020
	volatile unsigned long	PINSEL9;	//PINSEL9 Pin function select register 9. R/W 0x0000 0000 0xE002 C024
	volatile unsigned long	PINSEL10;	//PINSEL10 Pin function select register 10. R/W 0x0000 0000 0xE002 C028
};
#define	PINSEL	((struct str_pinsel*)0xE002C000)

struct str_pinmode {
	volatile unsigned long	PINMODE0;	//PINMODE0 Pin mode select register 0. R/W 0x0000 0000 0xE002 C040
	volatile unsigned long	PINMODE1;	//PINMODE1 Pin mode select register 1. R/W 0x0000 0000 0xE002 C044
	volatile unsigned long	PINMODE2;	//PINMODE2 Pin mode select register 2. R/W 0x0000 0000 0xE002 C048
	volatile unsigned long	PINMODE3;	//PINMODE3 Pin mode select register 3. R/W 0x0000 0000 0xE002 C04C
	volatile unsigned long	PINMODE4;	//PINMODE4 Pin mode select register 4. R/W 0x0000 0000 0xE002 C050
	volatile unsigned long	PINMODE5;	//PINMODE5 Pin mode select register 5. R/W 0x0000 0000 0xE002 C054
	volatile unsigned long	PINMODE6;	//PINMODE6 Pin mode select register 6. R/W 0x0000 0000 0xE002 C058
	volatile unsigned long	PINMODE7;	//PINMODE7 Pin mode select register 7. R/W 0x0000 0000 0xE002 C05C
	volatile unsigned long	PINMODE8;	//PINMODE8 Pin mode select register 8. R/W 0x0000 0000 0xE002 C060
	volatile unsigned long	PINMODE9;	//PINMODE9 Pin mode select register 9. R/W 0x0000 0000 0xE002 C064
};
#define	PINMODE	((struct str_pinmode*)0xE002C040)

