/************************************************************************/
/* CQBBEL GNU CC Common Control Software / (C) Toshio MURAI 2011, 2012	*/
/*      This is Free Software;   You can redistribute this software     */
/*      and/or modify it under the terms of the GNU General Public      */
/*      License version 3, or (at your option) any later version.       */
/************************************************************************/

#include "io.h"
#define	SETCPU()	\
	{	\
		CLK->FRQCR  = 0x1104;		\
	}
	/* Bφ=48M Iφ=144M Pφ=24M */	/*CCR1 = (1<<11) | (1<<3);  CCR1 = 0;  /* 命令キャッシュフラッシュ*/	\
		/*CCR1 = (1<<8) |  (1 << 0);   /* 命令キャッシュ、オペランドキャッシュイネーブル*/	\
		/* 割り込みイネーブル*/	\
		/*IBCR = 0xFFFF;*/	\
		/*IBNR = 0x4000; Bank Register*/	\

/*	On Board LED 	1 bit	*/
#define	SETBOARDLED()	\
	{	\
		  /* PortC8*/	\
		PORTC->CR2  &= 0xFFF0;	/* SEL PC08 */	\
		PORTC->IOR0 |= 0x100;	/* PC8 Output */	\
	}

#define	REVERSELED()	\
	{	\
		PORTC->DR0  ^= 0x0100;/*=0xFEFF; PC8='L' */	}

/*	8bit Dip Switch 8bit	J2:1-8 (A0-A7)	A0=PJ0 A1-A7=PB1-PB7 */
#define	SETDIPSWITCH()	\
	{	\
	/* PORTB	*/	\
		PORTB->CR0 &=0x0000;	/* PORTB 0-3 PB0-PB3(-0)*/	\
		PORTB->CR1 &=0x0000;	/* PORTB 4-7 */	\
		PORTB->CR2 &=0x0000;	/* PORTB 8-B */	\
		PORTB->CR3 &=0x0000;	/* PORTB C-F Mode1-3 IO Default*/	\
		PORTB->IOR0 = 0x0000;	/*1-7 8-15 All In Default PB0 invalid*/	\
			\
		PORTJ->CR0 &=0x0000;	/*PJ0 Default*/	\
		PORTJ->IOR0 = 0x0000; /*All Input Defalut*/	\
	}

#define	GETDIPSWITCH()		(((~PORTB->DR0) &0xFE)|((~PORTJ->DR0) & 0x01))

/*	7seg LED 15bit Hight/Low	J2:23-38 (D0-D15)	*/
#define	SET7SEGLED()	\
	{	\
		PORTD->CR0 &=0x0000;	/* PORTD 0-3 PD0-PD3*/	\
		PORTD->CR1 &=0x0000;	/* PORTD 4-7 */	\
		PORTD->CR2 &=0x0000;	/* PORTD 8-B */	\
		PORTD->CR3 &=0x0000;	/* PORTD C-F Mode1-3 IO Default*/	\
		PORTD->IOR0 = 0xFFFF;	/*1-7 8-15 All Output */	\
	}

#define	PUT7SEGHIGH(x)	\
	{	\
		PORTD->DR0 = (PORTD->DR0&0x00FF)| ((x<<8)&0xFF00);	\
	}

#define	PUT7SEGLOW(x)		\
	{	\
		PORTD->DR0 = (PORTD->DR0&0xFF00) | (x & 0xFF);	\
	}

#define	GET7SEGHIGH()		((PORTD->DR0/16) & 0xFF)

#define	GET7SEGLOW()		((PORTD->DR0) & 0xFF)

/*	Tact Switch :4 Interrupt Request Switch	J1:29-32() 01Fall 23Rise	*/
/*	nIRQ0-3	*/
#define	SETIRQ()	\
	{	\
		PORTE->IOR0=0x0000;		/*All Input Default*/	\
		PORTE->CR0=0x3333;		/*IRQ0-3*/	\
		PORTE->CR1=0x0000;	/*PB2-5 IRQ0-3*/	\
		/*IREQ->ICR0 = 0x0000;	*/	\
		IREQ->ICR1 = 0x00A5;	/*IRQ01- Fall 0101 IRQ23 Rise 1010*/	\
		/*IREQ->ICR2 = 0x0000;	PINT0-7*/	\
		IPRL->IPR01 =0xFFFF;	/*High Priority*/	\
	};

/*	Timer 1 msec interrupt	50000 */
#define	COUNTER	200000	
/*#define	COUNTER	500	*/
#define	SETTIMER()	\
	{	/*int i;*/\
		CLK->FRQCR  = 0x1104;	/*24MHz: CLK->FRQCR  = 0x1104;I:B:P 144:48:24*/	\
		STB7->STBCR7 = 0xFB;/*&= ~0x04;/*MSTP72 Activate CMT*/	\
		IPRH->IPR10 =0x00FF;	/*High Priority*/	\
		CMT->CMSTR =0x0000;	/*CMT0 0x01 CMT1 0x02*/	\
		CMT->CMCNT_0 =0x0000;		\
		CMT->CMCSR_0 = 0x0043;	/*40(1/1) 41(1/32) 43(1/512) Interrupt Enable 0x0043;	*/ \
		CMT->CMCOR_0 = 0x8954;/*0x8954;	/*0x5D 8M/1000=8000=0x1F40(1/8) 1500=0x5DC(1/32)	48MHz;*/	\
		/*	0x43(1/512) ->0x8954(0.7sec) 47=1msec  0x40(1/1)=0x5dc0 		24MHz;*/	\
		CMT->CMSTR = 0x0001;	/*CMT0 Start*/	\
	}
	
#define	CLEARTIMERINTERRUPT()	\
	{	\
		CMT->CMCSR_0 = 0x0040;\
	}
#define	CLEARIRQ0()	(0)
#define	CLEARIRQ1()	(0)
#define	CLEARIRQ2()	(0)
#define	CLEARIRQ3()	(0)
/*	AD Converter	J1:1(AN0) Port H0*/
#define	SETAD()	\
	{	int i;\
		STB3->STBCR3&= ~0x04;/* &=0xFC; /*&=~0x04;*/	\
		i= STB3->STBCR3;	\
		PORTH->CR0 = 0x1111;/*|=0x0001 PJ0->AN0*/	\
		ADC->ADCSR = 0x0000;/*Single AN0	*/	\
	}

#define	STARTAD0()	\
	{	\
		ADC->ADCSR = 0x2000;/*Start ANx*/	\
		while((ADC->ADCSR & 0x8000)==0);/*0x8000 WaitEnd*/	\
	}

#define	GETAD0()			((ADC->ADDRA)>>8)




#define	SETUART()	\
	{	\
	}

#define	PUTCHAR(data)	\
	{	\
		SCI1->SCFTDR = data;		/*Send Data*/	\
	}

#define	WAITUART()	\
	{	\
	}

#define GETCHAR()	(SCI1->SCFRDR)

#define	CLEARSENDFLAG()	{SCI1->SCFSR = SCI1->SCFSR & 0xFFFC;}

#define	CLEARRECFLAG()	{SCI1->SCFSR  = SCI1->SCFSR & 0xFFDF;}

/*	Interrupt Handler	*/
#define	ENABLEINTERRUPT()	\
	{	unsigned int SR_val;\
	/*	Enable Interrupt Register Bank	*/	\
	/*	IBCR = 0xFFFF;	/*Defaut 0x0000 Inhibit Interrupt  Register Bank for all Level*/	\
	/*	IBNR = 0x4000;	/*Defalut 0x0000 */	\
		asm volatile ("stc sr,%0" : "=r" (SR_val));			\
		SR_val = (SR_val & ~0xF0) | (12<<4);	/*0xF0 0xE0 Level 14)*/	\
		asm volatile ("ldc %0,sr" : : "r" (SR_val));		\
	}

#define	DISABLEINTERRUPT()	\
	{	\
	}

#define	DUMMYINTERRUPT()	\
	{	\
	}

//#define	INTERRUPTATTRIBUTE	__attribute__ ((interrupt))
#define	INTERRUPTATTRIBUTE	__attribute__ ((interrupt_handler))

