/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
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* software is owned by Renesas Electronics Corporation and is protected under
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
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* you agree to the additional terms and conditions found by accessing the
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* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* History      : DD.MM.YYYY Version  Description
*              : 25.08.2014 1.00     First Release
*******************************************************************************/
/*******************************************************************************
* File Name    : r_sci_iic_rx110_private.h
* Description  : Functions for using SCI_IIC on RX devices. 
*******************************************************************************/
/* Access to peripherals and board defines. */
#include "platform.h"

#ifdef BSP_MCU_RX110
#ifndef SCI_IIC_RX110_PRIVATE_H

/*******************************************************************************
Macro definitions
*******************************************************************************/
#define SCI_IIC_RX110_PRIVATE_H

/*============================================================================*/
/*  Parameter check of Configuration Options                                  */
/*============================================================================*/
#if (1 == SCI_IIC_CFG_CH0_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH0_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH2_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH2_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH3_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH3_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH4_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH4_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH6_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH6_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH7_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH7_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH8_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH8_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH9_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH9_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH10_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH10_INCLUDED - This channel is not supported by the current MCU."
#endif

#if (1 == SCI_IIC_CFG_CH11_INCLUDED)
    #error "ERROR - SCI_IIC_CFG_CH11_INCLUDED - This channel is not supported by the current MCU."
#endif

/*----------------------------------------------------------------------------*/
/*   Define register setting.                                                 */
/*----------------------------------------------------------------------------*/
/* Sets to use multi-function pin controller. */
#define SCI_IIC_MPC_SSDA_INIT       ((uint8_t)(0x00))   /* Pin function select to Hi-Z                 */
#define SCI_IIC_MPC_SSCL_INIT       ((uint8_t)(0x00))   /* Pin function select to Hi-Z                 */

#if SCI_IIC_CFG_CH1_INCLUDED
    #if ((SCI_IIC_CFG_CH1_SSDA_GP == PORTC_GR) && (SCI_IIC_CFG_CH1_SSDA_PIN == 7))
        #define SCI_IIC_MPC_SSDA1_ENABLE ((uint8_t)(0x0B))   /* Pin function select to SCI1 SSDA pin:b01011 */
    #else
        #define SCI_IIC_MPC_SSDA1_ENABLE ((uint8_t)(0x0A))   /* Pin function select to SCI1 SSDA pin:b01010 */
    #endif
    #if ((SCI_IIC_CFG_CH1_SSCL_GP == PORTC_GR) && (SCI_IIC_CFG_CH1_SSCL_PIN == 6))
        #define SCI_IIC_MPC_SSCL1_ENABLE ((uint8_t)(0x0B))   /* Pin function select to SCI1 SSCL pin:b01011 */
    #else
        #define SCI_IIC_MPC_SSCL1_ENABLE ((uint8_t)(0x0A))   /* Pin function select to SCI1 SSCL pin:b01010 */
    #endif
#endif /* #ifdef SCI_IIC_CFG_CH1_INCLUDED */

#if SCI_IIC_CFG_CH5_INCLUDED
    #define SCI_IIC_MPC_SSDA5_ENABLE    ((uint8_t)(0x0A))   /* Pin function select to SCI5 SSDA pin:b01010 */
    #define SCI_IIC_MPC_SSCL5_ENABLE    ((uint8_t)(0x0A))   /* Pin function select to SCI5 SSCL pin:b01010 */
#endif /* #ifdef SCI_IIC_CFG_CH5_INCLUDED */

#if SCI_IIC_CFG_CH12_INCLUDED
    #define SCI_IIC_MPC_SSDA12_ENABLE   ((uint8_t)(0x0C))   /* Pin function select to SCI12 SSDA pin:b01100 */
    #define SCI_IIC_MPC_SSCL12_ENABLE   ((uint8_t)(0x0C))   /* Pin function select to SCI12 SSCL pin:b01100 */
#endif /* #ifdef SCI_IIC_CFG_CH12_INCLUDED */

/* Interrupt register setting */
#define SCI_IIC_IR_CLR              ((uint8_t)(0x00))   /* Clears interrupt request register.           */
#define SCI_IIC_IR_SET              ((uint8_t)(0x01))   /* Sets interrupt request register.             */

/* Common register setting */
#define SCI_IIC_SMR_INIT            ((uint8_t)(0x00))   /* Initializes SMR.                    */

#define SCI_IIC_SCR_INIT            ((uint8_t)(0x00))   /* Initializes SCR.                    */
#define SCI_IIC_SCR_ENABLE          ((uint8_t)(0xB4))   /* Enable bit:TEIE,TIE,TE,RE bit       */
#define SCI_IIC_SCR_TE_RE           ((uint8_t)(0x30))   /* Enable bit:TE,RE bit                */

#define SCI_IIC_SCMR_INIT           ((uint8_t)(0xF2))   /* Initializes SCMR.                   */

#define SCI_IIC_BRR_INIT            ((uint8_t)(0xFF))   /* Initializes BRR.                    */

#define SCI_IIC_SEMR_INIT           ((uint8_t)(0x00))   /* Initializes SEMR.                   */

#define SCI_IIC_SNFR_INIT           ((uint8_t)(0x00))   /* Initializes SNFR.                   */

#define SCI_IIC_SIMR1_INIT          ((uint8_t)(0x00))   /* Initializes SIMR1.                  */

#define SCI_IIC_SIMR2_INIT          ((uint8_t)(0x00))   /* Initializes SIMR2.                  */

#define SCI_IIC_SIMR3_INIT          ((uint8_t)(0x00))   /* Initializes SIMR3.                  */

#define SCI_IIC_SISR_INIT           ((uint8_t)(0x00))   /* Initializes SISR.                   */

#define SCI_IIC_SPMR_INIT           ((uint8_t)(0x00))   /* Initializes SPMR.                   */

/* port register setting */
#define PORT_PFS_OFFSET             (12)                 /* minimum PORT PIN NUM for PFS */
#define PORT_ODR0_OFFSET            (3)                 /* minimum PORT NUM for ODR0 */
#define PORT_ODR1_OFFSET            (1)                 /* minimum PORT NUM for ODR1 */

/*******************************************************************************
Typedef definitions
*******************************************************************************/
/* define sci register type */
typedef volatile __evenaccess struct st_sci1 *  sci_regs_t;

/*----------------------------------------------------------------------------*/
/*   Define internal sci_iic information structure type.                      */
/*----------------------------------------------------------------------------*/
/* Specifies register addresses and bits associated with the SCI, module-stop, and ICU. */
typedef struct st_sci_iic_ch_rom    /* SCI ROM info for channel control block                       */
{
    mcu_lock_t                              hd_lock;    /* Hardware Lock number                     */
    sci_regs_t                              regs;       /* base ptr to ch registers                 */
    volatile __evenaccess uint32_t *        mstp;       /* ptr to mstp register                     */
    uint32_t                                stop_mask;  /* mstp mask to disable ch                  */
    volatile __evenaccess uint8_t *         ipr;        /* ptr to IPR register                      */
    volatile __evenaccess uint8_t *         ir_txi;     /* ptr to TXI IR register                   */
    volatile __evenaccess uint8_t *         ir_tei;     /* ptr to TEI IR register                   */
    uint8_t                                 tei_ir_mask; /* bit mask to enable/disable txi INT in ICU */
    volatile __evenaccess uint8_t *         icu_txi;
    uint8_t                                 txi_en_mask; /* bit mask to enable/disable txi INT in ICU */
    volatile __evenaccess uint8_t *         icu_tei;
    uint8_t                                 tei_en_mask; /* bit mask to enable/disable tei INT in ICU */
    uint8_t                                 ipr_set_val;
    uint8_t                                 sscl_port_gr;
    uint8_t                                 sscl_port_pin;
    uint8_t                                 sscl_en_val;
    uint8_t                                 ssda_port_gr;
    uint8_t                                 ssda_port_pin;
    uint8_t                                 ssda_en_val;
    uint8_t                                 ssda_delay;
    uint32_t                                bitrate;
    uint8_t                                 df_sel;
    uint8_t                                 df_clk;
} sci_iic_ch_rom_t;

/* CHANNEL CONTROL BLOCK */
typedef struct st_sci_iic_ch_ctrl   /* SCI channel control (for handle)                             */
{
    const sci_iic_ch_rom_t *        rom;                    /* pointer to rom info                  */
    sci_iic_api_event_t             api_Event;              /* Event flag pointer                   */
    sci_iic_api_mode_t              api_Mode;               /* Internal mode of control protocol    */
    sci_iic_api_status_t            api_N_status;           /* Internal Status of Now               */
    sci_iic_api_status_t            api_B_status;           /* Internal Status of Before            */
    uint8_t                         g_mode;                 /* Check I2C condition                  */
    sci_iic_info_t *                gp_sci_iic_info_ch;     /* Channel 1 SCI driver information     */
} sci_iic_ch_ctrl_t;

typedef sci_iic_ch_ctrl_t * sci_iic_hdl_t;

/*******************************************************************************
Private global variables and functions
*******************************************************************************/
static void sci_iic_set_frequency(sci_iic_info_t * p_sci_iic_info);
static void sci_iic_clear_ir_flag(sci_iic_info_t * p_sci_iic_info);

extern const sci_iic_hdl_t g_sci_iic_handles[SCI_IIC_NUM_CH_MAX];

/*----------------------------------------------------------------------------*/
/*   SCI IIC Module start / stop                                                 */
/*----------------------------------------------------------------------------*/
extern void power_on(uint8_t channel);
extern void power_off(uint8_t channel);

/*----------------------------------------------------------------------------*/
/*   Other function                                                           */
/*----------------------------------------------------------------------------*/
extern void sci_iic_io_open(uint8_t port_gr, uint8_t pin_num);
extern void sci_iic_init_io_register(sci_iic_info_t * p_sci_iic_info);
extern void sci_iic_clear_io_register(sci_iic_info_t * p_sci_iic_info);
extern void sci_iic_int_disable(sci_iic_info_t * p_sci_iic_info);
extern void sci_iic_int_enable(sci_iic_info_t * p_sci_iic_info);
extern void sci_iic_mpc_setting(uint8_t port_gr, uint8_t pin_num, uint8_t set_value);

/*----------------------------------------------------------------------------*/
/*   Interrupt Function                                                       */
/*----------------------------------------------------------------------------*/
#if SCI_IIC_CFG_CH1_INCLUDED
/* ---- SCI IIC ch1 TXI ---- */
#pragma interrupt (sci_iic_int_sci_iic1_txi_isr(vect=220))
void sci_iic_int_sci_iic1_txi_isr(void);

/* ---- SCI IIC ch1 TEI ---- */
#pragma interrupt (sci_iic_int_sci_iic1_tei_isr(vect=221))
void sci_iic_int_sci_iic1_tei_isr(void);
#endif


#if SCI_IIC_CFG_CH5_INCLUDED
/* ---- SCI IIC ch5 TXI ---- */
#pragma interrupt (sci_iic_int_sci_iic5_txi_isr(vect=224))
void sci_iic_int_sci_iic5_txi_isr(void);

/* ---- SCI IIC ch5 TEI ---- */
#pragma interrupt (sci_iic_int_sci_iic5_tei_isr(vect=225))
void sci_iic_int_sci_iic5_tei_isr(void);
#endif


#if SCI_IIC_CFG_CH12_INCLUDED
/* ---- SCI IIC ch12 TXI ---- */
#pragma interrupt (sci_iic_int_sci_iic12_txi_isr(vect=240))
void sci_iic_int_sci_iic12_txi_isr(void);

/* ---- SCI IIC ch12 TEI ---- */
#pragma interrupt (sci_iic_int_sci_iic12_tei_isr(vect=241))
void sci_iic_int_sci_iic12_tei_isr(void);
#endif


#endif /* SCI_IIC_RX110_PRIVATE_H */
#endif /* BSP_MCU_RX110 */

/* End of File */

