/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* History      : DD.MM.YYYY Version  Description
*              : 01.07.2013 1.00     First Release
*              : 30.09.2013 1.10     Change symbol of return value and status
*              : 01.07.2014 1.20     RX110 support added.
*              : 25.08.2014 1.30     RX113 and RX64M support added.
*******************************************************************************/
/*******************************************************************************
* File Name     : r_sci_iic_rx_config.h
* Description   : Configures the SCI IIC drivers
*******************************************************************************/
#ifndef SCI_IIC_CONFIG_H
#define SCI_IIC_CONFIG_H

/*******************************************************************************
Configuration Options
*******************************************************************************/
/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */
/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */
/* Setting to 1 includes parameter checking */
/*            0 compiles out parameter checking */
#define SCI_IIC_CFG_PARAM_CHECKING_ENABLE   (1)


/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */
                                                /* mcu supported channels           */
#define SCI_IIC_CFG_CH0_INCLUDED    (0)         /*                  RX113   RX64M   */
#define SCI_IIC_CFG_CH1_INCLUDED    (1)         /*  RX110   RX111   RX113   RX64M   */
#define SCI_IIC_CFG_CH2_INCLUDED    (0)         /*                  RX113   RX64M   */
#define SCI_IIC_CFG_CH3_INCLUDED    (0)         /*                          RX64M   */
#define SCI_IIC_CFG_CH4_INCLUDED    (0)         /*                          RX64M   */
#define SCI_IIC_CFG_CH5_INCLUDED    (0)         /*  RX110   RX111   RX113   RX64M   */
#define SCI_IIC_CFG_CH6_INCLUDED    (0)         /*                  RX113   RX64M   */
#define SCI_IIC_CFG_CH7_INCLUDED    (0)         /*                          RX64M   */
#define SCI_IIC_CFG_CH8_INCLUDED    (0)         /*                  RX113           */
#define SCI_IIC_CFG_CH9_INCLUDED    (0)         /*                  RX113           */
#define SCI_IIC_CFG_CH12_INCLUDED   (0)         /*  RX110   RX111   RX113   RX64M   */


/* Set SCI IIC bps */
/* 1K = 1000, 100K= 100000, Max:384k = 384000 */
#define SCI_IIC_CFG_CH0_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH1_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH2_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH3_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH4_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH5_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH6_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH7_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH8_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH9_BITRATE_BPS   (384000)
#define SCI_IIC_CFG_CH12_BITRATE_BPS  (384000)

/* SET GROUP12 (RECEIVER ERROR) INTERRUPT PRIORITY; RX63N ONLY
   This #define sets the priority level for the interrupt that handles 
   receiver overrun, framing, and parity errors for all SCI channels
   on the RX63N. It is ignored for all other parts.
*/
/* 1 lowest, 15 highest */
#define SCI_IIC_CFG_CH0_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH1_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH2_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH3_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH4_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH5_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH6_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH7_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH8_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH9_INT_PRIORITY  (2)
#define SCI_IIC_CFG_CH12_INT_PRIORITY (2)

/* Digital noise filter (NFEN bit).
   0 =  Noise cancellation function for the SSCLn and SSDAn input signals
        is disabled.
   1 =  Noise cancellation function for the SSCLn and SSDAn input signals
        is enable.
*/
#define SCI_IIC_CFG_CH0_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH1_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH2_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH3_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH4_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH5_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH6_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH7_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH8_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH9_DIGITAL_FILTER  (1)
#define SCI_IIC_CFG_CH12_DIGITAL_FILTER (1)

/* Noise Filter Setting Register (NFCS bit).
   001  =  1       =   The clock signal divided by 1 is used with the noise filter.
   010  =  2       =   The clock signal divided by 2 is used with the noise filter.
   011  =  3       =   The clock signal divided by 4 is used with the noise filter.
   100  =  4       =   The clock signal divided by 8 is used with the noise filter.
*/
#define SCI_IIC_CFG_CH0_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH1_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH2_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH3_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH4_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH5_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH6_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH7_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH8_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH9_FILTER_CLOCK    (1)
#define SCI_IIC_CFG_CH12_FILTER_CLOCK   (1)

/* I2C Mode Register 1 (IICDL bit).
   00001  =  1       =   0 to 1 cycle
   00010  =  2       =   1 to 2 cycles
   00011  =  3       =   2 to 3 cycles
   00100  =  4       =   3 to 4 cycles
   00101  =  5       =   4 to 5 cycles
   |
   11110  = 30       =  29 to 30 cycles
   11111  = 31       =  30 to 31 cycles
*/
#define SCI_IIC_CFG_CH0_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH1_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH2_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH3_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH4_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH5_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH6_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH7_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH8_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH9_SSDA_DELAY_SELECT   (1)
#define SCI_IIC_CFG_CH12_SSDA_DELAY_SELECT  (1)

/* Define software bus busy check counter. */
#define SCI_IIC_CFG_BUS_CHECK_COUNTER   (1000)

/* Setting to port.
   1 =  includes sci (simple iic)port setting processing
   0 =  compiles out sci (simple iic)port setting processing
 */
#define SCI_IIC_CFG_PORT_SETTING_PROCESSING   (1)

/*------------------------------------------------------------------------------*/
/*   Set using port as sci iic port                                             */
/*------------------------------------------------------------------------------*/
/* Select the port group and pin used by setting "SCI_IIC_CFG_CHi_xxxx_GP (select from port group 0 to J)" */
/* and "SCI_IIC_CFG_CHi_xxxx_PIN (select from port group 0 to 7)", respectively. */
/* For example, when assigning the SSCL1 pin to P34 (pin 4 of port group 3), set as follows: */
/*   #define SCI_IIC_CFG_CH1_SSCL_GP     (PORT3_GR)                              */
/*   #define SCI_IIC_CFG_CH1_SSCL_PIN    (4)                                     */

/* Select the ports (SSCL0 and SSDA0) to use in SCI0 */
#define SCI_IIC_CFG_CH0_SSCL_GP     (PORT2_GR) 
#define SCI_IIC_CFG_CH0_SSCL_PIN    (1)

#define SCI_IIC_CFG_CH0_SSDA_GP     (PORT2_GR)
#define SCI_IIC_CFG_CH0_SSDA_PIN    (0)


/* Select the ports (SSCL1 and SSDA1) to use in SCI1 */
#define SCI_IIC_CFG_CH1_SSCL_GP     (PORT1_GR) 
#define SCI_IIC_CFG_CH1_SSCL_PIN    (5)

#define SCI_IIC_CFG_CH1_SSDA_GP     (PORT1_GR)
#define SCI_IIC_CFG_CH1_SSDA_PIN    (6)


/* Select the ports (SSCL2 and SSDA2) to use in SCI2 */
#define SCI_IIC_CFG_CH2_SSCL_GP     (PORT5_GR) 
#define SCI_IIC_CFG_CH2_SSCL_PIN    (2)

#define SCI_IIC_CFG_CH2_SSDA_GP     (PORT5_GR)
#define SCI_IIC_CFG_CH2_SSDA_PIN    (0)


/* Select the ports (SSCL3 and SSDA3) to use in SCI3 */
#define SCI_IIC_CFG_CH3_SSCL_GP     (PORT2_GR) 
#define SCI_IIC_CFG_CH3_SSCL_PIN    (5)

#define SCI_IIC_CFG_CH3_SSDA_GP     (PORT2_GR)
#define SCI_IIC_CFG_CH3_SSDA_PIN    (3)


/* Select the ports (SSCL4 and SSDA4) to use in SCI4 */
#define SCI_IIC_CFG_CH4_SSCL_GP     (PORTB_GR) 
#define SCI_IIC_CFG_CH4_SSCL_PIN    (0)

#define SCI_IIC_CFG_CH4_SSDA_GP     (PORTB_GR)
#define SCI_IIC_CFG_CH4_SSDA_PIN    (1)


/* Select the ports (SSCL5 and SSDA5) to use in SCI5 */
#define SCI_IIC_CFG_CH5_SSCL_GP     (PORTC_GR)
#define SCI_IIC_CFG_CH5_SSCL_PIN    (2)

#define SCI_IIC_CFG_CH5_SSDA_GP     (PORTC_GR)
#define SCI_IIC_CFG_CH5_SSDA_PIN    (3)


/* Select the ports (SSCL6 and SSDA6) to use in SCI6 */
#define SCI_IIC_CFG_CH6_SSCL_GP     (PORTB_GR) 
#define SCI_IIC_CFG_CH6_SSCL_PIN    (0)

#define SCI_IIC_CFG_CH6_SSDA_GP     (PORTB_GR)
#define SCI_IIC_CFG_CH6_SSDA_PIN    (1)


/* Select the ports (SSCL7 and SSDA7) to use in SCI7 */
#define SCI_IIC_CFG_CH7_SSCL_GP     (PORT9_GR) 
#define SCI_IIC_CFG_CH7_SSCL_PIN    (2)

#define SCI_IIC_CFG_CH7_SSDA_GP     (PORT9_GR)
#define SCI_IIC_CFG_CH7_SSDA_PIN    (0)


/* Select the ports (SSCL8 and SSDA8) to use in SCI8 */
#define SCI_IIC_CFG_CH8_SSCL_GP     (PORTC_GR) 
#define SCI_IIC_CFG_CH8_SSCL_PIN    (6)

#define SCI_IIC_CFG_CH8_SSDA_GP     (PORTC_GR)
#define SCI_IIC_CFG_CH8_SSDA_PIN    (7)


/* Select the ports (SSCL9 and SSDA9) to use in SCI9 */
#define SCI_IIC_CFG_CH9_SSCL_GP     (PORTB_GR) 
#define SCI_IIC_CFG_CH9_SSCL_PIN    (6)

#define SCI_IIC_CFG_CH9_SSDA_GP     (PORTB_GR)
#define SCI_IIC_CFG_CH9_SSDA_PIN    (7)


/* Select the ports (SSCL12 and SSDA12) to use in SCI12 */
#define SCI_IIC_CFG_CH12_SSCL_GP    (PORTE_GR)
#define SCI_IIC_CFG_CH12_SSCL_PIN   (2)

#define SCI_IIC_CFG_CH12_SSDA_GP    (PORTE_GR)
#define SCI_IIC_CFG_CH12_SSDA_PIN   (1)


#endif /* SCI_IIC_CONFIG_H */
