/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* History      : DD.MM.YYYY Version  Description
*              : 25.08.2014 1.00     First Release
*******************************************************************************/
/*******************************************************************************
* File Name    : r_sci_iic_rx113.c
* Device(s)    : RX113
* Tool-Chain   : Renesas RX Standard Toolchain 2.01.00
* OS           : None
* H/W Platform : RSKRX113
* Description  : Functions for using SCI_IIC on RX devices. 
*******************************************************************************/
/* Access to peripherals and board defines. */
#include "platform.h"

#ifdef BSP_MCU_RX113
/*****************************************************************************
Includes   <System Includes> , "Project Includes"
******************************************************************************/
/* Defines for SCI_IIC support */
#include "../r_sci_iic_rx_private.h"
#include "r_sci_iic_rx113_private.h"
#include "r_sci_iic_rx_if.h"
#include "r_sci_iic_rx_config.h"


/*******************************************************************************
Exported global variables and functions (to be accessed by other files)
*******************************************************************************/
/*----------------------------------------------------------------------------*/
/*   Defines specific information for each SCI IIC channel.                   */
/*----------------------------------------------------------------------------*/
#if SCI_IIC_CFG_CH0_INCLUDED
    /* rom info */
    const sci_iic_ch_rom_t  g_ch0_rom = {
        BSP_LOCK_SCI0,
        (sci_regs_t)&SCI0,
        &SYSTEM.MSTPCRB.LONG, BIT31_MASK,
        &ICU.IPR[IPR_SCI0_TXI0].BYTE,
        &ICU.IR[IR_SCI0_TXI0].BYTE,
        &ICU.IR[IR_SCI0_TEI0].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI0_TXI0].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI0_TEI0].BYTE, BIT1_MASK,
        SCI_IIC_CFG_CH0_INT_PRIORITY,
        SCI_IIC_CFG_CH0_SSCL_GP,
        SCI_IIC_CFG_CH0_SSCL_PIN,
        SCI_IIC_MPC_SSCL0_ENABLE,
        SCI_IIC_CFG_CH0_SSDA_GP,
        SCI_IIC_CFG_CH0_SSDA_PIN,
        SCI_IIC_MPC_SSDA0_ENABLE,
        SCI_IIC_CFG_CH0_SSDA_DELAY_SELECT,
        SCI_IIC_CFG_CH0_BITRATE_BPS,
        SCI_IIC_CFG_CH0_DIGITAL_FILTER,
        SCI_IIC_CFG_CH0_FILTER_CLOCK
    };

    /* channel control block */
    sci_iic_ch_ctrl_t   g_sci_iic_ch0_ctrl = {
        &g_ch0_rom,
        SCI_IIC_EV_INIT,
        SCI_IIC_MODE_NONE,
        SCI_IIC_STS_NO_INIT,
        SCI_IIC_STS_NO_INIT,
        (uint8_t)NULL,
        (sci_iic_info_t *)NULL
    };
#endif


#if SCI_IIC_CFG_CH1_INCLUDED
    /* rom info */
    const sci_iic_ch_rom_t  g_ch1_rom = {
        BSP_LOCK_SCI1,
        (sci_regs_t)&SCI1,
        &SYSTEM.MSTPCRB.LONG, BIT30_MASK,
        &ICU.IPR[IPR_SCI1_TXI1].BYTE,
        &ICU.IR[IR_SCI1_TXI1].BYTE,
        &ICU.IR[IR_SCI1_TEI1].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI1_TXI1].BYTE, BIT4_MASK,
        &ICU.IER[IER_SCI1_TEI1].BYTE, BIT5_MASK,
        SCI_IIC_CFG_CH1_INT_PRIORITY,
        SCI_IIC_CFG_CH1_SSCL_GP,
        SCI_IIC_CFG_CH1_SSCL_PIN,
        SCI_IIC_MPC_SSCL1_ENABLE,
        SCI_IIC_CFG_CH1_SSDA_GP,
        SCI_IIC_CFG_CH1_SSDA_PIN,
        SCI_IIC_MPC_SSDA1_ENABLE,
        SCI_IIC_CFG_CH1_SSDA_DELAY_SELECT,
        SCI_IIC_CFG_CH1_BITRATE_BPS,
        SCI_IIC_CFG_CH1_DIGITAL_FILTER,
        SCI_IIC_CFG_CH1_FILTER_CLOCK
    };

    /* channel control block */
    sci_iic_ch_ctrl_t   g_sci_iic_ch1_ctrl = {
        &g_ch1_rom,
        SCI_IIC_EV_INIT,
        SCI_IIC_MODE_NONE,
        SCI_IIC_STS_NO_INIT,
        SCI_IIC_STS_NO_INIT,
        (uint8_t)NULL,
        (sci_iic_info_t *)NULL
    };
#endif


#if SCI_IIC_CFG_CH2_INCLUDED
    /* rom info */
    const sci_iic_ch_rom_t  g_ch2_rom = {
        BSP_LOCK_SCI2,
        (sci_regs_t)&SCI2,
        &SYSTEM.MSTPCRB.LONG, BIT29_MASK,
        &ICU.IPR[IPR_SCI2_TXI2].BYTE,
        &ICU.IR[IR_SCI2_TXI2].BYTE,
        &ICU.IR[IR_SCI2_TEI2].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI2_TXI2].BYTE, BIT4_MASK,
        &ICU.IER[IER_SCI2_TEI2].BYTE, BIT5_MASK,
        SCI_IIC_CFG_CH2_INT_PRIORITY,
        SCI_IIC_CFG_CH2_SSCL_GP,
        SCI_IIC_CFG_CH2_SSCL_PIN,
        SCI_IIC_MPC_SSCL2_ENABLE,
        SCI_IIC_CFG_CH2_SSDA_GP,
        SCI_IIC_CFG_CH2_SSDA_PIN,
        SCI_IIC_MPC_SSDA2_ENABLE,
        SCI_IIC_CFG_CH2_SSDA_DELAY_SELECT,
        SCI_IIC_CFG_CH2_BITRATE_BPS,
        SCI_IIC_CFG_CH2_DIGITAL_FILTER,
        SCI_IIC_CFG_CH2_FILTER_CLOCK
    };

    /* channel control block */
    sci_iic_ch_ctrl_t   g_sci_iic_ch2_ctrl = {
        &g_ch2_rom,
        SCI_IIC_EV_INIT,
        SCI_IIC_MODE_NONE,
        SCI_IIC_STS_NO_INIT,
        SCI_IIC_STS_NO_INIT,
        (uint8_t)NULL,
        (sci_iic_info_t *)NULL
    };
#endif


#if SCI_IIC_CFG_CH5_INCLUDED
    /* rom info */
    const sci_iic_ch_rom_t  g_ch5_rom = {
        BSP_LOCK_SCI5,
        (sci_regs_t)&SCI5,
        &SYSTEM.MSTPCRB.LONG, BIT26_MASK,
        &ICU.IPR[IPR_SCI5_TXI5].BYTE,
        &ICU.IR[IR_SCI5_TXI5].BYTE,
        &ICU.IR[IR_SCI5_TEI5].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI5_TXI5].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI5_TEI5].BYTE, BIT1_MASK,
        SCI_IIC_CFG_CH5_INT_PRIORITY,
        SCI_IIC_CFG_CH5_SSCL_GP,
        SCI_IIC_CFG_CH5_SSCL_PIN,
        SCI_IIC_MPC_SSCL5_ENABLE,
        SCI_IIC_CFG_CH5_SSDA_GP,
        SCI_IIC_CFG_CH5_SSDA_PIN,
        SCI_IIC_MPC_SSDA5_ENABLE,
        SCI_IIC_CFG_CH5_SSDA_DELAY_SELECT,
        SCI_IIC_CFG_CH5_BITRATE_BPS,
        SCI_IIC_CFG_CH5_DIGITAL_FILTER,
        SCI_IIC_CFG_CH5_FILTER_CLOCK
    };

    /* channel control block */
    sci_iic_ch_ctrl_t   g_sci_iic_ch5_ctrl = {
        &g_ch5_rom,
        SCI_IIC_EV_INIT,
        SCI_IIC_MODE_NONE,
        SCI_IIC_STS_NO_INIT,
        SCI_IIC_STS_NO_INIT,
        (uint8_t)NULL,
        (sci_iic_info_t *)NULL
    };
#endif


#if SCI_IIC_CFG_CH6_INCLUDED
    /* rom info */
    const sci_iic_ch_rom_t  g_ch6_rom = {
        BSP_LOCK_SCI6,
        (sci_regs_t)&SCI6,
        &SYSTEM.MSTPCRB.LONG, BIT25_MASK,
        &ICU.IPR[IPR_SCI6_TXI6].BYTE,
        &ICU.IR[IR_SCI6_TXI6].BYTE,
        &ICU.IR[IR_SCI6_TEI6].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI6_TXI6].BYTE, BIT4_MASK,
        &ICU.IER[IER_SCI6_TEI6].BYTE, BIT5_MASK,
        SCI_IIC_CFG_CH6_INT_PRIORITY,
        SCI_IIC_CFG_CH6_SSCL_GP,
        SCI_IIC_CFG_CH6_SSCL_PIN,
        SCI_IIC_MPC_SSCL6_ENABLE,
        SCI_IIC_CFG_CH6_SSDA_GP,
        SCI_IIC_CFG_CH6_SSDA_PIN,
        SCI_IIC_MPC_SSDA6_ENABLE,
        SCI_IIC_CFG_CH6_SSDA_DELAY_SELECT,
        SCI_IIC_CFG_CH6_BITRATE_BPS,
        SCI_IIC_CFG_CH6_DIGITAL_FILTER,
        SCI_IIC_CFG_CH6_FILTER_CLOCK
    };

    /* channel control block */
    sci_iic_ch_ctrl_t   g_sci_iic_ch6_ctrl = {
        &g_ch6_rom,
        SCI_IIC_EV_INIT,
        SCI_IIC_MODE_NONE,
        SCI_IIC_STS_NO_INIT,
        SCI_IIC_STS_NO_INIT,
        (uint8_t)NULL,
        (sci_iic_info_t *)NULL
    };
#endif


#if SCI_IIC_CFG_CH8_INCLUDED
    /* rom info */
    const sci_iic_ch_rom_t  g_ch8_rom = {
        BSP_LOCK_SCI8,
        (sci_regs_t)&SCI8,
        &SYSTEM.MSTPCRC.LONG, BIT27_MASK,
        &ICU.IPR[IPR_SCI8_TXI8].BYTE,
        &ICU.IR[IR_SCI8_TXI8].BYTE,
        &ICU.IR[IR_SCI8_TEI8].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI8_TXI8].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI8_TEI8].BYTE, BIT1_MASK,
        SCI_IIC_CFG_CH8_INT_PRIORITY,
        SCI_IIC_CFG_CH8_SSCL_GP,
        SCI_IIC_CFG_CH8_SSCL_PIN,
        SCI_IIC_MPC_SSCL8_ENABLE,
        SCI_IIC_CFG_CH8_SSDA_GP,
        SCI_IIC_CFG_CH8_SSDA_PIN,
        SCI_IIC_MPC_SSDA8_ENABLE,
        SCI_IIC_CFG_CH8_SSDA_DELAY_SELECT,
        SCI_IIC_CFG_CH8_BITRATE_BPS,
        SCI_IIC_CFG_CH8_DIGITAL_FILTER,
        SCI_IIC_CFG_CH8_FILTER_CLOCK
    };

    /* channel control block */
    sci_iic_ch_ctrl_t   g_sci_iic_ch8_ctrl = {
        &g_ch8_rom,
        SCI_IIC_EV_INIT,
        SCI_IIC_MODE_NONE,
        SCI_IIC_STS_NO_INIT,
        SCI_IIC_STS_NO_INIT,
        (uint8_t)NULL,
        (sci_iic_info_t *)NULL
    };
#endif


#if SCI_IIC_CFG_CH9_INCLUDED
    /* rom info */
    const sci_iic_ch_rom_t  g_ch9_rom = {
        BSP_LOCK_SCI9,
        (sci_regs_t)&SCI9,
        &SYSTEM.MSTPCRC.LONG, BIT26_MASK,
        &ICU.IPR[IPR_SCI9_TXI9].BYTE,
        &ICU.IR[IR_SCI9_TXI9].BYTE,
        &ICU.IR[IR_SCI9_TEI9].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI9_TXI9].BYTE, BIT4_MASK,
        &ICU.IER[IER_SCI9_TEI9].BYTE, BIT5_MASK,
        SCI_IIC_CFG_CH9_INT_PRIORITY,
        SCI_IIC_CFG_CH9_SSCL_GP,
        SCI_IIC_CFG_CH9_SSCL_PIN,
        SCI_IIC_MPC_SSCL9_ENABLE,
        SCI_IIC_CFG_CH9_SSDA_GP,
        SCI_IIC_CFG_CH9_SSDA_PIN,
        SCI_IIC_MPC_SSDA9_ENABLE,
        SCI_IIC_CFG_CH9_SSDA_DELAY_SELECT,
        SCI_IIC_CFG_CH9_BITRATE_BPS,
        SCI_IIC_CFG_CH9_DIGITAL_FILTER,
        SCI_IIC_CFG_CH9_FILTER_CLOCK
    };

    /* channel control block */
    sci_iic_ch_ctrl_t   g_sci_iic_ch9_ctrl = {
        &g_ch9_rom,
        SCI_IIC_EV_INIT,
        SCI_IIC_MODE_NONE,
        SCI_IIC_STS_NO_INIT,
        SCI_IIC_STS_NO_INIT,
        (uint8_t)NULL,
        (sci_iic_info_t *)NULL
    };
#endif


#if SCI_IIC_CFG_CH12_INCLUDED
    /* rom info */
    const sci_iic_ch_rom_t  g_ch12_rom = {
        BSP_LOCK_SCI12,
        (sci_regs_t)&SCI12,
        &SYSTEM.MSTPCRB.LONG, BIT4_MASK,
        &ICU.IPR[IPR_SCI12_TXI12].BYTE,
        &ICU.IR[IR_SCI12_TXI12].BYTE,
        &ICU.IR[IR_SCI12_TEI12].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI12_TXI12].BYTE, BIT0_MASK,
        &ICU.IER[IER_SCI12_TEI12].BYTE, BIT1_MASK,
        SCI_IIC_CFG_CH12_INT_PRIORITY,
        SCI_IIC_CFG_CH12_SSCL_GP,
        SCI_IIC_CFG_CH12_SSCL_PIN,
        SCI_IIC_MPC_SSCL12_ENABLE,
        SCI_IIC_CFG_CH12_SSDA_GP,
        SCI_IIC_CFG_CH12_SSDA_PIN,
        SCI_IIC_MPC_SSDA12_ENABLE,
        SCI_IIC_CFG_CH12_SSDA_DELAY_SELECT,
        SCI_IIC_CFG_CH12_BITRATE_BPS,
        SCI_IIC_CFG_CH12_DIGITAL_FILTER,
        SCI_IIC_CFG_CH12_FILTER_CLOCK
    };

    /* channel control block */
    sci_iic_ch_ctrl_t   g_sci_iic_ch12_ctrl = {
        &g_ch12_rom,
        SCI_IIC_EV_INIT,
        SCI_IIC_MODE_NONE,
        SCI_IIC_STS_NO_INIT,
        SCI_IIC_STS_NO_INIT,
        (uint8_t)NULL,
        (sci_iic_info_t *)NULL
    };
#endif


/*----------------------------------------------------------------------------*/
/*   Array for start addresses of information for each SCI IIC channel        */
/*----------------------------------------------------------------------------*/
const sci_iic_hdl_t g_sci_iic_handles[SCI_IIC_NUM_CH_MAX] =
{
#if SCI_IIC_CFG_CH0_INCLUDED
    &g_sci_iic_ch0_ctrl,
#else
    NULL,
#endif
#if SCI_IIC_CFG_CH1_INCLUDED
    &g_sci_iic_ch1_ctrl,
#else
    NULL,
#endif
#if SCI_IIC_CFG_CH2_INCLUDED
    &g_sci_iic_ch2_ctrl,
#else
    NULL,
#endif
    NULL,
    NULL,
#if SCI_IIC_CFG_CH5_INCLUDED
    &g_sci_iic_ch5_ctrl,
#else
    NULL,
#endif
#if SCI_IIC_CFG_CH6_INCLUDED
    &g_sci_iic_ch6_ctrl,
#else
    NULL,
#endif
    NULL,
#if SCI_IIC_CFG_CH8_INCLUDED
    &g_sci_iic_ch8_ctrl,
#else
    NULL,
#endif
#if SCI_IIC_CFG_CH9_INCLUDED
    &g_sci_iic_ch9_ctrl,
#else
    NULL,
#endif
    NULL,
    NULL,
#if SCI_IIC_CFG_CH12_INCLUDED
    &g_sci_iic_ch12_ctrl
#else
    NULL
#endif
};


/************************************************************************************
* Function Name: check_arguments
* Description : check to parameter .
* Arguments : channel -
* Which channel to use.
* Return Value : none
************************************************************************************/
sci_iic_return_t check_arguments(sci_iic_info_t * p_sci_iic_info, sci_iic_api_mode_t called_api)
{

    if (NULL == p_sci_iic_info)
    {
        return SCI_IIC_ERR_INVALID_ARG;
    }

    if (SCI_IIC_MODE_RECEIVE == called_api)
    {

        if (((NULL == p_sci_iic_info->p_slv_adr) ||
             (NULL == p_sci_iic_info->p_data2nd)) ||
            (NULL == p_sci_iic_info->cnt2nd))
        {
            return SCI_IIC_ERR_INVALID_ARG;
        }

    }

    if ((SCI_IIC_MODE_SEND == called_api) ||
        (SCI_IIC_MODE_RECEIVE == called_api))
    {

        if (NULL == p_sci_iic_info->callbackfunc)
        {
            return SCI_IIC_ERR_INVALID_ARG;
        }

    }

    if ((((((SCI_IIC_NUM_CH3 == p_sci_iic_info->ch_no) ||
            (SCI_IIC_NUM_CH4 == p_sci_iic_info->ch_no)) ||
           (SCI_IIC_NUM_CH7 == p_sci_iic_info->ch_no)) ||
          (SCI_IIC_NUM_CH10 == p_sci_iic_info->ch_no)) ||
         (SCI_IIC_NUM_CH11 == p_sci_iic_info->ch_no)) ||
        (SCI_IIC_NUM_CH12 < p_sci_iic_info->ch_no))
    {
        return SCI_IIC_ERR_INVALID_CHAN;
    }

    return SCI_IIC_SUCCESS;
}


/************************************************************************************
* Function Name: power_on
* Description : Turns on power to a SCI_IIC channel.
* Arguments : channel -
* Which channel to use.
* Return Value : none
************************************************************************************/
void power_on(uint8_t channel)
{
    volatile __evenaccess const sci_iic_ch_rom_t * prom = g_sci_iic_handles[channel]->rom;

    /* Enable writing to MSTP registers. */
    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR);

    /* Enable selected SCI_IIC Channel. */
    /* Bring module out of stop state. */
    (*prom->mstp) &= (~prom->stop_mask);

    /* Disable writing to MSTP registers. */
    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR);
}


/************************************************************************************
* Function Name: power_off
* Description : Turns off power to a SCI_IIC channel.
* Arguments : channel -
* Which channel to use.
* Return Value : none
************************************************************************************/
void power_off(uint8_t channel)
{
    volatile __evenaccess const sci_iic_ch_rom_t * prom = g_sci_iic_handles[channel]->rom;

    /* Enable writing to MSTP registers. */
    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR);

    /* Disable selected CMT Channel. */
    /* Put module in stop state. */
    (*prom->mstp) |= prom->stop_mask;

    /* Disable writing to MSTP registers. */
    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR);
}


/************************************************************************************
* Outline      : Open Port Processing
* Function Name: sci_iic_io_open
* Description  : Sets ports to input mode.
*              : Ports input pull-up becomes "Off".
* Arguments    : sci_iic_info_t * p_sci_iic_info     ;   IIC Information
* Return Value : None
************************************************************************************/
void sci_iic_io_open(uint8_t port_gr, uint8_t pin_num)
{
    volatile uint8_t __evenaccess * const ppcr = ((&PORT0.PCR.BYTE) + port_gr);
    volatile uint8_t __evenaccess * const ppdr = ((&PORT0.PDR.BYTE) + port_gr);
    volatile uint8_t __evenaccess * const podr0 = ((&PORT0.ODR0.BYTE) + (2 * (port_gr - PORT_ODR0_OFFSET)));
    volatile uint8_t __evenaccess * const podr1 = ((&PORT0.ODR1.BYTE) + (2 * (port_gr - PORT_ODR1_OFFSET)));

    /* Sets the port register */
    (*ppcr) &= (~(1U << pin_num));                       /* input pull-up resister : off                */
    (*ppdr) &= (~(1U << pin_num));                       /* input mode                                  */

    /* Set N-channel open-drain output */
    if (pin_num <= 3)
    {
        (*podr0)   |=  (0x01 << (2 * pin_num));
    }
    else
    {
        (*podr1)   |=  (0x01 << (2 * (pin_num & 0x03)));
    }

    if (*podr1)                                     /* dummy read */
    {
        /* Does nothing. */
    }

}


/************************************************************************************
* Outline      : Initialize IIC Driver Processing
* Function Name: sci_iic_init_io_register
* Description  : Initializes SCI_IIC register.
* Arguments    : sci_iic_info_t * p_sci_iic_info     ;   IIC Information
* Return Value : None
************************************************************************************/
void sci_iic_init_io_register(sci_iic_info_t * p_sci_iic_info)
{
    sci_regs_t  pregs = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom->regs;
    volatile __evenaccess const sci_iic_ch_rom_t * prom = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom;

    /* Sets SCLn and SDAn to non-driven state. */
    /* SCR - Serial Control Register 
    b5     TE - Transmit Enable - Serial transmission is enabled. */
    pregs->SCR.BYTE = SCI_IIC_SCR_INIT;

    /* Sets a transfer clock. */
    /* Includes I/O register read operation at the end of the following function. */
    sci_iic_set_frequency(p_sci_iic_info);

    /* SEMR - Serial Extended Mode Register
    b5    Digital Noise Filter Function Enable -
          Noise cancellation function for the SSCLn and SSDAn input signals enabled.*/
    pregs->SEMR.BIT.NFEN = prom->df_sel;

    /* SNFR - Noise Filter Setting Register
    b7;b3   Reserved - These bits are read as 0.
    b2:b0   NFCS - The clock signal divided by 1 is used with the noise filter.
    b0      IICM  - Simple I2C Mode Select - Serial Interface Mode */
    pregs->SNFR.BIT.NFCS = prom->df_clk;

    /* Resets all SCI_IIC registers and the internal status. */
    /* SIMR1 - I2C Mode Register 1
    b7;b3   IICDL - SSDA Delay Output Select
    b2:b1   Reserved - These bits are read as 0.
    b0      IICM  - Simple I2C Mode Select - Serial Interface Mode */
    pregs->SIMR1.BIT.IICM = 0;   /* Do not use Simple IIC mode. */

    /* SIMR1 - I2C Mode Register 1
     b7:b3  IICDL - SSDA Delay Output Select - 2 to 3 cycles */
    pregs->SIMR1.BIT.IICDL = prom->ssda_delay;

    /* SIMR2 - I2C Mode Register 2
    b5      IICACKT - ACK Transmission Data - NACK transmission and reception of ACK/NACK*/
    pregs->SIMR2.BIT.IICACKT = SCI_IIC_NACK_TRANS;

    /* SIMR2 - I2C Mode Register 2
    b1      IICCSC - Clock Synchronization - Enable Clock Synchronization*/
    pregs->SIMR2.BIT.IICCSC = SCI_IIC_SYNCHRO;

    /* SIMR2 - I2C Mode Register 2
    b0      IICINTM - I2C Interrupt Mode Select - Use reception and transmission interrupts.*/
    pregs->SIMR2.BIT.IICINTM = SCI_IIC_RCV_TRS_INTERRUPT;

    /* SISR - I2C Status Register
    b0      IICACKR - ACK Reception Data Flag - ACK received */
    pregs->SISR.BIT.IICACKR = SCI_IIC_ACK_RCV;

    /* SPMR - SPI Mode Register
    b7      CKPH   - Clock Phase Select - Clock is not delayed.
    b6      CKPOL  - Clock Polarity Select - Clock polarity is not inverted.
    b5      Reserved - These bits are read as 0.
    b4      MFF    - Mode Fault Flag - No mode-fault error.
    b3      Reserved - These bits are read as 0.
    b2      MSS - Master Slave Select - master mode.
    b1      CTSE - CTS Enable - CTS function is disabled (RTS output function is enabled).
    b0      SSE - SS Pin Function Enable - SS pin function is disabled. */
    pregs->SPMR.BYTE = 0x00;
}


/************************************************************************************
* Outline      : Reset SCI I/O register
* Function Name: sci_iic_clear_io_register
* Description  : Reset SCI I/O register.
* Arguments    : sci_iic_info_t * p_sci_iic_info     ;   IIC Information
* Return Value : None
************************************************************************************/
void sci_iic_clear_io_register(sci_iic_info_t * p_sci_iic_info)
{
    sci_regs_t  pregs = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom->regs;

    /* Initializes SCI I/O register */
    pregs->SMR.BYTE     = SCI_IIC_SMR_INIT;
    pregs->SCR.BYTE     = SCI_IIC_SCR_INIT;
    pregs->SCMR.BYTE    = SCI_IIC_SCMR_INIT;
    pregs->BRR          = SCI_IIC_BRR_INIT;
    pregs->SEMR.BYTE    = SCI_IIC_SEMR_INIT;
    pregs->SNFR.BYTE    = SCI_IIC_SNFR_INIT;
    pregs->SIMR1.BYTE   = SCI_IIC_SIMR1_INIT;
    pregs->SIMR2.BYTE   = SCI_IIC_SIMR2_INIT;
    pregs->SIMR3.BYTE   = SCI_IIC_SIMR3_INIT;
    pregs->SISR.BYTE    = SCI_IIC_SISR_INIT;
    pregs->SPMR.BYTE    = SCI_IIC_SPMR_INIT;
}


/************************************************************************************
* Outline      : Disable Interrupt Processing
* Function Name: sci_iic_int_disable
* Description  : Disables interrupt.
*              : Sets interrupt source priority.
*              : Clears interrupt request register.
* Arguments    : sci_iic_info_t * p_sci_iic_info     ;   IIC Information
* Return Value : None
************************************************************************************/
void sci_iic_int_disable(sci_iic_info_t * p_sci_iic_info)
{
    volatile __evenaccess const sci_iic_ch_rom_t * prom = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom;

    /* Disables interrupt. */
    /* Disables TXI interrupt request enable register.  */
    (*prom->icu_txi) &= (~prom->txi_en_mask);

    /* Disables TEI interrupt request enable register.  */
    (*prom->icu_tei) &= (~prom->tei_en_mask);

    /* Clears interrupt source priority. */
    (*prom->ipr) = 0;                   /* Clears interrupt source priority register.    */

    /* dummy read */
    if(*prom->ipr)
    {
        /* Does nothing. */
    }

    /* Clears the interrupt request register. */
    /* Includes I/O register read operation at the end of the following function. */
    sci_iic_clear_ir_flag(p_sci_iic_info);
}


/************************************************************************************
* Outline      : Enable Interrupt Processing
* Function Name: sci_iic_int_enable
* Description  : Clears interrupt request register.
*              : Enables interrupt.
* Arguments    : sci_iic_info_t * p_sci_iic_info     ;   IIC Information
* Return Value : None
************************************************************************************/
void sci_iic_int_enable(sci_iic_info_t * p_sci_iic_info)
{
    volatile __evenaccess const sci_iic_ch_rom_t * prom = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom;

    /* Clears the interrupt request register. */
    sci_iic_clear_ir_flag(p_sci_iic_info);

    /* Enables interrupt. */
    /* Enables TXI interrupt request enable register.  */
    (*prom->icu_txi) |= prom->txi_en_mask;

    /* Enables TEI interrupt request enable register.  */
    (*prom->icu_tei) |= prom->tei_en_mask;

    /* Sets interrupt source priority. */
    (*prom->ipr) = prom->ipr_set_val;       /* Sets interrupt source priority register.    */

    /* dummy read */
    if(*prom->ipr)
    {
        /* Does nothing. */
    }
}


/************************************************************************************
* Outline      : Set IIC Frequency Processing
* Function Name: sci_iic_set_frequency
* Description  : Sets ICMR1, ICBRL and ICBRH registers.
* Arguments    : sci_iic_info_t * p_sci_iic_info     ;   IIC Information
* Return Value : None
************************************************************************************/
static void sci_iic_set_frequency(sci_iic_info_t * p_sci_iic_info)
{
    volatile uint32_t   pckb_freq = 0U;
    volatile uint16_t   brr_n     = 32U;    /* default: 64*2^(2*0-1) = 32 */
    volatile uint8_t    cks_value = 0U;     /* default: PLCK/1 */
    volatile uint32_t   brr_value = 0U;
    volatile uint32_t   sci_iic_pckb_div = 0U;
    double              pllvco_freq;
    uint8_t             p_div;
    uint8_t             p_mul;
    volatile uint32_t   ch_bps    = 0U;

    const uint8_t       pclkb_div[7] = {1,2,4,8,16,32,64};
    const uint8_t       plldiv[3]    = {1,2,4};

    sci_regs_t          pregs = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom->regs;
    volatile __evenaccess const sci_iic_ch_rom_t * prom = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom;

    /* ----  Calculation PLCKB  ---- */
    /* Store PCLKB division */
    sci_iic_pckb_div = pclkb_div[SYSTEM.SCKCR.BIT.PCKB];

    /* Store PCLKB frequency */
    if (0 == SYSTEM.SCKCR3.BIT.CKSEL)
    {
        /* System clock select LOCO */
        pckb_freq = (BSP_LOCO_HZ / sci_iic_pckb_div);
    }
    else if (1 == SYSTEM.SCKCR3.BIT.CKSEL)
    {
        /* System clock select HOCO */
        pckb_freq = (BSP_HOCO_HZ / sci_iic_pckb_div);
    }
    else if (2 == SYSTEM.SCKCR3.BIT.CKSEL)
    {
         /* System clock select Main OSC */
        pckb_freq = (BSP_CFG_XTAL_HZ / sci_iic_pckb_div);
    }
    else if (3 == SYSTEM.SCKCR3.BIT.CKSEL)
    {
        /* System clock select Sub-clock */
        pckb_freq = (BSP_SUB_CLOCK_HZ / sci_iic_pckb_div);
    }
    else if (4 == SYSTEM.SCKCR3.BIT.CKSEL)
    {
        /* System clock select PLL */
        /* PLL division store */
        p_div = plldiv[SYSTEM.PLLCR.BIT.PLIDIV];
        p_mul = (uint8_t)((SYSTEM.PLLCR.BIT.STC >> 1) + 1);
        pllvco_freq = (double)((BSP_CFG_XTAL_HZ * p_mul) / p_div);
        pllvco_freq /= sci_iic_pckb_div;

        pckb_freq = (uint32_t)pllvco_freq;
    }
    else
    {
        /* nothing to do */
    }
    
    /*  ---- Store brr_n value ---- */
    ch_bps = prom->bitrate;

    /*  ---- Calculation BRR ---- */
    brr_value = (uint32_t)((double)((double)((double)pckb_freq / (brr_n*ch_bps)))-0.1);

    /* Set clock source */

    while (brr_value>255)
    {

        /* Counter over 0xff */
        switch(brr_n)
        {

            case 32:
                brr_n = 64;         /* 64*(2^(2*1-1)) */
                cks_value = 1;      /* clock select: PLCK/4 */
            break;

            case 64:
                brr_n  = 256;       /* 64*(2^(2*2-1))  */
                cks_value = 2;      /* clock select: PLCK/16 */
            break;

            case 256:
                brr_n = 1024;       /* 64*(2^(2*3-1)) */
                cks_value = 3;      /* clock select: PLCK/64 */
            break;

            default:

                /* nothing to do */

            break;
        }

        /*  ---- Calculation BRR ---- */
        brr_value = (uint32_t)((double)(((double)pckb_freq / (brr_n*ch_bps)))-0.1);
    }

    pregs->SMR.BYTE |= cks_value;         /* Sets SMR */
    pregs->BRR = brr_value;          /* Sets BRR */
}


/************************************************************************************
* Outline      : Set SCI_IIC Multi-function Pin Controller Processing
* Function Name: sci_iic_mpc_setting
* Description  : Set SCI_IIC multi-function pin controller.
* Arguments    : sci_iic_info_t * p_sci_iic_info     ;   IIC Information
* Return Value : None
************************************************************************************/
void sci_iic_mpc_setting(uint8_t port_gr, uint8_t pin_num, uint8_t set_value)
{
    volatile uint8_t __evenaccess * const ppmr = ((&PORT0.PMR.BYTE) + port_gr);
    volatile uint8_t __evenaccess * const ppfs = ((((&MPC.P02PFS.BYTE) + (port_gr * 8)) + pin_num) - PORT_PFS_OFFSET);

    if ((*ppfs) != set_value)
    {
        (*ppmr) &= (~(1U << pin_num));                      /* Uses as a GPIO (Input port).             */
        R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC);  /* Enables the PFS register writing.        */
        (*ppfs) = set_value;                                /* Pin function select to "SSCL/SSDA" or "Hi-Z" pin. */
        R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC);   /* Disables the PFS register writing.       */

        /* Verifies "set_value" (setting value for the PFS register).                                   */
        /* If "set_value" is a value other than 0 (default), sets the pin mode control bit to be used 
           as I/O port for peripheral functions.                                                        */
        if (SCI_IIC_MPC_SSCL_INIT != set_value)
        {
            (*ppmr) |= (1U << pin_num);                     /* Uses as SCI_IIC (SSCL/SSDA).             */
        }

        if (*ppmr)                                          /* dummy read                               */
        {
            /* Does nothing. */
        }
    }

}


/************************************************************************************
* Outline      : Clears Interrupt Request Flag Processing
* Function Name: sci_iic_clear_ir_flag
* Description  : Clears interrupt request register.
* Arguments    : sci_iic_info_t * p_sci_iic_info     ;   IIC Information
* Return Value : None
************************************************************************************/
static void sci_iic_clear_ir_flag(sci_iic_info_t * p_sci_iic_info)
{
    uint8_t         internal_flag = 0U;                 /* Determines whether re-initialization is necessary.    */
    sci_regs_t      pregs = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom->regs;
    volatile __evenaccess const sci_iic_ch_rom_t * prom = g_sci_iic_handles[p_sci_iic_info->ch_no]->rom;

    /* Checks IR flag. */
    /* If IR flag is set, clears IR flag. */
    if (SCI_IIC_IR_SET == (*prom->ir_txi))
    {
        /* Sets internal flag. */
        internal_flag = 1U;

        /* Initializes ICIER->SCR register. */
        pregs->SCR.BYTE = SCI_IIC_SCR_INIT;

        while (SCI_IIC_SCR_INIT != pregs->SCR.BYTE)
        {
            /* nothing to do */
        }

        /* Clears TXI1 interrupt request register. */
        (*prom->ir_txi) = SCI_IIC_IR_CLR;

        if (*prom->ir_txi)  /* dummy read                               */
        {
            /* Does nothing. */
        }

        /* Checks the need of the re-initialization. */
        if (1U == internal_flag)
        {
            internal_flag = 0U;

            /* Re-initializes SCI_IIC register because cleared ICCR1.ICE bit. */
            /* Includes I/O register read operation at the end of the following function. */
            sci_iic_init_io_register(p_sci_iic_info);
        }

    }

}


#if SCI_IIC_CFG_CH0_INCLUDED
/************************************************************************************
* Outline      : Interrupt TXI handler for channel 0
* Function Name: sci_iic_int_sci_iic0_txi_isr
* Description  : Types of interrupt requests transmission end.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic0_txi_isr(void)
{
    sci_iic_txi_isr_processing(SCI_IIC_NUM_CH0);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH0]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH1_INCLUDED
/************************************************************************************
* Outline      : Interrupt TXI handler for channel 1
* Function Name: sci_iic_int_sci_iic1_txi_isr
* Description  : Types of interrupt requests transmission end.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic1_txi_isr(void)
{
    sci_iic_txi_isr_processing(SCI_IIC_NUM_CH1);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH1]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH2_INCLUDED
/************************************************************************************
* Outline      : Interrupt TXI handler for channel 2
* Function Name: sci_iic_int_sci_iic2_txi_isr
* Description  : Types of interrupt requests transmission end.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic2_txi_isr(void)
{
    sci_iic_txi_isr_processing(SCI_IIC_NUM_CH2);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH2]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH5_INCLUDED
/************************************************************************************
* Outline      : Interrupt TXI handler for channel 5
* Function Name: sci_iic_int_sci_iic5_txi_isr
* Description  : Types of interrupt requests transmission end.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic5_txi_isr(void)
{
    sci_iic_txi_isr_processing(SCI_IIC_NUM_CH5);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH5]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH6_INCLUDED
/************************************************************************************
* Outline      : Interrupt TXI handler for channel 6
* Function Name: sci_iic_int_sci_iic6_txi_isr
* Description  : Types of interrupt requests transmission end.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic6_txi_isr(void)
{
    sci_iic_txi_isr_processing(SCI_IIC_NUM_CH6);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH6]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH8_INCLUDED
/************************************************************************************
* Outline      : Interrupt TXI handler for channel 8
* Function Name: sci_iic_int_sci_iic8_txi_isr
* Description  : Types of interrupt requests transmission end.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic8_txi_isr(void)
{
    sci_iic_txi_isr_processing(SCI_IIC_NUM_CH8);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH8]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH9_INCLUDED
/************************************************************************************
* Outline      : Interrupt TXI handler for channel 9
* Function Name: sci_iic_int_sci_iic9_txi_isr
* Description  : Types of interrupt requests transmission end.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic9_txi_isr(void)
{
    sci_iic_txi_isr_processing(SCI_IIC_NUM_CH9);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH9]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH12_INCLUDED
/************************************************************************************
* Outline      : Interrupt TXI handler for channel 12
* Function Name: sci_iic_int_sci_iic12_txi_isr
* Description  : Types of interrupt requests transmission end.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic12_txi_isr(void)
{
    sci_iic_txi_isr_processing(SCI_IIC_NUM_CH12);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH12]->gp_sci_iic_info_ch);
}
#endif


#if SCI_IIC_CFG_CH0_INCLUDED
/************************************************************************************
* Outline      : Interrupt TEI handler for channel 0
* Function Name: sci_iic_int_sci_iic0_tei_isr
* Description  : Types of interrupt requests transfer error or event generation.
*              : The event generations are arbitration-lost, NACK detection, timeout detection,
*              : start condition detection, and stop condition detection.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic0_tei_isr(void)
{
    sci_iic_tei_isr_processing(SCI_IIC_NUM_CH0);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH0]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH1_INCLUDED
/************************************************************************************
* Outline      : Interrupt TEI handler for channel 1
* Function Name: sci_iic_int_sci_iic1_tei_isr
* Description  : Types of interrupt requests transfer error or event generation.
*              : The event generations are arbitration-lost, NACK detection, timeout detection, 
*              : start condition detection, and stop condition detection.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic1_tei_isr(void)
{
    sci_iic_tei_isr_processing(SCI_IIC_NUM_CH1);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH1]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH2_INCLUDED
/************************************************************************************
* Outline      : Interrupt TEI handler for channel 2
* Function Name: sci_iic_int_sci_iic2_tei_isr
* Description  : Types of interrupt requests transfer error or event generation.
*              : The event generations are arbitration-lost, NACK detection, timeout detection,
*              : start condition detection, and stop condition detection.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic2_tei_isr(void)
{
    sci_iic_tei_isr_processing(SCI_IIC_NUM_CH2);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH2]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH5_INCLUDED
/************************************************************************************
* Outline      : Interrupt TEI handler for channel 5
* Function Name: sci_iic_int_sci_iic5_tei_isr
* Description  : Types of interrupt requests transfer error or event generation.
*              : The event generations are arbitration-lost, NACK detection, timeout detection,
*              : start condition detection, and stop condition detection.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic5_tei_isr(void)
{
    sci_iic_tei_isr_processing(SCI_IIC_NUM_CH5);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH5]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH6_INCLUDED
/************************************************************************************
* Outline      : Interrupt TEI handler for channel 6
* Function Name: sci_iic_int_sci_iic6_tei_isr
* Description  : Types of interrupt requests transfer error or event generation.
*              : The event generations are arbitration-lost, NACK detection, timeout detection,
*              : start condition detection, and stop condition detection.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic6_tei_isr(void)
{
    sci_iic_tei_isr_processing(SCI_IIC_NUM_CH6);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH6]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH8_INCLUDED
/************************************************************************************
* Outline      : Interrupt TEI handler for channel 8
* Function Name: sci_iic_int_sci_iic8_tei_isr
* Description  : Types of interrupt requests transfer error or event generation.
*              : The event generations are arbitration-lost, NACK detection, timeout detection,
*              : start condition detection, and stop condition detection.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic8_tei_isr(void)
{
    sci_iic_tei_isr_processing(SCI_IIC_NUM_CH8);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH8]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH9_INCLUDED
/************************************************************************************
* Outline      : Interrupt TEI handler for channel 9
* Function Name: sci_iic_int_sci_iic9_tei_isr
* Description  : Types of interrupt requests transfer error or event generation.
*              : The event generations are arbitration-lost, NACK detection, timeout detection,
*              : start condition detection, and stop condition detection.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic9_tei_isr(void)
{
    sci_iic_tei_isr_processing(SCI_IIC_NUM_CH9);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH9]->gp_sci_iic_info_ch);
}
#endif

#if SCI_IIC_CFG_CH12_INCLUDED
/************************************************************************************
* Outline      : Interrupt TEI handler for channel 12
* Function Name: sci_iic_int_sci_iic12_tei_isr
* Description  : Types of interrupt requests transfer error or event generation.
*              : The event generations are arbitration-lost, NACK detection, timeout detection,
*              : start condition detection, and stop condition detection.
* Arguments    : None
* Return Value : None
************************************************************************************/
void sci_iic_int_sci_iic12_tei_isr(void)
{
    sci_iic_tei_isr_processing(SCI_IIC_NUM_CH12);

    /* Calls advance function */
    R_SCI_IIC_Advance(g_sci_iic_handles[SCI_IIC_NUM_CH12]->gp_sci_iic_info_ch);
}
#endif


#endif /* BSP_MCU_RX113 */

/* End of File */

