; ModuleID = 'D:/20_sample_artix7/clock/solution1/.autopilot/db/a.o.3.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-w64-mingw32"

@mem_wreq = global i1 false, align 1              ; [#uses=5 type=i1*]
@mem_dout = global i8 0, align 1                  ; [#uses=5 type=i8*]
@mem_addr = global i8 0, align 1                  ; [#uses=5 type=i8*]
@mem_ack = common global i1 false, align 1        ; [#uses=3 type=i1*]
@dummy_tmr_out = global i1 false, align 1         ; [#uses=4 type=i1*]
@p_str1 = private unnamed_addr constant [8 x i8] c"ap_none\00", align 1 ; [#uses=5 type=[8 x i8]*]
@p_str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1 ; [#uses=20 type=[1 x i8]*]

; [#uses=8]
define internal fastcc void @clock_top_write_mem(i7 zeroext %addr, i8 %data) {
  %data_read = call i8 @_ssdm_op_Read.ap_auto.i8(i8 %data) ; [#uses=3 type=i8]
  call void @llvm.dbg.value(metadata !{i8 %data_read}, i64 0, metadata !27), !dbg !36 ; [debug line = 69:34] [debug variable = data]
  %addr_read = call i7 @_ssdm_op_Read.ap_auto.i7(i7 %addr) ; [#uses=1 type=i7]
  call void @llvm.dbg.value(metadata !{i7 %addr_read}, i64 0, metadata !37), !dbg !38 ; [debug line = 69:22] [debug variable = addr]
  %addr_cast = zext i7 %addr_read to i8           ; [#uses=3 type=i8]
  call void @llvm.dbg.value(metadata !{i7 %addr}, i64 0, metadata !37), !dbg !38 ; [debug line = 69:22] [debug variable = addr]
  call void @llvm.dbg.value(metadata !{i8 %data}, i64 0, metadata !27), !dbg !36 ; [debug line = 69:34] [debug variable = data]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !39 ; [debug line = 72:2]
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_addr, i8 %addr_cast), !dbg !41 ; [debug line = 73:2]
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_dout, i8 %data_read), !dbg !42 ; [debug line = 74:2]
  call void @_ssdm_op_Write.ap_none.volatile.i1P(i1* @mem_wreq, i1 false), !dbg !43 ; [debug line = 75:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !44 ; [debug line = 76:2]
  br label %._crit_edge, !dbg !45                 ; [debug line = 78:2]

._crit_edge:                                      ; preds = %._crit_edge, %0
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_addr, i8 %addr_cast), !dbg !46 ; [debug line = 79:3]
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_dout, i8 %data_read), !dbg !48 ; [debug line = 80:3]
  call void @_ssdm_op_Write.ap_none.volatile.i1P(i1* @mem_wreq, i1 true), !dbg !49 ; [debug line = 81:3]
  %mem_ack_read = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @mem_ack), !dbg !50 ; [#uses=1 type=i1] [debug line = 82:2]
  br i1 %mem_ack_read, label %1, label %._crit_edge, !dbg !50 ; [debug line = 82:2]

; <label>:1                                       ; preds = %._crit_edge
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !51 ; [debug line = 83:2]
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_addr, i8 %addr_cast), !dbg !52 ; [debug line = 85:2]
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_dout, i8 %data_read), !dbg !53 ; [debug line = 86:2]
  call void @_ssdm_op_Write.ap_none.volatile.i1P(i1* @mem_wreq, i1 false), !dbg !54 ; [debug line = 87:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !55 ; [debug line = 88:2]
  ret void, !dbg !56                              ; [debug line = 89:1]
}

; [#uses=1]
define internal fastcc void @clock_top_wait_tmr() nounwind uwtable {
  br label %.loopexit, !dbg !57                   ; [debug line = 62:7]

.loopexit:                                        ; preds = %.preheader, %0
  %u = phi i7 [ 0, %0 ], [ %u_1, %.preheader ]    ; [#uses=2 type=i7]
  %exitcond1 = icmp eq i7 %u, -28, !dbg !57       ; [#uses=1 type=i1] [debug line = 62:7]
  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 100, i64 100, i64 100) nounwind ; [#uses=0 type=i32]
  %u_1 = add i7 %u, 1, !dbg !65                   ; [#uses=1 type=i7] [debug line = 62:23]
  call void @llvm.dbg.value(metadata !{i7 %u_1}, i64 0, metadata !66), !dbg !65 ; [debug line = 62:23] [debug variable = u]
  br i1 %exitcond1, label %2, label %.preheader, !dbg !57 ; [debug line = 62:7]

.preheader:                                       ; preds = %1, %.loopexit
  %t = phi i17 [ %t_1, %1 ], [ 0, %.loopexit ]    ; [#uses=2 type=i17]
  %exitcond = icmp eq i17 %t, -31072, !dbg !67    ; [#uses=1 type=i1] [debug line = 63:8]
  %empty_3 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 100000, i64 100000, i64 100000) nounwind ; [#uses=0 type=i32]
  %t_1 = add i17 %t, 1, !dbg !70                  ; [#uses=1 type=i17] [debug line = 63:24]
  br i1 %exitcond, label %.loopexit, label %1, !dbg !67 ; [debug line = 63:8]

; <label>:1                                       ; preds = %.preheader
  %dummy_tmr_out_read = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @dummy_tmr_out) nounwind, !dbg !71 ; [#uses=1 type=i1] [debug line = 64:4]
  %not_s = xor i1 %dummy_tmr_out_read, true, !dbg !71 ; [#uses=1 type=i1] [debug line = 64:4]
  call void @_ssdm_op_Write.ap_none.volatile.i1P(i1* @dummy_tmr_out, i1 %not_s) nounwind, !dbg !71 ; [debug line = 64:4]
  call void @llvm.dbg.value(metadata !{i17 %t_1}, i64 0, metadata !73), !dbg !70 ; [debug line = 63:24] [debug variable = t]
  br label %.preheader, !dbg !70                  ; [debug line = 63:24]

; <label>:2                                       ; preds = %.loopexit
  ret void, !dbg !74                              ; [debug line = 67:1]
}

; [#uses=12]
declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone

; [#uses=4]
declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone

; [#uses=0]
define void @clock_top() noreturn nounwind uwtable {
  call void (...)* @_ssdm_op_SpecTopModule(), !dbg !75 ; [debug line = 93:1]
  %dummy_tmr_out_load = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @dummy_tmr_out) nounwind, !dbg !80 ; [#uses=0 type=i1] [debug line = 94:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @dummy_tmr_out, [8 x i8]* @p_str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind, !dbg !80 ; [debug line = 94:1]
  %mem_addr_load = call i8 @_ssdm_op_Read.ap_none.volatile.i8P(i8* @mem_addr) nounwind, !dbg !81 ; [#uses=0 type=i8] [debug line = 96:1]
  call void (...)* @_ssdm_op_SpecInterface(i8* @mem_addr, [8 x i8]* @p_str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind, !dbg !81 ; [debug line = 96:1]
  %mem_dout_load = call i8 @_ssdm_op_Read.ap_none.volatile.i8P(i8* @mem_dout) nounwind, !dbg !82 ; [#uses=0 type=i8] [debug line = 97:1]
  call void (...)* @_ssdm_op_SpecInterface(i8* @mem_dout, [8 x i8]* @p_str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind, !dbg !82 ; [debug line = 97:1]
  %mem_wreq_load = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @mem_wreq) nounwind, !dbg !83 ; [#uses=0 type=i1] [debug line = 98:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @mem_wreq, [8 x i8]* @p_str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind, !dbg !83 ; [debug line = 98:1]
  %mem_ack_load = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @mem_ack) nounwind, !dbg !84 ; [#uses=0 type=i1] [debug line = 99:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @mem_ack, [8 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind, !dbg !84 ; [debug line = 99:1]
  br label %1, !dbg !85                           ; [debug line = 108:7]

; <label>:1                                       ; preds = %2, %0
  %pos = phi i6 [ 0, %0 ], [ %pos_1, %2 ]         ; [#uses=3 type=i6]
  %exitcond = icmp eq i6 %pos, -32, !dbg !85      ; [#uses=1 type=i1] [debug line = 108:7]
  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32) nounwind ; [#uses=0 type=i32]
  %pos_1 = add i6 %pos, 1, !dbg !87               ; [#uses=1 type=i6] [debug line = 108:26]
  br i1 %exitcond, label %.preheader.preheader, label %2, !dbg !85 ; [debug line = 108:7]

.preheader.preheader:                             ; preds = %1
  %msec = alloca i8                               ; [#uses=7 type=i8*]
  call void @llvm.dbg.declare(metadata !{i8* %msec}, metadata !88) ; [debug variable = msec]
  %min = alloca i8                                ; [#uses=3 type=i8*]
  %min1 = alloca i8                               ; [#uses=4 type=i8*]
  call void @llvm.dbg.declare(metadata !{i8* %min1}, metadata !89) ; [debug variable = min1]
  %sec10_1 = alloca i8                            ; [#uses=4 type=i8*]
  call void @llvm.dbg.declare(metadata !{i8* %sec10_1}, metadata !90) ; [debug variable = sec10]
  %sec1 = alloca i8                               ; [#uses=6 type=i8*]
  call void @llvm.dbg.declare(metadata !{i8* %sec1}, metadata !91) ; [debug variable = sec1]
  store i8 48, i8* %sec1
  store i8 48, i8* %sec10_1
  store i8 48, i8* %min1
  store i8 48, i8* %min
  store i8 48, i8* %msec
  br label %.preheader, !dbg !92                  ; [debug line = 113:3]

; <label>:2                                       ; preds = %1
  %pos_cast1_cast = zext i6 %pos to i7, !dbg !94  ; [#uses=1 type=i7] [debug line = 109:3]
  call fastcc void @clock_top_write_mem(i7 zeroext %pos_cast1_cast, i8 zeroext 32) nounwind, !dbg !94 ; [debug line = 109:3]
  call void @llvm.dbg.value(metadata !{i6 %pos_1}, i64 0, metadata !96), !dbg !87 ; [debug line = 108:26] [debug variable = pos]
  br label %1, !dbg !87                           ; [debug line = 108:26]

.preheader:                                       ; preds = %.preheader.backedge, %.preheader.preheader
  %msec_load = load i8* %msec, !dbg !97           ; [#uses=2 type=i8] [debug line = 124:3]
  %min_load = load i8* %min, !dbg !98             ; [#uses=2 type=i8] [debug line = 136:7]
  %min1_load = load i8* %min1, !dbg !103          ; [#uses=2 type=i8] [debug line = 133:6]
  %sec10_1_load = load i8* %sec10_1, !dbg !104    ; [#uses=2 type=i8] [debug line = 130:5]
  %sec1_load = load i8* %sec1, !dbg !105          ; [#uses=2 type=i8] [debug line = 127:4]
  call fastcc void @clock_top_write_mem(i7 zeroext 16, i8 zeroext %min_load) nounwind, !dbg !92 ; [debug line = 113:3]
  call fastcc void @clock_top_write_mem(i7 zeroext 17, i8 zeroext %min1_load) nounwind, !dbg !106 ; [debug line = 114:3]
  call fastcc void @clock_top_write_mem(i7 zeroext 18, i8 zeroext 58) nounwind, !dbg !107 ; [debug line = 115:3]
  call fastcc void @clock_top_write_mem(i7 zeroext 19, i8 zeroext %sec10_1_load) nounwind, !dbg !108 ; [debug line = 116:3]
  call fastcc void @clock_top_write_mem(i7 zeroext 20, i8 zeroext %sec1_load) nounwind, !dbg !109 ; [debug line = 117:3]
  call fastcc void @clock_top_write_mem(i7 zeroext 21, i8 zeroext 46) nounwind, !dbg !110 ; [debug line = 118:3]
  call fastcc void @clock_top_write_mem(i7 zeroext 22, i8 zeroext %msec_load) nounwind, !dbg !111 ; [debug line = 119:3]
  call fastcc void @clock_top_wait_tmr(), !dbg !112 ; [debug line = 121:3]
  %msec_1 = add i8 %msec_load, 1, !dbg !97        ; [#uses=2 type=i8] [debug line = 124:3]
  call void @llvm.dbg.value(metadata !{i8 %msec_1}, i64 0, metadata !88), !dbg !97 ; [debug line = 124:3] [debug variable = msec]
  %tmp_7 = icmp ugt i8 %msec_1, 57, !dbg !113     ; [#uses=1 type=i1] [debug line = 125:3]
  br i1 %tmp_7, label %3, label %.preheader.backedge.pre3, !dbg !113 ; [debug line = 125:3]

; <label>:3                                       ; preds = %.preheader
  %sec1_1 = add i8 %sec1_load, 1, !dbg !105       ; [#uses=2 type=i8] [debug line = 127:4]
  call void @llvm.dbg.value(metadata !{i8 %sec1_1}, i64 0, metadata !91), !dbg !105 ; [debug line = 127:4] [debug variable = sec1]
  %tmp_9 = icmp ugt i8 %sec1_1, 57, !dbg !114     ; [#uses=1 type=i1] [debug line = 128:4]
  br i1 %tmp_9, label %4, label %.preheader.backedge.pre, !dbg !114 ; [debug line = 128:4]

; <label>:4                                       ; preds = %3
  %sec10 = add i8 %sec10_1_load, 1, !dbg !104     ; [#uses=2 type=i8] [debug line = 130:5]
  call void @llvm.dbg.value(metadata !{i8 %sec10}, i64 0, metadata !90), !dbg !104 ; [debug line = 130:5] [debug variable = sec10]
  %tmp_s = icmp ugt i8 %sec10, 53, !dbg !115      ; [#uses=1 type=i1] [debug line = 131:5]
  br i1 %tmp_s, label %5, label %.preheader.backedge.pre1, !dbg !115 ; [debug line = 131:5]

; <label>:5                                       ; preds = %4
  %min1_1 = add i8 %min1_load, 1, !dbg !103       ; [#uses=2 type=i8] [debug line = 133:6]
  call void @llvm.dbg.value(metadata !{i8 %min1_1}, i64 0, metadata !89), !dbg !103 ; [debug line = 133:6] [debug variable = min1]
  %tmp_1 = icmp ugt i8 %min1_1, 57, !dbg !116     ; [#uses=1 type=i1] [debug line = 134:6]
  store i8 48, i8* %sec10_1
  br i1 %tmp_1, label %6, label %.preheader.backedge.pre2, !dbg !116 ; [debug line = 134:6]

; <label>:6                                       ; preds = %5
  %min10 = add i8 1, %min_load, !dbg !98          ; [#uses=2 type=i8] [debug line = 136:7]
  %tmp = trunc i8 %min10 to i6, !dbg !98          ; [#uses=1 type=i6] [debug line = 136:7]
  call void @llvm.dbg.value(metadata !{i8 %min10}, i64 0, metadata !117), !dbg !98 ; [debug line = 136:7] [debug variable = min10]
  %tmp_2 = icmp ugt i8 %min10, 53, !dbg !118      ; [#uses=1 type=i1] [debug line = 137:7]
  %p_s = select i1 %tmp_2, i6 -16, i6 %tmp, !dbg !118 ; [#uses=1 type=i6] [debug line = 137:7]
  %p_cast = zext i6 %p_s to i8, !dbg !118         ; [#uses=1 type=i8] [debug line = 137:7]
  store i8 48, i8* %sec1
  store i8 48, i8* %min1
  store i8 %p_cast, i8* %min
  store i8 48, i8* %msec
  br label %.preheader.backedge, !dbg !119        ; [debug line = 140:6]

.preheader.backedge.pre:                          ; preds = %3
  store i8 %sec1_1, i8* %sec1, !dbg !105          ; [debug line = 127:4]
  store i8 48, i8* %msec
  br label %.preheader.backedge

.preheader.backedge.pre1:                         ; preds = %4
  store i8 48, i8* %sec1
  store i8 %sec10, i8* %sec10_1, !dbg !104        ; [debug line = 130:5]
  store i8 48, i8* %msec
  br label %.preheader.backedge

.preheader.backedge.pre2:                         ; preds = %5
  store i8 48, i8* %sec1
  store i8 %min1_1, i8* %min1, !dbg !103          ; [debug line = 133:6]
  store i8 48, i8* %msec
  br label %.preheader.backedge

.preheader.backedge.pre3:                         ; preds = %.preheader
  store i8 %msec_1, i8* %msec, !dbg !97           ; [debug line = 124:3]
  br label %.preheader.backedge

.preheader.backedge:                              ; preds = %.preheader.backedge.pre3, %.preheader.backedge.pre2, %.preheader.backedge.pre1, %.preheader.backedge.pre, %6
  br label %.preheader
}

; [#uses=6]
define weak void @_ssdm_op_Write.ap_none.volatile.i8P(i8*, i8) {
entry:
  store i8 %1, i8* %0
  ret void
}

; [#uses=4]
define weak void @_ssdm_op_Write.ap_none.volatile.i1P(i1*, i1) {
entry:
  store i1 %1, i1* %0
  ret void
}

; [#uses=4]
define weak void @_ssdm_op_Wait(...) nounwind {
entry:
  ret void
}

; [#uses=1]
define weak void @_ssdm_op_SpecTopModule(...) nounwind {
entry:
  ret void
}

; [#uses=3]
define weak i32 @_ssdm_op_SpecLoopTripCount(...) {
entry:
  ret i32 0
}

; [#uses=5]
define weak void @_ssdm_op_SpecInterface(...) nounwind {
entry:
  ret void
}

; [#uses=2]
define weak i8 @_ssdm_op_Read.ap_none.volatile.i8P(i8*) {
entry:
  %empty = load i8* %0                            ; [#uses=1 type=i8]
  ret i8 %empty
}

; [#uses=5]
define weak i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1*) {
entry:
  %empty = load i1* %0                            ; [#uses=1 type=i1]
  ret i1 %empty
}

; [#uses=1]
define weak i8 @_ssdm_op_Read.ap_auto.i8(i8) {
entry:
  ret i8 %0
}

; [#uses=1]
define weak i7 @_ssdm_op_Read.ap_auto.i7(i7) {
entry:
  ret i7 %0
}

; [#uses=0]
declare i6 @_ssdm_op_PartSelect.i6.i8.i32.i32(i8, i32, i32) nounwind readnone

!hls.encrypted.func = !{}
!llvm.map.gv = !{!0, !7, !12, !17, !22}

!0 = metadata !{metadata !1, i1* @mem_wreq}
!1 = metadata !{metadata !2}
!2 = metadata !{i32 0, i32 0, metadata !3}
!3 = metadata !{metadata !4}
!4 = metadata !{metadata !"mem_wreq", metadata !5, metadata !"uint1", i32 0, i32 0}
!5 = metadata !{metadata !6}
!6 = metadata !{i32 0, i32 0, i32 1}
!7 = metadata !{metadata !8, i8* @mem_dout}
!8 = metadata !{metadata !9}
!9 = metadata !{i32 0, i32 7, metadata !10}
!10 = metadata !{metadata !11}
!11 = metadata !{metadata !"mem_dout", metadata !5, metadata !"uint8", i32 0, i32 7}
!12 = metadata !{metadata !13, i8* @mem_addr}
!13 = metadata !{metadata !14}
!14 = metadata !{i32 0, i32 7, metadata !15}
!15 = metadata !{metadata !16}
!16 = metadata !{metadata !"mem_addr", metadata !5, metadata !"uint8", i32 0, i32 7}
!17 = metadata !{metadata !18, i1* @mem_ack}
!18 = metadata !{metadata !19}
!19 = metadata !{i32 0, i32 0, metadata !20}
!20 = metadata !{metadata !21}
!21 = metadata !{metadata !"mem_ack", metadata !5, metadata !"uint1", i32 0, i32 0}
!22 = metadata !{metadata !23, i1* @dummy_tmr_out}
!23 = metadata !{metadata !24}
!24 = metadata !{i32 0, i32 0, metadata !25}
!25 = metadata !{metadata !26}
!26 = metadata !{metadata !"dummy_tmr_out", metadata !5, metadata !"uint1", i32 0, i32 0}
!27 = metadata !{i32 786689, metadata !28, metadata !"data", metadata !29, i32 33554501, metadata !32, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
!28 = metadata !{i32 786478, i32 0, metadata !29, metadata !"write_mem", metadata !"write_mem", metadata !"", metadata !29, i32 69, metadata !30, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, null, metadata !34, i32 70} ; [ DW_TAG_subprogram ]
!29 = metadata !{i32 786473, metadata !"clock.c", metadata !"D:\5C20_sample_artix7", null} ; [ DW_TAG_file_type ]
!30 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !31, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!31 = metadata !{null, metadata !32, metadata !32}
!32 = metadata !{i32 786454, null, metadata !"uint8", metadata !29, i32 10, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ]
!33 = metadata !{i32 786468, null, metadata !"uint8", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
!34 = metadata !{metadata !35}
!35 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
!36 = metadata !{i32 69, i32 34, metadata !28, null}
!37 = metadata !{i32 786689, metadata !28, metadata !"addr", metadata !29, i32 16777285, metadata !32, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
!38 = metadata !{i32 69, i32 22, metadata !28, null}
!39 = metadata !{i32 72, i32 2, metadata !40, null}
!40 = metadata !{i32 786443, metadata !28, i32 70, i32 1, metadata !29, i32 5} ; [ DW_TAG_lexical_block ]
!41 = metadata !{i32 73, i32 2, metadata !40, null}
!42 = metadata !{i32 74, i32 2, metadata !40, null}
!43 = metadata !{i32 75, i32 2, metadata !40, null}
!44 = metadata !{i32 76, i32 2, metadata !40, null}
!45 = metadata !{i32 78, i32 2, metadata !40, null}
!46 = metadata !{i32 79, i32 3, metadata !47, null}
!47 = metadata !{i32 786443, metadata !40, i32 78, i32 5, metadata !29, i32 6} ; [ DW_TAG_lexical_block ]
!48 = metadata !{i32 80, i32 3, metadata !47, null}
!49 = metadata !{i32 81, i32 3, metadata !47, null}
!50 = metadata !{i32 82, i32 2, metadata !47, null}
!51 = metadata !{i32 83, i32 2, metadata !40, null}
!52 = metadata !{i32 85, i32 2, metadata !40, null}
!53 = metadata !{i32 86, i32 2, metadata !40, null}
!54 = metadata !{i32 87, i32 2, metadata !40, null}
!55 = metadata !{i32 88, i32 2, metadata !40, null}
!56 = metadata !{i32 89, i32 1, metadata !40, null}
!57 = metadata !{i32 62, i32 7, metadata !58, null}
!58 = metadata !{i32 786443, metadata !59, i32 62, i32 2, metadata !29, i32 1} ; [ DW_TAG_lexical_block ]
!59 = metadata !{i32 786443, metadata !60, i32 58, i32 1, metadata !29, i32 0} ; [ DW_TAG_lexical_block ]
!60 = metadata !{i32 786478, i32 0, metadata !29, metadata !"wait_tmr", metadata !"wait_tmr", metadata !"", metadata !29, i32 57, metadata !61, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, null, metadata !34, i32 58} ; [ DW_TAG_subprogram ]
!61 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !62, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!62 = metadata !{null, metadata !63}
!63 = metadata !{i32 786454, null, metadata !"uint32", metadata !29, i32 34, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_typedef ]
!64 = metadata !{i32 786468, null, metadata !"uint32", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
!65 = metadata !{i32 62, i32 23, metadata !58, null}
!66 = metadata !{i32 786688, metadata !59, metadata !"u", metadata !29, i32 60, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!67 = metadata !{i32 63, i32 8, metadata !68, null}
!68 = metadata !{i32 786443, metadata !69, i32 63, i32 3, metadata !29, i32 3} ; [ DW_TAG_lexical_block ]
!69 = metadata !{i32 786443, metadata !58, i32 62, i32 28, metadata !29, i32 2} ; [ DW_TAG_lexical_block ]
!70 = metadata !{i32 63, i32 24, metadata !68, null}
!71 = metadata !{i32 64, i32 4, metadata !72, null}
!72 = metadata !{i32 786443, metadata !68, i32 63, i32 29, metadata !29, i32 4} ; [ DW_TAG_lexical_block ]
!73 = metadata !{i32 786688, metadata !59, metadata !"t", metadata !29, i32 61, metadata !63, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!74 = metadata !{i32 67, i32 1, metadata !59, null}
!75 = metadata !{i32 93, i32 1, metadata !76, null}
!76 = metadata !{i32 786443, metadata !77, i32 92, i32 1, metadata !29, i32 7} ; [ DW_TAG_lexical_block ]
!77 = metadata !{i32 786478, i32 0, metadata !29, metadata !"clock_top", metadata !"clock_top", metadata !"", metadata !29, i32 91, metadata !78, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @clock_top, null, null, metadata !34, i32 92} ; [ DW_TAG_subprogram ]
!78 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !79, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!79 = metadata !{null}
!80 = metadata !{i32 94, i32 1, metadata !76, null}
!81 = metadata !{i32 96, i32 1, metadata !76, null}
!82 = metadata !{i32 97, i32 1, metadata !76, null}
!83 = metadata !{i32 98, i32 1, metadata !76, null}
!84 = metadata !{i32 99, i32 1, metadata !76, null}
!85 = metadata !{i32 108, i32 7, metadata !86, null}
!86 = metadata !{i32 786443, metadata !76, i32 108, i32 2, metadata !29, i32 8} ; [ DW_TAG_lexical_block ]
!87 = metadata !{i32 108, i32 26, metadata !86, null}
!88 = metadata !{i32 786688, metadata !76, metadata !"msec", metadata !29, i32 102, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!89 = metadata !{i32 786688, metadata !76, metadata !"min1", metadata !29, i32 105, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!90 = metadata !{i32 786688, metadata !76, metadata !"sec10", metadata !29, i32 104, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!91 = metadata !{i32 786688, metadata !76, metadata !"sec1", metadata !29, i32 103, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!92 = metadata !{i32 113, i32 3, metadata !93, null}
!93 = metadata !{i32 786443, metadata !76, i32 112, i32 12, metadata !29, i32 10} ; [ DW_TAG_lexical_block ]
!94 = metadata !{i32 109, i32 3, metadata !95, null}
!95 = metadata !{i32 786443, metadata !86, i32 108, i32 33, metadata !29, i32 9} ; [ DW_TAG_lexical_block ]
!96 = metadata !{i32 786688, metadata !76, metadata !"pos", metadata !29, i32 101, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!97 = metadata !{i32 124, i32 3, metadata !93, null}
!98 = metadata !{i32 136, i32 7, metadata !99, null}
!99 = metadata !{i32 786443, metadata !100, i32 134, i32 22, metadata !29, i32 14} ; [ DW_TAG_lexical_block ]
!100 = metadata !{i32 786443, metadata !101, i32 131, i32 22, metadata !29, i32 13} ; [ DW_TAG_lexical_block ]
!101 = metadata !{i32 786443, metadata !102, i32 128, i32 20, metadata !29, i32 12} ; [ DW_TAG_lexical_block ]
!102 = metadata !{i32 786443, metadata !93, i32 125, i32 19, metadata !29, i32 11} ; [ DW_TAG_lexical_block ]
!103 = metadata !{i32 133, i32 6, metadata !100, null}
!104 = metadata !{i32 130, i32 5, metadata !101, null}
!105 = metadata !{i32 127, i32 4, metadata !102, null}
!106 = metadata !{i32 114, i32 3, metadata !93, null}
!107 = metadata !{i32 115, i32 3, metadata !93, null}
!108 = metadata !{i32 116, i32 3, metadata !93, null}
!109 = metadata !{i32 117, i32 3, metadata !93, null}
!110 = metadata !{i32 118, i32 3, metadata !93, null}
!111 = metadata !{i32 119, i32 3, metadata !93, null}
!112 = metadata !{i32 121, i32 3, metadata !93, null}
!113 = metadata !{i32 125, i32 3, metadata !93, null}
!114 = metadata !{i32 128, i32 4, metadata !102, null}
!115 = metadata !{i32 131, i32 5, metadata !101, null}
!116 = metadata !{i32 134, i32 6, metadata !100, null}
!117 = metadata !{i32 786688, metadata !76, metadata !"min10", metadata !29, i32 106, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!118 = metadata !{i32 137, i32 7, metadata !99, null}
!119 = metadata !{i32 140, i32 6, metadata !99, null}
