/*
 * Copyright (c) 2015-2016, Sumio Morioka
 * All rights reserved.
 *
 * This source code was originally written by Dr.Sumio Morioka for use in the 2015-2016 issues of 
 * "the Interface magazine", published by CQ publishing Co.Ltd in Japan (http://www.cqpub.co.jp).
 * The author has no responsibility on any results caused by using this code.
 *
 * - Author: Dr.Sumio Morioka (http://www002.upp.so-net.ne.jp/morioka, FB:Sumio Morioka)
 *
 *
 * IMPORTANT NOTICE:
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   * Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *   * Neither the name of the copyright holder nor the
 *     names of its contributors may be used to endorse or promote products
 *     derived from this software/hardware without specific prior written permission.
 *
 * THIS SOFTWARE/HARDWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE/HARDWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

module car_top(
		rs, e, data,								// LCD
		led_out, dipsw_in, button_in,				// misc
		rst_n, clk
	);

// LCD
output			rs;				// (arduino D8) pin N15
output			e;				// (arduino D9) pin M16
output [3:0]	data;			// (arduino D7,6,5,4) pin T16,T15,T14,R12

output [3:0]	led_out;
input  [3:0]	dipsw_in;
input  [3:0]	button_in;

input			rst_n;			// (active L) pin C2
input			clk;			// pin E3


///////////////////////////////////////////////////////////////////////
// shared memory
///////////////////////////////////////////////////////////////////////
wire [7:0]	addr0;
wire [7:0]	din0;
wire [7:0]	dout0;
wire		r_req0;
wire		r_ack0;
wire		w_req0;
wire		w_ack0;

wire [7:0]	addr1;
wire [7:0]	din1;
wire [7:0]	dout1;
wire		r_req1;
wire		r_ack1;
wire		w_req1;
wire		w_ack1;

wire [7:0]	addr2;
wire [7:0]	din2;
wire [7:0]	dout2;
wire		r_req2;
wire		r_ack2;
wire		w_req2;
wire		w_ack2;

wire [7:0]	addr3;
wire [7:0]	din3;
wire [7:0]	dout3;
wire		r_req3;
wire		r_ack3;
wire		w_req3;
wire		w_ack3;


sharedmem u0 (
	.ap_clk(clk),
	.ap_rst(~rst_n),
	.ap_start(1'b1),

	.addr0(addr0),
	.din0(din0),
	.dout0_i(8'd0),
	.dout0_o(dout0),
	.r_req0(r_req0),
	.r_ack0_i(1'b0),
	.r_ack0_o(r_ack0),
	.w_req0	(w_req0),
	.w_ack0_i(1'b0),
	.w_ack0_o(w_ack0),

	.addr1(addr1),
	.din1(din1),
	.dout1_i(8'd0),
	.dout1_o(dout1),
	.r_req1(r_req1),
	.r_ack1_i(1'b0),
	.r_ack1_o(r_ack1),
	.w_req1(w_req1),
	.w_ack1_i(1'b0),
	.w_ack1_o(w_ack1),

	.addr2(addr2),
	.din2(din2),
	.dout2_i(8'd0),
	.dout2_o(dout2),
	.r_req2(r_req2),
	.r_ack2_i(1'b0),
	.r_ack2_o(r_ack2),
	.w_req2(w_req2),
	.w_ack2_i(1'b0),
	.w_ack2_o(w_ack2),

	.addr3(addr3),
	.din3(din3),
	.dout3_i(8'd0),
	.dout3_o(dout3),
	.r_req3(r_req3),
	.r_ack3_i(1'b0),
	.r_ack3_o(r_ack3),
	.w_req3(w_req3),
	.w_ack3_i(1'b0),
	.w_ack3_o(w_ack3)
);


///////////////////////////////////////////////////////////////////////
// lcd
///////////////////////////////////////////////////////////////////////
wire		en;

lcddrv u1 (
	.ap_clk(clk),
	.ap_rst(~rst_n),
	.ap_start(1'b1),

	.rs_o(rs),
	.en_o(en),
	.data_o(data),

	.dummy_tmr_out_i(1'b0),

	.mem_addr_i(5'd0),
	.mem_addr_o(addr0[4:0]),
	.mem_din(dout0),
	.mem_req_i(1'b0),
	.mem_req_o(r_req0),
	.mem_ack(r_ack0)
);

assign	e	= en;

assign	addr0[7:5]	= 3'd0;
assign	din0		= 8'd0;
assign	w_req0		= 1'b0;


///////////////////////////////////////////////////////////////////////
// clock
///////////////////////////////////////////////////////////////////////

clock_top u2 (
	.ap_clk(clk),
	.ap_rst(~rst_n),
	.ap_start(1'b1),
	.dummy_tmr_out_i(1'b0),
	.mem_addr_i(8'd0),
	.mem_addr_o(addr1),
	.mem_dout_i(8'd0),
	.mem_dout_o(din1),
	.mem_wreq_i(1'b0),
	.mem_wreq_o(w_req1),
	.mem_ack(w_ack1)
);

assign	r_req1		= 1'b0;


///////////////////////////////////////////////////////////////////////

assign	addr2	= 8'd0;
assign	din2	= 8'd0;
assign	r_req2	= 1'b0;
assign	w_req2	= 1'b0;

assign	addr3	= 8'd0;
assign	din3	= 8'd0;
assign	r_req3	= 1'b0;
assign	w_req3	= 1'b0;

assign	led_out	= {en, 1'b0, 1'b0, 1'b1};

endmodule

// end of file
