// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

#include "clock_top_wait_tmr.h"
#include "AESL_pkg.h"

using namespace std;

namespace ap_rtl {

const sc_logic clock_top_wait_tmr::ap_const_logic_1 = sc_dt::Log_1;
const sc_logic clock_top_wait_tmr::ap_const_logic_0 = sc_dt::Log_0;
const sc_lv<3> clock_top_wait_tmr::ap_ST_st1_fsm_0 = "1";
const sc_lv<3> clock_top_wait_tmr::ap_ST_st2_fsm_1 = "10";
const sc_lv<3> clock_top_wait_tmr::ap_ST_st3_fsm_2 = "100";
const sc_lv<32> clock_top_wait_tmr::ap_const_lv32_0 = "00000000000000000000000000000000";
const sc_lv<1> clock_top_wait_tmr::ap_const_lv1_1 = "1";
const sc_lv<32> clock_top_wait_tmr::ap_const_lv32_1 = "1";
const sc_lv<32> clock_top_wait_tmr::ap_const_lv32_2 = "10";
const sc_lv<7> clock_top_wait_tmr::ap_const_lv7_0 = "0000000";
const sc_lv<1> clock_top_wait_tmr::ap_const_lv1_0 = "0";
const sc_lv<17> clock_top_wait_tmr::ap_const_lv17_0 = "00000000000000000";
const sc_lv<7> clock_top_wait_tmr::ap_const_lv7_64 = "1100100";
const sc_lv<7> clock_top_wait_tmr::ap_const_lv7_1 = "1";
const sc_lv<17> clock_top_wait_tmr::ap_const_lv17_186A0 = "11000011010100000";
const sc_lv<17> clock_top_wait_tmr::ap_const_lv17_1 = "1";

clock_top_wait_tmr::clock_top_wait_tmr(sc_module_name name) : sc_module(name), mVcdFile(0) {

    SC_METHOD(thread_ap_clk_no_reset_);
    dont_initialize();
    sensitive << ( ap_clk.pos() );

    SC_METHOD(thread_ap_done);
    sensitive << ( ap_start );
    sensitive << ( ap_sig_cseq_ST_st1_fsm_0 );
    sensitive << ( ap_sig_cseq_ST_st2_fsm_1 );
    sensitive << ( exitcond1_fu_61_p2 );

    SC_METHOD(thread_ap_idle);
    sensitive << ( ap_start );
    sensitive << ( ap_sig_cseq_ST_st1_fsm_0 );

    SC_METHOD(thread_ap_ready);
    sensitive << ( ap_sig_cseq_ST_st2_fsm_1 );
    sensitive << ( exitcond1_fu_61_p2 );

    SC_METHOD(thread_ap_sig_20);
    sensitive << ( ap_CS_fsm );

    SC_METHOD(thread_ap_sig_35);
    sensitive << ( ap_CS_fsm );

    SC_METHOD(thread_ap_sig_44);
    sensitive << ( ap_CS_fsm );

    SC_METHOD(thread_ap_sig_cseq_ST_st1_fsm_0);
    sensitive << ( ap_sig_20 );

    SC_METHOD(thread_ap_sig_cseq_ST_st2_fsm_1);
    sensitive << ( ap_sig_35 );

    SC_METHOD(thread_ap_sig_cseq_ST_st3_fsm_2);
    sensitive << ( ap_sig_44 );

    SC_METHOD(thread_dummy_tmr_out_o);
    sensitive << ( dummy_tmr_out_i );
    sensitive << ( ap_sig_cseq_ST_st3_fsm_2 );
    sensitive << ( exitcond_fu_73_p2 );
    sensitive << ( not_s_fu_85_p2 );

    SC_METHOD(thread_dummy_tmr_out_o_ap_vld);
    sensitive << ( ap_sig_cseq_ST_st3_fsm_2 );
    sensitive << ( exitcond_fu_73_p2 );

    SC_METHOD(thread_exitcond1_fu_61_p2);
    sensitive << ( ap_sig_cseq_ST_st2_fsm_1 );
    sensitive << ( u_reg_39 );

    SC_METHOD(thread_exitcond_fu_73_p2);
    sensitive << ( ap_sig_cseq_ST_st3_fsm_2 );
    sensitive << ( t_reg_50 );

    SC_METHOD(thread_not_s_fu_85_p2);
    sensitive << ( dummy_tmr_out_i );

    SC_METHOD(thread_t_1_fu_79_p2);
    sensitive << ( t_reg_50 );

    SC_METHOD(thread_u_1_fu_67_p2);
    sensitive << ( u_reg_39 );

    SC_METHOD(thread_ap_NS_fsm);
    sensitive << ( ap_start );
    sensitive << ( ap_CS_fsm );
    sensitive << ( exitcond_fu_73_p2 );
    sensitive << ( exitcond1_fu_61_p2 );

    ap_CS_fsm = "001";
    static int apTFileNum = 0;
    stringstream apTFilenSS;
    apTFilenSS << "clock_top_wait_tmr_sc_trace_" << apTFileNum ++;
    string apTFn = apTFilenSS.str();
    mVcdFile = sc_create_vcd_trace_file(apTFn.c_str());
    mVcdFile->set_time_unit(1, SC_PS);
    if (1) {
#ifdef __HLS_TRACE_LEVEL_PORT_HIER__
    sc_trace(mVcdFile, ap_clk, "(port)ap_clk");
    sc_trace(mVcdFile, ap_rst, "(port)ap_rst");
    sc_trace(mVcdFile, ap_start, "(port)ap_start");
    sc_trace(mVcdFile, ap_done, "(port)ap_done");
    sc_trace(mVcdFile, ap_idle, "(port)ap_idle");
    sc_trace(mVcdFile, ap_ready, "(port)ap_ready");
    sc_trace(mVcdFile, dummy_tmr_out_i, "(port)dummy_tmr_out_i");
    sc_trace(mVcdFile, dummy_tmr_out_o, "(port)dummy_tmr_out_o");
    sc_trace(mVcdFile, dummy_tmr_out_o_ap_vld, "(port)dummy_tmr_out_o_ap_vld");
#endif
#ifdef __HLS_TRACE_LEVEL_INT__
    sc_trace(mVcdFile, ap_CS_fsm, "ap_CS_fsm");
    sc_trace(mVcdFile, ap_sig_cseq_ST_st1_fsm_0, "ap_sig_cseq_ST_st1_fsm_0");
    sc_trace(mVcdFile, ap_sig_20, "ap_sig_20");
    sc_trace(mVcdFile, u_1_fu_67_p2, "u_1_fu_67_p2");
    sc_trace(mVcdFile, u_1_reg_95, "u_1_reg_95");
    sc_trace(mVcdFile, ap_sig_cseq_ST_st2_fsm_1, "ap_sig_cseq_ST_st2_fsm_1");
    sc_trace(mVcdFile, ap_sig_35, "ap_sig_35");
    sc_trace(mVcdFile, t_1_fu_79_p2, "t_1_fu_79_p2");
    sc_trace(mVcdFile, ap_sig_cseq_ST_st3_fsm_2, "ap_sig_cseq_ST_st3_fsm_2");
    sc_trace(mVcdFile, ap_sig_44, "ap_sig_44");
    sc_trace(mVcdFile, u_reg_39, "u_reg_39");
    sc_trace(mVcdFile, exitcond_fu_73_p2, "exitcond_fu_73_p2");
    sc_trace(mVcdFile, t_reg_50, "t_reg_50");
    sc_trace(mVcdFile, exitcond1_fu_61_p2, "exitcond1_fu_61_p2");
    sc_trace(mVcdFile, not_s_fu_85_p2, "not_s_fu_85_p2");
    sc_trace(mVcdFile, ap_NS_fsm, "ap_NS_fsm");
#endif

    }
}

clock_top_wait_tmr::~clock_top_wait_tmr() {
    if (mVcdFile) 
        sc_close_vcd_trace_file(mVcdFile);

}

void clock_top_wait_tmr::thread_ap_clk_no_reset_() {
    if ( ap_rst.read() == ap_const_logic_1) {
        ap_CS_fsm = ap_ST_st1_fsm_0;
    } else {
        ap_CS_fsm = ap_NS_fsm.read();
    }
    if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read()) && 
         esl_seteq<1,1,1>(ap_const_lv1_0, exitcond1_fu_61_p2.read()))) {
        t_reg_50 = ap_const_lv17_0;
    } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st3_fsm_2.read()) && 
                esl_seteq<1,1,1>(exitcond_fu_73_p2.read(), ap_const_lv1_0))) {
        t_reg_50 = t_1_fu_79_p2.read();
    }
    if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st3_fsm_2.read()) && 
         !esl_seteq<1,1,1>(exitcond_fu_73_p2.read(), ap_const_lv1_0))) {
        u_reg_39 = u_1_reg_95.read();
    } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st1_fsm_0.read()) && 
                !esl_seteq<1,1,1>(ap_start.read(), ap_const_logic_0))) {
        u_reg_39 = ap_const_lv7_0;
    }
    if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read())) {
        u_1_reg_95 = u_1_fu_67_p2.read();
    }
}

void clock_top_wait_tmr::thread_ap_done() {
    if (((esl_seteq<1,1,1>(ap_const_logic_0, ap_start.read()) && 
          esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st1_fsm_0.read())) || 
         (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read()) && 
          !esl_seteq<1,1,1>(ap_const_lv1_0, exitcond1_fu_61_p2.read())))) {
        ap_done = ap_const_logic_1;
    } else {
        ap_done = ap_const_logic_0;
    }
}

void clock_top_wait_tmr::thread_ap_idle() {
    if ((esl_seteq<1,1,1>(ap_const_logic_0, ap_start.read()) && 
         esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st1_fsm_0.read()))) {
        ap_idle = ap_const_logic_1;
    } else {
        ap_idle = ap_const_logic_0;
    }
}

void clock_top_wait_tmr::thread_ap_ready() {
    if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read()) && 
         !esl_seteq<1,1,1>(ap_const_lv1_0, exitcond1_fu_61_p2.read()))) {
        ap_ready = ap_const_logic_1;
    } else {
        ap_ready = ap_const_logic_0;
    }
}

void clock_top_wait_tmr::thread_ap_sig_20() {
    ap_sig_20 = esl_seteq<1,1,1>(ap_CS_fsm.read().range(0, 0), ap_const_lv1_1);
}

void clock_top_wait_tmr::thread_ap_sig_35() {
    ap_sig_35 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(1, 1));
}

void clock_top_wait_tmr::thread_ap_sig_44() {
    ap_sig_44 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(2, 2));
}

void clock_top_wait_tmr::thread_ap_sig_cseq_ST_st1_fsm_0() {
    if (ap_sig_20.read()) {
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
    } else {
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
    }
}

void clock_top_wait_tmr::thread_ap_sig_cseq_ST_st2_fsm_1() {
    if (ap_sig_35.read()) {
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
    } else {
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
    }
}

void clock_top_wait_tmr::thread_ap_sig_cseq_ST_st3_fsm_2() {
    if (ap_sig_44.read()) {
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
    } else {
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
    }
}

void clock_top_wait_tmr::thread_dummy_tmr_out_o() {
    if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st3_fsm_2.read()) && 
         esl_seteq<1,1,1>(exitcond_fu_73_p2.read(), ap_const_lv1_0))) {
        dummy_tmr_out_o = not_s_fu_85_p2.read();
    } else {
        dummy_tmr_out_o = dummy_tmr_out_i.read();
    }
}

void clock_top_wait_tmr::thread_dummy_tmr_out_o_ap_vld() {
    if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st3_fsm_2.read()) && 
         esl_seteq<1,1,1>(exitcond_fu_73_p2.read(), ap_const_lv1_0))) {
        dummy_tmr_out_o_ap_vld = ap_const_logic_1;
    } else {
        dummy_tmr_out_o_ap_vld = ap_const_logic_0;
    }
}

void clock_top_wait_tmr::thread_exitcond1_fu_61_p2() {
    exitcond1_fu_61_p2 = (!u_reg_39.read().is_01() || !ap_const_lv7_64.is_01())? sc_lv<1>(): sc_lv<1>(u_reg_39.read() == ap_const_lv7_64);
}

void clock_top_wait_tmr::thread_exitcond_fu_73_p2() {
    exitcond_fu_73_p2 = (!t_reg_50.read().is_01() || !ap_const_lv17_186A0.is_01())? sc_lv<1>(): sc_lv<1>(t_reg_50.read() == ap_const_lv17_186A0);
}

void clock_top_wait_tmr::thread_not_s_fu_85_p2() {
    not_s_fu_85_p2 = (dummy_tmr_out_i.read() ^ ap_const_lv1_1);
}

void clock_top_wait_tmr::thread_t_1_fu_79_p2() {
    t_1_fu_79_p2 = (!t_reg_50.read().is_01() || !ap_const_lv17_1.is_01())? sc_lv<17>(): (sc_biguint<17>(t_reg_50.read()) + sc_biguint<17>(ap_const_lv17_1));
}

void clock_top_wait_tmr::thread_u_1_fu_67_p2() {
    u_1_fu_67_p2 = (!u_reg_39.read().is_01() || !ap_const_lv7_1.is_01())? sc_lv<7>(): (sc_biguint<7>(u_reg_39.read()) + sc_biguint<7>(ap_const_lv7_1));
}

void clock_top_wait_tmr::thread_ap_NS_fsm() {
    switch (ap_CS_fsm.read().to_uint64()) {
        case 1 : 
            if (!esl_seteq<1,1,1>(ap_start.read(), ap_const_logic_0)) {
                ap_NS_fsm = ap_ST_st2_fsm_1;
            } else {
                ap_NS_fsm = ap_ST_st1_fsm_0;
            }
            break;
        case 2 : 
            if (!esl_seteq<1,1,1>(ap_const_lv1_0, exitcond1_fu_61_p2.read())) {
                ap_NS_fsm = ap_ST_st1_fsm_0;
            } else {
                ap_NS_fsm = ap_ST_st3_fsm_2;
            }
            break;
        case 4 : 
            if (esl_seteq<1,1,1>(exitcond_fu_73_p2.read(), ap_const_lv1_0)) {
                ap_NS_fsm = ap_ST_st3_fsm_2;
            } else {
                ap_NS_fsm = ap_ST_st2_fsm_1;
            }
            break;
        default : 
            ap_NS_fsm = "XXX";
            break;
    }
}

}

