; ModuleID = 'D:/20_sample_artix7/clock/solution1/.autopilot/db/a.o.2.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-w64-mingw32"

@mem_wreq = global i1 false, align 1              ; [#uses=5 type=i1*]
@mem_dout = global i8 0, align 1                  ; [#uses=5 type=i8*]
@mem_addr = global i8 0, align 1                  ; [#uses=5 type=i8*]
@mem_ack = common global i1 false, align 1        ; [#uses=3 type=i1*]
@dummy_tmr_out = global i1 false, align 1         ; [#uses=4 type=i1*]
@.str1 = private unnamed_addr constant [8 x i8] c"ap_none\00", align 1 ; [#uses=5 type=[8 x i8]*]
@.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1 ; [#uses=20 type=[1 x i8]*]

; [#uses=8]
define internal fastcc void @write_mem(i7 zeroext %addr, i8 %data) {
  %addr.cast = zext i7 %addr to i8                ; [#uses=4 type=i8]
  call void (...)* @_ssdm_SpecKeepAssert(i8 %addr.cast) nounwind, !hlsrange !42
  call void @llvm.dbg.value(metadata !{i7 %addr}, i64 0, metadata !43), !dbg !49 ; [debug line = 69:22] [debug variable = addr]
  call void @llvm.dbg.value(metadata !{i8 %data}, i64 0, metadata !50), !dbg !51 ; [debug line = 69:34] [debug variable = data]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !52 ; [debug line = 72:2]
  store volatile i8 %addr.cast, i8* @mem_addr, align 1, !dbg !54 ; [debug line = 73:2]
  store volatile i8 %data, i8* @mem_dout, align 1, !dbg !55 ; [debug line = 74:2]
  store volatile i1 false, i1* @mem_wreq, align 1, !dbg !56 ; [debug line = 75:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !57 ; [debug line = 76:2]
  br label %._crit_edge, !dbg !58                 ; [debug line = 78:2]

._crit_edge:                                      ; preds = %._crit_edge, %0
  store volatile i8 %addr.cast, i8* @mem_addr, align 1, !dbg !59 ; [debug line = 79:3]
  store volatile i8 %data, i8* @mem_dout, align 1, !dbg !61 ; [debug line = 80:3]
  store volatile i1 true, i1* @mem_wreq, align 1, !dbg !62 ; [debug line = 81:3]
  %mem_ack.load = load volatile i1* @mem_ack, align 1, !dbg !63 ; [#uses=1 type=i1] [debug line = 82:2]
  br i1 %mem_ack.load, label %1, label %._crit_edge, !dbg !63 ; [debug line = 82:2]

; <label>:1                                       ; preds = %._crit_edge
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !64 ; [debug line = 83:2]
  store volatile i8 %addr.cast, i8* @mem_addr, align 1, !dbg !65 ; [debug line = 85:2]
  store volatile i8 %data, i8* @mem_dout, align 1, !dbg !66 ; [debug line = 86:2]
  store volatile i1 false, i1* @mem_wreq, align 1, !dbg !67 ; [debug line = 87:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !68 ; [debug line = 88:2]
  ret void, !dbg !69                              ; [debug line = 89:1]
}

; [#uses=1]
define internal fastcc void @wait_tmr() nounwind uwtable {
  br label %1, !dbg !70                           ; [debug line = 62:7]

; <label>:1                                       ; preds = %5, %0
  %u = phi i7 [ 0, %0 ], [ %u.1, %5 ]             ; [#uses=2 type=i7]
  %exitcond1 = icmp eq i7 %u, -28, !dbg !70       ; [#uses=1 type=i1] [debug line = 62:7]
  %2 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 100, i64 100, i64 100) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond1, label %6, label %.preheader.preheader, !dbg !70 ; [debug line = 62:7]

.preheader.preheader:                             ; preds = %1
  br label %.preheader, !dbg !78                  ; [debug line = 63:8]

.preheader:                                       ; preds = %4, %.preheader.preheader
  %t = phi i17 [ %t.1, %4 ], [ 0, %.preheader.preheader ] ; [#uses=2 type=i17]
  %exitcond = icmp eq i17 %t, -31072, !dbg !78    ; [#uses=1 type=i1] [debug line = 63:8]
  %3 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 100000, i64 100000, i64 100000) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond, label %5, label %4, !dbg !78   ; [debug line = 63:8]

; <label>:4                                       ; preds = %.preheader
  %dummy_tmr_out.load = load volatile i1* @dummy_tmr_out, align 1, !dbg !81 ; [#uses=1 type=i1] [debug line = 64:4]
  %not. = xor i1 %dummy_tmr_out.load, true, !dbg !81 ; [#uses=1 type=i1] [debug line = 64:4]
  store volatile i1 %not., i1* @dummy_tmr_out, align 1, !dbg !81 ; [debug line = 64:4]
  %t.1 = add i17 %t, 1, !dbg !83                  ; [#uses=1 type=i17] [debug line = 63:24]
  call void @llvm.dbg.value(metadata !{i17 %t.1}, i64 0, metadata !84), !dbg !83 ; [debug line = 63:24] [debug variable = t]
  br label %.preheader, !dbg !83                  ; [debug line = 63:24]

; <label>:5                                       ; preds = %.preheader
  %u.1 = add i7 %u, 1, !dbg !85                   ; [#uses=1 type=i7] [debug line = 62:23]
  call void @llvm.dbg.value(metadata !{i7 %u.1}, i64 0, metadata !86), !dbg !85 ; [debug line = 62:23] [debug variable = u]
  br label %1, !dbg !85                           ; [debug line = 62:23]

; <label>:6                                       ; preds = %1
  ret void, !dbg !87                              ; [debug line = 67:1]
}

; [#uses=10]
declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone

; [#uses=0]
define void @clock_top() noreturn nounwind uwtable {
  call void (...)* @_ssdm_op_SpecTopModule(), !dbg !88 ; [debug line = 93:1]
  %dummy_tmr_out.load = load volatile i1* @dummy_tmr_out, align 1, !dbg !93 ; [#uses=0 type=i1] [debug line = 94:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @dummy_tmr_out, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !93 ; [debug line = 94:1]
  %mem_addr.load = load volatile i8* @mem_addr, align 1, !dbg !94 ; [#uses=0 type=i8] [debug line = 96:1]
  call void (...)* @_ssdm_op_SpecInterface(i8* @mem_addr, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !94 ; [debug line = 96:1]
  %mem_dout.load = load volatile i8* @mem_dout, align 1, !dbg !95 ; [#uses=0 type=i8] [debug line = 97:1]
  call void (...)* @_ssdm_op_SpecInterface(i8* @mem_dout, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !95 ; [debug line = 97:1]
  %mem_wreq.load = load volatile i1* @mem_wreq, align 1, !dbg !96 ; [#uses=0 type=i1] [debug line = 98:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @mem_wreq, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !96 ; [debug line = 98:1]
  %mem_ack.load = load volatile i1* @mem_ack, align 1, !dbg !97 ; [#uses=0 type=i1] [debug line = 99:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @mem_ack, [8 x i8]* @.str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !97 ; [debug line = 99:1]
  br label %1, !dbg !98                           ; [debug line = 108:7]

; <label>:1                                       ; preds = %3, %0
  %pos = phi i6 [ 0, %0 ], [ %pos.1, %3 ]         ; [#uses=3 type=i6]
  %exitcond = icmp eq i6 %pos, -32, !dbg !98      ; [#uses=1 type=i1] [debug line = 108:7]
  %2 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond, label %.preheader.preheader, label %3, !dbg !98 ; [debug line = 108:7]

.preheader.preheader:                             ; preds = %1
  br label %.preheader, !dbg !100                 ; [debug line = 113:3]

; <label>:3                                       ; preds = %1
  %pos.cast1.cast = zext i6 %pos to i7, !dbg !102 ; [#uses=1 type=i7] [debug line = 109:3]
  call fastcc void @write_mem(i7 zeroext %pos.cast1.cast, i8 zeroext 32) nounwind, !dbg !102 ; [debug line = 109:3]
  %pos.1 = add i6 %pos, 1, !dbg !104              ; [#uses=1 type=i6] [debug line = 108:26]
  call void @llvm.dbg.value(metadata !{i6 %pos.1}, i64 0, metadata !105), !dbg !104 ; [debug line = 108:26] [debug variable = pos]
  br label %1, !dbg !104                          ; [debug line = 108:26]

.preheader:                                       ; preds = %.preheader.backedge, %.preheader.preheader
  %min = phi i8 [ 48, %.preheader.preheader ], [ %min.be, %.preheader.backedge ] ; [#uses=6 type=i8]
  %min1 = phi i8 [ 48, %.preheader.preheader ], [ %min1.be, %.preheader.backedge ] ; [#uses=5 type=i8]
  %sec = phi i8 [ 48, %.preheader.preheader ], [ %sec.be, %.preheader.backedge ] ; [#uses=4 type=i8]
  %sec1 = phi i8 [ 48, %.preheader.preheader ], [ %sec1.be, %.preheader.backedge ] ; [#uses=3 type=i8]
  %msec = phi i8 [ 48, %.preheader.preheader ], [ %msec.be, %.preheader.backedge ] ; [#uses=2 type=i8]
  call fastcc void @write_mem(i7 zeroext 16, i8 zeroext %min) nounwind, !dbg !100 ; [debug line = 113:3]
  call fastcc void @write_mem(i7 zeroext 17, i8 zeroext %min1) nounwind, !dbg !106 ; [debug line = 114:3]
  call fastcc void @write_mem(i7 zeroext 18, i8 zeroext 58) nounwind, !dbg !107 ; [debug line = 115:3]
  call fastcc void @write_mem(i7 zeroext 19, i8 zeroext %sec) nounwind, !dbg !108 ; [debug line = 116:3]
  call fastcc void @write_mem(i7 zeroext 20, i8 zeroext %sec1) nounwind, !dbg !109 ; [debug line = 117:3]
  call fastcc void @write_mem(i7 zeroext 21, i8 zeroext 46) nounwind, !dbg !110 ; [debug line = 118:3]
  call fastcc void @write_mem(i7 zeroext 22, i8 zeroext %msec) nounwind, !dbg !111 ; [debug line = 119:3]
  call fastcc void @wait_tmr(), !dbg !112         ; [debug line = 121:3]
  %msec.1 = add i8 %msec, 1, !dbg !113            ; [#uses=2 type=i8] [debug line = 124:3]
  call void @llvm.dbg.value(metadata !{i8 %msec.1}, i64 0, metadata !114), !dbg !113 ; [debug line = 124:3] [debug variable = msec]
  %tmp.7 = icmp ugt i8 %msec.1, 57, !dbg !115     ; [#uses=1 type=i1] [debug line = 125:3]
  br i1 %tmp.7, label %4, label %.preheader.backedge, !dbg !115 ; [debug line = 125:3]

; <label>:4                                       ; preds = %.preheader
  %sec1.1 = add i8 %sec1, 1, !dbg !116            ; [#uses=2 type=i8] [debug line = 127:4]
  call void @llvm.dbg.value(metadata !{i8 %sec1.1}, i64 0, metadata !118), !dbg !116 ; [debug line = 127:4] [debug variable = sec1]
  %tmp.9 = icmp ugt i8 %sec1.1, 57, !dbg !119     ; [#uses=1 type=i1] [debug line = 128:4]
  br i1 %tmp.9, label %5, label %.preheader.backedge, !dbg !119 ; [debug line = 128:4]

; <label>:5                                       ; preds = %4
  %sec10 = add i8 %sec, 1, !dbg !120              ; [#uses=2 type=i8] [debug line = 130:5]
  call void @llvm.dbg.value(metadata !{i8 %sec10}, i64 0, metadata !122), !dbg !120 ; [debug line = 130:5] [debug variable = sec10]
  %tmp. = icmp ugt i8 %sec10, 53, !dbg !123       ; [#uses=1 type=i1] [debug line = 131:5]
  br i1 %tmp., label %6, label %.preheader.backedge, !dbg !123 ; [debug line = 131:5]

; <label>:6                                       ; preds = %5
  %min1.1 = add i8 %min1, 1, !dbg !124            ; [#uses=2 type=i8] [debug line = 133:6]
  call void @llvm.dbg.value(metadata !{i8 %min1.1}, i64 0, metadata !126), !dbg !124 ; [debug line = 133:6] [debug variable = min1]
  %tmp.1 = icmp ugt i8 %min1.1, 57, !dbg !127     ; [#uses=1 type=i1] [debug line = 134:6]
  br i1 %tmp.1, label %7, label %.preheader.backedge, !dbg !127 ; [debug line = 134:6]

; <label>:7                                       ; preds = %6
  %min10 = add i8 %min, 1, !dbg !128              ; [#uses=2 type=i8] [debug line = 136:7]
  %min10.cast = trunc i8 %min10 to i6, !dbg !128  ; [#uses=1 type=i6] [debug line = 136:7]
  call void @llvm.dbg.value(metadata !{i8 %min10}, i64 0, metadata !130), !dbg !128 ; [debug line = 136:7] [debug variable = min10]
  %tmp.2 = icmp ugt i8 %min10, 53, !dbg !131      ; [#uses=1 type=i1] [debug line = 137:7]
  %. = select i1 %tmp.2, i6 -16, i6 %min10.cast, !dbg !131 ; [#uses=1 type=i6] [debug line = 137:7]
  %..cast = zext i6 %. to i8, !dbg !131           ; [#uses=1 type=i8] [debug line = 137:7]
  br label %.preheader.backedge, !dbg !132        ; [debug line = 140:6]

.preheader.backedge:                              ; preds = %7, %6, %5, %4, %.preheader
  %min.be = phi i8 [ %..cast, %7 ], [ %min, %.preheader ], [ %min, %4 ], [ %min, %5 ], [ %min, %6 ] ; [#uses=1 type=i8]
  %min1.be = phi i8 [ 48, %7 ], [ %min1, %.preheader ], [ %min1, %4 ], [ %min1, %5 ], [ %min1.1, %6 ] ; [#uses=1 type=i8]
  %sec.be = phi i8 [ 48, %7 ], [ %sec, %.preheader ], [ %sec, %4 ], [ %sec10, %5 ], [ 48, %6 ] ; [#uses=1 type=i8]
  %sec1.be = phi i8 [ 48, %7 ], [ %sec1, %.preheader ], [ %sec1.1, %4 ], [ 48, %5 ], [ 48, %6 ] ; [#uses=1 type=i8]
  %msec.be = phi i8 [ 48, %7 ], [ %msec.1, %.preheader ], [ 48, %4 ], [ 48, %5 ], [ 48, %6 ] ; [#uses=1 type=i8]
  br label %.preheader
}

; [#uses=4]
declare void @_ssdm_op_Wait(...) nounwind

; [#uses=1]
declare void @_ssdm_op_SpecTopModule(...) nounwind

; [#uses=3]
declare i32 @_ssdm_op_SpecLoopTripCount(...)

; [#uses=5]
declare void @_ssdm_op_SpecInterface(...) nounwind

; [#uses=1]
declare void @_ssdm_SpecKeepAssert(...)

!hls.encrypted.func = !{}
!llvm.map.gv = !{!0, !7, !12, !17, !22}
!llvm.dbg.cu = !{!27}

!0 = metadata !{metadata !1, i1* @mem_wreq}
!1 = metadata !{metadata !2}
!2 = metadata !{i32 0, i32 0, metadata !3}
!3 = metadata !{metadata !4}
!4 = metadata !{metadata !"mem_wreq", metadata !5, metadata !"uint1", i32 0, i32 0}
!5 = metadata !{metadata !6}
!6 = metadata !{i32 0, i32 0, i32 1}
!7 = metadata !{metadata !8, i8* @mem_dout}
!8 = metadata !{metadata !9}
!9 = metadata !{i32 0, i32 7, metadata !10}
!10 = metadata !{metadata !11}
!11 = metadata !{metadata !"mem_dout", metadata !5, metadata !"uint8", i32 0, i32 7}
!12 = metadata !{metadata !13, i8* @mem_addr}
!13 = metadata !{metadata !14}
!14 = metadata !{i32 0, i32 7, metadata !15}
!15 = metadata !{metadata !16}
!16 = metadata !{metadata !"mem_addr", metadata !5, metadata !"uint8", i32 0, i32 7}
!17 = metadata !{metadata !18, i1* @mem_ack}
!18 = metadata !{metadata !19}
!19 = metadata !{i32 0, i32 0, metadata !20}
!20 = metadata !{metadata !21}
!21 = metadata !{metadata !"mem_ack", metadata !5, metadata !"uint1", i32 0, i32 0}
!22 = metadata !{metadata !23, i1* @dummy_tmr_out}
!23 = metadata !{metadata !24}
!24 = metadata !{i32 0, i32 0, metadata !25}
!25 = metadata !{metadata !26}
!26 = metadata !{metadata !"dummy_tmr_out", metadata !5, metadata !"uint1", i32 0, i32 0}
!27 = metadata !{i32 786449, i32 0, i32 1, metadata !"D:/20_sample_artix7/clock/solution1/.autopilot/db/clock.pragma.2.c", metadata !"D:\5C20_sample_artix7", metadata !"clang version 3.1 ", i1 true, i1 false, metadata !"", i32 0, null, null, null, metadata !28} ; [ DW_TAG_compile_unit ]
!28 = metadata !{metadata !29}
!29 = metadata !{metadata !30, metadata !35, metadata !36, metadata !40, metadata !41}
!30 = metadata !{i32 786484, i32 0, null, metadata !"mem_addr", metadata !"mem_addr", metadata !"", metadata !31, i32 46, metadata !32, i32 0, i32 1, i8* @mem_addr} ; [ DW_TAG_variable ]
!31 = metadata !{i32 786473, metadata !"clock.c", metadata !"D:\5C20_sample_artix7", null} ; [ DW_TAG_file_type ]
!32 = metadata !{i32 786485, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_volatile_type ]
!33 = metadata !{i32 786454, null, metadata !"uint8", metadata !31, i32 10, i64 0, i64 0, i64 0, i32 0, metadata !34} ; [ DW_TAG_typedef ]
!34 = metadata !{i32 786468, null, metadata !"uint8", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
!35 = metadata !{i32 786484, i32 0, null, metadata !"mem_dout", metadata !"mem_dout", metadata !"", metadata !31, i32 47, metadata !32, i32 0, i32 1, i8* @mem_dout} ; [ DW_TAG_variable ]
!36 = metadata !{i32 786484, i32 0, null, metadata !"mem_wreq", metadata !"mem_wreq", metadata !"", metadata !31, i32 48, metadata !37, i32 0, i32 1, i1* @mem_wreq} ; [ DW_TAG_variable ]
!37 = metadata !{i32 786485, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !38} ; [ DW_TAG_volatile_type ]
!38 = metadata !{i32 786454, null, metadata !"uint1", metadata !31, i32 3, i64 0, i64 0, i64 0, i32 0, metadata !39} ; [ DW_TAG_typedef ]
!39 = metadata !{i32 786468, null, metadata !"uint1", null, i32 0, i64 1, i64 1, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
!40 = metadata !{i32 786484, i32 0, null, metadata !"mem_ack", metadata !"mem_ack", metadata !"", metadata !31, i32 49, metadata !37, i32 0, i32 1, i1* @mem_ack} ; [ DW_TAG_variable ]
!41 = metadata !{i32 786484, i32 0, null, metadata !"dummy_tmr_out", metadata !"dummy_tmr_out", metadata !"", metadata !31, i32 51, metadata !37, i32 0, i32 1, i1* @dummy_tmr_out} ; [ DW_TAG_variable ]
!42 = metadata !{i7 0, i7 31, i7 0, i7 31}        
!43 = metadata !{i32 786689, metadata !44, metadata !"addr", metadata !31, i32 16777285, metadata !33, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
!44 = metadata !{i32 786478, i32 0, metadata !31, metadata !"write_mem", metadata !"write_mem", metadata !"", metadata !31, i32 69, metadata !45, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, null, metadata !47, i32 70} ; [ DW_TAG_subprogram ]
!45 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !46, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!46 = metadata !{null, metadata !33, metadata !33}
!47 = metadata !{metadata !48}
!48 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
!49 = metadata !{i32 69, i32 22, metadata !44, null}
!50 = metadata !{i32 786689, metadata !44, metadata !"data", metadata !31, i32 33554501, metadata !33, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
!51 = metadata !{i32 69, i32 34, metadata !44, null}
!52 = metadata !{i32 72, i32 2, metadata !53, null}
!53 = metadata !{i32 786443, metadata !44, i32 70, i32 1, metadata !31, i32 5} ; [ DW_TAG_lexical_block ]
!54 = metadata !{i32 73, i32 2, metadata !53, null}
!55 = metadata !{i32 74, i32 2, metadata !53, null}
!56 = metadata !{i32 75, i32 2, metadata !53, null}
!57 = metadata !{i32 76, i32 2, metadata !53, null}
!58 = metadata !{i32 78, i32 2, metadata !53, null}
!59 = metadata !{i32 79, i32 3, metadata !60, null}
!60 = metadata !{i32 786443, metadata !53, i32 78, i32 5, metadata !31, i32 6} ; [ DW_TAG_lexical_block ]
!61 = metadata !{i32 80, i32 3, metadata !60, null}
!62 = metadata !{i32 81, i32 3, metadata !60, null}
!63 = metadata !{i32 82, i32 2, metadata !60, null}
!64 = metadata !{i32 83, i32 2, metadata !53, null}
!65 = metadata !{i32 85, i32 2, metadata !53, null}
!66 = metadata !{i32 86, i32 2, metadata !53, null}
!67 = metadata !{i32 87, i32 2, metadata !53, null}
!68 = metadata !{i32 88, i32 2, metadata !53, null}
!69 = metadata !{i32 89, i32 1, metadata !53, null}
!70 = metadata !{i32 62, i32 7, metadata !71, null}
!71 = metadata !{i32 786443, metadata !72, i32 62, i32 2, metadata !31, i32 1} ; [ DW_TAG_lexical_block ]
!72 = metadata !{i32 786443, metadata !73, i32 58, i32 1, metadata !31, i32 0} ; [ DW_TAG_lexical_block ]
!73 = metadata !{i32 786478, i32 0, metadata !31, metadata !"wait_tmr", metadata !"wait_tmr", metadata !"", metadata !31, i32 57, metadata !74, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, null, metadata !47, i32 58} ; [ DW_TAG_subprogram ]
!74 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !75, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!75 = metadata !{null, metadata !76}
!76 = metadata !{i32 786454, null, metadata !"uint32", metadata !31, i32 34, i64 0, i64 0, i64 0, i32 0, metadata !77} ; [ DW_TAG_typedef ]
!77 = metadata !{i32 786468, null, metadata !"uint32", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
!78 = metadata !{i32 63, i32 8, metadata !79, null}
!79 = metadata !{i32 786443, metadata !80, i32 63, i32 3, metadata !31, i32 3} ; [ DW_TAG_lexical_block ]
!80 = metadata !{i32 786443, metadata !71, i32 62, i32 28, metadata !31, i32 2} ; [ DW_TAG_lexical_block ]
!81 = metadata !{i32 64, i32 4, metadata !82, null}
!82 = metadata !{i32 786443, metadata !79, i32 63, i32 29, metadata !31, i32 4} ; [ DW_TAG_lexical_block ]
!83 = metadata !{i32 63, i32 24, metadata !79, null}
!84 = metadata !{i32 786688, metadata !72, metadata !"t", metadata !31, i32 61, metadata !76, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!85 = metadata !{i32 62, i32 23, metadata !71, null}
!86 = metadata !{i32 786688, metadata !72, metadata !"u", metadata !31, i32 60, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!87 = metadata !{i32 67, i32 1, metadata !72, null}
!88 = metadata !{i32 93, i32 1, metadata !89, null}
!89 = metadata !{i32 786443, metadata !90, i32 92, i32 1, metadata !31, i32 7} ; [ DW_TAG_lexical_block ]
!90 = metadata !{i32 786478, i32 0, metadata !31, metadata !"clock_top", metadata !"clock_top", metadata !"", metadata !31, i32 91, metadata !91, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @clock_top, null, null, metadata !47, i32 92} ; [ DW_TAG_subprogram ]
!91 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !92, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!92 = metadata !{null}
!93 = metadata !{i32 94, i32 1, metadata !89, null}
!94 = metadata !{i32 96, i32 1, metadata !89, null}
!95 = metadata !{i32 97, i32 1, metadata !89, null}
!96 = metadata !{i32 98, i32 1, metadata !89, null}
!97 = metadata !{i32 99, i32 1, metadata !89, null}
!98 = metadata !{i32 108, i32 7, metadata !99, null}
!99 = metadata !{i32 786443, metadata !89, i32 108, i32 2, metadata !31, i32 8} ; [ DW_TAG_lexical_block ]
!100 = metadata !{i32 113, i32 3, metadata !101, null}
!101 = metadata !{i32 786443, metadata !89, i32 112, i32 12, metadata !31, i32 10} ; [ DW_TAG_lexical_block ]
!102 = metadata !{i32 109, i32 3, metadata !103, null}
!103 = metadata !{i32 786443, metadata !99, i32 108, i32 33, metadata !31, i32 9} ; [ DW_TAG_lexical_block ]
!104 = metadata !{i32 108, i32 26, metadata !99, null}
!105 = metadata !{i32 786688, metadata !89, metadata !"pos", metadata !31, i32 101, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!106 = metadata !{i32 114, i32 3, metadata !101, null}
!107 = metadata !{i32 115, i32 3, metadata !101, null}
!108 = metadata !{i32 116, i32 3, metadata !101, null}
!109 = metadata !{i32 117, i32 3, metadata !101, null}
!110 = metadata !{i32 118, i32 3, metadata !101, null}
!111 = metadata !{i32 119, i32 3, metadata !101, null}
!112 = metadata !{i32 121, i32 3, metadata !101, null}
!113 = metadata !{i32 124, i32 3, metadata !101, null}
!114 = metadata !{i32 786688, metadata !89, metadata !"msec", metadata !31, i32 102, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!115 = metadata !{i32 125, i32 3, metadata !101, null}
!116 = metadata !{i32 127, i32 4, metadata !117, null}
!117 = metadata !{i32 786443, metadata !101, i32 125, i32 19, metadata !31, i32 11} ; [ DW_TAG_lexical_block ]
!118 = metadata !{i32 786688, metadata !89, metadata !"sec1", metadata !31, i32 103, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!119 = metadata !{i32 128, i32 4, metadata !117, null}
!120 = metadata !{i32 130, i32 5, metadata !121, null}
!121 = metadata !{i32 786443, metadata !117, i32 128, i32 20, metadata !31, i32 12} ; [ DW_TAG_lexical_block ]
!122 = metadata !{i32 786688, metadata !89, metadata !"sec10", metadata !31, i32 104, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!123 = metadata !{i32 131, i32 5, metadata !121, null}
!124 = metadata !{i32 133, i32 6, metadata !125, null}
!125 = metadata !{i32 786443, metadata !121, i32 131, i32 22, metadata !31, i32 13} ; [ DW_TAG_lexical_block ]
!126 = metadata !{i32 786688, metadata !89, metadata !"min1", metadata !31, i32 105, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!127 = metadata !{i32 134, i32 6, metadata !125, null}
!128 = metadata !{i32 136, i32 7, metadata !129, null}
!129 = metadata !{i32 786443, metadata !125, i32 134, i32 22, metadata !31, i32 14} ; [ DW_TAG_lexical_block ]
!130 = metadata !{i32 786688, metadata !89, metadata !"min10", metadata !31, i32 106, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
!131 = metadata !{i32 137, i32 7, metadata !129, null}
!132 = metadata !{i32 140, i32 6, metadata !129, null}
