// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="lcddrv,hls_ip_2016_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a35ticsg324-1l,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.862312,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=263,HLS_SYN_LUT=430}" *)

module lcddrv (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        dummy_tmr_out_i,
        dummy_tmr_out_o,
        rs_i,
        rs_o,
        en_i,
        en_o,
        data_i,
        data_o,
        ind,
        mem_addr_i,
        mem_addr_o,
        mem_din,
        mem_req_i,
        mem_req_o,
        mem_ack
);

parameter    ap_ST_st1_fsm_0 = 22'b1;
parameter    ap_ST_st2_fsm_1 = 22'b10;
parameter    ap_ST_st3_fsm_2 = 22'b100;
parameter    ap_ST_st4_fsm_3 = 22'b1000;
parameter    ap_ST_st5_fsm_4 = 22'b10000;
parameter    ap_ST_st6_fsm_5 = 22'b100000;
parameter    ap_ST_st7_fsm_6 = 22'b1000000;
parameter    ap_ST_st8_fsm_7 = 22'b10000000;
parameter    ap_ST_st9_fsm_8 = 22'b100000000;
parameter    ap_ST_st10_fsm_9 = 22'b1000000000;
parameter    ap_ST_st11_fsm_10 = 22'b10000000000;
parameter    ap_ST_st12_fsm_11 = 22'b100000000000;
parameter    ap_ST_st13_fsm_12 = 22'b1000000000000;
parameter    ap_ST_st14_fsm_13 = 22'b10000000000000;
parameter    ap_ST_st15_fsm_14 = 22'b100000000000000;
parameter    ap_ST_st16_fsm_15 = 22'b1000000000000000;
parameter    ap_ST_st17_fsm_16 = 22'b10000000000000000;
parameter    ap_ST_st18_fsm_17 = 22'b100000000000000000;
parameter    ap_ST_st19_fsm_18 = 22'b1000000000000000000;
parameter    ap_ST_st20_fsm_19 = 22'b10000000000000000000;
parameter    ap_ST_st21_fsm_20 = 22'b100000000000000000000;
parameter    ap_ST_st22_fsm_21 = 22'b1000000000000000000000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv4_0 = 4'b0000;
parameter    ap_const_lv5_0 = 5'b00000;
parameter    ap_const_lv32_9 = 32'b1001;
parameter    ap_const_lv32_11 = 32'b10001;
parameter    ap_const_lv32_8 = 32'b1000;
parameter    ap_const_lv32_10 = 32'b10000;
parameter    ap_const_lv32_7 = 32'b111;
parameter    ap_const_lv32_C = 32'b1100;
parameter    ap_const_lv6_10 = 6'b10000;
parameter    ap_const_lv32_F = 32'b1111;
parameter    ap_const_lv32_14 = 32'b10100;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv32_4 = 32'b100;
parameter    ap_const_lv32_6 = 32'b110;
parameter    ap_const_lv32_B = 32'b1011;
parameter    ap_const_lv32_E = 32'b1110;
parameter    ap_const_lv32_13 = 32'b10011;
parameter    ap_const_lv32_5 = 32'b101;
parameter    ap_const_lv32_D = 32'b1101;
parameter    ap_const_lv32_A = 32'b1010;
parameter    ap_const_lv32_12 = 32'b10010;
parameter    ap_const_lv4_8 = 4'b1000;
parameter    ap_const_lv4_C = 4'b1100;
parameter    ap_const_lv25_989680 = 25'b100110001001011010000000;
parameter    ap_const_lv32_15 = 32'b10101;
parameter    ap_const_lv5_10 = 5'b10000;
parameter    ap_const_lv5_1 = 5'b1;
parameter    ap_const_lv6_20 = 6'b100000;
parameter    ap_const_lv6_1 = 6'b1;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [0:0] dummy_tmr_out_i;
output  [0:0] dummy_tmr_out_o;
input  [0:0] rs_i;
output  [0:0] rs_o;
input  [0:0] en_i;
output  [0:0] en_o;
input  [3:0] data_i;
output  [3:0] data_o;
input  [0:0] ind;
input  [4:0] mem_addr_i;
output  [4:0] mem_addr_o;
input  [7:0] mem_din;
input  [0:0] mem_req_i;
output  [0:0] mem_req_o;
input  [0:0] mem_ack;

reg ap_idle;

(* fsm_encoding = "none" *) reg   [21:0] ap_CS_fsm;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_37;
reg   [0:0] dummy_tmr_out_0_data_reg;
reg    dummy_tmr_out_0_vld_reg;
wire    dummy_tmr_out_0_ack_out;
reg   [0:0] dummy_tmr_out_1_data_reg;
reg   [0:0] dummy_tmr_out_1_data_in;
reg    dummy_tmr_out_1_vld_reg;
reg    dummy_tmr_out_1_vld_in;
reg   [0:0] rs_1_data_reg;
reg   [0:0] rs_1_data_in;
reg    rs_1_vld_reg;
reg    rs_1_vld_in;
reg   [0:0] en_1_data_reg;
reg   [0:0] en_1_data_in;
reg    en_1_vld_reg;
reg    en_1_vld_in;
reg   [3:0] data_1_data_reg;
reg   [3:0] data_1_data_in;
reg    data_1_vld_reg;
reg    data_1_vld_in;
reg   [4:0] mem_addr_1_data_reg;
reg    mem_addr_1_vld_reg;
reg    mem_addr_1_vld_in;
reg   [0:0] mem_req_1_data_reg;
reg    mem_req_1_vld_reg;
reg    mem_req_1_vld_in;
reg   [3:0] reg_231;
reg    ap_sig_cseq_ST_st10_fsm_9;
reg    ap_sig_381;
wire    grp_lcddrv_read_mem_fu_206_ap_done;
reg    ap_sig_cseq_ST_st18_fsm_17;
reg    ap_sig_392;
wire   [4:0] pos_2_fu_242_p2;
reg   [4:0] pos_2_reg_276;
reg    ap_sig_cseq_ST_st9_fsm_8;
reg    ap_sig_403;
wire   [3:0] tmp_2_fu_248_p1;
reg   [3:0] tmp_2_reg_281;
wire   [4:0] tmp_3_fu_258_p1;
reg   [4:0] tmp_3_reg_289;
reg    ap_sig_cseq_ST_st17_fsm_16;
reg    ap_sig_414;
wire   [0:0] exitcond_fu_252_p2;
wire   [5:0] pos_3_fu_263_p2;
reg   [5:0] pos_3_reg_294;
wire   [3:0] tmp_4_fu_269_p1;
reg   [3:0] tmp_4_reg_299;
wire    grp_lcddrv_init_lcd_fu_167_ap_start;
wire    grp_lcddrv_init_lcd_fu_167_ap_done;
wire    grp_lcddrv_init_lcd_fu_167_ap_idle;
wire    grp_lcddrv_init_lcd_fu_167_ap_ready;
wire   [0:0] grp_lcddrv_init_lcd_fu_167_dummy_tmr_out_o;
wire    grp_lcddrv_init_lcd_fu_167_dummy_tmr_out_o_ap_vld;
wire   [0:0] grp_lcddrv_init_lcd_fu_167_en;
wire    grp_lcddrv_init_lcd_fu_167_en_ap_vld;
wire   [0:0] grp_lcddrv_init_lcd_fu_167_rs;
wire    grp_lcddrv_init_lcd_fu_167_rs_ap_vld;
wire   [3:0] grp_lcddrv_init_lcd_fu_167_data;
wire    grp_lcddrv_init_lcd_fu_167_data_ap_vld;
wire    grp_lcddrv_lcd_send_cmd_fu_179_ap_start;
wire    grp_lcddrv_lcd_send_cmd_fu_179_ap_done;
wire    grp_lcddrv_lcd_send_cmd_fu_179_ap_idle;
wire    grp_lcddrv_lcd_send_cmd_fu_179_ap_ready;
reg   [0:0] grp_lcddrv_lcd_send_cmd_fu_179_mode;
reg   [3:0] grp_lcddrv_lcd_send_cmd_fu_179_wd;
wire   [0:0] grp_lcddrv_lcd_send_cmd_fu_179_en;
wire    grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld;
wire   [0:0] grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o;
wire    grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld;
wire   [0:0] grp_lcddrv_lcd_send_cmd_fu_179_rs;
wire    grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld;
wire   [3:0] grp_lcddrv_lcd_send_cmd_fu_179_data;
wire    grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld;
wire    grp_lcddrv_wait_tmr_fu_198_ap_start;
wire    grp_lcddrv_wait_tmr_fu_198_ap_done;
wire    grp_lcddrv_wait_tmr_fu_198_ap_idle;
wire    grp_lcddrv_wait_tmr_fu_198_ap_ready;
wire   [0:0] grp_lcddrv_wait_tmr_fu_198_dummy_tmr_out_o;
wire    grp_lcddrv_wait_tmr_fu_198_dummy_tmr_out_o_ap_vld;
wire    grp_lcddrv_read_mem_fu_206_ap_start;
wire    grp_lcddrv_read_mem_fu_206_ap_idle;
wire    grp_lcddrv_read_mem_fu_206_ap_ready;
reg   [4:0] grp_lcddrv_read_mem_fu_206_addr;
wire   [4:0] grp_lcddrv_read_mem_fu_206_mem_addr;
wire    grp_lcddrv_read_mem_fu_206_mem_addr_ap_vld;
wire   [0:0] grp_lcddrv_read_mem_fu_206_mem_req;
wire    grp_lcddrv_read_mem_fu_206_mem_req_ap_vld;
wire   [7:0] grp_lcddrv_read_mem_fu_206_ap_return;
reg   [4:0] pos_reg_144;
reg    ap_sig_cseq_ST_st8_fsm_7;
reg    ap_sig_485;
reg    ap_sig_cseq_ST_st13_fsm_12;
reg    ap_sig_495;
reg   [5:0] pos_1_reg_156;
reg    ap_sig_cseq_ST_st16_fsm_15;
reg    ap_sig_506;
reg    ap_sig_cseq_ST_st21_fsm_20;
reg    ap_sig_514;
reg    ap_reg_grp_lcddrv_init_lcd_fu_167_ap_start;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_524;
reg    ap_sig_cseq_ST_st4_fsm_3;
reg    ap_sig_531;
reg    ap_reg_grp_lcddrv_lcd_send_cmd_fu_179_ap_start;
reg    ap_sig_cseq_ST_st5_fsm_4;
reg    ap_sig_548;
reg    ap_sig_cseq_ST_st7_fsm_6;
reg    ap_sig_555;
wire   [0:0] exitcond1_fu_236_p2;
reg    ap_sig_cseq_ST_st12_fsm_11;
reg    ap_sig_569;
reg    ap_sig_cseq_ST_st15_fsm_14;
reg    ap_sig_577;
reg    ap_sig_cseq_ST_st20_fsm_19;
reg    ap_sig_586;
reg    ap_sig_cseq_ST_st6_fsm_5;
reg    ap_sig_594;
reg    ap_sig_cseq_ST_st14_fsm_13;
reg    ap_sig_602;
reg    ap_sig_cseq_ST_st11_fsm_10;
reg    ap_sig_610;
reg    ap_sig_cseq_ST_st19_fsm_18;
reg    ap_sig_619;
reg    ap_reg_grp_lcddrv_wait_tmr_fu_198_ap_start;
reg    ap_sig_cseq_ST_st22_fsm_21;
reg    ap_sig_706;
reg    ap_reg_grp_lcddrv_read_mem_fu_206_ap_start;
reg   [21:0] ap_NS_fsm;

// power-on initialization
initial begin
#0 ap_CS_fsm = 22'b1;
#0 dummy_tmr_out_0_data_reg = 1'b0;
#0 dummy_tmr_out_0_vld_reg = 1'b0;
#0 dummy_tmr_out_1_data_reg = 1'b0;
#0 dummy_tmr_out_1_vld_reg = 1'b0;
#0 rs_1_data_reg = 1'b0;
#0 rs_1_vld_reg = 1'b0;
#0 en_1_data_reg = 1'b0;
#0 en_1_vld_reg = 1'b0;
#0 data_1_data_reg = 4'b0000;
#0 data_1_vld_reg = 1'b0;
#0 mem_addr_1_data_reg = 5'b00000;
#0 mem_addr_1_vld_reg = 1'b0;
#0 mem_req_1_data_reg = 1'b0;
#0 mem_req_1_vld_reg = 1'b0;
#0 ap_reg_grp_lcddrv_init_lcd_fu_167_ap_start = 1'b0;
#0 ap_reg_grp_lcddrv_lcd_send_cmd_fu_179_ap_start = 1'b0;
#0 ap_reg_grp_lcddrv_wait_tmr_fu_198_ap_start = 1'b0;
#0 ap_reg_grp_lcddrv_read_mem_fu_206_ap_start = 1'b0;
end

lcddrv_init_lcd grp_lcddrv_init_lcd_fu_167(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_lcddrv_init_lcd_fu_167_ap_start),
    .ap_done(grp_lcddrv_init_lcd_fu_167_ap_done),
    .ap_idle(grp_lcddrv_init_lcd_fu_167_ap_idle),
    .ap_ready(grp_lcddrv_init_lcd_fu_167_ap_ready),
    .dummy_tmr_out_i(dummy_tmr_out_0_data_reg),
    .dummy_tmr_out_o(grp_lcddrv_init_lcd_fu_167_dummy_tmr_out_o),
    .dummy_tmr_out_o_ap_vld(grp_lcddrv_init_lcd_fu_167_dummy_tmr_out_o_ap_vld),
    .en(grp_lcddrv_init_lcd_fu_167_en),
    .en_ap_vld(grp_lcddrv_init_lcd_fu_167_en_ap_vld),
    .rs(grp_lcddrv_init_lcd_fu_167_rs),
    .rs_ap_vld(grp_lcddrv_init_lcd_fu_167_rs_ap_vld),
    .data(grp_lcddrv_init_lcd_fu_167_data),
    .data_ap_vld(grp_lcddrv_init_lcd_fu_167_data_ap_vld)
);

lcddrv_lcd_send_cmd grp_lcddrv_lcd_send_cmd_fu_179(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_lcddrv_lcd_send_cmd_fu_179_ap_start),
    .ap_done(grp_lcddrv_lcd_send_cmd_fu_179_ap_done),
    .ap_idle(grp_lcddrv_lcd_send_cmd_fu_179_ap_idle),
    .ap_ready(grp_lcddrv_lcd_send_cmd_fu_179_ap_ready),
    .mode(grp_lcddrv_lcd_send_cmd_fu_179_mode),
    .wd(grp_lcddrv_lcd_send_cmd_fu_179_wd),
    .en(grp_lcddrv_lcd_send_cmd_fu_179_en),
    .en_ap_vld(grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld),
    .dummy_tmr_out_i(dummy_tmr_out_0_data_reg),
    .dummy_tmr_out_o(grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o),
    .dummy_tmr_out_o_ap_vld(grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld),
    .rs(grp_lcddrv_lcd_send_cmd_fu_179_rs),
    .rs_ap_vld(grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld),
    .data(grp_lcddrv_lcd_send_cmd_fu_179_data),
    .data_ap_vld(grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)
);

lcddrv_wait_tmr grp_lcddrv_wait_tmr_fu_198(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_lcddrv_wait_tmr_fu_198_ap_start),
    .ap_done(grp_lcddrv_wait_tmr_fu_198_ap_done),
    .ap_idle(grp_lcddrv_wait_tmr_fu_198_ap_idle),
    .ap_ready(grp_lcddrv_wait_tmr_fu_198_ap_ready),
    .tmr(ap_const_lv25_989680),
    .dummy_tmr_out_i(dummy_tmr_out_0_data_reg),
    .dummy_tmr_out_o(grp_lcddrv_wait_tmr_fu_198_dummy_tmr_out_o),
    .dummy_tmr_out_o_ap_vld(grp_lcddrv_wait_tmr_fu_198_dummy_tmr_out_o_ap_vld)
);

lcddrv_read_mem grp_lcddrv_read_mem_fu_206(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_lcddrv_read_mem_fu_206_ap_start),
    .ap_done(grp_lcddrv_read_mem_fu_206_ap_done),
    .ap_idle(grp_lcddrv_read_mem_fu_206_ap_idle),
    .ap_ready(grp_lcddrv_read_mem_fu_206_ap_ready),
    .addr(grp_lcddrv_read_mem_fu_206_addr),
    .mem_addr(grp_lcddrv_read_mem_fu_206_mem_addr),
    .mem_addr_ap_vld(grp_lcddrv_read_mem_fu_206_mem_addr_ap_vld),
    .mem_req(grp_lcddrv_read_mem_fu_206_mem_req),
    .mem_req_ap_vld(grp_lcddrv_read_mem_fu_206_mem_req_ap_vld),
    .mem_din(mem_din),
    .mem_ack(mem_ack),
    .ap_return(grp_lcddrv_read_mem_fu_206_ap_return)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_lcddrv_init_lcd_fu_167_ap_start <= 1'b0;
    end else begin
        if ((1'b1 == ap_sig_cseq_ST_st3_fsm_2)) begin
            ap_reg_grp_lcddrv_init_lcd_fu_167_ap_start <= 1'b1;
        end else if ((1'b1 == grp_lcddrv_init_lcd_fu_167_ap_ready)) begin
            ap_reg_grp_lcddrv_init_lcd_fu_167_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_lcddrv_lcd_send_cmd_fu_179_ap_start <= 1'b0;
    end else begin
        if ((((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == grp_lcddrv_read_mem_fu_206_ap_done)) | (~(1'b0 == grp_lcddrv_read_mem_fu_206_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17)) | (1'b1 == ap_sig_cseq_ST_st5_fsm_4) | (1'b1 == ap_sig_cseq_ST_st7_fsm_6) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(1'b0 == exitcond1_fu_236_p2)) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14) | (1'b1 == ap_sig_cseq_ST_st20_fsm_19))) begin
            ap_reg_grp_lcddrv_lcd_send_cmd_fu_179_ap_start <= 1'b1;
        end else if ((1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_ap_ready)) begin
            ap_reg_grp_lcddrv_lcd_send_cmd_fu_179_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_lcddrv_read_mem_fu_206_ap_start <= 1'b0;
    end else begin
        if ((((1'b1 == ap_sig_cseq_ST_st17_fsm_16) & (1'b0 == exitcond_fu_252_p2)) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & (1'b0 == exitcond1_fu_236_p2)))) begin
            ap_reg_grp_lcddrv_read_mem_fu_206_ap_start <= 1'b1;
        end else if ((1'b1 == grp_lcddrv_read_mem_fu_206_ap_ready)) begin
            ap_reg_grp_lcddrv_read_mem_fu_206_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_lcddrv_wait_tmr_fu_198_ap_start <= 1'b0;
    end else begin
        if (((1'b1 == ap_sig_cseq_ST_st17_fsm_16) & ~(1'b0 == exitcond_fu_252_p2))) begin
            ap_reg_grp_lcddrv_wait_tmr_fu_198_ap_start <= 1'b1;
        end else if ((1'b1 == grp_lcddrv_wait_tmr_fu_198_ap_ready)) begin
            ap_reg_grp_lcddrv_wait_tmr_fu_198_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
        if ((1'b1 == ap_sig_cseq_ST_st21_fsm_20)) begin
            pos_1_reg_156 <= pos_3_reg_294;
        end else if ((1'b1 == ap_sig_cseq_ST_st16_fsm_15)) begin
            pos_1_reg_156 <= ap_const_lv6_10;
        end
    end
end

always @ (posedge ap_clk) begin
    if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
        if ((1'b1 == ap_sig_cseq_ST_st13_fsm_12)) begin
            pos_reg_144 <= pos_2_reg_276;
        end else if ((1'b1 == ap_sig_cseq_ST_st8_fsm_7)) begin
            pos_reg_144 <= ap_const_lv5_0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == data_1_vld_in) & (1'b0 == data_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == data_1_vld_in) & (1'b1 == data_1_vld_reg) & (1'b1 == 1'b1)))) begin
        data_1_data_reg <= data_1_data_in;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == 1'b1) & (1'b0 == dummy_tmr_out_0_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == 1'b1) & (1'b1 == dummy_tmr_out_0_vld_reg) & (1'b1 == dummy_tmr_out_0_ack_out)))) begin
        dummy_tmr_out_0_data_reg <= dummy_tmr_out_i;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == dummy_tmr_out_1_vld_in) & (1'b0 == dummy_tmr_out_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == dummy_tmr_out_1_vld_in) & (1'b1 == dummy_tmr_out_1_vld_reg) & (1'b1 == 1'b1)))) begin
        dummy_tmr_out_1_data_reg <= dummy_tmr_out_1_data_in;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == en_1_vld_in) & (1'b0 == en_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == en_1_vld_in) & (1'b1 == en_1_vld_reg) & (1'b1 == 1'b1)))) begin
        en_1_data_reg <= en_1_data_in;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_addr_1_vld_in) & (1'b0 == mem_addr_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_addr_1_vld_in) & (1'b1 == mem_addr_1_vld_reg) & (1'b1 == 1'b1)))) begin
        mem_addr_1_data_reg <= grp_lcddrv_read_mem_fu_206_mem_addr;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_req_1_vld_in) & (1'b0 == mem_req_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_req_1_vld_in) & (1'b1 == mem_req_1_vld_reg) & (1'b1 == 1'b1)))) begin
        mem_req_1_data_reg <= grp_lcddrv_read_mem_fu_206_mem_req;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin
        pos_2_reg_276 <= pos_2_fu_242_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st17_fsm_16) & (1'b0 == exitcond_fu_252_p2))) begin
        pos_3_reg_294 <= pos_3_fu_263_p2;
        tmp_3_reg_289 <= tmp_3_fu_258_p1;
    end
end

always @ (posedge ap_clk) begin
    if ((((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == grp_lcddrv_read_mem_fu_206_ap_done)) | (~(1'b0 == grp_lcddrv_read_mem_fu_206_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17)))) begin
        reg_231 <= {{grp_lcddrv_read_mem_fu_206_ap_return[ap_const_lv32_7 : ap_const_lv32_4]}};
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == rs_1_vld_in) & (1'b0 == rs_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == rs_1_vld_in) & (1'b1 == rs_1_vld_reg) & (1'b1 == 1'b1)))) begin
        rs_1_data_reg <= rs_1_data_in;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == grp_lcddrv_read_mem_fu_206_ap_done))) begin
        tmp_2_reg_281 <= tmp_2_fu_248_p1;
    end
end

always @ (posedge ap_clk) begin
    if ((~(1'b0 == grp_lcddrv_read_mem_fu_206_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin
        tmp_4_reg_299 <= tmp_4_fu_269_p1;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_381) begin
        ap_sig_cseq_ST_st10_fsm_9 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st10_fsm_9 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_610) begin
        ap_sig_cseq_ST_st11_fsm_10 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st11_fsm_10 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_569) begin
        ap_sig_cseq_ST_st12_fsm_11 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st12_fsm_11 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_495) begin
        ap_sig_cseq_ST_st13_fsm_12 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st13_fsm_12 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_602) begin
        ap_sig_cseq_ST_st14_fsm_13 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st14_fsm_13 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_577) begin
        ap_sig_cseq_ST_st15_fsm_14 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st15_fsm_14 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_506) begin
        ap_sig_cseq_ST_st16_fsm_15 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st16_fsm_15 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_414) begin
        ap_sig_cseq_ST_st17_fsm_16 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st17_fsm_16 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_392) begin
        ap_sig_cseq_ST_st18_fsm_17 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st18_fsm_17 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_619) begin
        ap_sig_cseq_ST_st19_fsm_18 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st19_fsm_18 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_37) begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_586) begin
        ap_sig_cseq_ST_st20_fsm_19 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st20_fsm_19 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_514) begin
        ap_sig_cseq_ST_st21_fsm_20 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st21_fsm_20 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_706) begin
        ap_sig_cseq_ST_st22_fsm_21 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st22_fsm_21 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_524) begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_531) begin
        ap_sig_cseq_ST_st4_fsm_3 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st4_fsm_3 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_548) begin
        ap_sig_cseq_ST_st5_fsm_4 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st5_fsm_4 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_594) begin
        ap_sig_cseq_ST_st6_fsm_5 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st6_fsm_5 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_555) begin
        ap_sig_cseq_ST_st7_fsm_6 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st7_fsm_6 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_485) begin
        ap_sig_cseq_ST_st8_fsm_7 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st8_fsm_7 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_403) begin
        ap_sig_cseq_ST_st9_fsm_8 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st9_fsm_8 = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st8_fsm_7) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st14_fsm_13) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st11_fsm_10) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st16_fsm_15) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st21_fsm_20) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld)))) begin
        data_1_data_in = grp_lcddrv_lcd_send_cmd_fu_179_data;
    end else if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & (1'b1 == grp_lcddrv_init_lcd_fu_167_data_ap_vld))) begin
        data_1_data_in = grp_lcddrv_init_lcd_fu_167_data;
    end else begin
        data_1_data_in = 'bx;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st13_fsm_12) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st19_fsm_18))) begin
        data_1_vld_in = grp_lcddrv_lcd_send_cmd_fu_179_data_ap_vld;
    end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        data_1_vld_in = grp_lcddrv_init_lcd_fu_167_data_ap_vld;
    end else begin
        data_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st22_fsm_21) & (1'b1 == grp_lcddrv_wait_tmr_fu_198_dummy_tmr_out_o_ap_vld))) begin
        dummy_tmr_out_1_data_in = grp_lcddrv_wait_tmr_fu_198_dummy_tmr_out_o;
    end else if ((((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st8_fsm_7) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st14_fsm_13) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st11_fsm_10) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st16_fsm_15) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st21_fsm_20) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld)))) begin
        dummy_tmr_out_1_data_in = grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o;
    end else if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & (1'b1 == grp_lcddrv_init_lcd_fu_167_dummy_tmr_out_o_ap_vld))) begin
        dummy_tmr_out_1_data_in = grp_lcddrv_init_lcd_fu_167_dummy_tmr_out_o;
    end else begin
        dummy_tmr_out_1_data_in = 'bx;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st22_fsm_21)) begin
        dummy_tmr_out_1_vld_in = grp_lcddrv_wait_tmr_fu_198_dummy_tmr_out_o_ap_vld;
    end else if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st13_fsm_12) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st19_fsm_18))) begin
        dummy_tmr_out_1_vld_in = grp_lcddrv_lcd_send_cmd_fu_179_dummy_tmr_out_o_ap_vld;
    end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        dummy_tmr_out_1_vld_in = grp_lcddrv_init_lcd_fu_167_dummy_tmr_out_o_ap_vld;
    end else begin
        dummy_tmr_out_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st8_fsm_7) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st14_fsm_13) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st11_fsm_10) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st16_fsm_15) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st21_fsm_20) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld)))) begin
        en_1_data_in = grp_lcddrv_lcd_send_cmd_fu_179_en;
    end else if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & (1'b1 == grp_lcddrv_init_lcd_fu_167_en_ap_vld))) begin
        en_1_data_in = grp_lcddrv_init_lcd_fu_167_en;
    end else begin
        en_1_data_in = 'bx;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st13_fsm_12) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st19_fsm_18))) begin
        en_1_vld_in = grp_lcddrv_lcd_send_cmd_fu_179_en_ap_vld;
    end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        en_1_vld_in = grp_lcddrv_init_lcd_fu_167_en_ap_vld;
    end else begin
        en_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st13_fsm_12) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st19_fsm_18))) begin
        grp_lcddrv_lcd_send_cmd_fu_179_mode = 1'b1;
    end else if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13))) begin
        grp_lcddrv_lcd_send_cmd_fu_179_mode = 1'b0;
    end else begin
        grp_lcddrv_lcd_send_cmd_fu_179_mode = 'bx;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st21_fsm_20)) begin
        grp_lcddrv_lcd_send_cmd_fu_179_wd = tmp_4_reg_299;
    end else if ((1'b1 == ap_sig_cseq_ST_st13_fsm_12)) begin
        grp_lcddrv_lcd_send_cmd_fu_179_wd = tmp_2_reg_281;
    end else if (((1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st19_fsm_18))) begin
        grp_lcddrv_lcd_send_cmd_fu_179_wd = reg_231;
    end else if ((1'b1 == ap_sig_cseq_ST_st14_fsm_13)) begin
        grp_lcddrv_lcd_send_cmd_fu_179_wd = ap_const_lv4_C;
    end else if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15))) begin
        grp_lcddrv_lcd_send_cmd_fu_179_wd = ap_const_lv4_0;
    end else if ((1'b1 == ap_sig_cseq_ST_st6_fsm_5)) begin
        grp_lcddrv_lcd_send_cmd_fu_179_wd = ap_const_lv4_8;
    end else begin
        grp_lcddrv_lcd_send_cmd_fu_179_wd = 'bx;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin
        grp_lcddrv_read_mem_fu_206_addr = tmp_3_reg_289;
    end else if ((1'b1 == ap_sig_cseq_ST_st10_fsm_9)) begin
        grp_lcddrv_read_mem_fu_206_addr = pos_reg_144;
    end else begin
        grp_lcddrv_read_mem_fu_206_addr = 'bx;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin
        mem_addr_1_vld_in = grp_lcddrv_read_mem_fu_206_mem_addr_ap_vld;
    end else begin
        mem_addr_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin
        mem_req_1_vld_in = grp_lcddrv_read_mem_fu_206_mem_req_ap_vld;
    end else begin
        mem_req_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st8_fsm_7) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st14_fsm_13) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st11_fsm_10) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st16_fsm_15) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st21_fsm_20) & (1'b1 == grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld)))) begin
        rs_1_data_in = grp_lcddrv_lcd_send_cmd_fu_179_rs;
    end else if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & (1'b1 == grp_lcddrv_init_lcd_fu_167_rs_ap_vld))) begin
        rs_1_data_in = grp_lcddrv_init_lcd_fu_167_rs;
    end else begin
        rs_1_data_in = 'bx;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st13_fsm_12) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st19_fsm_18))) begin
        rs_1_vld_in = grp_lcddrv_lcd_send_cmd_fu_179_rs_ap_vld;
    end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        rs_1_vld_in = grp_lcddrv_init_lcd_fu_167_rs_ap_vld;
    end else begin
        rs_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : begin
            if (~(ap_start == 1'b0)) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : begin
            ap_NS_fsm = ap_ST_st3_fsm_2;
        end
        ap_ST_st3_fsm_2 : begin
            ap_NS_fsm = ap_ST_st4_fsm_3;
        end
        ap_ST_st4_fsm_3 : begin
            if (~(1'b0 == grp_lcddrv_init_lcd_fu_167_ap_done)) begin
                ap_NS_fsm = ap_ST_st5_fsm_4;
            end else begin
                ap_NS_fsm = ap_ST_st4_fsm_3;
            end
        end
        ap_ST_st5_fsm_4 : begin
            ap_NS_fsm = ap_ST_st6_fsm_5;
        end
        ap_ST_st6_fsm_5 : begin
            if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
                ap_NS_fsm = ap_ST_st7_fsm_6;
            end else begin
                ap_NS_fsm = ap_ST_st6_fsm_5;
            end
        end
        ap_ST_st7_fsm_6 : begin
            ap_NS_fsm = ap_ST_st8_fsm_7;
        end
        ap_ST_st8_fsm_7 : begin
            if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
                ap_NS_fsm = ap_ST_st9_fsm_8;
            end else begin
                ap_NS_fsm = ap_ST_st8_fsm_7;
            end
        end
        ap_ST_st9_fsm_8 : begin
            if (~(1'b0 == exitcond1_fu_236_p2)) begin
                ap_NS_fsm = ap_ST_st14_fsm_13;
            end else begin
                ap_NS_fsm = ap_ST_st10_fsm_9;
            end
        end
        ap_ST_st10_fsm_9 : begin
            if (~(1'b0 == grp_lcddrv_read_mem_fu_206_ap_done)) begin
                ap_NS_fsm = ap_ST_st11_fsm_10;
            end else begin
                ap_NS_fsm = ap_ST_st10_fsm_9;
            end
        end
        ap_ST_st11_fsm_10 : begin
            if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
                ap_NS_fsm = ap_ST_st12_fsm_11;
            end else begin
                ap_NS_fsm = ap_ST_st11_fsm_10;
            end
        end
        ap_ST_st12_fsm_11 : begin
            ap_NS_fsm = ap_ST_st13_fsm_12;
        end
        ap_ST_st13_fsm_12 : begin
            if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
                ap_NS_fsm = ap_ST_st9_fsm_8;
            end else begin
                ap_NS_fsm = ap_ST_st13_fsm_12;
            end
        end
        ap_ST_st14_fsm_13 : begin
            if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
                ap_NS_fsm = ap_ST_st15_fsm_14;
            end else begin
                ap_NS_fsm = ap_ST_st14_fsm_13;
            end
        end
        ap_ST_st15_fsm_14 : begin
            ap_NS_fsm = ap_ST_st16_fsm_15;
        end
        ap_ST_st16_fsm_15 : begin
            if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
                ap_NS_fsm = ap_ST_st17_fsm_16;
            end else begin
                ap_NS_fsm = ap_ST_st16_fsm_15;
            end
        end
        ap_ST_st17_fsm_16 : begin
            if (~(1'b0 == exitcond_fu_252_p2)) begin
                ap_NS_fsm = ap_ST_st22_fsm_21;
            end else begin
                ap_NS_fsm = ap_ST_st18_fsm_17;
            end
        end
        ap_ST_st18_fsm_17 : begin
            if (~(1'b0 == grp_lcddrv_read_mem_fu_206_ap_done)) begin
                ap_NS_fsm = ap_ST_st19_fsm_18;
            end else begin
                ap_NS_fsm = ap_ST_st18_fsm_17;
            end
        end
        ap_ST_st19_fsm_18 : begin
            if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
                ap_NS_fsm = ap_ST_st20_fsm_19;
            end else begin
                ap_NS_fsm = ap_ST_st19_fsm_18;
            end
        end
        ap_ST_st20_fsm_19 : begin
            ap_NS_fsm = ap_ST_st21_fsm_20;
        end
        ap_ST_st21_fsm_20 : begin
            if (~(1'b0 == grp_lcddrv_lcd_send_cmd_fu_179_ap_done)) begin
                ap_NS_fsm = ap_ST_st17_fsm_16;
            end else begin
                ap_NS_fsm = ap_ST_st21_fsm_20;
            end
        end
        ap_ST_st22_fsm_21 : begin
            if (~(1'b0 == grp_lcddrv_wait_tmr_fu_198_ap_done)) begin
                ap_NS_fsm = ap_ST_st5_fsm_4;
            end else begin
                ap_NS_fsm = ap_ST_st22_fsm_21;
            end
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_done = 1'b0;

assign ap_ready = 1'b0;

always @ (*) begin
    ap_sig_37 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end

always @ (*) begin
    ap_sig_381 = (1'b1 == ap_CS_fsm[ap_const_lv32_9]);
end

always @ (*) begin
    ap_sig_392 = (1'b1 == ap_CS_fsm[ap_const_lv32_11]);
end

always @ (*) begin
    ap_sig_403 = (1'b1 == ap_CS_fsm[ap_const_lv32_8]);
end

always @ (*) begin
    ap_sig_414 = (1'b1 == ap_CS_fsm[ap_const_lv32_10]);
end

always @ (*) begin
    ap_sig_485 = (1'b1 == ap_CS_fsm[ap_const_lv32_7]);
end

always @ (*) begin
    ap_sig_495 = (1'b1 == ap_CS_fsm[ap_const_lv32_C]);
end

always @ (*) begin
    ap_sig_506 = (1'b1 == ap_CS_fsm[ap_const_lv32_F]);
end

always @ (*) begin
    ap_sig_514 = (1'b1 == ap_CS_fsm[ap_const_lv32_14]);
end

always @ (*) begin
    ap_sig_524 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]);
end

always @ (*) begin
    ap_sig_531 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]);
end

always @ (*) begin
    ap_sig_548 = (1'b1 == ap_CS_fsm[ap_const_lv32_4]);
end

always @ (*) begin
    ap_sig_555 = (1'b1 == ap_CS_fsm[ap_const_lv32_6]);
end

always @ (*) begin
    ap_sig_569 = (1'b1 == ap_CS_fsm[ap_const_lv32_B]);
end

always @ (*) begin
    ap_sig_577 = (1'b1 == ap_CS_fsm[ap_const_lv32_E]);
end

always @ (*) begin
    ap_sig_586 = (1'b1 == ap_CS_fsm[ap_const_lv32_13]);
end

always @ (*) begin
    ap_sig_594 = (1'b1 == ap_CS_fsm[ap_const_lv32_5]);
end

always @ (*) begin
    ap_sig_602 = (1'b1 == ap_CS_fsm[ap_const_lv32_D]);
end

always @ (*) begin
    ap_sig_610 = (1'b1 == ap_CS_fsm[ap_const_lv32_A]);
end

always @ (*) begin
    ap_sig_619 = (1'b1 == ap_CS_fsm[ap_const_lv32_12]);
end

always @ (*) begin
    ap_sig_706 = (1'b1 == ap_CS_fsm[ap_const_lv32_15]);
end

assign data_o = data_1_data_reg;

assign dummy_tmr_out_0_ack_out = 1'b0;

assign dummy_tmr_out_o = dummy_tmr_out_1_data_reg;

assign en_o = en_1_data_reg;

assign exitcond1_fu_236_p2 = ((pos_reg_144 == ap_const_lv5_10) ? 1'b1 : 1'b0);

assign exitcond_fu_252_p2 = ((pos_1_reg_156 == ap_const_lv6_20) ? 1'b1 : 1'b0);

assign grp_lcddrv_init_lcd_fu_167_ap_start = ap_reg_grp_lcddrv_init_lcd_fu_167_ap_start;

assign grp_lcddrv_lcd_send_cmd_fu_179_ap_start = ap_reg_grp_lcddrv_lcd_send_cmd_fu_179_ap_start;

assign grp_lcddrv_read_mem_fu_206_ap_start = ap_reg_grp_lcddrv_read_mem_fu_206_ap_start;

assign grp_lcddrv_wait_tmr_fu_198_ap_start = ap_reg_grp_lcddrv_wait_tmr_fu_198_ap_start;

assign mem_addr_o = mem_addr_1_data_reg;

assign mem_req_o = mem_req_1_data_reg;

assign pos_2_fu_242_p2 = (pos_reg_144 + ap_const_lv5_1);

assign pos_3_fu_263_p2 = (ap_const_lv6_1 + pos_1_reg_156);

assign rs_o = rs_1_data_reg;

assign tmp_2_fu_248_p1 = grp_lcddrv_read_mem_fu_206_ap_return[3:0];

assign tmp_3_fu_258_p1 = pos_1_reg_156[4:0];

assign tmp_4_fu_269_p1 = grp_lcddrv_read_mem_fu_206_ap_return[3:0];

endmodule //lcddrv
