// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

#ifndef _clock_top_HH_
#define _clock_top_HH_

#include "systemc.h"
#include "AESL_pkg.h"

#include "clock_top_wait_tmr.h"
#include "clock_top_write_mem.h"

namespace ap_rtl {

struct clock_top : public sc_module {
    // Port declarations 15
    sc_in_clk ap_clk;
    sc_in< sc_logic > ap_rst;
    sc_in< sc_logic > ap_start;
    sc_out< sc_logic > ap_done;
    sc_out< sc_logic > ap_idle;
    sc_out< sc_logic > ap_ready;
    sc_in< sc_lv<1> > dummy_tmr_out_i;
    sc_out< sc_lv<1> > dummy_tmr_out_o;
    sc_in< sc_lv<8> > mem_addr_i;
    sc_out< sc_lv<8> > mem_addr_o;
    sc_in< sc_lv<8> > mem_dout_i;
    sc_out< sc_lv<8> > mem_dout_o;
    sc_in< sc_lv<1> > mem_wreq_i;
    sc_out< sc_lv<1> > mem_wreq_o;
    sc_in< sc_lv<1> > mem_ack;


    // Module declarations
    clock_top(sc_module_name name);
    SC_HAS_PROCESS(clock_top);

    ~clock_top();

    sc_trace_file* mVcdFile;

    ofstream mHdltvinHandle;
    ofstream mHdltvoutHandle;
    clock_top_wait_tmr* grp_clock_top_wait_tmr_fu_131;
    clock_top_write_mem* grp_clock_top_write_mem_fu_137;
    sc_signal< sc_lv<18> > ap_CS_fsm;
    sc_signal< sc_logic > ap_sig_cseq_ST_st1_fsm_0;
    sc_signal< bool > ap_sig_33;
    sc_signal< sc_lv<1> > dummy_tmr_out_0_data_reg;
    sc_signal< sc_logic > dummy_tmr_out_0_vld_reg;
    sc_signal< sc_logic > dummy_tmr_out_0_ack_out;
    sc_signal< sc_lv<1> > dummy_tmr_out_1_data_reg;
    sc_signal< sc_logic > dummy_tmr_out_1_vld_reg;
    sc_signal< sc_logic > dummy_tmr_out_1_vld_in;
    sc_signal< sc_lv<8> > mem_addr_1_data_reg;
    sc_signal< sc_logic > mem_addr_1_vld_reg;
    sc_signal< sc_logic > mem_addr_1_vld_in;
    sc_signal< sc_lv<8> > mem_dout_1_data_reg;
    sc_signal< sc_logic > mem_dout_1_vld_reg;
    sc_signal< sc_logic > mem_dout_1_vld_in;
    sc_signal< sc_lv<1> > mem_wreq_1_data_reg;
    sc_signal< sc_logic > mem_wreq_1_vld_reg;
    sc_signal< sc_logic > mem_wreq_1_vld_in;
    sc_signal< sc_lv<6> > pos_1_fu_187_p2;
    sc_signal< sc_lv<6> > pos_1_reg_322;
    sc_signal< sc_logic > ap_sig_cseq_ST_st3_fsm_2;
    sc_signal< bool > ap_sig_251;
    sc_signal< sc_lv<7> > pos_cast1_cast_fu_193_p1;
    sc_signal< sc_lv<7> > pos_cast1_cast_reg_327;
    sc_signal< sc_lv<1> > exitcond_fu_181_p2;
    sc_signal< sc_lv<8> > min_load_reg_367;
    sc_signal< sc_logic > ap_sig_cseq_ST_st5_fsm_4;
    sc_signal< bool > ap_sig_265;
    sc_signal< sc_lv<8> > min1_load_reg_373;
    sc_signal< sc_logic > ap_sig_cseq_ST_st7_fsm_6;
    sc_signal< bool > ap_sig_274;
    sc_signal< sc_lv<8> > sec10_1_load_reg_379;
    sc_signal< sc_logic > ap_sig_cseq_ST_st11_fsm_10;
    sc_signal< bool > ap_sig_283;
    sc_signal< sc_lv<8> > sec1_load_reg_385;
    sc_signal< sc_logic > ap_sig_cseq_ST_st13_fsm_12;
    sc_signal< bool > ap_sig_292;
    sc_signal< sc_logic > ap_sig_cseq_ST_st17_fsm_16;
    sc_signal< bool > ap_sig_301;
    sc_signal< sc_logic > grp_clock_top_wait_tmr_fu_131_ap_start;
    sc_signal< sc_logic > grp_clock_top_wait_tmr_fu_131_ap_done;
    sc_signal< sc_logic > grp_clock_top_wait_tmr_fu_131_ap_idle;
    sc_signal< sc_logic > grp_clock_top_wait_tmr_fu_131_ap_ready;
    sc_signal< sc_lv<1> > grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o;
    sc_signal< sc_logic > grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o_ap_vld;
    sc_signal< sc_logic > grp_clock_top_write_mem_fu_137_ap_start;
    sc_signal< sc_logic > grp_clock_top_write_mem_fu_137_ap_done;
    sc_signal< sc_logic > grp_clock_top_write_mem_fu_137_ap_idle;
    sc_signal< sc_logic > grp_clock_top_write_mem_fu_137_ap_ready;
    sc_signal< sc_lv<7> > grp_clock_top_write_mem_fu_137_addr;
    sc_signal< sc_lv<8> > grp_clock_top_write_mem_fu_137_data;
    sc_signal< sc_lv<8> > grp_clock_top_write_mem_fu_137_mem_addr;
    sc_signal< sc_logic > grp_clock_top_write_mem_fu_137_mem_addr_ap_vld;
    sc_signal< sc_lv<8> > grp_clock_top_write_mem_fu_137_mem_dout;
    sc_signal< sc_logic > grp_clock_top_write_mem_fu_137_mem_dout_ap_vld;
    sc_signal< sc_lv<1> > grp_clock_top_write_mem_fu_137_mem_wreq;
    sc_signal< sc_logic > grp_clock_top_write_mem_fu_137_mem_wreq_ap_vld;
    sc_signal< sc_lv<6> > pos_reg_120;
    sc_signal< sc_logic > ap_sig_cseq_ST_st2_fsm_1;
    sc_signal< bool > ap_sig_335;
    sc_signal< sc_logic > ap_sig_cseq_ST_st4_fsm_3;
    sc_signal< bool > ap_sig_342;
    sc_signal< sc_logic > ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start;
    sc_signal< sc_logic > ap_sig_cseq_ST_st6_fsm_5;
    sc_signal< bool > ap_sig_354;
    sc_signal< sc_logic > ap_reg_grp_clock_top_write_mem_fu_137_ap_start;
    sc_signal< sc_logic > ap_sig_cseq_ST_st9_fsm_8;
    sc_signal< bool > ap_sig_367;
    sc_signal< sc_logic > ap_sig_cseq_ST_st15_fsm_14;
    sc_signal< bool > ap_sig_377;
    sc_signal< sc_logic > ap_sig_cseq_ST_st8_fsm_7;
    sc_signal< bool > ap_sig_388;
    sc_signal< sc_logic > ap_sig_cseq_ST_st10_fsm_9;
    sc_signal< bool > ap_sig_396;
    sc_signal< sc_logic > ap_sig_cseq_ST_st12_fsm_11;
    sc_signal< bool > ap_sig_404;
    sc_signal< sc_logic > ap_sig_cseq_ST_st14_fsm_13;
    sc_signal< bool > ap_sig_412;
    sc_signal< sc_logic > ap_sig_cseq_ST_st16_fsm_15;
    sc_signal< bool > ap_sig_420;
    sc_signal< sc_logic > ap_sig_cseq_ST_st18_fsm_17;
    sc_signal< bool > ap_sig_428;
    sc_signal< sc_lv<8> > msec_fu_70;
    sc_signal< sc_lv<8> > msec_1_fu_223_p2;
    sc_signal< sc_lv<1> > tmp_7_fu_228_p2;
    sc_signal< sc_lv<1> > tmp_9_fu_244_p2;
    sc_signal< sc_lv<1> > tmp_s_fu_260_p2;
    sc_signal< sc_lv<1> > tmp_1_fu_276_p2;
    sc_signal< sc_lv<8> > min_fu_74;
    sc_signal< sc_lv<8> > p_cast_fu_310_p1;
    sc_signal< sc_lv<8> > min1_fu_78;
    sc_signal< sc_lv<8> > min1_1_fu_271_p2;
    sc_signal< sc_lv<8> > sec10_1_fu_82;
    sc_signal< sc_lv<8> > sec10_fu_255_p2;
    sc_signal< sc_lv<8> > sec1_fu_86;
    sc_signal< sc_lv<8> > sec1_1_fu_239_p2;
    sc_signal< sc_lv<8> > min10_fu_287_p2;
    sc_signal< sc_lv<1> > tmp_2_fu_296_p2;
    sc_signal< sc_lv<6> > tmp_fu_292_p1;
    sc_signal< sc_lv<6> > p_s_fu_302_p3;
    sc_signal< sc_lv<18> > ap_NS_fsm;
    static const sc_logic ap_const_logic_1;
    static const sc_logic ap_const_logic_0;
    static const sc_lv<18> ap_ST_st1_fsm_0;
    static const sc_lv<18> ap_ST_st2_fsm_1;
    static const sc_lv<18> ap_ST_st3_fsm_2;
    static const sc_lv<18> ap_ST_st4_fsm_3;
    static const sc_lv<18> ap_ST_st5_fsm_4;
    static const sc_lv<18> ap_ST_st6_fsm_5;
    static const sc_lv<18> ap_ST_st7_fsm_6;
    static const sc_lv<18> ap_ST_st8_fsm_7;
    static const sc_lv<18> ap_ST_st9_fsm_8;
    static const sc_lv<18> ap_ST_st10_fsm_9;
    static const sc_lv<18> ap_ST_st11_fsm_10;
    static const sc_lv<18> ap_ST_st12_fsm_11;
    static const sc_lv<18> ap_ST_st13_fsm_12;
    static const sc_lv<18> ap_ST_st14_fsm_13;
    static const sc_lv<18> ap_ST_st15_fsm_14;
    static const sc_lv<18> ap_ST_st16_fsm_15;
    static const sc_lv<18> ap_ST_st17_fsm_16;
    static const sc_lv<18> ap_ST_st18_fsm_17;
    static const sc_lv<32> ap_const_lv32_0;
    static const sc_lv<1> ap_const_lv1_1;
    static const sc_lv<1> ap_const_lv1_0;
    static const sc_lv<32> ap_const_lv32_2;
    static const sc_lv<32> ap_const_lv32_4;
    static const sc_lv<32> ap_const_lv32_6;
    static const sc_lv<32> ap_const_lv32_A;
    static const sc_lv<32> ap_const_lv32_C;
    static const sc_lv<32> ap_const_lv32_10;
    static const sc_lv<6> ap_const_lv6_0;
    static const sc_lv<32> ap_const_lv32_1;
    static const sc_lv<32> ap_const_lv32_3;
    static const sc_lv<32> ap_const_lv32_5;
    static const sc_lv<32> ap_const_lv32_8;
    static const sc_lv<32> ap_const_lv32_E;
    static const sc_lv<7> ap_const_lv7_10;
    static const sc_lv<7> ap_const_lv7_11;
    static const sc_lv<32> ap_const_lv32_7;
    static const sc_lv<7> ap_const_lv7_12;
    static const sc_lv<32> ap_const_lv32_9;
    static const sc_lv<7> ap_const_lv7_13;
    static const sc_lv<32> ap_const_lv32_B;
    static const sc_lv<7> ap_const_lv7_14;
    static const sc_lv<32> ap_const_lv32_D;
    static const sc_lv<7> ap_const_lv7_15;
    static const sc_lv<32> ap_const_lv32_F;
    static const sc_lv<7> ap_const_lv7_16;
    static const sc_lv<32> ap_const_lv32_11;
    static const sc_lv<8> ap_const_lv8_20;
    static const sc_lv<8> ap_const_lv8_3A;
    static const sc_lv<8> ap_const_lv8_2E;
    static const sc_lv<8> ap_const_lv8_30;
    static const sc_lv<6> ap_const_lv6_20;
    static const sc_lv<6> ap_const_lv6_1;
    static const sc_lv<8> ap_const_lv8_1;
    static const sc_lv<8> ap_const_lv8_39;
    static const sc_lv<8> ap_const_lv8_35;
    static const sc_lv<6> ap_const_lv6_30;
    // Thread declarations
    void thread_ap_clk_no_reset_();
    void thread_ap_done();
    void thread_ap_idle();
    void thread_ap_ready();
    void thread_ap_sig_251();
    void thread_ap_sig_265();
    void thread_ap_sig_274();
    void thread_ap_sig_283();
    void thread_ap_sig_292();
    void thread_ap_sig_301();
    void thread_ap_sig_33();
    void thread_ap_sig_335();
    void thread_ap_sig_342();
    void thread_ap_sig_354();
    void thread_ap_sig_367();
    void thread_ap_sig_377();
    void thread_ap_sig_388();
    void thread_ap_sig_396();
    void thread_ap_sig_404();
    void thread_ap_sig_412();
    void thread_ap_sig_420();
    void thread_ap_sig_428();
    void thread_ap_sig_cseq_ST_st10_fsm_9();
    void thread_ap_sig_cseq_ST_st11_fsm_10();
    void thread_ap_sig_cseq_ST_st12_fsm_11();
    void thread_ap_sig_cseq_ST_st13_fsm_12();
    void thread_ap_sig_cseq_ST_st14_fsm_13();
    void thread_ap_sig_cseq_ST_st15_fsm_14();
    void thread_ap_sig_cseq_ST_st16_fsm_15();
    void thread_ap_sig_cseq_ST_st17_fsm_16();
    void thread_ap_sig_cseq_ST_st18_fsm_17();
    void thread_ap_sig_cseq_ST_st1_fsm_0();
    void thread_ap_sig_cseq_ST_st2_fsm_1();
    void thread_ap_sig_cseq_ST_st3_fsm_2();
    void thread_ap_sig_cseq_ST_st4_fsm_3();
    void thread_ap_sig_cseq_ST_st5_fsm_4();
    void thread_ap_sig_cseq_ST_st6_fsm_5();
    void thread_ap_sig_cseq_ST_st7_fsm_6();
    void thread_ap_sig_cseq_ST_st8_fsm_7();
    void thread_ap_sig_cseq_ST_st9_fsm_8();
    void thread_dummy_tmr_out_0_ack_out();
    void thread_dummy_tmr_out_1_vld_in();
    void thread_dummy_tmr_out_o();
    void thread_exitcond_fu_181_p2();
    void thread_grp_clock_top_wait_tmr_fu_131_ap_start();
    void thread_grp_clock_top_write_mem_fu_137_addr();
    void thread_grp_clock_top_write_mem_fu_137_ap_start();
    void thread_grp_clock_top_write_mem_fu_137_data();
    void thread_mem_addr_1_vld_in();
    void thread_mem_addr_o();
    void thread_mem_dout_1_vld_in();
    void thread_mem_dout_o();
    void thread_mem_wreq_1_vld_in();
    void thread_mem_wreq_o();
    void thread_min10_fu_287_p2();
    void thread_min1_1_fu_271_p2();
    void thread_msec_1_fu_223_p2();
    void thread_p_cast_fu_310_p1();
    void thread_p_s_fu_302_p3();
    void thread_pos_1_fu_187_p2();
    void thread_pos_cast1_cast_fu_193_p1();
    void thread_sec10_fu_255_p2();
    void thread_sec1_1_fu_239_p2();
    void thread_tmp_1_fu_276_p2();
    void thread_tmp_2_fu_296_p2();
    void thread_tmp_7_fu_228_p2();
    void thread_tmp_9_fu_244_p2();
    void thread_tmp_fu_292_p1();
    void thread_tmp_s_fu_260_p2();
    void thread_ap_NS_fsm();
    void thread_hdltv_gen();
};

}

using namespace ap_rtl;

#endif
