// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

#ifndef _clock_top_write_mem_HH_
#define _clock_top_write_mem_HH_

#include "systemc.h"
#include "AESL_pkg.h"


namespace ap_rtl {

struct clock_top_write_mem : public sc_module {
    // Port declarations 15
    sc_in_clk ap_clk;
    sc_in< sc_logic > ap_rst;
    sc_in< sc_logic > ap_start;
    sc_out< sc_logic > ap_done;
    sc_out< sc_logic > ap_idle;
    sc_out< sc_logic > ap_ready;
    sc_in< sc_lv<7> > addr;
    sc_in< sc_lv<8> > data;
    sc_out< sc_lv<8> > mem_addr;
    sc_out< sc_logic > mem_addr_ap_vld;
    sc_out< sc_lv<8> > mem_dout;
    sc_out< sc_logic > mem_dout_ap_vld;
    sc_out< sc_lv<1> > mem_wreq;
    sc_out< sc_logic > mem_wreq_ap_vld;
    sc_in< sc_lv<1> > mem_ack;


    // Module declarations
    clock_top_write_mem(sc_module_name name);
    SC_HAS_PROCESS(clock_top_write_mem);

    ~clock_top_write_mem();

    sc_trace_file* mVcdFile;

    sc_signal< sc_lv<6> > ap_CS_fsm;
    sc_signal< sc_logic > ap_sig_cseq_ST_st1_fsm_0;
    sc_signal< bool > ap_sig_23;
    sc_signal< sc_lv<8> > addr_cast_fu_71_p1;
    sc_signal< sc_lv<8> > addr_cast_reg_85;
    sc_signal< sc_logic > ap_sig_cseq_ST_st2_fsm_1;
    sc_signal< bool > ap_sig_51;
    sc_signal< sc_logic > ap_sig_cseq_ST_st4_fsm_3;
    sc_signal< bool > ap_sig_58;
    sc_signal< sc_logic > ap_sig_cseq_ST_st5_fsm_4;
    sc_signal< bool > ap_sig_65;
    sc_signal< sc_lv<1> > mem_ack_read_read_fu_65_p2;
    sc_signal< sc_logic > ap_sig_cseq_ST_st6_fsm_5;
    sc_signal< bool > ap_sig_80;
    sc_signal< sc_lv<6> > ap_NS_fsm;
    static const sc_logic ap_const_logic_1;
    static const sc_logic ap_const_logic_0;
    static const sc_lv<6> ap_ST_st1_fsm_0;
    static const sc_lv<6> ap_ST_st2_fsm_1;
    static const sc_lv<6> ap_ST_st3_fsm_2;
    static const sc_lv<6> ap_ST_st4_fsm_3;
    static const sc_lv<6> ap_ST_st5_fsm_4;
    static const sc_lv<6> ap_ST_st6_fsm_5;
    static const sc_lv<32> ap_const_lv32_0;
    static const sc_lv<1> ap_const_lv1_1;
    static const sc_lv<32> ap_const_lv32_1;
    static const sc_lv<32> ap_const_lv32_3;
    static const sc_lv<32> ap_const_lv32_4;
    static const sc_lv<1> ap_const_lv1_0;
    static const sc_lv<32> ap_const_lv32_5;
    // Thread declarations
    void thread_ap_clk_no_reset_();
    void thread_addr_cast_fu_71_p1();
    void thread_ap_done();
    void thread_ap_idle();
    void thread_ap_ready();
    void thread_ap_sig_23();
    void thread_ap_sig_51();
    void thread_ap_sig_58();
    void thread_ap_sig_65();
    void thread_ap_sig_80();
    void thread_ap_sig_cseq_ST_st1_fsm_0();
    void thread_ap_sig_cseq_ST_st2_fsm_1();
    void thread_ap_sig_cseq_ST_st4_fsm_3();
    void thread_ap_sig_cseq_ST_st5_fsm_4();
    void thread_ap_sig_cseq_ST_st6_fsm_5();
    void thread_mem_ack_read_read_fu_65_p2();
    void thread_mem_addr();
    void thread_mem_addr_ap_vld();
    void thread_mem_dout();
    void thread_mem_dout_ap_vld();
    void thread_mem_wreq();
    void thread_mem_wreq_ap_vld();
    void thread_ap_NS_fsm();
};

}

using namespace ap_rtl;

#endif
