-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.2
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity lcddrv_lcd_send_cmd is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    mode : IN STD_LOGIC_VECTOR (0 downto 0);
    wd : IN STD_LOGIC_VECTOR (3 downto 0);
    en : OUT STD_LOGIC_VECTOR (0 downto 0);
    en_ap_vld : OUT STD_LOGIC;
    dummy_tmr_out_i : IN STD_LOGIC_VECTOR (0 downto 0);
    dummy_tmr_out_o : OUT STD_LOGIC_VECTOR (0 downto 0);
    dummy_tmr_out_o_ap_vld : OUT STD_LOGIC;
    rs : OUT STD_LOGIC_VECTOR (0 downto 0);
    rs_ap_vld : OUT STD_LOGIC;
    data : OUT STD_LOGIC_VECTOR (3 downto 0);
    data_ap_vld : OUT STD_LOGIC );
end;


architecture behav of lcddrv_lcd_send_cmd is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
    constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
    constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
    constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
    constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (8 downto 0) := "000010000";
    constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (8 downto 0) := "000100000";
    constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (8 downto 0) := "001000000";
    constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (8 downto 0) := "010000000";
    constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
    constant ap_const_lv25_3E8 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000001111101000";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";

    signal ap_CS_fsm : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
    signal ap_sig_26 : BOOLEAN;
    signal grp_lcddrv_wait_tmr_fu_67_ap_start : STD_LOGIC;
    signal grp_lcddrv_wait_tmr_fu_67_ap_done : STD_LOGIC;
    signal grp_lcddrv_wait_tmr_fu_67_ap_idle : STD_LOGIC;
    signal grp_lcddrv_wait_tmr_fu_67_ap_ready : STD_LOGIC;
    signal grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o : STD_LOGIC_VECTOR (0 downto 0);
    signal grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld : STD_LOGIC;
    signal ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start : STD_LOGIC := '0';
    signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
    signal ap_sig_66 : BOOLEAN;
    signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
    signal ap_sig_73 : BOOLEAN;
    signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
    signal ap_sig_81 : BOOLEAN;
    signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
    signal ap_sig_89 : BOOLEAN;
    signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
    signal ap_sig_98 : BOOLEAN;
    signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
    signal ap_sig_105 : BOOLEAN;
    signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
    signal ap_sig_113 : BOOLEAN;
    signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
    signal ap_sig_121 : BOOLEAN;
    signal ap_NS_fsm : STD_LOGIC_VECTOR (8 downto 0);

    component lcddrv_wait_tmr IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        tmr : IN STD_LOGIC_VECTOR (24 downto 0);
        dummy_tmr_out_i : IN STD_LOGIC_VECTOR (0 downto 0);
        dummy_tmr_out_o : OUT STD_LOGIC_VECTOR (0 downto 0);
        dummy_tmr_out_o_ap_vld : OUT STD_LOGIC );
    end component;



begin
    grp_lcddrv_wait_tmr_fu_67 : component lcddrv_wait_tmr
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_lcddrv_wait_tmr_fu_67_ap_start,
        ap_done => grp_lcddrv_wait_tmr_fu_67_ap_done,
        ap_idle => grp_lcddrv_wait_tmr_fu_67_ap_idle,
        ap_ready => grp_lcddrv_wait_tmr_fu_67_ap_ready,
        tmr => ap_const_lv25_3E8,
        dummy_tmr_out_i => dummy_tmr_out_i,
        dummy_tmr_out_o => grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o,
        dummy_tmr_out_o_ap_vld => grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_st1_fsm_0;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then 
                    ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = grp_lcddrv_wait_tmr_fu_67_ap_ready)) then 
                    ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, grp_lcddrv_wait_tmr_fu_67_ap_done)
    begin
        case ap_CS_fsm is
            when ap_ST_st1_fsm_0 => 
                if (not((ap_start = ap_const_logic_0))) then
                    ap_NS_fsm <= ap_ST_st2_fsm_1;
                else
                    ap_NS_fsm <= ap_ST_st1_fsm_0;
                end if;
            when ap_ST_st2_fsm_1 => 
                ap_NS_fsm <= ap_ST_st3_fsm_2;
            when ap_ST_st3_fsm_2 => 
                if (not((ap_const_logic_0 = grp_lcddrv_wait_tmr_fu_67_ap_done))) then
                    ap_NS_fsm <= ap_ST_st4_fsm_3;
                else
                    ap_NS_fsm <= ap_ST_st3_fsm_2;
                end if;
            when ap_ST_st4_fsm_3 => 
                ap_NS_fsm <= ap_ST_st5_fsm_4;
            when ap_ST_st5_fsm_4 => 
                if (not((ap_const_logic_0 = grp_lcddrv_wait_tmr_fu_67_ap_done))) then
                    ap_NS_fsm <= ap_ST_st6_fsm_5;
                else
                    ap_NS_fsm <= ap_ST_st5_fsm_4;
                end if;
            when ap_ST_st6_fsm_5 => 
                ap_NS_fsm <= ap_ST_st7_fsm_6;
            when ap_ST_st7_fsm_6 => 
                if (not((ap_const_logic_0 = grp_lcddrv_wait_tmr_fu_67_ap_done))) then
                    ap_NS_fsm <= ap_ST_st8_fsm_7;
                else
                    ap_NS_fsm <= ap_ST_st7_fsm_6;
                end if;
            when ap_ST_st8_fsm_7 => 
                ap_NS_fsm <= ap_ST_st9_fsm_8;
            when ap_ST_st9_fsm_8 => 
                if (not((ap_const_logic_0 = grp_lcddrv_wait_tmr_fu_67_ap_done))) then
                    ap_NS_fsm <= ap_ST_st1_fsm_0;
                else
                    ap_NS_fsm <= ap_ST_st9_fsm_8;
                end if;
            when others =>  
                ap_NS_fsm <= "XXXXXXXXX";
        end case;
    end process;

    ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, grp_lcddrv_wait_tmr_fu_67_ap_done, ap_sig_cseq_ST_st9_fsm_8)
    begin
        if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((ap_const_logic_0 = grp_lcddrv_wait_tmr_fu_67_ap_done))))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
    begin
        if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_ready_assign_proc : process(grp_lcddrv_wait_tmr_fu_67_ap_done, ap_sig_cseq_ST_st9_fsm_8)
    begin
        if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((ap_const_logic_0 = grp_lcddrv_wait_tmr_fu_67_ap_done)))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_105_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_105 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
    end process;


    ap_sig_113_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_113 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
    end process;


    ap_sig_121_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_121 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
    end process;


    ap_sig_26_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
    end process;


    ap_sig_66_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_66 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
    end process;


    ap_sig_73_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_73 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
    end process;


    ap_sig_81_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_81 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
    end process;


    ap_sig_89_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_89 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
    end process;


    ap_sig_98_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_98 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
    end process;


    ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_26)
    begin
        if (ap_sig_26) then 
            ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_66)
    begin
        if (ap_sig_66) then 
            ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_98)
    begin
        if (ap_sig_98) then 
            ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_73)
    begin
        if (ap_sig_73) then 
            ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_105)
    begin
        if (ap_sig_105) then 
            ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_81)
    begin
        if (ap_sig_81) then 
            ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_113)
    begin
        if (ap_sig_113) then 
            ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_89)
    begin
        if (ap_sig_89) then 
            ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_121)
    begin
        if (ap_sig_121) then 
            ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
        end if; 
    end process;

    data <= wd;

    data_ap_vld_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7)
    begin
        if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then 
            data_ap_vld <= ap_const_logic_1;
        else 
            data_ap_vld <= ap_const_logic_0;
        end if; 
    end process;


    dummy_tmr_out_o_assign_proc : process(dummy_tmr_out_i, grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o, grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st9_fsm_8)
    begin
        if ((((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_logic_1 = grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_logic_1 = grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_logic_1 = grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and (ap_const_logic_1 = grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)))) then 
            dummy_tmr_out_o <= grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o;
        else 
            dummy_tmr_out_o <= dummy_tmr_out_i;
        end if; 
    end process;

    dummy_tmr_out_o_ap_vld <= grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld;

    en_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7)
    begin
        if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then 
            en <= ap_const_lv1_1;
        elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then 
            en <= ap_const_lv1_0;
        else 
            en <= "X";
        end if; 
    end process;


    en_ap_vld_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7)
    begin
        if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then 
            en_ap_vld <= ap_const_logic_1;
        else 
            en_ap_vld <= ap_const_logic_0;
        end if; 
    end process;

    grp_lcddrv_wait_tmr_fu_67_ap_start <= ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start;
    rs <= mode;

    rs_ap_vld_assign_proc : process(ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7)
    begin
        if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then 
            rs_ap_vld <= ap_const_logic_1;
        else 
            rs_ap_vld <= ap_const_logic_0;
        end if; 
    end process;

end behav;
