; ModuleID = 'D:/20_sample_artix7/clock/solution1/.autopilot/db/a.o.2.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-w64-mingw32"

@mem_wreq = global i1 false, align 1
@mem_dout = global i8 0, align 1
@mem_addr = global i8 0, align 1
@mem_ack = common global i1 false, align 1
@dummy_tmr_out = global i1 false, align 1
@p_str1 = private unnamed_addr constant [8 x i8] c"ap_none\00", align 1
@p_str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1

define internal fastcc void @clock_top_write_mem(i7 zeroext %addr, i8 %data) {
  %data_read = call i8 @_ssdm_op_Read.ap_auto.i8(i8 %data)
  %addr_read = call i7 @_ssdm_op_Read.ap_auto.i7(i7 %addr)
  %addr_cast = zext i7 %addr_read to i8
  call void (...)* @_ssdm_op_Wait(i32 1)
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_addr, i8 %addr_cast)
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_dout, i8 %data_read)
  call void @_ssdm_op_Write.ap_none.volatile.i1P(i1* @mem_wreq, i1 false)
  call void (...)* @_ssdm_op_Wait(i32 1)
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge, %0
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_addr, i8 %addr_cast)
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_dout, i8 %data_read)
  call void @_ssdm_op_Write.ap_none.volatile.i1P(i1* @mem_wreq, i1 true)
  %mem_ack_read = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @mem_ack)
  br i1 %mem_ack_read, label %1, label %._crit_edge

; <label>:1                                       ; preds = %._crit_edge
  call void (...)* @_ssdm_op_Wait(i32 1)
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_addr, i8 %addr_cast)
  call void @_ssdm_op_Write.ap_none.volatile.i8P(i8* @mem_dout, i8 %data_read)
  call void @_ssdm_op_Write.ap_none.volatile.i1P(i1* @mem_wreq, i1 false)
  call void (...)* @_ssdm_op_Wait(i32 1)
  ret void
}

define internal fastcc void @clock_top_wait_tmr() nounwind uwtable {
  br label %.loopexit

.loopexit:                                        ; preds = %.preheader, %0
  %u = phi i7 [ 0, %0 ], [ %u_1, %.preheader ]
  %exitcond1 = icmp eq i7 %u, -28
  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 100, i64 100, i64 100) nounwind
  %u_1 = add i7 %u, 1
  br i1 %exitcond1, label %2, label %.preheader

.preheader:                                       ; preds = %.loopexit, %1
  %t = phi i17 [ %t_1, %1 ], [ 0, %.loopexit ]
  %exitcond = icmp eq i17 %t, -31072
  %empty_3 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 100000, i64 100000, i64 100000) nounwind
  %t_1 = add i17 %t, 1
  br i1 %exitcond, label %.loopexit, label %1

; <label>:1                                       ; preds = %.preheader
  %dummy_tmr_out_read = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @dummy_tmr_out) nounwind
  %not_s = xor i1 %dummy_tmr_out_read, true
  call void @_ssdm_op_Write.ap_none.volatile.i1P(i1* @dummy_tmr_out, i1 %not_s) nounwind
  br label %.preheader

; <label>:2                                       ; preds = %.loopexit
  ret void
}

declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone

declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone

define void @clock_top() noreturn nounwind uwtable {
  call void (...)* @_ssdm_op_SpecTopModule()
  %dummy_tmr_out_load = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @dummy_tmr_out) nounwind
  call void (...)* @_ssdm_op_SpecInterface(i1* @dummy_tmr_out, [8 x i8]* @p_str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind
  %mem_addr_load = call i8 @_ssdm_op_Read.ap_none.volatile.i8P(i8* @mem_addr) nounwind
  call void (...)* @_ssdm_op_SpecInterface(i8* @mem_addr, [8 x i8]* @p_str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind
  %mem_dout_load = call i8 @_ssdm_op_Read.ap_none.volatile.i8P(i8* @mem_dout) nounwind
  call void (...)* @_ssdm_op_SpecInterface(i8* @mem_dout, [8 x i8]* @p_str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind
  %mem_wreq_load = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @mem_wreq) nounwind
  call void (...)* @_ssdm_op_SpecInterface(i1* @mem_wreq, [8 x i8]* @p_str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind
  %mem_ack_load = call i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1* @mem_ack) nounwind
  call void (...)* @_ssdm_op_SpecInterface(i1* @mem_ack, [8 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind
  br label %1

; <label>:1                                       ; preds = %2, %0
  %pos = phi i6 [ 0, %0 ], [ %pos_1, %2 ]
  %exitcond = icmp eq i6 %pos, -32
  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32) nounwind
  %pos_1 = add i6 %pos, 1
  br i1 %exitcond, label %.preheader.preheader, label %2

.preheader.preheader:                             ; preds = %1
  %msec = alloca i8
  %min = alloca i8
  %min1 = alloca i8
  %sec10_1 = alloca i8
  %sec1 = alloca i8
  store i8 48, i8* %sec1
  store i8 48, i8* %sec10_1
  store i8 48, i8* %min1
  store i8 48, i8* %min
  store i8 48, i8* %msec
  br label %.preheader

; <label>:2                                       ; preds = %1
  %pos_cast1_cast = zext i6 %pos to i7
  call fastcc void @clock_top_write_mem(i7 zeroext %pos_cast1_cast, i8 zeroext 32) nounwind
  br label %1

.preheader:                                       ; preds = %.preheader.backedge, %.preheader.preheader
  %msec_load = load i8* %msec
  %min_load = load i8* %min
  %min1_load = load i8* %min1
  %sec10_1_load = load i8* %sec10_1
  %sec1_load = load i8* %sec1
  call fastcc void @clock_top_write_mem(i7 zeroext 16, i8 zeroext %min_load) nounwind
  call fastcc void @clock_top_write_mem(i7 zeroext 17, i8 zeroext %min1_load) nounwind
  call fastcc void @clock_top_write_mem(i7 zeroext 18, i8 zeroext 58) nounwind
  call fastcc void @clock_top_write_mem(i7 zeroext 19, i8 zeroext %sec10_1_load) nounwind
  call fastcc void @clock_top_write_mem(i7 zeroext 20, i8 zeroext %sec1_load) nounwind
  call fastcc void @clock_top_write_mem(i7 zeroext 21, i8 zeroext 46) nounwind
  call fastcc void @clock_top_write_mem(i7 zeroext 22, i8 zeroext %msec_load) nounwind
  call fastcc void @clock_top_wait_tmr()
  %msec_1 = add i8 %msec_load, 1
  %tmp_7 = icmp ugt i8 %msec_1, 57
  br i1 %tmp_7, label %3, label %.preheader.backedge.pre3

; <label>:3                                       ; preds = %.preheader
  %sec1_1 = add i8 %sec1_load, 1
  %tmp_9 = icmp ugt i8 %sec1_1, 57
  br i1 %tmp_9, label %4, label %.preheader.backedge.pre

; <label>:4                                       ; preds = %3
  %sec10 = add i8 %sec10_1_load, 1
  %tmp_s = icmp ugt i8 %sec10, 53
  br i1 %tmp_s, label %5, label %.preheader.backedge.pre1

; <label>:5                                       ; preds = %4
  %min1_1 = add i8 %min1_load, 1
  %tmp_1 = icmp ugt i8 %min1_1, 57
  store i8 48, i8* %sec10_1
  br i1 %tmp_1, label %6, label %.preheader.backedge.pre2

; <label>:6                                       ; preds = %5
  %min10 = add i8 1, %min_load
  %tmp = trunc i8 %min10 to i6
  %tmp_2 = icmp ugt i8 %min10, 53
  %p_s = select i1 %tmp_2, i6 -16, i6 %tmp
  %p_cast = zext i6 %p_s to i8
  store i8 48, i8* %sec1
  store i8 48, i8* %min1
  store i8 %p_cast, i8* %min
  store i8 48, i8* %msec
  br label %.preheader.backedge

.preheader.backedge.pre:                          ; preds = %3
  store i8 %sec1_1, i8* %sec1
  store i8 48, i8* %msec
  br label %.preheader.backedge

.preheader.backedge.pre1:                         ; preds = %4
  store i8 48, i8* %sec1
  store i8 %sec10, i8* %sec10_1
  store i8 48, i8* %msec
  br label %.preheader.backedge

.preheader.backedge.pre2:                         ; preds = %5
  store i8 48, i8* %sec1
  store i8 %min1_1, i8* %min1
  store i8 48, i8* %msec
  br label %.preheader.backedge

.preheader.backedge.pre3:                         ; preds = %.preheader
  store i8 %msec_1, i8* %msec
  br label %.preheader.backedge

.preheader.backedge:                              ; preds = %.preheader.backedge.pre3, %.preheader.backedge.pre2, %.preheader.backedge.pre1, %.preheader.backedge.pre, %6
  br label %.preheader
}

define weak void @_ssdm_op_Write.ap_none.volatile.i8P(i8*, i8) {
entry:
  store i8 %1, i8* %0
  ret void
}

define weak void @_ssdm_op_Write.ap_none.volatile.i1P(i1*, i1) {
entry:
  store i1 %1, i1* %0
  ret void
}

define weak void @_ssdm_op_Wait(...) nounwind {
entry:
  ret void
}

define weak void @_ssdm_op_SpecTopModule(...) nounwind {
entry:
  ret void
}

define weak i32 @_ssdm_op_SpecLoopTripCount(...) {
entry:
  ret i32 0
}

define weak void @_ssdm_op_SpecInterface(...) nounwind {
entry:
  ret void
}

define weak i8 @_ssdm_op_Read.ap_none.volatile.i8P(i8*) {
entry:
  %empty = load i8* %0
  ret i8 %empty
}

define weak i1 @_ssdm_op_Read.ap_none.volatile.i1P(i1*) {
entry:
  %empty = load i1* %0
  ret i1 %empty
}

define weak i8 @_ssdm_op_Read.ap_auto.i8(i8) {
entry:
  ret i8 %0
}

define weak i7 @_ssdm_op_Read.ap_auto.i7(i7) {
entry:
  ret i7 %0
}

declare i6 @_ssdm_op_PartSelect.i6.i8.i32.i32(i8, i32, i32) nounwind readnone

!hls.encrypted.func = !{}
!llvm.map.gv = !{!0, !7, !12, !17, !22}

!0 = metadata !{metadata !1, i1* @mem_wreq}
!1 = metadata !{metadata !2}
!2 = metadata !{i32 0, i32 0, metadata !3}
!3 = metadata !{metadata !4}
!4 = metadata !{metadata !"mem_wreq", metadata !5, metadata !"uint1", i32 0, i32 0}
!5 = metadata !{metadata !6}
!6 = metadata !{i32 0, i32 0, i32 1}
!7 = metadata !{metadata !8, i8* @mem_dout}
!8 = metadata !{metadata !9}
!9 = metadata !{i32 0, i32 7, metadata !10}
!10 = metadata !{metadata !11}
!11 = metadata !{metadata !"mem_dout", metadata !5, metadata !"uint8", i32 0, i32 7}
!12 = metadata !{metadata !13, i8* @mem_addr}
!13 = metadata !{metadata !14}
!14 = metadata !{i32 0, i32 7, metadata !15}
!15 = metadata !{metadata !16}
!16 = metadata !{metadata !"mem_addr", metadata !5, metadata !"uint8", i32 0, i32 7}
!17 = metadata !{metadata !18, i1* @mem_ack}
!18 = metadata !{metadata !19}
!19 = metadata !{i32 0, i32 0, metadata !20}
!20 = metadata !{metadata !21}
!21 = metadata !{metadata !"mem_ack", metadata !5, metadata !"uint1", i32 0, i32 0}
!22 = metadata !{metadata !23, i1* @dummy_tmr_out}
!23 = metadata !{metadata !24}
!24 = metadata !{i32 0, i32 0, metadata !25}
!25 = metadata !{metadata !26}
!26 = metadata !{metadata !"dummy_tmr_out", metadata !5, metadata !"uint1", i32 0, i32 0}
