// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="clock_top,hls_ip_2016_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a35ticsg324-1l,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.080000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=172,HLS_SYN_LUT=234}" *)

module clock_top (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        dummy_tmr_out_i,
        dummy_tmr_out_o,
        mem_addr_i,
        mem_addr_o,
        mem_dout_i,
        mem_dout_o,
        mem_wreq_i,
        mem_wreq_o,
        mem_ack
);

parameter    ap_ST_st1_fsm_0 = 18'b1;
parameter    ap_ST_st2_fsm_1 = 18'b10;
parameter    ap_ST_st3_fsm_2 = 18'b100;
parameter    ap_ST_st4_fsm_3 = 18'b1000;
parameter    ap_ST_st5_fsm_4 = 18'b10000;
parameter    ap_ST_st6_fsm_5 = 18'b100000;
parameter    ap_ST_st7_fsm_6 = 18'b1000000;
parameter    ap_ST_st8_fsm_7 = 18'b10000000;
parameter    ap_ST_st9_fsm_8 = 18'b100000000;
parameter    ap_ST_st10_fsm_9 = 18'b1000000000;
parameter    ap_ST_st11_fsm_10 = 18'b10000000000;
parameter    ap_ST_st12_fsm_11 = 18'b100000000000;
parameter    ap_ST_st13_fsm_12 = 18'b1000000000000;
parameter    ap_ST_st14_fsm_13 = 18'b10000000000000;
parameter    ap_ST_st15_fsm_14 = 18'b100000000000000;
parameter    ap_ST_st16_fsm_15 = 18'b1000000000000000;
parameter    ap_ST_st17_fsm_16 = 18'b10000000000000000;
parameter    ap_ST_st18_fsm_17 = 18'b100000000000000000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv32_4 = 32'b100;
parameter    ap_const_lv32_6 = 32'b110;
parameter    ap_const_lv32_A = 32'b1010;
parameter    ap_const_lv32_C = 32'b1100;
parameter    ap_const_lv32_10 = 32'b10000;
parameter    ap_const_lv6_0 = 6'b000000;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv32_5 = 32'b101;
parameter    ap_const_lv32_8 = 32'b1000;
parameter    ap_const_lv32_E = 32'b1110;
parameter    ap_const_lv7_10 = 7'b10000;
parameter    ap_const_lv7_11 = 7'b10001;
parameter    ap_const_lv32_7 = 32'b111;
parameter    ap_const_lv7_12 = 7'b10010;
parameter    ap_const_lv32_9 = 32'b1001;
parameter    ap_const_lv7_13 = 7'b10011;
parameter    ap_const_lv32_B = 32'b1011;
parameter    ap_const_lv7_14 = 7'b10100;
parameter    ap_const_lv32_D = 32'b1101;
parameter    ap_const_lv7_15 = 7'b10101;
parameter    ap_const_lv32_F = 32'b1111;
parameter    ap_const_lv7_16 = 7'b10110;
parameter    ap_const_lv32_11 = 32'b10001;
parameter    ap_const_lv8_20 = 8'b100000;
parameter    ap_const_lv8_3A = 8'b111010;
parameter    ap_const_lv8_2E = 8'b101110;
parameter    ap_const_lv8_30 = 8'b110000;
parameter    ap_const_lv6_20 = 6'b100000;
parameter    ap_const_lv6_1 = 6'b1;
parameter    ap_const_lv8_1 = 8'b1;
parameter    ap_const_lv8_39 = 8'b111001;
parameter    ap_const_lv8_35 = 8'b110101;
parameter    ap_const_lv6_30 = 6'b110000;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [0:0] dummy_tmr_out_i;
output  [0:0] dummy_tmr_out_o;
input  [7:0] mem_addr_i;
output  [7:0] mem_addr_o;
input  [7:0] mem_dout_i;
output  [7:0] mem_dout_o;
input  [0:0] mem_wreq_i;
output  [0:0] mem_wreq_o;
input  [0:0] mem_ack;

reg ap_idle;

(* fsm_encoding = "none" *) reg   [17:0] ap_CS_fsm;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_33;
reg   [0:0] dummy_tmr_out_0_data_reg;
reg    dummy_tmr_out_0_vld_reg;
wire    dummy_tmr_out_0_ack_out;
reg   [0:0] dummy_tmr_out_1_data_reg;
reg    dummy_tmr_out_1_vld_reg;
reg    dummy_tmr_out_1_vld_in;
reg   [7:0] mem_addr_1_data_reg;
reg    mem_addr_1_vld_reg;
reg    mem_addr_1_vld_in;
reg   [7:0] mem_dout_1_data_reg;
reg    mem_dout_1_vld_reg;
reg    mem_dout_1_vld_in;
reg   [0:0] mem_wreq_1_data_reg;
reg    mem_wreq_1_vld_reg;
reg    mem_wreq_1_vld_in;
wire   [5:0] pos_1_fu_187_p2;
reg   [5:0] pos_1_reg_322;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_251;
wire   [6:0] pos_cast1_cast_fu_193_p1;
reg   [6:0] pos_cast1_cast_reg_327;
wire   [0:0] exitcond_fu_181_p2;
reg   [7:0] min_load_reg_367;
reg    ap_sig_cseq_ST_st5_fsm_4;
reg    ap_sig_265;
reg   [7:0] min1_load_reg_373;
reg    ap_sig_cseq_ST_st7_fsm_6;
reg    ap_sig_274;
reg   [7:0] sec10_1_load_reg_379;
reg    ap_sig_cseq_ST_st11_fsm_10;
reg    ap_sig_283;
reg   [7:0] sec1_load_reg_385;
reg    ap_sig_cseq_ST_st13_fsm_12;
reg    ap_sig_292;
reg    ap_sig_cseq_ST_st17_fsm_16;
reg    ap_sig_301;
wire    grp_clock_top_wait_tmr_fu_131_ap_start;
wire    grp_clock_top_wait_tmr_fu_131_ap_done;
wire    grp_clock_top_wait_tmr_fu_131_ap_idle;
wire    grp_clock_top_wait_tmr_fu_131_ap_ready;
wire   [0:0] grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o;
wire    grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o_ap_vld;
wire    grp_clock_top_write_mem_fu_137_ap_start;
wire    grp_clock_top_write_mem_fu_137_ap_done;
wire    grp_clock_top_write_mem_fu_137_ap_idle;
wire    grp_clock_top_write_mem_fu_137_ap_ready;
reg   [6:0] grp_clock_top_write_mem_fu_137_addr;
reg   [7:0] grp_clock_top_write_mem_fu_137_data;
wire   [7:0] grp_clock_top_write_mem_fu_137_mem_addr;
wire    grp_clock_top_write_mem_fu_137_mem_addr_ap_vld;
wire   [7:0] grp_clock_top_write_mem_fu_137_mem_dout;
wire    grp_clock_top_write_mem_fu_137_mem_dout_ap_vld;
wire   [0:0] grp_clock_top_write_mem_fu_137_mem_wreq;
wire    grp_clock_top_write_mem_fu_137_mem_wreq_ap_vld;
reg   [5:0] pos_reg_120;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_335;
reg    ap_sig_cseq_ST_st4_fsm_3;
reg    ap_sig_342;
reg    ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start;
reg    ap_sig_cseq_ST_st6_fsm_5;
reg    ap_sig_354;
reg    ap_reg_grp_clock_top_write_mem_fu_137_ap_start;
reg    ap_sig_cseq_ST_st9_fsm_8;
reg    ap_sig_367;
reg    ap_sig_cseq_ST_st15_fsm_14;
reg    ap_sig_377;
reg    ap_sig_cseq_ST_st8_fsm_7;
reg    ap_sig_388;
reg    ap_sig_cseq_ST_st10_fsm_9;
reg    ap_sig_396;
reg    ap_sig_cseq_ST_st12_fsm_11;
reg    ap_sig_404;
reg    ap_sig_cseq_ST_st14_fsm_13;
reg    ap_sig_412;
reg    ap_sig_cseq_ST_st16_fsm_15;
reg    ap_sig_420;
reg    ap_sig_cseq_ST_st18_fsm_17;
reg    ap_sig_428;
reg   [7:0] msec_fu_70;
wire   [7:0] msec_1_fu_223_p2;
wire   [0:0] tmp_7_fu_228_p2;
wire   [0:0] tmp_9_fu_244_p2;
wire   [0:0] tmp_s_fu_260_p2;
wire   [0:0] tmp_1_fu_276_p2;
reg   [7:0] min_fu_74;
wire   [7:0] p_cast_fu_310_p1;
reg   [7:0] min1_fu_78;
wire   [7:0] min1_1_fu_271_p2;
reg   [7:0] sec10_1_fu_82;
wire   [7:0] sec10_fu_255_p2;
reg   [7:0] sec1_fu_86;
wire   [7:0] sec1_1_fu_239_p2;
wire   [7:0] min10_fu_287_p2;
wire   [0:0] tmp_2_fu_296_p2;
wire   [5:0] tmp_fu_292_p1;
wire   [5:0] p_s_fu_302_p3;
reg   [17:0] ap_NS_fsm;

// power-on initialization
initial begin
#0 ap_CS_fsm = 18'b1;
#0 dummy_tmr_out_0_data_reg = 1'b0;
#0 dummy_tmr_out_0_vld_reg = 1'b0;
#0 dummy_tmr_out_1_data_reg = 1'b0;
#0 dummy_tmr_out_1_vld_reg = 1'b0;
#0 mem_addr_1_data_reg = 8'b00000000;
#0 mem_addr_1_vld_reg = 1'b0;
#0 mem_dout_1_data_reg = 8'b00000000;
#0 mem_dout_1_vld_reg = 1'b0;
#0 mem_wreq_1_data_reg = 1'b0;
#0 mem_wreq_1_vld_reg = 1'b0;
#0 ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start = 1'b0;
#0 ap_reg_grp_clock_top_write_mem_fu_137_ap_start = 1'b0;
end

clock_top_wait_tmr grp_clock_top_wait_tmr_fu_131(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_clock_top_wait_tmr_fu_131_ap_start),
    .ap_done(grp_clock_top_wait_tmr_fu_131_ap_done),
    .ap_idle(grp_clock_top_wait_tmr_fu_131_ap_idle),
    .ap_ready(grp_clock_top_wait_tmr_fu_131_ap_ready),
    .dummy_tmr_out_i(dummy_tmr_out_0_data_reg),
    .dummy_tmr_out_o(grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o),
    .dummy_tmr_out_o_ap_vld(grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o_ap_vld)
);

clock_top_write_mem grp_clock_top_write_mem_fu_137(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_clock_top_write_mem_fu_137_ap_start),
    .ap_done(grp_clock_top_write_mem_fu_137_ap_done),
    .ap_idle(grp_clock_top_write_mem_fu_137_ap_idle),
    .ap_ready(grp_clock_top_write_mem_fu_137_ap_ready),
    .addr(grp_clock_top_write_mem_fu_137_addr),
    .data(grp_clock_top_write_mem_fu_137_data),
    .mem_addr(grp_clock_top_write_mem_fu_137_mem_addr),
    .mem_addr_ap_vld(grp_clock_top_write_mem_fu_137_mem_addr_ap_vld),
    .mem_dout(grp_clock_top_write_mem_fu_137_mem_dout),
    .mem_dout_ap_vld(grp_clock_top_write_mem_fu_137_mem_dout_ap_vld),
    .mem_wreq(grp_clock_top_write_mem_fu_137_mem_wreq),
    .mem_wreq_ap_vld(grp_clock_top_write_mem_fu_137_mem_wreq_ap_vld),
    .mem_ack(mem_ack)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start <= 1'b0;
    end else begin
        if ((1'b1 == ap_sig_cseq_ST_st5_fsm_4)) begin
            ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start <= 1'b1;
        end else if ((1'b1 == grp_clock_top_wait_tmr_fu_131_ap_ready)) begin
            ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_clock_top_write_mem_fu_137_ap_start <= 1'b0;
    end else begin
        if ((((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (1'b0 == exitcond_fu_181_p2)) | (1'b1 == ap_sig_cseq_ST_st5_fsm_4) | (1'b1 == ap_sig_cseq_ST_st7_fsm_6) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st13_fsm_12) | (1'b1 == ap_sig_cseq_ST_st17_fsm_16) | (1'b1 == ap_sig_cseq_ST_st9_fsm_8) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14))) begin
            ap_reg_grp_clock_top_write_mem_fu_137_ap_start <= 1'b1;
        end else if ((1'b1 == grp_clock_top_write_mem_fu_137_ap_ready)) begin
            ap_reg_grp_clock_top_write_mem_fu_137_ap_start <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if ((~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & ~(1'b0 == tmp_s_fu_260_p2) & (1'b0 == tmp_1_fu_276_p2))) begin
        min1_fu_78 <= min1_1_fu_271_p2;
    end else if ((((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~(1'b0 == exitcond_fu_181_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & ~(1'b0 == tmp_s_fu_260_p2) & ~(1'b0 == tmp_1_fu_276_p2)))) begin
        min1_fu_78 <= ap_const_lv8_30;
    end
end

always @ (posedge ap_clk) begin
    if ((~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & ~(1'b0 == tmp_s_fu_260_p2) & ~(1'b0 == tmp_1_fu_276_p2))) begin
                min_fu_74[5 : 0] <= p_cast_fu_310_p1[5 : 0];
    end else if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~(1'b0 == exitcond_fu_181_p2))) begin
                min_fu_74[0] <= 1'b0;
        min_fu_74[1] <= 1'b0;
        min_fu_74[2] <= 1'b0;
        min_fu_74[3] <= 1'b0;
        min_fu_74[4] <= 1'b1;
        min_fu_74[5] <= 1'b1;
    end
end

always @ (posedge ap_clk) begin
    if ((~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & (1'b0 == tmp_7_fu_228_p2))) begin
        msec_fu_70 <= msec_1_fu_223_p2;
    end else if ((((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~(1'b0 == exitcond_fu_181_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & (1'b0 == tmp_9_fu_244_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & (1'b0 == tmp_s_fu_260_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & ~(1'b0 == tmp_s_fu_260_p2) & (1'b0 == tmp_1_fu_276_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & ~(1'b0 == tmp_s_fu_260_p2) & ~(1'b0 == tmp_1_fu_276_p2)))) begin
        msec_fu_70 <= ap_const_lv8_30;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & ~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done))) begin
        pos_reg_120 <= pos_1_reg_322;
    end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        pos_reg_120 <= ap_const_lv6_0;
    end
end

always @ (posedge ap_clk) begin
    if ((~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & (1'b0 == tmp_s_fu_260_p2))) begin
        sec10_1_fu_82 <= sec10_fu_255_p2;
    end else if ((((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~(1'b0 == exitcond_fu_181_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & ~(1'b0 == tmp_s_fu_260_p2)))) begin
        sec10_1_fu_82 <= ap_const_lv8_30;
    end
end

always @ (posedge ap_clk) begin
    if ((~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & (1'b0 == tmp_9_fu_244_p2))) begin
        sec1_fu_86 <= sec1_1_fu_239_p2;
    end else if ((((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~(1'b0 == exitcond_fu_181_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & (1'b0 == tmp_s_fu_260_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & ~(1'b0 == tmp_s_fu_260_p2) & (1'b0 == tmp_1_fu_276_p2)) | (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done) & (1'b1 == ap_sig_cseq_ST_st18_fsm_17) & ~(1'b0 == tmp_7_fu_228_p2) & ~(1'b0 == tmp_9_fu_244_p2) & ~(1'b0 == tmp_s_fu_260_p2) & ~(1'b0 == tmp_1_fu_276_p2)))) begin
        sec1_fu_86 <= ap_const_lv8_30;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == 1'b1) & (1'b0 == dummy_tmr_out_0_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == 1'b1) & (1'b1 == dummy_tmr_out_0_vld_reg) & (1'b1 == dummy_tmr_out_0_ack_out)))) begin
        dummy_tmr_out_0_data_reg <= dummy_tmr_out_i;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == dummy_tmr_out_1_vld_in) & (1'b0 == dummy_tmr_out_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == dummy_tmr_out_1_vld_in) & (1'b1 == dummy_tmr_out_1_vld_reg) & (1'b1 == 1'b1)))) begin
        dummy_tmr_out_1_data_reg <= grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_addr_1_vld_in) & (1'b0 == mem_addr_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_addr_1_vld_in) & (1'b1 == mem_addr_1_vld_reg) & (1'b1 == 1'b1)))) begin
        mem_addr_1_data_reg <= grp_clock_top_write_mem_fu_137_mem_addr;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_dout_1_vld_in) & (1'b0 == mem_dout_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_dout_1_vld_in) & (1'b1 == mem_dout_1_vld_reg) & (1'b1 == 1'b1)))) begin
        mem_dout_1_data_reg <= grp_clock_top_write_mem_fu_137_mem_dout;
    end
end

always @ (posedge ap_clk) begin
    if (((~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_wreq_1_vld_in) & (1'b0 == mem_wreq_1_vld_reg)) | (~((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) & (1'b1 == mem_wreq_1_vld_in) & (1'b1 == mem_wreq_1_vld_reg) & (1'b1 == 1'b1)))) begin
        mem_wreq_1_data_reg <= grp_clock_top_write_mem_fu_137_mem_wreq;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_sig_cseq_ST_st7_fsm_6)) begin
        min1_load_reg_373 <= min1_fu_78;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        min_load_reg_367[5 : 0] <= min_fu_74[5 : 0];
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        pos_1_reg_322 <= pos_1_fu_187_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (1'b0 == exitcond_fu_181_p2))) begin
        pos_cast1_cast_reg_327[5 : 0] <= pos_cast1_cast_fu_193_p1[5 : 0];
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_sig_cseq_ST_st11_fsm_10)) begin
        sec10_1_load_reg_379 <= sec10_1_fu_82;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_sig_cseq_ST_st13_fsm_12)) begin
        sec1_load_reg_385 <= sec1_fu_86;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_396) begin
        ap_sig_cseq_ST_st10_fsm_9 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st10_fsm_9 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_283) begin
        ap_sig_cseq_ST_st11_fsm_10 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st11_fsm_10 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_404) begin
        ap_sig_cseq_ST_st12_fsm_11 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st12_fsm_11 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_292) begin
        ap_sig_cseq_ST_st13_fsm_12 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st13_fsm_12 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_412) begin
        ap_sig_cseq_ST_st14_fsm_13 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st14_fsm_13 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_377) begin
        ap_sig_cseq_ST_st15_fsm_14 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st15_fsm_14 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_420) begin
        ap_sig_cseq_ST_st16_fsm_15 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st16_fsm_15 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_301) begin
        ap_sig_cseq_ST_st17_fsm_16 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st17_fsm_16 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_428) begin
        ap_sig_cseq_ST_st18_fsm_17 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st18_fsm_17 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_33) begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_335) begin
        ap_sig_cseq_ST_st2_fsm_1 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_251) begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_342) begin
        ap_sig_cseq_ST_st4_fsm_3 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st4_fsm_3 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_265) begin
        ap_sig_cseq_ST_st5_fsm_4 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st5_fsm_4 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_354) begin
        ap_sig_cseq_ST_st6_fsm_5 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st6_fsm_5 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_274) begin
        ap_sig_cseq_ST_st7_fsm_6 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st7_fsm_6 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_388) begin
        ap_sig_cseq_ST_st8_fsm_7 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st8_fsm_7 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_367) begin
        ap_sig_cseq_ST_st9_fsm_8 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st9_fsm_8 = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st6_fsm_5)) begin
        dummy_tmr_out_1_vld_in = grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o_ap_vld;
    end else begin
        dummy_tmr_out_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin
        grp_clock_top_write_mem_fu_137_addr = ap_const_lv7_16;
    end else if ((1'b1 == ap_sig_cseq_ST_st16_fsm_15)) begin
        grp_clock_top_write_mem_fu_137_addr = ap_const_lv7_15;
    end else if ((1'b1 == ap_sig_cseq_ST_st14_fsm_13)) begin
        grp_clock_top_write_mem_fu_137_addr = ap_const_lv7_14;
    end else if ((1'b1 == ap_sig_cseq_ST_st12_fsm_11)) begin
        grp_clock_top_write_mem_fu_137_addr = ap_const_lv7_13;
    end else if ((1'b1 == ap_sig_cseq_ST_st10_fsm_9)) begin
        grp_clock_top_write_mem_fu_137_addr = ap_const_lv7_12;
    end else if ((1'b1 == ap_sig_cseq_ST_st8_fsm_7)) begin
        grp_clock_top_write_mem_fu_137_addr = ap_const_lv7_11;
    end else if ((1'b1 == ap_sig_cseq_ST_st6_fsm_5)) begin
        grp_clock_top_write_mem_fu_137_addr = ap_const_lv7_10;
    end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        grp_clock_top_write_mem_fu_137_addr = pos_cast1_cast_reg_327;
    end else begin
        grp_clock_top_write_mem_fu_137_addr = 'bx;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin
        grp_clock_top_write_mem_fu_137_data = msec_fu_70;
    end else if ((1'b1 == ap_sig_cseq_ST_st16_fsm_15)) begin
        grp_clock_top_write_mem_fu_137_data = ap_const_lv8_2E;
    end else if ((1'b1 == ap_sig_cseq_ST_st14_fsm_13)) begin
        grp_clock_top_write_mem_fu_137_data = sec1_load_reg_385;
    end else if ((1'b1 == ap_sig_cseq_ST_st12_fsm_11)) begin
        grp_clock_top_write_mem_fu_137_data = sec10_1_load_reg_379;
    end else if ((1'b1 == ap_sig_cseq_ST_st10_fsm_9)) begin
        grp_clock_top_write_mem_fu_137_data = ap_const_lv8_3A;
    end else if ((1'b1 == ap_sig_cseq_ST_st8_fsm_7)) begin
        grp_clock_top_write_mem_fu_137_data = min1_load_reg_373;
    end else if ((1'b1 == ap_sig_cseq_ST_st6_fsm_5)) begin
        grp_clock_top_write_mem_fu_137_data = min_load_reg_367;
    end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        grp_clock_top_write_mem_fu_137_data = ap_const_lv8_20;
    end else begin
        grp_clock_top_write_mem_fu_137_data = 'bx;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st10_fsm_9) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin
        mem_addr_1_vld_in = grp_clock_top_write_mem_fu_137_mem_addr_ap_vld;
    end else begin
        mem_addr_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st10_fsm_9) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin
        mem_dout_1_vld_in = grp_clock_top_write_mem_fu_137_mem_dout_ap_vld;
    end else begin
        mem_dout_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | (1'b1 == ap_sig_cseq_ST_st10_fsm_9) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin
        mem_wreq_1_vld_in = grp_clock_top_write_mem_fu_137_mem_wreq_ap_vld;
    end else begin
        mem_wreq_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : begin
            if (~(ap_start == 1'b0)) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : begin
            ap_NS_fsm = ap_ST_st3_fsm_2;
        end
        ap_ST_st3_fsm_2 : begin
            if (~(1'b0 == exitcond_fu_181_p2)) begin
                ap_NS_fsm = ap_ST_st5_fsm_4;
            end else begin
                ap_NS_fsm = ap_ST_st4_fsm_3;
            end
        end
        ap_ST_st4_fsm_3 : begin
            if (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done)) begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end else begin
                ap_NS_fsm = ap_ST_st4_fsm_3;
            end
        end
        ap_ST_st5_fsm_4 : begin
            ap_NS_fsm = ap_ST_st6_fsm_5;
        end
        ap_ST_st6_fsm_5 : begin
            if (~((1'b0 == grp_clock_top_write_mem_fu_137_ap_done) | (1'b0 == grp_clock_top_wait_tmr_fu_131_ap_done))) begin
                ap_NS_fsm = ap_ST_st7_fsm_6;
            end else begin
                ap_NS_fsm = ap_ST_st6_fsm_5;
            end
        end
        ap_ST_st7_fsm_6 : begin
            ap_NS_fsm = ap_ST_st8_fsm_7;
        end
        ap_ST_st8_fsm_7 : begin
            if (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done)) begin
                ap_NS_fsm = ap_ST_st9_fsm_8;
            end else begin
                ap_NS_fsm = ap_ST_st8_fsm_7;
            end
        end
        ap_ST_st9_fsm_8 : begin
            ap_NS_fsm = ap_ST_st10_fsm_9;
        end
        ap_ST_st10_fsm_9 : begin
            if (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done)) begin
                ap_NS_fsm = ap_ST_st11_fsm_10;
            end else begin
                ap_NS_fsm = ap_ST_st10_fsm_9;
            end
        end
        ap_ST_st11_fsm_10 : begin
            ap_NS_fsm = ap_ST_st12_fsm_11;
        end
        ap_ST_st12_fsm_11 : begin
            if (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done)) begin
                ap_NS_fsm = ap_ST_st13_fsm_12;
            end else begin
                ap_NS_fsm = ap_ST_st12_fsm_11;
            end
        end
        ap_ST_st13_fsm_12 : begin
            ap_NS_fsm = ap_ST_st14_fsm_13;
        end
        ap_ST_st14_fsm_13 : begin
            if (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done)) begin
                ap_NS_fsm = ap_ST_st15_fsm_14;
            end else begin
                ap_NS_fsm = ap_ST_st14_fsm_13;
            end
        end
        ap_ST_st15_fsm_14 : begin
            ap_NS_fsm = ap_ST_st16_fsm_15;
        end
        ap_ST_st16_fsm_15 : begin
            if (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done)) begin
                ap_NS_fsm = ap_ST_st17_fsm_16;
            end else begin
                ap_NS_fsm = ap_ST_st16_fsm_15;
            end
        end
        ap_ST_st17_fsm_16 : begin
            ap_NS_fsm = ap_ST_st18_fsm_17;
        end
        ap_ST_st18_fsm_17 : begin
            if (~(1'b0 == grp_clock_top_write_mem_fu_137_ap_done)) begin
                ap_NS_fsm = ap_ST_st5_fsm_4;
            end else begin
                ap_NS_fsm = ap_ST_st18_fsm_17;
            end
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_done = 1'b0;

assign ap_ready = 1'b0;

always @ (*) begin
    ap_sig_251 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]);
end

always @ (*) begin
    ap_sig_265 = (1'b1 == ap_CS_fsm[ap_const_lv32_4]);
end

always @ (*) begin
    ap_sig_274 = (1'b1 == ap_CS_fsm[ap_const_lv32_6]);
end

always @ (*) begin
    ap_sig_283 = (1'b1 == ap_CS_fsm[ap_const_lv32_A]);
end

always @ (*) begin
    ap_sig_292 = (1'b1 == ap_CS_fsm[ap_const_lv32_C]);
end

always @ (*) begin
    ap_sig_301 = (1'b1 == ap_CS_fsm[ap_const_lv32_10]);
end

always @ (*) begin
    ap_sig_33 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end

always @ (*) begin
    ap_sig_335 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]);
end

always @ (*) begin
    ap_sig_342 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]);
end

always @ (*) begin
    ap_sig_354 = (1'b1 == ap_CS_fsm[ap_const_lv32_5]);
end

always @ (*) begin
    ap_sig_367 = (1'b1 == ap_CS_fsm[ap_const_lv32_8]);
end

always @ (*) begin
    ap_sig_377 = (1'b1 == ap_CS_fsm[ap_const_lv32_E]);
end

always @ (*) begin
    ap_sig_388 = (1'b1 == ap_CS_fsm[ap_const_lv32_7]);
end

always @ (*) begin
    ap_sig_396 = (1'b1 == ap_CS_fsm[ap_const_lv32_9]);
end

always @ (*) begin
    ap_sig_404 = (1'b1 == ap_CS_fsm[ap_const_lv32_B]);
end

always @ (*) begin
    ap_sig_412 = (1'b1 == ap_CS_fsm[ap_const_lv32_D]);
end

always @ (*) begin
    ap_sig_420 = (1'b1 == ap_CS_fsm[ap_const_lv32_F]);
end

always @ (*) begin
    ap_sig_428 = (1'b1 == ap_CS_fsm[ap_const_lv32_11]);
end

assign dummy_tmr_out_0_ack_out = 1'b0;

assign dummy_tmr_out_o = dummy_tmr_out_1_data_reg;

assign exitcond_fu_181_p2 = ((pos_reg_120 == ap_const_lv6_20) ? 1'b1 : 1'b0);

assign grp_clock_top_wait_tmr_fu_131_ap_start = ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start;

assign grp_clock_top_write_mem_fu_137_ap_start = ap_reg_grp_clock_top_write_mem_fu_137_ap_start;

assign mem_addr_o = mem_addr_1_data_reg;

assign mem_dout_o = mem_dout_1_data_reg;

assign mem_wreq_o = mem_wreq_1_data_reg;

assign min10_fu_287_p2 = (ap_const_lv8_1 + min_load_reg_367);

assign min1_1_fu_271_p2 = (min1_load_reg_373 + ap_const_lv8_1);

assign msec_1_fu_223_p2 = (msec_fu_70 + ap_const_lv8_1);

assign p_cast_fu_310_p1 = p_s_fu_302_p3;

assign p_s_fu_302_p3 = ((tmp_2_fu_296_p2[0:0] === 1'b1) ? ap_const_lv6_30 : tmp_fu_292_p1);

assign pos_1_fu_187_p2 = (pos_reg_120 + ap_const_lv6_1);

assign pos_cast1_cast_fu_193_p1 = pos_reg_120;

assign sec10_fu_255_p2 = (sec10_1_load_reg_379 + ap_const_lv8_1);

assign sec1_1_fu_239_p2 = (sec1_load_reg_385 + ap_const_lv8_1);

assign tmp_1_fu_276_p2 = ((min1_1_fu_271_p2 > ap_const_lv8_39) ? 1'b1 : 1'b0);

assign tmp_2_fu_296_p2 = ((min10_fu_287_p2 > ap_const_lv8_35) ? 1'b1 : 1'b0);

assign tmp_7_fu_228_p2 = ((msec_1_fu_223_p2 > ap_const_lv8_39) ? 1'b1 : 1'b0);

assign tmp_9_fu_244_p2 = ((sec1_1_fu_239_p2 > ap_const_lv8_39) ? 1'b1 : 1'b0);

assign tmp_fu_292_p1 = min10_fu_287_p2[5:0];

assign tmp_s_fu_260_p2 = ((sec10_fu_255_p2 > ap_const_lv8_35) ? 1'b1 : 1'b0);

always @ (posedge ap_clk) begin
    pos_cast1_cast_reg_327[6] <= 1'b0;
    min_load_reg_367[7:6] <= 2'b00;
    min_fu_74[7:6] <= 2'b00;
end

endmodule //clock_top
