; ModuleID = 'D:/20_sample_artix7/lcddrv/solution1/.autopilot/db/a.o.2.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-w64-mingw32"

@rs = global i1 false, align 1                    ; [#uses=5 type=i1*]
@mem_req = global i1 false, align 1               ; [#uses=5 type=i1*]
@mem_din = common global i8 0, align 1            ; [#uses=3 type=i8*]
@mem_addr = global i5 0, align 1                  ; [#uses=4 type=i5*]
@mem_ack = common global i1 false, align 1        ; [#uses=3 type=i1*]
@ind = global i1 false, align 1                   ; [#uses=2 type=i1*]
@en = global i1 false, align 1                    ; [#uses=6 type=i1*]
@dummy_tmr_out = global i1 false, align 1         ; [#uses=4 type=i1*]
@data = global i4 0, align 1                      ; [#uses=5 type=i4*]
@.str2 = private unnamed_addr constant [12 x i8] c"hls_label_0\00", align 1 ; [#uses=2 type=[12 x i8]*]
@.str1 = private unnamed_addr constant [8 x i8] c"ap_none\00", align 1 ; [#uses=9 type=[8 x i8]*]
@.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1 ; [#uses=36 type=[1 x i8]*]

; [#uses=13]
define internal fastcc void @wait_tmr(i25 %tmr) {
  call void @llvm.dbg.value(metadata !{i25 %tmr}, i64 0, metadata !72), !dbg !80 ; [debug line = 65:22] [debug variable = tmr]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !81 ; [debug line = 69:2]
  br label %1, !dbg !83                           ; [debug line = 70:7]

; <label>:1                                       ; preds = %3, %0
  %t = phi i24 [ 0, %0 ], [ %t.1, %3 ]            ; [#uses=2 type=i24]
  %t.cast = zext i24 %t to i25, !dbg !83          ; [#uses=1 type=i25] [debug line = 70:7]
  %exitcond = icmp eq i25 %t.cast, %tmr, !dbg !83 ; [#uses=1 type=i1] [debug line = 70:7]
  %2 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 1000, i64 10000000, i64 0) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond, label %4, label %3, !dbg !83   ; [debug line = 70:7]

; <label>:3                                       ; preds = %1
  %dummy_tmr_out.load = load volatile i1* @dummy_tmr_out, align 1, !dbg !85 ; [#uses=1 type=i1] [debug line = 71:3]
  %not. = xor i1 %dummy_tmr_out.load, true, !dbg !85 ; [#uses=1 type=i1] [debug line = 71:3]
  store volatile i1 %not., i1* @dummy_tmr_out, align 1, !dbg !85 ; [debug line = 71:3]
  %t.1 = add i24 %t, 1, !dbg !87                  ; [#uses=1 type=i24] [debug line = 70:23]
  call void @llvm.dbg.value(metadata !{i24 %t.1}, i64 0, metadata !88), !dbg !87 ; [debug line = 70:23] [debug variable = t]
  br label %1, !dbg !87                           ; [debug line = 70:23]

; <label>:4                                       ; preds = %1
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !89 ; [debug line = 73:2]
  ret void, !dbg !90                              ; [debug line = 74:1]
}

; [#uses=2]
define internal fastcc zeroext i8 @read_mem(i5 zeroext %addr) nounwind uwtable {
  call void @llvm.dbg.value(metadata !{i5 %addr}, i64 0, metadata !91), !dbg !95 ; [debug line = 138:22] [debug variable = addr]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !96 ; [debug line = 143:2]
  store volatile i5 %addr, i5* @mem_addr, align 1, !dbg !98 ; [debug line = 144:2]
  store volatile i1 true, i1* @mem_req, align 1, !dbg !99 ; [debug line = 145:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !100 ; [debug line = 146:2]
  br label %._crit_edge, !dbg !101                ; [debug line = 147:2]

._crit_edge:                                      ; preds = %._crit_edge, %0
  store volatile i5 %addr, i5* @mem_addr, align 1, !dbg !102 ; [debug line = 148:3]
  store volatile i1 true, i1* @mem_req, align 1, !dbg !104 ; [debug line = 149:3]
  %dt = load volatile i8* @mem_din, align 1, !dbg !105 ; [#uses=1 type=i8] [debug line = 150:3]
  call void @llvm.dbg.value(metadata !{i8 %dt}, i64 0, metadata !106), !dbg !105 ; [debug line = 150:3] [debug variable = dt]
  %mem_ack.load = load volatile i1* @mem_ack, align 1, !dbg !107 ; [#uses=1 type=i1] [debug line = 151:2]
  br i1 %mem_ack.load, label %1, label %._crit_edge, !dbg !107 ; [debug line = 151:2]

; <label>:1                                       ; preds = %._crit_edge
  %dt.lcssa = phi i8 [ %dt, %._crit_edge ]        ; [#uses=1 type=i8]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !108 ; [debug line = 152:2]
  store volatile i1 false, i1* @mem_req, align 1, !dbg !109 ; [debug line = 153:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !110 ; [debug line = 154:2]
  ret i8 %dt.lcssa, !dbg !111                     ; [debug line = 156:2]
}

; [#uses=10]
declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone

; [#uses=0]
define void @lcddrv() noreturn nounwind uwtable {
  call void (...)* @_ssdm_op_SpecTopModule(), !dbg !112 ; [debug line = 162:1]
  %dummy_tmr_out.load = load volatile i1* @dummy_tmr_out, align 1, !dbg !117 ; [#uses=0 type=i1] [debug line = 163:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @dummy_tmr_out, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !117 ; [debug line = 163:1]
  %rs.load = load volatile i1* @rs, align 1, !dbg !118 ; [#uses=0 type=i1] [debug line = 165:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @rs, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !118 ; [debug line = 165:1]
  %en.load = load volatile i1* @en, align 1, !dbg !119 ; [#uses=0 type=i1] [debug line = 166:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @en, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !119 ; [debug line = 166:1]
  %data.load = load volatile i4* @data, align 1, !dbg !120 ; [#uses=0 type=i4] [debug line = 167:1]
  call void (...)* @_ssdm_op_SpecInterface(i4* @data, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !120 ; [debug line = 167:1]
  %ind.load = load volatile i1* @ind, align 1, !dbg !121 ; [#uses=0 type=i1] [debug line = 168:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @ind, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !121 ; [debug line = 168:1]
  %mem_addr.load = load volatile i5* @mem_addr, align 1, !dbg !122 ; [#uses=0 type=i5] [debug line = 170:1]
  call void (...)* @_ssdm_op_SpecInterface(i5* @mem_addr, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !122 ; [debug line = 170:1]
  %mem_din.load = load volatile i8* @mem_din, align 1, !dbg !123 ; [#uses=0 type=i8] [debug line = 171:1]
  call void (...)* @_ssdm_op_SpecInterface(i8* @mem_din, [8 x i8]* @.str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !123 ; [debug line = 171:1]
  %mem_req.load = load volatile i1* @mem_req, align 1, !dbg !124 ; [#uses=0 type=i1] [debug line = 172:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @mem_req, [8 x i8]* @.str1, i32 1, i32 1, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !124 ; [debug line = 172:1]
  %mem_ack.load = load volatile i1* @mem_ack, align 1, !dbg !125 ; [#uses=0 type=i1] [debug line = 173:1]
  call void (...)* @_ssdm_op_SpecInterface(i1* @mem_ack, [8 x i8]* @.str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str, [1 x i8]* @.str, [1 x i8]* @.str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @.str) nounwind, !dbg !125 ; [debug line = 173:1]
  call fastcc void @init_lcd(), !dbg !126         ; [debug line = 178:2]
  br label %1, !dbg !127                          ; [debug line = 180:2]

; <label>:1                                       ; preds = %9, %0
  %loop_begin = call i32 (...)* @_ssdm_op_SpecLoopBegin() nounwind ; [#uses=0 type=i32]
  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @.str2) nounwind, !dbg !128 ; [#uses=1 type=i32] [debug line = 180:13]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext -8), !dbg !130 ; [debug line = 182:3]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 0), !dbg !131 ; [debug line = 183:3]
  br label %2, !dbg !132                          ; [debug line = 185:8]

; <label>:2                                       ; preds = %4, %1
  %pos = phi i5 [ 0, %1 ], [ %pos.2, %4 ]         ; [#uses=3 type=i5]
  %exitcond1 = icmp eq i5 %pos, -16, !dbg !132    ; [#uses=1 type=i1] [debug line = 185:8]
  %3 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond1, label %5, label %4, !dbg !132 ; [debug line = 185:8]

; <label>:4                                       ; preds = %2
  %dt = call fastcc zeroext i8 @read_mem(i5 zeroext %pos), !dbg !134 ; [#uses=2 type=i8] [debug line = 186:9]
  call void @llvm.dbg.value(metadata !{i8 %dt}, i64 0, metadata !136), !dbg !134 ; [debug line = 186:9] [debug variable = dt]
  %tmp. = lshr i8 %dt, 4, !dbg !137               ; [#uses=1 type=i8] [debug line = 187:4]
  %tmp.1 = trunc i8 %tmp. to i4, !dbg !137        ; [#uses=1 type=i4] [debug line = 187:4]
  call fastcc void @lcd_send_cmd(i1 zeroext true, i4 zeroext %tmp.1), !dbg !137 ; [debug line = 187:4]
  %tmp.2 = trunc i8 %dt to i4, !dbg !138          ; [#uses=1 type=i4] [debug line = 188:4]
  call fastcc void @lcd_send_cmd(i1 zeroext true, i4 zeroext %tmp.2), !dbg !138 ; [debug line = 188:4]
  %pos.2 = add i5 %pos, 1, !dbg !139              ; [#uses=1 type=i5] [debug line = 185:27]
  call void @llvm.dbg.value(metadata !{i5 %pos.2}, i64 0, metadata !140), !dbg !139 ; [debug line = 185:27] [debug variable = pos]
  br label %2, !dbg !139                          ; [debug line = 185:27]

; <label>:5                                       ; preds = %2
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext -4), !dbg !141 ; [debug line = 192:3]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 0), !dbg !142 ; [debug line = 193:3]
  br label %6, !dbg !143                          ; [debug line = 195:8]

; <label>:6                                       ; preds = %8, %5
  %pos.1 = phi i6 [ 16, %5 ], [ %pos.3, %8 ]      ; [#uses=3 type=i6]
  %exitcond = icmp eq i6 %pos.1, -32, !dbg !143   ; [#uses=1 type=i1] [debug line = 195:8]
  %7 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16) nounwind ; [#uses=0 type=i32]
  br i1 %exitcond, label %9, label %8, !dbg !143  ; [debug line = 195:8]

; <label>:8                                       ; preds = %6
  %tmp.3 = trunc i6 %pos.1 to i5, !dbg !145       ; [#uses=1 type=i5] [debug line = 196:9]
  %dt.1 = call fastcc zeroext i8 @read_mem(i5 zeroext %tmp.3), !dbg !145 ; [#uses=2 type=i8] [debug line = 196:9]
  call void @llvm.dbg.value(metadata !{i8 %dt.1}, i64 0, metadata !136), !dbg !145 ; [debug line = 196:9] [debug variable = dt]
  %tmp.4 = lshr i8 %dt.1, 4, !dbg !147            ; [#uses=1 type=i8] [debug line = 197:4]
  %tmp.5 = trunc i8 %tmp.4 to i4, !dbg !147       ; [#uses=1 type=i4] [debug line = 197:4]
  call fastcc void @lcd_send_cmd(i1 zeroext true, i4 zeroext %tmp.5), !dbg !147 ; [debug line = 197:4]
  %tmp.6 = trunc i8 %dt.1 to i4, !dbg !148        ; [#uses=1 type=i4] [debug line = 198:4]
  call fastcc void @lcd_send_cmd(i1 zeroext true, i4 zeroext %tmp.6), !dbg !148 ; [debug line = 198:4]
  %pos.3 = add i6 %pos.1, 1, !dbg !149            ; [#uses=1 type=i6] [debug line = 195:28]
  call void @llvm.dbg.value(metadata !{i6 %pos.3}, i64 0, metadata !140), !dbg !149 ; [debug line = 195:28] [debug variable = pos]
  br label %6, !dbg !149                          ; [debug line = 195:28]

; <label>:9                                       ; preds = %6
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !150 ; [debug line = 202:3]
  call fastcc void @wait_tmr(i25 10000000) nounwind, !dbg !151 ; [debug line = 203:3]
  %10 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @.str2, i32 %tmp) nounwind, !dbg !152 ; [#uses=0 type=i32] [debug line = 204:2]
  br label %1, !dbg !152                          ; [debug line = 204:2]
}

; [#uses=20]
define internal fastcc void @lcd_send_cmd(i1 zeroext %mode, i4 zeroext %wd) nounwind uwtable {
  call void @llvm.dbg.value(metadata !{i1 %mode}, i64 0, metadata !153), !dbg !157 ; [debug line = 77:25] [debug variable = mode]
  call void @llvm.dbg.value(metadata !{i4 %wd}, i64 0, metadata !158), !dbg !159 ; [debug line = 77:37] [debug variable = wd]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !160 ; [debug line = 80:2]
  store volatile i1 false, i1* @en, align 1, !dbg !162 ; [debug line = 81:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !163 ; [debug line = 82:2]
  call fastcc void @wait_tmr(i25 1000) nounwind, !dbg !164 ; [debug line = 83:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !165 ; [debug line = 85:2]
  store volatile i1 false, i1* @en, align 1, !dbg !166 ; [debug line = 86:2]
  store volatile i1 %mode, i1* @rs, align 1, !dbg !167 ; [debug line = 87:2]
  store volatile i4 %wd, i4* @data, align 1, !dbg !168 ; [debug line = 88:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !169 ; [debug line = 89:2]
  call fastcc void @wait_tmr(i25 1000) nounwind, !dbg !170 ; [debug line = 90:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !171 ; [debug line = 92:2]
  store volatile i1 true, i1* @en, align 1, !dbg !172 ; [debug line = 93:2]
  store volatile i1 %mode, i1* @rs, align 1, !dbg !173 ; [debug line = 94:2]
  store volatile i4 %wd, i4* @data, align 1, !dbg !174 ; [debug line = 95:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !175 ; [debug line = 96:2]
  call fastcc void @wait_tmr(i25 1000) nounwind, !dbg !176 ; [debug line = 97:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !177 ; [debug line = 99:2]
  store volatile i1 false, i1* @en, align 1, !dbg !178 ; [debug line = 100:2]
  store volatile i1 %mode, i1* @rs, align 1, !dbg !179 ; [debug line = 101:2]
  store volatile i4 %wd, i4* @data, align 1, !dbg !180 ; [debug line = 102:2]
  call void (...)* @_ssdm_op_Wait(i32 1), !dbg !181 ; [debug line = 103:2]
  call fastcc void @wait_tmr(i25 1000) nounwind, !dbg !182 ; [debug line = 104:2]
  ret void, !dbg !183                             ; [debug line = 105:1]
}

; [#uses=1]
define internal fastcc void @init_lcd() nounwind uwtable {
  call fastcc void @wait_tmr(i25 2000000) nounwind, !dbg !184 ; [debug line = 111:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 3), !dbg !187 ; [debug line = 112:2]
  call fastcc void @wait_tmr(i25 500000) nounwind, !dbg !188 ; [debug line = 113:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 3), !dbg !189 ; [debug line = 114:2]
  call fastcc void @wait_tmr(i25 50000) nounwind, !dbg !190 ; [debug line = 115:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 3), !dbg !191 ; [debug line = 116:2]
  call fastcc void @wait_tmr(i25 50000) nounwind, !dbg !192 ; [debug line = 117:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 2), !dbg !193 ; [debug line = 119:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 2), !dbg !194 ; [debug line = 120:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext -8), !dbg !195 ; [debug line = 121:2]
  call fastcc void @wait_tmr(i25 10000) nounwind, !dbg !196 ; [debug line = 122:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 0), !dbg !197 ; [debug line = 124:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext -4), !dbg !198 ; [debug line = 125:2]
  call fastcc void @wait_tmr(i25 10000) nounwind, !dbg !199 ; [debug line = 126:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 0), !dbg !200 ; [debug line = 128:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 1), !dbg !201 ; [debug line = 129:2]
  call fastcc void @wait_tmr(i25 200000) nounwind, !dbg !202 ; [debug line = 130:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 0), !dbg !203 ; [debug line = 132:2]
  call fastcc void @lcd_send_cmd(i1 zeroext false, i4 zeroext 2), !dbg !204 ; [debug line = 133:2]
  call fastcc void @wait_tmr(i25 10000) nounwind, !dbg !205 ; [debug line = 134:2]
  ret void, !dbg !206                             ; [debug line = 135:1]
}

; [#uses=15]
declare void @_ssdm_op_Wait(...) nounwind

; [#uses=1]
declare void @_ssdm_op_SpecTopModule(...) nounwind

; [#uses=1]
declare i32 @_ssdm_op_SpecRegionEnd(...)

; [#uses=1]
declare i32 @_ssdm_op_SpecRegionBegin(...)

; [#uses=3]
declare i32 @_ssdm_op_SpecLoopTripCount(...)

; [#uses=1]
declare i32 @_ssdm_op_SpecLoopBegin(...)

; [#uses=9]
declare void @_ssdm_op_SpecInterface(...) nounwind

; [#uses=0]
declare void @_ssdm_SpecKeepAssert(...)

!hls.encrypted.func = !{}
!llvm.map.gv = !{!0, !7, !12, !17, !22, !27, !32, !37, !42}
!llvm.dbg.cu = !{!47}

!0 = metadata !{metadata !1, i1* @rs}
!1 = metadata !{metadata !2}
!2 = metadata !{i32 0, i32 0, metadata !3}
!3 = metadata !{metadata !4}
!4 = metadata !{metadata !"rs", metadata !5, metadata !"uint1", i32 0, i32 0}
!5 = metadata !{metadata !6}
!6 = metadata !{i32 0, i32 0, i32 1}
!7 = metadata !{metadata !8, i1* @mem_req}
!8 = metadata !{metadata !9}
!9 = metadata !{i32 0, i32 0, metadata !10}
!10 = metadata !{metadata !11}
!11 = metadata !{metadata !"mem_req", metadata !5, metadata !"uint1", i32 0, i32 0}
!12 = metadata !{metadata !13, i8* @mem_din}
!13 = metadata !{metadata !14}
!14 = metadata !{i32 0, i32 7, metadata !15}
!15 = metadata !{metadata !16}
!16 = metadata !{metadata !"mem_din", metadata !5, metadata !"uint8", i32 0, i32 7}
!17 = metadata !{metadata !18, i5* @mem_addr}
!18 = metadata !{metadata !19}
!19 = metadata !{i32 0, i32 4, metadata !20}
!20 = metadata !{metadata !21}
!21 = metadata !{metadata !"mem_addr", metadata !5, metadata !"uint5", i32 0, i32 4}
!22 = metadata !{metadata !23, i1* @mem_ack}
!23 = metadata !{metadata !24}
!24 = metadata !{i32 0, i32 0, metadata !25}
!25 = metadata !{metadata !26}
!26 = metadata !{metadata !"mem_ack", metadata !5, metadata !"uint1", i32 0, i32 0}
!27 = metadata !{metadata !28, i1* @ind}
!28 = metadata !{metadata !29}
!29 = metadata !{i32 0, i32 0, metadata !30}
!30 = metadata !{metadata !31}
!31 = metadata !{metadata !"ind", metadata !5, metadata !"uint1", i32 0, i32 0}
!32 = metadata !{metadata !33, i1* @en}
!33 = metadata !{metadata !34}
!34 = metadata !{i32 0, i32 0, metadata !35}
!35 = metadata !{metadata !36}
!36 = metadata !{metadata !"en", metadata !5, metadata !"uint1", i32 0, i32 0}
!37 = metadata !{metadata !38, i1* @dummy_tmr_out}
!38 = metadata !{metadata !39}
!39 = metadata !{i32 0, i32 0, metadata !40}
!40 = metadata !{metadata !41}
!41 = metadata !{metadata !"dummy_tmr_out", metadata !5, metadata !"uint1", i32 0, i32 0}
!42 = metadata !{metadata !43, i4* @data}
!43 = metadata !{metadata !44}
!44 = metadata !{i32 0, i32 3, metadata !45}
!45 = metadata !{metadata !46}
!46 = metadata !{metadata !"data", metadata !5, metadata !"uint4", i32 0, i32 3}
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