# 
# Synthesis run script generated by Vivado
# 

set_msg_config -id {HDL 9-1061} -limit 100000
set_msg_config -id {HDL 9-1654} -limit 100000
create_project -in_memory -part xc7a35ticsg324-1L

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir D:/20_sample_artix7/project_1/project_1.cache/wt [current_project]
set_property parent.project_path D:/20_sample_artix7/project_1/project_1.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
read_verilog -library xil_defaultlib {
  D:/20_sample_artix7/lcddrv/solution1/syn/verilog/lcddrv_wait_tmr.v
  D:/20_sample_artix7/lcddrv/solution1/syn/verilog/lcddrv_lcd_send_cmd.v
  D:/20_sample_artix7/clock/solution1/syn/verilog/clock_top_wait_tmr.v
  D:/20_sample_artix7/lcddrv/solution1/syn/verilog/lcddrv_init_lcd.v
  D:/20_sample_artix7/clock/solution1/syn/verilog/clock_top_write_mem.v
  D:/20_sample_artix7/lcddrv/solution1/syn/verilog/lcddrv_read_mem.v
  D:/20_sample_artix7/sharedmem/solution1/syn/verilog/sharedmem_mem.v
  D:/20_sample_artix7/lcddrv/solution1/syn/verilog/lcddrv.v
  D:/20_sample_artix7/clock/solution1/syn/verilog/clock_top.v
  D:/20_sample_artix7/sharedmem/solution1/syn/verilog/sharedmem.v
  D:/20_sample_artix7/car_top.v
}
foreach dcp [get_files -quiet -all *.dcp] {
  set_property used_in_implementation false $dcp
}
read_xdc D:/20_sample_artix7/car_top.xdc
set_property used_in_implementation false [get_files D:/20_sample_artix7/car_top.xdc]


synth_design -top car_top -part xc7a35ticsg324-1L


write_checkpoint -force -noxdef car_top.dcp

catch { report_utilization -file car_top_utilization_synth.rpt -pb car_top_utilization_synth.pb }
