// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module clock_top_wait_tmr (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        dummy_tmr_out_i,
        dummy_tmr_out_o,
        dummy_tmr_out_o_ap_vld
);

parameter    ap_ST_st1_fsm_0 = 3'b1;
parameter    ap_ST_st2_fsm_1 = 3'b10;
parameter    ap_ST_st3_fsm_2 = 3'b100;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv7_0 = 7'b0000000;
parameter    ap_const_lv17_0 = 17'b00000000000000000;
parameter    ap_const_lv7_64 = 7'b1100100;
parameter    ap_const_lv7_1 = 7'b1;
parameter    ap_const_lv17_186A0 = 17'b11000011010100000;
parameter    ap_const_lv17_1 = 17'b1;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [0:0] dummy_tmr_out_i;
output  [0:0] dummy_tmr_out_o;
output   dummy_tmr_out_o_ap_vld;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg[0:0] dummy_tmr_out_o;
reg dummy_tmr_out_o_ap_vld;

(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_20;
wire   [6:0] u_1_fu_67_p2;
reg   [6:0] u_1_reg_95;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_35;
wire   [16:0] t_1_fu_79_p2;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_44;
reg   [6:0] u_reg_39;
wire   [0:0] exitcond_fu_73_p2;
reg   [16:0] t_reg_50;
wire   [0:0] exitcond1_fu_61_p2;
wire   [0:0] not_s_fu_85_p2;
reg   [2:0] ap_NS_fsm;

// power-on initialization
initial begin
#0 ap_CS_fsm = 3'b1;
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond1_fu_61_p2))) begin
        t_reg_50 <= ap_const_lv17_0;
    end else if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_73_p2 == 1'b0))) begin
        t_reg_50 <= t_1_fu_79_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~(exitcond_fu_73_p2 == 1'b0))) begin
        u_reg_39 <= u_1_reg_95;
    end else if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin
        u_reg_39 <= ap_const_lv7_0;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        u_1_reg_95 <= u_1_fu_67_p2;
    end
end

always @ (*) begin
    if ((((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & ~(1'b0 == exitcond1_fu_61_p2)))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & ~(1'b0 == exitcond1_fu_61_p2))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_20) begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_35) begin
        ap_sig_cseq_ST_st2_fsm_1 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_44) begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_73_p2 == 1'b0))) begin
        dummy_tmr_out_o = not_s_fu_85_p2;
    end else begin
        dummy_tmr_out_o = dummy_tmr_out_i;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_73_p2 == 1'b0))) begin
        dummy_tmr_out_o_ap_vld = 1'b1;
    end else begin
        dummy_tmr_out_o_ap_vld = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : begin
            if (~(ap_start == 1'b0)) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : begin
            if (~(1'b0 == exitcond1_fu_61_p2)) begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end else begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end
        end
        ap_ST_st3_fsm_2 : begin
            if ((exitcond_fu_73_p2 == 1'b0)) begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end else begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

always @ (*) begin
    ap_sig_20 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end

always @ (*) begin
    ap_sig_35 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]);
end

always @ (*) begin
    ap_sig_44 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]);
end

assign exitcond1_fu_61_p2 = ((u_reg_39 == ap_const_lv7_64) ? 1'b1 : 1'b0);

assign exitcond_fu_73_p2 = ((t_reg_50 == ap_const_lv17_186A0) ? 1'b1 : 1'b0);

assign not_s_fu_85_p2 = (dummy_tmr_out_i ^ 1'b1);

assign t_1_fu_79_p2 = (t_reg_50 + ap_const_lv17_1);

assign u_1_fu_67_p2 = (u_reg_39 + ap_const_lv7_1);

endmodule //clock_top_wait_tmr
