-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.2
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity clock_top is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    dummy_tmr_out_i : IN STD_LOGIC_VECTOR (0 downto 0);
    dummy_tmr_out_o : OUT STD_LOGIC_VECTOR (0 downto 0);
    mem_addr_i : IN STD_LOGIC_VECTOR (7 downto 0);
    mem_addr_o : OUT STD_LOGIC_VECTOR (7 downto 0);
    mem_dout_i : IN STD_LOGIC_VECTOR (7 downto 0);
    mem_dout_o : OUT STD_LOGIC_VECTOR (7 downto 0);
    mem_wreq_i : IN STD_LOGIC_VECTOR (0 downto 0);
    mem_wreq_o : OUT STD_LOGIC_VECTOR (0 downto 0);
    mem_ack : IN STD_LOGIC_VECTOR (0 downto 0) );
end;


architecture behav of clock_top is 
    attribute CORE_GENERATION_INFO : STRING;
    attribute CORE_GENERATION_INFO of behav : architecture is
    "clock_top,hls_ip_2016_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a35ticsg324-1l,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.080000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=172,HLS_SYN_LUT=234}";
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
    constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000010";
    constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000100";
    constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000001000";
    constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000010000";
    constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000100000";
    constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (17 downto 0) := "000000000001000000";
    constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (17 downto 0) := "000000000010000000";
    constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (17 downto 0) := "000000000100000000";
    constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (17 downto 0) := "000000001000000000";
    constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (17 downto 0) := "000000010000000000";
    constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (17 downto 0) := "000000100000000000";
    constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (17 downto 0) := "000001000000000000";
    constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (17 downto 0) := "000010000000000000";
    constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (17 downto 0) := "000100000000000000";
    constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (17 downto 0) := "001000000000000000";
    constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (17 downto 0) := "010000000000000000";
    constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
    constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
    constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
    constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
    constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
    constant ap_const_lv7_10 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
    constant ap_const_lv7_11 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
    constant ap_const_lv7_12 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
    constant ap_const_lv7_13 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
    constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
    constant ap_const_lv7_14 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
    constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
    constant ap_const_lv7_15 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
    constant ap_const_lv7_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
    constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
    constant ap_const_lv8_20 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
    constant ap_const_lv8_3A : STD_LOGIC_VECTOR (7 downto 0) := "00111010";
    constant ap_const_lv8_2E : STD_LOGIC_VECTOR (7 downto 0) := "00101110";
    constant ap_const_lv8_30 : STD_LOGIC_VECTOR (7 downto 0) := "00110000";
    constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
    constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
    constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
    constant ap_const_lv8_39 : STD_LOGIC_VECTOR (7 downto 0) := "00111001";
    constant ap_const_lv8_35 : STD_LOGIC_VECTOR (7 downto 0) := "00110101";
    constant ap_const_lv6_30 : STD_LOGIC_VECTOR (5 downto 0) := "110000";

    signal ap_CS_fsm : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
    signal ap_sig_33 : BOOLEAN;
    signal dummy_tmr_out_0_data_reg : STD_LOGIC_VECTOR (0 downto 0) := "0";
    signal dummy_tmr_out_0_vld_reg : STD_LOGIC := '0';
    signal dummy_tmr_out_0_ack_out : STD_LOGIC;
    signal dummy_tmr_out_1_data_reg : STD_LOGIC_VECTOR (0 downto 0) := "0";
    signal dummy_tmr_out_1_vld_reg : STD_LOGIC := '0';
    signal dummy_tmr_out_1_vld_in : STD_LOGIC;
    signal mem_addr_1_data_reg : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
    signal mem_addr_1_vld_reg : STD_LOGIC := '0';
    signal mem_addr_1_vld_in : STD_LOGIC;
    signal mem_dout_1_data_reg : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
    signal mem_dout_1_vld_reg : STD_LOGIC := '0';
    signal mem_dout_1_vld_in : STD_LOGIC;
    signal mem_wreq_1_data_reg : STD_LOGIC_VECTOR (0 downto 0) := "0";
    signal mem_wreq_1_vld_reg : STD_LOGIC := '0';
    signal mem_wreq_1_vld_in : STD_LOGIC;
    signal pos_1_fu_187_p2 : STD_LOGIC_VECTOR (5 downto 0);
    signal pos_1_reg_322 : STD_LOGIC_VECTOR (5 downto 0);
    signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
    signal ap_sig_251 : BOOLEAN;
    signal pos_cast1_cast_fu_193_p1 : STD_LOGIC_VECTOR (6 downto 0);
    signal pos_cast1_cast_reg_327 : STD_LOGIC_VECTOR (6 downto 0);
    signal exitcond_fu_181_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal min_load_reg_367 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
    signal ap_sig_265 : BOOLEAN;
    signal min1_load_reg_373 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
    signal ap_sig_274 : BOOLEAN;
    signal sec10_1_load_reg_379 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
    signal ap_sig_283 : BOOLEAN;
    signal sec1_load_reg_385 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
    signal ap_sig_292 : BOOLEAN;
    signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
    signal ap_sig_301 : BOOLEAN;
    signal grp_clock_top_wait_tmr_fu_131_ap_start : STD_LOGIC;
    signal grp_clock_top_wait_tmr_fu_131_ap_done : STD_LOGIC;
    signal grp_clock_top_wait_tmr_fu_131_ap_idle : STD_LOGIC;
    signal grp_clock_top_wait_tmr_fu_131_ap_ready : STD_LOGIC;
    signal grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o : STD_LOGIC_VECTOR (0 downto 0);
    signal grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o_ap_vld : STD_LOGIC;
    signal grp_clock_top_write_mem_fu_137_ap_start : STD_LOGIC;
    signal grp_clock_top_write_mem_fu_137_ap_done : STD_LOGIC;
    signal grp_clock_top_write_mem_fu_137_ap_idle : STD_LOGIC;
    signal grp_clock_top_write_mem_fu_137_ap_ready : STD_LOGIC;
    signal grp_clock_top_write_mem_fu_137_addr : STD_LOGIC_VECTOR (6 downto 0);
    signal grp_clock_top_write_mem_fu_137_data : STD_LOGIC_VECTOR (7 downto 0);
    signal grp_clock_top_write_mem_fu_137_mem_addr : STD_LOGIC_VECTOR (7 downto 0);
    signal grp_clock_top_write_mem_fu_137_mem_addr_ap_vld : STD_LOGIC;
    signal grp_clock_top_write_mem_fu_137_mem_dout : STD_LOGIC_VECTOR (7 downto 0);
    signal grp_clock_top_write_mem_fu_137_mem_dout_ap_vld : STD_LOGIC;
    signal grp_clock_top_write_mem_fu_137_mem_wreq : STD_LOGIC_VECTOR (0 downto 0);
    signal grp_clock_top_write_mem_fu_137_mem_wreq_ap_vld : STD_LOGIC;
    signal pos_reg_120 : STD_LOGIC_VECTOR (5 downto 0);
    signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
    signal ap_sig_335 : BOOLEAN;
    signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
    signal ap_sig_342 : BOOLEAN;
    signal ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start : STD_LOGIC := '0';
    signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
    signal ap_sig_354 : BOOLEAN;
    signal ap_reg_grp_clock_top_write_mem_fu_137_ap_start : STD_LOGIC := '0';
    signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
    signal ap_sig_367 : BOOLEAN;
    signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
    signal ap_sig_377 : BOOLEAN;
    signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
    signal ap_sig_388 : BOOLEAN;
    signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
    signal ap_sig_396 : BOOLEAN;
    signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
    signal ap_sig_404 : BOOLEAN;
    signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
    signal ap_sig_412 : BOOLEAN;
    signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
    signal ap_sig_420 : BOOLEAN;
    signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
    signal ap_sig_428 : BOOLEAN;
    signal msec_fu_70 : STD_LOGIC_VECTOR (7 downto 0);
    signal msec_1_fu_223_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_7_fu_228_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_9_fu_244_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_s_fu_260_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_1_fu_276_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal min_fu_74 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_cast_fu_310_p1 : STD_LOGIC_VECTOR (7 downto 0);
    signal min1_fu_78 : STD_LOGIC_VECTOR (7 downto 0);
    signal min1_1_fu_271_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal sec10_1_fu_82 : STD_LOGIC_VECTOR (7 downto 0);
    signal sec10_fu_255_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal sec1_fu_86 : STD_LOGIC_VECTOR (7 downto 0);
    signal sec1_1_fu_239_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal min10_fu_287_p2 : STD_LOGIC_VECTOR (7 downto 0);
    signal tmp_2_fu_296_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_fu_292_p1 : STD_LOGIC_VECTOR (5 downto 0);
    signal p_s_fu_302_p3 : STD_LOGIC_VECTOR (5 downto 0);
    signal ap_NS_fsm : STD_LOGIC_VECTOR (17 downto 0);

    component clock_top_wait_tmr IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        dummy_tmr_out_i : IN STD_LOGIC_VECTOR (0 downto 0);
        dummy_tmr_out_o : OUT STD_LOGIC_VECTOR (0 downto 0);
        dummy_tmr_out_o_ap_vld : OUT STD_LOGIC );
    end component;


    component clock_top_write_mem IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        addr : IN STD_LOGIC_VECTOR (6 downto 0);
        data : IN STD_LOGIC_VECTOR (7 downto 0);
        mem_addr : OUT STD_LOGIC_VECTOR (7 downto 0);
        mem_addr_ap_vld : OUT STD_LOGIC;
        mem_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
        mem_dout_ap_vld : OUT STD_LOGIC;
        mem_wreq : OUT STD_LOGIC_VECTOR (0 downto 0);
        mem_wreq_ap_vld : OUT STD_LOGIC;
        mem_ack : IN STD_LOGIC_VECTOR (0 downto 0) );
    end component;



begin
    grp_clock_top_wait_tmr_fu_131 : component clock_top_wait_tmr
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_clock_top_wait_tmr_fu_131_ap_start,
        ap_done => grp_clock_top_wait_tmr_fu_131_ap_done,
        ap_idle => grp_clock_top_wait_tmr_fu_131_ap_idle,
        ap_ready => grp_clock_top_wait_tmr_fu_131_ap_ready,
        dummy_tmr_out_i => dummy_tmr_out_0_data_reg,
        dummy_tmr_out_o => grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o,
        dummy_tmr_out_o_ap_vld => grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o_ap_vld);

    grp_clock_top_write_mem_fu_137 : component clock_top_write_mem
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_clock_top_write_mem_fu_137_ap_start,
        ap_done => grp_clock_top_write_mem_fu_137_ap_done,
        ap_idle => grp_clock_top_write_mem_fu_137_ap_idle,
        ap_ready => grp_clock_top_write_mem_fu_137_ap_ready,
        addr => grp_clock_top_write_mem_fu_137_addr,
        data => grp_clock_top_write_mem_fu_137_data,
        mem_addr => grp_clock_top_write_mem_fu_137_mem_addr,
        mem_addr_ap_vld => grp_clock_top_write_mem_fu_137_mem_addr_ap_vld,
        mem_dout => grp_clock_top_write_mem_fu_137_mem_dout,
        mem_dout_ap_vld => grp_clock_top_write_mem_fu_137_mem_dout_ap_vld,
        mem_wreq => grp_clock_top_write_mem_fu_137_mem_wreq,
        mem_wreq_ap_vld => grp_clock_top_write_mem_fu_137_mem_wreq_ap_vld,
        mem_ack => mem_ack);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_st1_fsm_0;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then 
                    ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = grp_clock_top_wait_tmr_fu_131_ap_ready)) then 
                    ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_grp_clock_top_write_mem_fu_137_ap_start_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_grp_clock_top_write_mem_fu_137_ap_start <= ap_const_logic_0;
            else
                if ((((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = exitcond_fu_181_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14))) then 
                    ap_reg_grp_clock_top_write_mem_fu_137_ap_start <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = grp_clock_top_write_mem_fu_137_ap_ready)) then 
                    ap_reg_grp_clock_top_write_mem_fu_137_ap_start <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    dummy_tmr_out_0_vld_reg_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
        end if;
    end process;

    dummy_tmr_out_1_vld_reg_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
        end if;
    end process;

    mem_addr_1_vld_reg_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
        end if;
    end process;

    mem_dout_1_vld_reg_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
        end if;
    end process;

    mem_wreq_1_vld_reg_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
        end if;
    end process;

    min1_fu_78_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and not((ap_const_lv1_0 = tmp_s_fu_260_p2)) and (ap_const_lv1_0 = tmp_1_fu_276_p2))) then 
                min1_fu_78 <= min1_1_fu_271_p2;
            elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = exitcond_fu_181_p2))) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and not((ap_const_lv1_0 = tmp_s_fu_260_p2)) and not((ap_const_lv1_0 = tmp_1_fu_276_p2))))) then 
                min1_fu_78 <= ap_const_lv8_30;
            end if; 
        end if;
    end process;

    min_fu_74_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and not((ap_const_lv1_0 = tmp_s_fu_260_p2)) and not((ap_const_lv1_0 = tmp_1_fu_276_p2)))) then 
                                min_fu_74(5 downto 0) <= p_cast_fu_310_p1(5 downto 0);
            elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = exitcond_fu_181_p2)))) then 
                min_fu_74(0) <= '0';
                min_fu_74(1) <= '0';
                min_fu_74(2) <= '0';
                min_fu_74(3) <= '0';
                min_fu_74(4) <= '1';
                min_fu_74(5) <= '1';
            end if; 
        end if;
    end process;

    msec_fu_70_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and (ap_const_lv1_0 = tmp_7_fu_228_p2))) then 
                msec_fu_70 <= msec_1_fu_223_p2;
            elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = exitcond_fu_181_p2))) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and (ap_const_lv1_0 = tmp_9_fu_244_p2)) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and (ap_const_lv1_0 = tmp_s_fu_260_p2)) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and not((ap_const_lv1_0 = tmp_s_fu_260_p2)) and (ap_const_lv1_0 = tmp_1_fu_276_p2)) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and not((ap_const_lv1_0 = tmp_s_fu_260_p2)) and not((ap_const_lv1_0 = tmp_1_fu_276_p2))))) then 
                msec_fu_70 <= ap_const_lv8_30;
            end if; 
        end if;
    end process;

    pos_reg_120_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)))) then 
                pos_reg_120 <= pos_1_reg_322;
            elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then 
                pos_reg_120 <= ap_const_lv6_0;
            end if; 
        end if;
    end process;

    sec10_1_fu_82_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and (ap_const_lv1_0 = tmp_s_fu_260_p2))) then 
                sec10_1_fu_82 <= sec10_fu_255_p2;
            elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = exitcond_fu_181_p2))) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and not((ap_const_lv1_0 = tmp_s_fu_260_p2))))) then 
                sec10_1_fu_82 <= ap_const_lv8_30;
            end if; 
        end if;
    end process;

    sec1_fu_86_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and (ap_const_lv1_0 = tmp_9_fu_244_p2))) then 
                sec1_fu_86 <= sec1_1_fu_239_p2;
            elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = exitcond_fu_181_p2))) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and (ap_const_lv1_0 = tmp_s_fu_260_p2)) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and not((ap_const_lv1_0 = tmp_s_fu_260_p2)) and (ap_const_lv1_0 = tmp_1_fu_276_p2)) or (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and not((ap_const_lv1_0 = tmp_7_fu_228_p2)) and not((ap_const_lv1_0 = tmp_9_fu_244_p2)) and not((ap_const_lv1_0 = tmp_s_fu_260_p2)) and not((ap_const_lv1_0 = tmp_1_fu_276_p2))))) then 
                sec1_fu_86 <= ap_const_lv8_30;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = ap_const_logic_1) and (ap_const_logic_0 = dummy_tmr_out_0_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = ap_const_logic_1) and (ap_const_logic_1 = dummy_tmr_out_0_vld_reg) and (ap_const_logic_1 = dummy_tmr_out_0_ack_out)))) then
                dummy_tmr_out_0_data_reg <= dummy_tmr_out_i;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = dummy_tmr_out_1_vld_in) and (ap_const_logic_0 = dummy_tmr_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = dummy_tmr_out_1_vld_in) and (ap_const_logic_1 = dummy_tmr_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
                dummy_tmr_out_1_data_reg <= grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = mem_addr_1_vld_in) and (ap_const_logic_0 = mem_addr_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = mem_addr_1_vld_in) and (ap_const_logic_1 = mem_addr_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
                mem_addr_1_data_reg <= grp_clock_top_write_mem_fu_137_mem_addr;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = mem_dout_1_vld_in) and (ap_const_logic_0 = mem_dout_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = mem_dout_1_vld_in) and (ap_const_logic_1 = mem_dout_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
                mem_dout_1_data_reg <= grp_clock_top_write_mem_fu_137_mem_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = mem_wreq_1_vld_in) and (ap_const_logic_0 = mem_wreq_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) and (ap_const_logic_1 = mem_wreq_1_vld_in) and (ap_const_logic_1 = mem_wreq_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
                mem_wreq_1_data_reg <= grp_clock_top_write_mem_fu_137_mem_wreq;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
                min1_load_reg_373 <= min1_fu_78;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
                    min_load_reg_367(5 downto 0) <= min_fu_74(5 downto 0);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
                pos_1_reg_322 <= pos_1_fu_187_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = exitcond_fu_181_p2))) then
                    pos_cast1_cast_reg_327(5 downto 0) <= pos_cast1_cast_fu_193_p1(5 downto 0);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
                sec10_1_load_reg_379 <= sec10_1_fu_82;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
                sec1_load_reg_385 <= sec1_fu_86;
            end if;
        end if;
    end process;
    pos_cast1_cast_reg_327(6) <= '0';
    min_load_reg_367(7 downto 6) <= "00";
    min_fu_74(7 downto 6) <= "00";

    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond_fu_181_p2, grp_clock_top_wait_tmr_fu_131_ap_done, grp_clock_top_write_mem_fu_137_ap_done)
    begin
        case ap_CS_fsm is
            when ap_ST_st1_fsm_0 => 
                if (not((ap_start = ap_const_logic_0))) then
                    ap_NS_fsm <= ap_ST_st2_fsm_1;
                else
                    ap_NS_fsm <= ap_ST_st1_fsm_0;
                end if;
            when ap_ST_st2_fsm_1 => 
                ap_NS_fsm <= ap_ST_st3_fsm_2;
            when ap_ST_st3_fsm_2 => 
                if (not((ap_const_lv1_0 = exitcond_fu_181_p2))) then
                    ap_NS_fsm <= ap_ST_st5_fsm_4;
                else
                    ap_NS_fsm <= ap_ST_st4_fsm_3;
                end if;
            when ap_ST_st4_fsm_3 => 
                if (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done))) then
                    ap_NS_fsm <= ap_ST_st3_fsm_2;
                else
                    ap_NS_fsm <= ap_ST_st4_fsm_3;
                end if;
            when ap_ST_st5_fsm_4 => 
                ap_NS_fsm <= ap_ST_st6_fsm_5;
            when ap_ST_st6_fsm_5 => 
                if (not(((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done) or (ap_const_logic_0 = grp_clock_top_wait_tmr_fu_131_ap_done)))) then
                    ap_NS_fsm <= ap_ST_st7_fsm_6;
                else
                    ap_NS_fsm <= ap_ST_st6_fsm_5;
                end if;
            when ap_ST_st7_fsm_6 => 
                ap_NS_fsm <= ap_ST_st8_fsm_7;
            when ap_ST_st8_fsm_7 => 
                if (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done))) then
                    ap_NS_fsm <= ap_ST_st9_fsm_8;
                else
                    ap_NS_fsm <= ap_ST_st8_fsm_7;
                end if;
            when ap_ST_st9_fsm_8 => 
                ap_NS_fsm <= ap_ST_st10_fsm_9;
            when ap_ST_st10_fsm_9 => 
                if (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done))) then
                    ap_NS_fsm <= ap_ST_st11_fsm_10;
                else
                    ap_NS_fsm <= ap_ST_st10_fsm_9;
                end if;
            when ap_ST_st11_fsm_10 => 
                ap_NS_fsm <= ap_ST_st12_fsm_11;
            when ap_ST_st12_fsm_11 => 
                if (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done))) then
                    ap_NS_fsm <= ap_ST_st13_fsm_12;
                else
                    ap_NS_fsm <= ap_ST_st12_fsm_11;
                end if;
            when ap_ST_st13_fsm_12 => 
                ap_NS_fsm <= ap_ST_st14_fsm_13;
            when ap_ST_st14_fsm_13 => 
                if (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done))) then
                    ap_NS_fsm <= ap_ST_st15_fsm_14;
                else
                    ap_NS_fsm <= ap_ST_st14_fsm_13;
                end if;
            when ap_ST_st15_fsm_14 => 
                ap_NS_fsm <= ap_ST_st16_fsm_15;
            when ap_ST_st16_fsm_15 => 
                if (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done))) then
                    ap_NS_fsm <= ap_ST_st17_fsm_16;
                else
                    ap_NS_fsm <= ap_ST_st16_fsm_15;
                end if;
            when ap_ST_st17_fsm_16 => 
                ap_NS_fsm <= ap_ST_st18_fsm_17;
            when ap_ST_st18_fsm_17 => 
                if (not((ap_const_logic_0 = grp_clock_top_write_mem_fu_137_ap_done))) then
                    ap_NS_fsm <= ap_ST_st5_fsm_4;
                else
                    ap_NS_fsm <= ap_ST_st18_fsm_17;
                end if;
            when others =>  
                ap_NS_fsm <= "XXXXXXXXXXXXXXXXXX";
        end case;
    end process;
    ap_done <= ap_const_logic_0;

    ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
    begin
        if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;

    ap_ready <= ap_const_logic_0;

    ap_sig_251_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_251 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
    end process;


    ap_sig_265_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_265 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
    end process;


    ap_sig_274_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_274 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
    end process;


    ap_sig_283_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_283 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
    end process;


    ap_sig_292_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_292 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
    end process;


    ap_sig_301_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_301 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
    end process;


    ap_sig_33_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_33 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
    end process;


    ap_sig_335_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_335 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
    end process;


    ap_sig_342_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_342 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
    end process;


    ap_sig_354_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_354 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
    end process;


    ap_sig_367_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_367 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
    end process;


    ap_sig_377_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_377 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
    end process;


    ap_sig_388_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_388 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
    end process;


    ap_sig_396_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_396 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
    end process;


    ap_sig_404_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_404 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
    end process;


    ap_sig_412_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_412 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
    end process;


    ap_sig_420_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_420 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
    end process;


    ap_sig_428_assign_proc : process(ap_CS_fsm)
    begin
                ap_sig_428 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
    end process;


    ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_396)
    begin
        if (ap_sig_396) then 
            ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_283)
    begin
        if (ap_sig_283) then 
            ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_404)
    begin
        if (ap_sig_404) then 
            ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_292)
    begin
        if (ap_sig_292) then 
            ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_412)
    begin
        if (ap_sig_412) then 
            ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_377)
    begin
        if (ap_sig_377) then 
            ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_420)
    begin
        if (ap_sig_420) then 
            ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_301)
    begin
        if (ap_sig_301) then 
            ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_428)
    begin
        if (ap_sig_428) then 
            ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_33)
    begin
        if (ap_sig_33) then 
            ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_335)
    begin
        if (ap_sig_335) then 
            ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_251)
    begin
        if (ap_sig_251) then 
            ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_342)
    begin
        if (ap_sig_342) then 
            ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_265)
    begin
        if (ap_sig_265) then 
            ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_354)
    begin
        if (ap_sig_354) then 
            ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_274)
    begin
        if (ap_sig_274) then 
            ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_388)
    begin
        if (ap_sig_388) then 
            ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_367)
    begin
        if (ap_sig_367) then 
            ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
        else 
            ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
        end if; 
    end process;

    dummy_tmr_out_0_ack_out <= ap_const_logic_0;

    dummy_tmr_out_1_vld_in_assign_proc : process(grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o_ap_vld, ap_sig_cseq_ST_st6_fsm_5)
    begin
        if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then 
            dummy_tmr_out_1_vld_in <= grp_clock_top_wait_tmr_fu_131_dummy_tmr_out_o_ap_vld;
        else 
            dummy_tmr_out_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    dummy_tmr_out_o <= dummy_tmr_out_1_data_reg;
    exitcond_fu_181_p2 <= "1" when (pos_reg_120 = ap_const_lv6_20) else "0";
    grp_clock_top_wait_tmr_fu_131_ap_start <= ap_reg_grp_clock_top_wait_tmr_fu_131_ap_start;

    grp_clock_top_write_mem_fu_137_addr_assign_proc : process(pos_cast1_cast_reg_327, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st18_fsm_17)
    begin
        if ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then 
            grp_clock_top_write_mem_fu_137_addr <= ap_const_lv7_16;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then 
            grp_clock_top_write_mem_fu_137_addr <= ap_const_lv7_15;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then 
            grp_clock_top_write_mem_fu_137_addr <= ap_const_lv7_14;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then 
            grp_clock_top_write_mem_fu_137_addr <= ap_const_lv7_13;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then 
            grp_clock_top_write_mem_fu_137_addr <= ap_const_lv7_12;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then 
            grp_clock_top_write_mem_fu_137_addr <= ap_const_lv7_11;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then 
            grp_clock_top_write_mem_fu_137_addr <= ap_const_lv7_10;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then 
            grp_clock_top_write_mem_fu_137_addr <= pos_cast1_cast_reg_327;
        else 
            grp_clock_top_write_mem_fu_137_addr <= "XXXXXXX";
        end if; 
    end process;

    grp_clock_top_write_mem_fu_137_ap_start <= ap_reg_grp_clock_top_write_mem_fu_137_ap_start;

    grp_clock_top_write_mem_fu_137_data_assign_proc : process(min_load_reg_367, min1_load_reg_373, sec10_1_load_reg_379, sec1_load_reg_385, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st18_fsm_17, msec_fu_70)
    begin
        if ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then 
            grp_clock_top_write_mem_fu_137_data <= msec_fu_70;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then 
            grp_clock_top_write_mem_fu_137_data <= ap_const_lv8_2E;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then 
            grp_clock_top_write_mem_fu_137_data <= sec1_load_reg_385;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then 
            grp_clock_top_write_mem_fu_137_data <= sec10_1_load_reg_379;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then 
            grp_clock_top_write_mem_fu_137_data <= ap_const_lv8_3A;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then 
            grp_clock_top_write_mem_fu_137_data <= min1_load_reg_373;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then 
            grp_clock_top_write_mem_fu_137_data <= min_load_reg_367;
        elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then 
            grp_clock_top_write_mem_fu_137_data <= ap_const_lv8_20;
        else 
            grp_clock_top_write_mem_fu_137_data <= "XXXXXXXX";
        end if; 
    end process;


    mem_addr_1_vld_in_assign_proc : process(grp_clock_top_write_mem_fu_137_mem_addr_ap_vld, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st18_fsm_17)
    begin
        if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then 
            mem_addr_1_vld_in <= grp_clock_top_write_mem_fu_137_mem_addr_ap_vld;
        else 
            mem_addr_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    mem_addr_o <= mem_addr_1_data_reg;

    mem_dout_1_vld_in_assign_proc : process(grp_clock_top_write_mem_fu_137_mem_dout_ap_vld, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st18_fsm_17)
    begin
        if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then 
            mem_dout_1_vld_in <= grp_clock_top_write_mem_fu_137_mem_dout_ap_vld;
        else 
            mem_dout_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    mem_dout_o <= mem_dout_1_data_reg;

    mem_wreq_1_vld_in_assign_proc : process(grp_clock_top_write_mem_fu_137_mem_wreq_ap_vld, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st18_fsm_17)
    begin
        if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then 
            mem_wreq_1_vld_in <= grp_clock_top_write_mem_fu_137_mem_wreq_ap_vld;
        else 
            mem_wreq_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    mem_wreq_o <= mem_wreq_1_data_reg;
    min10_fu_287_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(min_load_reg_367));
    min1_1_fu_271_p2 <= std_logic_vector(unsigned(min1_load_reg_373) + unsigned(ap_const_lv8_1));
    msec_1_fu_223_p2 <= std_logic_vector(unsigned(msec_fu_70) + unsigned(ap_const_lv8_1));
    p_cast_fu_310_p1 <= std_logic_vector(resize(unsigned(p_s_fu_302_p3),8));
    p_s_fu_302_p3 <= 
        ap_const_lv6_30 when (tmp_2_fu_296_p2(0) = '1') else 
        tmp_fu_292_p1;
    pos_1_fu_187_p2 <= std_logic_vector(unsigned(pos_reg_120) + unsigned(ap_const_lv6_1));
    pos_cast1_cast_fu_193_p1 <= std_logic_vector(resize(unsigned(pos_reg_120),7));
    sec10_fu_255_p2 <= std_logic_vector(unsigned(sec10_1_load_reg_379) + unsigned(ap_const_lv8_1));
    sec1_1_fu_239_p2 <= std_logic_vector(unsigned(sec1_load_reg_385) + unsigned(ap_const_lv8_1));
    tmp_1_fu_276_p2 <= "1" when (unsigned(min1_1_fu_271_p2) > unsigned(ap_const_lv8_39)) else "0";
    tmp_2_fu_296_p2 <= "1" when (unsigned(min10_fu_287_p2) > unsigned(ap_const_lv8_35)) else "0";
    tmp_7_fu_228_p2 <= "1" when (unsigned(msec_1_fu_223_p2) > unsigned(ap_const_lv8_39)) else "0";
    tmp_9_fu_244_p2 <= "1" when (unsigned(sec1_1_fu_239_p2) > unsigned(ap_const_lv8_39)) else "0";
    tmp_fu_292_p1 <= min10_fu_287_p2(6 - 1 downto 0);
    tmp_s_fu_260_p2 <= "1" when (unsigned(sec10_fu_255_p2) > unsigned(ap_const_lv8_35)) else "0";
end behav;
