// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module lcddrv_lcd_send_cmd (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        mode,
        wd,
        en,
        en_ap_vld,
        dummy_tmr_out_i,
        dummy_tmr_out_o,
        dummy_tmr_out_o_ap_vld,
        rs,
        rs_ap_vld,
        data,
        data_ap_vld
);

parameter    ap_ST_st1_fsm_0 = 9'b1;
parameter    ap_ST_st2_fsm_1 = 9'b10;
parameter    ap_ST_st3_fsm_2 = 9'b100;
parameter    ap_ST_st4_fsm_3 = 9'b1000;
parameter    ap_ST_st5_fsm_4 = 9'b10000;
parameter    ap_ST_st6_fsm_5 = 9'b100000;
parameter    ap_ST_st7_fsm_6 = 9'b1000000;
parameter    ap_ST_st8_fsm_7 = 9'b10000000;
parameter    ap_ST_st9_fsm_8 = 9'b100000000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv32_5 = 32'b101;
parameter    ap_const_lv32_7 = 32'b111;
parameter    ap_const_lv25_3E8 = 25'b1111101000;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv32_4 = 32'b100;
parameter    ap_const_lv32_6 = 32'b110;
parameter    ap_const_lv32_8 = 32'b1000;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [0:0] mode;
input  [3:0] wd;
output  [0:0] en;
output   en_ap_vld;
input  [0:0] dummy_tmr_out_i;
output  [0:0] dummy_tmr_out_o;
output   dummy_tmr_out_o_ap_vld;
output  [0:0] rs;
output   rs_ap_vld;
output  [3:0] data;
output   data_ap_vld;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg[0:0] en;
reg en_ap_vld;
reg[0:0] dummy_tmr_out_o;
reg rs_ap_vld;
reg data_ap_vld;

(* fsm_encoding = "none" *) reg   [8:0] ap_CS_fsm;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_26;
wire    grp_lcddrv_wait_tmr_fu_67_ap_start;
wire    grp_lcddrv_wait_tmr_fu_67_ap_done;
wire    grp_lcddrv_wait_tmr_fu_67_ap_idle;
wire    grp_lcddrv_wait_tmr_fu_67_ap_ready;
wire   [0:0] grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o;
wire    grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld;
reg    ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_66;
reg    ap_sig_cseq_ST_st4_fsm_3;
reg    ap_sig_73;
reg    ap_sig_cseq_ST_st6_fsm_5;
reg    ap_sig_81;
reg    ap_sig_cseq_ST_st8_fsm_7;
reg    ap_sig_89;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_98;
reg    ap_sig_cseq_ST_st5_fsm_4;
reg    ap_sig_105;
reg    ap_sig_cseq_ST_st7_fsm_6;
reg    ap_sig_113;
reg    ap_sig_cseq_ST_st9_fsm_8;
reg    ap_sig_121;
reg   [8:0] ap_NS_fsm;

// power-on initialization
initial begin
#0 ap_CS_fsm = 9'b1;
#0 ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start = 1'b0;
end

lcddrv_wait_tmr grp_lcddrv_wait_tmr_fu_67(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(grp_lcddrv_wait_tmr_fu_67_ap_start),
    .ap_done(grp_lcddrv_wait_tmr_fu_67_ap_done),
    .ap_idle(grp_lcddrv_wait_tmr_fu_67_ap_idle),
    .ap_ready(grp_lcddrv_wait_tmr_fu_67_ap_ready),
    .tmr(ap_const_lv25_3E8),
    .dummy_tmr_out_i(dummy_tmr_out_i),
    .dummy_tmr_out_o(grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o),
    .dummy_tmr_out_o_ap_vld(grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start <= 1'b0;
    end else begin
        if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7))) begin
            ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start <= 1'b1;
        end else if ((1'b1 == grp_lcddrv_wait_tmr_fu_67_ap_ready)) begin
            ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start <= 1'b0;
        end
    end
end

always @ (*) begin
    if ((((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0)) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(1'b0 == grp_lcddrv_wait_tmr_fu_67_ap_done)))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(1'b0 == grp_lcddrv_wait_tmr_fu_67_ap_done))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_26) begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_66) begin
        ap_sig_cseq_ST_st2_fsm_1 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_98) begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_73) begin
        ap_sig_cseq_ST_st4_fsm_3 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st4_fsm_3 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_105) begin
        ap_sig_cseq_ST_st5_fsm_4 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st5_fsm_4 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_81) begin
        ap_sig_cseq_ST_st6_fsm_5 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st6_fsm_5 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_113) begin
        ap_sig_cseq_ST_st7_fsm_6 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st7_fsm_6 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_89) begin
        ap_sig_cseq_ST_st8_fsm_7 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st8_fsm_7 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_121) begin
        ap_sig_cseq_ST_st9_fsm_8 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st9_fsm_8 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7))) begin
        data_ap_vld = 1'b1;
    end else begin
        data_ap_vld = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (1'b1 == grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st5_fsm_4) & (1'b1 == grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st7_fsm_6) & (1'b1 == grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & (1'b1 == grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld)))) begin
        dummy_tmr_out_o = grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o;
    end else begin
        dummy_tmr_out_o = dummy_tmr_out_i;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st6_fsm_5)) begin
        en = 1'b1;
    end else if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7))) begin
        en = 1'b0;
    end else begin
        en = 'bx;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7))) begin
        en_ap_vld = 1'b1;
    end else begin
        en_ap_vld = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7))) begin
        rs_ap_vld = 1'b1;
    end else begin
        rs_ap_vld = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : begin
            if (~(ap_start == 1'b0)) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : begin
            ap_NS_fsm = ap_ST_st3_fsm_2;
        end
        ap_ST_st3_fsm_2 : begin
            if (~(1'b0 == grp_lcddrv_wait_tmr_fu_67_ap_done)) begin
                ap_NS_fsm = ap_ST_st4_fsm_3;
            end else begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end
        end
        ap_ST_st4_fsm_3 : begin
            ap_NS_fsm = ap_ST_st5_fsm_4;
        end
        ap_ST_st5_fsm_4 : begin
            if (~(1'b0 == grp_lcddrv_wait_tmr_fu_67_ap_done)) begin
                ap_NS_fsm = ap_ST_st6_fsm_5;
            end else begin
                ap_NS_fsm = ap_ST_st5_fsm_4;
            end
        end
        ap_ST_st6_fsm_5 : begin
            ap_NS_fsm = ap_ST_st7_fsm_6;
        end
        ap_ST_st7_fsm_6 : begin
            if (~(1'b0 == grp_lcddrv_wait_tmr_fu_67_ap_done)) begin
                ap_NS_fsm = ap_ST_st8_fsm_7;
            end else begin
                ap_NS_fsm = ap_ST_st7_fsm_6;
            end
        end
        ap_ST_st8_fsm_7 : begin
            ap_NS_fsm = ap_ST_st9_fsm_8;
        end
        ap_ST_st9_fsm_8 : begin
            if (~(1'b0 == grp_lcddrv_wait_tmr_fu_67_ap_done)) begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end else begin
                ap_NS_fsm = ap_ST_st9_fsm_8;
            end
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

always @ (*) begin
    ap_sig_105 = (1'b1 == ap_CS_fsm[ap_const_lv32_4]);
end

always @ (*) begin
    ap_sig_113 = (1'b1 == ap_CS_fsm[ap_const_lv32_6]);
end

always @ (*) begin
    ap_sig_121 = (1'b1 == ap_CS_fsm[ap_const_lv32_8]);
end

always @ (*) begin
    ap_sig_26 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end

always @ (*) begin
    ap_sig_66 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]);
end

always @ (*) begin
    ap_sig_73 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]);
end

always @ (*) begin
    ap_sig_81 = (1'b1 == ap_CS_fsm[ap_const_lv32_5]);
end

always @ (*) begin
    ap_sig_89 = (1'b1 == ap_CS_fsm[ap_const_lv32_7]);
end

always @ (*) begin
    ap_sig_98 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]);
end

assign data = wd;

assign dummy_tmr_out_o_ap_vld = grp_lcddrv_wait_tmr_fu_67_dummy_tmr_out_o_ap_vld;

assign grp_lcddrv_wait_tmr_fu_67_ap_start = ap_reg_grp_lcddrv_wait_tmr_fu_67_ap_start;

assign rs = mode;

endmodule //lcddrv_lcd_send_cmd
