//  Copyright (C) 2016, mituhiromatuura all right reserved.

typedef volatile unsigned int	v32_t;
typedef volatile unsigned short	v16_t;
typedef volatile unsigned char	v8_t;

#define FM4_PERIPH_BASE		(0x40000000UL)
#define FM4_HWWDT_WDG_BASE	(FM4_PERIPH_BASE + 0x11000UL)
#define FM4_BT_BASE			(FM4_PERIPH_BASE + 0x25000UL)
#define FM4_ADC_BASE		(FM4_PERIPH_BASE + 0x27000UL)
#define FM4_EXTI_BASE		(FM4_PERIPH_BASE + 0x30000UL)
#define FM4_INTREQ_BASE		(FM4_PERIPH_BASE + 0x31000UL)
#define FM4_MFS_BASE		(FM4_PERIPH_BASE + 0x38000UL)
#define FM4_GPIO_BASE		(FM4_PERIPH_BASE + 0x6F000UL)
#define FM4_RTC_BASE		(FM4_PERIPH_BASE + 0x3B100UL)
#define FM4_EXBUS_BASE		(FM4_PERIPH_BASE + 0x3F000UL)
#define FM4_DMAC_BASE		(FM4_PERIPH_BASE + 0x60000UL)

#define PERIPH_BASE			FM4_PERIPH_BASE
#define BITBAND(a, b)		((v32_t*)(0x42000000UL + (a - PERIPH_BASE) * 32 + b * 4))

#define HWWDT_WDG_BASE			(FM4_HWWDT_WDG_BASE)
#define HWWDT_WDG_LDR			(HWWDT_WDG_BASE + 0x000)
#define HWWDT_WDG_VLR			(HWWDT_WDG_BASE + 0x004)
#define HWWDT_WDG_CTL			(HWWDT_WDG_BASE + 0x008)
#define HWWDT_WDG_ICL			(HWWDT_WDG_BASE + 0x00c)
#define HWWDT_WDG_RIS			(HWWDT_WDG_BASE + 0x010)
#define HWWDT_WDG_LCK			(HWWDT_WDG_BASE + 0xc00)

#define BT_BASE				(FM4_BT_BASE)
#define BT_RT_PCSR			(BT_BASE + 0x000)
#define BT_RT_TMR			(BT_BASE + 0x008)
#define BT_RT_TMCR			(BT_BASE + 0x00c)
#define BT_RT_TMCR_BIT_FMD		4
#define BT_RT_TMCR_BIT_CTEN		1
#define BT_RT_TMCR_BIT_STRG		0
#define BT_RT_STC			(BT_BASE + 0x010)
#define BT_RT_STC_BIT_UDIE		4
#define BT_RT_STC_BIT_UDIR		0
#define BT_RT_TMCR2			(BT_BASE + 0x011)

#define BT_PWM_PCSR			(BT_BASE + 0x000)
#define BT_PWM_PDUT			(BT_BASE + 0x004)
#define BT_PWM_TMR			(BT_BASE + 0x008)
#define BT_PWM_TMCR			(BT_BASE + 0x00c)
#define BT_PWM_TMCR_BIT_FMD		4
#define BT_PWM_TMCR_BIT_CTEN	1
#define BT_PWM_TMCR_BIT_STRG	0
#define BT_PWM_STC			(BT_BASE + 0x010)
#define BT_PWM_TMCR2		(BT_BASE + 0x011)

#define ADC_BASE			(FM4_ADC_BASE)
#define ADC_ADSR(ch)		(ADC_BASE + (ch) * 0x100 + 0x000)
#define ADC_ADCR(ch)		(ADC_BASE + (ch) * 0x100 + 0x001)
#define ADC_SFNS(ch)		(ADC_BASE + (ch) * 0x100 + 0x008)
#define ADC_SCCR(ch)		(ADC_BASE + (ch) * 0x100 + 0x009)
#define ADC_SCFD(ch)		(ADC_BASE + (ch) * 0x100 + 0x00c)
#define ADC_SCIS23(ch)		(ADC_BASE + (ch) * 0x100 + 0x010)
#define ADC_SCIS01(ch)		(ADC_BASE + (ch) * 0x100 + 0x014)
#define ADC_ADSS23(ch)		(ADC_BASE + (ch) * 0x100 + 0x028)
#define ADC_ADSS01(ch)		(ADC_BASE + (ch) * 0x100 + 0x02c)
#define ADC_ADST1(ch)		(ADC_BASE + (ch) * 0x100 + 0x030)
#define ADC_ADST0(ch)		(ADC_BASE + (ch) * 0x100 + 0x031)
#define ADC_ADCEN(ch)		(ADC_BASE + (ch) * 0x100 + 0x03c)

#define EXTI_BASE			(FM4_EXTI_BASE)
#define EXTI_ENIR			(EXTI_BASE + 0x000)
#define EXTI_EIRR			(EXTI_BASE + 0x004)
#define EXTI_EICL			(EXTI_BASE + 0x008)
#define EXTI_ELVR			(EXTI_BASE + 0x00c)
#define EXTI_ELVR_BIT_LLEVEL	0
#define EXTI_ELVR_BIT_HLEVEL	1
#define EXTI_ELVR_BIT_UPEDGE	2
#define EXTI_ELVR_BIT_DNEDGE	3
#define EXTI_ELVR1			(EXTI_BASE + 0x010)
#define EXTI_NMIRR			(EXTI_BASE + 0x014)
#define EXTI_NMICL			(EXTI_BASE + 0x018)

#define INTREQ				(FM4_INTREQ_BASE)
#define INTREQ_DRQSEL		(INTREQ + 0x0000)
#define INTREQ_IRQ_MON(ch)	(INTREQ + ((8 > ch) ? (0x230 + ch * 4) : (0x2d0 + (ch - 8) * 4)))

#define MFS_BASE			(FM4_MFS_BASE)
#define MFS_SMR(ch)			(MFS_BASE + (ch) * 0x100 + 0x000)
#define MFS_SMR_BIT_MD_I2C	(4<<5)
#define MFS_SCR(ch)			(MFS_BASE + (ch) * 0x100 + 0x001)
#define MFS_IBCR(ch)		(MFS_BASE + (ch) * 0x100 + 0x001)
#define MFS_IBCR_BIT_MSS	(1<<7)
#define MFS_IBCR_BIT_SCC	(1<<6)
#define MFS_IBCR_BIT_INT	(1<<0)
#define MFS_ESCR(ch)		(MFS_BASE + (ch) * 0x100 + 0x004)
#define MFS_IBSR(ch)		(MFS_BASE + (ch) * 0x100 + 0x004)
#define MFS_SSR(ch)			(MFS_BASE + (ch) * 0x100 + 0x005)
#define MFS_SSR_BIT_TDRE	(1<<1)
#define MFS_TDR(ch)			(MFS_BASE + (ch) * 0x100 + 0x008)
#define MFS_RDT(ch)			(MFS_BASE + (ch) * 0x100 + 0x008)
#define MFS_BGR0(ch)		(MFS_BASE + (ch) * 0x100 + 0x00c)
#define MFS_BGR1(ch)		(MFS_BASE + (ch) * 0x100 + 0x00d)
#define MFS_ISBA(ch)		(MFS_BASE + (ch) * 0x100 + 0x010)
#define MFS_ISMK(ch)		(MFS_BASE + (ch) * 0x100 + 0x011)
#define MFS_ISMK_BIT_EN		(1<<7)
#define MFS_FCR0(ch)		(MFS_BASE + (ch) * 0x100 + 0x014)
#define MFS_FCR1(ch)		(MFS_BASE + (ch) * 0x100 + 0x015)
#define MFS_FBYTE1(ch)		(MFS_BASE + (ch) * 0x100 + 0x018)
#define MFS_FBYTE2(ch)		(MFS_BASE + (ch) * 0x100 + 0x019)
#define MFS_SCSTR0(ch)		(MFS_BASE + (ch) * 0x100 + 0x01c)
#define MFS_NFCR(ch)		(MFS_BASE + (ch) * 0x100 + 0x01c)
#define MFS_SCSTR1(ch)		(MFS_BASE + (ch) * 0x100 + 0x01d)
#define MFS_EIBCR(ch)		(MFS_BASE + (ch) * 0x100 + 0x01d)
#define MFS_SCSTR2(ch)		(MFS_BASE + (ch) * 0x100 + 0x020)
#define MFS_SCSTR3(ch)		(MFS_BASE + (ch) * 0x100 + 0x021)
#define MFS_SACSR0(ch)		(MFS_BASE + (ch) * 0x100 + 0x024)
#define MFS_SACSR1(ch)		(MFS_BASE + (ch) * 0x100 + 0x025)
#define MFS_STMR0(ch)		(MFS_BASE + (ch) * 0x100 + 0x028)
#define MFS_STRMR1(ch)		(MFS_BASE + (ch) * 0x100 + 0x029)
#define MFS_STMCR0(ch)		(MFS_BASE + (ch) * 0x100 + 0x02c)
#define MFS_STMCR1(ch)		(MFS_BASE + (ch) * 0x100 + 0x02d)
#define MFS_SCSCR0(ch)		(MFS_BASE + (ch) * 0x100 + 0x030)
#define MFS_SCSCR1(ch)		(MFS_BASE + (ch) * 0x100 + 0x031)
#define MFS_SCSFR0(ch)		(MFS_BASE + (ch) * 0x100 + 0x034)
#define MFS_SCSFR1(ch)		(MFS_BASE + (ch) * 0x100 + 0x035)
#define MFS_SCSFR2(ch)		(MFS_BASE + (ch) * 0x100 + 0x038)
#define MFS_TBYTE0(ch)		(MFS_BASE + (ch) * 0x100 + 0x03c)
#define MFS_TBYTE1(ch)		(MFS_BASE + (ch) * 0x100 + 0x03d)
#define MFS_TBYTE2(ch)		(MFS_BASE + (ch) * 0x100 + 0x040)
#define MFS_TBYTE3(ch)		(MFS_BASE + (ch) * 0x100 + 0x041)

#define GPIO_BASE			(FM4_GPIO_BASE)
#define GPIO_PFR			(GPIO_BASE + 0x000)
#define GPIO_PCR			(GPIO_BASE + 0x100)
#define GPIO_DDR			(GPIO_BASE + 0x200)
#define GPIO_PDIR			(GPIO_BASE + 0x300)
#define GPIO_PDOR			(GPIO_BASE + 0x400)
#define GPIO_ADE			(GPIO_BASE + 0x500)
#define GPIO_EPFR(n)		(GPIO_BASE + 0x600 + 4 * n)
#define GPIO_PZR			(GPIO_BASE + 0x700)

#define VBAT_BASE			(FM4_RTC_BASE)
#define VBAT_VBPFR			(VBAT_BASE + 0x9c)
#define VBAT_VBPCR			(VBAT_BASE + 0xa0)
#define VBAT_VBDDR			(VBAT_BASE + 0xa4)
#define VBAT_VBDIR			(VBAT_BASE + 0xa8)
#define VBAT_VBDOR			(VBAT_BASE + 0xac)
#define VBAT_VBPZR			(VBAT_BASE + 0xb0)

#define EXBUS_BASE			(FM4_EXBUS_BASE)
#define EXBUS_MODE0			(EXBUS_BASE + 0x0000)
#define EXBUS_MODE1			(EXBUS_BASE + 0x0004)
#define EXBUS_TIM0			(EXBUS_BASE + 0x0020)
#define EXBUS_TIM1			(EXBUS_BASE + 0x0024)
#define EXBUS_AREA0			(EXBUS_BASE + 0x0040)
#define EXBUS_AREA1			(EXBUS_BASE + 0x0044)
#define EXBUS_DCLKR			(EXBUS_BASE + 0x0300)

#define DMAC_BASE			(FM4_DMAC_BASE)
#define DMAC_DMACR			(DMAC_BASE + 0x0000)
#define DMAC_DMACA			(DMAC_BASE + 0x0010)
#define DMAC_DMACB			(DMAC_BASE + 0x0014)
#define DMAC_DMACSA			(DMAC_BASE + 0x0018)
#define DMAC_DMACDA			(DMAC_BASE + 0x001c)
