### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
date_generated | Fri May 27 23:10:05 2016 | product_version | Vivado v2016.1 (64-bit)
build_version | 1538259 | os_platform | WIN64
registration_id | 210942454_1777511609_0_329 | tool_flow | Vivado
beta | FALSE | route_design | TRUE
target_family | artix7 | target_device | xc7a35ti
target_package | csg324 | target_speed | -1L
random_id | 5201a2a4f4ac57a498dbce6f7cc4b9b0 | project_id | 5ab661e04ae74361b2c0e5847fedb6e0
project_iteration | 4

user_environment
os_name | Microsoft Windows 8 or later , 64-bit | os_release | major release (build 9200)
cpu_name | Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz | cpu_speed | 2694 MHz
total_processors | 1 | system_ram | 8.000 GB

vivado_usage

project_data
srcsetcount=30 | constraintsetcount=1 | designmode=RTL | synthesisstrategy=Vivado Synthesis Defaults
implstrategy=Vivado Implementation Defaults | currentsynthesisrun=synth_1 | currentimplrun=impl_1 | totalsynthesisruns=1
totalimplruns=1 | core_container=false | simulator_language=Mixed | target_language=Verilog
default_library=xil_defaultlib | target_simulator=XSim | launch_simulation_xsim=0 | launch_simulation_modelsim=0
launch_simulation_questa=0 | launch_simulation_ies=0 | launch_simulation_vcs=0 | launch_simulation_riviera=0
launch_simulation_activehdl=0 | export_simulation_xsim=0 | export_simulation_modelsim=0 | export_simulation_questa=0
export_simulation_ies=0 | export_simulation_vcs=0 | export_simulation_riviera=0 | export_simulation_activehdl=0

other_data
guimode=4

unisim_transformation
pre_unisim_transformation
bufg=1 | carry4=237 | dsp48e1=1 | fdre=2353
fdse=45 | gnd=42 | ibuf=4 | iobuf=1
lut1=62 | lut2=499 | lut3=324 | lut4=329
lut5=298 | lut6=479 | muxf7=1 | obuf=17
ramb18e1=1 | srlc32e=2 | vcc=48
post_unisim_transformation
bufg=1 | carry4=237 | dsp48e1=1 | fdre=2353
fdse=45 | gnd=42 | ibuf=5 | lut1=62
lut2=499 | lut3=324 | lut4=329 | lut5=298
lut6=479 | muxf7=1 | obuf=17 | obuft=1
ramb18e1=1 | srlc32e=2 | vcc=48

power_opt_design
usage
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=2398 | srls_augmented=0
srls_newly_gated=0 | srls_total=2 | bram_ports_augmented=0 | bram_ports_newly_gated=0
bram_ports_total=2 | flow_state=default
command_line_options_spo
-clocks=default::[not_specified] | -include_cells=default::[not_specified] | -exclude_cells=default::[not_specified] | -cell_types=default::all

ip_statistics
hls_ip_2016_1/1
iptotal=1 | core_container=NA | hls_input_type=c | hls_input_float=0
hls_input_fixed=0 | hls_input_part=xc7a35ticsg324-1l | hls_input_clock=10.000000 | hls_input_arch=others
hls_syn_clock=7.180000 | hls_syn_lat=-1 | hls_syn_tpt=none | hls_syn_mem=0
hls_syn_dsp=1 | hls_syn_ff=968 | hls_syn_lut=1501
hls_ip_2016_1/2
iptotal=1 | core_container=NA | hls_input_type=c | hls_input_float=0
hls_input_fixed=0 | hls_input_part=xc7a35ticsg324-1l | hls_input_clock=10.000000 | hls_input_arch=others
hls_syn_clock=3.040000 | hls_syn_lat=-1 | hls_syn_tpt=none | hls_syn_mem=0
hls_syn_dsp=0 | hls_syn_ff=318 | hls_syn_lut=358
hls_ip_2016_1/3
iptotal=1 | core_container=NA | hls_input_type=c | hls_input_float=0
hls_input_fixed=0 | hls_input_part=xc7a35ticsg324-1l | hls_input_clock=10.000000 | hls_input_arch=others
hls_syn_clock=2.862312 | hls_syn_lat=-1 | hls_syn_tpt=none | hls_syn_mem=0
hls_syn_dsp=0 | hls_syn_ff=263 | hls_syn_lut=435
hls_ip_2016_1/4
iptotal=1 | core_container=NA | hls_input_type=c | hls_input_float=0
hls_input_fixed=0 | hls_input_part=xc7a35ticsg324-1l | hls_input_clock=10.000000 | hls_input_arch=others
hls_syn_clock=8.293813 | hls_syn_lat=-1 | hls_syn_tpt=none | hls_syn_mem=0
hls_syn_dsp=1 | hls_syn_ff=946 | hls_syn_lut=1289
hls_ip_2016_1/5
iptotal=1 | core_container=NA | hls_input_type=c | hls_input_float=0
hls_input_fixed=0 | hls_input_part=xc7a35ticsg324-1l | hls_input_clock=10.000000 | hls_input_arch=others
hls_syn_clock=4.446125 | hls_syn_lat=-1 | hls_syn_tpt=none | hls_syn_mem=1
hls_syn_dsp=0 | hls_syn_ff=162 | hls_syn_lut=135

report_drc
command_line_options
-checks=default::[not_specified] | -ruledecks=default::[not_specified] | -name=default::[not_specified] | -format=default::[not_specified]
-fail_on=default::[not_specified] | -return_string=default::[not_specified] | -messages=default::[not_specified] | -force=default::[not_specified]
-append=default::[not_specified] | -checks=default::[not_specified] | -ruledecks=default::[not_specified] | -name=default::[not_specified]
-format=default::[not_specified] | -fail_on=default::[not_specified] | -return_string=default::[not_specified] | -messages=default::[not_specified]
-force=default::[not_specified] | -append=default::[not_specified]
results
cfgbvs-1=1 | dpop-2=1 | cfgbvs-1=1 | dpop-2=1

report_power
command_line_options
-verbose=default::[not_specified] | -hier=default::power | -no_propagation=default::[not_specified] | -format=default::text
-file=[specified] | -rpx=[specified] | -name=default::[not_specified] | -xpe=default::[not_specified]
-return_string=default::[not_specified] | -vid=default::[not_specified] | -advisory=default::[not_specified] | -append=default::[not_specified]
-l=default::[not_specified]
usage
customer=TBD | customer_class=TBD | flow_state=routed | family=artix7
die=xc7a35ticsg324-1L | package=csg324 | speedgrade=-1L | version=2016.1
platform=nt64 | temp_grade=industrial | process=typical | simulation_file=None
netlist_net_matched=NA | pct_clock_constrained=6.000000 | pct_inputs_defined=20 | user_junc_temp=25.4 (C)
ambient_temp=25.0 (C) | user_effective_thetaja=4.8 | airflow=250 (LFM) | heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) | board_selection=medium (10"x10") | board_layers=12to15 (12 to 15 Layers) | user_thetajb=6.8 (C/W)
user_board_temp=25.0 (C) | junction_temp=25.4 (C) | input_toggle=12.500000 | output_toggle=12.500000
bi-dir_toggle=12.500000 | output_enable=1.000000 | bidir_output_enable=1.000000 | output_load=5.000000
ff_toggle=12.500000 | ram_enable=50.000000 | ram_write=50.000000 | dsp_output_toggle=12.500000
set/reset_probability=0.000000 | enable_probability=0.990000 | toggle_rate=False | signal_rate=False
static_prob=False | read_saif=False | on-chip_power=0.077349 | dynamic=0.015477
effective_thetaja=4.8 | thetasa=4.6 (C/W) | thetajb=6.8 (C/W) | off-chip_power=0.000000
clocks=0.007794 | logic=0.002723 | signals=0.003156 | bram=0.001228
dsp=0.000191 | i/o=0.000384 | devstatic=0.061872 | vccint_voltage=0.950000
vccint_total_current=0.021818 | vccint_dynamic_current=0.015888 | vccint_static_current=0.005931 | vccaux_voltage=1.800000
vccaux_total_current=0.011366 | vccaux_dynamic_current=0.000012 | vccaux_static_current=0.011354 | vcco33_voltage=3.300000
vcco33_total_current=0.001089 | vcco33_dynamic_current=0.000089 | vcco33_static_current=0.001000 | vcco25_voltage=2.500000
vcco25_total_current=0.000000 | vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000 | vcco18_voltage=1.800000
vcco18_total_current=0.000000 | vcco18_dynamic_current=0.000000 | vcco18_static_current=0.000000 | vcco15_voltage=1.500000
vcco15_total_current=0.000000 | vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000 | vcco135_voltage=1.350000
vcco135_total_current=0.000000 | vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000 | vcco12_voltage=1.200000
vcco12_total_current=0.000000 | vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000 | vccaux_io_voltage=1.800000
vccaux_io_total_current=0.000000 | vccaux_io_dynamic_current=0.000000 | vccaux_io_static_current=0.000000 | vccbram_voltage=0.950000
vccbram_total_current=0.000177 | vccbram_dynamic_current=0.000071 | vccbram_static_current=0.000106 | mgtavcc_voltage=1.000000
mgtavcc_total_current=0.000000 | mgtavcc_dynamic_current=0.000000 | mgtavcc_static_current=0.000000 | mgtavtt_voltage=1.200000
mgtavtt_total_current=0.000000 | mgtavtt_dynamic_current=0.000000 | mgtavtt_static_current=0.000000 | vccadc_voltage=1.800000
vccadc_total_current=0.018000 | vccadc_dynamic_current=0.000000 | vccadc_static_current=0.018000 | confidence_level_design_state=High
confidence_level_clock_activity=High | confidence_level_io_activity=Low | confidence_level_internal_activity=Medium | confidence_level_device_models=Medium
confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=1612 | slice_luts_fixed=0 | slice_luts_available=20800 | slice_luts_util_percentage=7.75
lut_as_logic_used=1610 | lut_as_logic_fixed=0 | lut_as_logic_available=20800 | lut_as_logic_util_percentage=7.74
lut_as_memory_used=2 | lut_as_memory_fixed=0 | lut_as_memory_available=9600 | lut_as_memory_util_percentage=0.02
lut_as_distributed_ram_used=0 | lut_as_distributed_ram_fixed=0 | lut_as_shift_register_used=2 | lut_as_shift_register_fixed=0
slice_registers_used=2398 | slice_registers_fixed=0 | slice_registers_available=41600 | slice_registers_util_percentage=5.76
register_as_flip_flop_used=2398 | register_as_flip_flop_fixed=0 | register_as_flip_flop_available=41600 | register_as_flip_flop_util_percentage=5.76
register_as_latch_used=0 | register_as_latch_fixed=0 | register_as_latch_available=41600 | register_as_latch_util_percentage=0.00
f7_muxes_used=1 | f7_muxes_fixed=0 | f7_muxes_available=16300 | f7_muxes_util_percentage=<0.01
f8_muxes_used=0 | f8_muxes_fixed=0 | f8_muxes_available=8150 | f8_muxes_util_percentage=0.00
slice_used=756 | slice_fixed=0 | slice_available=8150 | slice_util_percentage=9.28
slicel_used=494 | slicel_fixed=0 | slicem_used=262 | slicem_fixed=0
lut_as_logic_used=1610 | lut_as_logic_fixed=0 | lut_as_logic_available=20800 | lut_as_logic_util_percentage=7.74
using_o5_output_only_used=6 | using_o5_output_only_fixed= | using_o6_output_only_used=1227 | using_o6_output_only_fixed=
using_o5_and_o6_used=377 | using_o5_and_o6_fixed= | lut_as_memory_used=2 | lut_as_memory_fixed=0
lut_as_memory_available=9600 | lut_as_memory_util_percentage=0.02 | lut_as_distributed_ram_used=0 | lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=2 | lut_as_shift_register_fixed=0 | using_o5_output_only_used=0 | using_o5_output_only_fixed=
using_o6_output_only_used=2 | using_o6_output_only_fixed= | using_o5_and_o6_used=0 | using_o5_and_o6_fixed=
lut_flip_flop_pairs_used=888 | lut_flip_flop_pairs_fixed=0 | lut_flip_flop_pairs_available=20800 | lut_flip_flop_pairs_util_percentage=4.27
fully_used_lut_ff_pairs_used=165 | fully_used_lut_ff_pairs_fixed= | lut_ff_pairs_with_one_unused_lut_used=659 | lut_ff_pairs_with_one_unused_lut_fixed=
lut_ff_pairs_with_one_unused_flip_flop_used=658 | lut_ff_pairs_with_one_unused_flip_flop_fixed= | unique_control_sets_used=145
memory
block_ram_tile_used=0.5 | block_ram_tile_fixed=0 | block_ram_tile_available=50 | block_ram_tile_util_percentage=1.00
ramb36_fifo_used=0 | ramb36_fifo_fixed=0 | ramb36_fifo_available=50 | ramb36_fifo_util_percentage=0.00
ramb18_used=1 | ramb18_fixed=0 | ramb18_available=100 | ramb18_util_percentage=1.00
ramb18e1_only_used=1
dsp
dsps_used=1 | dsps_fixed=0 | dsps_available=90 | dsps_util_percentage=1.11
dsp48e1_only_used=1
clocking
bufgctrl_used=1 | bufgctrl_fixed=0 | bufgctrl_available=32 | bufgctrl_util_percentage=3.13
bufio_used=0 | bufio_fixed=0 | bufio_available=20 | bufio_util_percentage=0.00
mmcme2_adv_used=0 | mmcme2_adv_fixed=0 | mmcme2_adv_available=5 | mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 | plle2_adv_fixed=0 | plle2_adv_available=5 | plle2_adv_util_percentage=0.00
bufmrce_used=0 | bufmrce_fixed=0 | bufmrce_available=10 | bufmrce_util_percentage=0.00
bufhce_used=0 | bufhce_fixed=0 | bufhce_available=72 | bufhce_util_percentage=0.00
bufr_used=0 | bufr_fixed=0 | bufr_available=20 | bufr_util_percentage=0.00
specific_feature
bscane2_used=0 | bscane2_fixed=0 | bscane2_available=4 | bscane2_util_percentage=0.00
capturee2_used=0 | capturee2_fixed=0 | capturee2_available=1 | capturee2_util_percentage=0.00
dna_port_used=0 | dna_port_fixed=0 | dna_port_available=1 | dna_port_util_percentage=0.00
efuse_usr_used=0 | efuse_usr_fixed=0 | efuse_usr_available=1 | efuse_usr_util_percentage=0.00
frame_ecce2_used=0 | frame_ecce2_fixed=0 | frame_ecce2_available=1 | frame_ecce2_util_percentage=0.00
icape2_used=0 | icape2_fixed=0 | icape2_available=2 | icape2_util_percentage=0.00
pcie_2_1_used=0 | pcie_2_1_fixed=0 | pcie_2_1_available=1 | pcie_2_1_util_percentage=0.00
startupe2_used=0 | startupe2_fixed=0 | startupe2_available=1 | startupe2_util_percentage=0.00
xadc_used=0 | xadc_fixed=0 | xadc_available=1 | xadc_util_percentage=0.00
primitives
fdre_used=2353 | fdre_functional_category=Flop & Latch | lut2_used=499 | lut2_functional_category=LUT
lut6_used=479 | lut6_functional_category=LUT | lut4_used=329 | lut4_functional_category=LUT
lut3_used=324 | lut3_functional_category=LUT | lut5_used=298 | lut5_functional_category=LUT
carry4_used=237 | carry4_functional_category=CarryLogic | lut1_used=58 | lut1_functional_category=LUT
fdse_used=45 | fdse_functional_category=Flop & Latch | obuf_used=17 | obuf_functional_category=IO
ibuf_used=5 | ibuf_functional_category=IO | srlc32e_used=2 | srlc32e_functional_category=Distributed Memory
ramb18e1_used=1 | ramb18e1_functional_category=Block Memory | obuft_used=1 | obuft_functional_category=IO
muxf7_used=1 | muxf7_functional_category=MuxFx | dsp48e1_used=1 | dsp48e1_functional_category=Block Arithmetic
bufg_used=1 | bufg_functional_category=Clock
io_standard
diff_sstl15_r=0 | hstl_ii=0 | lvcmos15=0 | blvds_25=0
lvttl=0 | diff_sstl15=0 | hstl_i=0 | diff_mobile_ddr=0
lvcmos33=1 | mobile_ddr=0 | lvcmos12=0 | lvcmos25=0
pci33_3=0 | hsul_12=0 | lvcmos18=0 | hstl_i_18=0
diff_hsul_12=0 | hstl_ii_18=0 | sstl18_i=0 | sstl18_ii=0
sstl15=0 | sstl15_r=0 | sstl135=0 | sstl135_r=0
lvds_25=0 | diff_hstl_i=0 | rsds_25=0 | diff_hstl_ii=0
tmds_33=0 | diff_hstl_i_18=0 | mini_lvds_25=0 | diff_hstl_ii_18=0
ppds_25=0 | diff_sstl18_i=0 | diff_sstl18_ii=0 | diff_sstl135=0
diff_sstl135_r=0

router
usage
lut=1752 | ff=2398 | bram36=0 | bram18=1
ctrls=145 | dsp=1 | iob=22 | bufg=0
global_clocks=1 | pll=0 | bufr=0 | nets=5486
movable_instances=4741 | pins=26647 | bogomips=0 | high_fanout_nets=2
effort=2 | threads=2 | router_timing_driven=1 | timing_constraints_exist=1
congestion_level=0 | estimated_expansions=2073048 | actual_expansions=1202153 | router_runtime=110.744000

synthesis
command_line_options
-part=xc7a35ticsg324-1L | -name=default::[not_specified] | -top=car_top | -include_dirs=default::[not_specified]
-generic=default::[not_specified] | -verilog_define=default::[not_specified] | -constrset=default::[not_specified] | -seu_protect=default::none
-flatten_hierarchy=default::rebuilt | -gated_clock_conversion=default::off | -directive=default::default | -rtl=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -rtl_skip_constraints=default::[not_specified] | -no_lc=default::[not_specified] | -bufg=default::12
-fanout_limit=default::10000 | -shreg_min_size=default::3 | -mode=default::default | -fsm_extraction=default::auto
-keep_equivalent_registers=default::[not_specified] | -resource_sharing=default::auto | -cascade_dsp=default::auto | -control_set_opt_threshold=default::auto
-max_bram=default::-1 | -max_uram=default::-1 | -max_dsp=default::-1 | -max_bram_cascade_height=default::-1
-max_uram_cascade_height=default::-1 | -retiming=default::[not_specified] | -no_srlextract=default::[not_specified] | -assert=default::[not_specified]
-no_timing_driven=default::[not_specified]
usage
elapsed=00:03:14s | memory_peak=717.750MB | memory_gain=510.848MB | hls_ip=5