Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Workspace\add4bit\src\add4bit.v
C:\Gowin\Workspace\add4bit\src\clkdiv.v
C:\Gowin\Workspace\add4bit\src\drv7seg.v
C:\Gowin\Workspace\add4bit\src\mux7seg.v
C:\Gowin\Workspace\add4bit\src\test_add4bit.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.06Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Sat Jun 05 12:41:42 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module test_add4bit
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.123s, Peak memory usage = 135.449MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 135.449MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 135.449MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 135.449MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 135.449MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 135.449MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 135.449MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 135.449MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 135.449MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 135.449MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 135.449MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.449MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 135.449MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 135.449MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 135.449MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 21
I/O Buf 21
    IBUF 9
    OBUF 12
Register 14
    DFF 3
    DFFR 11
LUT 50
    LUT2 7
    LUT3 4
    LUT4 39
ALU 10
    ALU 10
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 62(52 LUTs, 10 ALUs) / 4608 1%
Register 14 / 3756 1%
  --Register as Latch 0 / 3756 0%
  --Register as FF 14 / 3756 1%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
clk10KHz Base 10.000 100.0 0.000 5.000 mux7seg_1/i4/clk10KHz_s/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 257.6(MHz) 4 TOP
2 clk10KHz 100.0(MHz) 342.8(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.118
Data Arrival Time 4.827
Data Required Time 10.945
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_10_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 11 clk_ibuf/O
1.345 0.363 tNET RR 1 mux7seg_1/i4/count_0_s0/CLK
1.803 0.458 tC2Q RF 2 mux7seg_1/i4/count_0_s0/Q
2.283 0.480 tNET FF 2 mux7seg_1/i4/n30_s/I1
3.328 1.045 tINS FF 1 mux7seg_1/i4/n30_s/COUT
3.328 0.000 tNET FF 2 mux7seg_1/i4/n29_s/CIN
3.385 0.057 tINS FF 1 mux7seg_1/i4/n29_s/COUT
3.385 0.000 tNET FF 2 mux7seg_1/i4/n28_s/CIN
3.442 0.057 tINS FF 1 mux7seg_1/i4/n28_s/COUT
3.442 0.000 tNET FF 2 mux7seg_1/i4/n27_s/CIN
3.499 0.057 tINS FF 1 mux7seg_1/i4/n27_s/COUT
3.499 0.000 tNET FF 2 mux7seg_1/i4/n26_s/CIN
3.556 0.057 tINS FF 1 mux7seg_1/i4/n26_s/COUT
3.556 0.000 tNET FF 2 mux7seg_1/i4/n25_s/CIN
3.613 0.057 tINS FF 1 mux7seg_1/i4/n25_s/COUT
3.613 0.000 tNET FF 2 mux7seg_1/i4/n24_s/CIN
3.670 0.057 tINS FF 1 mux7seg_1/i4/n24_s/COUT
3.670 0.000 tNET FF 2 mux7seg_1/i4/n23_s/CIN
3.727 0.057 tINS FF 1 mux7seg_1/i4/n23_s/COUT
3.727 0.000 tNET FF 2 mux7seg_1/i4/n22_s/CIN
3.784 0.057 tINS FF 1 mux7seg_1/i4/n22_s/COUT
3.784 0.000 tNET FF 2 mux7seg_1/i4/n21_s/CIN
4.347 0.563 tINS FF 1 mux7seg_1/i4/n21_s/SUM
4.827 0.480 tNET FF 1 mux7seg_1/i4/count_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 11 clk_ibuf/O
11.345 0.363 tNET RR 1 mux7seg_1/i4/count_10_s0/CLK
10.945 -0.400 tSu 1 mux7seg_1/i4/count_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 2.064, 59.270%; route: 0.960, 27.568%; tC2Q: 0.458, 13.162%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 6.175
Data Arrival Time 4.770
Data Required Time 10.945
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_9_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 11 clk_ibuf/O
1.345 0.363 tNET RR 1 mux7seg_1/i4/count_0_s0/CLK
1.803 0.458 tC2Q RF 2 mux7seg_1/i4/count_0_s0/Q
2.283 0.480 tNET FF 2 mux7seg_1/i4/n30_s/I1
3.328 1.045 tINS FF 1 mux7seg_1/i4/n30_s/COUT
3.328 0.000 tNET FF 2 mux7seg_1/i4/n29_s/CIN
3.385 0.057 tINS FF 1 mux7seg_1/i4/n29_s/COUT
3.385 0.000 tNET FF 2 mux7seg_1/i4/n28_s/CIN
3.442 0.057 tINS FF 1 mux7seg_1/i4/n28_s/COUT
3.442 0.000 tNET FF 2 mux7seg_1/i4/n27_s/CIN
3.499 0.057 tINS FF 1 mux7seg_1/i4/n27_s/COUT
3.499 0.000 tNET FF 2 mux7seg_1/i4/n26_s/CIN
3.556 0.057 tINS FF 1 mux7seg_1/i4/n26_s/COUT
3.556 0.000 tNET FF 2 mux7seg_1/i4/n25_s/CIN
3.613 0.057 tINS FF 1 mux7seg_1/i4/n25_s/COUT
3.613 0.000 tNET FF 2 mux7seg_1/i4/n24_s/CIN
3.670 0.057 tINS FF 1 mux7seg_1/i4/n24_s/COUT
3.670 0.000 tNET FF 2 mux7seg_1/i4/n23_s/CIN
3.727 0.057 tINS FF 1 mux7seg_1/i4/n23_s/COUT
3.727 0.000 tNET FF 2 mux7seg_1/i4/n22_s/CIN
4.290 0.563 tINS FF 1 mux7seg_1/i4/n22_s/SUM
4.770 0.480 tNET FF 1 mux7seg_1/i4/count_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 11 clk_ibuf/O
11.345 0.363 tNET RR 1 mux7seg_1/i4/count_9_s0/CLK
10.945 -0.400 tSu 1 mux7seg_1/i4/count_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 2.007, 58.593%; route: 0.960, 28.026%; tC2Q: 0.458, 13.381%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 6.232
Data Arrival Time 4.713
Data Required Time 10.945
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_8_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 11 clk_ibuf/O
1.345 0.363 tNET RR 1 mux7seg_1/i4/count_0_s0/CLK
1.803 0.458 tC2Q RF 2 mux7seg_1/i4/count_0_s0/Q
2.283 0.480 tNET FF 2 mux7seg_1/i4/n30_s/I1
3.328 1.045 tINS FF 1 mux7seg_1/i4/n30_s/COUT
3.328 0.000 tNET FF 2 mux7seg_1/i4/n29_s/CIN
3.385 0.057 tINS FF 1 mux7seg_1/i4/n29_s/COUT
3.385 0.000 tNET FF 2 mux7seg_1/i4/n28_s/CIN
3.442 0.057 tINS FF 1 mux7seg_1/i4/n28_s/COUT
3.442 0.000 tNET FF 2 mux7seg_1/i4/n27_s/CIN
3.499 0.057 tINS FF 1 mux7seg_1/i4/n27_s/COUT
3.499 0.000 tNET FF 2 mux7seg_1/i4/n26_s/CIN
3.556 0.057 tINS FF 1 mux7seg_1/i4/n26_s/COUT
3.556 0.000 tNET FF 2 mux7seg_1/i4/n25_s/CIN
3.613 0.057 tINS FF 1 mux7seg_1/i4/n25_s/COUT
3.613 0.000 tNET FF 2 mux7seg_1/i4/n24_s/CIN
3.670 0.057 tINS FF 1 mux7seg_1/i4/n24_s/COUT
3.670 0.000 tNET FF 2 mux7seg_1/i4/n23_s/CIN
4.233 0.563 tINS FF 1 mux7seg_1/i4/n23_s/SUM
4.713 0.480 tNET FF 1 mux7seg_1/i4/count_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 11 clk_ibuf/O
11.345 0.363 tNET RR 1 mux7seg_1/i4/count_8_s0/CLK
10.945 -0.400 tSu 1 mux7seg_1/i4/count_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 1.950, 57.892%; route: 0.960, 28.501%; tC2Q: 0.458, 13.607%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 6.289
Data Arrival Time 4.656
Data Required Time 10.945
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 11 clk_ibuf/O
1.345 0.363 tNET RR 1 mux7seg_1/i4/count_0_s0/CLK
1.803 0.458 tC2Q RF 2 mux7seg_1/i4/count_0_s0/Q
2.283 0.480 tNET FF 2 mux7seg_1/i4/n30_s/I1
3.328 1.045 tINS FF 1 mux7seg_1/i4/n30_s/COUT
3.328 0.000 tNET FF 2 mux7seg_1/i4/n29_s/CIN
3.385 0.057 tINS FF 1 mux7seg_1/i4/n29_s/COUT
3.385 0.000 tNET FF 2 mux7seg_1/i4/n28_s/CIN
3.442 0.057 tINS FF 1 mux7seg_1/i4/n28_s/COUT
3.442 0.000 tNET FF 2 mux7seg_1/i4/n27_s/CIN
3.499 0.057 tINS FF 1 mux7seg_1/i4/n27_s/COUT
3.499 0.000 tNET FF 2 mux7seg_1/i4/n26_s/CIN
3.556 0.057 tINS FF 1 mux7seg_1/i4/n26_s/COUT
3.556 0.000 tNET FF 2 mux7seg_1/i4/n25_s/CIN
3.613 0.057 tINS FF 1 mux7seg_1/i4/n25_s/COUT
3.613 0.000 tNET FF 2 mux7seg_1/i4/n24_s/CIN
4.176 0.563 tINS FF 1 mux7seg_1/i4/n24_s/SUM
4.656 0.480 tNET FF 1 mux7seg_1/i4/count_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 11 clk_ibuf/O
11.345 0.363 tNET RR 1 mux7seg_1/i4/count_7_s0/CLK
10.945 -0.400 tSu 1 mux7seg_1/i4/count_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 1.893, 57.168%; route: 0.960, 28.991%; tC2Q: 0.458, 13.841%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 6.346
Data Arrival Time 4.599
Data Required Time 10.945
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_6_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 11 clk_ibuf/O
1.345 0.363 tNET RR 1 mux7seg_1/i4/count_0_s0/CLK
1.803 0.458 tC2Q RF 2 mux7seg_1/i4/count_0_s0/Q
2.283 0.480 tNET FF 2 mux7seg_1/i4/n30_s/I1
3.328 1.045 tINS FF 1 mux7seg_1/i4/n30_s/COUT
3.328 0.000 tNET FF 2 mux7seg_1/i4/n29_s/CIN
3.385 0.057 tINS FF 1 mux7seg_1/i4/n29_s/COUT
3.385 0.000 tNET FF 2 mux7seg_1/i4/n28_s/CIN
3.442 0.057 tINS FF 1 mux7seg_1/i4/n28_s/COUT
3.442 0.000 tNET FF 2 mux7seg_1/i4/n27_s/CIN
3.499 0.057 tINS FF 1 mux7seg_1/i4/n27_s/COUT
3.499 0.000 tNET FF 2 mux7seg_1/i4/n26_s/CIN
3.556 0.057 tINS FF 1 mux7seg_1/i4/n26_s/COUT
3.556 0.000 tNET FF 2 mux7seg_1/i4/n25_s/CIN
4.119 0.563 tINS FF 1 mux7seg_1/i4/n25_s/SUM
4.599 0.480 tNET FF 1 mux7seg_1/i4/count_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 11 clk_ibuf/O
11.345 0.363 tNET RR 1 mux7seg_1/i4/count_6_s0/CLK
10.945 -0.400 tSu 1 mux7seg_1/i4/count_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 1.836, 56.417%; route: 0.960, 29.499%; tC2Q: 0.458, 14.084%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%