Timing Messages

Report Title Gowin Timing Analysis Report
Design File C:\Gowin\Workspace\add4bit\impl\gwsynthesis\add4bit.vg
Physical Constraints File C:\Gowin\Workspace\add4bit\src\add4bit.cst
Timing Constraint File C:\Gowin\Workspace\add4bit\src\add4bit.sdc
GOWIN version V1.9.7.06Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Sat Jun 05 12:41:47 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 2.375V 85C
Hold Delay Model Fast 2.625V 0C
Numbers of Paths Analyzed 93
Numbers of Endpoints Analyzed 37
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 11

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I
mux7seg_1/clk10KHz Base 10.000 100.000 0.000 5.000 mux7seg_1/i4/clk10KHz_s/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 306.914(MHz) 4 TOP
2 mux7seg_1/clk10KHz 100.000(MHz) 446.598(MHz) 2 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
mux7seg_1/clk10KHz Setup 0.000 0
mux7seg_1/clk10KHz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 6.742 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_10_s0/D clk:[R] clk:[R] 10.000 0.000 2.858
2 6.799 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_9_s0/D clk:[R] clk:[R] 10.000 0.000 2.801
3 6.856 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_8_s0/D clk:[R] clk:[R] 10.000 0.000 2.744
4 6.913 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_7_s0/D clk:[R] clk:[R] 10.000 0.000 2.687
5 6.970 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_6_s0/D clk:[R] clk:[R] 10.000 0.000 2.630
6 7.027 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_5_s0/D clk:[R] clk:[R] 10.000 0.000 2.573
7 7.084 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_4_s0/D clk:[R] clk:[R] 10.000 0.000 2.516
8 7.141 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_3_s0/D clk:[R] clk:[R] 10.000 0.000 2.459
9 7.198 mux7seg_1/i4/count_1_s0/Q mux7seg_1/i4/count_2_s0/D clk:[R] clk:[R] 10.000 0.000 2.402
10 7.761 mux7seg_1/seg_no_0_s0/Q mux7seg_1/seg_no_2_s0/D mux7seg_1/clk10KHz:[R] mux7seg_1/clk10KHz:[R] 10.000 0.000 1.839
11 7.761 mux7seg_1/seg_no_0_s0/Q mux7seg_1/seg_no_1_s0/D mux7seg_1/clk10KHz:[R] mux7seg_1/clk10KHz:[R] 10.000 0.000 1.839
12 7.948 mux7seg_1/i4/count_0_s0/Q mux7seg_1/i4/count_1_s0/D clk:[R] clk:[R] 10.000 0.000 1.652
13 8.034 mux7seg_1/seg_no_0_s0/Q mux7seg_1/seg_no_0_s0/D mux7seg_1/clk10KHz:[R] mux7seg_1/clk10KHz:[R] 10.000 0.000 1.566
14 8.507 mux7seg_1/i4/count_0_s0/Q mux7seg_1/i4/count_0_s0/D clk:[R] clk:[R] 10.000 0.000 1.093
15 10.115 mux7seg_1/i4/count_1_s0/RESET mux7seg_1/i4/count_1_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.942
16 10.115 mux7seg_1/i4/count_2_s0/RESET mux7seg_1/i4/count_2_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.942
17 10.115 mux7seg_1/i4/count_3_s0/RESET mux7seg_1/i4/count_3_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.942
18 10.115 mux7seg_1/i4/count_4_s0/RESET mux7seg_1/i4/count_4_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.942
19 10.115 mux7seg_1/i4/count_5_s0/RESET mux7seg_1/i4/count_5_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.942
20 10.115 mux7seg_1/i4/count_6_s0/RESET mux7seg_1/i4/count_6_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.942
21 10.119 mux7seg_1/i4/count_7_s0/RESET mux7seg_1/i4/count_7_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.937
22 10.119 mux7seg_1/i4/count_8_s0/RESET mux7seg_1/i4/count_8_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.937
23 10.119 mux7seg_1/i4/count_9_s0/RESET mux7seg_1/i4/count_9_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.937
24 10.119 mux7seg_1/i4/count_10_s0/RESET mux7seg_1/i4/count_10_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.937
25 10.124 mux7seg_1/i4/count_0_s0/RESET mux7seg_1/i4/count_0_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 10.000 -2.130 1.933

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.320 mux7seg_1/i4/count_0_s0/RESET mux7seg_1/i4/count_0_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.376
2 -0.316 mux7seg_1/i4/count_7_s0/RESET mux7seg_1/i4/count_7_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.379
3 -0.316 mux7seg_1/i4/count_8_s0/RESET mux7seg_1/i4/count_8_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.379
4 -0.316 mux7seg_1/i4/count_9_s0/RESET mux7seg_1/i4/count_9_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.379
5 -0.316 mux7seg_1/i4/count_10_s0/RESET mux7seg_1/i4/count_10_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.379
6 -0.313 mux7seg_1/i4/count_1_s0/RESET mux7seg_1/i4/count_1_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.383
7 -0.313 mux7seg_1/i4/count_2_s0/RESET mux7seg_1/i4/count_2_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.383
8 -0.313 mux7seg_1/i4/count_3_s0/RESET mux7seg_1/i4/count_3_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.383
9 -0.313 mux7seg_1/i4/count_4_s0/RESET mux7seg_1/i4/count_4_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.383
10 -0.313 mux7seg_1/i4/count_5_s0/RESET mux7seg_1/i4/count_5_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.383
11 -0.313 mux7seg_1/i4/count_6_s0/RESET mux7seg_1/i4/count_6_s0/RESET mux7seg_1/clk10KHz:[R] clk:[R] 0.000 -1.651 1.383
12 0.708 mux7seg_1/i4/count_0_s0/Q mux7seg_1/i4/count_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
13 0.712 mux7seg_1/seg_no_1_s0/Q mux7seg_1/seg_no_1_s0/D mux7seg_1/clk10KHz:[R] mux7seg_1/clk10KHz:[R] 0.000 0.000 0.712
14 0.714 mux7seg_1/seg_no_2_s0/Q mux7seg_1/seg_no_2_s0/D mux7seg_1/clk10KHz:[R] mux7seg_1/clk10KHz:[R] 0.000 0.000 0.714
15 0.729 mux7seg_1/i4/count_3_s0/Q mux7seg_1/i4/count_3_s0/D clk:[R] clk:[R] 0.000 0.000 0.729
16 0.730 mux7seg_1/i4/count_7_s0/Q mux7seg_1/i4/count_7_s0/D clk:[R] clk:[R] 0.000 0.000 0.730
17 0.730 mux7seg_1/i4/count_9_s0/Q mux7seg_1/i4/count_9_s0/D clk:[R] clk:[R] 0.000 0.000 0.730
18 0.959 mux7seg_1/i4/count_2_s0/Q mux7seg_1/i4/count_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.959
19 0.965 mux7seg_1/i4/count_10_s0/Q mux7seg_1/i4/count_10_s0/D clk:[R] clk:[R] 0.000 0.000 0.965
20 0.970 mux7seg_1/i4/count_4_s0/Q mux7seg_1/i4/count_4_s0/D clk:[R] clk:[R] 0.000 0.000 0.970
21 0.970 mux7seg_1/i4/count_5_s0/Q mux7seg_1/i4/count_5_s0/D clk:[R] clk:[R] 0.000 0.000 0.970
22 0.970 mux7seg_1/i4/count_6_s0/Q mux7seg_1/i4/count_6_s0/D clk:[R] clk:[R] 0.000 0.000 0.970
23 0.993 mux7seg_1/i4/count_0_s0/Q mux7seg_1/i4/count_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.993
24 1.060 mux7seg_1/seg_no_0_s0/Q mux7seg_1/seg_no_0_s0/D mux7seg_1/clk10KHz:[R] mux7seg_1/clk10KHz:[R] 0.000 0.000 1.060
25 1.064 mux7seg_1/i4/count_7_s0/Q mux7seg_1/i4/count_8_s0/D clk:[R] clk:[R] 0.000 0.000 1.064

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_10_s0
2 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_8_s0
3 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_4_s0
4 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_5_s0
5 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_9_s0
6 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_6_s0
7 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_0_s0
8 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_1_s0
9 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_7_s0
10 2.911 4.161 1.250 Low Pulse Width clk mux7seg_1/i4/count_2_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 6.742
Data Arrival Time 4.988
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.026 0.057 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/COUT
4.026 0.000 tNET FF 2 R11C10[1][A] mux7seg_1/i4/n28_s/CIN
4.083 0.057 tINS FF 1 R11C10[1][A] mux7seg_1/i4/n28_s/COUT
4.083 0.000 tNET FF 2 R11C10[1][B] mux7seg_1/i4/n27_s/CIN
4.140 0.057 tINS FF 1 R11C10[1][B] mux7seg_1/i4/n27_s/COUT
4.140 0.000 tNET FF 2 R11C10[2][A] mux7seg_1/i4/n26_s/CIN
4.197 0.057 tINS FF 1 R11C10[2][A] mux7seg_1/i4/n26_s/COUT
4.197 0.000 tNET FF 2 R11C10[2][B] mux7seg_1/i4/n25_s/CIN
4.254 0.057 tINS FF 1 R11C10[2][B] mux7seg_1/i4/n25_s/COUT
4.254 0.000 tNET FF 2 R11C11[0][A] mux7seg_1/i4/n24_s/CIN
4.311 0.057 tINS FF 1 R11C11[0][A] mux7seg_1/i4/n24_s/COUT
4.311 0.000 tNET FF 2 R11C11[0][B] mux7seg_1/i4/n23_s/CIN
4.368 0.057 tINS FF 1 R11C11[0][B] mux7seg_1/i4/n23_s/COUT
4.368 0.000 tNET FF 2 R11C11[1][A] mux7seg_1/i4/n22_s/CIN
4.425 0.057 tINS FF 1 R11C11[1][A] mux7seg_1/i4/n22_s/COUT
4.425 0.000 tNET FF 2 R11C11[1][B] mux7seg_1/i4/n21_s/CIN
4.988 0.563 tINS FF 1 R11C11[1][B] mux7seg_1/i4/n21_s/SUM
4.988 0.000 tNET FF 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/CLK
11.730 -0.400 tSu 1 R11C11[1][B] mux7seg_1/i4/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 2.064, 72.212%; route: 0.336, 11.752%; tC2Q: 0.458, 16.035%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path2

Path Summary:

Slack 6.799
Data Arrival Time 4.931
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_9_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.026 0.057 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/COUT
4.026 0.000 tNET FF 2 R11C10[1][A] mux7seg_1/i4/n28_s/CIN
4.083 0.057 tINS FF 1 R11C10[1][A] mux7seg_1/i4/n28_s/COUT
4.083 0.000 tNET FF 2 R11C10[1][B] mux7seg_1/i4/n27_s/CIN
4.140 0.057 tINS FF 1 R11C10[1][B] mux7seg_1/i4/n27_s/COUT
4.140 0.000 tNET FF 2 R11C10[2][A] mux7seg_1/i4/n26_s/CIN
4.197 0.057 tINS FF 1 R11C10[2][A] mux7seg_1/i4/n26_s/COUT
4.197 0.000 tNET FF 2 R11C10[2][B] mux7seg_1/i4/n25_s/CIN
4.254 0.057 tINS FF 1 R11C10[2][B] mux7seg_1/i4/n25_s/COUT
4.254 0.000 tNET FF 2 R11C11[0][A] mux7seg_1/i4/n24_s/CIN
4.311 0.057 tINS FF 1 R11C11[0][A] mux7seg_1/i4/n24_s/COUT
4.311 0.000 tNET FF 2 R11C11[0][B] mux7seg_1/i4/n23_s/CIN
4.368 0.057 tINS FF 1 R11C11[0][B] mux7seg_1/i4/n23_s/COUT
4.368 0.000 tNET FF 2 R11C11[1][A] mux7seg_1/i4/n22_s/CIN
4.931 0.563 tINS FF 1 R11C11[1][A] mux7seg_1/i4/n22_s/SUM
4.931 0.000 tNET FF 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/CLK
11.730 -0.400 tSu 1 R11C11[1][A] mux7seg_1/i4/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 2.007, 71.647%; route: 0.336, 11.991%; tC2Q: 0.458, 16.362%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path3

Path Summary:

Slack 6.856
Data Arrival Time 4.874
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.026 0.057 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/COUT
4.026 0.000 tNET FF 2 R11C10[1][A] mux7seg_1/i4/n28_s/CIN
4.083 0.057 tINS FF 1 R11C10[1][A] mux7seg_1/i4/n28_s/COUT
4.083 0.000 tNET FF 2 R11C10[1][B] mux7seg_1/i4/n27_s/CIN
4.140 0.057 tINS FF 1 R11C10[1][B] mux7seg_1/i4/n27_s/COUT
4.140 0.000 tNET FF 2 R11C10[2][A] mux7seg_1/i4/n26_s/CIN
4.197 0.057 tINS FF 1 R11C10[2][A] mux7seg_1/i4/n26_s/COUT
4.197 0.000 tNET FF 2 R11C10[2][B] mux7seg_1/i4/n25_s/CIN
4.254 0.057 tINS FF 1 R11C10[2][B] mux7seg_1/i4/n25_s/COUT
4.254 0.000 tNET FF 2 R11C11[0][A] mux7seg_1/i4/n24_s/CIN
4.311 0.057 tINS FF 1 R11C11[0][A] mux7seg_1/i4/n24_s/COUT
4.311 0.000 tNET FF 2 R11C11[0][B] mux7seg_1/i4/n23_s/CIN
4.874 0.563 tINS FF 1 R11C11[0][B] mux7seg_1/i4/n23_s/SUM
4.874 0.000 tNET FF 1 R11C11[0][B] mux7seg_1/i4/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C11[0][B] mux7seg_1/i4/count_8_s0/CLK
11.730 -0.400 tSu 1 R11C11[0][B] mux7seg_1/i4/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 1.950, 71.058%; route: 0.336, 12.241%; tC2Q: 0.458, 16.702%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path4

Path Summary:

Slack 6.913
Data Arrival Time 4.817
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_7_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.026 0.057 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/COUT
4.026 0.000 tNET FF 2 R11C10[1][A] mux7seg_1/i4/n28_s/CIN
4.083 0.057 tINS FF 1 R11C10[1][A] mux7seg_1/i4/n28_s/COUT
4.083 0.000 tNET FF 2 R11C10[1][B] mux7seg_1/i4/n27_s/CIN
4.140 0.057 tINS FF 1 R11C10[1][B] mux7seg_1/i4/n27_s/COUT
4.140 0.000 tNET FF 2 R11C10[2][A] mux7seg_1/i4/n26_s/CIN
4.197 0.057 tINS FF 1 R11C10[2][A] mux7seg_1/i4/n26_s/COUT
4.197 0.000 tNET FF 2 R11C10[2][B] mux7seg_1/i4/n25_s/CIN
4.254 0.057 tINS FF 1 R11C10[2][B] mux7seg_1/i4/n25_s/COUT
4.254 0.000 tNET FF 2 R11C11[0][A] mux7seg_1/i4/n24_s/CIN
4.817 0.563 tINS FF 1 R11C11[0][A] mux7seg_1/i4/n24_s/SUM
4.817 0.000 tNET FF 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/CLK
11.730 -0.400 tSu 1 R11C11[0][A] mux7seg_1/i4/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 1.893, 70.444%; route: 0.336, 12.500%; tC2Q: 0.458, 17.056%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path5

Path Summary:

Slack 6.970
Data Arrival Time 4.760
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.026 0.057 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/COUT
4.026 0.000 tNET FF 2 R11C10[1][A] mux7seg_1/i4/n28_s/CIN
4.083 0.057 tINS FF 1 R11C10[1][A] mux7seg_1/i4/n28_s/COUT
4.083 0.000 tNET FF 2 R11C10[1][B] mux7seg_1/i4/n27_s/CIN
4.140 0.057 tINS FF 1 R11C10[1][B] mux7seg_1/i4/n27_s/COUT
4.140 0.000 tNET FF 2 R11C10[2][A] mux7seg_1/i4/n26_s/CIN
4.197 0.057 tINS FF 1 R11C10[2][A] mux7seg_1/i4/n26_s/COUT
4.197 0.000 tNET FF 2 R11C10[2][B] mux7seg_1/i4/n25_s/CIN
4.760 0.563 tINS FF 1 R11C10[2][B] mux7seg_1/i4/n25_s/SUM
4.760 0.000 tNET FF 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/CLK
11.730 -0.400 tSu 1 R11C10[2][B] mux7seg_1/i4/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 1.836, 69.803%; route: 0.336, 12.771%; tC2Q: 0.458, 17.426%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path6

Path Summary:

Slack 7.027
Data Arrival Time 4.703
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.026 0.057 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/COUT
4.026 0.000 tNET FF 2 R11C10[1][A] mux7seg_1/i4/n28_s/CIN
4.083 0.057 tINS FF 1 R11C10[1][A] mux7seg_1/i4/n28_s/COUT
4.083 0.000 tNET FF 2 R11C10[1][B] mux7seg_1/i4/n27_s/CIN
4.140 0.057 tINS FF 1 R11C10[1][B] mux7seg_1/i4/n27_s/COUT
4.140 0.000 tNET FF 2 R11C10[2][A] mux7seg_1/i4/n26_s/CIN
4.703 0.563 tINS FF 1 R11C10[2][A] mux7seg_1/i4/n26_s/SUM
4.703 0.000 tNET FF 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/CLK
11.730 -0.400 tSu 1 R11C10[2][A] mux7seg_1/i4/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 1.779, 69.135%; route: 0.336, 13.054%; tC2Q: 0.458, 17.811%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path7

Path Summary:

Slack 7.084
Data Arrival Time 4.646
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.026 0.057 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/COUT
4.026 0.000 tNET FF 2 R11C10[1][A] mux7seg_1/i4/n28_s/CIN
4.083 0.057 tINS FF 1 R11C10[1][A] mux7seg_1/i4/n28_s/COUT
4.083 0.000 tNET FF 2 R11C10[1][B] mux7seg_1/i4/n27_s/CIN
4.646 0.563 tINS FF 1 R11C10[1][B] mux7seg_1/i4/n27_s/SUM
4.646 0.000 tNET FF 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/CLK
11.730 -0.400 tSu 1 R11C10[1][B] mux7seg_1/i4/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 1.722, 68.435%; route: 0.336, 13.350%; tC2Q: 0.458, 18.215%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path8

Path Summary:

Slack 7.141
Data Arrival Time 4.589
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.026 0.057 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/COUT
4.026 0.000 tNET FF 2 R11C10[1][A] mux7seg_1/i4/n28_s/CIN
4.589 0.563 tINS FF 1 R11C10[1][A] mux7seg_1/i4/n28_s/SUM
4.589 0.000 tNET FF 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/CLK
11.730 -0.400 tSu 1 R11C10[1][A] mux7seg_1/i4/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 1.665, 67.704%; route: 0.336, 13.659%; tC2Q: 0.458, 18.637%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path9

Path Summary:

Slack 7.198
Data Arrival Time 4.532
Data Required Time 11.730
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
2.588 0.458 tC2Q RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/Q
2.924 0.336 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I0
3.969 1.045 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/COUT
3.969 0.000 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/CIN
4.532 0.563 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/SUM
4.532 0.000 tNET FF 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/CLK
11.730 -0.400 tSu 1 R11C10[0][B] mux7seg_1/i4/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 1.608, 66.937%; route: 0.336, 13.983%; tC2Q: 0.458, 19.079%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path10

Path Summary:

Slack 7.761
Data Arrival Time 2.987
Data Required Time 10.748
From mux7seg_1/seg_no_0_s0
To mux7seg_1/seg_no_2_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk mux7seg_1/clk10KHz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.148 1.148 tNET RR 1 R11C15[0][B] mux7seg_1/seg_no_0_s0/CLK
1.607 0.458 tC2Q RF 3 R11C15[0][B] mux7seg_1/seg_no_0_s0/Q
1.955 0.349 tNET FF 1 R11C15[0][A] mux7seg_1/n7_s0/I1
2.987 1.032 tINS FF 1 R11C15[0][A] mux7seg_1/n7_s0/F
2.987 0.000 tNET FF 1 R11C15[0][A] mux7seg_1/seg_no_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 mux7seg_1/clk10KHz
10.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
11.148 1.148 tNET RR 1 R11C15[0][A] mux7seg_1/seg_no_2_s0/CLK
10.748 -0.400 tSu 1 R11C15[0][A] mux7seg_1/seg_no_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.148, 100.000%
Arrival Data Path Delay cell: 1.032, 56.113%; route: 0.349, 18.966%; tC2Q: 0.458, 24.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.148, 100.000%

Path11

Path Summary:

Slack 7.761
Data Arrival Time 2.987
Data Required Time 10.748
From mux7seg_1/seg_no_0_s0
To mux7seg_1/seg_no_1_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk mux7seg_1/clk10KHz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.148 1.148 tNET RR 1 R11C15[0][B] mux7seg_1/seg_no_0_s0/CLK
1.607 0.458 tC2Q RF 3 R11C15[0][B] mux7seg_1/seg_no_0_s0/Q
1.955 0.349 tNET FF 1 R11C15[1][A] mux7seg_1/n8_s0/I1
2.987 1.032 tINS FF 1 R11C15[1][A] mux7seg_1/n8_s0/F
2.987 0.000 tNET FF 1 R11C15[1][A] mux7seg_1/seg_no_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 mux7seg_1/clk10KHz
10.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
11.148 1.148 tNET RR 1 R11C15[1][A] mux7seg_1/seg_no_1_s0/CLK
10.748 -0.400 tSu 1 R11C15[1][A] mux7seg_1/seg_no_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.148, 100.000%
Arrival Data Path Delay cell: 1.032, 56.113%; route: 0.349, 18.966%; tC2Q: 0.458, 24.921%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.148, 100.000%

Path12

Path Summary:

Slack 7.948
Data Arrival Time 3.782
Data Required Time 11.730
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/CLK
2.588 0.458 tC2Q RF 2 R11C12[0][A] mux7seg_1/i4/count_0_s0/Q
3.081 0.493 tNET FF 2 R11C10[0][A] mux7seg_1/i4/n30_s/I1
3.782 0.701 tINS FR 1 R11C10[0][A] mux7seg_1/i4/n30_s/SUM
3.782 0.000 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
11.730 -0.400 tSu 1 R11C10[0][A] mux7seg_1/i4/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 0.701, 42.431%; route: 0.493, 29.826%; tC2Q: 0.458, 27.743%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path13

Path Summary:

Slack 8.034
Data Arrival Time 2.714
Data Required Time 10.748
From mux7seg_1/seg_no_0_s0
To mux7seg_1/seg_no_0_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk mux7seg_1/clk10KHz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.148 1.148 tNET RR 1 R11C15[0][B] mux7seg_1/seg_no_0_s0/CLK
1.607 0.458 tC2Q RF 3 R11C15[0][B] mux7seg_1/seg_no_0_s0/Q
1.615 0.008 tNET FF 1 R11C15[0][B] mux7seg_1/n9_s2/I
2.714 1.099 tINS FF 1 R11C15[0][B] mux7seg_1/n9_s2/O
2.714 0.000 tNET FF 1 R11C15[0][B] mux7seg_1/seg_no_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 mux7seg_1/clk10KHz
10.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
11.148 1.148 tNET RR 1 R11C15[0][B] mux7seg_1/seg_no_0_s0/CLK
10.748 -0.400 tSu 1 R11C15[0][B] mux7seg_1/seg_no_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.148, 100.000%
Arrival Data Path Delay cell: 1.099, 70.200%; route: 0.008, 0.523%; tC2Q: 0.458, 29.277%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.148, 100.000%

Path14

Path Summary:

Slack 8.507
Data Arrival Time 3.223
Data Required Time 11.730
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/CLK
2.588 0.458 tC2Q RF 2 R11C12[0][A] mux7seg_1/i4/count_0_s0/Q
2.597 0.008 tNET FF 1 R11C12[0][A] mux7seg_1/i4/n31_s2/I
3.223 0.626 tINS FF 1 R11C12[0][A] mux7seg_1/i4/n31_s2/O
3.223 0.000 tNET FF 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/CLK
11.730 -0.400 tSu 1 R11C12[0][A] mux7seg_1/i4/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 0.626, 57.298%; route: 0.008, 0.750%; tC2Q: 0.458, 41.952%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path15

Path Summary:

Slack 10.115
Data Arrival Time 1.942
Data Required Time 12.057
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_1_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.942 1.942 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_1_s0
12.057 -0.043 tSu 1 R11C10[0][A] mux7seg_1/i4/count_1_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.942, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path16

Path Summary:

Slack 10.115
Data Arrival Time 1.942
Data Required Time 12.057
From mux7seg_1/i4/count_2_s0
To mux7seg_1/i4/count_2_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.942 1.942 tNET RR 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_2_s0
12.057 -0.043 tSu 1 R11C10[0][B] mux7seg_1/i4/count_2_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.942, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path17

Path Summary:

Slack 10.115
Data Arrival Time 1.942
Data Required Time 12.057
From mux7seg_1/i4/count_3_s0
To mux7seg_1/i4/count_3_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.942 1.942 tNET RR 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_3_s0
12.057 -0.043 tSu 1 R11C10[1][A] mux7seg_1/i4/count_3_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.942, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path18

Path Summary:

Slack 10.115
Data Arrival Time 1.942
Data Required Time 12.057
From mux7seg_1/i4/count_4_s0
To mux7seg_1/i4/count_4_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.942 1.942 tNET RR 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_4_s0
12.057 -0.043 tSu 1 R11C10[1][B] mux7seg_1/i4/count_4_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.942, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path19

Path Summary:

Slack 10.115
Data Arrival Time 1.942
Data Required Time 12.057
From mux7seg_1/i4/count_5_s0
To mux7seg_1/i4/count_5_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.942 1.942 tNET RR 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_5_s0
12.057 -0.043 tSu 1 R11C10[2][A] mux7seg_1/i4/count_5_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.942, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path20

Path Summary:

Slack 10.115
Data Arrival Time 1.942
Data Required Time 12.057
From mux7seg_1/i4/count_6_s0
To mux7seg_1/i4/count_6_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.942 1.942 tNET RR 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_6_s0
12.057 -0.043 tSu 1 R11C10[2][B] mux7seg_1/i4/count_6_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.942, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path21

Path Summary:

Slack 10.119
Data Arrival Time 1.937
Data Required Time 12.057
From mux7seg_1/i4/count_7_s0
To mux7seg_1/i4/count_7_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.937 1.937 tNET RR 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_7_s0
12.057 -0.043 tSu 1 R11C11[0][A] mux7seg_1/i4/count_7_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.937, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path22

Path Summary:

Slack 10.119
Data Arrival Time 1.937
Data Required Time 12.057
From mux7seg_1/i4/count_8_s0
To mux7seg_1/i4/count_8_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.937 1.937 tNET RR 1 R11C11[0][B] mux7seg_1/i4/count_8_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C11[0][B] mux7seg_1/i4/count_8_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_8_s0
12.057 -0.043 tSu 1 R11C11[0][B] mux7seg_1/i4/count_8_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.937, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path23

Path Summary:

Slack 10.119
Data Arrival Time 1.937
Data Required Time 12.057
From mux7seg_1/i4/count_9_s0
To mux7seg_1/i4/count_9_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.937 1.937 tNET RR 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_9_s0
12.057 -0.043 tSu 1 R11C11[1][A] mux7seg_1/i4/count_9_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.937, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path24

Path Summary:

Slack 10.119
Data Arrival Time 1.937
Data Required Time 12.057
From mux7seg_1/i4/count_10_s0
To mux7seg_1/i4/count_10_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.937 1.937 tNET RR 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_10_s0
12.057 -0.043 tSu 1 R11C11[1][B] mux7seg_1/i4/count_10_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.937, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path25

Path Summary:

Slack 10.124
Data Arrival Time 1.933
Data Required Time 12.057
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_0_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.933 1.933 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 11 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/CLK
12.100 -0.030 tUnc mux7seg_1/i4/count_0_s0
12.057 -0.043 tSu 1 R11C12[0][A] mux7seg_1/i4/count_0_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.933, 100.000%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -0.320
Data Arrival Time 1.376
Data Required Time 1.696
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_0_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.376 1.376 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_0_s0
1.696 0.015 tHld 1 R11C12[0][A] mux7seg_1/i4/count_0_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.376, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path2

Path Summary:

Slack -0.316
Data Arrival Time 1.379
Data Required Time 1.696
From mux7seg_1/i4/count_7_s0
To mux7seg_1/i4/count_7_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.379 1.379 tNET RR 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_7_s0
1.696 0.015 tHld 1 R11C11[0][A] mux7seg_1/i4/count_7_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.379, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path3

Path Summary:

Slack -0.316
Data Arrival Time 1.379
Data Required Time 1.696
From mux7seg_1/i4/count_8_s0
To mux7seg_1/i4/count_8_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.379 1.379 tNET RR 1 R11C11[0][B] mux7seg_1/i4/count_8_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[0][B] mux7seg_1/i4/count_8_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_8_s0
1.696 0.015 tHld 1 R11C11[0][B] mux7seg_1/i4/count_8_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.379, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path4

Path Summary:

Slack -0.316
Data Arrival Time 1.379
Data Required Time 1.696
From mux7seg_1/i4/count_9_s0
To mux7seg_1/i4/count_9_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.379 1.379 tNET RR 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_9_s0
1.696 0.015 tHld 1 R11C11[1][A] mux7seg_1/i4/count_9_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.379, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path5

Path Summary:

Slack -0.316
Data Arrival Time 1.379
Data Required Time 1.696
From mux7seg_1/i4/count_10_s0
To mux7seg_1/i4/count_10_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.379 1.379 tNET RR 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_10_s0
1.696 0.015 tHld 1 R11C11[1][B] mux7seg_1/i4/count_10_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.379, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path6

Path Summary:

Slack -0.313
Data Arrival Time 1.383
Data Required Time 1.696
From mux7seg_1/i4/count_1_s0
To mux7seg_1/i4/count_1_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.383 1.383 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_1_s0
1.696 0.015 tHld 1 R11C10[0][A] mux7seg_1/i4/count_1_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.383, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path7

Path Summary:

Slack -0.313
Data Arrival Time 1.383
Data Required Time 1.696
From mux7seg_1/i4/count_2_s0
To mux7seg_1/i4/count_2_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.383 1.383 tNET RR 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_2_s0
1.696 0.015 tHld 1 R11C10[0][B] mux7seg_1/i4/count_2_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.383, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path8

Path Summary:

Slack -0.313
Data Arrival Time 1.383
Data Required Time 1.696
From mux7seg_1/i4/count_3_s0
To mux7seg_1/i4/count_3_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.383 1.383 tNET RR 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_3_s0
1.696 0.015 tHld 1 R11C10[1][A] mux7seg_1/i4/count_3_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.383, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path9

Path Summary:

Slack -0.313
Data Arrival Time 1.383
Data Required Time 1.696
From mux7seg_1/i4/count_4_s0
To mux7seg_1/i4/count_4_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.383 1.383 tNET RR 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_4_s0
1.696 0.015 tHld 1 R11C10[1][B] mux7seg_1/i4/count_4_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.383, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path10

Path Summary:

Slack -0.313
Data Arrival Time 1.383
Data Required Time 1.696
From mux7seg_1/i4/count_5_s0
To mux7seg_1/i4/count_5_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.383 1.383 tNET RR 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_5_s0
1.696 0.015 tHld 1 R11C10[2][A] mux7seg_1/i4/count_5_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.383, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path11

Path Summary:

Slack -0.313
Data Arrival Time 1.383
Data Required Time 1.696
From mux7seg_1/i4/count_6_s0
To mux7seg_1/i4/count_6_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
1.383 1.383 tNET RR 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/CLK
1.681 0.030 tUnc mux7seg_1/i4/count_6_s0
1.696 0.015 tHld 1 R11C10[2][B] mux7seg_1/i4/count_6_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.383, 100.000%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path12

Path Summary:

Slack 0.708
Data Arrival Time 2.358
Data Required Time 1.651
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/CLK
1.984 0.333 tC2Q RR 2 R11C12[0][A] mux7seg_1/i4/count_0_s0/Q
1.986 0.002 tNET RR 1 R11C12[0][A] mux7seg_1/i4/n31_s2/I
2.358 0.372 tINS RF 1 R11C12[0][A] mux7seg_1/i4/n31_s2/O
2.358 0.000 tNET FF 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/CLK
1.651 0.000 tHld 1 R11C12[0][A] mux7seg_1/i4/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path13

Path Summary:

Slack 0.712
Data Arrival Time 1.519
Data Required Time 0.806
From mux7seg_1/seg_no_1_s0
To mux7seg_1/seg_no_1_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk mux7seg_1/clk10KHz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
0.806 0.806 tNET RR 1 R11C15[1][A] mux7seg_1/seg_no_1_s0/CLK
1.140 0.333 tC2Q RR 15 R11C15[1][A] mux7seg_1/seg_no_1_s0/Q
1.147 0.007 tNET RR 1 R11C15[1][A] mux7seg_1/n8_s0/I0
1.519 0.372 tINS RF 1 R11C15[1][A] mux7seg_1/n8_s0/F
1.519 0.000 tNET FF 1 R11C15[1][A] mux7seg_1/seg_no_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
0.806 0.806 tNET RR 1 R11C15[1][A] mux7seg_1/seg_no_1_s0/CLK
0.806 0.000 tHld 1 R11C15[1][A] mux7seg_1/seg_no_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.806, 100.000%
Arrival Data Path Delay cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.806, 100.000%

Path14

Path Summary:

Slack 0.714
Data Arrival Time 1.520
Data Required Time 0.806
From mux7seg_1/seg_no_2_s0
To mux7seg_1/seg_no_2_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk mux7seg_1/clk10KHz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
0.806 0.806 tNET RR 1 R11C15[0][A] mux7seg_1/seg_no_2_s0/CLK
1.140 0.333 tC2Q RR 14 R11C15[0][A] mux7seg_1/seg_no_2_s0/Q
1.148 0.008 tNET RR 1 R11C15[0][A] mux7seg_1/n7_s0/I2
1.520 0.372 tINS RF 1 R11C15[0][A] mux7seg_1/n7_s0/F
1.520 0.000 tNET FF 1 R11C15[0][A] mux7seg_1/seg_no_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
0.806 0.806 tNET RR 1 R11C15[0][A] mux7seg_1/seg_no_2_s0/CLK
0.806 0.000 tHld 1 R11C15[0][A] mux7seg_1/seg_no_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.806, 100.000%
Arrival Data Path Delay cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.806, 100.000%

Path15

Path Summary:

Slack 0.729
Data Arrival Time 2.379
Data Required Time 1.651
From mux7seg_1/i4/count_3_s0
To mux7seg_1/i4/count_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/CLK
1.984 0.333 tC2Q RR 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/Q
1.985 0.001 tNET RR 2 R11C10[1][A] mux7seg_1/i4/n28_s/I1
2.379 0.394 tINS RF 1 R11C10[1][A] mux7seg_1/i4/n28_s/SUM
2.379 0.000 tNET FF 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[1][A] mux7seg_1/i4/count_3_s0/CLK
1.651 0.000 tHld 1 R11C10[1][A] mux7seg_1/i4/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 54.083%; route: 0.001, 0.162%; tC2Q: 0.333, 45.755%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path16

Path Summary:

Slack 0.730
Data Arrival Time 2.380
Data Required Time 1.651
From mux7seg_1/i4/count_7_s0
To mux7seg_1/i4/count_7_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/CLK
1.984 0.333 tC2Q RR 2 R11C11[0][A] mux7seg_1/i4/count_7_s0/Q
1.986 0.002 tNET RR 2 R11C11[0][A] mux7seg_1/i4/n24_s/I1
2.380 0.394 tINS RF 1 R11C11[0][A] mux7seg_1/i4/n24_s/SUM
2.380 0.000 tNET FF 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/CLK
1.651 0.000 tHld 1 R11C11[0][A] mux7seg_1/i4/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path17

Path Summary:

Slack 0.730
Data Arrival Time 2.380
Data Required Time 1.651
From mux7seg_1/i4/count_9_s0
To mux7seg_1/i4/count_9_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/CLK
1.984 0.333 tC2Q RR 2 R11C11[1][A] mux7seg_1/i4/count_9_s0/Q
1.986 0.002 tNET RR 2 R11C11[1][A] mux7seg_1/i4/n22_s/I1
2.380 0.394 tINS RF 1 R11C11[1][A] mux7seg_1/i4/n22_s/SUM
2.380 0.000 tNET FF 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[1][A] mux7seg_1/i4/count_9_s0/CLK
1.651 0.000 tHld 1 R11C11[1][A] mux7seg_1/i4/count_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path18

Path Summary:

Slack 0.959
Data Arrival Time 2.609
Data Required Time 1.651
From mux7seg_1/i4/count_2_s0
To mux7seg_1/i4/count_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/CLK
1.984 0.333 tC2Q RF 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/Q
2.215 0.231 tNET FF 2 R11C10[0][B] mux7seg_1/i4/n29_s/I1
2.609 0.394 tINS FF 1 R11C10[0][B] mux7seg_1/i4/n29_s/SUM
2.609 0.000 tNET FF 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[0][B] mux7seg_1/i4/count_2_s0/CLK
1.651 0.000 tHld 1 R11C10[0][B] mux7seg_1/i4/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 41.102%; route: 0.231, 24.124%; tC2Q: 0.333, 34.773%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path19

Path Summary:

Slack 0.965
Data Arrival Time 2.616
Data Required Time 1.651
From mux7seg_1/i4/count_10_s0
To mux7seg_1/i4/count_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/CLK
1.984 0.333 tC2Q RR 2 R11C11[1][B] mux7seg_1/i4/count_10_s0/Q
2.222 0.238 tNET RR 2 R11C11[1][B] mux7seg_1/i4/n21_s/I1
2.616 0.394 tINS RF 1 R11C11[1][B] mux7seg_1/i4/n21_s/SUM
2.616 0.000 tNET FF 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[1][B] mux7seg_1/i4/count_10_s0/CLK
1.651 0.000 tHld 1 R11C11[1][B] mux7seg_1/i4/count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path20

Path Summary:

Slack 0.970
Data Arrival Time 2.621
Data Required Time 1.651
From mux7seg_1/i4/count_4_s0
To mux7seg_1/i4/count_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/CLK
1.984 0.333 tC2Q RR 2 R11C10[1][B] mux7seg_1/i4/count_4_s0/Q
2.227 0.243 tNET RR 2 R11C10[1][B] mux7seg_1/i4/n27_s/I1
2.621 0.394 tINS RF 1 R11C10[1][B] mux7seg_1/i4/n27_s/SUM
2.621 0.000 tNET FF 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[1][B] mux7seg_1/i4/count_4_s0/CLK
1.651 0.000 tHld 1 R11C10[1][B] mux7seg_1/i4/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path21

Path Summary:

Slack 0.970
Data Arrival Time 2.621
Data Required Time 1.651
From mux7seg_1/i4/count_5_s0
To mux7seg_1/i4/count_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/CLK
1.984 0.333 tC2Q RR 2 R11C10[2][A] mux7seg_1/i4/count_5_s0/Q
2.227 0.243 tNET RR 2 R11C10[2][A] mux7seg_1/i4/n26_s/I1
2.621 0.394 tINS RF 1 R11C10[2][A] mux7seg_1/i4/n26_s/SUM
2.621 0.000 tNET FF 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[2][A] mux7seg_1/i4/count_5_s0/CLK
1.651 0.000 tHld 1 R11C10[2][A] mux7seg_1/i4/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path22

Path Summary:

Slack 0.970
Data Arrival Time 2.621
Data Required Time 1.651
From mux7seg_1/i4/count_6_s0
To mux7seg_1/i4/count_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/CLK
1.984 0.333 tC2Q RR 2 R11C10[2][B] mux7seg_1/i4/count_6_s0/Q
2.227 0.243 tNET RR 2 R11C10[2][B] mux7seg_1/i4/n25_s/I1
2.621 0.394 tINS RF 1 R11C10[2][B] mux7seg_1/i4/n25_s/SUM
2.621 0.000 tNET FF 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[2][B] mux7seg_1/i4/count_6_s0/CLK
1.651 0.000 tHld 1 R11C10[2][B] mux7seg_1/i4/count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path23

Path Summary:

Slack 0.993
Data Arrival Time 2.644
Data Required Time 1.651
From mux7seg_1/i4/count_0_s0
To mux7seg_1/i4/count_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C12[0][A] mux7seg_1/i4/count_0_s0/CLK
1.984 0.333 tC2Q RR 2 R11C12[0][A] mux7seg_1/i4/count_0_s0/Q
2.250 0.266 tNET RR 2 R11C10[0][A] mux7seg_1/i4/n30_s/I1
2.644 0.394 tINS RF 1 R11C10[0][A] mux7seg_1/i4/n30_s/SUM
2.644 0.000 tNET FF 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C10[0][A] mux7seg_1/i4/count_1_s0/CLK
1.651 0.000 tHld 1 R11C10[0][A] mux7seg_1/i4/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.394, 39.660%; route: 0.266, 26.787%; tC2Q: 0.333, 33.553%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path24

Path Summary:

Slack 1.060
Data Arrival Time 1.866
Data Required Time 0.806
From mux7seg_1/seg_no_0_s0
To mux7seg_1/seg_no_0_s0
Launch Clk mux7seg_1/clk10KHz:[R]
Latch Clk mux7seg_1/clk10KHz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
0.806 0.806 tNET RR 1 R11C15[0][B] mux7seg_1/seg_no_0_s0/CLK
1.140 0.333 tC2Q RR 3 R11C15[0][B] mux7seg_1/seg_no_0_s0/Q
1.142 0.002 tNET RR 1 R11C15[0][B] mux7seg_1/n9_s2/I
1.866 0.724 tINS RR 1 R11C15[0][B] mux7seg_1/n9_s2/O
1.866 0.000 tNET RR 1 R11C15[0][B] mux7seg_1/seg_no_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 mux7seg_1/clk10KHz
0.000 0.000 tCL RR 14 R11C11[2][B] mux7seg_1/i4/clk10KHz_s/F
0.806 0.806 tNET RR 1 R11C15[0][B] mux7seg_1/seg_no_0_s0/CLK
0.806 0.000 tHld 1 R11C15[0][B] mux7seg_1/seg_no_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.806, 100.000%
Arrival Data Path Delay cell: 0.724, 68.322%; route: 0.002, 0.223%; tC2Q: 0.333, 31.456%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.806, 100.000%

Path25

Path Summary:

Slack 1.064
Data Arrival Time 2.714
Data Required Time 1.651
From mux7seg_1/i4/count_7_s0
To mux7seg_1/i4/count_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[0][A] mux7seg_1/i4/count_7_s0/CLK
1.984 0.333 tC2Q RR 2 R11C11[0][A] mux7seg_1/i4/count_7_s0/Q
1.986 0.002 tNET RR 2 R11C11[0][A] mux7seg_1/i4/n24_s/I1
2.288 0.302 tINS RR 1 R11C11[0][A] mux7seg_1/i4/n24_s/COUT
2.288 0.000 tNET RR 2 R11C11[0][B] mux7seg_1/i4/n23_s/CIN
2.714 0.426 tINS RF 1 R11C11[0][B] mux7seg_1/i4/n23_s/SUM
2.714 0.000 tNET FF 1 R11C11[0][B] mux7seg_1/i4/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 11 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C11[0][B] mux7seg_1/i4/count_8_s0/CLK
1.651 0.000 tHld 1 R11C11[0][B] mux7seg_1/i4/count_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay cell: 0.728, 68.441%; route: 0.002, 0.222%; tC2Q: 0.333, 31.337%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_10_s0/CLK

MPW2

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_8_s0/CLK

MPW3

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_4_s0/CLK

MPW4

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_5_s0/CLK

MPW5

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_9_s0/CLK

MPW6

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_6_s0/CLK

MPW7

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_0_s0/CLK

MPW8

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_1_s0/CLK

MPW9

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_7_s0/CLK

MPW10

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: mux7seg_1/i4/count_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF mux7seg_1/i4/count_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR mux7seg_1/i4/count_2_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
15 seg_no[1] 7.954 1.972
14 clk10KHz 7.761 2.313
14 seg_no[2] 8.487 2.142
11 clk_d 6.742 1.505
3 seg_no[0] 7.761 0.349
2 count[9] 8.020 0.339
2 count[10] 8.102 0.339
2 count[6] 7.513 0.345
2 count[8] 7.165 0.807
2 count[7] 7.906 0.420

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R11C15 23.61%
R11C27 20.83%
R11C11 18.06%
R11C28 18.06%
R11C26 16.67%
R11C29 16.67%
R11C10 15.28%
R20C36 12.50%
R11C25 9.72%
R11C16 9.72%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command