Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Workspace210723\leg4\src\alu.v
C:\Gowin\Workspace210723\leg4\src\clkdiv.v
C:\Gowin\Workspace210723\leg4\src\debounce.v
C:\Gowin\Workspace210723\leg4\src\drv7seg.v
C:\Gowin\Workspace210723\leg4\src\leg4.v
C:\Gowin\Workspace210723\leg4\src\leg4_rom.v
C:\Gowin\Workspace210723\leg4\src\leg4sys.v
C:\Gowin\Workspace210723\leg4\src\mux7seg.v
C:\Gowin\Workspace210723\leg4\src\pc.v
C:\Gowin\Workspace210723\leg4\src\toggle.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.03Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Sat Jul 24 09:55:52 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module leg4sys
Synthesis Process Running parser:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.112s, Peak memory usage = 139.320MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 139.320MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 139.320MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 139.320MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 139.320MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 139.320MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 139.320MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 139.320MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 139.320MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 139.320MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 139.320MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 139.320MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 139.320MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 139.320MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 139.320MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 30
I/O Buf 26
    IBUF 5
    OBUF 21
Register 108
    DFF 3
    DFFR 11
    DFFC 86
    DFFCE 8
LUT 228
    LUT2 29
    LUT3 69
    LUT4 130
ALU 17
    ALU 17
INV 4
    INV 4

Resource Utilization Summary

Resource Usage Utilization
Logic 249(232 LUTs, 17 ALUs) / 4608 5%
Register 108 / 3756 3%
  --Register as Latch 0 / 3756 0%
  --Register as FF 108 / 3756 3%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
clk400Hz Base 10.000 100.0 0.000 5.000 inst1/clkdiv_1/clk400Hz_s/F
leg4_clk Base 10.000 100.0 0.000 5.000 leg4_clk_s4/F
clk10KHz Base 10.000 100.0 0.000 5.000 inst15/i4/clk10KHz_s/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 130.6(MHz) 5 TOP
2 clk400Hz 100.0(MHz) 747.2(MHz) 1 TOP
3 leg4_clk 100.0(MHz) 104.4(MHz) 7 TOP
4 clk10KHz 100.0(MHz) 342.8(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.422
Data Arrival Time 9.541
Data Required Time 9.963
From inst7/inst1/adr_2_s0
To inst7/a_3_s0
Launch Clk leg4_clk[R]
Latch Clk leg4_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 leg4_clk
0.000 0.000 tCL RR 13 leg4_clk_s4/F
0.363 0.363 tNET RR 1 inst7/inst1/adr_2_s0/CLK
0.821 0.458 tC2Q RF 26 inst7/inst1/adr_2_s0/Q
1.301 0.480 tNET FF 1 inst10/rom_out_0_s1/I1
2.400 1.099 tINS FF 3 inst10/rom_out_0_s1/F
2.880 0.480 tNET FF 2 inst7/inst2/n14_s/I1
3.925 1.045 tINS FF 1 inst7/inst2/n14_s/COUT
3.925 0.000 tNET FF 2 inst7/inst2/n13_s/CIN
3.982 0.057 tINS FF 1 inst7/inst2/n13_s/COUT
3.982 0.000 tNET FF 2 inst7/inst2/n12_s/CIN
4.039 0.057 tINS FF 1 inst7/inst2/n12_s/COUT
4.519 0.480 tNET FF 1 inst7/inst2/n15_s22/I2
5.341 0.822 tINS FF 1 inst7/inst2/n15_s22/F
5.821 0.480 tNET FF 1 inst7/inst2/n15_s25/I0
6.853 1.032 tINS FF 1 inst7/inst2/n15_s25/F
7.333 0.480 tNET FF 1 inst7/inst2/n15_s19/I1
7.482 0.149 tINS FF 1 inst7/inst2/n15_s19/O
7.962 0.480 tNET FF 1 inst7/inst2/data_Z_3_s/I1
9.061 1.099 tINS FF 2 inst7/inst2/data_Z_3_s/F
9.541 0.480 tNET FF 1 inst7/a_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 leg4_clk
10.000 0.000 tCL RR 13 leg4_clk_s4/F
10.363 0.363 tNET RR 1 inst7/a_3_s0/CLK
9.963 -0.400 tSu 1 inst7/a_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 5.360, 58.398%; route: 3.360, 36.608%; tC2Q: 0.458, 4.994%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 2

Path Summary:
Slack 0.422
Data Arrival Time 9.541
Data Required Time 9.963
From inst7/inst1/adr_2_s0
To inst7/out_3_s0
Launch Clk leg4_clk[R]
Latch Clk leg4_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 leg4_clk
0.000 0.000 tCL RR 13 leg4_clk_s4/F
0.363 0.363 tNET RR 1 inst7/inst1/adr_2_s0/CLK
0.821 0.458 tC2Q RF 26 inst7/inst1/adr_2_s0/Q
1.301 0.480 tNET FF 1 inst10/rom_out_0_s1/I1
2.400 1.099 tINS FF 3 inst10/rom_out_0_s1/F
2.880 0.480 tNET FF 2 inst7/inst2/n14_s/I1
3.925 1.045 tINS FF 1 inst7/inst2/n14_s/COUT
3.925 0.000 tNET FF 2 inst7/inst2/n13_s/CIN
3.982 0.057 tINS FF 1 inst7/inst2/n13_s/COUT
3.982 0.000 tNET FF 2 inst7/inst2/n12_s/CIN
4.039 0.057 tINS FF 1 inst7/inst2/n12_s/COUT
4.519 0.480 tNET FF 1 inst7/inst2/n15_s22/I2
5.341 0.822 tINS FF 1 inst7/inst2/n15_s22/F
5.821 0.480 tNET FF 1 inst7/inst2/n15_s25/I0
6.853 1.032 tINS FF 1 inst7/inst2/n15_s25/F
7.333 0.480 tNET FF 1 inst7/inst2/n15_s19/I1
7.482 0.149 tINS FF 1 inst7/inst2/n15_s19/O
7.962 0.480 tNET FF 1 inst7/inst2/data_Z_3_s/I1
9.061 1.099 tINS FF 2 inst7/inst2/data_Z_3_s/F
9.541 0.480 tNET FF 1 inst7/out_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 leg4_clk
10.000 0.000 tCL RR 13 leg4_clk_s4/F
10.363 0.363 tNET RR 1 inst7/out_3_s0/CLK
9.963 -0.400 tSu 1 inst7/out_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 5.360, 58.398%; route: 3.360, 36.608%; tC2Q: 0.458, 4.994%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 3

Path Summary:
Slack 1.151
Data Arrival Time 8.812
Data Required Time 9.963
From inst7/inst1/adr_2_s0
To inst7/out_2_s0
Launch Clk leg4_clk[R]
Latch Clk leg4_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 leg4_clk
0.000 0.000 tCL RR 13 leg4_clk_s4/F
0.363 0.363 tNET RR 1 inst7/inst1/adr_2_s0/CLK
0.821 0.458 tC2Q RF 26 inst7/inst1/adr_2_s0/Q
1.301 0.480 tNET FF 1 inst10/rom_out_0_s1/I1
2.400 1.099 tINS FF 3 inst10/rom_out_0_s1/F
2.880 0.480 tNET FF 2 inst7/inst2/n14_s/I1
3.925 1.045 tINS FF 1 inst7/inst2/n14_s/COUT
3.925 0.000 tNET FF 2 inst7/inst2/n13_s/CIN
3.982 0.057 tINS FF 1 inst7/inst2/n13_s/COUT
3.982 0.000 tNET FF 2 inst7/inst2/n12_s/CIN
4.545 0.563 tINS FF 1 inst7/inst2/n12_s/SUM
5.025 0.480 tNET FF 1 inst7/inst2/n16_s23/I1
6.124 1.099 tINS FF 1 inst7/inst2/n16_s23/F
6.604 0.480 tNET FF 1 inst7/inst2/n16_s19/I1
6.753 0.149 tINS FF 1 inst7/inst2/n16_s19/O
7.233 0.480 tNET FF 1 inst7/inst2/data_Z_2_s/I1
8.332 1.099 tINS FF 2 inst7/inst2/data_Z_2_s/F
8.812 0.480 tNET FF 1 inst7/out_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 leg4_clk
10.000 0.000 tCL RR 13 leg4_clk_s4/F
10.363 0.363 tNET RR 1 inst7/out_2_s0/CLK
9.963 -0.400 tSu 1 inst7/out_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 5.111, 60.490%; route: 2.880, 34.086%; tC2Q: 0.458, 5.424%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 4

Path Summary:
Slack 1.151
Data Arrival Time 8.812
Data Required Time 9.963
From inst7/inst1/adr_2_s0
To inst7/a_2_s0
Launch Clk leg4_clk[R]
Latch Clk leg4_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 leg4_clk
0.000 0.000 tCL RR 13 leg4_clk_s4/F
0.363 0.363 tNET RR 1 inst7/inst1/adr_2_s0/CLK
0.821 0.458 tC2Q RF 26 inst7/inst1/adr_2_s0/Q
1.301 0.480 tNET FF 1 inst10/rom_out_0_s1/I1
2.400 1.099 tINS FF 3 inst10/rom_out_0_s1/F
2.880 0.480 tNET FF 2 inst7/inst2/n14_s/I1
3.925 1.045 tINS FF 1 inst7/inst2/n14_s/COUT
3.925 0.000 tNET FF 2 inst7/inst2/n13_s/CIN
3.982 0.057 tINS FF 1 inst7/inst2/n13_s/COUT
3.982 0.000 tNET FF 2 inst7/inst2/n12_s/CIN
4.545 0.563 tINS FF 1 inst7/inst2/n12_s/SUM
5.025 0.480 tNET FF 1 inst7/inst2/n16_s23/I1
6.124 1.099 tINS FF 1 inst7/inst2/n16_s23/F
6.604 0.480 tNET FF 1 inst7/inst2/n16_s19/I1
6.753 0.149 tINS FF 1 inst7/inst2/n16_s19/O
7.233 0.480 tNET FF 1 inst7/inst2/data_Z_2_s/I1
8.332 1.099 tINS FF 2 inst7/inst2/data_Z_2_s/F
8.812 0.480 tNET FF 1 inst7/a_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 leg4_clk
10.000 0.000 tCL RR 13 leg4_clk_s4/F
10.363 0.363 tNET RR 1 inst7/a_2_s0/CLK
9.963 -0.400 tSu 1 inst7/a_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 5.111, 60.490%; route: 2.880, 34.086%; tC2Q: 0.458, 5.424%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%

Path 5

Path Summary:
Slack 1.208
Data Arrival Time 8.755
Data Required Time 9.963
From inst7/inst1/adr_2_s0
To inst7/out_1_s0
Launch Clk leg4_clk[R]
Latch Clk leg4_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 leg4_clk
0.000 0.000 tCL RR 13 leg4_clk_s4/F
0.363 0.363 tNET RR 1 inst7/inst1/adr_2_s0/CLK
0.821 0.458 tC2Q RF 26 inst7/inst1/adr_2_s0/Q
1.301 0.480 tNET FF 1 inst10/rom_out_0_s1/I1
2.400 1.099 tINS FF 3 inst10/rom_out_0_s1/F
2.880 0.480 tNET FF 2 inst7/inst2/n14_s/I1
3.925 1.045 tINS FF 1 inst7/inst2/n14_s/COUT
3.925 0.000 tNET FF 2 inst7/inst2/n13_s/CIN
4.488 0.563 tINS FF 1 inst7/inst2/n13_s/SUM
4.968 0.480 tNET FF 1 inst7/inst2/n17_s23/I1
6.067 1.099 tINS FF 1 inst7/inst2/n17_s23/F
6.547 0.480 tNET FF 1 inst7/inst2/n17_s19/I1
6.696 0.149 tINS FF 1 inst7/inst2/n17_s19/O
7.176 0.480 tNET FF 1 inst7/inst2/data_Z_1_s/I1
8.275 1.099 tINS FF 2 inst7/inst2/data_Z_1_s/F
8.755 0.480 tNET FF 1 inst7/out_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 leg4_clk
10.000 0.000 tCL RR 13 leg4_clk_s4/F
10.363 0.363 tNET RR 1 inst7/out_1_s0/CLK
9.963 -0.400 tSu 1 inst7/out_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay: cell: 5.054, 60.222%; route: 2.880, 34.317%; tC2Q: 0.458, 5.461%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.363, 100.000%