Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	C:\Gowin\Workspace210723\leg4\impl\gwsynthesis\leg4.vg
Physical Constraints File	C:\Gowin\Workspace210723\leg4\src\leg4.cst
Timing Constraint File	---
GOWIN version	V1.9.7.03Beta
Part Number	GW1N-UV4LQ144C6/I5
Device	GW1N-4B
Created Time	Sat Jul 24 09:55:56 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 2.375V 85C
Hold Delay Model	Fast 2.625V 0C
Numbers of Paths Analyzed	283
Numbers of Endpoints Analyzed	242
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	4
Numbers of Hold Violated Endpoints	26

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Objects
clk	Base	10.000	100.000	5.000	clk_ibuf/I
inst1/clk400Hz	Base	10.000	100.000	5.000	inst1/clkdiv_1/clk400Hz_s/F
leg4_clk	Base	10.000	100.000	5.000	leg4_clk_s4/F
inst15/clk10KHz	Base	10.000	100.000	5.000	inst15/i4/clk10KHz_s/F

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	112.087(MHz)	5	TOP
2	inst1/clk400Hz	100.000(MHz)	360.040(MHz)	1	TOP
3	leg4_clk	100.000(MHz)	97.014(MHz)	7	TOP
4	inst15/clk10KHz	100.000(MHz)	446.598(MHz)	2	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
inst1/clk400Hz	Setup	0.000	0
inst1/clk400Hz	Hold	0.000	0
leg4_clk	Setup	-1.043	4
leg4_clk	Hold	0.000	0
inst15/clk10KHz	Setup	0.000	0
inst15/clk10KHz	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	-0.308	inst7/inst1/adr_1_s0/Q	inst7/a_3_s0/D	leg4_clk:[R]	leg4_clk:[R]	10.000	9.908
2	-0.308	inst7/inst1/adr_1_s0/Q	inst7/out_3_s0/D	leg4_clk:[R]	leg4_clk:[R]	10.000	9.908
3	-0.214	inst7/inst1/adr_1_s0/Q	inst7/out_1_s0/D	leg4_clk:[R]	leg4_clk:[R]	10.000	9.814
4	-0.214	inst7/inst1/adr_1_s0/Q	inst7/a_1_s0/D	leg4_clk:[R]	leg4_clk:[R]	10.000	9.814
5	0.925	inst7/inst1/adr_1_s0/Q	inst7/out_2_s0/D	leg4_clk:[R]	leg4_clk:[R]	10.000	8.675
6	1.002	inst7/inst1/adr_1_s0/Q	inst7/a_2_s0/D	leg4_clk:[R]	leg4_clk:[R]	10.000	8.598
7	1.078	inst5/count_19_s0/Q	inst6/out_s0/D	clk:[R]	clk:[R]	10.000	8.522
8	1.118	inst7/inst1/adr_1_s0/Q	inst7/out_0_s0/D	leg4_clk:[R]	leg4_clk:[R]	10.000	8.482
9	1.118	inst7/inst1/adr_1_s0/Q	inst7/a_0_s0/D	leg4_clk:[R]	leg4_clk:[R]	10.000	8.482
10	1.312	inst5/count_19_s0/Q	inst5/count_17_s0/D	clk:[R]	clk:[R]	10.000	8.288
11	1.432	inst5/count_19_s0/Q	inst5/count_12_s0/D	clk:[R]	clk:[R]	10.000	8.168
12	1.551	inst5/count_19_s0/Q	inst6/prev_in_s0/D	clk:[R]	clk:[R]	10.000	8.049
13	1.610	inst5/count_19_s0/Q	inst5/count_0_s0/D	clk:[R]	clk:[R]	10.000	7.990
14	1.610	inst5/count_19_s0/Q	inst5/count_13_s0/D	clk:[R]	clk:[R]	10.000	7.990
15	1.610	inst5/count_19_s0/Q	inst5/count_18_s0/D	clk:[R]	clk:[R]	10.000	7.990
16	1.630	inst5/count_19_s0/Q	inst5/count_3_s0/D	clk:[R]	clk:[R]	10.000	7.970
17	1.692	inst1/clkdiv_1/count_1_s0/Q	inst1/clkdiv_1/count_13_s0/D	clk:[R]	clk:[R]	10.000	7.908
18	1.813	inst5/count_19_s0/Q	inst5/count_10_s0/D	clk:[R]	clk:[R]	10.000	7.787
19	1.813	inst5/count_19_s0/Q	inst5/count_11_s0/D	clk:[R]	clk:[R]	10.000	7.787
20	1.832	inst5/count_1_s0/Q	inst5/count_16_s0/D	clk:[R]	clk:[R]	10.000	7.768
21	1.859	inst5/count_19_s0/Q	inst5/count_4_s0/D	clk:[R]	clk:[R]	10.000	7.741
22	1.902	inst1/clkdiv_1/count_1_s0/Q	inst1/clkdiv_1/count_14_s0/D	clk:[R]	clk:[R]	10.000	7.698
23	1.921	inst5/count_19_s0/Q	inst5/count_9_s0/D	clk:[R]	clk:[R]	10.000	7.679
24	1.921	inst5/count_19_s0/Q	inst5/count_19_s0/D	clk:[R]	clk:[R]	10.000	7.679
25	1.921	inst5/count_19_s0/Q	inst5/count_21_s0/D	clk:[R]	clk:[R]	10.000	7.679

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	-1.358	inst1/clkdiv_1/n44_s1/I0	inst1/clkdiv_1/count_11_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	0.727
2	-0.654	inst15/i4/count_0_s0/RESET	inst15/i4/count_0_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.446
3	-0.650	inst15/i4/count_7_s0/RESET	inst15/i4/count_7_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.450
4	-0.650	inst15/i4/count_8_s0/RESET	inst15/i4/count_8_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.450
5	-0.650	inst15/i4/count_9_s0/RESET	inst15/i4/count_9_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.450
6	-0.650	inst15/i4/count_10_s0/RESET	inst15/i4/count_10_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.450
7	-0.647	inst15/i4/count_1_s0/RESET	inst15/i4/count_1_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.453
8	-0.647	inst15/i4/count_2_s0/RESET	inst15/i4/count_2_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.453
9	-0.647	inst15/i4/count_3_s0/RESET	inst15/i4/count_3_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.453
10	-0.647	inst15/i4/count_4_s0/RESET	inst15/i4/count_4_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.453
11	-0.647	inst15/i4/count_5_s0/RESET	inst15/i4/count_5_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.453
12	-0.647	inst15/i4/count_6_s0/RESET	inst15/i4/count_6_s0/RESET	inst15/clk10KHz:[R]	clk:[R]	-2.055	1.453
13	-0.529	inst1/clkdiv_1/n47_s1/I2	inst1/clkdiv_1/count_8_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.556
14	-0.528	inst1/clkdiv_1/n54_s1/I0	inst1/clkdiv_1/count_1_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.557
15	-0.528	inst1/clkdiv_1/n52_s1/I0	inst1/clkdiv_1/count_3_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.557
16	-0.528	inst1/clkdiv_1/n50_s1/I2	inst1/clkdiv_1/count_5_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.557
17	-0.528	inst1/clkdiv_1/n45_s1/I2	inst1/clkdiv_1/count_10_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.557
18	-0.528	inst1/clkdiv_1/n43_s1/I2	inst1/clkdiv_1/count_12_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.557
19	-0.525	inst1/clkdiv_1/n46_s1/I0	inst1/clkdiv_1/count_9_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.560
20	-0.525	inst1/clkdiv_1/n42_s1/I0	inst1/clkdiv_1/count_13_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.560
21	-0.177	inst1/clkdiv_1/n48_s1/I0	inst1/clkdiv_1/count_7_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.908
22	-0.176	inst1/clkdiv_1/n53_s1/I2	inst1/clkdiv_1/count_2_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.909
23	-0.174	inst1/clkdiv_1/n51_s1/I0	inst1/clkdiv_1/count_4_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.911
24	-0.174	inst1/clkdiv_1/n49_s1/I0	inst1/clkdiv_1/count_6_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.911
25	-0.173	inst1/clkdiv_1/n55_s1/I1	inst1/clkdiv_1/count_0_s0/D	inst1/clk400Hz:[R]	clk:[R]	-2.055	1.912

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.991	4.241	1.250	Low Pulse Width	clk	inst1/clkdiv_1/count_14_s0
2	2.991	4.241	1.250	Low Pulse Width	clk	inst1/clkdiv_1/count_12_s0
3	2.991	4.241	1.250	Low Pulse Width	clk	inst1/clkdiv_1/count_8_s0
4	2.991	4.241	1.250	Low Pulse Width	clk	inst1/clkdiv_1/count_0_s0
5	2.991	4.241	1.250	Low Pulse Width	clk	inst2/count_4_s0
6	2.991	4.241	1.250	Low Pulse Width	clk	inst8/count_12_s0
7	2.991	4.241	1.250	Low Pulse Width	clk	inst6/out_s0
8	2.991	4.241	1.250	Low Pulse Width	clk	inst2/count_5_s0
9	2.991	4.241	1.250	Low Pulse Width	clk	inst6/prev_in_s0
10	2.991	4.241	1.250	Low Pulse Width	clk	inst5/count_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.308
Data Arrival Time	11.139
Data Required Time	10.831
From	inst7/inst1/adr_1_s0
To	inst7/a_3_s0
Launch Clk	leg4_clk:[R]
Latch Clk	leg4_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					leg4_clk
0.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
1.231	1.231	tNET	RR	1	R11C14[1][B]	inst7/inst1/adr_1_s0/CLK
1.689	0.458	tC2Q	RF	22	R11C14[1][B]	inst7/inst1/adr_1_s0/Q
3.032	1.343	tNET	FF	1	R9C16[1][B]	inst10/rom_out_0_s1/I0
4.064	1.032	tINS	FF	3	R9C16[1][B]	inst10/rom_out_0_s1/F
4.896	0.832	tNET	FF	2	R11C16[0][A]	inst7/inst2/n14_s/I1
5.446	0.550	tINS	FR	1	R11C16[0][A]	inst7/inst2/n14_s/COUT
5.446	0.000	tNET	RR	2	R11C16[0][B]	inst7/inst2/n13_s/CIN
5.503	0.057	tINS	RF	1	R11C16[0][B]	inst7/inst2/n13_s/COUT
5.503	0.000	tNET	FF	2	R11C16[1][A]	inst7/inst2/n12_s/CIN
5.560	0.057	tINS	FF	1	R11C16[1][A]	inst7/inst2/n12_s/COUT
6.128	0.568	tNET	FF	1	R11C16[2][B]	inst7/inst2/n15_s22/I2
7.189	1.061	tINS	FR	1	R11C16[2][B]	inst7/inst2/n15_s22/F
7.608	0.419	tNET	RR	1	R11C17[3][B]	inst7/inst2/n15_s25/I0
8.640	1.032	tINS	RF	1	R11C17[3][B]	inst7/inst2/n15_s25/F
8.640	0.000	tNET	FF	1	R11C17[3][A]	inst7/inst2/n15_s19/I1
8.789	0.149	tINS	FF	1	R11C17[3][A]	inst7/inst2/n15_s19/O
9.289	0.500	tNET	FF	1	R11C16[2][A]	inst7/inst2/data_Z_3_s/I1
10.091	0.802	tINS	FR	2	R11C16[2][A]	inst7/inst2/data_Z_3_s/F
11.139	1.048	tNET	RR	1	R12C16[0][B]	inst7/a_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					leg4_clk
10.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
11.231	1.231	tNET	RR	1	R12C16[0][B]	inst7/a_3_s0/CLK
10.831	-0.400	tSu		1	R12C16[0][B]	inst7/a_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay	cell: 4.740, 47.841%; route: 4.709, 47.533%; tC2Q: 0.458, 4.626%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%

Path2

Path Summary:

Slack	-0.308
Data Arrival Time	11.139
Data Required Time	10.831
From	inst7/inst1/adr_1_s0
To	inst7/out_3_s0
Launch Clk	leg4_clk:[R]
Latch Clk	leg4_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					leg4_clk
0.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
1.231	1.231	tNET	RR	1	R11C14[1][B]	inst7/inst1/adr_1_s0/CLK
1.689	0.458	tC2Q	RF	22	R11C14[1][B]	inst7/inst1/adr_1_s0/Q
3.032	1.343	tNET	FF	1	R9C16[1][B]	inst10/rom_out_0_s1/I0
4.064	1.032	tINS	FF	3	R9C16[1][B]	inst10/rom_out_0_s1/F
4.896	0.832	tNET	FF	2	R11C16[0][A]	inst7/inst2/n14_s/I1
5.446	0.550	tINS	FR	1	R11C16[0][A]	inst7/inst2/n14_s/COUT
5.446	0.000	tNET	RR	2	R11C16[0][B]	inst7/inst2/n13_s/CIN
5.503	0.057	tINS	RF	1	R11C16[0][B]	inst7/inst2/n13_s/COUT
5.503	0.000	tNET	FF	2	R11C16[1][A]	inst7/inst2/n12_s/CIN
5.560	0.057	tINS	FF	1	R11C16[1][A]	inst7/inst2/n12_s/COUT
6.128	0.568	tNET	FF	1	R11C16[2][B]	inst7/inst2/n15_s22/I2
7.189	1.061	tINS	FR	1	R11C16[2][B]	inst7/inst2/n15_s22/F
7.608	0.419	tNET	RR	1	R11C17[3][B]	inst7/inst2/n15_s25/I0
8.640	1.032	tINS	RF	1	R11C17[3][B]	inst7/inst2/n15_s25/F
8.640	0.000	tNET	FF	1	R11C17[3][A]	inst7/inst2/n15_s19/I1
8.789	0.149	tINS	FF	1	R11C17[3][A]	inst7/inst2/n15_s19/O
9.289	0.500	tNET	FF	1	R11C16[2][A]	inst7/inst2/data_Z_3_s/I1
10.091	0.802	tINS	FR	2	R11C16[2][A]	inst7/inst2/data_Z_3_s/F
11.139	1.048	tNET	RR	1	R12C16[1][A]	inst7/out_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					leg4_clk
10.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
11.231	1.231	tNET	RR	1	R12C16[1][A]	inst7/out_3_s0/CLK
10.831	-0.400	tSu		1	R12C16[1][A]	inst7/out_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay	cell: 4.740, 47.841%; route: 4.709, 47.533%; tC2Q: 0.458, 4.626%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%

Path3

Path Summary:

Slack	-0.214
Data Arrival Time	11.045
Data Required Time	10.831
From	inst7/inst1/adr_1_s0
To	inst7/out_1_s0
Launch Clk	leg4_clk:[R]
Latch Clk	leg4_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					leg4_clk
0.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
1.231	1.231	tNET	RR	1	R11C14[1][B]	inst7/inst1/adr_1_s0/CLK
1.689	0.458	tC2Q	RF	22	R11C14[1][B]	inst7/inst1/adr_1_s0/Q
3.032	1.343	tNET	FF	1	R9C16[1][B]	inst10/rom_out_0_s1/I0
4.064	1.032	tINS	FF	3	R9C16[1][B]	inst10/rom_out_0_s1/F
4.879	0.815	tNET	FF	2	R11C17[0][B]	inst7/inst2/n9_s/I1
5.429	0.550	tINS	FR	1	R11C17[0][B]	inst7/inst2/n9_s/COUT
5.429	0.000	tNET	RR	2	R11C17[1][A]	inst7/inst2/n8_s/CIN
5.992	0.563	tINS	RF	1	R11C17[1][A]	inst7/inst2/n8_s/SUM
6.482	0.490	tNET	FF	1	R11C15[3][A]	inst7/inst2/n17_s22/I3
7.108	0.626	tINS	FF	1	R11C15[3][A]	inst7/inst2/n17_s22/F
7.108	0.000	tNET	FF	1	R11C15[3][A]	inst7/inst2/n17_s19/I0
7.257	0.149	tINS	FF	1	R11C15[3][A]	inst7/inst2/n17_s19/O
9.040	1.783	tNET	FF	1	R11C15[0][B]	inst7/inst2/data_Z_1_s/I1
10.072	1.032	tINS	FF	2	R11C15[0][B]	inst7/inst2/data_Z_1_s/F
11.045	0.972	tNET	FF	1	R11C15[0][A]	inst7/out_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					leg4_clk
10.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
11.231	1.231	tNET	RR	1	R11C15[0][A]	inst7/out_1_s0/CLK
10.831	-0.400	tSu		1	R11C15[0][A]	inst7/out_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay	cell: 3.952, 40.271%; route: 5.403, 55.059%; tC2Q: 0.458, 4.670%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%

Path4

Path Summary:

Slack	-0.214
Data Arrival Time	11.045
Data Required Time	10.831
From	inst7/inst1/adr_1_s0
To	inst7/a_1_s0
Launch Clk	leg4_clk:[R]
Latch Clk	leg4_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					leg4_clk
0.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
1.231	1.231	tNET	RR	1	R11C14[1][B]	inst7/inst1/adr_1_s0/CLK
1.689	0.458	tC2Q	RF	22	R11C14[1][B]	inst7/inst1/adr_1_s0/Q
3.032	1.343	tNET	FF	1	R9C16[1][B]	inst10/rom_out_0_s1/I0
4.064	1.032	tINS	FF	3	R9C16[1][B]	inst10/rom_out_0_s1/F
4.879	0.815	tNET	FF	2	R11C17[0][B]	inst7/inst2/n9_s/I1
5.429	0.550	tINS	FR	1	R11C17[0][B]	inst7/inst2/n9_s/COUT
5.429	0.000	tNET	RR	2	R11C17[1][A]	inst7/inst2/n8_s/CIN
5.992	0.563	tINS	RF	1	R11C17[1][A]	inst7/inst2/n8_s/SUM
6.482	0.490	tNET	FF	1	R11C15[3][A]	inst7/inst2/n17_s22/I3
7.108	0.626	tINS	FF	1	R11C15[3][A]	inst7/inst2/n17_s22/F
7.108	0.000	tNET	FF	1	R11C15[3][A]	inst7/inst2/n17_s19/I0
7.257	0.149	tINS	FF	1	R11C15[3][A]	inst7/inst2/n17_s19/O
9.040	1.783	tNET	FF	1	R11C15[0][B]	inst7/inst2/data_Z_1_s/I1
10.072	1.032	tINS	FF	2	R11C15[0][B]	inst7/inst2/data_Z_1_s/F
11.045	0.972	tNET	FF	1	R11C15[1][A]	inst7/a_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					leg4_clk
10.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
11.231	1.231	tNET	RR	1	R11C15[1][A]	inst7/a_1_s0/CLK
10.831	-0.400	tSu		1	R11C15[1][A]	inst7/a_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay	cell: 3.952, 40.271%; route: 5.403, 55.059%; tC2Q: 0.458, 4.670%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%

Path5

Path Summary:

Slack	0.925
Data Arrival Time	9.905
Data Required Time	10.831
From	inst7/inst1/adr_1_s0
To	inst7/out_2_s0
Launch Clk	leg4_clk:[R]
Latch Clk	leg4_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					leg4_clk
0.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
1.231	1.231	tNET	RR	1	R11C14[1][B]	inst7/inst1/adr_1_s0/CLK
1.689	0.458	tC2Q	RF	22	R11C14[1][B]	inst7/inst1/adr_1_s0/Q
3.032	1.343	tNET	FF	1	R9C16[1][B]	inst10/rom_out_0_s1/I0
4.064	1.032	tINS	FF	3	R9C16[1][B]	inst10/rom_out_0_s1/F
4.879	0.815	tNET	FF	2	R11C17[0][B]	inst7/inst2/n9_s/I1
5.429	0.550	tINS	FR	1	R11C17[0][B]	inst7/inst2/n9_s/COUT
5.429	0.000	tNET	RR	2	R11C17[1][A]	inst7/inst2/n8_s/CIN
5.486	0.057	tINS	RF	1	R11C17[1][A]	inst7/inst2/n8_s/COUT
5.486	0.000	tNET	FF	2	R11C17[1][B]	inst7/inst2/n7_s/CIN
6.014	0.528	tINS	FR	1	R11C17[1][B]	inst7/inst2/n7_s/SUM
6.433	0.419	tNET	RR	1	R11C16[3][A]	inst7/inst2/n16_s22/I3
7.255	0.822	tINS	RF	1	R11C16[3][A]	inst7/inst2/n16_s22/F
7.255	0.000	tNET	FF	1	R11C16[3][A]	inst7/inst2/n16_s19/I0
7.404	0.149	tINS	FF	1	R11C16[3][A]	inst7/inst2/n16_s19/O
8.235	0.830	tNET	FF	1	R12C16[1][B]	inst7/inst2/data_Z_2_s/I1
8.860	0.625	tINS	FR	2	R12C16[1][B]	inst7/inst2/data_Z_2_s/F
9.905	1.046	tNET	RR	1	R12C15[0][B]	inst7/out_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					leg4_clk
10.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
11.231	1.231	tNET	RR	1	R12C15[0][B]	inst7/out_2_s0/CLK
10.831	-0.400	tSu		1	R12C15[0][B]	inst7/out_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay	cell: 3.763, 43.380%; route: 4.453, 51.337%; tC2Q: 0.458, 5.284%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%

Path6

Path Summary:

Slack	1.002
Data Arrival Time	9.828
Data Required Time	10.831
From	inst7/inst1/adr_1_s0
To	inst7/a_2_s0
Launch Clk	leg4_clk:[R]
Latch Clk	leg4_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					leg4_clk
0.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
1.231	1.231	tNET	RR	1	R11C14[1][B]	inst7/inst1/adr_1_s0/CLK
1.689	0.458	tC2Q	RF	22	R11C14[1][B]	inst7/inst1/adr_1_s0/Q
3.032	1.343	tNET	FF	1	R9C16[1][B]	inst10/rom_out_0_s1/I0
4.064	1.032	tINS	FF	3	R9C16[1][B]	inst10/rom_out_0_s1/F
4.879	0.815	tNET	FF	2	R11C17[0][B]	inst7/inst2/n9_s/I1
5.429	0.550	tINS	FR	1	R11C17[0][B]	inst7/inst2/n9_s/COUT
5.429	0.000	tNET	RR	2	R11C17[1][A]	inst7/inst2/n8_s/CIN
5.486	0.057	tINS	RF	1	R11C17[1][A]	inst7/inst2/n8_s/COUT
5.486	0.000	tNET	FF	2	R11C17[1][B]	inst7/inst2/n7_s/CIN
6.014	0.528	tINS	FR	1	R11C17[1][B]	inst7/inst2/n7_s/SUM
6.433	0.419	tNET	RR	1	R11C16[3][A]	inst7/inst2/n16_s22/I3
7.255	0.822	tINS	RF	1	R11C16[3][A]	inst7/inst2/n16_s22/F
7.255	0.000	tNET	FF	1	R11C16[3][A]	inst7/inst2/n16_s19/I0
7.404	0.149	tINS	FF	1	R11C16[3][A]	inst7/inst2/n16_s19/O
8.235	0.830	tNET	FF	1	R12C16[1][B]	inst7/inst2/data_Z_2_s/I1
8.861	0.626	tINS	FF	2	R12C16[1][B]	inst7/inst2/data_Z_2_s/F
9.828	0.968	tNET	FF	1	R12C16[0][A]	inst7/a_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					leg4_clk
10.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
11.231	1.231	tNET	RR	1	R12C16[0][A]	inst7/a_2_s0/CLK
10.831	-0.400	tSu		1	R12C16[0][A]	inst7/a_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay	cell: 3.764, 43.780%; route: 4.375, 50.889%; tC2Q: 0.458, 5.331%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%

Path7

Path Summary:

Slack	1.078
Data Arrival Time	11.193
Data Required Time	12.272
From	inst5/count_19_s0
To	inst6/out_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
10.094	1.322	tNET	FF	1	R12C27[0][A]	inst6/n9_s0/I0
11.193	1.099	tINS	FF	1	R12C27[0][A]	inst6/n9_s0/F
11.193	0.000	tNET	FF	1	R12C27[0][A]	inst6/out_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R12C27[0][A]	inst6/out_s0/CLK
12.272	-0.400	tSu		1	R12C27[0][A]	inst6/out_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.119, 48.336%; route: 3.944, 46.286%; tC2Q: 0.458, 5.378%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path8

Path Summary:

Slack	1.118
Data Arrival Time	9.713
Data Required Time	10.831
From	inst7/inst1/adr_1_s0
To	inst7/out_0_s0
Launch Clk	leg4_clk:[R]
Latch Clk	leg4_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					leg4_clk
0.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
1.231	1.231	tNET	RR	1	R11C14[1][B]	inst7/inst1/adr_1_s0/CLK
1.689	0.458	tC2Q	RF	22	R11C14[1][B]	inst7/inst1/adr_1_s0/Q
3.032	1.343	tNET	FF	1	R9C16[1][B]	inst10/rom_out_0_s1/I0
4.064	1.032	tINS	FF	3	R9C16[1][B]	inst10/rom_out_0_s1/F
4.879	0.815	tNET	FF	2	R11C17[0][B]	inst7/inst2/n9_s/I1
5.580	0.701	tINS	FR	1	R11C17[0][B]	inst7/inst2/n9_s/SUM
6.367	0.786	tNET	RR	1	R9C16[3][A]	inst7/inst2/n18_s22/I3
7.466	1.099	tINS	RF	1	R9C16[3][A]	inst7/inst2/n18_s22/F
7.466	0.000	tNET	FF	1	R9C16[3][A]	inst7/inst2/n18_s19/I0
7.615	0.149	tINS	FF	1	R9C16[3][A]	inst7/inst2/n18_s19/O
8.114	0.500	tNET	FF	1	R9C16[2][A]	inst7/inst2/data_Z_0_s/I1
8.740	0.626	tINS	FF	2	R9C16[2][A]	inst7/inst2/data_Z_0_s/F
9.713	0.972	tNET	FF	1	R9C16[0][A]	inst7/out_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					leg4_clk
10.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
11.231	1.231	tNET	RR	1	R9C16[0][A]	inst7/out_0_s0/CLK
10.831	-0.400	tSu		1	R9C16[0][A]	inst7/out_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay	cell: 3.607, 42.527%; route: 4.416, 52.069%; tC2Q: 0.458, 5.404%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%

Path9

Path Summary:

Slack	1.118
Data Arrival Time	9.713
Data Required Time	10.831
From	inst7/inst1/adr_1_s0
To	inst7/a_0_s0
Launch Clk	leg4_clk:[R]
Latch Clk	leg4_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					leg4_clk
0.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
1.231	1.231	tNET	RR	1	R11C14[1][B]	inst7/inst1/adr_1_s0/CLK
1.689	0.458	tC2Q	RF	22	R11C14[1][B]	inst7/inst1/adr_1_s0/Q
3.032	1.343	tNET	FF	1	R9C16[1][B]	inst10/rom_out_0_s1/I0
4.064	1.032	tINS	FF	3	R9C16[1][B]	inst10/rom_out_0_s1/F
4.879	0.815	tNET	FF	2	R11C17[0][B]	inst7/inst2/n9_s/I1
5.580	0.701	tINS	FR	1	R11C17[0][B]	inst7/inst2/n9_s/SUM
6.367	0.786	tNET	RR	1	R9C16[3][A]	inst7/inst2/n18_s22/I3
7.466	1.099	tINS	RF	1	R9C16[3][A]	inst7/inst2/n18_s22/F
7.466	0.000	tNET	FF	1	R9C16[3][A]	inst7/inst2/n18_s19/I0
7.615	0.149	tINS	FF	1	R9C16[3][A]	inst7/inst2/n18_s19/O
8.114	0.500	tNET	FF	1	R9C16[2][A]	inst7/inst2/data_Z_0_s/I1
8.740	0.626	tINS	FF	2	R9C16[2][A]	inst7/inst2/data_Z_0_s/F
9.713	0.972	tNET	FF	1	R9C16[1][A]	inst7/a_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					leg4_clk
10.000	0.000	tCL	RR	13	R12C24[1][A]	leg4_clk_s4/F
11.231	1.231	tNET	RR	1	R9C16[1][A]	inst7/a_0_s0/CLK
10.831	-0.400	tSu		1	R9C16[1][A]	inst7/a_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%
Arrival Data Path Delay	cell: 3.607, 42.527%; route: 4.416, 52.069%; tC2Q: 0.458, 5.404%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.231, 100.000%

Path10

Path Summary:

Slack	1.312
Data Arrival Time	10.960
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
10.138	1.366	tNET	FF	1	R11C27[0][B]	inst5/n38_s1/I0
10.960	0.822	tINS	FF	1	R11C27[0][B]	inst5/n38_s1/F
10.960	0.000	tNET	FF	1	R11C27[0][B]	inst5/count_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C27[0][B]	inst5/count_17_s0/CLK
12.272	-0.400	tSu		1	R11C27[0][B]	inst5/count_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 3.842, 46.354%; route: 3.988, 48.117%; tC2Q: 0.458, 5.530%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path11

Path Summary:

Slack	1.432
Data Arrival Time	10.839
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.807	1.035	tNET	FF	1	R11C27[0][A]	inst5/n43_s1/I0
10.839	1.032	tINS	FF	1	R11C27[0][A]	inst5/n43_s1/F
10.839	0.000	tNET	FF	1	R11C27[0][A]	inst5/count_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C27[0][A]	inst5/count_12_s0/CLK
12.272	-0.400	tSu		1	R11C27[0][A]	inst5/count_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.052, 49.610%; route: 3.657, 44.778%; tC2Q: 0.458, 5.612%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path12

Path Summary:

Slack	1.551
Data Arrival Time	10.720
Data Required Time	12.272
From	inst5/count_19_s0
To	inst6/prev_in_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
10.720	1.948	tNET	FF	1	R12C27[0][B]	inst6/prev_in_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R12C27[0][B]	inst6/prev_in_s0/CLK
12.272	-0.400	tSu		1	R12C27[0][B]	inst6/prev_in_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 3.020, 37.522%; route: 4.570, 56.783%; tC2Q: 0.458, 5.695%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path13

Path Summary:

Slack	1.610
Data Arrival Time	10.662
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.630	0.858	tNET	FF	1	R11C30[1][A]	inst5/n55_s1/I1
10.662	1.032	tINS	FF	1	R11C30[1][A]	inst5/n55_s1/F
10.662	0.000	tNET	FF	1	R11C30[1][A]	inst5/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C30[1][A]	inst5/count_0_s0/CLK
12.272	-0.400	tSu		1	R11C30[1][A]	inst5/count_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.052, 50.710%; route: 3.480, 43.554%; tC2Q: 0.458, 5.736%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path14

Path Summary:

Slack	1.610
Data Arrival Time	10.662
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.630	0.858	tNET	FF	1	R11C30[0][B]	inst5/n42_s1/I0
10.662	1.032	tINS	FF	1	R11C30[0][B]	inst5/n42_s1/F
10.662	0.000	tNET	FF	1	R11C30[0][B]	inst5/count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C30[0][B]	inst5/count_13_s0/CLK
12.272	-0.400	tSu		1	R11C30[0][B]	inst5/count_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.052, 50.710%; route: 3.480, 43.554%; tC2Q: 0.458, 5.736%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path15

Path Summary:

Slack	1.610
Data Arrival Time	10.662
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.630	0.858	tNET	FF	1	R11C30[0][A]	inst5/n37_s1/I2
10.662	1.032	tINS	FF	1	R11C30[0][A]	inst5/n37_s1/F
10.662	0.000	tNET	FF	1	R11C30[0][A]	inst5/count_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C30[0][A]	inst5/count_18_s0/CLK
12.272	-0.400	tSu		1	R11C30[0][A]	inst5/count_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.052, 50.710%; route: 3.480, 43.554%; tC2Q: 0.458, 5.736%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path16

Path Summary:

Slack	1.630
Data Arrival Time	10.642
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.610	0.837	tNET	FF	1	R11C28[0][B]	inst5/n52_s1/I0
10.642	1.032	tINS	FF	1	R11C28[0][B]	inst5/n52_s1/F
10.642	0.000	tNET	FF	1	R11C28[0][B]	inst5/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C28[0][B]	inst5/count_3_s0/CLK
12.272	-0.400	tSu		1	R11C28[0][B]	inst5/count_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.052, 50.840%; route: 3.460, 43.409%; tC2Q: 0.458, 5.751%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path17

Path Summary:

Slack	1.692
Data Arrival Time	10.579
Data Required Time	12.272
From	inst1/clkdiv_1/count_1_s0
To	inst1/clkdiv_1/count_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R11C24[0][B]	inst1/clkdiv_1/count_1_s0/CLK
3.130	0.458	tC2Q	RF	4	R11C24[0][B]	inst1/clkdiv_1/count_1_s0/Q
4.282	1.152	tNET	FF	1	R11C25[1][B]	inst1/clkdiv_1/n51_s2/I0
5.381	1.099	tINS	FF	5	R11C25[1][B]	inst1/clkdiv_1/n51_s2/F
6.218	0.837	tNET	FF	1	R9C26[3][A]	inst1/clkdiv_1/n48_s2/I3
7.250	1.032	tINS	FF	5	R9C26[3][A]	inst1/clkdiv_1/n48_s2/F
8.066	0.815	tNET	FF	1	R11C25[3][A]	inst1/clkdiv_1/n42_s2/I3
9.127	1.061	tINS	FR	2	R11C25[3][A]	inst1/clkdiv_1/n42_s2/F
9.547	0.421	tNET	RR	1	R11C24[2][A]	inst1/clkdiv_1/n42_s1/I2
10.579	1.032	tINS	RF	1	R11C24[2][A]	inst1/clkdiv_1/n42_s1/F
10.579	0.000	tNET	FF	1	R11C24[2][A]	inst1/clkdiv_1/count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C24[2][A]	inst1/clkdiv_1/count_13_s0/CLK
12.272	-0.400	tSu		1	R11C24[2][A]	inst1/clkdiv_1/count_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.224, 53.416%; route: 3.225, 40.788%; tC2Q: 0.458, 5.796%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path18

Path Summary:

Slack	1.813
Data Arrival Time	10.459
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.637	0.864	tNET	FF	1	R11C28[0][A]	inst5/n45_s1/I2
10.459	0.822	tINS	FF	1	R11C28[0][A]	inst5/n45_s1/F
10.459	0.000	tNET	FF	1	R11C28[0][A]	inst5/count_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C28[0][A]	inst5/count_10_s0/CLK
12.272	-0.400	tSu		1	R11C28[0][A]	inst5/count_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 3.842, 49.337%; route: 3.487, 44.777%; tC2Q: 0.458, 5.886%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path19

Path Summary:

Slack	1.813
Data Arrival Time	10.459
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.637	0.864	tNET	FF	1	R11C28[1][A]	inst5/n44_s1/I2
10.459	0.822	tINS	FF	1	R11C28[1][A]	inst5/n44_s1/F
10.459	0.000	tNET	FF	1	R11C28[1][A]	inst5/count_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C28[1][A]	inst5/count_11_s0/CLK
12.272	-0.400	tSu		1	R11C28[1][A]	inst5/count_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 3.842, 49.337%; route: 3.487, 44.777%; tC2Q: 0.458, 5.886%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path20

Path Summary:

Slack	1.832
Data Arrival Time	10.440
Data Required Time	12.272
From	inst5/count_1_s0
To	inst5/count_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C30[2][A]	inst5/count_1_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C30[2][A]	inst5/count_1_s0/Q
4.116	0.986	tNET	FF	1	R11C28[2][B]	inst5/n51_s2/I0
4.938	0.822	tINS	FF	7	R11C28[2][B]	inst5/n51_s2/F
5.774	0.836	tNET	FF	1	R9C28[0][A]	inst5/n42_s2/I1
6.873	1.099	tINS	FF	9	R9C28[0][A]	inst5/n42_s2/F
7.698	0.824	tNET	FF	1	R11C27[1][A]	inst5/n39_s3/I1
8.797	1.099	tINS	FF	1	R11C27[1][A]	inst5/n39_s3/F
9.618	0.821	tNET	FF	1	R9C27[0][A]	inst5/n39_s1/I1
10.440	0.822	tINS	FF	1	R9C27[0][A]	inst5/n39_s1/F
10.440	0.000	tNET	FF	1	R9C27[0][A]	inst5/count_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R9C27[0][A]	inst5/count_16_s0/CLK
12.272	-0.400	tSu		1	R9C27[0][A]	inst5/count_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 3.842, 49.460%; route: 3.468, 44.640%; tC2Q: 0.458, 5.900%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path21

Path Summary:

Slack	1.859
Data Arrival Time	10.413
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.314	0.541	tNET	FF	1	R11C29[2][A]	inst5/n51_s1/I0
10.413	1.099	tINS	FF	1	R11C29[2][A]	inst5/n51_s1/F
10.413	0.000	tNET	FF	1	R11C29[2][A]	inst5/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C29[2][A]	inst5/count_4_s0/CLK
12.272	-0.400	tSu		1	R11C29[2][A]	inst5/count_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.119, 53.210%; route: 3.164, 40.869%; tC2Q: 0.458, 5.921%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path22

Path Summary:

Slack	1.902
Data Arrival Time	10.369
Data Required Time	12.272
From	inst1/clkdiv_1/count_1_s0
To	inst1/clkdiv_1/count_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R11C24[0][B]	inst1/clkdiv_1/count_1_s0/CLK
3.130	0.458	tC2Q	RF	4	R11C24[0][B]	inst1/clkdiv_1/count_1_s0/Q
4.282	1.152	tNET	FF	1	R11C25[1][B]	inst1/clkdiv_1/n51_s2/I0
5.381	1.099	tINS	FF	5	R11C25[1][B]	inst1/clkdiv_1/n51_s2/F
6.218	0.837	tNET	FF	1	R9C26[3][A]	inst1/clkdiv_1/n48_s2/I3
7.250	1.032	tINS	FF	5	R9C26[3][A]	inst1/clkdiv_1/n48_s2/F
8.066	0.815	tNET	FF	1	R11C25[3][A]	inst1/clkdiv_1/n42_s2/I3
9.127	1.061	tINS	FR	2	R11C25[3][A]	inst1/clkdiv_1/n42_s2/F
9.547	0.421	tNET	RR	1	R11C24[0][A]	inst1/clkdiv_1/n41_s1/I1
10.369	0.822	tINS	RF	1	R11C24[0][A]	inst1/clkdiv_1/n41_s1/F
10.369	0.000	tNET	FF	1	R11C24[0][A]	inst1/clkdiv_1/count_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R11C24[0][A]	inst1/clkdiv_1/count_14_s0/CLK
12.272	-0.400	tSu		1	R11C24[0][A]	inst1/clkdiv_1/count_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.014, 52.145%; route: 3.225, 41.901%; tC2Q: 0.458, 5.954%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path23

Path Summary:

Slack	1.921
Data Arrival Time	10.350
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.318	0.546	tNET	FF	1	R9C27[1][B]	inst5/n46_s1/I0
10.350	1.032	tINS	FF	1	R9C27[1][B]	inst5/n46_s1/F
10.350	0.000	tNET	FF	1	R9C27[1][B]	inst5/count_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R9C27[1][B]	inst5/count_9_s0/CLK
12.272	-0.400	tSu		1	R9C27[1][B]	inst5/count_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.052, 52.770%; route: 3.168, 41.261%; tC2Q: 0.458, 5.969%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path24

Path Summary:

Slack	1.921
Data Arrival Time	10.350
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.318	0.546	tNET	FF	1	R9C27[0][B]	inst5/n36_s1/I0
10.350	1.032	tINS	FF	1	R9C27[0][B]	inst5/n36_s1/F
10.350	0.000	tNET	FF	1	R9C27[0][B]	inst5/count_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
12.272	-0.400	tSu		1	R9C27[0][B]	inst5/count_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.052, 52.770%; route: 3.168, 41.261%; tC2Q: 0.458, 5.969%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Path25

Path Summary:

Slack	1.921
Data Arrival Time	10.350
Data Required Time	12.272
From	inst5/count_19_s0
To	inst5/count_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.672	1.690	tNET	RR	1	R9C27[0][B]	inst5/count_19_s0/CLK
3.130	0.458	tC2Q	RF	4	R9C27[0][B]	inst5/count_19_s0/Q
3.953	0.822	tNET	FF	1	R9C30[1][A]	inst5/tc1hz_s8/I1
5.052	1.099	tINS	FF	2	R9C30[1][A]	inst5/tc1hz_s8/F
6.031	0.979	tNET	FF	1	R9C27[2][B]	inst5/tc1hz_s3/I0
7.130	1.099	tINS	FF	1	R9C27[2][B]	inst5/tc1hz_s3/F
7.951	0.821	tNET	FF	1	R9C29[2][B]	inst5/tc1hz_s/I3
8.773	0.822	tINS	FF	25	R9C29[2][B]	inst5/tc1hz_s/F
9.318	0.546	tNET	FF	1	R9C27[2][A]	inst5/n34_s1/I0
10.350	1.032	tINS	FF	1	R9C27[2][A]	inst5/n34_s1/F
10.350	0.000	tNET	FF	1	R9C27[2][A]	inst5/count_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	89	IOL3[A]	clk_ibuf/O
12.672	1.690	tNET	RR	1	R9C27[2][A]	inst5/count_21_s0/CLK
12.272	-0.400	tSu		1	R9C27[2][A]	inst5/count_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%
Arrival Data Path Delay	cell: 4.052, 52.770%; route: 3.168, 41.261%; tC2Q: 0.458, 5.969%
Required Clock Path Delay	cell: 0.982, 36.750%; route: 1.690, 63.250%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.358
Data Arrival Time	0.727
Data Required Time	2.085
From	inst1/clkdiv_1/n44_s1
To	inst1/clkdiv_1/count_11_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
0.003	0.003	tNET	RR	1	R9C26[0][B]	inst1/clkdiv_1/n44_s1/I0
0.727	0.724	tINS	RR	1	R9C26[0][B]	inst1/clkdiv_1/n44_s1/F
0.727	0.000	tNET	RR	1	R9C26[0][B]	inst1/clkdiv_1/count_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C26[0][B]	inst1/clkdiv_1/count_11_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_11_s0
2.085	0.000	tHld		1	R9C26[0][B]	inst1/clkdiv_1/count_11_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 99.564%; route: 0.000, 0.000%; tC2Q: 0.003, 0.436%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path2

Path Summary:

Slack	-0.654
Data Arrival Time	1.446
Data Required Time	2.100
From	inst15/i4/count_0_s0
To	inst15/i4/count_0_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.446	1.446	tNET	RR	1	R11C10[0][A]	inst15/i4/count_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C10[0][A]	inst15/i4/count_0_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_0_s0
2.100	0.015	tHld		1	R11C10[0][A]	inst15/i4/count_0_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.446, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path3

Path Summary:

Slack	-0.650
Data Arrival Time	1.450
Data Required Time	2.100
From	inst15/i4/count_7_s0
To	inst15/i4/count_7_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.450	1.450	tNET	RR	1	R9C10[0][A]	inst15/i4/count_7_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C10[0][A]	inst15/i4/count_7_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_7_s0
2.100	0.015	tHld		1	R9C10[0][A]	inst15/i4/count_7_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.450, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path4

Path Summary:

Slack	-0.650
Data Arrival Time	1.450
Data Required Time	2.100
From	inst15/i4/count_8_s0
To	inst15/i4/count_8_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.450	1.450	tNET	RR	1	R9C10[0][B]	inst15/i4/count_8_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C10[0][B]	inst15/i4/count_8_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_8_s0
2.100	0.015	tHld		1	R9C10[0][B]	inst15/i4/count_8_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.450, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path5

Path Summary:

Slack	-0.650
Data Arrival Time	1.450
Data Required Time	2.100
From	inst15/i4/count_9_s0
To	inst15/i4/count_9_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.450	1.450	tNET	RR	1	R9C10[1][A]	inst15/i4/count_9_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C10[1][A]	inst15/i4/count_9_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_9_s0
2.100	0.015	tHld		1	R9C10[1][A]	inst15/i4/count_9_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.450, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path6

Path Summary:

Slack	-0.650
Data Arrival Time	1.450
Data Required Time	2.100
From	inst15/i4/count_10_s0
To	inst15/i4/count_10_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.450	1.450	tNET	RR	1	R9C10[1][B]	inst15/i4/count_10_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C10[1][B]	inst15/i4/count_10_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_10_s0
2.100	0.015	tHld		1	R9C10[1][B]	inst15/i4/count_10_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.450, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path7

Path Summary:

Slack	-0.647
Data Arrival Time	1.453
Data Required Time	2.100
From	inst15/i4/count_1_s0
To	inst15/i4/count_1_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.453	1.453	tNET	RR	1	R9C9[0][A]	inst15/i4/count_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C9[0][A]	inst15/i4/count_1_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_1_s0
2.100	0.015	tHld		1	R9C9[0][A]	inst15/i4/count_1_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path8

Path Summary:

Slack	-0.647
Data Arrival Time	1.453
Data Required Time	2.100
From	inst15/i4/count_2_s0
To	inst15/i4/count_2_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.453	1.453	tNET	RR	1	R9C9[0][B]	inst15/i4/count_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C9[0][B]	inst15/i4/count_2_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_2_s0
2.100	0.015	tHld		1	R9C9[0][B]	inst15/i4/count_2_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path9

Path Summary:

Slack	-0.647
Data Arrival Time	1.453
Data Required Time	2.100
From	inst15/i4/count_3_s0
To	inst15/i4/count_3_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.453	1.453	tNET	RR	1	R9C9[1][A]	inst15/i4/count_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C9[1][A]	inst15/i4/count_3_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_3_s0
2.100	0.015	tHld		1	R9C9[1][A]	inst15/i4/count_3_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path10

Path Summary:

Slack	-0.647
Data Arrival Time	1.453
Data Required Time	2.100
From	inst15/i4/count_4_s0
To	inst15/i4/count_4_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.453	1.453	tNET	RR	1	R9C9[1][B]	inst15/i4/count_4_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C9[1][B]	inst15/i4/count_4_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_4_s0
2.100	0.015	tHld		1	R9C9[1][B]	inst15/i4/count_4_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path11

Path Summary:

Slack	-0.647
Data Arrival Time	1.453
Data Required Time	2.100
From	inst15/i4/count_5_s0
To	inst15/i4/count_5_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.453	1.453	tNET	RR	1	R9C9[2][A]	inst15/i4/count_5_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C9[2][A]	inst15/i4/count_5_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_5_s0
2.100	0.015	tHld		1	R9C9[2][A]	inst15/i4/count_5_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path12

Path Summary:

Slack	-0.647
Data Arrival Time	1.453
Data Required Time	2.100
From	inst15/i4/count_6_s0
To	inst15/i4/count_6_s0
Launch Clk	inst15/clk10KHz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst15/clk10KHz
0.000	0.000	tCL	RR	14	R9C10[2][B]	inst15/i4/clk10KHz_s/F
1.453	1.453	tNET	RR	1	R9C9[2][B]	inst15/i4/count_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C9[2][B]	inst15/i4/count_6_s0/CLK
2.085	0.030	tUnc				inst15/i4/count_6_s0
2.100	0.015	tHld		1	R9C9[2][B]	inst15/i4/count_6_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.453, 100.000%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path13

Path Summary:

Slack	-0.529
Data Arrival Time	1.556
Data Required Time	2.085
From	inst1/clkdiv_1/n47_s1
To	inst1/clkdiv_1/count_8_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.184	1.184	tNET	RR	1	R9C24[0][B]	inst1/clkdiv_1/n47_s1/I2
1.556	0.372	tINS	RF	1	R9C24[0][B]	inst1/clkdiv_1/n47_s1/F
1.556	0.000	tNET	FF	1	R9C24[0][B]	inst1/clkdiv_1/count_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C24[0][B]	inst1/clkdiv_1/count_8_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_8_s0
2.085	0.000	tHld		1	R9C24[0][B]	inst1/clkdiv_1/count_8_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 23.913%; route: 0.000, 0.000%; tC2Q: 1.184, 76.087%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path14

Path Summary:

Slack	-0.528
Data Arrival Time	1.557
Data Required Time	2.085
From	inst1/clkdiv_1/n54_s1
To	inst1/clkdiv_1/count_1_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.185	1.185	tNET	RR	1	R11C24[0][B]	inst1/clkdiv_1/n54_s1/I0
1.557	0.372	tINS	RF	1	R11C24[0][B]	inst1/clkdiv_1/n54_s1/F
1.557	0.000	tNET	FF	1	R11C24[0][B]	inst1/clkdiv_1/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C24[0][B]	inst1/clkdiv_1/count_1_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_1_s0
2.085	0.000	tHld		1	R11C24[0][B]	inst1/clkdiv_1/count_1_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 23.890%; route: 0.000, 0.000%; tC2Q: 1.185, 76.110%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path15

Path Summary:

Slack	-0.528
Data Arrival Time	1.557
Data Required Time	2.085
From	inst1/clkdiv_1/n52_s1
To	inst1/clkdiv_1/count_3_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.185	1.185	tNET	RR	1	R11C26[1][B]	inst1/clkdiv_1/n52_s1/I0
1.557	0.372	tINS	RF	1	R11C26[1][B]	inst1/clkdiv_1/n52_s1/F
1.557	0.000	tNET	FF	1	R11C26[1][B]	inst1/clkdiv_1/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C26[1][B]	inst1/clkdiv_1/count_3_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_3_s0
2.085	0.000	tHld		1	R11C26[1][B]	inst1/clkdiv_1/count_3_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 23.890%; route: 0.000, 0.000%; tC2Q: 1.185, 76.110%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path16

Path Summary:

Slack	-0.528
Data Arrival Time	1.557
Data Required Time	2.085
From	inst1/clkdiv_1/n50_s1
To	inst1/clkdiv_1/count_5_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.185	1.185	tNET	RR	1	R11C26[0][B]	inst1/clkdiv_1/n50_s1/I2
1.557	0.372	tINS	RF	1	R11C26[0][B]	inst1/clkdiv_1/n50_s1/F
1.557	0.000	tNET	FF	1	R11C26[0][B]	inst1/clkdiv_1/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C26[0][B]	inst1/clkdiv_1/count_5_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_5_s0
2.085	0.000	tHld		1	R11C26[0][B]	inst1/clkdiv_1/count_5_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 23.890%; route: 0.000, 0.000%; tC2Q: 1.185, 76.110%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path17

Path Summary:

Slack	-0.528
Data Arrival Time	1.557
Data Required Time	2.085
From	inst1/clkdiv_1/n45_s1
To	inst1/clkdiv_1/count_10_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.185	1.185	tNET	RR	1	R11C24[1][B]	inst1/clkdiv_1/n45_s1/I2
1.557	0.372	tINS	RF	1	R11C24[1][B]	inst1/clkdiv_1/n45_s1/F
1.557	0.000	tNET	FF	1	R11C24[1][B]	inst1/clkdiv_1/count_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C24[1][B]	inst1/clkdiv_1/count_10_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_10_s0
2.085	0.000	tHld		1	R11C24[1][B]	inst1/clkdiv_1/count_10_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 23.890%; route: 0.000, 0.000%; tC2Q: 1.185, 76.110%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path18

Path Summary:

Slack	-0.528
Data Arrival Time	1.557
Data Required Time	2.085
From	inst1/clkdiv_1/n43_s1
To	inst1/clkdiv_1/count_12_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.185	1.185	tNET	RR	1	R11C25[2][A]	inst1/clkdiv_1/n43_s1/I2
1.557	0.372	tINS	RF	1	R11C25[2][A]	inst1/clkdiv_1/n43_s1/F
1.557	0.000	tNET	FF	1	R11C25[2][A]	inst1/clkdiv_1/count_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C25[2][A]	inst1/clkdiv_1/count_12_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_12_s0
2.085	0.000	tHld		1	R11C25[2][A]	inst1/clkdiv_1/count_12_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 23.890%; route: 0.000, 0.000%; tC2Q: 1.185, 76.110%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path19

Path Summary:

Slack	-0.525
Data Arrival Time	1.560
Data Required Time	2.085
From	inst1/clkdiv_1/n46_s1
To	inst1/clkdiv_1/count_9_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.188	1.188	tNET	RR	1	R11C24[2][B]	inst1/clkdiv_1/n46_s1/I0
1.560	0.372	tINS	RF	1	R11C24[2][B]	inst1/clkdiv_1/n46_s1/F
1.560	0.000	tNET	FF	1	R11C24[2][B]	inst1/clkdiv_1/count_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C24[2][B]	inst1/clkdiv_1/count_9_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_9_s0
2.085	0.000	tHld		1	R11C24[2][B]	inst1/clkdiv_1/count_9_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 23.846%; route: 0.000, 0.000%; tC2Q: 1.188, 76.154%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path20

Path Summary:

Slack	-0.525
Data Arrival Time	1.560
Data Required Time	2.085
From	inst1/clkdiv_1/n42_s1
To	inst1/clkdiv_1/count_13_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.188	1.188	tNET	RR	1	R11C24[2][A]	inst1/clkdiv_1/n42_s1/I0
1.560	0.372	tINS	RF	1	R11C24[2][A]	inst1/clkdiv_1/n42_s1/F
1.560	0.000	tNET	FF	1	R11C24[2][A]	inst1/clkdiv_1/count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C24[2][A]	inst1/clkdiv_1/count_13_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_13_s0
2.085	0.000	tHld		1	R11C24[2][A]	inst1/clkdiv_1/count_13_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 23.846%; route: 0.000, 0.000%; tC2Q: 1.188, 76.154%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path21

Path Summary:

Slack	-0.177
Data Arrival Time	1.908
Data Required Time	2.085
From	inst1/clkdiv_1/n48_s1
To	inst1/clkdiv_1/count_7_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.184	1.184	tNET	RR	1	R9C24[0][A]	inst1/clkdiv_1/n48_s1/I0
1.908	0.724	tINS	RR	1	R9C24[0][A]	inst1/clkdiv_1/n48_s1/F
1.908	0.000	tNET	RR	1	R9C24[0][A]	inst1/clkdiv_1/count_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R9C24[0][A]	inst1/clkdiv_1/count_7_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_7_s0
2.085	0.000	tHld		1	R9C24[0][A]	inst1/clkdiv_1/count_7_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 37.952%; route: 0.000, 0.000%; tC2Q: 1.184, 62.048%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path22

Path Summary:

Slack	-0.176
Data Arrival Time	1.909
Data Required Time	2.085
From	inst1/clkdiv_1/n53_s1
To	inst1/clkdiv_1/count_2_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.185	1.185	tNET	RR	1	R11C25[1][A]	inst1/clkdiv_1/n53_s1/I2
1.909	0.724	tINS	RR	1	R11C25[1][A]	inst1/clkdiv_1/n53_s1/F
1.909	0.000	tNET	RR	1	R11C25[1][A]	inst1/clkdiv_1/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C25[1][A]	inst1/clkdiv_1/count_2_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_2_s0
2.085	0.000	tHld		1	R11C25[1][A]	inst1/clkdiv_1/count_2_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 37.923%; route: 0.000, 0.000%; tC2Q: 1.185, 62.077%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path23

Path Summary:

Slack	-0.174
Data Arrival Time	1.911
Data Required Time	2.085
From	inst1/clkdiv_1/n51_s1
To	inst1/clkdiv_1/count_4_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.185	1.185	tNET	RR	1	R11C26[0][A]	inst1/clkdiv_1/n51_s1/I0
1.911	0.726	tINS	RR	1	R11C26[0][A]	inst1/clkdiv_1/n51_s1/F
1.911	0.000	tNET	RR	1	R11C26[0][A]	inst1/clkdiv_1/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C26[0][A]	inst1/clkdiv_1/count_4_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_4_s0
2.085	0.000	tHld		1	R11C26[0][A]	inst1/clkdiv_1/count_4_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.726, 37.988%; route: 0.000, 0.000%; tC2Q: 1.185, 62.012%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path24

Path Summary:

Slack	-0.174
Data Arrival Time	1.911
Data Required Time	2.085
From	inst1/clkdiv_1/n49_s1
To	inst1/clkdiv_1/count_6_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.185	1.185	tNET	RR	1	R11C26[1][A]	inst1/clkdiv_1/n49_s1/I0
1.911	0.726	tINS	RR	1	R11C26[1][A]	inst1/clkdiv_1/n49_s1/F
1.911	0.000	tNET	RR	1	R11C26[1][A]	inst1/clkdiv_1/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C26[1][A]	inst1/clkdiv_1/count_6_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_6_s0
2.085	0.000	tHld		1	R11C26[1][A]	inst1/clkdiv_1/count_6_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.726, 37.988%; route: 0.000, 0.000%; tC2Q: 1.185, 62.012%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Path25

Path Summary:

Slack	-0.173
Data Arrival Time	1.912
Data Required Time	2.085
From	inst1/clkdiv_1/n55_s1
To	inst1/clkdiv_1/count_0_s0
Launch Clk	inst1/clk400Hz:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst1/clk400Hz
0.000	0.000	tCL	RR	19	R9C26[1][B]	inst1/clkdiv_1/clk400Hz_s/F
1.188	1.188	tNET	RR	1	R11C24[1][A]	inst1/clkdiv_1/n55_s1/I1
1.912	0.724	tINS	RR	1	R11C24[1][A]	inst1/clkdiv_1/n55_s1/F
1.912	0.000	tNET	RR	1	R11C24[1][A]	inst1/clkdiv_1/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	89	IOL3[A]	clk_ibuf/O
2.055	1.211	tNET	RR	1	R11C24[1][A]	inst1/clkdiv_1/count_0_s0/CLK
2.085	0.030	tUnc				inst1/clkdiv_1/count_0_s0
2.085	0.000	tHld		1	R11C24[1][A]	inst1/clkdiv_1/count_0_s0

Path Statistics:

Clock Skew	2.055
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.724, 37.865%; route: 0.000, 0.000%; tC2Q: 1.188, 62.135%
Required Clock Path Delay	cell: 0.844, 41.090%; route: 1.211, 58.910%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst1/clkdiv_1/count_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst1/clkdiv_1/count_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst1/clkdiv_1/count_14_s0/CLK

MPW2

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst1/clkdiv_1/count_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst1/clkdiv_1/count_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst1/clkdiv_1/count_12_s0/CLK

MPW3

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst1/clkdiv_1/count_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst1/clkdiv_1/count_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst1/clkdiv_1/count_8_s0/CLK

MPW4

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst1/clkdiv_1/count_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst1/clkdiv_1/count_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst1/clkdiv_1/count_0_s0/CLK

MPW5

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst2/count_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst2/count_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst2/count_4_s0/CLK

MPW6

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst8/count_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst8/count_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst8/count_12_s0/CLK

MPW7

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst6/out_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst6/out_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst6/out_s0/CLK

MPW8

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst2/count_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst2/count_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst2/count_5_s0/CLK

MPW9

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst6/prev_in_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst6/prev_in_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst6/prev_in_s0/CLK

MPW10

MPW Summary:

Slack:	2.991
Actual Width:	4.241
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	inst5/count_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.814	1.830	tNET	FF	inst5/count_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
12.055	1.211	tNET	RR	inst5/count_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
89	clk_d	1.078	2.314
26	address[2]	-0.084	1.681
25	tc1hz	1.078	1.948
22	address[1]	-0.308	1.343
22	address[3]	0.332	1.499
21	n9_4	2.557	1.344
20	seg_no[1]	7.811	1.356
19	clk400Hz	4.301	1.842
19	address[0]	-0.030	1.510
18	tc10hz_5	4.663	1.837

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C14	50.00%
R12C16	33.33%
R11C15	31.94%
R9C16	30.56%
R9C28	30.56%
R11C11	27.78%
R11C16	27.78%
R9C29	26.39%
R12C15	25.00%
R12C21	25.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command