Synthesis Messages

Report Title	GowinSynthesis Report
Design File	C:\Gowin\Workspace\matrix_key\src\clkdiv.v C:\Gowin\Workspace\matrix_key\src\dec16to4.v C:\Gowin\Workspace\matrix_key\src\drv7seg.v C:\Gowin\Workspace\matrix_key\src\matrix_key.v C:\Gowin\Workspace\matrix_key\src\mux7seg.v C:\Gowin\Workspace\matrix_key\src\test_matrix_key.v
GowinSynthesis Constraints File	---
GowinSynthesis Version	GowinSynthesis V1.9.7.06Beta
Part Number	GW1N-UV4LQ144C6/I5
Device	GW1N-4B
Created Time	Sat Jun 05 14:44:53 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	test_matrix_key
Synthesis Process	Running parser:     CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.127s, Peak memory usage = 141.207MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 141.207MB     Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 141.207MB     Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 141.207MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 141.207MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 141.207MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 141.207MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 141.207MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 141.207MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 141.207MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 141.207MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.975s, Peak memory usage = 141.207MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 141.207MB Generate output files:     CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 141.207MB
Total Time and Memory Usage	CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 141.207MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	23
I/O Buf	23
IBUF	6
OBUF	17
Register	57
DFFS	2
DFFSE	2
DFFPE	16
DFFC	21
DFFCE	16
LUT	101
LUT2	17
LUT3	27
LUT4	57
INV	18
INV	18

Resource Utilization Summary

Resource	Usage	Utilization
Logic	119(119 LUTs, 0 ALUs) / 4608	3%
Register	57 / 3756	2%
--Register as Latch	0 / 3756	0%
--Register as FF	57 / 3756	2%
BSRAM	0 / 10	0%

Timing

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
clk	Base	10.000	100.0	0.000	5.000			clk_ibuf/I
clk50hz	Base	10.000	100.0	0.000	5.000			inst1/clk50hz_s/F

Max Frequency Summary:

No.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.0(MHz)	133.0(MHz)	5	TOP
2	clk50hz	100.0(MHz)	342.8(MHz)	2	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	2.480
Data Arrival Time	8.465
Data Required Time	10.945
From	inst1/count_0_s0
To	inst1/count_12_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	18	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_0_s0/CLK
1.803	0.458	tC2Q	RF	5	inst1/count_0_s0/Q
2.283	0.480	tNET	FF	1	inst1/n51_s2/I1
3.382	1.099	tINS	FF	6	inst1/n51_s2/F
3.862	0.480	tNET	FF	1	inst1/n48_s4/I0
4.894	1.032	tINS	FF	6	inst1/n48_s4/F
5.374	0.480	tNET	FF	1	inst1/n44_s2/I0
6.406	1.032	tINS	FF	1	inst1/n44_s2/F
6.886	0.480	tNET	FF	1	inst1/n43_s1/I1
7.985	1.099	tINS	FF	1	inst1/n43_s1/F
8.465	0.480	tNET	FF	1	inst1/count_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	18	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst1/count_12_s0/CLK
10.945	-0.400	tSu		1	inst1/count_12_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 4.262, 59.857%; route: 2.400, 33.706%; tC2Q: 0.458, 6.437%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:

Slack	2.690
Data Arrival Time	8.255
Data Required Time	10.945
From	inst1/count_0_s0
To	inst1/count_9_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	18	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_0_s0/CLK
1.803	0.458	tC2Q	RF	5	inst1/count_0_s0/Q
2.283	0.480	tNET	FF	1	inst1/n51_s2/I1
3.382	1.099	tINS	FF	6	inst1/n51_s2/F
3.862	0.480	tNET	FF	1	inst1/n48_s4/I0
4.894	1.032	tINS	FF	6	inst1/n48_s4/F
5.374	0.480	tNET	FF	1	inst1/n46_s2/I2
6.196	0.822	tINS	FF	1	inst1/n46_s2/F
6.676	0.480	tNET	FF	1	inst1/n46_s1/I1
7.775	1.099	tINS	FF	1	inst1/n46_s1/F
8.255	0.480	tNET	FF	1	inst1/count_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	18	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst1/count_9_s0/CLK
10.945	-0.400	tSu		1	inst1/count_9_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 4.052, 58.636%; route: 2.400, 34.731%; tC2Q: 0.458, 6.633%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:

Slack	2.819
Data Arrival Time	8.126
Data Required Time	10.945
From	inst1/count_0_s0
To	inst1/count_17_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	18	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_0_s0/CLK
1.803	0.458	tC2Q	RF	5	inst1/count_0_s0/Q
2.283	0.480	tNET	FF	1	inst1/n51_s2/I1
3.382	1.099	tINS	FF	6	inst1/n51_s2/F
3.862	0.480	tNET	FF	1	inst1/n42_s2/I1
4.961	1.099	tINS	FF	4	inst1/n42_s2/F
5.441	0.480	tNET	FF	1	inst1/n39_s3/I3
6.067	0.626	tINS	FF	2	inst1/n39_s3/F
6.547	0.480	tNET	FF	1	inst1/n38_s1/I1
7.646	1.099	tINS	FF	1	inst1/n38_s1/F
8.126	0.480	tNET	FF	1	inst1/count_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	18	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst1/count_17_s0/CLK
10.945	-0.400	tSu		1	inst1/count_17_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 3.923, 57.850%; route: 2.400, 35.391%; tC2Q: 0.458, 6.759%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:

Slack	2.886
Data Arrival Time	8.059
Data Required Time	10.945
From	inst1/count_0_s0
To	inst1/count_10_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	18	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_0_s0/CLK
1.803	0.458	tC2Q	RF	5	inst1/count_0_s0/Q
2.283	0.480	tNET	FF	1	inst1/n51_s2/I1
3.382	1.099	tINS	FF	6	inst1/n51_s2/F
3.862	0.480	tNET	FF	1	inst1/n48_s4/I0
4.894	1.032	tINS	FF	6	inst1/n48_s4/F
5.374	0.480	tNET	FF	1	inst1/n45_s2/I3
6.000	0.626	tINS	FF	1	inst1/n45_s2/F
6.480	0.480	tNET	FF	1	inst1/n45_s1/I1
7.579	1.099	tINS	FF	1	inst1/n45_s1/F
8.059	0.480	tNET	FF	1	inst1/count_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	18	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst1/count_10_s0/CLK
10.945	-0.400	tSu		1	inst1/count_10_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 3.856, 57.430%; route: 2.400, 35.744%; tC2Q: 0.458, 6.826%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:

Slack	2.900
Data Arrival Time	8.045
Data Required Time	10.945
From	inst1/count_0_s0
To	inst1/count_15_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.982	0.982	tINS	RR	18	clk_ibuf/O
1.345	0.363	tNET	RR	1	inst1/count_0_s0/CLK
1.803	0.458	tC2Q	RF	5	inst1/count_0_s0/Q
2.283	0.480	tNET	FF	1	inst1/n51_s2/I1
3.382	1.099	tINS	FF	6	inst1/n51_s2/F
3.862	0.480	tNET	FF	1	inst1/n42_s2/I1
4.961	1.099	tINS	FF	4	inst1/n42_s2/F
5.441	0.480	tNET	FF	1	inst1/n40_s2/I2
6.263	0.822	tINS	FF	1	inst1/n40_s2/F
6.743	0.480	tNET	FF	1	inst1/n40_s1/I2
7.565	0.822	tINS	FF	1	inst1/n40_s1/F
8.045	0.480	tNET	FF	1	inst1/count_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				clk
10.000	0.000	tCL	RR	1	clk_ibuf/I
10.982	0.982	tINS	RR	18	clk_ibuf/O
11.345	0.363	tNET	RR	1	inst1/count_15_s0/CLK
10.945	-0.400	tSu		1	inst1/count_15_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay:	cell: 3.842, 57.341%; route: 2.400, 35.819%; tC2Q: 0.458, 6.840%
Required Clock Path Delay:	cell: 0.982, 73.009%; route: 0.363, 26.991%