Timing Messages

Report Title Gowin Timing Analysis Report
Design File C:\Gowin\Workspace210605\matrix_key\impl\gwsynthesis\matrix_key.vg
Physical Constraints File C:\Gowin\Workspace210605\matrix_key\src\matrix_key.cst
Timing Constraint File ---
GOWIN version V1.9.7.03Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Fri Jul 23 14:11:35 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 2.375V 85C
Hold Delay Model Fast 2.625V 0C
Numbers of Paths Analyzed 203
Numbers of Endpoints Analyzed 165
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 18

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I
clk50hz Base 10.000 100.000 0.000 5.000 inst1/clk50hz_s/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 128.232(MHz) 5 TOP
2 clk50hz 100.000(MHz) 240.088(MHz) 2 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
clk50hz Setup 0.000 0
clk50hz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.202 inst1/count_1_s0/Q inst1/count_9_s0/D clk:[R] clk:[R] 10.000 0.000 7.398
2 2.207 inst1/count_10_s0/Q inst1/count_15_s0/D clk:[R] clk:[R] 10.000 0.000 7.393
3 2.294 inst1/count_1_s0/Q inst1/count_10_s0/D clk:[R] clk:[R] 10.000 0.000 7.306
4 2.701 inst1/count_10_s0/Q inst1/count_16_s0/D clk:[R] clk:[R] 10.000 0.000 6.899
5 2.881 inst1/count_10_s0/Q inst1/count_17_s0/D clk:[R] clk:[R] 10.000 0.000 6.719
6 3.017 inst1/count_1_s0/Q inst1/count_12_s0/D clk:[R] clk:[R] 10.000 0.000 6.583
7 3.844 inst1/count_1_s0/Q inst1/count_11_s0/D clk:[R] clk:[R] 10.000 0.000 5.756
8 3.907 inst1/count_10_s0/Q inst1/count_14_s0/D clk:[R] clk:[R] 10.000 0.000 5.693
9 3.924 inst1/count_10_s0/Q inst1/count_13_s0/D clk:[R] clk:[R] 10.000 0.000 5.676
10 4.322 inst1/count_1_s0/Q inst1/count_8_s0/D clk:[R] clk:[R] 10.000 0.000 5.278
11 4.414 inst1/n48_s1/I0 inst1/count_7_s0/D clk50hz:[F] clk:[R] 5.000 -2.130 2.286
12 4.425 inst1/n53_s1/I2 inst1/count_2_s0/D clk50hz:[F] clk:[R] 5.000 -2.130 2.275
13 4.437 inst1/n52_s1/I0 inst1/count_3_s0/D clk50hz:[F] clk:[R] 5.000 -2.130 2.264
14 4.583 inst1/count_1_s0/Q inst1/count_6_s0/D clk:[R] clk:[R] 10.000 0.000 5.017
15 4.887 inst1/n50_s1/I2 inst1/count_5_s0/D clk50hz:[F] clk:[R] 5.000 -2.130 1.813
16 4.898 inst1/n55_s1/I1 inst1/count_0_s0/D clk50hz:[F] clk:[R] 5.000 -2.130 1.802
17 4.898 inst1/n54_s1/I0 inst1/count_1_s0/D clk50hz:[F] clk:[R] 5.000 -2.130 1.802
18 4.910 inst1/n51_s1/I0 inst1/count_4_s0/D clk50hz:[F] clk:[R] 5.000 -2.130 1.791
19 5.835 i9/index_0_s0/Q i9/tmp_4_s1/D clk50hz:[R] clk50hz:[R] 10.000 0.000 3.765
20 5.835 i9/index_0_s0/Q i9/tmp_5_s1/D clk50hz:[R] clk50hz:[R] 10.000 0.000 3.765
21 5.835 i9/index_0_s0/Q i9/tmp_6_s1/D clk50hz:[R] clk50hz:[R] 10.000 0.000 3.765
22 6.024 i9/index_0_s0/Q i9/tmp_1_s1/D clk50hz:[R] clk50hz:[R] 10.000 0.000 3.576
23 6.024 i9/index_0_s0/Q i9/tmp_2_s1/D clk50hz:[R] clk50hz:[R] 10.000 0.000 3.576
24 6.024 i9/index_0_s0/Q i9/tmp_3_s1/D clk50hz:[R] clk50hz:[R] 10.000 0.000 3.576
25 6.238 i9/index_0_s0/Q i9/tmp_7_s1/D clk50hz:[R] clk50hz:[R] 10.000 0.000 3.362

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.952 inst1/n47_s1/I2 inst1/count_8_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 0.729
2 -0.952 inst1/n38_s1/I3 inst1/count_17_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 0.729
3 -0.406 inst1/n51_s1/I0 inst1/count_4_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.274
4 -0.406 inst1/n49_s1/I0 inst1/count_6_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.274
5 -0.406 inst1/n43_s1/I2 inst1/count_12_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.274
6 -0.406 inst1/n40_s1/I0 inst1/count_15_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.274
7 -0.405 inst1/n55_s1/I1 inst1/count_0_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.276
8 -0.405 inst1/n54_s1/I0 inst1/count_1_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.276
9 -0.405 inst1/n46_s1/I0 inst1/count_9_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.276
10 -0.405 inst1/n44_s4/I0 inst1/count_11_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.276
11 -0.403 inst1/n50_s1/I2 inst1/count_5_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.277
12 -0.403 inst1/n39_s1/I0 inst1/count_16_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.277
13 -0.054 inst1/n52_s1/I0 inst1/count_3_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.626
14 -0.054 inst1/n42_s1/I0 inst1/count_13_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.626
15 -0.053 inst1/n53_s1/I2 inst1/count_2_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.628
16 -0.053 inst1/n45_s1/I0 inst1/count_10_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.628
17 -0.052 inst1/n41_s1/I2 inst1/count_14_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.628
18 -0.051 inst1/n48_s1/I0 inst1/count_7_s0/D clk50hz:[R] clk:[R] 0.000 -1.651 1.629
19 0.708 i9/col_1_s1/Q i9/col_1_s1/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.708
20 0.708 i9/col_3_s1/Q i9/col_3_s1/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.708
21 0.711 i9/index_1_s0/Q i9/index_1_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.711
22 0.894 i9/index_2_s0/Q i9/index_2_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.894
23 0.970 i9/tmp_2_s1/Q i9/key_2_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.970
24 0.970 i9/tmp_3_s1/Q i9/key_3_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.970
25 0.970 i9/tmp_9_s1/Q i9/key_9_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.970

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.911 4.161 1.250 Low Pulse Width clk inst1/count_17_s0
2 2.911 4.161 1.250 Low Pulse Width clk inst1/count_15_s0
3 2.911 4.161 1.250 Low Pulse Width clk inst1/count_11_s0
4 2.911 4.161 1.250 Low Pulse Width clk inst1/count_3_s0
5 2.911 4.161 1.250 Low Pulse Width clk inst1/count_4_s0
6 2.911 4.161 1.250 Low Pulse Width clk inst1/count_12_s0
7 2.911 4.161 1.250 Low Pulse Width clk inst1/count_5_s0
8 2.911 4.161 1.250 Low Pulse Width clk inst1/count_6_s0
9 2.911 4.161 1.250 Low Pulse Width clk inst1/count_16_s0
10 2.911 4.161 1.250 Low Pulse Width clk inst1/count_13_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.202
Data Arrival Time 9.529
Data Required Time 11.730
From inst1/count_1_s0
To inst1/count_9_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[2][A] inst1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R9C17[2][A] inst1/count_1_s0/Q
3.404 0.816 tNET FF 1 R12C17[0][B] inst1/n51_s2/I0
4.503 1.099 tINS FF 6 R12C17[0][B] inst1/n51_s2/F
5.335 0.832 tNET FF 1 R12C18[0][A] inst1/n48_s4/I0
5.961 0.626 tINS FF 6 R12C18[0][A] inst1/n48_s4/F
6.803 0.842 tNET FF 1 R11C18[1][A] inst1/n46_s2/I2
7.902 1.099 tINS FF 1 R11C18[1][A] inst1/n46_s2/F
8.707 0.804 tNET FF 1 R9C17[1][B] inst1/n46_s1/I1
9.529 0.822 tINS FF 1 R9C17[1][B] inst1/n46_s1/F
9.529 0.000 tNET FF 1 R9C17[1][B] inst1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R9C17[1][B] inst1/count_9_s0/CLK
11.730 -0.400 tSu 1 R9C17[1][B] inst1/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.646, 49.281%; route: 3.294, 44.524%; tC2Q: 0.458, 6.195%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path2

Path Summary:

Slack 2.207
Data Arrival Time 9.524
Data Required Time 11.730
From inst1/count_10_s0
To inst1/count_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[0][A] inst1/count_10_s0/CLK
2.588 0.458 tC2Q RF 3 R9C17[0][A] inst1/count_10_s0/Q
3.416 0.828 tNET FF 1 R11C17[2][B] inst1/n44_s3/I3
4.515 1.099 tINS FF 3 R11C17[2][B] inst1/n44_s3/F
5.347 0.832 tNET FF 1 R12C17[0][A] inst1/n42_s2/I3
6.149 0.802 tINS FR 4 R12C17[0][A] inst1/n42_s2/F
6.572 0.423 tNET RR 1 R12C18[0][B] inst1/n40_s2/I2
7.671 1.099 tINS RF 1 R12C18[0][B] inst1/n40_s2/F
8.492 0.821 tNET FF 1 R12C17[1][B] inst1/n40_s1/I2
9.524 1.032 tINS FF 1 R12C17[1][B] inst1/n40_s1/F
9.524 0.000 tNET FF 1 R12C17[1][B] inst1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C17[1][B] inst1/count_15_s0/CLK
11.730 -0.400 tSu 1 R12C17[1][B] inst1/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 4.032, 54.535%; route: 2.903, 39.266%; tC2Q: 0.458, 6.199%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path3

Path Summary:

Slack 2.294
Data Arrival Time 9.436
Data Required Time 11.730
From inst1/count_1_s0
To inst1/count_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[2][A] inst1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R9C17[2][A] inst1/count_1_s0/Q
3.404 0.816 tNET FF 1 R12C17[0][B] inst1/n51_s2/I0
4.503 1.099 tINS FF 6 R12C17[0][B] inst1/n51_s2/F
5.335 0.832 tNET FF 1 R12C18[0][A] inst1/n48_s4/I0
5.961 0.626 tINS FF 6 R12C18[0][A] inst1/n48_s4/F
6.957 0.996 tNET FF 1 R11C17[1][A] inst1/n45_s2/I3
7.583 0.626 tINS FF 1 R11C17[1][A] inst1/n45_s2/F
8.404 0.821 tNET FF 1 R9C17[0][A] inst1/n45_s1/I1
9.436 1.032 tINS FF 1 R9C17[0][A] inst1/n45_s1/F
9.436 0.000 tNET FF 1 R9C17[0][A] inst1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R9C17[0][A] inst1/count_10_s0/CLK
11.730 -0.400 tSu 1 R9C17[0][A] inst1/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.383, 46.307%; route: 3.464, 47.419%; tC2Q: 0.458, 6.274%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path4

Path Summary:

Slack 2.701
Data Arrival Time 9.029
Data Required Time 11.730
From inst1/count_10_s0
To inst1/count_16_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[0][A] inst1/count_10_s0/CLK
2.588 0.458 tC2Q RF 3 R9C17[0][A] inst1/count_10_s0/Q
3.416 0.828 tNET FF 1 R11C17[2][B] inst1/n44_s3/I3
4.515 1.099 tINS FF 3 R11C17[2][B] inst1/n44_s3/F
5.347 0.832 tNET FF 1 R12C17[0][A] inst1/n42_s2/I3
6.169 0.822 tINS FF 4 R12C17[0][A] inst1/n42_s2/F
6.984 0.815 tNET FF 1 R11C18[2][B] inst1/n39_s3/I3
7.786 0.802 tINS FR 2 R11C18[2][B] inst1/n39_s3/F
8.207 0.421 tNET RR 1 R12C18[2][B] inst1/n39_s1/I2
9.029 0.822 tINS RF 1 R12C18[2][B] inst1/n39_s1/F
9.029 0.000 tNET FF 1 R12C18[2][B] inst1/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C18[2][B] inst1/count_16_s0/CLK
11.730 -0.400 tSu 1 R12C18[2][B] inst1/count_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.545, 51.385%; route: 2.896, 41.972%; tC2Q: 0.458, 6.644%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path5

Path Summary:

Slack 2.881
Data Arrival Time 8.849
Data Required Time 11.730
From inst1/count_10_s0
To inst1/count_17_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[0][A] inst1/count_10_s0/CLK
2.588 0.458 tC2Q RF 3 R9C17[0][A] inst1/count_10_s0/Q
3.416 0.828 tNET FF 1 R11C17[2][B] inst1/n44_s3/I3
4.515 1.099 tINS FF 3 R11C17[2][B] inst1/n44_s3/F
5.347 0.832 tNET FF 1 R12C17[0][A] inst1/n42_s2/I3
6.169 0.822 tINS FF 4 R12C17[0][A] inst1/n42_s2/F
6.984 0.815 tNET FF 1 R11C18[2][B] inst1/n39_s3/I3
7.806 0.822 tINS FF 2 R11C18[2][B] inst1/n39_s3/F
7.817 0.011 tNET FF 1 R11C18[0][B] inst1/n38_s1/I1
8.849 1.032 tINS FF 1 R11C18[0][B] inst1/n38_s1/F
8.849 0.000 tNET FF 1 R11C18[0][B] inst1/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C18[0][B] inst1/count_17_s0/CLK
11.730 -0.400 tSu 1 R11C18[0][B] inst1/count_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.775, 56.183%; route: 2.486, 36.996%; tC2Q: 0.458, 6.821%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path6

Path Summary:

Slack 3.017
Data Arrival Time 8.713
Data Required Time 11.730
From inst1/count_1_s0
To inst1/count_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[2][A] inst1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R9C17[2][A] inst1/count_1_s0/Q
3.404 0.816 tNET FF 1 R12C17[0][B] inst1/n51_s2/I0
4.503 1.099 tINS FF 6 R12C17[0][B] inst1/n51_s2/F
5.335 0.832 tNET FF 1 R12C18[0][A] inst1/n48_s4/I0
5.961 0.626 tINS FF 6 R12C18[0][A] inst1/n48_s4/F
6.787 0.825 tNET FF 1 R11C17[3][A] inst1/n44_s2/I0
7.886 1.099 tINS FF 1 R11C17[3][A] inst1/n44_s2/F
7.891 0.005 tNET FF 1 R11C17[1][B] inst1/n43_s1/I1
8.713 0.822 tINS FF 1 R11C17[1][B] inst1/n43_s1/F
8.713 0.000 tNET FF 1 R11C17[1][B] inst1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C17[1][B] inst1/count_12_s0/CLK
11.730 -0.400 tSu 1 R11C17[1][B] inst1/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 3.646, 55.385%; route: 2.479, 37.653%; tC2Q: 0.458, 6.962%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path7

Path Summary:

Slack 3.844
Data Arrival Time 7.886
Data Required Time 11.730
From inst1/count_1_s0
To inst1/count_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[2][A] inst1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R9C17[2][A] inst1/count_1_s0/Q
3.404 0.816 tNET FF 1 R12C17[0][B] inst1/n51_s2/I0
4.503 1.099 tINS FF 6 R12C17[0][B] inst1/n51_s2/F
5.335 0.832 tNET FF 1 R12C18[0][A] inst1/n48_s4/I0
5.961 0.626 tINS FF 6 R12C18[0][A] inst1/n48_s4/F
6.787 0.825 tNET FF 1 R11C17[2][A] inst1/n44_s4/I2
7.886 1.099 tINS FF 1 R11C17[2][A] inst1/n44_s4/F
7.886 0.000 tNET FF 1 R11C17[2][A] inst1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C17[2][A] inst1/count_11_s0/CLK
11.730 -0.400 tSu 1 R11C17[2][A] inst1/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 2.824, 49.066%; route: 2.473, 42.971%; tC2Q: 0.458, 7.963%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path8

Path Summary:

Slack 3.907
Data Arrival Time 7.823
Data Required Time 11.730
From inst1/count_10_s0
To inst1/count_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[0][A] inst1/count_10_s0/CLK
2.588 0.458 tC2Q RF 3 R9C17[0][A] inst1/count_10_s0/Q
3.416 0.828 tNET FF 1 R11C17[2][B] inst1/n44_s3/I3
4.515 1.099 tINS FF 3 R11C17[2][B] inst1/n44_s3/F
5.347 0.832 tNET FF 1 R12C17[0][A] inst1/n42_s2/I3
6.169 0.822 tINS FF 4 R12C17[0][A] inst1/n42_s2/F
7.001 0.832 tNET FF 1 R12C19[0][A] inst1/n41_s1/I1
7.823 0.822 tINS FF 1 R12C19[0][A] inst1/n41_s1/F
7.823 0.000 tNET FF 1 R12C19[0][A] inst1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C19[0][A] inst1/count_14_s0/CLK
11.730 -0.400 tSu 1 R12C19[0][A] inst1/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 2.743, 48.185%; route: 2.491, 43.764%; tC2Q: 0.458, 8.051%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path9

Path Summary:

Slack 3.924
Data Arrival Time 7.806
Data Required Time 11.730
From inst1/count_10_s0
To inst1/count_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[0][A] inst1/count_10_s0/CLK
2.588 0.458 tC2Q RF 3 R9C17[0][A] inst1/count_10_s0/Q
3.416 0.828 tNET FF 1 R11C17[2][B] inst1/n44_s3/I3
4.515 1.099 tINS FF 3 R11C17[2][B] inst1/n44_s3/F
5.347 0.832 tNET FF 1 R12C17[0][A] inst1/n42_s2/I3
6.169 0.822 tINS FF 4 R12C17[0][A] inst1/n42_s2/F
6.984 0.815 tNET FF 1 R11C19[0][A] inst1/n42_s1/I2
7.806 0.822 tINS FF 1 R11C19[0][A] inst1/n42_s1/F
7.806 0.000 tNET FF 1 R11C19[0][A] inst1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C19[0][A] inst1/count_13_s0/CLK
11.730 -0.400 tSu 1 R11C19[0][A] inst1/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 2.743, 48.325%; route: 2.475, 43.600%; tC2Q: 0.458, 8.075%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path10

Path Summary:

Slack 4.322
Data Arrival Time 7.408
Data Required Time 11.730
From inst1/count_1_s0
To inst1/count_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[2][A] inst1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R9C17[2][A] inst1/count_1_s0/Q
3.404 0.816 tNET FF 1 R12C17[0][B] inst1/n51_s2/I0
4.503 1.099 tINS FF 6 R12C17[0][B] inst1/n51_s2/F
5.335 0.832 tNET FF 1 R12C18[0][A] inst1/n48_s4/I0
5.961 0.626 tINS FF 6 R12C18[0][A] inst1/n48_s4/F
6.782 0.821 tNET FF 1 R11C18[2][A] inst1/n47_s1/I1
7.408 0.626 tINS FF 1 R11C18[2][A] inst1/n47_s1/F
7.408 0.000 tNET FF 1 R11C18[2][A] inst1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C18[2][A] inst1/count_8_s0/CLK
11.730 -0.400 tSu 1 R11C18[2][A] inst1/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 2.351, 44.544%; route: 2.469, 46.772%; tC2Q: 0.458, 8.684%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path11

Path Summary:

Slack 4.414
Data Arrival Time 7.286
Data Required Time 11.700
From inst1/n48_s1
To inst1/count_7_s0
Launch Clk clk50hz:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk50hz
5.000 0.000 tCL FF 57 R11C18[1][B] inst1/clk50hz_s/F
6.187 1.187 tNET FF 1 R12C18[1][A] inst1/n48_s1/I0
7.286 1.099 tINS FF 1 R12C18[1][A] inst1/n48_s1/F
7.286 0.000 tNET FF 1 R12C18[1][A] inst1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C18[1][A] inst1/count_7_s0/CLK
12.100 -0.030 tUnc inst1/count_7_s0
11.700 -0.400 tSu 1 R12C18[1][A] inst1/count_7_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.099, 48.070%; route: 0.000, 0.000%; tC2Q: 1.187, 51.930%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path12

Path Summary:

Slack 4.425
Data Arrival Time 7.275
Data Required Time 11.700
From inst1/n53_s1
To inst1/count_2_s0
Launch Clk clk50hz:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk50hz
5.000 0.000 tCL FF 57 R11C18[1][B] inst1/clk50hz_s/F
6.176 1.176 tNET FF 1 R11C17[0][A] inst1/n53_s1/I2
7.275 1.099 tINS FF 1 R11C17[0][A] inst1/n53_s1/F
7.275 0.000 tNET FF 1 R11C17[0][A] inst1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R11C17[0][A] inst1/count_2_s0/CLK
12.100 -0.030 tUnc inst1/count_2_s0
11.700 -0.400 tSu 1 R11C17[0][A] inst1/count_2_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.099, 48.309%; route: 0.000, 0.000%; tC2Q: 1.176, 51.691%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path13

Path Summary:

Slack 4.437
Data Arrival Time 7.264
Data Required Time 11.700
From inst1/n52_s1
To inst1/count_3_s0
Launch Clk clk50hz:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk50hz
5.000 0.000 tCL FF 57 R11C18[1][B] inst1/clk50hz_s/F
6.165 1.165 tNET FF 1 R12C17[1][A] inst1/n52_s1/I0
7.264 1.099 tINS FF 1 R12C17[1][A] inst1/n52_s1/F
7.264 0.000 tNET FF 1 R12C17[1][A] inst1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C17[1][A] inst1/count_3_s0/CLK
12.100 -0.030 tUnc inst1/count_3_s0
11.700 -0.400 tSu 1 R12C17[1][A] inst1/count_3_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.099, 48.550%; route: 0.000, 0.000%; tC2Q: 1.165, 51.450%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path14

Path Summary:

Slack 4.583
Data Arrival Time 7.147
Data Required Time 11.730
From inst1/count_1_s0
To inst1/count_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
2.130 1.148 tNET RR 1 R9C17[2][A] inst1/count_1_s0/CLK
2.588 0.458 tC2Q RF 4 R9C17[2][A] inst1/count_1_s0/Q
3.404 0.816 tNET FF 1 R12C17[0][B] inst1/n51_s2/I0
4.465 1.061 tINS FR 6 R12C17[0][B] inst1/n51_s2/F
4.894 0.429 tNET RR 1 R12C18[3][B] inst1/n49_s2/I2
5.696 0.802 tINS RR 1 R12C18[3][B] inst1/n49_s2/F
6.115 0.419 tNET RR 1 R12C19[0][B] inst1/n49_s1/I1
7.147 1.032 tINS RF 1 R12C19[0][B] inst1/n49_s1/F
7.147 0.000 tNET FF 1 R12C19[0][B] inst1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C19[0][B] inst1/count_6_s0/CLK
11.730 -0.400 tSu 1 R12C19[0][B] inst1/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay cell: 2.895, 57.708%; route: 1.663, 33.155%; tC2Q: 0.458, 9.136%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path15

Path Summary:

Slack 4.887
Data Arrival Time 6.813
Data Required Time 11.700
From inst1/n50_s1
To inst1/count_5_s0
Launch Clk clk50hz:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk50hz
5.000 0.000 tCL FF 57 R11C18[1][B] inst1/clk50hz_s/F
6.187 1.187 tNET FF 1 R12C18[2][A] inst1/n50_s1/I2
6.813 0.626 tINS FF 1 R12C18[2][A] inst1/n50_s1/F
6.813 0.000 tNET FF 1 R12C18[2][A] inst1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C18[2][A] inst1/count_5_s0/CLK
12.100 -0.030 tUnc inst1/count_5_s0
11.700 -0.400 tSu 1 R12C18[2][A] inst1/count_5_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.626, 34.524%; route: 0.000, 0.000%; tC2Q: 1.187, 65.476%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path16

Path Summary:

Slack 4.898
Data Arrival Time 6.802
Data Required Time 11.700
From inst1/n55_s1
To inst1/count_0_s0
Launch Clk clk50hz:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk50hz
5.000 0.000 tCL FF 57 R11C18[1][B] inst1/clk50hz_s/F
6.176 1.176 tNET FF 1 R9C17[0][B] inst1/n55_s1/I1
6.802 0.626 tINS FF 1 R9C17[0][B] inst1/n55_s1/F
6.802 0.000 tNET FF 1 R9C17[0][B] inst1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R9C17[0][B] inst1/count_0_s0/CLK
12.100 -0.030 tUnc inst1/count_0_s0
11.700 -0.400 tSu 1 R9C17[0][B] inst1/count_0_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.626, 34.740%; route: 0.000, 0.000%; tC2Q: 1.176, 65.260%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path17

Path Summary:

Slack 4.898
Data Arrival Time 6.802
Data Required Time 11.700
From inst1/n54_s1
To inst1/count_1_s0
Launch Clk clk50hz:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk50hz
5.000 0.000 tCL FF 57 R11C18[1][B] inst1/clk50hz_s/F
6.176 1.176 tNET FF 1 R9C17[2][A] inst1/n54_s1/I0
6.802 0.626 tINS FF 1 R9C17[2][A] inst1/n54_s1/F
6.802 0.000 tNET FF 1 R9C17[2][A] inst1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R9C17[2][A] inst1/count_1_s0/CLK
12.100 -0.030 tUnc inst1/count_1_s0
11.700 -0.400 tSu 1 R9C17[2][A] inst1/count_1_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.626, 34.740%; route: 0.000, 0.000%; tC2Q: 1.176, 65.260%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path18

Path Summary:

Slack 4.910
Data Arrival Time 6.791
Data Required Time 11.700
From inst1/n51_s1
To inst1/count_4_s0
Launch Clk clk50hz:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk50hz
5.000 0.000 tCL FF 57 R11C18[1][B] inst1/clk50hz_s/F
6.165 1.165 tNET FF 1 R12C18[1][B] inst1/n51_s1/I0
6.791 0.626 tINS FF 1 R12C18[1][B] inst1/n51_s1/F
6.791 0.000 tNET FF 1 R12C18[1][B] inst1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
10.982 0.982 tINS RR 18 IOL3[A] clk_ibuf/O
12.130 1.148 tNET RR 1 R12C18[1][B] inst1/count_4_s0/CLK
12.100 -0.030 tUnc inst1/count_4_s0
11.700 -0.400 tSu 1 R12C18[1][B] inst1/count_4_s0

Path Statistics:

Clock Skew 2.130
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.626, 34.960%; route: 0.000, 0.000%; tC2Q: 1.165, 65.040%
Required Clock Path Delay cell: 0.982, 46.094%; route: 1.148, 53.906%

Path19

Path Summary:

Slack 5.835
Data Arrival Time 4.584
Data Required Time 10.419
From i9/index_0_s0
To i9/tmp_4_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.819 0.819 tNET RR 1 R12C14[2][B] i9/index_0_s0/CLK
1.278 0.458 tC2Q RF 16 R12C14[2][B] i9/index_0_s0/Q
2.106 0.828 tNET FF 1 R13C15[0][A] i9/n122_s1/I1
3.138 1.032 tINS FF 4 R13C15[0][A] i9/n122_s1/F
4.584 1.447 tNET FF 1 R12C16[0][B] i9/tmp_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk50hz
10.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
10.819 0.819 tNET RR 1 R12C16[0][B] i9/tmp_4_s1/CLK
10.419 -0.400 tSu 1 R12C16[0][B] i9/tmp_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%
Arrival Data Path Delay cell: 1.032, 27.409%; route: 2.275, 60.418%; tC2Q: 0.458, 12.173%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%

Path20

Path Summary:

Slack 5.835
Data Arrival Time 4.584
Data Required Time 10.419
From i9/index_0_s0
To i9/tmp_5_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.819 0.819 tNET RR 1 R12C14[2][B] i9/index_0_s0/CLK
1.278 0.458 tC2Q RF 16 R12C14[2][B] i9/index_0_s0/Q
2.106 0.828 tNET FF 1 R13C15[0][A] i9/n122_s1/I1
3.138 1.032 tINS FF 4 R13C15[0][A] i9/n122_s1/F
4.584 1.447 tNET FF 1 R11C16[2][B] i9/tmp_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk50hz
10.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
10.819 0.819 tNET RR 1 R11C16[2][B] i9/tmp_5_s1/CLK
10.419 -0.400 tSu 1 R11C16[2][B] i9/tmp_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%
Arrival Data Path Delay cell: 1.032, 27.409%; route: 2.275, 60.418%; tC2Q: 0.458, 12.173%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%

Path21

Path Summary:

Slack 5.835
Data Arrival Time 4.584
Data Required Time 10.419
From i9/index_0_s0
To i9/tmp_6_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.819 0.819 tNET RR 1 R12C14[2][B] i9/index_0_s0/CLK
1.278 0.458 tC2Q RF 16 R12C14[2][B] i9/index_0_s0/Q
2.106 0.828 tNET FF 1 R13C15[0][A] i9/n122_s1/I1
3.138 1.032 tINS FF 4 R13C15[0][A] i9/n122_s1/F
4.584 1.447 tNET FF 1 R11C16[1][B] i9/tmp_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk50hz
10.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
10.819 0.819 tNET RR 1 R11C16[1][B] i9/tmp_6_s1/CLK
10.419 -0.400 tSu 1 R11C16[1][B] i9/tmp_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%
Arrival Data Path Delay cell: 1.032, 27.409%; route: 2.275, 60.418%; tC2Q: 0.458, 12.173%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%

Path22

Path Summary:

Slack 6.024
Data Arrival Time 4.395
Data Required Time 10.419
From i9/index_0_s0
To i9/tmp_1_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.819 0.819 tNET RR 1 R12C14[2][B] i9/index_0_s0/CLK
1.278 0.458 tC2Q RF 16 R12C14[2][B] i9/index_0_s0/Q
2.128 0.851 tNET FF 1 R11C13[0][A] i9/n126_s1/I1
2.950 0.822 tINS FF 4 R11C13[0][A] i9/n126_s1/F
4.395 1.445 tNET FF 1 R11C16[2][A] i9/tmp_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk50hz
10.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
10.819 0.819 tNET RR 1 R11C16[2][A] i9/tmp_1_s1/CLK
10.419 -0.400 tSu 1 R11C16[2][A] i9/tmp_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%
Arrival Data Path Delay cell: 0.822, 22.987%; route: 2.296, 64.196%; tC2Q: 0.458, 12.817%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%

Path23

Path Summary:

Slack 6.024
Data Arrival Time 4.395
Data Required Time 10.419
From i9/index_0_s0
To i9/tmp_2_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.819 0.819 tNET RR 1 R12C14[2][B] i9/index_0_s0/CLK
1.278 0.458 tC2Q RF 16 R12C14[2][B] i9/index_0_s0/Q
2.128 0.851 tNET FF 1 R11C13[0][A] i9/n126_s1/I1
2.950 0.822 tINS FF 4 R11C13[0][A] i9/n126_s1/F
4.395 1.445 tNET FF 1 R11C16[1][A] i9/tmp_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk50hz
10.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
10.819 0.819 tNET RR 1 R11C16[1][A] i9/tmp_2_s1/CLK
10.419 -0.400 tSu 1 R11C16[1][A] i9/tmp_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%
Arrival Data Path Delay cell: 0.822, 22.987%; route: 2.296, 64.196%; tC2Q: 0.458, 12.817%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%

Path24

Path Summary:

Slack 6.024
Data Arrival Time 4.395
Data Required Time 10.419
From i9/index_0_s0
To i9/tmp_3_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.819 0.819 tNET RR 1 R12C14[2][B] i9/index_0_s0/CLK
1.278 0.458 tC2Q RF 16 R12C14[2][B] i9/index_0_s0/Q
2.128 0.851 tNET FF 1 R11C13[0][A] i9/n126_s1/I1
2.950 0.822 tINS FF 4 R11C13[0][A] i9/n126_s1/F
4.395 1.445 tNET FF 1 R11C16[0][A] i9/tmp_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk50hz
10.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
10.819 0.819 tNET RR 1 R11C16[0][A] i9/tmp_3_s1/CLK
10.419 -0.400 tSu 1 R11C16[0][A] i9/tmp_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%
Arrival Data Path Delay cell: 0.822, 22.987%; route: 2.296, 64.196%; tC2Q: 0.458, 12.817%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%

Path25

Path Summary:

Slack 6.238
Data Arrival Time 4.181
Data Required Time 10.419
From i9/index_0_s0
To i9/tmp_7_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.819 0.819 tNET RR 1 R12C14[2][B] i9/index_0_s0/CLK
1.278 0.458 tC2Q RF 16 R12C14[2][B] i9/index_0_s0/Q
2.106 0.828 tNET FF 1 R13C15[0][A] i9/n122_s1/I1
3.132 1.026 tINS FR 4 R13C15[0][A] i9/n122_s1/F
4.181 1.050 tNET RR 1 R12C15[2][B] i9/tmp_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk50hz
10.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
10.819 0.819 tNET RR 1 R12C15[2][B] i9/tmp_7_s1/CLK
10.419 -0.400 tSu 1 R12C15[2][B] i9/tmp_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%
Arrival Data Path Delay cell: 1.026, 30.517%; route: 1.878, 55.850%; tC2Q: 0.458, 13.633%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.819, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -0.952
Data Arrival Time 0.729
Data Required Time 1.681
From inst1/n47_s1
To inst1/count_8_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.005 0.005 tNET RR 1 R11C18[2][A] inst1/n47_s1/I2
0.729 0.724 tINS RR 1 R11C18[2][A] inst1/n47_s1/F
0.729 0.000 tNET RR 1 R11C18[2][A] inst1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C18[2][A] inst1/count_8_s0/CLK
1.681 0.030 tUnc inst1/count_8_s0
1.681 0.000 tHld 1 R11C18[2][A] inst1/count_8_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.724, 99.347%; route: 0.000, 0.000%; tC2Q: 0.005, 0.653%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path2

Path Summary:

Slack -0.952
Data Arrival Time 0.729
Data Required Time 1.681
From inst1/n38_s1
To inst1/count_17_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.005 0.005 tNET RR 1 R11C18[0][B] inst1/n38_s1/I3
0.729 0.724 tINS RR 1 R11C18[0][B] inst1/n38_s1/F
0.729 0.000 tNET RR 1 R11C18[0][B] inst1/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C18[0][B] inst1/count_17_s0/CLK
1.681 0.030 tUnc inst1/count_17_s0
1.681 0.000 tHld 1 R11C18[0][B] inst1/count_17_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.724, 99.347%; route: 0.000, 0.000%; tC2Q: 0.005, 0.653%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path3

Path Summary:

Slack -0.406
Data Arrival Time 1.274
Data Required Time 1.681
From inst1/n51_s1
To inst1/count_4_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.902 0.902 tNET RR 1 R12C18[1][B] inst1/n51_s1/I0
1.274 0.372 tINS RF 1 R12C18[1][B] inst1/n51_s1/F
1.274 0.000 tNET FF 1 R12C18[1][B] inst1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C18[1][B] inst1/count_4_s0/CLK
1.681 0.030 tUnc inst1/count_4_s0
1.681 0.000 tHld 1 R12C18[1][B] inst1/count_4_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.190%; route: 0.000, 0.000%; tC2Q: 0.902, 70.810%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path4

Path Summary:

Slack -0.406
Data Arrival Time 1.274
Data Required Time 1.681
From inst1/n49_s1
To inst1/count_6_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.902 0.902 tNET RR 1 R12C19[0][B] inst1/n49_s1/I0
1.274 0.372 tINS RF 1 R12C19[0][B] inst1/n49_s1/F
1.274 0.000 tNET FF 1 R12C19[0][B] inst1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C19[0][B] inst1/count_6_s0/CLK
1.681 0.030 tUnc inst1/count_6_s0
1.681 0.000 tHld 1 R12C19[0][B] inst1/count_6_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.190%; route: 0.000, 0.000%; tC2Q: 0.902, 70.810%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path5

Path Summary:

Slack -0.406
Data Arrival Time 1.274
Data Required Time 1.681
From inst1/n43_s1
To inst1/count_12_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.902 0.902 tNET RR 1 R11C17[1][B] inst1/n43_s1/I2
1.274 0.372 tINS RF 1 R11C17[1][B] inst1/n43_s1/F
1.274 0.000 tNET FF 1 R11C17[1][B] inst1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C17[1][B] inst1/count_12_s0/CLK
1.681 0.030 tUnc inst1/count_12_s0
1.681 0.000 tHld 1 R11C17[1][B] inst1/count_12_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.190%; route: 0.000, 0.000%; tC2Q: 0.902, 70.810%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path6

Path Summary:

Slack -0.406
Data Arrival Time 1.274
Data Required Time 1.681
From inst1/n40_s1
To inst1/count_15_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.902 0.902 tNET RR 1 R12C17[1][B] inst1/n40_s1/I0
1.274 0.372 tINS RF 1 R12C17[1][B] inst1/n40_s1/F
1.274 0.000 tNET FF 1 R12C17[1][B] inst1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C17[1][B] inst1/count_15_s0/CLK
1.681 0.030 tUnc inst1/count_15_s0
1.681 0.000 tHld 1 R12C17[1][B] inst1/count_15_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.190%; route: 0.000, 0.000%; tC2Q: 0.902, 70.810%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path7

Path Summary:

Slack -0.405
Data Arrival Time 1.276
Data Required Time 1.681
From inst1/n55_s1
To inst1/count_0_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.904 0.904 tNET RR 1 R9C17[0][B] inst1/n55_s1/I1
1.276 0.372 tINS RF 1 R9C17[0][B] inst1/n55_s1/F
1.276 0.000 tNET FF 1 R9C17[0][B] inst1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C17[0][B] inst1/count_0_s0/CLK
1.681 0.030 tUnc inst1/count_0_s0
1.681 0.000 tHld 1 R9C17[0][B] inst1/count_0_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.156%; route: 0.000, 0.000%; tC2Q: 0.904, 70.844%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path8

Path Summary:

Slack -0.405
Data Arrival Time 1.276
Data Required Time 1.681
From inst1/n54_s1
To inst1/count_1_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.904 0.904 tNET RR 1 R9C17[2][A] inst1/n54_s1/I0
1.276 0.372 tINS RF 1 R9C17[2][A] inst1/n54_s1/F
1.276 0.000 tNET FF 1 R9C17[2][A] inst1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C17[2][A] inst1/count_1_s0/CLK
1.681 0.030 tUnc inst1/count_1_s0
1.681 0.000 tHld 1 R9C17[2][A] inst1/count_1_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.156%; route: 0.000, 0.000%; tC2Q: 0.904, 70.844%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path9

Path Summary:

Slack -0.405
Data Arrival Time 1.276
Data Required Time 1.681
From inst1/n46_s1
To inst1/count_9_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.904 0.904 tNET RR 1 R9C17[1][B] inst1/n46_s1/I0
1.276 0.372 tINS RF 1 R9C17[1][B] inst1/n46_s1/F
1.276 0.000 tNET FF 1 R9C17[1][B] inst1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C17[1][B] inst1/count_9_s0/CLK
1.681 0.030 tUnc inst1/count_9_s0
1.681 0.000 tHld 1 R9C17[1][B] inst1/count_9_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.156%; route: 0.000, 0.000%; tC2Q: 0.904, 70.844%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path10

Path Summary:

Slack -0.405
Data Arrival Time 1.276
Data Required Time 1.681
From inst1/n44_s4
To inst1/count_11_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.904 0.904 tNET RR 1 R11C17[2][A] inst1/n44_s4/I0
1.276 0.372 tINS RF 1 R11C17[2][A] inst1/n44_s4/F
1.276 0.000 tNET FF 1 R11C17[2][A] inst1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C17[2][A] inst1/count_11_s0/CLK
1.681 0.030 tUnc inst1/count_11_s0
1.681 0.000 tHld 1 R11C17[2][A] inst1/count_11_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.156%; route: 0.000, 0.000%; tC2Q: 0.904, 70.844%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path11

Path Summary:

Slack -0.403
Data Arrival Time 1.277
Data Required Time 1.681
From inst1/n50_s1
To inst1/count_5_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.905 0.905 tNET RR 1 R12C18[2][A] inst1/n50_s1/I2
1.277 0.372 tINS RF 1 R12C18[2][A] inst1/n50_s1/F
1.277 0.000 tNET FF 1 R12C18[2][A] inst1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C18[2][A] inst1/count_5_s0/CLK
1.681 0.030 tUnc inst1/count_5_s0
1.681 0.000 tHld 1 R12C18[2][A] inst1/count_5_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.123%; route: 0.000, 0.000%; tC2Q: 0.905, 70.877%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path12

Path Summary:

Slack -0.403
Data Arrival Time 1.277
Data Required Time 1.681
From inst1/n39_s1
To inst1/count_16_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.905 0.905 tNET RR 1 R12C18[2][B] inst1/n39_s1/I0
1.277 0.372 tINS RF 1 R12C18[2][B] inst1/n39_s1/F
1.277 0.000 tNET FF 1 R12C18[2][B] inst1/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C18[2][B] inst1/count_16_s0/CLK
1.681 0.030 tUnc inst1/count_16_s0
1.681 0.000 tHld 1 R12C18[2][B] inst1/count_16_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.372, 29.123%; route: 0.000, 0.000%; tC2Q: 0.905, 70.877%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path13

Path Summary:

Slack -0.054
Data Arrival Time 1.626
Data Required Time 1.681
From inst1/n52_s1
To inst1/count_3_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.902 0.902 tNET RR 1 R12C17[1][A] inst1/n52_s1/I0
1.626 0.724 tINS RR 1 R12C17[1][A] inst1/n52_s1/F
1.626 0.000 tNET RR 1 R12C17[1][A] inst1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C17[1][A] inst1/count_3_s0/CLK
1.681 0.030 tUnc inst1/count_3_s0
1.681 0.000 tHld 1 R12C17[1][A] inst1/count_3_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.724, 44.515%; route: 0.000, 0.000%; tC2Q: 0.902, 55.485%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path14

Path Summary:

Slack -0.054
Data Arrival Time 1.626
Data Required Time 1.681
From inst1/n42_s1
To inst1/count_13_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.902 0.902 tNET RR 1 R11C19[0][A] inst1/n42_s1/I0
1.626 0.724 tINS RR 1 R11C19[0][A] inst1/n42_s1/F
1.626 0.000 tNET RR 1 R11C19[0][A] inst1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C19[0][A] inst1/count_13_s0/CLK
1.681 0.030 tUnc inst1/count_13_s0
1.681 0.000 tHld 1 R11C19[0][A] inst1/count_13_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.724, 44.515%; route: 0.000, 0.000%; tC2Q: 0.902, 55.485%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path15

Path Summary:

Slack -0.053
Data Arrival Time 1.628
Data Required Time 1.681
From inst1/n53_s1
To inst1/count_2_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.904 0.904 tNET RR 1 R11C17[0][A] inst1/n53_s1/I2
1.628 0.724 tINS RR 1 R11C17[0][A] inst1/n53_s1/F
1.628 0.000 tNET RR 1 R11C17[0][A] inst1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R11C17[0][A] inst1/count_2_s0/CLK
1.681 0.030 tUnc inst1/count_2_s0
1.681 0.000 tHld 1 R11C17[0][A] inst1/count_2_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.724, 44.475%; route: 0.000, 0.000%; tC2Q: 0.904, 55.525%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path16

Path Summary:

Slack -0.053
Data Arrival Time 1.628
Data Required Time 1.681
From inst1/n45_s1
To inst1/count_10_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.904 0.904 tNET RR 1 R9C17[0][A] inst1/n45_s1/I0
1.628 0.724 tINS RR 1 R9C17[0][A] inst1/n45_s1/F
1.628 0.000 tNET RR 1 R9C17[0][A] inst1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R9C17[0][A] inst1/count_10_s0/CLK
1.681 0.030 tUnc inst1/count_10_s0
1.681 0.000 tHld 1 R9C17[0][A] inst1/count_10_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.724, 44.475%; route: 0.000, 0.000%; tC2Q: 0.904, 55.525%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path17

Path Summary:

Slack -0.052
Data Arrival Time 1.628
Data Required Time 1.681
From inst1/n41_s1
To inst1/count_14_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.902 0.902 tNET RR 1 R12C19[0][A] inst1/n41_s1/I2
1.628 0.726 tINS RR 1 R12C19[0][A] inst1/n41_s1/F
1.628 0.000 tNET RR 1 R12C19[0][A] inst1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C19[0][A] inst1/count_14_s0/CLK
1.681 0.030 tUnc inst1/count_14_s0
1.681 0.000 tHld 1 R12C19[0][A] inst1/count_14_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.726, 44.583%; route: 0.000, 0.000%; tC2Q: 0.902, 55.417%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path18

Path Summary:

Slack -0.051
Data Arrival Time 1.629
Data Required Time 1.681
From inst1/n48_s1
To inst1/count_7_s0
Launch Clk clk50hz:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.905 0.905 tNET RR 1 R12C18[1][A] inst1/n48_s1/I0
1.629 0.724 tINS RR 1 R12C18[1][A] inst1/n48_s1/F
1.629 0.000 tNET RR 1 R12C18[1][A] inst1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL3[A] clk_ibuf/I
0.844 0.844 tINS RR 18 IOL3[A] clk_ibuf/O
1.651 0.806 tNET RR 1 R12C18[1][A] inst1/count_7_s0/CLK
1.681 0.030 tUnc inst1/count_7_s0
1.681 0.000 tHld 1 R12C18[1][A] inst1/count_7_s0

Path Statistics:

Clock Skew 1.651
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 0.724, 44.435%; route: 0.000, 0.000%; tC2Q: 0.905, 55.565%
Required Clock Path Delay cell: 0.844, 51.151%; route: 0.806, 48.849%

Path19

Path Summary:

Slack 0.708
Data Arrival Time 1.305
Data Required Time 0.597
From i9/col_1_s1
To i9/col_1_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R12C14[1][A] i9/col_1_s1/CLK
0.930 0.333 tC2Q RR 2 R12C14[1][A] i9/col_1_s1/Q
0.933 0.002 tNET RR 1 R12C14[1][A] i9/n23_s13/I3
1.305 0.372 tINS RF 1 R12C14[1][A] i9/n23_s13/F
1.305 0.000 tNET FF 1 R12C14[1][A] i9/col_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R12C14[1][A] i9/col_1_s1/CLK
0.597 0.000 tHld 1 R12C14[1][A] i9/col_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%

Path20

Path Summary:

Slack 0.708
Data Arrival Time 1.305
Data Required Time 0.597
From i9/col_3_s1
To i9/col_3_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R13C15[1][A] i9/col_3_s1/CLK
0.930 0.333 tC2Q RR 2 R13C15[1][A] i9/col_3_s1/Q
0.933 0.002 tNET RR 1 R13C15[1][A] i9/n23_s11/I0
1.305 0.372 tINS RF 1 R13C15[1][A] i9/n23_s11/F
1.305 0.000 tNET FF 1 R13C15[1][A] i9/col_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R13C15[1][A] i9/col_3_s1/CLK
0.597 0.000 tHld 1 R13C15[1][A] i9/col_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%

Path21

Path Summary:

Slack 0.711
Data Arrival Time 1.308
Data Required Time 0.597
From i9/index_1_s0
To i9/index_1_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R11C13[1][A] i9/index_1_s0/CLK
0.930 0.333 tC2Q RR 11 R11C13[1][A] i9/index_1_s0/Q
0.936 0.006 tNET RR 1 R11C13[1][A] i9/n132_s0/I1
1.308 0.372 tINS RF 1 R11C13[1][A] i9/n132_s0/F
1.308 0.000 tNET FF 1 R11C13[1][A] i9/index_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R11C13[1][A] i9/index_1_s0/CLK
0.597 0.000 tHld 1 R11C13[1][A] i9/index_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%

Path22

Path Summary:

Slack 0.894
Data Arrival Time 1.491
Data Required Time 0.597
From i9/index_2_s0
To i9/index_2_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R12C14[2][A] i9/index_2_s0/CLK
0.930 0.333 tC2Q RR 8 R12C14[2][A] i9/index_2_s0/Q
0.935 0.005 tNET RR 1 R12C14[2][A] i9/n131_s0/I2
1.491 0.556 tINS RR 1 R12C14[2][A] i9/n131_s0/F
1.491 0.000 tNET RR 1 R12C14[2][A] i9/index_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R12C14[2][A] i9/index_2_s0/CLK
0.597 0.000 tHld 1 R12C14[2][A] i9/index_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%
Arrival Data Path Delay cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%

Path23

Path Summary:

Slack 0.970
Data Arrival Time 1.567
Data Required Time 0.597
From i9/tmp_2_s1
To i9/key_2_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R11C16[1][A] i9/tmp_2_s1/CLK
0.930 0.333 tC2Q RR 1 R11C16[1][A] i9/tmp_2_s1/Q
1.195 0.265 tNET RR 1 R9C16[0][B] i9/n111_s3/I
1.567 0.372 tINS RF 1 R9C16[0][B] i9/n111_s3/O
1.567 0.000 tNET FF 1 R9C16[0][B] i9/key_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R9C16[0][B] i9/key_2_s0/CLK
0.597 0.000 tHld 1 R9C16[0][B] i9/key_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%
Arrival Data Path Delay cell: 0.372, 38.340%; route: 0.265, 27.305%; tC2Q: 0.333, 34.355%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%

Path24

Path Summary:

Slack 0.970
Data Arrival Time 1.567
Data Required Time 0.597
From i9/tmp_3_s1
To i9/key_3_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R11C16[0][A] i9/tmp_3_s1/CLK
0.930 0.333 tC2Q RR 1 R11C16[0][A] i9/tmp_3_s1/Q
1.195 0.265 tNET RR 1 R9C16[1][A] i9/n110_s3/I
1.567 0.372 tINS RF 1 R9C16[1][A] i9/n110_s3/O
1.567 0.000 tNET FF 1 R9C16[1][A] i9/key_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R9C16[1][A] i9/key_3_s0/CLK
0.597 0.000 tHld 1 R9C16[1][A] i9/key_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%
Arrival Data Path Delay cell: 0.372, 38.340%; route: 0.265, 27.305%; tC2Q: 0.333, 34.355%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%

Path25

Path Summary:

Slack 0.970
Data Arrival Time 1.567
Data Required Time 0.597
From i9/tmp_9_s1
To i9/key_9_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R12C15[0][A] i9/tmp_9_s1/CLK
0.930 0.333 tC2Q RR 1 R12C15[0][A] i9/tmp_9_s1/Q
1.195 0.265 tNET RR 1 R12C13[1][A] i9/n104_s3/I
1.567 0.372 tINS RF 1 R12C13[1][A] i9/n104_s3/O
1.567 0.000 tNET FF 1 R12C13[1][A] i9/key_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 57 R11C18[1][B] inst1/clk50hz_s/F
0.597 0.597 tNET RR 1 R12C13[1][A] i9/key_9_s0/CLK
0.597 0.000 tHld 1 R12C13[1][A] i9/key_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%
Arrival Data Path Delay cell: 0.372, 38.340%; route: 0.265, 27.305%; tC2Q: 0.333, 34.355%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.597, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_17_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_17_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_17_s0/CLK

MPW2

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_15_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_15_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_15_s0/CLK

MPW3

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_11_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_11_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_11_s0/CLK

MPW4

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_3_s0/CLK

MPW5

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_4_s0/CLK

MPW6

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_12_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_12_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_12_s0/CLK

MPW7

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_5_s0/CLK

MPW8

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_6_s0/CLK

MPW9

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_16_s0/CLK

MPW10

MPW Summary:

Slack: 2.911
Actual Width: 4.161
Required Width: 1.250
Type: Low Pulse Width
Clock: clk
Objects: inst1/count_13_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.984 0.984 tINS FF clk_ibuf/O
7.489 1.505 tNET FF inst1/count_13_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.844 0.844 tINS RR clk_ibuf/O
11.651 0.806 tNET RR inst1/count_13_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
57 clk50hz 4.414 1.244
18 clk_d 2.202 1.505
17 key_15_5 6.510 2.125
16 index[0] 5.835 0.855
11 index[1] 6.510 1.959
8 index[2] 6.736 0.836
6 count[7] 2.274 0.827
6 n48_9 2.202 0.996
6 n51_6 2.202 0.832
5 count[8] 3.080 0.827

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R11C9 29.17%
R12C13 29.17%
R11C17 26.39%
R12C14 26.39%
R12C18 26.39%
R9C9 25.00%
R12C15 23.61%
R11C14 23.61%
R11C15 22.22%
R9C10 20.83%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command