Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Workspace\organ\src\clkdiv.v
C:\Gowin\Workspace\organ\src\debounce.v
C:\Gowin\Workspace\organ\src\decdiv.v
C:\Gowin\Workspace\organ\src\organ.v
C:\Gowin\Workspace\organ\src\toggle.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.06Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Sat Jun 05 15:43:09 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module organ
Synthesis Process Running parser:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.262s, Peak memory usage = 63.227MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 63.227MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 63.227MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 63.227MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 63.227MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 63.227MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 63.227MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 63.227MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 63.227MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 63.227MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 63.227MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.786s, Peak memory usage = 78.684MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 78.684MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 78.684MB
Total Time and Memory Usage CPU time = 0h 0m 0.92s, Elapsed time = 0h 0m 1s, Peak memory usage = 78.684MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 10
I/O Buf 10
    IBUF 9
    OBUF 1
Register 26
    DFF 1
    DFFS 1
    DFFR 24
LUT 53
    LUT2 5
    LUT3 14
    LUT4 34
ALU 23
    ALU 23
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 77(54 LUTs, 23 ALUs) / 4608 2%
Register 26 / 3756 1%
  --Register as Latch 0 / 3756 0%
  --Register as FF 26 / 3756 1%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 97.4(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.267
Data Arrival Time 11.212
Data Required Time 10.945
From clkdiv_1/count_0_s0
To toggle_1/out_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 26 clk_ibuf/O
1.345 0.363 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.803 0.458 tC2Q RF 3 clkdiv_1/count_0_s0/Q
2.283 0.480 tNET FF 1 clkdiv_1/n80_s101/I0
3.315 1.032 tINS FF 1 clkdiv_1/n80_s101/F
3.795 0.480 tNET FF 1 clkdiv_1/n80_s79/I2
4.617 0.822 tINS FF 1 clkdiv_1/n80_s79/F
5.097 0.480 tNET FF 1 clkdiv_1/n80_s69/I1
6.196 1.099 tINS FF 1 clkdiv_1/n80_s69/F
6.676 0.480 tNET FF 1 clkdiv_1/n80_s66/I0
7.708 1.032 tINS FF 2 clkdiv_1/n80_s66/F
8.188 0.480 tNET FF 1 toggle_1/n9_s1/I0
9.220 1.032 tINS FF 1 toggle_1/n9_s1/F
9.700 0.480 tNET FF 1 toggle_1/n9_s0/I0
10.732 1.032 tINS FF 1 toggle_1/n9_s0/F
11.212 0.480 tNET FF 1 toggle_1/out_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 26 clk_ibuf/O
11.345 0.363 tNET RR 1 toggle_1/out_s0/CLK
10.945 -0.400 tSu 1 toggle_1/out_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 6.049, 61.303%; route: 3.360, 34.052%; tC2Q: 0.458, 4.645%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 0.177
Data Arrival Time 11.124
Data Required Time 11.302
From clkdiv_1/count_0_s0
To clkdiv_1/count_23_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 26 clk_ibuf/O
1.345 0.363 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.803 0.458 tC2Q RF 3 clkdiv_1/count_0_s0/Q
2.283 0.480 tNET FF 1 clkdiv_1/n80_s101/I0
3.315 1.032 tINS FF 1 clkdiv_1/n80_s101/F
3.795 0.480 tNET FF 1 clkdiv_1/n80_s79/I2
4.617 0.822 tINS FF 1 clkdiv_1/n80_s79/F
5.097 0.480 tNET FF 1 clkdiv_1/n80_s69/I1
6.196 1.099 tINS FF 1 clkdiv_1/n80_s69/F
6.676 0.480 tNET FF 1 clkdiv_1/n80_s66/I0
7.708 1.032 tINS FF 2 clkdiv_1/n80_s66/F
8.188 0.480 tNET FF 1 clkdiv_1/n80_s65/I0
9.220 1.032 tINS FF 2 clkdiv_1/n80_s65/F
9.700 0.480 tNET FF 1 clkdiv_1/tc_Z_s/I1
10.761 1.061 tINS FR 24 clkdiv_1/tc_Z_s/F
11.124 0.363 tNET RR 1 clkdiv_1/count_23_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 26 clk_ibuf/O
11.345 0.363 tNET RR 1 clkdiv_1/count_23_s0/CLK
11.302 -0.043 tSu 1 clkdiv_1/count_23_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 6.078, 62.151%; route: 3.243, 33.162%; tC2Q: 0.458, 4.687%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 0.177
Data Arrival Time 11.124
Data Required Time 11.302
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 26 clk_ibuf/O
1.345 0.363 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.803 0.458 tC2Q RF 3 clkdiv_1/count_0_s0/Q
2.283 0.480 tNET FF 1 clkdiv_1/n80_s101/I0
3.315 1.032 tINS FF 1 clkdiv_1/n80_s101/F
3.795 0.480 tNET FF 1 clkdiv_1/n80_s79/I2
4.617 0.822 tINS FF 1 clkdiv_1/n80_s79/F
5.097 0.480 tNET FF 1 clkdiv_1/n80_s69/I1
6.196 1.099 tINS FF 1 clkdiv_1/n80_s69/F
6.676 0.480 tNET FF 1 clkdiv_1/n80_s66/I0
7.708 1.032 tINS FF 2 clkdiv_1/n80_s66/F
8.188 0.480 tNET FF 1 clkdiv_1/n80_s65/I0
9.220 1.032 tINS FF 2 clkdiv_1/n80_s65/F
9.700 0.480 tNET FF 1 clkdiv_1/tc_Z_s/I1
10.761 1.061 tINS FR 24 clkdiv_1/tc_Z_s/F
11.124 0.363 tNET RR 1 clkdiv_1/count_0_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 26 clk_ibuf/O
11.345 0.363 tNET RR 1 clkdiv_1/count_0_s0/CLK
11.302 -0.043 tSu 1 clkdiv_1/count_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 6.078, 62.151%; route: 3.243, 33.162%; tC2Q: 0.458, 4.687%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 0.177
Data Arrival Time 11.124
Data Required Time 11.302
From clkdiv_1/count_0_s0
To clkdiv_1/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 26 clk_ibuf/O
1.345 0.363 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.803 0.458 tC2Q RF 3 clkdiv_1/count_0_s0/Q
2.283 0.480 tNET FF 1 clkdiv_1/n80_s101/I0
3.315 1.032 tINS FF 1 clkdiv_1/n80_s101/F
3.795 0.480 tNET FF 1 clkdiv_1/n80_s79/I2
4.617 0.822 tINS FF 1 clkdiv_1/n80_s79/F
5.097 0.480 tNET FF 1 clkdiv_1/n80_s69/I1
6.196 1.099 tINS FF 1 clkdiv_1/n80_s69/F
6.676 0.480 tNET FF 1 clkdiv_1/n80_s66/I0
7.708 1.032 tINS FF 2 clkdiv_1/n80_s66/F
8.188 0.480 tNET FF 1 clkdiv_1/n80_s65/I0
9.220 1.032 tINS FF 2 clkdiv_1/n80_s65/F
9.700 0.480 tNET FF 1 clkdiv_1/tc_Z_s/I1
10.761 1.061 tINS FR 24 clkdiv_1/tc_Z_s/F
11.124 0.363 tNET RR 1 clkdiv_1/count_1_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 26 clk_ibuf/O
11.345 0.363 tNET RR 1 clkdiv_1/count_1_s0/CLK
11.302 -0.043 tSu 1 clkdiv_1/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 6.078, 62.151%; route: 3.243, 33.162%; tC2Q: 0.458, 4.687%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 0.177
Data Arrival Time 11.124
Data Required Time 11.302
From clkdiv_1/count_0_s0
To clkdiv_1/count_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 26 clk_ibuf/O
1.345 0.363 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.803 0.458 tC2Q RF 3 clkdiv_1/count_0_s0/Q
2.283 0.480 tNET FF 1 clkdiv_1/n80_s101/I0
3.315 1.032 tINS FF 1 clkdiv_1/n80_s101/F
3.795 0.480 tNET FF 1 clkdiv_1/n80_s79/I2
4.617 0.822 tINS FF 1 clkdiv_1/n80_s79/F
5.097 0.480 tNET FF 1 clkdiv_1/n80_s69/I1
6.196 1.099 tINS FF 1 clkdiv_1/n80_s69/F
6.676 0.480 tNET FF 1 clkdiv_1/n80_s66/I0
7.708 1.032 tINS FF 2 clkdiv_1/n80_s66/F
8.188 0.480 tNET FF 1 clkdiv_1/n80_s65/I0
9.220 1.032 tINS FF 2 clkdiv_1/n80_s65/F
9.700 0.480 tNET FF 1 clkdiv_1/tc_Z_s/I1
10.761 1.061 tINS FR 24 clkdiv_1/tc_Z_s/F
11.124 0.363 tNET RR 1 clkdiv_1/count_2_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 26 clk_ibuf/O
11.345 0.363 tNET RR 1 clkdiv_1/count_2_s0/CLK
11.302 -0.043 tSu 1 clkdiv_1/count_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 6.078, 62.151%; route: 3.243, 33.162%; tC2Q: 0.458, 4.687%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%