Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	C:\Gowin\Workspace\organ\impl\gwsynthesis\organ.vg
Physical Constraints File	C:\Gowin\Workspace\organ\src\organ.cst
Timing Constraint File	---
GOWIN version	V1.9.7.06Beta
Part Number	GW1N-UV4LQ144C6/I5
Device	GW1N-4B
Created Time	Sat Jun 05 15:43:14 2021
Legal Announcement	Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 2.375V 85C
Hold Delay Model	Fast 2.625V 0C
Numbers of Paths Analyzed	261
Numbers of Endpoints Analyzed	52
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	25
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	96.707(MHz)	7	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	-7.734	25
clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_23_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
2	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_6_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
3	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_7_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
4	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_8_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
5	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_9_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
6	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_10_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
7	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_11_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
8	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_18_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
9	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_19_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
10	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_20_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
11	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_21_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
12	-0.340	clkdiv_1/count_10_s0/Q	clkdiv_1/count_22_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.297
13	-0.331	clkdiv_1/count_10_s0/Q	clkdiv_1/count_0_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.288
14	-0.296	clkdiv_1/count_10_s0/Q	clkdiv_1/count_1_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.252
15	-0.296	clkdiv_1/count_10_s0/Q	clkdiv_1/count_2_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.252
16	-0.296	clkdiv_1/count_10_s0/Q	clkdiv_1/count_3_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.252
17	-0.296	clkdiv_1/count_10_s0/Q	clkdiv_1/count_4_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.252
18	-0.296	clkdiv_1/count_10_s0/Q	clkdiv_1/count_5_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.252
19	-0.268	clkdiv_1/count_10_s0/Q	clkdiv_1/count_12_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.225
20	-0.268	clkdiv_1/count_10_s0/Q	clkdiv_1/count_13_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.225
21	-0.268	clkdiv_1/count_10_s0/Q	clkdiv_1/count_14_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.225
22	-0.268	clkdiv_1/count_10_s0/Q	clkdiv_1/count_15_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.225
23	-0.268	clkdiv_1/count_10_s0/Q	clkdiv_1/count_16_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.225
24	-0.268	clkdiv_1/count_10_s0/Q	clkdiv_1/count_17_s0/RESET	clk:[R]	clk:[R]	10.000	0.000	10.225
25	-0.230	clkdiv_1/count_10_s0/Q	toggle_1/out_s0/D	clk:[R]	clk:[R]	10.000	0.000	9.830

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.730	clkdiv_1/count_2_s0/Q	clkdiv_1/count_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
2	0.730	clkdiv_1/count_6_s0/Q	clkdiv_1/count_6_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
3	0.730	clkdiv_1/count_8_s0/Q	clkdiv_1/count_8_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
4	0.730	clkdiv_1/count_14_s0/Q	clkdiv_1/count_14_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
5	0.730	clkdiv_1/count_18_s0/Q	clkdiv_1/count_18_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
6	0.730	clkdiv_1/count_20_s0/Q	clkdiv_1/count_20_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.730
7	0.731	clkdiv_1/count_12_s0/Q	clkdiv_1/count_12_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.731
8	0.853	clkdiv_1/count_1_s0/Q	clkdiv_1/count_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.853
9	0.895	clkdiv_1/count_23_s0/Q	toggle_1/prev_in_s1/SET	clk:[R]	clk:[R]	0.000	0.000	0.910
10	0.942	toggle_1/prev_in_s1/Q	toggle_1/out_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.942
11	0.959	clkdiv_1/count_7_s0/Q	clkdiv_1/count_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.959
12	0.962	clkdiv_1/count_5_s0/Q	clkdiv_1/count_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.962
13	0.962	clkdiv_1/count_9_s0/Q	clkdiv_1/count_9_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.962
14	0.962	clkdiv_1/count_15_s0/Q	clkdiv_1/count_15_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.962
15	0.965	clkdiv_1/count_3_s0/Q	clkdiv_1/count_3_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.965
16	0.965	clkdiv_1/count_11_s0/Q	clkdiv_1/count_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.965
17	0.965	clkdiv_1/count_13_s0/Q	clkdiv_1/count_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.965
18	0.965	clkdiv_1/count_17_s0/Q	clkdiv_1/count_17_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.965
19	0.965	clkdiv_1/count_21_s0/Q	clkdiv_1/count_21_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.965
20	0.965	clkdiv_1/count_22_s0/Q	clkdiv_1/count_22_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.965
21	0.966	clkdiv_1/count_23_s0/Q	clkdiv_1/count_23_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.966
22	0.966	clkdiv_1/count_4_s0/Q	clkdiv_1/count_4_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.966
23	0.966	clkdiv_1/count_10_s0/Q	clkdiv_1/count_10_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.966
24	0.970	clkdiv_1/count_16_s0/Q	clkdiv_1/count_16_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.970
25	1.063	clkdiv_1/count_0_s0/Q	clkdiv_1/count_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.063

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_22_s0
2	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_20_s0
3	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_16_s0
4	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_8_s0
5	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_9_s0
6	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_17_s0
7	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_10_s0
8	2.911	4.161	1.250	Low Pulse Width	clk	toggle_1/prev_in_s1
9	2.911	4.161	1.250	Low Pulse Width	clk	clkdiv_1/count_11_s0
10	2.911	4.161	1.250	Low Pulse Width	clk	toggle_1/out_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C12[2][B]	clkdiv_1/count_23_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C12[2][B]	clkdiv_1/count_23_s0/CLK
12.087	-0.043	tSu		1	R11C12[2][B]	clkdiv_1/count_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path2

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/CLK
12.087	-0.043	tSu		1	R11C10[0][A]	clkdiv_1/count_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path3

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/CLK
12.087	-0.043	tSu		1	R11C10[0][B]	clkdiv_1/count_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path4

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
12.087	-0.043	tSu		1	R11C10[1][A]	clkdiv_1/count_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path5

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/CLK
12.087	-0.043	tSu		1	R11C10[1][B]	clkdiv_1/count_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path6

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
12.087	-0.043	tSu		1	R11C10[2][A]	clkdiv_1/count_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path7

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C10[2][B]	clkdiv_1/count_11_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C10[2][B]	clkdiv_1/count_11_s0/CLK
12.087	-0.043	tSu		1	R11C10[2][B]	clkdiv_1/count_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path8

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C12[0][A]	clkdiv_1/count_18_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C12[0][A]	clkdiv_1/count_18_s0/CLK
12.087	-0.043	tSu		1	R11C12[0][A]	clkdiv_1/count_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path9

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C12[0][B]	clkdiv_1/count_19_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C12[0][B]	clkdiv_1/count_19_s0/CLK
12.087	-0.043	tSu		1	R11C12[0][B]	clkdiv_1/count_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path10

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C12[1][A]	clkdiv_1/count_20_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C12[1][A]	clkdiv_1/count_20_s0/CLK
12.087	-0.043	tSu		1	R11C12[1][A]	clkdiv_1/count_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path11

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C12[1][B]	clkdiv_1/count_21_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C12[1][B]	clkdiv_1/count_21_s0/CLK
12.087	-0.043	tSu		1	R11C12[1][B]	clkdiv_1/count_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path12

Path Summary:

Slack	-0.340
Data Arrival Time	12.427
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.427	0.801	tNET	RR	1	R11C12[2][A]	clkdiv_1/count_22_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C12[2][A]	clkdiv_1/count_22_s0/CLK
12.087	-0.043	tSu		1	R11C12[2][A]	clkdiv_1/count_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.867%; route: 5.219, 50.682%; tC2Q: 0.458, 4.451%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path13

Path Summary:

Slack	-0.331
Data Arrival Time	12.418
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.418	0.792	tNET	RR	1	R12C11[2][B]	clkdiv_1/count_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R12C11[2][B]	clkdiv_1/count_0_s0/CLK
12.087	-0.043	tSu		1	R12C11[2][B]	clkdiv_1/count_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 44.907%; route: 5.210, 50.638%; tC2Q: 0.458, 4.455%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path14

Path Summary:

Slack	-0.296
Data Arrival Time	12.383
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.383	0.757	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
12.087	-0.043	tSu		1	R11C9[0][B]	clkdiv_1/count_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.063%; route: 5.174, 50.467%; tC2Q: 0.458, 4.471%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path15

Path Summary:

Slack	-0.296
Data Arrival Time	12.383
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.383	0.757	tNET	RR	1	R11C9[1][A]	clkdiv_1/count_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[1][A]	clkdiv_1/count_2_s0/CLK
12.087	-0.043	tSu		1	R11C9[1][A]	clkdiv_1/count_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.063%; route: 5.174, 50.467%; tC2Q: 0.458, 4.471%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path16

Path Summary:

Slack	-0.296
Data Arrival Time	12.383
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.383	0.757	tNET	RR	1	R11C9[1][B]	clkdiv_1/count_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[1][B]	clkdiv_1/count_3_s0/CLK
12.087	-0.043	tSu		1	R11C9[1][B]	clkdiv_1/count_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.063%; route: 5.174, 50.467%; tC2Q: 0.458, 4.471%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path17

Path Summary:

Slack	-0.296
Data Arrival Time	12.383
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.383	0.757	tNET	RR	1	R11C9[2][A]	clkdiv_1/count_4_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[2][A]	clkdiv_1/count_4_s0/CLK
12.087	-0.043	tSu		1	R11C9[2][A]	clkdiv_1/count_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.063%; route: 5.174, 50.467%; tC2Q: 0.458, 4.471%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path18

Path Summary:

Slack	-0.296
Data Arrival Time	12.383
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.383	0.757	tNET	RR	1	R11C9[2][B]	clkdiv_1/count_5_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C9[2][B]	clkdiv_1/count_5_s0/CLK
12.087	-0.043	tSu		1	R11C9[2][B]	clkdiv_1/count_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.063%; route: 5.174, 50.467%; tC2Q: 0.458, 4.471%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path19

Path Summary:

Slack	-0.268
Data Arrival Time	12.355
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.355	0.729	tNET	RR	1	R11C11[0][A]	clkdiv_1/count_12_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C11[0][A]	clkdiv_1/count_12_s0/CLK
12.087	-0.043	tSu		1	R11C11[0][A]	clkdiv_1/count_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.185%; route: 5.146, 50.333%; tC2Q: 0.458, 4.483%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path20

Path Summary:

Slack	-0.268
Data Arrival Time	12.355
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.355	0.729	tNET	RR	1	R11C11[0][B]	clkdiv_1/count_13_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C11[0][B]	clkdiv_1/count_13_s0/CLK
12.087	-0.043	tSu		1	R11C11[0][B]	clkdiv_1/count_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.185%; route: 5.146, 50.333%; tC2Q: 0.458, 4.483%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path21

Path Summary:

Slack	-0.268
Data Arrival Time	12.355
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.355	0.729	tNET	RR	1	R11C11[1][A]	clkdiv_1/count_14_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C11[1][A]	clkdiv_1/count_14_s0/CLK
12.087	-0.043	tSu		1	R11C11[1][A]	clkdiv_1/count_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.185%; route: 5.146, 50.333%; tC2Q: 0.458, 4.483%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path22

Path Summary:

Slack	-0.268
Data Arrival Time	12.355
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.355	0.729	tNET	RR	1	R11C11[1][B]	clkdiv_1/count_15_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C11[1][B]	clkdiv_1/count_15_s0/CLK
12.087	-0.043	tSu		1	R11C11[1][B]	clkdiv_1/count_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.185%; route: 5.146, 50.333%; tC2Q: 0.458, 4.483%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path23

Path Summary:

Slack	-0.268
Data Arrival Time	12.355
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.355	0.729	tNET	RR	1	R11C11[2][A]	clkdiv_1/count_16_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C11[2][A]	clkdiv_1/count_16_s0/CLK
12.087	-0.043	tSu		1	R11C11[2][A]	clkdiv_1/count_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.185%; route: 5.146, 50.333%; tC2Q: 0.458, 4.483%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path24

Path Summary:

Slack	-0.268
Data Arrival Time	12.355
Data Required Time	12.087
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[0][A]	clkdiv_1/n80_s65/I1
10.990	1.099	tINS	FF	2	R9C11[0][A]	clkdiv_1/n80_s65/F
11.001	0.011	tNET	FF	1	R9C11[0][B]	clkdiv_1/tc_Z_s/I1
11.626	0.625	tINS	FR	24	R9C11[0][B]	clkdiv_1/tc_Z_s/F
12.355	0.729	tNET	RR	1	R11C11[2][B]	clkdiv_1/count_17_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R11C11[2][B]	clkdiv_1/count_17_s0/CLK
12.087	-0.043	tSu		1	R11C11[2][B]	clkdiv_1/count_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.620, 45.185%; route: 5.146, 50.333%; tC2Q: 0.458, 4.483%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Path25

Path Summary:

Slack	-0.230
Data Arrival Time	11.960
Data Required Time	11.730
From	clkdiv_1/count_10_s0
To	toggle_1/out_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
2.130	1.148	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
2.588	0.458	tC2Q	RF	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
3.400	0.811	tNET	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/I3
4.222	0.822	tINS	FF	1	R11C13[1][B]	clkdiv_1/n80_s104/F
5.042	0.821	tNET	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/I2
5.668	0.626	tINS	FF	1	R11C14[3][B]	clkdiv_1/n80_s92/F
6.473	0.804	tNET	FF	1	R11C17[0][B]	clkdiv_1/n80_s74/I3
7.295	0.822	tINS	FF	2	R11C17[0][B]	clkdiv_1/n80_s74/F
8.121	0.826	tNET	FF	1	R11C15[1][A]	clkdiv_1/n80_s67/I2
8.747	0.626	tINS	FF	2	R11C15[1][A]	clkdiv_1/n80_s67/F
9.891	1.144	tNET	FF	1	R9C11[3][B]	toggle_1/n9_s1/I1
10.923	1.032	tINS	FF	1	R9C11[3][B]	toggle_1/n9_s1/F
10.928	0.005	tNET	FF	1	R9C11[1][B]	toggle_1/n9_s0/I0
11.960	1.032	tINS	FF	1	R9C11[1][B]	toggle_1/n9_s0/F
11.960	0.000	tNET	FF	1	R9C11[1][B]	toggle_1/out_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
10.982	0.982	tINS	RR	26	IOL3[A]	clk_ibuf/O
12.130	1.148	tNET	RR	1	R9C11[1][B]	toggle_1/out_s0/CLK
11.730	-0.400	tSu		1	R9C11[1][B]	toggle_1/out_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%
Arrival Data Path Delay	cell: 4.960, 50.457%; route: 4.412, 44.881%; tC2Q: 0.458, 4.662%
Required Clock Path Delay	cell: 0.982, 46.094%; route: 1.148, 53.906%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_2_s0
To	clkdiv_1/count_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[1][A]	clkdiv_1/count_2_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C9[1][A]	clkdiv_1/count_2_s0/Q
1.986	0.002	tNET	RR	2	R11C9[1][A]	clkdiv_1/n29_s/I1
2.380	0.394	tINS	RF	1	R11C9[1][A]	clkdiv_1/n29_s/SUM
2.380	0.000	tNET	FF	1	R11C9[1][A]	clkdiv_1/count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[1][A]	clkdiv_1/count_2_s0/CLK
1.651	0.000	tHld		1	R11C9[1][A]	clkdiv_1/count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path2

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_6_s0
To	clkdiv_1/count_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[0][A]	clkdiv_1/count_6_s0/Q
1.986	0.002	tNET	RR	2	R11C10[0][A]	clkdiv_1/n25_s/I1
2.380	0.394	tINS	RF	1	R11C10[0][A]	clkdiv_1/n25_s/SUM
2.380	0.000	tNET	FF	1	R11C10[0][A]	clkdiv_1/count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][A]	clkdiv_1/count_6_s0/CLK
1.651	0.000	tHld		1	R11C10[0][A]	clkdiv_1/count_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path3

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_8_s0
To	clkdiv_1/count_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
1.984	0.333	tC2Q	RR	4	R11C10[1][A]	clkdiv_1/count_8_s0/Q
1.986	0.002	tNET	RR	2	R11C10[1][A]	clkdiv_1/n23_s/I1
2.380	0.394	tINS	RF	1	R11C10[1][A]	clkdiv_1/n23_s/SUM
2.380	0.000	tNET	FF	1	R11C10[1][A]	clkdiv_1/count_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][A]	clkdiv_1/count_8_s0/CLK
1.651	0.000	tHld		1	R11C10[1][A]	clkdiv_1/count_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path4

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_14_s0
To	clkdiv_1/count_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[1][A]	clkdiv_1/count_14_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C11[1][A]	clkdiv_1/count_14_s0/Q
1.986	0.002	tNET	RR	2	R11C11[1][A]	clkdiv_1/n17_s/I1
2.380	0.394	tINS	RF	1	R11C11[1][A]	clkdiv_1/n17_s/SUM
2.380	0.000	tNET	FF	1	R11C11[1][A]	clkdiv_1/count_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[1][A]	clkdiv_1/count_14_s0/CLK
1.651	0.000	tHld		1	R11C11[1][A]	clkdiv_1/count_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path5

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_18_s0
To	clkdiv_1/count_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[0][A]	clkdiv_1/count_18_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C12[0][A]	clkdiv_1/count_18_s0/Q
1.986	0.002	tNET	RR	2	R11C12[0][A]	clkdiv_1/n13_s/I1
2.380	0.394	tINS	RF	1	R11C12[0][A]	clkdiv_1/n13_s/SUM
2.380	0.000	tNET	FF	1	R11C12[0][A]	clkdiv_1/count_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[0][A]	clkdiv_1/count_18_s0/CLK
1.651	0.000	tHld		1	R11C12[0][A]	clkdiv_1/count_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path6

Path Summary:

Slack	0.730
Data Arrival Time	2.380
Data Required Time	1.651
From	clkdiv_1/count_20_s0
To	clkdiv_1/count_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[1][A]	clkdiv_1/count_20_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C12[1][A]	clkdiv_1/count_20_s0/Q
1.986	0.002	tNET	RR	2	R11C12[1][A]	clkdiv_1/n11_s/I1
2.380	0.394	tINS	RF	1	R11C12[1][A]	clkdiv_1/n11_s/SUM
2.380	0.000	tNET	FF	1	R11C12[1][A]	clkdiv_1/count_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[1][A]	clkdiv_1/count_20_s0/CLK
1.651	0.000	tHld		1	R11C12[1][A]	clkdiv_1/count_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path7

Path Summary:

Slack	0.731
Data Arrival Time	2.382
Data Required Time	1.651
From	clkdiv_1/count_12_s0
To	clkdiv_1/count_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[0][A]	clkdiv_1/count_12_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C11[0][A]	clkdiv_1/count_12_s0/Q
1.988	0.004	tNET	RR	2	R11C11[0][A]	clkdiv_1/n19_s/I1
2.382	0.394	tINS	RF	1	R11C11[0][A]	clkdiv_1/n19_s/SUM
2.382	0.000	tNET	FF	1	R11C11[0][A]	clkdiv_1/count_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[0][A]	clkdiv_1/count_12_s0/CLK
1.651	0.000	tHld		1	R11C11[0][A]	clkdiv_1/count_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 53.908%; route: 0.004, 0.485%; tC2Q: 0.333, 45.607%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path8

Path Summary:

Slack	0.853
Data Arrival Time	2.503
Data Required Time	1.651
From	clkdiv_1/count_1_s0
To	clkdiv_1/count_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C9[0][B]	clkdiv_1/count_1_s0/Q
1.986	0.002	tNET	RR	2	R11C9[0][B]	clkdiv_1/n30_s/I0
2.503	0.517	tINS	RF	1	R11C9[0][B]	clkdiv_1/n30_s/SUM
2.503	0.000	tNET	FF	1	R11C9[0][B]	clkdiv_1/count_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[0][B]	clkdiv_1/count_1_s0/CLK
1.651	0.000	tHld		1	R11C9[0][B]	clkdiv_1/count_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path9

Path Summary:

Slack	0.895
Data Arrival Time	2.561
Data Required Time	1.666
From	clkdiv_1/count_23_s0
To	toggle_1/prev_in_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[2][B]	clkdiv_1/count_23_s0/CLK
1.984	0.333	tC2Q	RR	4	R11C12[2][B]	clkdiv_1/count_23_s0/Q
2.561	0.576	tNET	RR	1	R9C11[2][A]	toggle_1/prev_in_s1/SET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C11[2][A]	toggle_1/prev_in_s1/CLK
1.666	0.015	tHld		1	R9C11[2][A]	toggle_1/prev_in_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.576, 63.363%; tC2Q: 0.333, 36.637%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path10

Path Summary:

Slack	0.942
Data Arrival Time	2.592
Data Required Time	1.651
From	toggle_1/prev_in_s1
To	toggle_1/out_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C11[2][A]	toggle_1/prev_in_s1/CLK
1.984	0.333	tC2Q	RR	1	R9C11[2][A]	toggle_1/prev_in_s1/Q
2.220	0.236	tNET	RR	1	R9C11[1][B]	toggle_1/n9_s0/I1
2.592	0.372	tINS	RF	1	R9C11[1][B]	toggle_1/n9_s0/F
2.592	0.000	tNET	FF	1	R9C11[1][B]	toggle_1/out_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R9C11[1][B]	toggle_1/out_s0/CLK
1.651	0.000	tHld		1	R9C11[1][B]	toggle_1/out_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.372, 39.502%; route: 0.236, 25.102%; tC2Q: 0.333, 35.396%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path11

Path Summary:

Slack	0.959
Data Arrival Time	2.609
Data Required Time	1.651
From	clkdiv_1/count_7_s0
To	clkdiv_1/count_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/CLK
1.984	0.333	tC2Q	RF	3	R11C10[0][B]	clkdiv_1/count_7_s0/Q
2.215	0.231	tNET	FF	2	R11C10[0][B]	clkdiv_1/n24_s/I1
2.609	0.394	tINS	FF	1	R11C10[0][B]	clkdiv_1/n24_s/SUM
2.609	0.000	tNET	FF	1	R11C10[0][B]	clkdiv_1/count_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[0][B]	clkdiv_1/count_7_s0/CLK
1.651	0.000	tHld		1	R11C10[0][B]	clkdiv_1/count_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 41.102%; route: 0.231, 24.124%; tC2Q: 0.333, 34.773%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path12

Path Summary:

Slack	0.962
Data Arrival Time	2.613
Data Required Time	1.651
From	clkdiv_1/count_5_s0
To	clkdiv_1/count_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[2][B]	clkdiv_1/count_5_s0/CLK
1.984	0.333	tC2Q	RF	3	R11C9[2][B]	clkdiv_1/count_5_s0/Q
2.219	0.234	tNET	FF	2	R11C9[2][B]	clkdiv_1/n26_s/I1
2.613	0.394	tINS	FF	1	R11C9[2][B]	clkdiv_1/n26_s/SUM
2.613	0.000	tNET	FF	1	R11C9[2][B]	clkdiv_1/count_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[2][B]	clkdiv_1/count_5_s0/CLK
1.651	0.000	tHld		1	R11C9[2][B]	clkdiv_1/count_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path13

Path Summary:

Slack	0.962
Data Arrival Time	2.613
Data Required Time	1.651
From	clkdiv_1/count_9_s0
To	clkdiv_1/count_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/CLK
1.984	0.333	tC2Q	RF	3	R11C10[1][B]	clkdiv_1/count_9_s0/Q
2.219	0.234	tNET	FF	2	R11C10[1][B]	clkdiv_1/n22_s/I1
2.613	0.394	tINS	FF	1	R11C10[1][B]	clkdiv_1/n22_s/SUM
2.613	0.000	tNET	FF	1	R11C10[1][B]	clkdiv_1/count_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[1][B]	clkdiv_1/count_9_s0/CLK
1.651	0.000	tHld		1	R11C10[1][B]	clkdiv_1/count_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path14

Path Summary:

Slack	0.962
Data Arrival Time	2.613
Data Required Time	1.651
From	clkdiv_1/count_15_s0
To	clkdiv_1/count_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[1][B]	clkdiv_1/count_15_s0/CLK
1.984	0.333	tC2Q	RF	2	R11C11[1][B]	clkdiv_1/count_15_s0/Q
2.219	0.234	tNET	FF	2	R11C11[1][B]	clkdiv_1/n16_s/I1
2.613	0.394	tINS	FF	1	R11C11[1][B]	clkdiv_1/n16_s/SUM
2.613	0.000	tNET	FF	1	R11C11[1][B]	clkdiv_1/count_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[1][B]	clkdiv_1/count_15_s0/CLK
1.651	0.000	tHld		1	R11C11[1][B]	clkdiv_1/count_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path15

Path Summary:

Slack	0.965
Data Arrival Time	2.616
Data Required Time	1.651
From	clkdiv_1/count_3_s0
To	clkdiv_1/count_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[1][B]	clkdiv_1/count_3_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C9[1][B]	clkdiv_1/count_3_s0/Q
2.222	0.238	tNET	RR	2	R11C9[1][B]	clkdiv_1/n28_s/I1
2.616	0.394	tINS	RF	1	R11C9[1][B]	clkdiv_1/n28_s/SUM
2.616	0.000	tNET	FF	1	R11C9[1][B]	clkdiv_1/count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[1][B]	clkdiv_1/count_3_s0/CLK
1.651	0.000	tHld		1	R11C9[1][B]	clkdiv_1/count_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path16

Path Summary:

Slack	0.965
Data Arrival Time	2.616
Data Required Time	1.651
From	clkdiv_1/count_11_s0
To	clkdiv_1/count_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[2][B]	clkdiv_1/count_11_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[2][B]	clkdiv_1/count_11_s0/Q
2.222	0.238	tNET	RR	2	R11C10[2][B]	clkdiv_1/n20_s/I1
2.616	0.394	tINS	RF	1	R11C10[2][B]	clkdiv_1/n20_s/SUM
2.616	0.000	tNET	FF	1	R11C10[2][B]	clkdiv_1/count_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[2][B]	clkdiv_1/count_11_s0/CLK
1.651	0.000	tHld		1	R11C10[2][B]	clkdiv_1/count_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path17

Path Summary:

Slack	0.965
Data Arrival Time	2.616
Data Required Time	1.651
From	clkdiv_1/count_13_s0
To	clkdiv_1/count_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[0][B]	clkdiv_1/count_13_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C11[0][B]	clkdiv_1/count_13_s0/Q
2.222	0.238	tNET	RR	2	R11C11[0][B]	clkdiv_1/n18_s/I1
2.616	0.394	tINS	RF	1	R11C11[0][B]	clkdiv_1/n18_s/SUM
2.616	0.000	tNET	FF	1	R11C11[0][B]	clkdiv_1/count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[0][B]	clkdiv_1/count_13_s0/CLK
1.651	0.000	tHld		1	R11C11[0][B]	clkdiv_1/count_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path18

Path Summary:

Slack	0.965
Data Arrival Time	2.616
Data Required Time	1.651
From	clkdiv_1/count_17_s0
To	clkdiv_1/count_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[2][B]	clkdiv_1/count_17_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C11[2][B]	clkdiv_1/count_17_s0/Q
2.222	0.238	tNET	RR	2	R11C11[2][B]	clkdiv_1/n14_s/I1
2.616	0.394	tINS	RF	1	R11C11[2][B]	clkdiv_1/n14_s/SUM
2.616	0.000	tNET	FF	1	R11C11[2][B]	clkdiv_1/count_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[2][B]	clkdiv_1/count_17_s0/CLK
1.651	0.000	tHld		1	R11C11[2][B]	clkdiv_1/count_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path19

Path Summary:

Slack	0.965
Data Arrival Time	2.616
Data Required Time	1.651
From	clkdiv_1/count_21_s0
To	clkdiv_1/count_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[1][B]	clkdiv_1/count_21_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C12[1][B]	clkdiv_1/count_21_s0/Q
2.222	0.238	tNET	RR	2	R11C12[1][B]	clkdiv_1/n10_s/I1
2.616	0.394	tINS	RF	1	R11C12[1][B]	clkdiv_1/n10_s/SUM
2.616	0.000	tNET	FF	1	R11C12[1][B]	clkdiv_1/count_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[1][B]	clkdiv_1/count_21_s0/CLK
1.651	0.000	tHld		1	R11C12[1][B]	clkdiv_1/count_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path20

Path Summary:

Slack	0.965
Data Arrival Time	2.616
Data Required Time	1.651
From	clkdiv_1/count_22_s0
To	clkdiv_1/count_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[2][A]	clkdiv_1/count_22_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C12[2][A]	clkdiv_1/count_22_s0/Q
2.222	0.238	tNET	RR	2	R11C12[2][A]	clkdiv_1/n9_s/I1
2.616	0.394	tINS	RF	1	R11C12[2][A]	clkdiv_1/n9_s/SUM
2.616	0.000	tNET	FF	1	R11C12[2][A]	clkdiv_1/count_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[2][A]	clkdiv_1/count_22_s0/CLK
1.651	0.000	tHld		1	R11C12[2][A]	clkdiv_1/count_22_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path21

Path Summary:

Slack	0.966
Data Arrival Time	2.617
Data Required Time	1.651
From	clkdiv_1/count_23_s0
To	clkdiv_1/count_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[2][B]	clkdiv_1/count_23_s0/CLK
1.984	0.333	tC2Q	RR	4	R11C12[2][B]	clkdiv_1/count_23_s0/Q
2.223	0.239	tNET	RR	2	R11C12[2][B]	clkdiv_1/n8_s/I1
2.617	0.394	tINS	RF	1	R11C12[2][B]	clkdiv_1/n8_s/SUM
2.617	0.000	tNET	FF	1	R11C12[2][B]	clkdiv_1/count_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C12[2][B]	clkdiv_1/count_23_s0/CLK
1.651	0.000	tHld		1	R11C12[2][B]	clkdiv_1/count_23_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.783%; route: 0.239, 24.713%; tC2Q: 0.333, 34.503%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path22

Path Summary:

Slack	0.966
Data Arrival Time	2.617
Data Required Time	1.651
From	clkdiv_1/count_4_s0
To	clkdiv_1/count_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[2][A]	clkdiv_1/count_4_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C9[2][A]	clkdiv_1/count_4_s0/Q
2.223	0.239	tNET	RR	2	R11C9[2][A]	clkdiv_1/n27_s/I1
2.617	0.394	tINS	RF	1	R11C9[2][A]	clkdiv_1/n27_s/SUM
2.617	0.000	tNET	FF	1	R11C9[2][A]	clkdiv_1/count_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C9[2][A]	clkdiv_1/count_4_s0/CLK
1.651	0.000	tHld		1	R11C9[2][A]	clkdiv_1/count_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.783%; route: 0.239, 24.713%; tC2Q: 0.333, 34.503%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path23

Path Summary:

Slack	0.966
Data Arrival Time	2.617
Data Required Time	1.651
From	clkdiv_1/count_10_s0
To	clkdiv_1/count_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
1.984	0.333	tC2Q	RR	3	R11C10[2][A]	clkdiv_1/count_10_s0/Q
2.223	0.239	tNET	RR	2	R11C10[2][A]	clkdiv_1/n21_s/I1
2.617	0.394	tINS	RF	1	R11C10[2][A]	clkdiv_1/n21_s/SUM
2.617	0.000	tNET	FF	1	R11C10[2][A]	clkdiv_1/count_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C10[2][A]	clkdiv_1/count_10_s0/CLK
1.651	0.000	tHld		1	R11C10[2][A]	clkdiv_1/count_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.783%; route: 0.239, 24.713%; tC2Q: 0.333, 34.503%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path24

Path Summary:

Slack	0.970
Data Arrival Time	2.621
Data Required Time	1.651
From	clkdiv_1/count_16_s0
To	clkdiv_1/count_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[2][A]	clkdiv_1/count_16_s0/CLK
1.984	0.333	tC2Q	RR	2	R11C11[2][A]	clkdiv_1/count_16_s0/Q
2.227	0.243	tNET	RR	2	R11C11[2][A]	clkdiv_1/n15_s/I1
2.621	0.394	tINS	RF	1	R11C11[2][A]	clkdiv_1/n15_s/SUM
2.621	0.000	tNET	FF	1	R11C11[2][A]	clkdiv_1/count_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R11C11[2][A]	clkdiv_1/count_16_s0/CLK
1.651	0.000	tHld		1	R11C11[2][A]	clkdiv_1/count_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Path25

Path Summary:

Slack	1.063
Data Arrival Time	2.714
Data Required Time	1.651
From	clkdiv_1/count_0_s0
To	clkdiv_1/count_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R12C11[2][B]	clkdiv_1/count_0_s0/CLK
1.984	0.333	tC2Q	RR	3	R12C11[2][B]	clkdiv_1/count_0_s0/Q
1.988	0.004	tNET	RR	1	R12C11[2][B]	clkdiv_1/n31_s2/I
2.714	0.726	tINS	RR	1	R12C11[2][B]	clkdiv_1/n31_s2/O
2.714	0.000	tNET	RR	1	R12C11[2][B]	clkdiv_1/count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL3[A]	clk_ibuf/I
0.844	0.844	tINS	RR	26	IOL3[A]	clk_ibuf/O
1.651	0.806	tNET	RR	1	R12C11[2][B]	clkdiv_1/count_0_s0/CLK
1.651	0.000	tHld		1	R12C11[2][B]	clkdiv_1/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%
Arrival Data Path Delay	cell: 0.726, 68.305%; route: 0.004, 0.333%; tC2Q: 0.333, 31.361%
Required Clock Path Delay	cell: 0.844, 51.151%; route: 0.806, 48.849%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_22_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_22_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_22_s0/CLK

MPW2

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_20_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_20_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_20_s0/CLK

MPW3

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_16_s0/CLK

MPW4

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_8_s0/CLK

MPW5

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_9_s0/CLK

MPW6

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_17_s0/CLK

MPW7

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_10_s0/CLK

MPW8

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	toggle_1/prev_in_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	toggle_1/prev_in_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	toggle_1/prev_in_s1/CLK

MPW9

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	clkdiv_1/count_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	clkdiv_1/count_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	clkdiv_1/count_11_s0/CLK

MPW10

MPW Summary:

Slack:	2.911
Actual Width:	4.161
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk
Objects:	toggle_1/out_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.984	0.984	tINS	FF	clk_ibuf/O
7.489	1.505	tNET	FF	toggle_1/out_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.844	0.844	tINS	RR	clk_ibuf/O
11.651	0.806	tNET	RR	toggle_1/out_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
26	clk_d	-0.340	1.505
24	tc_Z	-0.340	1.005
4	count[23]	6.471	0.816
4	count_0[8]	0.885	1.487
3	count[13]	2.735	1.149
3	count[12]	1.158	1.296
3	count_0[0]	0.866	0.811
3	count_0[10]	-0.340	0.981
3	count_0[11]	0.395	1.313
3	count_0[9]	0.956	1.467

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C11	40.28%
R11C12	37.50%
R11C10	22.22%
R11C13	22.22%
R11C9	18.06%
R11C15	18.06%
R11C14	18.06%
R11C16	16.67%
R20C21	15.28%
R11C17	13.89%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command