Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Workspace\pwm_servo\src\clkdiv.v
C:\Gowin\Workspace\pwm_servo\src\pwm.v
C:\Gowin\Workspace\pwm_servo\src\test_pwm_servo.v
C:\Gowin\Workspace\pwm_servo\src\toggle.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.06Beta
Part Number GW1N-UV4LQ144C6/I5
Device GW1N-4B
Created Time Sat Jun 05 15:04:15 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module test_pwm_servo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.213s, Peak memory usage = 65.863MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 65.863MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 65.863MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 65.863MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 65.863MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 65.863MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 65.863MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 65.863MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 65.863MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 65.863MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 65.863MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.344s, Peak memory usage = 79.945MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 79.945MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 79.945MB
Total Time and Memory Usage CPU time = 0h 0m 0.606s, Elapsed time = 0h 0m 0.602s, Peak memory usage = 79.945MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 10
I/O Buf 10
    IBUF 9
    OBUF 1
Register 25
    DFF 1
    DFFE 5
    DFFR 19
LUT 37
    LUT2 1
    LUT3 5
    LUT4 31
ALU 21
    ALU 21
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 60(39 LUTs, 21 ALUs) / 4608 1%
Register 25 / 3756 1%
  --Register as Latch 0 / 3756 0%
  --Register as FF 25 / 3756 1%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
clk10khz Base 10.000 100.0 0.000 5.000 toggle_1/out_s0/Q

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 138.1(MHz) 5 TOP
2 clk10khz 100.0(MHz) 251.0(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.757
Data Arrival Time 8.188
Data Required Time 10.945
From clkdiv_1/count_2_s0
To toggle_1/out_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 17 clk_ibuf/O
1.345 0.363 tNET RR 1 clkdiv_1/count_2_s0/CLK
1.803 0.458 tC2Q RF 2 clkdiv_1/count_2_s0/Q
2.283 0.480 tNET FF 1 clkdiv_1/tc20khz_s1/I1
3.382 1.099 tINS FF 1 clkdiv_1/tc20khz_s1/F
3.862 0.480 tNET FF 1 clkdiv_1/tc20khz_s0/I0
4.894 1.032 tINS FF 2 clkdiv_1/tc20khz_s0/F
5.374 0.480 tNET FF 1 clkdiv_1/tc20khz_s/I2
6.196 0.822 tINS FF 11 clkdiv_1/tc20khz_s/F
6.676 0.480 tNET FF 1 toggle_1/n9_s0/I0
7.708 1.032 tINS FF 1 toggle_1/n9_s0/F
8.188 0.480 tNET FF 1 toggle_1/out_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 17 clk_ibuf/O
11.345 0.363 tNET RR 1 toggle_1/out_s0/CLK
10.945 -0.400 tSu 1 toggle_1/out_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.985, 58.231%; route: 2.400, 35.071%; tC2Q: 0.458, 6.698%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 3.163
Data Arrival Time 7.782
Data Required Time 10.945
From compare_3_s2
To compare_2_s2
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 17 clk_ibuf/O
1.345 0.363 tNET RR 1 compare_3_s2/CLK
1.803 0.458 tC2Q RF 6 compare_3_s2/Q
2.283 0.480 tNET FF 1 compare_4_s24/I1
3.382 1.099 tINS FF 2 compare_4_s24/F
3.862 0.480 tNET FF 1 n247_s33/I0
4.894 1.032 tINS FF 2 n247_s33/F
5.374 0.480 tNET FF 1 compare_4_s23/I3
6.000 0.626 tINS FF 2 compare_4_s23/F
6.480 0.480 tNET FF 1 n245_s32/I2
7.302 0.822 tINS FF 1 n245_s32/F
7.782 0.480 tNET FF 1 compare_2_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 17 clk_ibuf/O
11.345 0.363 tNET RR 1 compare_2_s2/CLK
10.945 -0.400 tSu 1 compare_2_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.579, 55.597%; route: 2.400, 37.283%; tC2Q: 0.458, 7.120%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 3.183
Data Arrival Time 8.118
Data Required Time 11.302
From compare_3_s2
To compare_0_s2
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 17 clk_ibuf/O
1.345 0.363 tNET RR 1 compare_3_s2/CLK
1.803 0.458 tC2Q RF 6 compare_3_s2/Q
2.283 0.480 tNET FF 1 n245_s37/I1
3.382 1.099 tINS FF 2 n245_s37/F
3.862 0.480 tNET FF 1 n245_s34/I0
4.894 1.032 tINS FF 2 n245_s34/F
5.374 0.480 tNET FF 1 n246_s32/I1
6.473 1.099 tINS FF 2 n246_s32/F
6.953 0.480 tNET FF 1 compare_4_s18/I2
7.755 0.802 tINS FR 5 compare_4_s18/F
8.118 0.363 tNET RR 1 compare_0_s2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 17 clk_ibuf/O
11.345 0.363 tNET RR 1 compare_0_s2/CLK
11.302 -0.043 tSu 1 compare_0_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.032, 59.527%; route: 2.283, 33.706%; tC2Q: 0.458, 6.767%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 3.183
Data Arrival Time 8.118
Data Required Time 11.302
From compare_3_s2
To compare_1_s2
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 17 clk_ibuf/O
1.345 0.363 tNET RR 1 compare_3_s2/CLK
1.803 0.458 tC2Q RF 6 compare_3_s2/Q
2.283 0.480 tNET FF 1 n245_s37/I1
3.382 1.099 tINS FF 2 n245_s37/F
3.862 0.480 tNET FF 1 n245_s34/I0
4.894 1.032 tINS FF 2 n245_s34/F
5.374 0.480 tNET FF 1 n246_s32/I1
6.473 1.099 tINS FF 2 n246_s32/F
6.953 0.480 tNET FF 1 compare_4_s18/I2
7.755 0.802 tINS FR 5 compare_4_s18/F
8.118 0.363 tNET RR 1 compare_1_s2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 17 clk_ibuf/O
11.345 0.363 tNET RR 1 compare_1_s2/CLK
11.302 -0.043 tSu 1 compare_1_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.032, 59.527%; route: 2.283, 33.706%; tC2Q: 0.458, 6.767%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 3.183
Data Arrival Time 8.118
Data Required Time 11.302
From compare_3_s2
To compare_2_s2
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 17 clk_ibuf/O
1.345 0.363 tNET RR 1 compare_3_s2/CLK
1.803 0.458 tC2Q RF 6 compare_3_s2/Q
2.283 0.480 tNET FF 1 n245_s37/I1
3.382 1.099 tINS FF 2 n245_s37/F
3.862 0.480 tNET FF 1 n245_s34/I0
4.894 1.032 tINS FF 2 n245_s34/F
5.374 0.480 tNET FF 1 n246_s32/I1
6.473 1.099 tINS FF 2 n246_s32/F
6.953 0.480 tNET FF 1 compare_4_s18/I2
7.755 0.802 tINS FR 5 compare_4_s18/F
8.118 0.363 tNET RR 1 compare_2_s2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.982 0.982 tINS RR 17 clk_ibuf/O
11.345 0.363 tNET RR 1 compare_2_s2/CLK
11.302 -0.043 tSu 1 compare_2_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.032, 59.527%; route: 2.283, 33.706%; tC2Q: 0.458, 6.767%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%